commit fb9ebbf236974beac31705eaeb9f50ab585af6ab
author Jakob Stoklund Olesen <stoklund@2pi.dk> Mon Oct 15 21:57:41 2012 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Mon Oct 15 21:57:41 2012 +0000
tree 7d01bb6c43ca1854b208c80f34b6158644eb78f9
parent e4f273908bd37df5f0f6b2c575dcb2af99f6b85b

Switch most getReservedRegs() clients to the MRI equivalent.

Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/PostRASchedulerList.cpp

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 32c02bf..d57bc73 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -490,7 +490,6 @@
   DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
 
   BitVector killedRegs(TRI->getNumRegs());
-  BitVector ReservedRegs = TRI->getReservedRegs(MF);
 
   StartBlockForKills(MBB);
 
@@ -531,7 +530,7 @@
       MachineOperand &MO = MI->getOperand(i);
       if (!MO.isReg() || !MO.isUse()) continue;
       unsigned Reg = MO.getReg();
-      if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
+      if ((Reg == 0) || MRI.isReserved(Reg)) continue;
 
       bool kill = false;
       if (!killedRegs.test(Reg)) {
@@ -566,7 +565,7 @@
       MachineOperand &MO = MI->getOperand(i);
       if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
       unsigned Reg = MO.getReg();
-      if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
+      if ((Reg == 0) || MRI.isReserved(Reg)) continue;
 
       LiveRegs.set(Reg);