Sparc backend:
Rename FLUSH to FLUSHW.
Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index f78d5fa..2767862 100644
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -721,7 +721,7 @@
case SPISD::CALL: return "SPISD::CALL";
case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
- case SPISD::FLUSH: return "SPISD::FLUSH";
+ case SPISD::FLUSHW: return "SPISD::FLUSHW";
}
}
@@ -969,9 +969,9 @@
}
-static SDValue getFLUSH(SDValue Op, SelectionDAG &DAG) {
+static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- SDValue Chain = DAG.getNode(SPISD::FLUSH,
+ SDValue Chain = DAG.getNode(SPISD::FLUSHW,
dl, MVT::Other, DAG.getEntryNode());
return Chain;
}
@@ -987,19 +987,19 @@
uint64_t depth = Op.getConstantOperandVal(0);
SDValue FrameAddr;
- if (depth == 0)
+ if (depth == 0)
FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
else {
// flush first to make sure the windowed registers' values are in stack
- SDValue Chain = getFLUSH(Op, DAG);
+ SDValue Chain = getFLUSHW(Op, DAG);
FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
-
+
for (uint64_t i = 0; i != depth; ++i) {
- SDValue Ptr = DAG.getNode(ISD::ADD,
+ SDValue Ptr = DAG.getNode(ISD::ADD,
dl, MVT::i32,
FrameAddr, DAG.getIntPtrConstant(56));
- FrameAddr = DAG.getLoad(MVT::i32, dl,
- Chain,
+ FrameAddr = DAG.getLoad(MVT::i32, dl,
+ Chain,
Ptr,
MachinePointerInfo(), false, false, 0);
}
@@ -1018,20 +1018,20 @@
uint64_t depth = Op.getConstantOperandVal(0);
SDValue RetAddr;
- if (depth == 0)
+ if (depth == 0)
RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
else {
// flush first to make sure the windowed registers' values are in stack
- SDValue Chain = getFLUSH(Op, DAG);
+ SDValue Chain = getFLUSHW(Op, DAG);
RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
-
+
for (uint64_t i = 0; i != depth; ++i) {
- SDValue Ptr = DAG.getNode(ISD::ADD,
+ SDValue Ptr = DAG.getNode(ISD::ADD,
dl, MVT::i32,
- RetAddr,
+ RetAddr,
DAG.getIntPtrConstant((i == depth-1)?60:56));
- RetAddr = DAG.getLoad(MVT::i32, dl,
- Chain,
+ RetAddr = DAG.getLoad(MVT::i32, dl,
+ Chain,
Ptr,
MachinePointerInfo(), false, false, 0);
}
diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h
index 8b2be7a..849e401 100644
--- a/lib/Target/Sparc/SparcISelLowering.h
+++ b/lib/Target/Sparc/SparcISelLowering.h
@@ -37,7 +37,7 @@
CALL, // A call instruction.
RET_FLAG, // Return with a flag operand.
GLOBAL_BASE_REG, // Global base reg for PIC
- FLUSH // FLUSH registers to stack
+ FLUSHW // FLUSH register windows to stack
};
}
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 4f7b7c5..ffeb8b5 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -127,7 +127,7 @@
def retflag : SDNode<"SPISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
-def flush : SDNode<"SPISD::FLUSH", SDTNone,
+def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
[SDNPHasChain]>;
def getPCX : Operand<i32> {
@@ -221,11 +221,16 @@
[(callseq_end timm:$amt1, timm:$amt2)]>;
}
-let hasSideEffects = 1, mayStore = 1 in
- let rs2 = 0 in
- def FLUSH : F3_1<0b10, 0b101011, (outs), (ins),
- "flushw",
- [(flush)]>;
+let hasSideEffects = 1, mayStore = 1 in {
+ let rd = 0, rs1 = 0, rs2 = 0 in
+ def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
+ "flushw",
+ [(flushw)]>, Requires<[HasV9]>;
+ let rd = 0, rs1 = 1, simm13 = 3 in
+ def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
+ "ta 3",
+ [(flushw)]>;
+}
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.