movnt* and maskmovdqu intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27587 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td
index f44526d..7944099 100644
--- a/lib/Target/X86/X86InstrMMX.td
+++ b/lib/Target/X86/X86InstrMMX.td
@@ -13,6 +13,13 @@
//
//===----------------------------------------------------------------------===//
+// Instruction templates
+// MMXi8 - MMX instructions with ImmT == Imm8 and TB prefix.
+class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+ : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasMMX]> {
+ let Pattern = pattern;
+}
+
// Some 'special' instructions
def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
"#IMPLICIT_DEF $dst",
@@ -50,3 +57,21 @@
def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasMMX]>;
+
+// Shuffle and unpack instructions
+def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
+ (ops VR64:$dst, VR64:$src1, i8imm:$src2),
+ "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
+def PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
+ (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
+ "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
+
+// Misc.
+def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+ "movntq {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasMMX]>;
+
+def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
+ "maskmovq {$mask, $src|$src, $mask}", []>, TB,
+ Requires<[HasMMX]>;
+