commit fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaa
author Jiangning Liu <jiangning.liu@arm.com> Thu Aug 02 08:29:50 2012 +0000
committer Jiangning Liu <jiangning.liu@arm.com> Thu Aug 02 08:29:50 2012 +0000
tree 5d0ce3d875c3c64330d094500418b1470087d2ad
parent c1b7ca5ba28ded2d83ae534c8e072c2538d43295

Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 6f36dcc..e47bf66 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -3151,9 +3151,14 @@
 
 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
                            uint64_t Address, const void *Decoder) {
-  int imm = Val & 0xFF;
-  if (!(Val & 0x100)) imm *= -1;
-  Inst.addOperand(MCOperand::CreateImm(imm << 2));
+  if (Val == 0)
+    Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
+  else {
+    int imm = Val & 0xFF;
+
+    if (!(Val & 0x100)) imm *= -1;
+    Inst.addOperand(MCOperand::CreateImm(imm << 2));
+  }
 
   return MCDisassembler::Success;
 }