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gerrit-public.fairphone.software / platform / external / llvm / 01817c39a9d7ff864d0b5de4941eec93d2f9e3a8 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: b1f7fd6fe4a592695c9aecdbb6ae013d11424468 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]16#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]17#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]18#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]22#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]39 ARMDisassembler(const MCSubtargetInfo &STI) :
40 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]41 }
42
43 ~ARMDisassembler() {
44 }
45
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
48 uint64_t &size,
49 const MemoryObject &region,
50 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]51 raw_ostream &vStream,
52 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]53
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62 /// Constructor - Initializes the disassembler.
63 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]64 ThumbDisassembler(const MCSubtargetInfo &STI) :
65 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]66 }
67
68 ~ThumbDisassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
74 const MemoryObject &region,
75 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]78
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
81private:
82 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]83 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]84 void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]88static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]89 switch (In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
92 return true;
93 case MCDisassembler::SoftFail:
94 Out = In;
95 return true;
96 case MCDisassembler::Fail:
97 Out = In;
98 return false;
99 }
100 return false;
101}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]102
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]103
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]120 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]122 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]129
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]148 unsigned Insn,
149 uint64_t Address,
150 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]154 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 unsigned Insn,
162 uint64_t Adddress,
163 const void *Decoder);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]182static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]184static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]186static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]188static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]190static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]192static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]194static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]196static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]198static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]200static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]202static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]204static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]210static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]212static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]214static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]216static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]218static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]224static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]226static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]228static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]230static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]232static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]234static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]236static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]238static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]240static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]242static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]244static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]246static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]252
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]253static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]255static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]257static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]259static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]261static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]277static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
278 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]279static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]287static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]293static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
294 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]295static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]296 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]297static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]299static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]301static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]303static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]304 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]305static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
306 uint64_t Address, const void *Decoder);
307static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]309static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
310 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]311static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]313static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
315
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]316
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]317
318#include "ARMGenDisassemblerTables.inc"
319#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]320#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]321
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]322static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
323 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]324}
325
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]326static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
327 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]328}
329
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]330EDInstInfo *ARMDisassembler::getEDInfo() const {
331 return instInfoARM;
332}
333
334EDInstInfo *ThumbDisassembler::getEDInfo() const {
335 return instInfoARM;
336}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]338DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]339 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]340 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]341 raw_ostream &os,
342 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]343 CommentStream = &cs;
344
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 uint8_t bytes[4];
346
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
348 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
349
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]350 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]351 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
352 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]353 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]354 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355
356 // Encoded as a small-endian 32-bit word in the stream.
357 uint32_t insn = (bytes[3] << 24) |
358 (bytes[2] << 16) |
359 (bytes[1] << 8) |
360 (bytes[0] << 0);
361
362 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]364 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]366 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 }
368
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 // VFP and NEON instructions, similarly, are shared between ARM
370 // and Thumb modes.
371 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]372 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]375 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 }
377
378 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]379 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]380 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]381 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382 // Add a fake predicate operand, because we share these instruction
383 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]384 if (!DecodePredicateOperand(MI, 0xE, Address, this))
385 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]386 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]387 }
388
389 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]390 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]391 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]392 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]393 // Add a fake predicate operand, because we share these instruction
394 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]395 if (!DecodePredicateOperand(MI, 0xE, Address, this))
396 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]397 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]398 }
399
400 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]401 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]402 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]403 Size = 4;
404 // Add a fake predicate operand, because we share these instruction
405 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]406 if (!DecodePredicateOperand(MI, 0xE, Address, this))
407 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]408 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]409 }
410
411 MI.clear();
412
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]413 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]414 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415}
416
417namespace llvm {
418extern MCInstrDesc ARMInsts[];
419}
420
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]421/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
422/// immediate Value in the MCInst. The immediate Value has had any PC
423/// adjustment made by the caller. If the instruction is a branch instruction
424/// then isBranch is true, else false. If the getOpInfo() function was set as
425/// part of the setupForSymbolicDisassembly() call then that function is called
426/// to get any symbolic information at the Address for this instruction. If
427/// that returns non-zero then the symbolic information it returns is used to
428/// create an MCExpr and that is added as an operand to the MCInst. If
429/// getOpInfo() returns zero and isBranch is true then a symbol look up for
430/// Value is done and if a symbol is found an MCExpr is created with that, else
431/// an MCExpr with Value is created. This function returns true if it adds an
432/// operand to the MCInst and false otherwise.
433static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
434 bool isBranch, uint64_t InstSize,
435 MCInst &MI, const void *Decoder) {
436 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
437 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
438 if (!getOpInfo)
439 return false;
440
441 struct LLVMOpInfo1 SymbolicOp;
442 SymbolicOp.Value = Value;
443 void *DisInfo = Dis->getDisInfoBlock();
444 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
445 if (isBranch) {
446 LLVMSymbolLookupCallback SymbolLookUp =
447 Dis->getLLVMSymbolLookupCallback();
448 if (SymbolLookUp) {
449 uint64_t ReferenceType;
450 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
451 const char *ReferenceName;
452 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
453 &ReferenceName);
454 if (Name) {
455 SymbolicOp.AddSymbol.Name = Name;
456 SymbolicOp.AddSymbol.Present = true;
457 SymbolicOp.Value = 0;
458 }
459 else {
460 SymbolicOp.Value = Value;
461 }
462 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
463 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
464 }
465 else {
466 return false;
467 }
468 }
469 else {
470 return false;
471 }
472 }
473
474 MCContext *Ctx = Dis->getMCContext();
475 const MCExpr *Add = NULL;
476 if (SymbolicOp.AddSymbol.Present) {
477 if (SymbolicOp.AddSymbol.Name) {
478 StringRef Name(SymbolicOp.AddSymbol.Name);
479 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
480 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
481 } else {
482 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
483 }
484 }
485
486 const MCExpr *Sub = NULL;
487 if (SymbolicOp.SubtractSymbol.Present) {
488 if (SymbolicOp.SubtractSymbol.Name) {
489 StringRef Name(SymbolicOp.SubtractSymbol.Name);
490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
491 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
492 } else {
493 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
494 }
495 }
496
497 const MCExpr *Off = NULL;
498 if (SymbolicOp.Value != 0)
499 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
500
501 const MCExpr *Expr;
502 if (Sub) {
503 const MCExpr *LHS;
504 if (Add)
505 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
506 else
507 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
508 if (Off != 0)
509 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
510 else
511 Expr = LHS;
512 } else if (Add) {
513 if (Off != 0)
514 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
515 else
516 Expr = Add;
517 } else {
518 if (Off != 0)
519 Expr = Off;
520 else
521 Expr = MCConstantExpr::Create(0, *Ctx);
522 }
523
524 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
526 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
529 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame^]530 else
Richard Trieu8223e452011-10-14 20:50:26 +0000[diff] [blame]531 assert(0 && "bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]532
533 return true;
534}
535
536/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
537/// referenced by a load instruction with the base register that is the Pc.
538/// These can often be values in a literal pool near the Address of the
539/// instruction. The Address of the instruction and its immediate Value are
540/// used as a possible literal pool entry. The SymbolLookUp call back will
541/// return the name of a symbol referenced by the the literal pool's entry if
542/// the referenced address is that of a symbol. Or it will return a pointer to
543/// a literal 'C' string if the referenced address of the literal pool's entry
544/// is an address into a section with 'C' string literals.
545static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
546 const void *Decoder) {
547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
548 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
549 if (SymbolLookUp) {
550 void *DisInfo = Dis->getDisInfoBlock();
551 uint64_t ReferenceType;
552 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
553 const char *ReferenceName;
554 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
555 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
556 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
557 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
558 }
559}
560
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]561// Thumb1 instructions don't have explicit S bits. Rather, they
562// implicitly set CPSR. Since it's not represented in the encoding, the
563// auto-generated decoder won't inject the CPSR operand. We need to fix
564// that as a post-pass.
565static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]568 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]569 for (unsigned i = 0; i < NumOps; ++i, ++I) {
570 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]572 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
574 return;
575 }
576 }
577
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579}
580
581// Most Thumb instructions don't have explicit predicates in the
582// encoding, but rather get their predicates from IT context. We need
583// to fix up the predicate operands using this context information as a
584// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]585MCDisassembler::DecodeStatus
586ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]587 MCDisassembler::DecodeStatus S = Success;
588
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]589 // A few instructions actually have predicates encoded in them. Don't
590 // try to overwrite it if we're seeing one of those.
591 switch (MI.getOpcode()) {
592 case ARM::tBcc:
593 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]594 case ARM::tCBZ:
595 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]596 case ARM::tCPS:
597 case ARM::t2CPS3p:
598 case ARM::t2CPS2p:
599 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]600 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]601 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]602 // Some instructions (mostly conditional branches) are not
603 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]604 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]605 S = SoftFail;
606 else
607 return Success;
608 break;
609 case ARM::tB:
610 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]611 case ARM::t2TBB:
612 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]613 // Some instructions (mostly unconditional branches) can
614 // only appears at the end of, or outside of, an IT.
615 if (ITBlock.size() > 1)
616 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]617 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]618 default:
619 break;
620 }
621
622 // If we're in an IT block, base the predicate on that. Otherwise,
623 // assume a predicate of AL.
624 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]625 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]626 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]627 if (CC == 0xF)
628 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]629 ITBlock.pop_back();
630 } else
631 CC = ARMCC::AL;
632
633 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]634 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]635 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]636 for (unsigned i = 0; i < NumOps; ++i, ++I) {
637 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]638 if (OpInfo[i].isPredicate()) {
639 I = MI.insert(I, MCOperand::CreateImm(CC));
640 ++I;
641 if (CC == ARMCC::AL)
642 MI.insert(I, MCOperand::CreateReg(0));
643 else
644 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]645 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]646 }
647 }
648
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]649 I = MI.insert(I, MCOperand::CreateImm(CC));
650 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]651 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]652 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]653 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]655
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]656 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]657}
658
659// Thumb VFP instructions are a special case. Because we share their
660// encodings between ARM and Thumb modes, and they are predicable in ARM
661// mode, the auto-generated decoder will give them an (incorrect)
662// predicate operand. We need to rewrite these operands based on the IT
663// context as a post-pass.
664void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
665 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]666 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]667 CC = ITBlock.back();
668 ITBlock.pop_back();
669 } else
670 CC = ARMCC::AL;
671
672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
673 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
675 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]676 if (OpInfo[i].isPredicate() ) {
677 I->setImm(CC);
678 ++I;
679 if (CC == ARMCC::AL)
680 I->setReg(0);
681 else
682 I->setReg(ARM::CPSR);
683 return;
684 }
685 }
686}
687
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]688DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]689 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]690 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]691 raw_ostream &os,
692 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]693 CommentStream = &cs;
694
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]695 uint8_t bytes[4];
696
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]697 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
698 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
699
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]700 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]701 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
702 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]703 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]704 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]705
706 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]707 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]708 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]709 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]710 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]711 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]712 }
713
714 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]715 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]716 if (result) {
717 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]718 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]719 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]720 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]721 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]722 }
723
724 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]725 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]726 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]727 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]728
729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
730 // the Thumb predicate.
731 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
732 result = MCDisassembler::SoftFail;
733
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]734 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]735
736 // If we find an IT instruction, we need to parse its condition
737 // code and mask operands so that we can apply them correctly
738 // to the subsequent instructions.
739 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]740
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]741 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]742 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]743 unsigned Mask = MI.getOperand(1).getImm();
744 unsigned CondBit0 = Mask >> 4 & 1;
745 unsigned NumTZ = CountTrailingZeros_32(Mask);
746 assert(NumTZ <= 3 && "Invalid IT mask!");
747 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
748 bool T = ((Mask >> Pos) & 1) == CondBit0;
749 if (T)
750 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]751 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]752 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]754
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]755 ITBlock.push_back(firstcond);
756 }
757
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]758 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]759 }
760
761 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]762 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
763 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]764 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]765 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]766
767 uint32_t insn32 = (bytes[3] << 8) |
768 (bytes[2] << 0) |
769 (bytes[1] << 24) |
770 (bytes[0] << 16);
771 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]772 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]773 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]774 Size = 4;
775 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]776 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]778 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]779 }
780
781 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]782 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]783 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]784 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]785 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]786 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]787 }
788
789 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]790 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]791 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]792 Size = 4;
793 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]794 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]795 }
796
797 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]798 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]799 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]800 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]801 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]802 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]803 }
804
805 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
806 MI.clear();
807 uint32_t NEONLdStInsn = insn32;
808 NEONLdStInsn &= 0xF0FFFFFF;
809 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]810 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]811 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]812 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]813 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]814 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]815 }
816 }
817
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]818 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]819 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]820 uint32_t NEONDataInsn = insn32;
821 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
822 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
823 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]824 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]825 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]826 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]827 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]828 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]829 }
830 }
831
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]832 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]833 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]834}
835
836
837extern "C" void LLVMInitializeARMDisassembler() {
838 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
839 createARMDisassembler);
840 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
841 createThumbDisassembler);
842}
843
844static const unsigned GPRDecoderTable[] = {
845 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
846 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
847 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
848 ARM::R12, ARM::SP, ARM::LR, ARM::PC
849};
850
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]851static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]852 uint64_t Address, const void *Decoder) {
853 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]854 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]855
856 unsigned Register = GPRDecoderTable[RegNo];
857 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]858 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]859}
860
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]861static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]862DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
863 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]864 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]865 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
866}
867
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]868static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]869 uint64_t Address, const void *Decoder) {
870 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]871 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]872 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
873}
874
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]875static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]876 uint64_t Address, const void *Decoder) {
877 unsigned Register = 0;
878 switch (RegNo) {
879 case 0:
880 Register = ARM::R0;
881 break;
882 case 1:
883 Register = ARM::R1;
884 break;
885 case 2:
886 Register = ARM::R2;
887 break;
888 case 3:
889 Register = ARM::R3;
890 break;
891 case 9:
892 Register = ARM::R9;
893 break;
894 case 12:
895 Register = ARM::R12;
896 break;
897 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]898 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]899 }
900
901 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]902 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]903}
904
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]905static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]906 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]907 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
909}
910
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]911static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]912 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
913 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
914 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
915 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
916 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
917 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
918 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
919 ARM::S28, ARM::S29, ARM::S30, ARM::S31
920};
921
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]922static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]923 uint64_t Address, const void *Decoder) {
924 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]925 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]926
927 unsigned Register = SPRDecoderTable[RegNo];
928 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]929 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]930}
931
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]932static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]933 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
934 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
935 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
936 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
937 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
938 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
939 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
940 ARM::D28, ARM::D29, ARM::D30, ARM::D31
941};
942
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]943static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]944 uint64_t Address, const void *Decoder) {
945 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]946 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]947
948 unsigned Register = DPRDecoderTable[RegNo];
949 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]950 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]951}
952
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]953static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]954 uint64_t Address, const void *Decoder) {
955 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]956 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]957 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
958}
959
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]960static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]961DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
962 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]964 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]965 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
966}
967
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]968static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]969 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
970 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
971 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
972 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
973};
974
975
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]976static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]977 uint64_t Address, const void *Decoder) {
978 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]979 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]980 RegNo >>= 1;
981
982 unsigned Register = QPRDecoderTable[RegNo];
983 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]984 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]985}
986
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]987static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]988 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]989 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]990 // AL predicate is not allowed on Thumb1 branches.
991 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]992 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]993 Inst.addOperand(MCOperand::CreateImm(Val));
994 if (Val == ARMCC::AL) {
995 Inst.addOperand(MCOperand::CreateReg(0));
996 } else
997 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]998 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999}
1000
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1001static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002 uint64_t Address, const void *Decoder) {
1003 if (Val)
1004 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1005 else
1006 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1007 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1008}
1009
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1010static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1011 uint64_t Address, const void *Decoder) {
1012 uint32_t imm = Val & 0xFF;
1013 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1014 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1015 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1016 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1017}
1018
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1019static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1020 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1021 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1022
1023 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1024 unsigned type = fieldFromInstruction32(Val, 5, 2);
1025 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1026
1027 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1029 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1030
1031 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1032 switch (type) {
1033 case 0:
1034 Shift = ARM_AM::lsl;
1035 break;
1036 case 1:
1037 Shift = ARM_AM::lsr;
1038 break;
1039 case 2:
1040 Shift = ARM_AM::asr;
1041 break;
1042 case 3:
1043 Shift = ARM_AM::ror;
1044 break;
1045 }
1046
1047 if (Shift == ARM_AM::ror && imm == 0)
1048 Shift = ARM_AM::rrx;
1049
1050 unsigned Op = Shift | (imm << 3);
1051 Inst.addOperand(MCOperand::CreateImm(Op));
1052
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1053 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1054}
1055
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1056static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1057 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1058 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1059
1060 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1061 unsigned type = fieldFromInstruction32(Val, 5, 2);
1062 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1063
1064 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1065 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1066 return MCDisassembler::Fail;
1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1068 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1069
1070 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1071 switch (type) {
1072 case 0:
1073 Shift = ARM_AM::lsl;
1074 break;
1075 case 1:
1076 Shift = ARM_AM::lsr;
1077 break;
1078 case 2:
1079 Shift = ARM_AM::asr;
1080 break;
1081 case 3:
1082 Shift = ARM_AM::ror;
1083 break;
1084 }
1085
1086 Inst.addOperand(MCOperand::CreateImm(Shift));
1087
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1088 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1089}
1090
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1091static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1092 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1093 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1094
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1095 bool writebackLoad = false;
1096 unsigned writebackReg = 0;
1097 switch (Inst.getOpcode()) {
1098 default:
1099 break;
1100 case ARM::LDMIA_UPD:
1101 case ARM::LDMDB_UPD:
1102 case ARM::LDMIB_UPD:
1103 case ARM::LDMDA_UPD:
1104 case ARM::t2LDMIA_UPD:
1105 case ARM::t2LDMDB_UPD:
1106 writebackLoad = true;
1107 writebackReg = Inst.getOperand(0).getReg();
1108 break;
1109 }
1110
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1111 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1112 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1113 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1114 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1115 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1116 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1117 // Writeback not allowed if Rn is in the target list.
1118 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1119 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1120 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1121 }
1122
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1123 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1124}
1125
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1126static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1127 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1128 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1129
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1130 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1131 unsigned regs = Val & 0xFF;
1132
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1133 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1134 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1135 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1136 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1137 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1138 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1139
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1140 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1141}
1142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1143static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1144 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1145 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1146
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1147 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1148 unsigned regs = (Val & 0xFF) / 2;
1149
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1151 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1152 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1153 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1154 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1155 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1156
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1157 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1158}
1159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1160static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1161 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1162 // This operand encodes a mask of contiguous zeros between a specified MSB
1163 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1164 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1165 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1166 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1167 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1168 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1169
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1170 DecodeStatus S = MCDisassembler::Success;
1171 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1172
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1173 uint32_t msb_mask = 0xFFFFFFFF;
1174 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1175 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1176
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1177 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1178 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1179}
1180
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1181static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1182 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1183 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1184
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1185 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1186 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1187 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1188 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1189 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1190 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1191
1192 switch (Inst.getOpcode()) {
1193 case ARM::LDC_OFFSET:
1194 case ARM::LDC_PRE:
1195 case ARM::LDC_POST:
1196 case ARM::LDC_OPTION:
1197 case ARM::LDCL_OFFSET:
1198 case ARM::LDCL_PRE:
1199 case ARM::LDCL_POST:
1200 case ARM::LDCL_OPTION:
1201 case ARM::STC_OFFSET:
1202 case ARM::STC_PRE:
1203 case ARM::STC_POST:
1204 case ARM::STC_OPTION:
1205 case ARM::STCL_OFFSET:
1206 case ARM::STCL_PRE:
1207 case ARM::STCL_POST:
1208 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1209 case ARM::t2LDC_OFFSET:
1210 case ARM::t2LDC_PRE:
1211 case ARM::t2LDC_POST:
1212 case ARM::t2LDC_OPTION:
1213 case ARM::t2LDCL_OFFSET:
1214 case ARM::t2LDCL_PRE:
1215 case ARM::t2LDCL_POST:
1216 case ARM::t2LDCL_OPTION:
1217 case ARM::t2STC_OFFSET:
1218 case ARM::t2STC_PRE:
1219 case ARM::t2STC_POST:
1220 case ARM::t2STC_OPTION:
1221 case ARM::t2STCL_OFFSET:
1222 case ARM::t2STCL_PRE:
1223 case ARM::t2STCL_POST:
1224 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1225 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1226 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1227 break;
1228 default:
1229 break;
1230 }
1231
1232 Inst.addOperand(MCOperand::CreateImm(coproc));
1233 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1235 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1236
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1237 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1238 case ARM::t2LDC2_OFFSET:
1239 case ARM::t2LDC2L_OFFSET:
1240 case ARM::t2LDC2_PRE:
1241 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1242 case ARM::t2STC2_OFFSET:
1243 case ARM::t2STC2L_OFFSET:
1244 case ARM::t2STC2_PRE:
1245 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1246 case ARM::LDC2_OFFSET:
1247 case ARM::LDC2L_OFFSET:
1248 case ARM::LDC2_PRE:
1249 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1250 case ARM::STC2_OFFSET:
1251 case ARM::STC2L_OFFSET:
1252 case ARM::STC2_PRE:
1253 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1254 case ARM::t2LDC_OFFSET:
1255 case ARM::t2LDCL_OFFSET:
1256 case ARM::t2LDC_PRE:
1257 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1258 case ARM::t2STC_OFFSET:
1259 case ARM::t2STCL_OFFSET:
1260 case ARM::t2STC_PRE:
1261 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1262 case ARM::LDC_OFFSET:
1263 case ARM::LDCL_OFFSET:
1264 case ARM::LDC_PRE:
1265 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1266 case ARM::STC_OFFSET:
1267 case ARM::STCL_OFFSET:
1268 case ARM::STC_PRE:
1269 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1270 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1271 Inst.addOperand(MCOperand::CreateImm(imm));
1272 break;
1273 case ARM::t2LDC2_POST:
1274 case ARM::t2LDC2L_POST:
1275 case ARM::t2STC2_POST:
1276 case ARM::t2STC2L_POST:
1277 case ARM::LDC2_POST:
1278 case ARM::LDC2L_POST:
1279 case ARM::STC2_POST:
1280 case ARM::STC2L_POST:
1281 case ARM::t2LDC_POST:
1282 case ARM::t2LDCL_POST:
1283 case ARM::t2STC_POST:
1284 case ARM::t2STCL_POST:
1285 case ARM::LDC_POST:
1286 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1287 case ARM::STC_POST:
1288 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1289 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1290 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1291 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1292 // The 'option' variant doesn't encode 'U' in the immediate since
1293 // the immediate is unsigned [0,255].
1294 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1295 break;
1296 }
1297
1298 switch (Inst.getOpcode()) {
1299 case ARM::LDC_OFFSET:
1300 case ARM::LDC_PRE:
1301 case ARM::LDC_POST:
1302 case ARM::LDC_OPTION:
1303 case ARM::LDCL_OFFSET:
1304 case ARM::LDCL_PRE:
1305 case ARM::LDCL_POST:
1306 case ARM::LDCL_OPTION:
1307 case ARM::STC_OFFSET:
1308 case ARM::STC_PRE:
1309 case ARM::STC_POST:
1310 case ARM::STC_OPTION:
1311 case ARM::STCL_OFFSET:
1312 case ARM::STCL_PRE:
1313 case ARM::STCL_POST:
1314 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1315 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1316 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1317 break;
1318 default:
1319 break;
1320 }
1321
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1322 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1323}
1324
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1325static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1326DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1327 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1328 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1329
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1330 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1331 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1332 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1333 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1334 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1335 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1336 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1337 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1338
1339 // On stores, the writeback operand precedes Rt.
1340 switch (Inst.getOpcode()) {
1341 case ARM::STR_POST_IMM:
1342 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1343 case ARM::STRB_POST_IMM:
1344 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1345 case ARM::STRT_POST_REG:
1346 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1347 case ARM::STRBT_POST_REG:
1348 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1350 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1351 break;
1352 default:
1353 break;
1354 }
1355
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1357 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1358
1359 // On loads, the writeback operand comes after Rt.
1360 switch (Inst.getOpcode()) {
1361 case ARM::LDR_POST_IMM:
1362 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1363 case ARM::LDRB_POST_IMM:
1364 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1365 case ARM::LDRBT_POST_REG:
1366 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1367 case ARM::LDRT_POST_REG:
1368 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1370 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1371 break;
1372 default:
1373 break;
1374 }
1375
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1377 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1378
1379 ARM_AM::AddrOpc Op = ARM_AM::add;
1380 if (!fieldFromInstruction32(Insn, 23, 1))
1381 Op = ARM_AM::sub;
1382
1383 bool writeback = (P == 0) || (W == 1);
1384 unsigned idx_mode = 0;
1385 if (P && writeback)
1386 idx_mode = ARMII::IndexModePre;
1387 else if (!P && writeback)
1388 idx_mode = ARMII::IndexModePost;
1389
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1390 if (writeback && (Rn == 15 || Rn == Rt))
1391 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1392
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1393 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1394 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1395 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1396 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1397 switch( fieldFromInstruction32(Insn, 5, 2)) {
1398 case 0:
1399 Opc = ARM_AM::lsl;
1400 break;
1401 case 1:
1402 Opc = ARM_AM::lsr;
1403 break;
1404 case 2:
1405 Opc = ARM_AM::asr;
1406 break;
1407 case 3:
1408 Opc = ARM_AM::ror;
1409 break;
1410 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1411 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1412 }
1413 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1414 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1415
1416 Inst.addOperand(MCOperand::CreateImm(imm));
1417 } else {
1418 Inst.addOperand(MCOperand::CreateReg(0));
1419 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1420 Inst.addOperand(MCOperand::CreateImm(tmp));
1421 }
1422
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1423 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1424 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1425
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1426 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1427}
1428
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1429static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1430 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1431 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1432
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1433 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1434 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1435 unsigned type = fieldFromInstruction32(Val, 5, 2);
1436 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1437 unsigned U = fieldFromInstruction32(Val, 12, 1);
1438
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1439 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1440 switch (type) {
1441 case 0:
1442 ShOp = ARM_AM::lsl;
1443 break;
1444 case 1:
1445 ShOp = ARM_AM::lsr;
1446 break;
1447 case 2:
1448 ShOp = ARM_AM::asr;
1449 break;
1450 case 3:
1451 ShOp = ARM_AM::ror;
1452 break;
1453 }
1454
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1456 return MCDisassembler::Fail;
1457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1458 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1459 unsigned shift;
1460 if (U)
1461 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1462 else
1463 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1464 Inst.addOperand(MCOperand::CreateImm(shift));
1465
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1466 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1467}
1468
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1469static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1470DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1471 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1472 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1473
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1474 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1475 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1476 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1477 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1478 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1479 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1480 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1481 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1482 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1483
1484 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1485
1486 // For {LD,ST}RD, Rt must be even, else undefined.
1487 switch (Inst.getOpcode()) {
1488 case ARM::STRD:
1489 case ARM::STRD_PRE:
1490 case ARM::STRD_POST:
1491 case ARM::LDRD:
1492 case ARM::LDRD_PRE:
1493 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1494 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1495 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1496 default:
1497 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1498 }
1499
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1500 if (writeback) { // Writeback
1501 if (P)
1502 U |= ARMII::IndexModePre << 9;
1503 else
1504 U |= ARMII::IndexModePost << 9;
1505
1506 // On stores, the writeback operand precedes Rt.
1507 switch (Inst.getOpcode()) {
1508 case ARM::STRD:
1509 case ARM::STRD_PRE:
1510 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1511 case ARM::STRH:
1512 case ARM::STRH_PRE:
1513 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1515 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1516 break;
1517 default:
1518 break;
1519 }
1520 }
1521
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1523 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1524 switch (Inst.getOpcode()) {
1525 case ARM::STRD:
1526 case ARM::STRD_PRE:
1527 case ARM::STRD_POST:
1528 case ARM::LDRD:
1529 case ARM::LDRD_PRE:
1530 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1532 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1533 break;
1534 default:
1535 break;
1536 }
1537
1538 if (writeback) {
1539 // On loads, the writeback operand comes after Rt.
1540 switch (Inst.getOpcode()) {
1541 case ARM::LDRD:
1542 case ARM::LDRD_PRE:
1543 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1544 case ARM::LDRH:
1545 case ARM::LDRH_PRE:
1546 case ARM::LDRH_POST:
1547 case ARM::LDRSH:
1548 case ARM::LDRSH_PRE:
1549 case ARM::LDRSH_POST:
1550 case ARM::LDRSB:
1551 case ARM::LDRSB_PRE:
1552 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1553 case ARM::LDRHTr:
1554 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1556 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1557 break;
1558 default:
1559 break;
1560 }
1561 }
1562
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1564 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1565
1566 if (type) {
1567 Inst.addOperand(MCOperand::CreateReg(0));
1568 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1569 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1571 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1572 Inst.addOperand(MCOperand::CreateImm(U));
1573 }
1574
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1575 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1576 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1577
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1578 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1579}
1580
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1581static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1582 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1583 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1584
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1585 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1586 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1587
1588 switch (mode) {
1589 case 0:
1590 mode = ARM_AM::da;
1591 break;
1592 case 1:
1593 mode = ARM_AM::ia;
1594 break;
1595 case 2:
1596 mode = ARM_AM::db;
1597 break;
1598 case 3:
1599 mode = ARM_AM::ib;
1600 break;
1601 }
1602
1603 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1605 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1606
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1607 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1608}
1609
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1610static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1611 unsigned Insn,
1612 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1613 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1614
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1615 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1616 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1617 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1618
1619 if (pred == 0xF) {
1620 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1621 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1622 Inst.setOpcode(ARM::RFEDA);
1623 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1624 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1625 Inst.setOpcode(ARM::RFEDA_UPD);
1626 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1627 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1628 Inst.setOpcode(ARM::RFEDB);
1629 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1630 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1631 Inst.setOpcode(ARM::RFEDB_UPD);
1632 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1633 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1634 Inst.setOpcode(ARM::RFEIA);
1635 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1636 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 Inst.setOpcode(ARM::RFEIA_UPD);
1638 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1639 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1640 Inst.setOpcode(ARM::RFEIB);
1641 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1642 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1643 Inst.setOpcode(ARM::RFEIB_UPD);
1644 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1645 case ARM::STMDA:
1646 Inst.setOpcode(ARM::SRSDA);
1647 break;
1648 case ARM::STMDA_UPD:
1649 Inst.setOpcode(ARM::SRSDA_UPD);
1650 break;
1651 case ARM::STMDB:
1652 Inst.setOpcode(ARM::SRSDB);
1653 break;
1654 case ARM::STMDB_UPD:
1655 Inst.setOpcode(ARM::SRSDB_UPD);
1656 break;
1657 case ARM::STMIA:
1658 Inst.setOpcode(ARM::SRSIA);
1659 break;
1660 case ARM::STMIA_UPD:
1661 Inst.setOpcode(ARM::SRSIA_UPD);
1662 break;
1663 case ARM::STMIB:
1664 Inst.setOpcode(ARM::SRSIB);
1665 break;
1666 case ARM::STMIB_UPD:
1667 Inst.setOpcode(ARM::SRSIB_UPD);
1668 break;
1669 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1670 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1671 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1672
1673 // For stores (which become SRS's, the only operand is the mode.
1674 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1675 Inst.addOperand(
1676 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1677 return S;
1678 }
1679
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1680 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1681 }
1682
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1684 return MCDisassembler::Fail;
1685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1686 return MCDisassembler::Fail; // Tied
1687 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1688 return MCDisassembler::Fail;
1689 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1690 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1691
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1692 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1693}
1694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1695static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1696 uint64_t Address, const void *Decoder) {
1697 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1698 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1699 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1700 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1701
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1702 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1703
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1704 // imod == '01' --> UNPREDICTABLE
1705 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1706 // return failure here. The '01' imod value is unprintable, so there's
1707 // nothing useful we could do even if we returned UNPREDICTABLE.
1708
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1709 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1710
1711 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1712 Inst.setOpcode(ARM::CPS3p);
1713 Inst.addOperand(MCOperand::CreateImm(imod));
1714 Inst.addOperand(MCOperand::CreateImm(iflags));
1715 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1716 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1717 Inst.setOpcode(ARM::CPS2p);
1718 Inst.addOperand(MCOperand::CreateImm(imod));
1719 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1720 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1721 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1722 Inst.setOpcode(ARM::CPS1p);
1723 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1724 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1725 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1726 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1727 Inst.setOpcode(ARM::CPS1p);
1728 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1729 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1730 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1731
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1732 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1733}
1734
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1735static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1736 uint64_t Address, const void *Decoder) {
1737 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1738 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1739 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1740 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1741
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1742 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1743
1744 // imod == '01' --> UNPREDICTABLE
1745 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1746 // return failure here. The '01' imod value is unprintable, so there's
1747 // nothing useful we could do even if we returned UNPREDICTABLE.
1748
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1749 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1750
1751 if (imod && M) {
1752 Inst.setOpcode(ARM::t2CPS3p);
1753 Inst.addOperand(MCOperand::CreateImm(imod));
1754 Inst.addOperand(MCOperand::CreateImm(iflags));
1755 Inst.addOperand(MCOperand::CreateImm(mode));
1756 } else if (imod && !M) {
1757 Inst.setOpcode(ARM::t2CPS2p);
1758 Inst.addOperand(MCOperand::CreateImm(imod));
1759 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1760 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1761 } else if (!imod && M) {
1762 Inst.setOpcode(ARM::t2CPS1p);
1763 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1764 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1765 } else {
1766 // imod == '00' && M == '0' --> UNPREDICTABLE
1767 Inst.setOpcode(ARM::t2CPS1p);
1768 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1769 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1770 }
1771
1772 return S;
1773}
1774
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1775static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1776 uint64_t Address, const void *Decoder) {
1777 DecodeStatus S = MCDisassembler::Success;
1778
1779 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1780 unsigned imm = 0;
1781
1782 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1783 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1784 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1785 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1786
1787 if (Inst.getOpcode() == ARM::t2MOVTi16)
1788 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1789 return MCDisassembler::Fail;
1790 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1791 return MCDisassembler::Fail;
1792
1793 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1794 Inst.addOperand(MCOperand::CreateImm(imm));
1795
1796 return S;
1797}
1798
1799static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1800 uint64_t Address, const void *Decoder) {
1801 DecodeStatus S = MCDisassembler::Success;
1802
1803 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1804 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1805 unsigned imm = 0;
1806
1807 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1808 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1809
1810 if (Inst.getOpcode() == ARM::MOVTi16)
1811 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1812 return MCDisassembler::Fail;
1813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1814 return MCDisassembler::Fail;
1815
1816 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1817 Inst.addOperand(MCOperand::CreateImm(imm));
1818
1819 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1820 return MCDisassembler::Fail;
1821
1822 return S;
1823}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1824
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1825static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1826 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1827 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1828
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1829 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1830 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1831 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1832 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1833 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1834
1835 if (pred == 0xF)
1836 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1837
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1838 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1839 return MCDisassembler::Fail;
1840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1841 return MCDisassembler::Fail;
1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1843 return MCDisassembler::Fail;
1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1845 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1846
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1847 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1848 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1849
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1850 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1851}
1852
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1853static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1854 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1855 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1856
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1857 unsigned add = fieldFromInstruction32(Val, 12, 1);
1858 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1859 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1860
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1862 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1863
1864 if (!add) imm *= -1;
1865 if (imm == 0 && !add) imm = INT32_MIN;
1866 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1867 if (Rn == 15)
1868 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1869
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1870 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1871}
1872
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1873static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1874 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1875 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1876
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1877 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1878 unsigned U = fieldFromInstruction32(Val, 8, 1);
1879 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1882 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1883
1884 if (U)
1885 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1886 else
1887 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1888
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1889 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1890}
1891
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1892static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1893 uint64_t Address, const void *Decoder) {
1894 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1895}
1896
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1897static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1898DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1899 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1900 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1901
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1902 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1903 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1904
1905 if (pred == 0xF) {
1906 Inst.setOpcode(ARM::BLXi);
1907 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1908 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1909 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1910 }
1911
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1912 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1913 4, Inst, Decoder))
1914 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1915 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1916 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1917
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1918 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1919}
1920
1921
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1922static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1923 uint64_t Address, const void *Decoder) {
1924 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1925 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1926}
1927
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1928static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1929 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1930 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1931
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1932 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1933 unsigned align = fieldFromInstruction32(Val, 4, 2);
1934
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1936 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1937 if (!align)
1938 Inst.addOperand(MCOperand::CreateImm(0));
1939 else
1940 Inst.addOperand(MCOperand::CreateImm(4 << align));
1941
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1942 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1943}
1944
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1945static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1946 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1947 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1948
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1949 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1950 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1951 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1952 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1953 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1954 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1955
1956 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1958 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1959
1960 // Second output register
1961 switch (Inst.getOpcode()) {
1962 case ARM::VLD1q8:
1963 case ARM::VLD1q16:
1964 case ARM::VLD1q32:
1965 case ARM::VLD1q64:
1966 case ARM::VLD1q8_UPD:
1967 case ARM::VLD1q16_UPD:
1968 case ARM::VLD1q32_UPD:
1969 case ARM::VLD1q64_UPD:
1970 case ARM::VLD1d8T:
1971 case ARM::VLD1d16T:
1972 case ARM::VLD1d32T:
1973 case ARM::VLD1d64T:
1974 case ARM::VLD1d8T_UPD:
1975 case ARM::VLD1d16T_UPD:
1976 case ARM::VLD1d32T_UPD:
1977 case ARM::VLD1d64T_UPD:
1978 case ARM::VLD1d8Q:
1979 case ARM::VLD1d16Q:
1980 case ARM::VLD1d32Q:
1981 case ARM::VLD1d64Q:
1982 case ARM::VLD1d8Q_UPD:
1983 case ARM::VLD1d16Q_UPD:
1984 case ARM::VLD1d32Q_UPD:
1985 case ARM::VLD1d64Q_UPD:
1986 case ARM::VLD2d8:
1987 case ARM::VLD2d16:
1988 case ARM::VLD2d32:
1989 case ARM::VLD2d8_UPD:
1990 case ARM::VLD2d16_UPD:
1991 case ARM::VLD2d32_UPD:
1992 case ARM::VLD2q8:
1993 case ARM::VLD2q16:
1994 case ARM::VLD2q32:
1995 case ARM::VLD2q8_UPD:
1996 case ARM::VLD2q16_UPD:
1997 case ARM::VLD2q32_UPD:
1998 case ARM::VLD3d8:
1999 case ARM::VLD3d16:
2000 case ARM::VLD3d32:
2001 case ARM::VLD3d8_UPD:
2002 case ARM::VLD3d16_UPD:
2003 case ARM::VLD3d32_UPD:
2004 case ARM::VLD4d8:
2005 case ARM::VLD4d16:
2006 case ARM::VLD4d32:
2007 case ARM::VLD4d8_UPD:
2008 case ARM::VLD4d16_UPD:
2009 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2010 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2011 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2012 break;
2013 case ARM::VLD2b8:
2014 case ARM::VLD2b16:
2015 case ARM::VLD2b32:
2016 case ARM::VLD2b8_UPD:
2017 case ARM::VLD2b16_UPD:
2018 case ARM::VLD2b32_UPD:
2019 case ARM::VLD3q8:
2020 case ARM::VLD3q16:
2021 case ARM::VLD3q32:
2022 case ARM::VLD3q8_UPD:
2023 case ARM::VLD3q16_UPD:
2024 case ARM::VLD3q32_UPD:
2025 case ARM::VLD4q8:
2026 case ARM::VLD4q16:
2027 case ARM::VLD4q32:
2028 case ARM::VLD4q8_UPD:
2029 case ARM::VLD4q16_UPD:
2030 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2031 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2032 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2033 default:
2034 break;
2035 }
2036
2037 // Third output register
2038 switch(Inst.getOpcode()) {
2039 case ARM::VLD1d8T:
2040 case ARM::VLD1d16T:
2041 case ARM::VLD1d32T:
2042 case ARM::VLD1d64T:
2043 case ARM::VLD1d8T_UPD:
2044 case ARM::VLD1d16T_UPD:
2045 case ARM::VLD1d32T_UPD:
2046 case ARM::VLD1d64T_UPD:
2047 case ARM::VLD1d8Q:
2048 case ARM::VLD1d16Q:
2049 case ARM::VLD1d32Q:
2050 case ARM::VLD1d64Q:
2051 case ARM::VLD1d8Q_UPD:
2052 case ARM::VLD1d16Q_UPD:
2053 case ARM::VLD1d32Q_UPD:
2054 case ARM::VLD1d64Q_UPD:
2055 case ARM::VLD2q8:
2056 case ARM::VLD2q16:
2057 case ARM::VLD2q32:
2058 case ARM::VLD2q8_UPD:
2059 case ARM::VLD2q16_UPD:
2060 case ARM::VLD2q32_UPD:
2061 case ARM::VLD3d8:
2062 case ARM::VLD3d16:
2063 case ARM::VLD3d32:
2064 case ARM::VLD3d8_UPD:
2065 case ARM::VLD3d16_UPD:
2066 case ARM::VLD3d32_UPD:
2067 case ARM::VLD4d8:
2068 case ARM::VLD4d16:
2069 case ARM::VLD4d32:
2070 case ARM::VLD4d8_UPD:
2071 case ARM::VLD4d16_UPD:
2072 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2073 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2074 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2075 break;
2076 case ARM::VLD3q8:
2077 case ARM::VLD3q16:
2078 case ARM::VLD3q32:
2079 case ARM::VLD3q8_UPD:
2080 case ARM::VLD3q16_UPD:
2081 case ARM::VLD3q32_UPD:
2082 case ARM::VLD4q8:
2083 case ARM::VLD4q16:
2084 case ARM::VLD4q32:
2085 case ARM::VLD4q8_UPD:
2086 case ARM::VLD4q16_UPD:
2087 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2088 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2089 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2090 break;
2091 default:
2092 break;
2093 }
2094
2095 // Fourth output register
2096 switch (Inst.getOpcode()) {
2097 case ARM::VLD1d8Q:
2098 case ARM::VLD1d16Q:
2099 case ARM::VLD1d32Q:
2100 case ARM::VLD1d64Q:
2101 case ARM::VLD1d8Q_UPD:
2102 case ARM::VLD1d16Q_UPD:
2103 case ARM::VLD1d32Q_UPD:
2104 case ARM::VLD1d64Q_UPD:
2105 case ARM::VLD2q8:
2106 case ARM::VLD2q16:
2107 case ARM::VLD2q32:
2108 case ARM::VLD2q8_UPD:
2109 case ARM::VLD2q16_UPD:
2110 case ARM::VLD2q32_UPD:
2111 case ARM::VLD4d8:
2112 case ARM::VLD4d16:
2113 case ARM::VLD4d32:
2114 case ARM::VLD4d8_UPD:
2115 case ARM::VLD4d16_UPD:
2116 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2117 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2118 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2119 break;
2120 case ARM::VLD4q8:
2121 case ARM::VLD4q16:
2122 case ARM::VLD4q32:
2123 case ARM::VLD4q8_UPD:
2124 case ARM::VLD4q16_UPD:
2125 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2126 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2127 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2128 break;
2129 default:
2130 break;
2131 }
2132
2133 // Writeback operand
2134 switch (Inst.getOpcode()) {
2135 case ARM::VLD1d8_UPD:
2136 case ARM::VLD1d16_UPD:
2137 case ARM::VLD1d32_UPD:
2138 case ARM::VLD1d64_UPD:
2139 case ARM::VLD1q8_UPD:
2140 case ARM::VLD1q16_UPD:
2141 case ARM::VLD1q32_UPD:
2142 case ARM::VLD1q64_UPD:
2143 case ARM::VLD1d8T_UPD:
2144 case ARM::VLD1d16T_UPD:
2145 case ARM::VLD1d32T_UPD:
2146 case ARM::VLD1d64T_UPD:
2147 case ARM::VLD1d8Q_UPD:
2148 case ARM::VLD1d16Q_UPD:
2149 case ARM::VLD1d32Q_UPD:
2150 case ARM::VLD1d64Q_UPD:
2151 case ARM::VLD2d8_UPD:
2152 case ARM::VLD2d16_UPD:
2153 case ARM::VLD2d32_UPD:
2154 case ARM::VLD2q8_UPD:
2155 case ARM::VLD2q16_UPD:
2156 case ARM::VLD2q32_UPD:
2157 case ARM::VLD2b8_UPD:
2158 case ARM::VLD2b16_UPD:
2159 case ARM::VLD2b32_UPD:
2160 case ARM::VLD3d8_UPD:
2161 case ARM::VLD3d16_UPD:
2162 case ARM::VLD3d32_UPD:
2163 case ARM::VLD3q8_UPD:
2164 case ARM::VLD3q16_UPD:
2165 case ARM::VLD3q32_UPD:
2166 case ARM::VLD4d8_UPD:
2167 case ARM::VLD4d16_UPD:
2168 case ARM::VLD4d32_UPD:
2169 case ARM::VLD4q8_UPD:
2170 case ARM::VLD4q16_UPD:
2171 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2172 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2173 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2174 break;
2175 default:
2176 break;
2177 }
2178
2179 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2180 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2181 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2182
2183 // AddrMode6 Offset (register)
2184 if (Rm == 0xD)
2185 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2186 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2188 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2189 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2190
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2191 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2192}
2193
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2194static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2195 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2196 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2197
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2198 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2199 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2200 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2201 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2202 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2203 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2204
2205 // Writeback Operand
2206 switch (Inst.getOpcode()) {
2207 case ARM::VST1d8_UPD:
2208 case ARM::VST1d16_UPD:
2209 case ARM::VST1d32_UPD:
2210 case ARM::VST1d64_UPD:
2211 case ARM::VST1q8_UPD:
2212 case ARM::VST1q16_UPD:
2213 case ARM::VST1q32_UPD:
2214 case ARM::VST1q64_UPD:
2215 case ARM::VST1d8T_UPD:
2216 case ARM::VST1d16T_UPD:
2217 case ARM::VST1d32T_UPD:
2218 case ARM::VST1d64T_UPD:
2219 case ARM::VST1d8Q_UPD:
2220 case ARM::VST1d16Q_UPD:
2221 case ARM::VST1d32Q_UPD:
2222 case ARM::VST1d64Q_UPD:
2223 case ARM::VST2d8_UPD:
2224 case ARM::VST2d16_UPD:
2225 case ARM::VST2d32_UPD:
2226 case ARM::VST2q8_UPD:
2227 case ARM::VST2q16_UPD:
2228 case ARM::VST2q32_UPD:
2229 case ARM::VST2b8_UPD:
2230 case ARM::VST2b16_UPD:
2231 case ARM::VST2b32_UPD:
2232 case ARM::VST3d8_UPD:
2233 case ARM::VST3d16_UPD:
2234 case ARM::VST3d32_UPD:
2235 case ARM::VST3q8_UPD:
2236 case ARM::VST3q16_UPD:
2237 case ARM::VST3q32_UPD:
2238 case ARM::VST4d8_UPD:
2239 case ARM::VST4d16_UPD:
2240 case ARM::VST4d32_UPD:
2241 case ARM::VST4q8_UPD:
2242 case ARM::VST4q16_UPD:
2243 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2244 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2245 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2246 break;
2247 default:
2248 break;
2249 }
2250
2251 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2252 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2253 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2254
2255 // AddrMode6 Offset (register)
2256 if (Rm == 0xD)
2257 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2258 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2260 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2261 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2262
2263 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2264 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2265 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2266
2267 // Second input register
2268 switch (Inst.getOpcode()) {
2269 case ARM::VST1q8:
2270 case ARM::VST1q16:
2271 case ARM::VST1q32:
2272 case ARM::VST1q64:
2273 case ARM::VST1q8_UPD:
2274 case ARM::VST1q16_UPD:
2275 case ARM::VST1q32_UPD:
2276 case ARM::VST1q64_UPD:
2277 case ARM::VST1d8T:
2278 case ARM::VST1d16T:
2279 case ARM::VST1d32T:
2280 case ARM::VST1d64T:
2281 case ARM::VST1d8T_UPD:
2282 case ARM::VST1d16T_UPD:
2283 case ARM::VST1d32T_UPD:
2284 case ARM::VST1d64T_UPD:
2285 case ARM::VST1d8Q:
2286 case ARM::VST1d16Q:
2287 case ARM::VST1d32Q:
2288 case ARM::VST1d64Q:
2289 case ARM::VST1d8Q_UPD:
2290 case ARM::VST1d16Q_UPD:
2291 case ARM::VST1d32Q_UPD:
2292 case ARM::VST1d64Q_UPD:
2293 case ARM::VST2d8:
2294 case ARM::VST2d16:
2295 case ARM::VST2d32:
2296 case ARM::VST2d8_UPD:
2297 case ARM::VST2d16_UPD:
2298 case ARM::VST2d32_UPD:
2299 case ARM::VST2q8:
2300 case ARM::VST2q16:
2301 case ARM::VST2q32:
2302 case ARM::VST2q8_UPD:
2303 case ARM::VST2q16_UPD:
2304 case ARM::VST2q32_UPD:
2305 case ARM::VST3d8:
2306 case ARM::VST3d16:
2307 case ARM::VST3d32:
2308 case ARM::VST3d8_UPD:
2309 case ARM::VST3d16_UPD:
2310 case ARM::VST3d32_UPD:
2311 case ARM::VST4d8:
2312 case ARM::VST4d16:
2313 case ARM::VST4d32:
2314 case ARM::VST4d8_UPD:
2315 case ARM::VST4d16_UPD:
2316 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2317 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2318 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2319 break;
2320 case ARM::VST2b8:
2321 case ARM::VST2b16:
2322 case ARM::VST2b32:
2323 case ARM::VST2b8_UPD:
2324 case ARM::VST2b16_UPD:
2325 case ARM::VST2b32_UPD:
2326 case ARM::VST3q8:
2327 case ARM::VST3q16:
2328 case ARM::VST3q32:
2329 case ARM::VST3q8_UPD:
2330 case ARM::VST3q16_UPD:
2331 case ARM::VST3q32_UPD:
2332 case ARM::VST4q8:
2333 case ARM::VST4q16:
2334 case ARM::VST4q32:
2335 case ARM::VST4q8_UPD:
2336 case ARM::VST4q16_UPD:
2337 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2338 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2339 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2340 break;
2341 default:
2342 break;
2343 }
2344
2345 // Third input register
2346 switch (Inst.getOpcode()) {
2347 case ARM::VST1d8T:
2348 case ARM::VST1d16T:
2349 case ARM::VST1d32T:
2350 case ARM::VST1d64T:
2351 case ARM::VST1d8T_UPD:
2352 case ARM::VST1d16T_UPD:
2353 case ARM::VST1d32T_UPD:
2354 case ARM::VST1d64T_UPD:
2355 case ARM::VST1d8Q:
2356 case ARM::VST1d16Q:
2357 case ARM::VST1d32Q:
2358 case ARM::VST1d64Q:
2359 case ARM::VST1d8Q_UPD:
2360 case ARM::VST1d16Q_UPD:
2361 case ARM::VST1d32Q_UPD:
2362 case ARM::VST1d64Q_UPD:
2363 case ARM::VST2q8:
2364 case ARM::VST2q16:
2365 case ARM::VST2q32:
2366 case ARM::VST2q8_UPD:
2367 case ARM::VST2q16_UPD:
2368 case ARM::VST2q32_UPD:
2369 case ARM::VST3d8:
2370 case ARM::VST3d16:
2371 case ARM::VST3d32:
2372 case ARM::VST3d8_UPD:
2373 case ARM::VST3d16_UPD:
2374 case ARM::VST3d32_UPD:
2375 case ARM::VST4d8:
2376 case ARM::VST4d16:
2377 case ARM::VST4d32:
2378 case ARM::VST4d8_UPD:
2379 case ARM::VST4d16_UPD:
2380 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2381 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2382 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2383 break;
2384 case ARM::VST3q8:
2385 case ARM::VST3q16:
2386 case ARM::VST3q32:
2387 case ARM::VST3q8_UPD:
2388 case ARM::VST3q16_UPD:
2389 case ARM::VST3q32_UPD:
2390 case ARM::VST4q8:
2391 case ARM::VST4q16:
2392 case ARM::VST4q32:
2393 case ARM::VST4q8_UPD:
2394 case ARM::VST4q16_UPD:
2395 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2396 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2397 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2398 break;
2399 default:
2400 break;
2401 }
2402
2403 // Fourth input register
2404 switch (Inst.getOpcode()) {
2405 case ARM::VST1d8Q:
2406 case ARM::VST1d16Q:
2407 case ARM::VST1d32Q:
2408 case ARM::VST1d64Q:
2409 case ARM::VST1d8Q_UPD:
2410 case ARM::VST1d16Q_UPD:
2411 case ARM::VST1d32Q_UPD:
2412 case ARM::VST1d64Q_UPD:
2413 case ARM::VST2q8:
2414 case ARM::VST2q16:
2415 case ARM::VST2q32:
2416 case ARM::VST2q8_UPD:
2417 case ARM::VST2q16_UPD:
2418 case ARM::VST2q32_UPD:
2419 case ARM::VST4d8:
2420 case ARM::VST4d16:
2421 case ARM::VST4d32:
2422 case ARM::VST4d8_UPD:
2423 case ARM::VST4d16_UPD:
2424 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2425 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2426 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2427 break;
2428 case ARM::VST4q8:
2429 case ARM::VST4q16:
2430 case ARM::VST4q32:
2431 case ARM::VST4q8_UPD:
2432 case ARM::VST4q16_UPD:
2433 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2434 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2435 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2436 break;
2437 default:
2438 break;
2439 }
2440
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2441 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2442}
2443
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2444static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2445 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2446 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2447
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2448 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2449 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2450 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2451 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2452 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2453 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2454 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2455
2456 align *= (1 << size);
2457
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2459 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2460 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2461 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2462 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2463 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2464 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2466 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2467 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2468
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2470 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2471 Inst.addOperand(MCOperand::CreateImm(align));
2472
2473 if (Rm == 0xD)
2474 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2475 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2476 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2477 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2478 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2479
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2480 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2481}
2482
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2483static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2484 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2485 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2486
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2487 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2488 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2489 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2490 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2491 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2492 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2493 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2494 align *= 2*size;
2495
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2496 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2497 return MCDisassembler::Fail;
2498 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2499 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2500 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2502 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2503 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2504
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2506 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2507 Inst.addOperand(MCOperand::CreateImm(align));
2508
2509 if (Rm == 0xD)
2510 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2511 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2513 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2514 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2515
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2516 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2517}
2518
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2519static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2520 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2521 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2522
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2523 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2524 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2525 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2526 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2527 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2528
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2529 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2530 return MCDisassembler::Fail;
2531 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2532 return MCDisassembler::Fail;
2533 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2534 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2535 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2537 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2538 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2539
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2541 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2542 Inst.addOperand(MCOperand::CreateImm(0));
2543
2544 if (Rm == 0xD)
2545 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2546 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2548 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2549 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2550
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2551 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2552}
2553
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2554static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2555 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2556 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2557
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2558 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2559 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2560 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2561 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2562 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2563 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2564 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2565
2566 if (size == 0x3) {
2567 size = 4;
2568 align = 16;
2569 } else {
2570 if (size == 2) {
2571 size = 1 << size;
2572 align *= 8;
2573 } else {
2574 size = 1 << size;
2575 align *= 4*size;
2576 }
2577 }
2578
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2579 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2580 return MCDisassembler::Fail;
2581 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2582 return MCDisassembler::Fail;
2583 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2584 return MCDisassembler::Fail;
2585 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2586 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2587 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2589 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2590 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2591
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2593 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2594 Inst.addOperand(MCOperand::CreateImm(align));
2595
2596 if (Rm == 0xD)
2597 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2598 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2600 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2601 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2602
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2603 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2604}
2605
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2606static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2607DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2608 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2609 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2610
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2611 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2612 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2613 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2614 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2615 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2616 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2617 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2618 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2619
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2620 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2621 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2622 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2623 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2625 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2626 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2627
2628 Inst.addOperand(MCOperand::CreateImm(imm));
2629
2630 switch (Inst.getOpcode()) {
2631 case ARM::VORRiv4i16:
2632 case ARM::VORRiv2i32:
2633 case ARM::VBICiv4i16:
2634 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2636 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2637 break;
2638 case ARM::VORRiv8i16:
2639 case ARM::VORRiv4i32:
2640 case ARM::VBICiv8i16:
2641 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2642 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2643 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2644 break;
2645 default:
2646 break;
2647 }
2648
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2649 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2650}
2651
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2652static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2653 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2654 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2655
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2656 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2657 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2658 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2659 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2660 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2661
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2662 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2663 return MCDisassembler::Fail;
2664 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2665 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2666 Inst.addOperand(MCOperand::CreateImm(8 << size));
2667
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2668 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2669}
2670
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2671static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2672 uint64_t Address, const void *Decoder) {
2673 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2674 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2675}
2676
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2677static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2678 uint64_t Address, const void *Decoder) {
2679 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2680 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2681}
2682
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2683static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684 uint64_t Address, const void *Decoder) {
2685 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2686 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2687}
2688
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2689static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2690 uint64_t Address, const void *Decoder) {
2691 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2692 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2693}
2694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2695static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2696 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2697 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2698
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2699 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2700 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2701 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2702 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2703 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2704 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2705 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2706 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2707
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2709 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2710 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2712 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2713 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2714
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2715 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2716 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2717 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2718 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2719
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2721 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2722
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2723 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2724}
2725
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2726static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2727 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2728 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2729
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2730 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2731 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2732
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2733 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2734 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2735
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2736 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2737 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2738 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2739 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2740 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2741 case ARM::tADDrSPi:
2742 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2743 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2744 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2745
2746 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2747 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2748}
2749
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2750static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2751 uint64_t Address, const void *Decoder) {
2752 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2753 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2754}
2755
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2756static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757 uint64_t Address, const void *Decoder) {
2758 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2759 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2760}
2761
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2762static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2763 uint64_t Address, const void *Decoder) {
2764 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2765 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2766}
2767
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2768static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2769 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2770 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2771
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2772 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2773 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2774
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2775 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2776 return MCDisassembler::Fail;
2777 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2778 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2779
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2780 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2781}
2782
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2783static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2784 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2785 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2786
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2787 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2788 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2789
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2790 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2791 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2792 Inst.addOperand(MCOperand::CreateImm(imm));
2793
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2794 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2795}
2796
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2797static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2798 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2799 unsigned imm = Val << 2;
2800
2801 Inst.addOperand(MCOperand::CreateImm(imm));
2802 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2803
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2804 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2805}
2806
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2807static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808 uint64_t Address, const void *Decoder) {
2809 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2810 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2811
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2812 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2813}
2814
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2815static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2816 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2817 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2818
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2819 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2820 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2821 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2822
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2824 return MCDisassembler::Fail;
2825 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2826 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2827 Inst.addOperand(MCOperand::CreateImm(imm));
2828
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2829 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2830}
2831
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2832static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2833 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2834 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2835
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2836 switch (Inst.getOpcode()) {
2837 case ARM::t2PLDs:
2838 case ARM::t2PLDWs:
2839 case ARM::t2PLIs:
2840 break;
2841 default: {
2842 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2843 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2844 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2845 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2846 }
2847
2848 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2849 if (Rn == 0xF) {
2850 switch (Inst.getOpcode()) {
2851 case ARM::t2LDRBs:
2852 Inst.setOpcode(ARM::t2LDRBpci);
2853 break;
2854 case ARM::t2LDRHs:
2855 Inst.setOpcode(ARM::t2LDRHpci);
2856 break;
2857 case ARM::t2LDRSHs:
2858 Inst.setOpcode(ARM::t2LDRSHpci);
2859 break;
2860 case ARM::t2LDRSBs:
2861 Inst.setOpcode(ARM::t2LDRSBpci);
2862 break;
2863 case ARM::t2PLDs:
2864 Inst.setOpcode(ARM::t2PLDi12);
2865 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2866 break;
2867 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2868 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2869 }
2870
2871 int imm = fieldFromInstruction32(Insn, 0, 12);
2872 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2873 Inst.addOperand(MCOperand::CreateImm(imm));
2874
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2875 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2876 }
2877
2878 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2879 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2880 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2881 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2882 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2883
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2884 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2885}
2886
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2887static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2888 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2889 int imm = Val & 0xFF;
2890 if (!(Val & 0x100)) imm *= -1;
2891 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2892
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2893 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2894}
2895
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2896static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2897 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2898 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2899
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2901 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2902
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2904 return MCDisassembler::Fail;
2905 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2906 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2908 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2909}
2910
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2911static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2912 uint64_t Address, const void *Decoder) {
2913 DecodeStatus S = MCDisassembler::Success;
2914
2915 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2916 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2917
2918 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2919 return MCDisassembler::Fail;
2920
2921 Inst.addOperand(MCOperand::CreateImm(imm));
2922
2923 return S;
2924}
2925
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2926static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2927 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2928 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2929 if (Val == 0)
2930 imm = INT32_MIN;
2931 else if (!(Val & 0x100))
2932 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2933 Inst.addOperand(MCOperand::CreateImm(imm));
2934
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2935 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2936}
2937
2938
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2939static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2940 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2941 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2942
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2943 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2944 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2945
2946 // Some instructions always use an additive offset.
2947 switch (Inst.getOpcode()) {
2948 case ARM::t2LDRT:
2949 case ARM::t2LDRBT:
2950 case ARM::t2LDRHT:
2951 case ARM::t2LDRSBT:
2952 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2953 case ARM::t2STRT:
2954 case ARM::t2STRBT:
2955 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2956 imm |= 0x100;
2957 break;
2958 default:
2959 break;
2960 }
2961
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2963 return MCDisassembler::Fail;
2964 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2965 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2966
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2967 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2968}
2969
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2970static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2971 uint64_t Address, const void *Decoder) {
2972 DecodeStatus S = MCDisassembler::Success;
2973
2974 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2975 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2976 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2977 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2978 addr |= Rn << 9;
2979 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2980
2981 if (!load) {
2982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2983 return MCDisassembler::Fail;
2984 }
2985
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2986 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2987 return MCDisassembler::Fail;
2988
2989 if (load) {
2990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2991 return MCDisassembler::Fail;
2992 }
2993
2994 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996
2997 return S;
2998}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3000static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3001 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3002 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3003
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3004 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3005 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3006
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3008 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3009 Inst.addOperand(MCOperand::CreateImm(imm));
3010
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3011 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3012}
3013
3014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3015static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3016 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3017 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3018
3019 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3020 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3021 Inst.addOperand(MCOperand::CreateImm(imm));
3022
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3023 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3024}
3025
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3026static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3027 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3028 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3029
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3030 if (Inst.getOpcode() == ARM::tADDrSP) {
3031 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3032 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3033
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3035 return MCDisassembler::Fail;
3036 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3037 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3038 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3039 } else if (Inst.getOpcode() == ARM::tADDspr) {
3040 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3041
3042 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3043 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3045 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3046 }
3047
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3048 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3049}
3050
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3051static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3052 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3053 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3054 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3055
3056 Inst.addOperand(MCOperand::CreateImm(imod));
3057 Inst.addOperand(MCOperand::CreateImm(flags));
3058
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3059 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3060}
3061
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3062static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3063 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3064 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3065 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3066 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3067
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3068 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3069 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3070 Inst.addOperand(MCOperand::CreateImm(add));
3071
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3072 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3073}
3074
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3075static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3076 uint64_t Address, const void *Decoder) {
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame^]3077 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3078 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3079 true, 4, Inst, Decoder))
3080 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3081 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3082}
3083
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3084static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3085 uint64_t Address, const void *Decoder) {
3086 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3087 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3088
3089 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3090 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3091}
3092
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3093static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3094DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3095 uint64_t Address, const void *Decoder) {
3096 DecodeStatus S = MCDisassembler::Success;
3097
3098 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3099 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3100
3101 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3103 return MCDisassembler::Fail;
3104 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3105 return MCDisassembler::Fail;
3106 return S;
3107}
3108
3109static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3110DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3111 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3112 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3113
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3114 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3115 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3116 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3117 switch (opc) {
3118 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3119 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3120 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3121 Inst.setOpcode(ARM::t2DSB);
3122 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3123 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3124 Inst.setOpcode(ARM::t2DMB);
3125 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3126 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3127 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3128 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3129 }
3130
3131 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3132 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3133 }
3134
3135 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3136 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3137 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3138 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3139 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3140
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3141 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3142 return MCDisassembler::Fail;
3143 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3144 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3145
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3146 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3147}
3148
3149// Decode a shifted immediate operand. These basically consist
3150// of an 8-bit value, and a 4-bit directive that specifies either
3151// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3152static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3153 uint64_t Address, const void *Decoder) {
3154 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3155 if (ctrl == 0) {
3156 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3157 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3158 switch (byte) {
3159 case 0:
3160 Inst.addOperand(MCOperand::CreateImm(imm));
3161 break;
3162 case 1:
3163 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3164 break;
3165 case 2:
3166 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3167 break;
3168 case 3:
3169 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3170 (imm << 8) | imm));
3171 break;
3172 }
3173 } else {
3174 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3175 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3176 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3177 Inst.addOperand(MCOperand::CreateImm(imm));
3178 }
3179
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3180 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3181}
3182
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3183static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3184DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3185 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3186 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3187 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3188}
3189
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3190static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3191 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3192 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3193 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3194}
3195
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3196static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3197 uint64_t Address, const void *Decoder) {
3198 switch (Val) {
3199 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3200 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3201 case 0xF: // SY
3202 case 0xE: // ST
3203 case 0xB: // ISH
3204 case 0xA: // ISHST
3205 case 0x7: // NSH
3206 case 0x6: // NSHST
3207 case 0x3: // OSH
3208 case 0x2: // OSHST
3209 break;
3210 }
3211
3212 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3213 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3214}
3215
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3216static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3217 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3218 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3219 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3220 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3221}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3222
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3223static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3224 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3225 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3226
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3227 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3228 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3229 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3230
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3231 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3232
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3234 return MCDisassembler::Fail;
3235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3236 return MCDisassembler::Fail;
3237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3238 return MCDisassembler::Fail;
3239 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3240 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3241
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3242 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3243}
3244
3245
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3246static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3247 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3248 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3249
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3250 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3251 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3252 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3253 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3255 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3256 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3257
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3258 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3259 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3260
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3262 return MCDisassembler::Fail;
3263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3264 return MCDisassembler::Fail;
3265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3266 return MCDisassembler::Fail;
3267 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3268 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3269
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3270 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3271}
3272
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3273static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3274 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3275 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3276
3277 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3278 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3279 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3280 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3281 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3282 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3283
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3284 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3285
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3287 return MCDisassembler::Fail;
3288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3289 return MCDisassembler::Fail;
3290 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3291 return MCDisassembler::Fail;
3292 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3293 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3294
3295 return S;
3296}
3297
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3298static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3299 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3300 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3301
3302 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3303 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3304 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3305 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3306 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3307 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3308 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3309
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3310 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3311 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3312
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3314 return MCDisassembler::Fail;
3315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3316 return MCDisassembler::Fail;
3317 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3318 return MCDisassembler::Fail;
3319 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3320 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3321
3322 return S;
3323}
3324
3325
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3326static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3327 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3328 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3329
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3330 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3331 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3332 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3333 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3334 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3335 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3336
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3337 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3338
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3340 return MCDisassembler::Fail;
3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3342 return MCDisassembler::Fail;
3343 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3344 return MCDisassembler::Fail;
3345 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3346 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3347
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3348 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3349}
3350
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3351static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3352 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3353 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3354
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3355 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3356 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3357 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3358 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3359 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3360 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3361
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3362 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3363
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3365 return MCDisassembler::Fail;
3366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3367 return MCDisassembler::Fail;
3368 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3369 return MCDisassembler::Fail;
3370 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3371 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3372
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3373 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3374}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3375
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3376static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3377 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3378 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3379
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3380 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3381 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3382 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3383 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3384 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3385
3386 unsigned align = 0;
3387 unsigned index = 0;
3388 switch (size) {
3389 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3390 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3391 case 0:
3392 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3393 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3394 index = fieldFromInstruction32(Insn, 5, 3);
3395 break;
3396 case 1:
3397 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3398 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3399 index = fieldFromInstruction32(Insn, 6, 2);
3400 if (fieldFromInstruction32(Insn, 4, 1))
3401 align = 2;
3402 break;
3403 case 2:
3404 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3405 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3406 index = fieldFromInstruction32(Insn, 7, 1);
3407 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3408 align = 4;
3409 }
3410
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3411 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3412 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3413 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3415 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3416 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3418 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3419 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3420 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3421 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3423 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3424 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3425 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3426 }
3427
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3429 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3430 Inst.addOperand(MCOperand::CreateImm(index));
3431
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3432 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3433}
3434
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3435static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3436 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3437 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3438
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3439 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3440 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3441 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3442 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3443 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3444
3445 unsigned align = 0;
3446 unsigned index = 0;
3447 switch (size) {
3448 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3449 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3450 case 0:
3451 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3452 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3453 index = fieldFromInstruction32(Insn, 5, 3);
3454 break;
3455 case 1:
3456 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3457 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3458 index = fieldFromInstruction32(Insn, 6, 2);
3459 if (fieldFromInstruction32(Insn, 4, 1))
3460 align = 2;
3461 break;
3462 case 2:
3463 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3464 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3465 index = fieldFromInstruction32(Insn, 7, 1);
3466 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3467 align = 4;
3468 }
3469
3470 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3472 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3473 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3475 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3476 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3477 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3478 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3480 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3481 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3482 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3483 }
3484
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3485 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3486 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3487 Inst.addOperand(MCOperand::CreateImm(index));
3488
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3489 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3490}
3491
3492
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3493static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3494 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3495 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3496
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3497 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3498 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3499 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3500 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3501 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3502
3503 unsigned align = 0;
3504 unsigned index = 0;
3505 unsigned inc = 1;
3506 switch (size) {
3507 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3508 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3509 case 0:
3510 index = fieldFromInstruction32(Insn, 5, 3);
3511 if (fieldFromInstruction32(Insn, 4, 1))
3512 align = 2;
3513 break;
3514 case 1:
3515 index = fieldFromInstruction32(Insn, 6, 2);
3516 if (fieldFromInstruction32(Insn, 4, 1))
3517 align = 4;
3518 if (fieldFromInstruction32(Insn, 5, 1))
3519 inc = 2;
3520 break;
3521 case 2:
3522 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3523 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3524 index = fieldFromInstruction32(Insn, 7, 1);
3525 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3526 align = 8;
3527 if (fieldFromInstruction32(Insn, 6, 1))
3528 inc = 2;
3529 break;
3530 }
3531
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3532 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3533 return MCDisassembler::Fail;
3534 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3535 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3536 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3538 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3539 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3541 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3542 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3543 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3544 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3546 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3547 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3548 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3549 }
3550
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3551 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3552 return MCDisassembler::Fail;
3553 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3554 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3555 Inst.addOperand(MCOperand::CreateImm(index));
3556
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3557 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3558}
3559
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3560static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3561 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3562 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3563
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3564 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3565 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3566 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3567 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3568 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3569
3570 unsigned align = 0;
3571 unsigned index = 0;
3572 unsigned inc = 1;
3573 switch (size) {
3574 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3575 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3576 case 0:
3577 index = fieldFromInstruction32(Insn, 5, 3);
3578 if (fieldFromInstruction32(Insn, 4, 1))
3579 align = 2;
3580 break;
3581 case 1:
3582 index = fieldFromInstruction32(Insn, 6, 2);
3583 if (fieldFromInstruction32(Insn, 4, 1))
3584 align = 4;
3585 if (fieldFromInstruction32(Insn, 5, 1))
3586 inc = 2;
3587 break;
3588 case 2:
3589 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3590 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3591 index = fieldFromInstruction32(Insn, 7, 1);
3592 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3593 align = 8;
3594 if (fieldFromInstruction32(Insn, 6, 1))
3595 inc = 2;
3596 break;
3597 }
3598
3599 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3600 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3601 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3602 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3604 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3605 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3606 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3607 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3609 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3610 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3611 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3612 }
3613
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3615 return MCDisassembler::Fail;
3616 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3617 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3618 Inst.addOperand(MCOperand::CreateImm(index));
3619
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3620 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3621}
3622
3623
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3624static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3625 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3626 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3627
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3628 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3629 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3630 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3631 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3632 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3633
3634 unsigned align = 0;
3635 unsigned index = 0;
3636 unsigned inc = 1;
3637 switch (size) {
3638 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3639 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3640 case 0:
3641 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3642 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3643 index = fieldFromInstruction32(Insn, 5, 3);
3644 break;
3645 case 1:
3646 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3647 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3648 index = fieldFromInstruction32(Insn, 6, 2);
3649 if (fieldFromInstruction32(Insn, 5, 1))
3650 inc = 2;
3651 break;
3652 case 2:
3653 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3654 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3655 index = fieldFromInstruction32(Insn, 7, 1);
3656 if (fieldFromInstruction32(Insn, 6, 1))
3657 inc = 2;
3658 break;
3659 }
3660
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3662 return MCDisassembler::Fail;
3663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3664 return MCDisassembler::Fail;
3665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3666 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3667
3668 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3670 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3671 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3672 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3673 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3674 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3675 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3676 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3678 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3679 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3680 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3681 }
3682
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3683 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3684 return MCDisassembler::Fail;
3685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3686 return MCDisassembler::Fail;
3687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3688 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3689 Inst.addOperand(MCOperand::CreateImm(index));
3690
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3691 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3692}
3693
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3694static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3695 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3696 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3697
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3698 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3699 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3700 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3701 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3702 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3703
3704 unsigned align = 0;
3705 unsigned index = 0;
3706 unsigned inc = 1;
3707 switch (size) {
3708 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3709 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3710 case 0:
3711 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3712 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3713 index = fieldFromInstruction32(Insn, 5, 3);
3714 break;
3715 case 1:
3716 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3717 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3718 index = fieldFromInstruction32(Insn, 6, 2);
3719 if (fieldFromInstruction32(Insn, 5, 1))
3720 inc = 2;
3721 break;
3722 case 2:
3723 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3724 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3725 index = fieldFromInstruction32(Insn, 7, 1);
3726 if (fieldFromInstruction32(Insn, 6, 1))
3727 inc = 2;
3728 break;
3729 }
3730
3731 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3733 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3734 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3736 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3737 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3738 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3739 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3741 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3742 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3743 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3744 }
3745
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3747 return MCDisassembler::Fail;
3748 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3749 return MCDisassembler::Fail;
3750 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3751 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3752 Inst.addOperand(MCOperand::CreateImm(index));
3753
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3754 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3755}
3756
3757
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3758static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3759 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3760 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3761
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3762 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3763 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3764 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3765 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3766 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3767
3768 unsigned align = 0;
3769 unsigned index = 0;
3770 unsigned inc = 1;
3771 switch (size) {
3772 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3773 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3774 case 0:
3775 if (fieldFromInstruction32(Insn, 4, 1))
3776 align = 4;
3777 index = fieldFromInstruction32(Insn, 5, 3);
3778 break;
3779 case 1:
3780 if (fieldFromInstruction32(Insn, 4, 1))
3781 align = 8;
3782 index = fieldFromInstruction32(Insn, 6, 2);
3783 if (fieldFromInstruction32(Insn, 5, 1))
3784 inc = 2;
3785 break;
3786 case 2:
3787 if (fieldFromInstruction32(Insn, 4, 2))
3788 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3789 index = fieldFromInstruction32(Insn, 7, 1);
3790 if (fieldFromInstruction32(Insn, 6, 1))
3791 inc = 2;
3792 break;
3793 }
3794
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3795 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3796 return MCDisassembler::Fail;
3797 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3798 return MCDisassembler::Fail;
3799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3800 return MCDisassembler::Fail;
3801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3802 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3803
3804 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3806 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3807 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3809 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3810 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3811 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3812 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3814 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3815 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3816 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3817 }
3818
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3819 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3820 return MCDisassembler::Fail;
3821 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3822 return MCDisassembler::Fail;
3823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3824 return MCDisassembler::Fail;
3825 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3826 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3827 Inst.addOperand(MCOperand::CreateImm(index));
3828
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3829 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3830}
3831
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3832static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3833 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3834 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3835
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3836 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3837 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3838 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3839 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3840 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3841
3842 unsigned align = 0;
3843 unsigned index = 0;
3844 unsigned inc = 1;
3845 switch (size) {
3846 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3847 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3848 case 0:
3849 if (fieldFromInstruction32(Insn, 4, 1))
3850 align = 4;
3851 index = fieldFromInstruction32(Insn, 5, 3);
3852 break;
3853 case 1:
3854 if (fieldFromInstruction32(Insn, 4, 1))
3855 align = 8;
3856 index = fieldFromInstruction32(Insn, 6, 2);
3857 if (fieldFromInstruction32(Insn, 5, 1))
3858 inc = 2;
3859 break;
3860 case 2:
3861 if (fieldFromInstruction32(Insn, 4, 2))
3862 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3863 index = fieldFromInstruction32(Insn, 7, 1);
3864 if (fieldFromInstruction32(Insn, 6, 1))
3865 inc = 2;
3866 break;
3867 }
3868
3869 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3871 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3872 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3874 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3875 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3876 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3877 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3879 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3880 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3881 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3882 }
3883
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3884 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3885 return MCDisassembler::Fail;
3886 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3887 return MCDisassembler::Fail;
3888 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3889 return MCDisassembler::Fail;
3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3891 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3892 Inst.addOperand(MCOperand::CreateImm(index));
3893
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3894 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3895}
3896
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3897static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3898 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3899 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3900 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3901 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3902 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3903 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3904 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3905
3906 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3907 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3908
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3909 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3910 return MCDisassembler::Fail;
3911 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3912 return MCDisassembler::Fail;
3913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3914 return MCDisassembler::Fail;
3915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3916 return MCDisassembler::Fail;
3917 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3918 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3919
3920 return S;
3921}
3922
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3923static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3924 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3925 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3926 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3927 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3928 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3929 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3930 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3931
3932 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3933 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3934
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3936 return MCDisassembler::Fail;
3937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3938 return MCDisassembler::Fail;
3939 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3940 return MCDisassembler::Fail;
3941 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3942 return MCDisassembler::Fail;
3943 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3944 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3945
3946 return S;
3947}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3948
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3949static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3950 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3951 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3952 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3953 // The InstPrinter needs to have the low bit of the predicate in
3954 // the mask operand to be able to print it properly.
3955 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3956
3957 if (pred == 0xF) {
3958 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3959 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3960 }
3961
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3962 if ((mask & 0xF) == 0) {
3963 // Preserve the high bit of the mask, which is the low bit of
3964 // the predicate.
3965 mask &= 0x10;
3966 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3967 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3968 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3969
3970 Inst.addOperand(MCOperand::CreateImm(pred));
3971 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3972 return S;
3973}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3974
3975static DecodeStatus
3976DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3977 uint64_t Address, const void *Decoder) {
3978 DecodeStatus S = MCDisassembler::Success;
3979
3980 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3981 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3982 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3983 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3984 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3985 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3986 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3987 bool writeback = (W == 1) | (P == 0);
3988
3989 addr |= (U << 8) | (Rn << 9);
3990
3991 if (writeback && (Rn == Rt || Rn == Rt2))
3992 Check(S, MCDisassembler::SoftFail);
3993 if (Rt == Rt2)
3994 Check(S, MCDisassembler::SoftFail);
3995
3996 // Rt
3997 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3998 return MCDisassembler::Fail;
3999 // Rt2
4000 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4001 return MCDisassembler::Fail;
4002 // Writeback operand
4003 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4004 return MCDisassembler::Fail;
4005 // addr
4006 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4007 return MCDisassembler::Fail;
4008
4009 return S;
4010}
4011
4012static DecodeStatus
4013DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4014 uint64_t Address, const void *Decoder) {
4015 DecodeStatus S = MCDisassembler::Success;
4016
4017 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4018 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4019 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4020 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4021 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4022 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4023 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4024 bool writeback = (W == 1) | (P == 0);
4025
4026 addr |= (U << 8) | (Rn << 9);
4027
4028 if (writeback && (Rn == Rt || Rn == Rt2))
4029 Check(S, MCDisassembler::SoftFail);
4030
4031 // Writeback operand
4032 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4033 return MCDisassembler::Fail;
4034 // Rt
4035 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4036 return MCDisassembler::Fail;
4037 // Rt2
4038 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4039 return MCDisassembler::Fail;
4040 // addr
4041 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4042 return MCDisassembler::Fail;
4043
4044 return S;
4045}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4046
4047static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4048 uint64_t Address, const void *Decoder) {
4049 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4050 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4051 if (sign1 != sign2) return MCDisassembler::Fail;
4052
4053 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4054 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4055 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4056 Val |= sign1 << 12;
4057 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4058
4059 return MCDisassembler::Success;
4060}
4061
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4062static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4063 uint64_t Address,
4064 const void *Decoder) {
4065 DecodeStatus S = MCDisassembler::Success;
4066
4067 // Shift of "asr #32" is not allowed in Thumb2 mode.
4068 if (Val == 0x20) S = MCDisassembler::SoftFail;
4069 Inst.addOperand(MCOperand::CreateImm(Val));
4070 return S;
4071}
4072