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gerrit-public.fairphone.software / platform / external / llvm / 46ac94ba8b22f1c24100765c4da9d65d7e858410 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
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Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
50 raw_ostream &vStream) const;
51
52 /// getEDInfo - See MCDisassembler.
53 EDInstInfo *getEDInfo() const;
54private:
55};
56
57/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
58class ThumbDisassembler : public MCDisassembler {
59public:
60 /// Constructor - Initializes the disassembler.
61 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]62 ThumbDisassembler(const MCSubtargetInfo &STI) :
63 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]64 }
65
66 ~ThumbDisassembler() {
67 }
68
69 /// getInstruction - See MCDisassembler.
70 DecodeStatus getInstruction(MCInst &instr,
71 uint64_t &size,
72 const MemoryObject &region,
73 uint64_t address,
74 raw_ostream &vStream) const;
75
76 /// getEDInfo - See MCDisassembler.
77 EDInstInfo *getEDInfo() const;
78private:
79 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]80 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]81 void UpdateThumbVFPPredicate(MCInst&) const;
82};
83}
84
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]85static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]86 switch (In) {
87 case MCDisassembler::Success:
88 // Out stays the same.
89 return true;
90 case MCDisassembler::SoftFail:
91 Out = In;
92 return true;
93 case MCDisassembler::Fail:
94 Out = In;
95 return false;
96 }
97 return false;
98}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]99
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]100
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]101// Forward declare these because the autogenerated code will reference them.
102// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]103static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]106 unsigned RegNo, uint64_t Address,
107 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]109 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]121 unsigned RegNo,
122 uint64_t Address,
123 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]124static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]125 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]126
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]139
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]145 unsigned Insn,
146 uint64_t Address,
147 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]148static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]149 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
156
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 unsigned Insn,
159 uint64_t Adddress,
160 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]161static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
273 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]274static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]290static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]298static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
299 uint64_t Address, const void *Decoder);
300static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
301 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302
303#include "ARMGenDisassemblerTables.inc"
304#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]305#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]306
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]307static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
308 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]309}
310
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]311static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
312 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]313}
314
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]315EDInstInfo *ARMDisassembler::getEDInfo() const {
316 return instInfoARM;
317}
318
319EDInstInfo *ThumbDisassembler::getEDInfo() const {
320 return instInfoARM;
321}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]322
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]323DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]324 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]325 uint64_t Address,
326 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327 uint8_t bytes[4];
328
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]329 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
330 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
331
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]332 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]333 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
334 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]335 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]336 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337
338 // Encoded as a small-endian 32-bit word in the stream.
339 uint32_t insn = (bytes[3] << 24) |
340 (bytes[2] << 16) |
341 (bytes[1] << 8) |
342 (bytes[0] << 0);
343
344 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]345 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]346 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]348 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]349 }
350
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]351 // VFP and NEON instructions, similarly, are shared between ARM
352 // and Thumb modes.
353 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]354 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]355 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]356 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]357 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]358 }
359
360 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]361 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]362 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]363 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]364 // Add a fake predicate operand, because we share these instruction
365 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]366 if (!DecodePredicateOperand(MI, 0xE, Address, this))
367 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]368 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]369 }
370
371 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]372 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]375 // Add a fake predicate operand, because we share these instruction
376 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]377 if (!DecodePredicateOperand(MI, 0xE, Address, this))
378 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]379 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]380 }
381
382 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]383 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]384 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]385 Size = 4;
386 // Add a fake predicate operand, because we share these instruction
387 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]388 if (!DecodePredicateOperand(MI, 0xE, Address, this))
389 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]390 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]391 }
392
393 MI.clear();
394
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]395 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]396 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]397}
398
399namespace llvm {
400extern MCInstrDesc ARMInsts[];
401}
402
403// Thumb1 instructions don't have explicit S bits. Rather, they
404// implicitly set CPSR. Since it's not represented in the encoding, the
405// auto-generated decoder won't inject the CPSR operand. We need to fix
406// that as a post-pass.
407static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
408 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]409 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]410 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]411 for (unsigned i = 0; i < NumOps; ++i, ++I) {
412 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]413 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]414 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
416 return;
417 }
418 }
419
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]420 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]421}
422
423// Most Thumb instructions don't have explicit predicates in the
424// encoding, but rather get their predicates from IT context. We need
425// to fix up the predicate operands using this context information as a
426// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]427MCDisassembler::DecodeStatus
428ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]429 MCDisassembler::DecodeStatus S = Success;
430
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]431 // A few instructions actually have predicates encoded in them. Don't
432 // try to overwrite it if we're seeing one of those.
433 switch (MI.getOpcode()) {
434 case ARM::tBcc:
435 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]436 case ARM::tCBZ:
437 case ARM::tCBNZ:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]438 // Some instructions (mostly conditional branches) are not
439 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]440 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]441 S = SoftFail;
442 else
443 return Success;
444 break;
445 case ARM::tB:
446 case ARM::t2B:
447 // Some instructions (mostly unconditional branches) can
448 // only appears at the end of, or outside of, an IT.
449 if (ITBlock.size() > 1)
450 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]451 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]452 default:
453 break;
454 }
455
456 // If we're in an IT block, base the predicate on that. Otherwise,
457 // assume a predicate of AL.
458 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]459 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]460 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]461 if (CC == 0xF)
462 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]463 ITBlock.pop_back();
464 } else
465 CC = ARMCC::AL;
466
467 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]468 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]469 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]470 for (unsigned i = 0; i < NumOps; ++i, ++I) {
471 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]472 if (OpInfo[i].isPredicate()) {
473 I = MI.insert(I, MCOperand::CreateImm(CC));
474 ++I;
475 if (CC == ARMCC::AL)
476 MI.insert(I, MCOperand::CreateReg(0));
477 else
478 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]479 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]480 }
481 }
482
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]483 I = MI.insert(I, MCOperand::CreateImm(CC));
484 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]485 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]486 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]487 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]488 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]489
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]490 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]491}
492
493// Thumb VFP instructions are a special case. Because we share their
494// encodings between ARM and Thumb modes, and they are predicable in ARM
495// mode, the auto-generated decoder will give them an (incorrect)
496// predicate operand. We need to rewrite these operands based on the IT
497// context as a post-pass.
498void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
499 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]500 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]501 CC = ITBlock.back();
502 ITBlock.pop_back();
503 } else
504 CC = ARMCC::AL;
505
506 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
507 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]508 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
509 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]510 if (OpInfo[i].isPredicate() ) {
511 I->setImm(CC);
512 ++I;
513 if (CC == ARMCC::AL)
514 I->setReg(0);
515 else
516 I->setReg(ARM::CPSR);
517 return;
518 }
519 }
520}
521
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]522DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]523 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]524 uint64_t Address,
525 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]526 uint8_t bytes[4];
527
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]528 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
529 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
530
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]531 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]532 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
533 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]534 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]535 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]536
537 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]538 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]539 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]540 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]541 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]542 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]543 }
544
545 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]546 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]547 if (result) {
548 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]549 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]550 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]551 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]552 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]553 }
554
555 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]556 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]557 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]558 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]559 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]560
561 // If we find an IT instruction, we need to parse its condition
562 // code and mask operands so that we can apply them correctly
563 // to the subsequent instructions.
564 if (MI.getOpcode() == ARM::t2IT) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]565 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]566 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]567 unsigned Mask = MI.getOperand(1).getImm();
568 unsigned CondBit0 = Mask >> 4 & 1;
569 unsigned NumTZ = CountTrailingZeros_32(Mask);
570 assert(NumTZ <= 3 && "Invalid IT mask!");
571 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
572 bool T = ((Mask >> Pos) & 1) == CondBit0;
573 if (T)
574 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]575 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]576 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]577 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]578
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579 ITBlock.push_back(firstcond);
580 }
581
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]582 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]583 }
584
585 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]586 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
587 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]588 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]589 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]590
591 uint32_t insn32 = (bytes[3] << 8) |
592 (bytes[2] << 0) |
593 (bytes[1] << 24) |
594 (bytes[0] << 16);
595 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]596 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]597 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]598 Size = 4;
599 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]600 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]601 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]602 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]603 }
604
605 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]606 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]607 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]608 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]609 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]610 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]611 }
612
613 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]614 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]615 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]616 Size = 4;
617 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]618 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]619 }
620
621 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]622 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]623 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]624 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]625 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]626 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]627 }
628
629 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
630 MI.clear();
631 uint32_t NEONLdStInsn = insn32;
632 NEONLdStInsn &= 0xF0FFFFFF;
633 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]634 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]635 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]636 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]637 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]638 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]639 }
640 }
641
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]642 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]643 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]644 uint32_t NEONDataInsn = insn32;
645 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
646 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
647 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]648 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]649 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]650 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]651 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]652 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]653 }
654 }
655
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]656 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]657 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]658}
659
660
661extern "C" void LLVMInitializeARMDisassembler() {
662 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
663 createARMDisassembler);
664 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
665 createThumbDisassembler);
666}
667
668static const unsigned GPRDecoderTable[] = {
669 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
670 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
671 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
672 ARM::R12, ARM::SP, ARM::LR, ARM::PC
673};
674
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]675static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]676 uint64_t Address, const void *Decoder) {
677 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]678 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]679
680 unsigned Register = GPRDecoderTable[RegNo];
681 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]682 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]683}
684
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]685static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]686DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
687 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]688 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]689 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
690}
691
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]692static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]693 uint64_t Address, const void *Decoder) {
694 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]695 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]696 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
697}
698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]699static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]700 uint64_t Address, const void *Decoder) {
701 unsigned Register = 0;
702 switch (RegNo) {
703 case 0:
704 Register = ARM::R0;
705 break;
706 case 1:
707 Register = ARM::R1;
708 break;
709 case 2:
710 Register = ARM::R2;
711 break;
712 case 3:
713 Register = ARM::R3;
714 break;
715 case 9:
716 Register = ARM::R9;
717 break;
718 case 12:
719 Register = ARM::R12;
720 break;
721 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]722 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]723 }
724
725 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]726 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]727}
728
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]729static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]730 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]731 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]732 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
733}
734
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]735static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]736 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
737 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
738 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
739 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
740 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
741 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
742 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
743 ARM::S28, ARM::S29, ARM::S30, ARM::S31
744};
745
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]746static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]747 uint64_t Address, const void *Decoder) {
748 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]749 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]750
751 unsigned Register = SPRDecoderTable[RegNo];
752 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]753 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]754}
755
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]756static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]757 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
758 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
759 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
760 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
761 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
762 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
763 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
764 ARM::D28, ARM::D29, ARM::D30, ARM::D31
765};
766
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]767static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]768 uint64_t Address, const void *Decoder) {
769 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]770 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]771
772 unsigned Register = DPRDecoderTable[RegNo];
773 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]774 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]775}
776
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]777static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]778 uint64_t Address, const void *Decoder) {
779 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]780 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]781 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
782}
783
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]784static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]785DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
786 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]787 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]788 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]789 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
790}
791
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]792static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]793 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
794 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
795 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
796 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
797};
798
799
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]800static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]801 uint64_t Address, const void *Decoder) {
802 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]803 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]804 RegNo >>= 1;
805
806 unsigned Register = QPRDecoderTable[RegNo];
807 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]808 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]809}
810
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]811static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]812 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]813 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]814 // AL predicate is not allowed on Thumb1 branches.
815 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]816 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]817 Inst.addOperand(MCOperand::CreateImm(Val));
818 if (Val == ARMCC::AL) {
819 Inst.addOperand(MCOperand::CreateReg(0));
820 } else
821 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]822 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]823}
824
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]825static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]826 uint64_t Address, const void *Decoder) {
827 if (Val)
828 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
829 else
830 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]831 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]832}
833
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]834static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]835 uint64_t Address, const void *Decoder) {
836 uint32_t imm = Val & 0xFF;
837 uint32_t rot = (Val & 0xF00) >> 7;
838 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
839 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]840 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]841}
842
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]843static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]844 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]845 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]846
847 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
848 unsigned type = fieldFromInstruction32(Val, 5, 2);
849 unsigned imm = fieldFromInstruction32(Val, 7, 5);
850
851 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]852 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
853 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854
855 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
856 switch (type) {
857 case 0:
858 Shift = ARM_AM::lsl;
859 break;
860 case 1:
861 Shift = ARM_AM::lsr;
862 break;
863 case 2:
864 Shift = ARM_AM::asr;
865 break;
866 case 3:
867 Shift = ARM_AM::ror;
868 break;
869 }
870
871 if (Shift == ARM_AM::ror && imm == 0)
872 Shift = ARM_AM::rrx;
873
874 unsigned Op = Shift | (imm << 3);
875 Inst.addOperand(MCOperand::CreateImm(Op));
876
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]877 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]878}
879
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]880static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]881 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]882 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]883
884 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
885 unsigned type = fieldFromInstruction32(Val, 5, 2);
886 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
887
888 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]889 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
890 return MCDisassembler::Fail;
891 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
892 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]893
894 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
895 switch (type) {
896 case 0:
897 Shift = ARM_AM::lsl;
898 break;
899 case 1:
900 Shift = ARM_AM::lsr;
901 break;
902 case 2:
903 Shift = ARM_AM::asr;
904 break;
905 case 3:
906 Shift = ARM_AM::ror;
907 break;
908 }
909
910 Inst.addOperand(MCOperand::CreateImm(Shift));
911
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]912 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]913}
914
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]915static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]916 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]917 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]918
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]919 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]920 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]921 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]922 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]923 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
924 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]925 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]926 }
927
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]928 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929}
930
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]931static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]932 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]933 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]934
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]935 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
936 unsigned regs = Val & 0xFF;
937
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]938 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
939 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]940 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]941 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
942 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]943 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]944
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]945 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946}
947
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]948static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]949 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]950 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]951
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]952 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
953 unsigned regs = (Val & 0xFF) / 2;
954
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]955 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
956 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]957 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]958 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
959 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]960 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]961
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]962 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963}
964
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]965static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]966 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]967 // This operand encodes a mask of contiguous zeros between a specified MSB
968 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
969 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]970 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]971 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]972 unsigned msb = fieldFromInstruction32(Val, 5, 5);
973 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
974 uint32_t msb_mask = (1 << (msb+1)) - 1;
975 uint32_t lsb_mask = (1 << lsb) - 1;
976 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]977 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978}
979
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]980static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]981 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]982 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]983
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
985 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
986 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
987 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
988 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
989 unsigned U = fieldFromInstruction32(Insn, 23, 1);
990
991 switch (Inst.getOpcode()) {
992 case ARM::LDC_OFFSET:
993 case ARM::LDC_PRE:
994 case ARM::LDC_POST:
995 case ARM::LDC_OPTION:
996 case ARM::LDCL_OFFSET:
997 case ARM::LDCL_PRE:
998 case ARM::LDCL_POST:
999 case ARM::LDCL_OPTION:
1000 case ARM::STC_OFFSET:
1001 case ARM::STC_PRE:
1002 case ARM::STC_POST:
1003 case ARM::STC_OPTION:
1004 case ARM::STCL_OFFSET:
1005 case ARM::STCL_PRE:
1006 case ARM::STCL_POST:
1007 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1008 case ARM::t2LDC_OFFSET:
1009 case ARM::t2LDC_PRE:
1010 case ARM::t2LDC_POST:
1011 case ARM::t2LDC_OPTION:
1012 case ARM::t2LDCL_OFFSET:
1013 case ARM::t2LDCL_PRE:
1014 case ARM::t2LDCL_POST:
1015 case ARM::t2LDCL_OPTION:
1016 case ARM::t2STC_OFFSET:
1017 case ARM::t2STC_PRE:
1018 case ARM::t2STC_POST:
1019 case ARM::t2STC_OPTION:
1020 case ARM::t2STCL_OFFSET:
1021 case ARM::t2STCL_PRE:
1022 case ARM::t2STCL_POST:
1023 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1025 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1026 break;
1027 default:
1028 break;
1029 }
1030
1031 Inst.addOperand(MCOperand::CreateImm(coproc));
1032 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1034 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1035 switch (Inst.getOpcode()) {
1036 case ARM::LDC_OPTION:
1037 case ARM::LDCL_OPTION:
1038 case ARM::LDC2_OPTION:
1039 case ARM::LDC2L_OPTION:
1040 case ARM::STC_OPTION:
1041 case ARM::STCL_OPTION:
1042 case ARM::STC2_OPTION:
1043 case ARM::STC2L_OPTION:
1044 case ARM::LDCL_POST:
1045 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1046 case ARM::LDC2L_POST:
1047 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1048 case ARM::t2LDC_OPTION:
1049 case ARM::t2LDCL_OPTION:
1050 case ARM::t2STC_OPTION:
1051 case ARM::t2STCL_OPTION:
1052 case ARM::t2LDCL_POST:
1053 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1054 break;
1055 default:
1056 Inst.addOperand(MCOperand::CreateReg(0));
1057 break;
1058 }
1059
1060 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1061 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1062
1063 bool writeback = (P == 0) || (W == 1);
1064 unsigned idx_mode = 0;
1065 if (P && writeback)
1066 idx_mode = ARMII::IndexModePre;
1067 else if (!P && writeback)
1068 idx_mode = ARMII::IndexModePost;
1069
1070 switch (Inst.getOpcode()) {
1071 case ARM::LDCL_POST:
1072 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1073 case ARM::t2LDCL_POST:
1074 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1075 case ARM::LDC2L_POST:
1076 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1077 imm |= U << 8;
1078 case ARM::LDC_OPTION:
1079 case ARM::LDCL_OPTION:
1080 case ARM::LDC2_OPTION:
1081 case ARM::LDC2L_OPTION:
1082 case ARM::STC_OPTION:
1083 case ARM::STCL_OPTION:
1084 case ARM::STC2_OPTION:
1085 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1086 case ARM::t2LDC_OPTION:
1087 case ARM::t2LDCL_OPTION:
1088 case ARM::t2STC_OPTION:
1089 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1090 Inst.addOperand(MCOperand::CreateImm(imm));
1091 break;
1092 default:
1093 if (U)
1094 Inst.addOperand(MCOperand::CreateImm(
1095 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1096 else
1097 Inst.addOperand(MCOperand::CreateImm(
1098 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1099 break;
1100 }
1101
1102 switch (Inst.getOpcode()) {
1103 case ARM::LDC_OFFSET:
1104 case ARM::LDC_PRE:
1105 case ARM::LDC_POST:
1106 case ARM::LDC_OPTION:
1107 case ARM::LDCL_OFFSET:
1108 case ARM::LDCL_PRE:
1109 case ARM::LDCL_POST:
1110 case ARM::LDCL_OPTION:
1111 case ARM::STC_OFFSET:
1112 case ARM::STC_PRE:
1113 case ARM::STC_POST:
1114 case ARM::STC_OPTION:
1115 case ARM::STCL_OFFSET:
1116 case ARM::STCL_PRE:
1117 case ARM::STCL_POST:
1118 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1119 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1120 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1121 break;
1122 default:
1123 break;
1124 }
1125
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1126 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1127}
1128
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1129static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1130DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1131 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1132 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1133
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1134 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1135 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1136 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1137 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1138 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1139 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1140 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1141 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1142
1143 // On stores, the writeback operand precedes Rt.
1144 switch (Inst.getOpcode()) {
1145 case ARM::STR_POST_IMM:
1146 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1147 case ARM::STRB_POST_IMM:
1148 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1149 case ARM::STRT_POST_REG:
1150 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1151 case ARM::STRBT_POST_REG:
1152 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1153 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1154 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1155 break;
1156 default:
1157 break;
1158 }
1159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1160 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1161 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1162
1163 // On loads, the writeback operand comes after Rt.
1164 switch (Inst.getOpcode()) {
1165 case ARM::LDR_POST_IMM:
1166 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1167 case ARM::LDRB_POST_IMM:
1168 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1169 case ARM::LDRBT_POST_REG:
1170 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1171 case ARM::LDRT_POST_REG:
1172 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1174 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1175 break;
1176 default:
1177 break;
1178 }
1179
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1181 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1182
1183 ARM_AM::AddrOpc Op = ARM_AM::add;
1184 if (!fieldFromInstruction32(Insn, 23, 1))
1185 Op = ARM_AM::sub;
1186
1187 bool writeback = (P == 0) || (W == 1);
1188 unsigned idx_mode = 0;
1189 if (P && writeback)
1190 idx_mode = ARMII::IndexModePre;
1191 else if (!P && writeback)
1192 idx_mode = ARMII::IndexModePost;
1193
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1194 if (writeback && (Rn == 15 || Rn == Rt))
1195 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1196
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1197 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1198 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1199 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1200 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1201 switch( fieldFromInstruction32(Insn, 5, 2)) {
1202 case 0:
1203 Opc = ARM_AM::lsl;
1204 break;
1205 case 1:
1206 Opc = ARM_AM::lsr;
1207 break;
1208 case 2:
1209 Opc = ARM_AM::asr;
1210 break;
1211 case 3:
1212 Opc = ARM_AM::ror;
1213 break;
1214 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1215 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1216 }
1217 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1218 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1219
1220 Inst.addOperand(MCOperand::CreateImm(imm));
1221 } else {
1222 Inst.addOperand(MCOperand::CreateReg(0));
1223 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1224 Inst.addOperand(MCOperand::CreateImm(tmp));
1225 }
1226
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1227 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1228 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1229
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1230 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1231}
1232
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1234 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1235 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1236
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1237 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1238 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1239 unsigned type = fieldFromInstruction32(Val, 5, 2);
1240 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1241 unsigned U = fieldFromInstruction32(Val, 12, 1);
1242
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1243 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1244 switch (type) {
1245 case 0:
1246 ShOp = ARM_AM::lsl;
1247 break;
1248 case 1:
1249 ShOp = ARM_AM::lsr;
1250 break;
1251 case 2:
1252 ShOp = ARM_AM::asr;
1253 break;
1254 case 3:
1255 ShOp = ARM_AM::ror;
1256 break;
1257 }
1258
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1260 return MCDisassembler::Fail;
1261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1262 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1263 unsigned shift;
1264 if (U)
1265 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1266 else
1267 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1268 Inst.addOperand(MCOperand::CreateImm(shift));
1269
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1270 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1271}
1272
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1273static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1274DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1275 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1276 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1277
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1278 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1279 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1280 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1281 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1282 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1283 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1284 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1285 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1286 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1287
1288 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1289
1290 // For {LD,ST}RD, Rt must be even, else undefined.
1291 switch (Inst.getOpcode()) {
1292 case ARM::STRD:
1293 case ARM::STRD_PRE:
1294 case ARM::STRD_POST:
1295 case ARM::LDRD:
1296 case ARM::LDRD_PRE:
1297 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1298 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1299 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1300 default:
1301 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1302 }
1303
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1304 if (writeback) { // Writeback
1305 if (P)
1306 U |= ARMII::IndexModePre << 9;
1307 else
1308 U |= ARMII::IndexModePost << 9;
1309
1310 // On stores, the writeback operand precedes Rt.
1311 switch (Inst.getOpcode()) {
1312 case ARM::STRD:
1313 case ARM::STRD_PRE:
1314 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1315 case ARM::STRH:
1316 case ARM::STRH_PRE:
1317 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1319 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1320 break;
1321 default:
1322 break;
1323 }
1324 }
1325
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1327 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1328 switch (Inst.getOpcode()) {
1329 case ARM::STRD:
1330 case ARM::STRD_PRE:
1331 case ARM::STRD_POST:
1332 case ARM::LDRD:
1333 case ARM::LDRD_PRE:
1334 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1336 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1337 break;
1338 default:
1339 break;
1340 }
1341
1342 if (writeback) {
1343 // On loads, the writeback operand comes after Rt.
1344 switch (Inst.getOpcode()) {
1345 case ARM::LDRD:
1346 case ARM::LDRD_PRE:
1347 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1348 case ARM::LDRH:
1349 case ARM::LDRH_PRE:
1350 case ARM::LDRH_POST:
1351 case ARM::LDRSH:
1352 case ARM::LDRSH_PRE:
1353 case ARM::LDRSH_POST:
1354 case ARM::LDRSB:
1355 case ARM::LDRSB_PRE:
1356 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1357 case ARM::LDRHTr:
1358 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1360 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1361 break;
1362 default:
1363 break;
1364 }
1365 }
1366
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1368 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1369
1370 if (type) {
1371 Inst.addOperand(MCOperand::CreateReg(0));
1372 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1373 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1375 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1376 Inst.addOperand(MCOperand::CreateImm(U));
1377 }
1378
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1379 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1380 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1381
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1382 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1383}
1384
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1385static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1386 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1387 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1388
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1389 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1390 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1391
1392 switch (mode) {
1393 case 0:
1394 mode = ARM_AM::da;
1395 break;
1396 case 1:
1397 mode = ARM_AM::ia;
1398 break;
1399 case 2:
1400 mode = ARM_AM::db;
1401 break;
1402 case 3:
1403 mode = ARM_AM::ib;
1404 break;
1405 }
1406
1407 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1409 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1410
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1411 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1412}
1413
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1414static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1415 unsigned Insn,
1416 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1417 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1418
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1419 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1420 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1421 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1422
1423 if (pred == 0xF) {
1424 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1425 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1426 Inst.setOpcode(ARM::RFEDA);
1427 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1428 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1429 Inst.setOpcode(ARM::RFEDA_UPD);
1430 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1431 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1432 Inst.setOpcode(ARM::RFEDB);
1433 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1434 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1435 Inst.setOpcode(ARM::RFEDB_UPD);
1436 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1437 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1438 Inst.setOpcode(ARM::RFEIA);
1439 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1440 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1441 Inst.setOpcode(ARM::RFEIA_UPD);
1442 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1443 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1444 Inst.setOpcode(ARM::RFEIB);
1445 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1446 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1447 Inst.setOpcode(ARM::RFEIB_UPD);
1448 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1449 case ARM::STMDA:
1450 Inst.setOpcode(ARM::SRSDA);
1451 break;
1452 case ARM::STMDA_UPD:
1453 Inst.setOpcode(ARM::SRSDA_UPD);
1454 break;
1455 case ARM::STMDB:
1456 Inst.setOpcode(ARM::SRSDB);
1457 break;
1458 case ARM::STMDB_UPD:
1459 Inst.setOpcode(ARM::SRSDB_UPD);
1460 break;
1461 case ARM::STMIA:
1462 Inst.setOpcode(ARM::SRSIA);
1463 break;
1464 case ARM::STMIA_UPD:
1465 Inst.setOpcode(ARM::SRSIA_UPD);
1466 break;
1467 case ARM::STMIB:
1468 Inst.setOpcode(ARM::SRSIB);
1469 break;
1470 case ARM::STMIB_UPD:
1471 Inst.setOpcode(ARM::SRSIB_UPD);
1472 break;
1473 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1474 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1475 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1476
1477 // For stores (which become SRS's, the only operand is the mode.
1478 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1479 Inst.addOperand(
1480 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1481 return S;
1482 }
1483
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1484 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1485 }
1486
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1488 return MCDisassembler::Fail;
1489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1490 return MCDisassembler::Fail; // Tied
1491 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1492 return MCDisassembler::Fail;
1493 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1494 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1495
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1496 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1497}
1498
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1499static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1500 uint64_t Address, const void *Decoder) {
1501 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1502 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1503 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1504 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1505
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1506 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1507
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1508 // imod == '01' --> UNPREDICTABLE
1509 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1510 // return failure here. The '01' imod value is unprintable, so there's
1511 // nothing useful we could do even if we returned UNPREDICTABLE.
1512
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1513 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1514
1515 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1516 Inst.setOpcode(ARM::CPS3p);
1517 Inst.addOperand(MCOperand::CreateImm(imod));
1518 Inst.addOperand(MCOperand::CreateImm(iflags));
1519 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1520 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1521 Inst.setOpcode(ARM::CPS2p);
1522 Inst.addOperand(MCOperand::CreateImm(imod));
1523 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1524 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1525 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1526 Inst.setOpcode(ARM::CPS1p);
1527 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1528 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1529 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1530 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1531 Inst.setOpcode(ARM::CPS1p);
1532 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1533 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1534 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1535
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1536 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1537}
1538
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1539static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1540 uint64_t Address, const void *Decoder) {
1541 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1542 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1543 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1544 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1545
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1546 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1547
1548 // imod == '01' --> UNPREDICTABLE
1549 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1550 // return failure here. The '01' imod value is unprintable, so there's
1551 // nothing useful we could do even if we returned UNPREDICTABLE.
1552
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1553 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1554
1555 if (imod && M) {
1556 Inst.setOpcode(ARM::t2CPS3p);
1557 Inst.addOperand(MCOperand::CreateImm(imod));
1558 Inst.addOperand(MCOperand::CreateImm(iflags));
1559 Inst.addOperand(MCOperand::CreateImm(mode));
1560 } else if (imod && !M) {
1561 Inst.setOpcode(ARM::t2CPS2p);
1562 Inst.addOperand(MCOperand::CreateImm(imod));
1563 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1564 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1565 } else if (!imod && M) {
1566 Inst.setOpcode(ARM::t2CPS1p);
1567 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1568 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1569 } else {
1570 // imod == '00' && M == '0' --> UNPREDICTABLE
1571 Inst.setOpcode(ARM::t2CPS1p);
1572 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1573 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1574 }
1575
1576 return S;
1577}
1578
1579
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1580static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1581 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1582 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1583
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1584 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1585 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1586 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1587 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1588 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1589
1590 if (pred == 0xF)
1591 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1592
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1593 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1594 return MCDisassembler::Fail;
1595 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1596 return MCDisassembler::Fail;
1597 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1598 return MCDisassembler::Fail;
1599 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1600 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1601
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1602 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1603 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1604
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1605 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1606}
1607
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1608static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1609 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1610 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1611
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1612 unsigned add = fieldFromInstruction32(Val, 12, 1);
1613 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1614 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1615
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1617 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1618
1619 if (!add) imm *= -1;
1620 if (imm == 0 && !add) imm = INT32_MIN;
1621 Inst.addOperand(MCOperand::CreateImm(imm));
1622
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1623 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1624}
1625
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1626static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1627 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1628 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1629
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1630 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1631 unsigned U = fieldFromInstruction32(Val, 8, 1);
1632 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1633
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1635 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1636
1637 if (U)
1638 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1639 else
1640 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1641
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1642 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1643}
1644
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1645static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1646 uint64_t Address, const void *Decoder) {
1647 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1648}
1649
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1650static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1651DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1652 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1653 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1654
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1655 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1656 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1657
1658 if (pred == 0xF) {
1659 Inst.setOpcode(ARM::BLXi);
1660 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1661 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1662 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1663 }
1664
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1665 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1666 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1667 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1668
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1669 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1670}
1671
1672
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1673static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1674 uint64_t Address, const void *Decoder) {
1675 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1676 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1677}
1678
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1679static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1680 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1681 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1682
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1683 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1684 unsigned align = fieldFromInstruction32(Val, 4, 2);
1685
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1687 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1688 if (!align)
1689 Inst.addOperand(MCOperand::CreateImm(0));
1690 else
1691 Inst.addOperand(MCOperand::CreateImm(4 << align));
1692
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1693 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1694}
1695
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1696static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1697 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1698 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1699
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1700 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1701 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1702 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1703 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1704 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1705 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1706
1707 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1709 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1710
1711 // Second output register
1712 switch (Inst.getOpcode()) {
1713 case ARM::VLD1q8:
1714 case ARM::VLD1q16:
1715 case ARM::VLD1q32:
1716 case ARM::VLD1q64:
1717 case ARM::VLD1q8_UPD:
1718 case ARM::VLD1q16_UPD:
1719 case ARM::VLD1q32_UPD:
1720 case ARM::VLD1q64_UPD:
1721 case ARM::VLD1d8T:
1722 case ARM::VLD1d16T:
1723 case ARM::VLD1d32T:
1724 case ARM::VLD1d64T:
1725 case ARM::VLD1d8T_UPD:
1726 case ARM::VLD1d16T_UPD:
1727 case ARM::VLD1d32T_UPD:
1728 case ARM::VLD1d64T_UPD:
1729 case ARM::VLD1d8Q:
1730 case ARM::VLD1d16Q:
1731 case ARM::VLD1d32Q:
1732 case ARM::VLD1d64Q:
1733 case ARM::VLD1d8Q_UPD:
1734 case ARM::VLD1d16Q_UPD:
1735 case ARM::VLD1d32Q_UPD:
1736 case ARM::VLD1d64Q_UPD:
1737 case ARM::VLD2d8:
1738 case ARM::VLD2d16:
1739 case ARM::VLD2d32:
1740 case ARM::VLD2d8_UPD:
1741 case ARM::VLD2d16_UPD:
1742 case ARM::VLD2d32_UPD:
1743 case ARM::VLD2q8:
1744 case ARM::VLD2q16:
1745 case ARM::VLD2q32:
1746 case ARM::VLD2q8_UPD:
1747 case ARM::VLD2q16_UPD:
1748 case ARM::VLD2q32_UPD:
1749 case ARM::VLD3d8:
1750 case ARM::VLD3d16:
1751 case ARM::VLD3d32:
1752 case ARM::VLD3d8_UPD:
1753 case ARM::VLD3d16_UPD:
1754 case ARM::VLD3d32_UPD:
1755 case ARM::VLD4d8:
1756 case ARM::VLD4d16:
1757 case ARM::VLD4d32:
1758 case ARM::VLD4d8_UPD:
1759 case ARM::VLD4d16_UPD:
1760 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1761 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1762 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1763 break;
1764 case ARM::VLD2b8:
1765 case ARM::VLD2b16:
1766 case ARM::VLD2b32:
1767 case ARM::VLD2b8_UPD:
1768 case ARM::VLD2b16_UPD:
1769 case ARM::VLD2b32_UPD:
1770 case ARM::VLD3q8:
1771 case ARM::VLD3q16:
1772 case ARM::VLD3q32:
1773 case ARM::VLD3q8_UPD:
1774 case ARM::VLD3q16_UPD:
1775 case ARM::VLD3q32_UPD:
1776 case ARM::VLD4q8:
1777 case ARM::VLD4q16:
1778 case ARM::VLD4q32:
1779 case ARM::VLD4q8_UPD:
1780 case ARM::VLD4q16_UPD:
1781 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1782 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1783 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1784 default:
1785 break;
1786 }
1787
1788 // Third output register
1789 switch(Inst.getOpcode()) {
1790 case ARM::VLD1d8T:
1791 case ARM::VLD1d16T:
1792 case ARM::VLD1d32T:
1793 case ARM::VLD1d64T:
1794 case ARM::VLD1d8T_UPD:
1795 case ARM::VLD1d16T_UPD:
1796 case ARM::VLD1d32T_UPD:
1797 case ARM::VLD1d64T_UPD:
1798 case ARM::VLD1d8Q:
1799 case ARM::VLD1d16Q:
1800 case ARM::VLD1d32Q:
1801 case ARM::VLD1d64Q:
1802 case ARM::VLD1d8Q_UPD:
1803 case ARM::VLD1d16Q_UPD:
1804 case ARM::VLD1d32Q_UPD:
1805 case ARM::VLD1d64Q_UPD:
1806 case ARM::VLD2q8:
1807 case ARM::VLD2q16:
1808 case ARM::VLD2q32:
1809 case ARM::VLD2q8_UPD:
1810 case ARM::VLD2q16_UPD:
1811 case ARM::VLD2q32_UPD:
1812 case ARM::VLD3d8:
1813 case ARM::VLD3d16:
1814 case ARM::VLD3d32:
1815 case ARM::VLD3d8_UPD:
1816 case ARM::VLD3d16_UPD:
1817 case ARM::VLD3d32_UPD:
1818 case ARM::VLD4d8:
1819 case ARM::VLD4d16:
1820 case ARM::VLD4d32:
1821 case ARM::VLD4d8_UPD:
1822 case ARM::VLD4d16_UPD:
1823 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1824 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1825 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1826 break;
1827 case ARM::VLD3q8:
1828 case ARM::VLD3q16:
1829 case ARM::VLD3q32:
1830 case ARM::VLD3q8_UPD:
1831 case ARM::VLD3q16_UPD:
1832 case ARM::VLD3q32_UPD:
1833 case ARM::VLD4q8:
1834 case ARM::VLD4q16:
1835 case ARM::VLD4q32:
1836 case ARM::VLD4q8_UPD:
1837 case ARM::VLD4q16_UPD:
1838 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1839 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1840 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1841 break;
1842 default:
1843 break;
1844 }
1845
1846 // Fourth output register
1847 switch (Inst.getOpcode()) {
1848 case ARM::VLD1d8Q:
1849 case ARM::VLD1d16Q:
1850 case ARM::VLD1d32Q:
1851 case ARM::VLD1d64Q:
1852 case ARM::VLD1d8Q_UPD:
1853 case ARM::VLD1d16Q_UPD:
1854 case ARM::VLD1d32Q_UPD:
1855 case ARM::VLD1d64Q_UPD:
1856 case ARM::VLD2q8:
1857 case ARM::VLD2q16:
1858 case ARM::VLD2q32:
1859 case ARM::VLD2q8_UPD:
1860 case ARM::VLD2q16_UPD:
1861 case ARM::VLD2q32_UPD:
1862 case ARM::VLD4d8:
1863 case ARM::VLD4d16:
1864 case ARM::VLD4d32:
1865 case ARM::VLD4d8_UPD:
1866 case ARM::VLD4d16_UPD:
1867 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1868 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1869 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1870 break;
1871 case ARM::VLD4q8:
1872 case ARM::VLD4q16:
1873 case ARM::VLD4q32:
1874 case ARM::VLD4q8_UPD:
1875 case ARM::VLD4q16_UPD:
1876 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1877 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1878 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1879 break;
1880 default:
1881 break;
1882 }
1883
1884 // Writeback operand
1885 switch (Inst.getOpcode()) {
1886 case ARM::VLD1d8_UPD:
1887 case ARM::VLD1d16_UPD:
1888 case ARM::VLD1d32_UPD:
1889 case ARM::VLD1d64_UPD:
1890 case ARM::VLD1q8_UPD:
1891 case ARM::VLD1q16_UPD:
1892 case ARM::VLD1q32_UPD:
1893 case ARM::VLD1q64_UPD:
1894 case ARM::VLD1d8T_UPD:
1895 case ARM::VLD1d16T_UPD:
1896 case ARM::VLD1d32T_UPD:
1897 case ARM::VLD1d64T_UPD:
1898 case ARM::VLD1d8Q_UPD:
1899 case ARM::VLD1d16Q_UPD:
1900 case ARM::VLD1d32Q_UPD:
1901 case ARM::VLD1d64Q_UPD:
1902 case ARM::VLD2d8_UPD:
1903 case ARM::VLD2d16_UPD:
1904 case ARM::VLD2d32_UPD:
1905 case ARM::VLD2q8_UPD:
1906 case ARM::VLD2q16_UPD:
1907 case ARM::VLD2q32_UPD:
1908 case ARM::VLD2b8_UPD:
1909 case ARM::VLD2b16_UPD:
1910 case ARM::VLD2b32_UPD:
1911 case ARM::VLD3d8_UPD:
1912 case ARM::VLD3d16_UPD:
1913 case ARM::VLD3d32_UPD:
1914 case ARM::VLD3q8_UPD:
1915 case ARM::VLD3q16_UPD:
1916 case ARM::VLD3q32_UPD:
1917 case ARM::VLD4d8_UPD:
1918 case ARM::VLD4d16_UPD:
1919 case ARM::VLD4d32_UPD:
1920 case ARM::VLD4q8_UPD:
1921 case ARM::VLD4q16_UPD:
1922 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1923 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1924 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1925 break;
1926 default:
1927 break;
1928 }
1929
1930 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1931 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1932 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1933
1934 // AddrMode6 Offset (register)
1935 if (Rm == 0xD)
1936 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1937 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1939 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1940 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1941
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1942 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1943}
1944
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1945static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1946 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1947 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1948
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1949 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1950 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1951 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1952 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1953 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1954 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1955
1956 // Writeback Operand
1957 switch (Inst.getOpcode()) {
1958 case ARM::VST1d8_UPD:
1959 case ARM::VST1d16_UPD:
1960 case ARM::VST1d32_UPD:
1961 case ARM::VST1d64_UPD:
1962 case ARM::VST1q8_UPD:
1963 case ARM::VST1q16_UPD:
1964 case ARM::VST1q32_UPD:
1965 case ARM::VST1q64_UPD:
1966 case ARM::VST1d8T_UPD:
1967 case ARM::VST1d16T_UPD:
1968 case ARM::VST1d32T_UPD:
1969 case ARM::VST1d64T_UPD:
1970 case ARM::VST1d8Q_UPD:
1971 case ARM::VST1d16Q_UPD:
1972 case ARM::VST1d32Q_UPD:
1973 case ARM::VST1d64Q_UPD:
1974 case ARM::VST2d8_UPD:
1975 case ARM::VST2d16_UPD:
1976 case ARM::VST2d32_UPD:
1977 case ARM::VST2q8_UPD:
1978 case ARM::VST2q16_UPD:
1979 case ARM::VST2q32_UPD:
1980 case ARM::VST2b8_UPD:
1981 case ARM::VST2b16_UPD:
1982 case ARM::VST2b32_UPD:
1983 case ARM::VST3d8_UPD:
1984 case ARM::VST3d16_UPD:
1985 case ARM::VST3d32_UPD:
1986 case ARM::VST3q8_UPD:
1987 case ARM::VST3q16_UPD:
1988 case ARM::VST3q32_UPD:
1989 case ARM::VST4d8_UPD:
1990 case ARM::VST4d16_UPD:
1991 case ARM::VST4d32_UPD:
1992 case ARM::VST4q8_UPD:
1993 case ARM::VST4q16_UPD:
1994 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1995 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1996 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1997 break;
1998 default:
1999 break;
2000 }
2001
2002 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2003 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2004 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2005
2006 // AddrMode6 Offset (register)
2007 if (Rm == 0xD)
2008 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2009 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2011 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2012 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2013
2014 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2016 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2017
2018 // Second input register
2019 switch (Inst.getOpcode()) {
2020 case ARM::VST1q8:
2021 case ARM::VST1q16:
2022 case ARM::VST1q32:
2023 case ARM::VST1q64:
2024 case ARM::VST1q8_UPD:
2025 case ARM::VST1q16_UPD:
2026 case ARM::VST1q32_UPD:
2027 case ARM::VST1q64_UPD:
2028 case ARM::VST1d8T:
2029 case ARM::VST1d16T:
2030 case ARM::VST1d32T:
2031 case ARM::VST1d64T:
2032 case ARM::VST1d8T_UPD:
2033 case ARM::VST1d16T_UPD:
2034 case ARM::VST1d32T_UPD:
2035 case ARM::VST1d64T_UPD:
2036 case ARM::VST1d8Q:
2037 case ARM::VST1d16Q:
2038 case ARM::VST1d32Q:
2039 case ARM::VST1d64Q:
2040 case ARM::VST1d8Q_UPD:
2041 case ARM::VST1d16Q_UPD:
2042 case ARM::VST1d32Q_UPD:
2043 case ARM::VST1d64Q_UPD:
2044 case ARM::VST2d8:
2045 case ARM::VST2d16:
2046 case ARM::VST2d32:
2047 case ARM::VST2d8_UPD:
2048 case ARM::VST2d16_UPD:
2049 case ARM::VST2d32_UPD:
2050 case ARM::VST2q8:
2051 case ARM::VST2q16:
2052 case ARM::VST2q32:
2053 case ARM::VST2q8_UPD:
2054 case ARM::VST2q16_UPD:
2055 case ARM::VST2q32_UPD:
2056 case ARM::VST3d8:
2057 case ARM::VST3d16:
2058 case ARM::VST3d32:
2059 case ARM::VST3d8_UPD:
2060 case ARM::VST3d16_UPD:
2061 case ARM::VST3d32_UPD:
2062 case ARM::VST4d8:
2063 case ARM::VST4d16:
2064 case ARM::VST4d32:
2065 case ARM::VST4d8_UPD:
2066 case ARM::VST4d16_UPD:
2067 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2068 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2069 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2070 break;
2071 case ARM::VST2b8:
2072 case ARM::VST2b16:
2073 case ARM::VST2b32:
2074 case ARM::VST2b8_UPD:
2075 case ARM::VST2b16_UPD:
2076 case ARM::VST2b32_UPD:
2077 case ARM::VST3q8:
2078 case ARM::VST3q16:
2079 case ARM::VST3q32:
2080 case ARM::VST3q8_UPD:
2081 case ARM::VST3q16_UPD:
2082 case ARM::VST3q32_UPD:
2083 case ARM::VST4q8:
2084 case ARM::VST4q16:
2085 case ARM::VST4q32:
2086 case ARM::VST4q8_UPD:
2087 case ARM::VST4q16_UPD:
2088 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2089 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2090 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2091 break;
2092 default:
2093 break;
2094 }
2095
2096 // Third input register
2097 switch (Inst.getOpcode()) {
2098 case ARM::VST1d8T:
2099 case ARM::VST1d16T:
2100 case ARM::VST1d32T:
2101 case ARM::VST1d64T:
2102 case ARM::VST1d8T_UPD:
2103 case ARM::VST1d16T_UPD:
2104 case ARM::VST1d32T_UPD:
2105 case ARM::VST1d64T_UPD:
2106 case ARM::VST1d8Q:
2107 case ARM::VST1d16Q:
2108 case ARM::VST1d32Q:
2109 case ARM::VST1d64Q:
2110 case ARM::VST1d8Q_UPD:
2111 case ARM::VST1d16Q_UPD:
2112 case ARM::VST1d32Q_UPD:
2113 case ARM::VST1d64Q_UPD:
2114 case ARM::VST2q8:
2115 case ARM::VST2q16:
2116 case ARM::VST2q32:
2117 case ARM::VST2q8_UPD:
2118 case ARM::VST2q16_UPD:
2119 case ARM::VST2q32_UPD:
2120 case ARM::VST3d8:
2121 case ARM::VST3d16:
2122 case ARM::VST3d32:
2123 case ARM::VST3d8_UPD:
2124 case ARM::VST3d16_UPD:
2125 case ARM::VST3d32_UPD:
2126 case ARM::VST4d8:
2127 case ARM::VST4d16:
2128 case ARM::VST4d32:
2129 case ARM::VST4d8_UPD:
2130 case ARM::VST4d16_UPD:
2131 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2132 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2133 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2134 break;
2135 case ARM::VST3q8:
2136 case ARM::VST3q16:
2137 case ARM::VST3q32:
2138 case ARM::VST3q8_UPD:
2139 case ARM::VST3q16_UPD:
2140 case ARM::VST3q32_UPD:
2141 case ARM::VST4q8:
2142 case ARM::VST4q16:
2143 case ARM::VST4q32:
2144 case ARM::VST4q8_UPD:
2145 case ARM::VST4q16_UPD:
2146 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2147 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2148 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2149 break;
2150 default:
2151 break;
2152 }
2153
2154 // Fourth input register
2155 switch (Inst.getOpcode()) {
2156 case ARM::VST1d8Q:
2157 case ARM::VST1d16Q:
2158 case ARM::VST1d32Q:
2159 case ARM::VST1d64Q:
2160 case ARM::VST1d8Q_UPD:
2161 case ARM::VST1d16Q_UPD:
2162 case ARM::VST1d32Q_UPD:
2163 case ARM::VST1d64Q_UPD:
2164 case ARM::VST2q8:
2165 case ARM::VST2q16:
2166 case ARM::VST2q32:
2167 case ARM::VST2q8_UPD:
2168 case ARM::VST2q16_UPD:
2169 case ARM::VST2q32_UPD:
2170 case ARM::VST4d8:
2171 case ARM::VST4d16:
2172 case ARM::VST4d32:
2173 case ARM::VST4d8_UPD:
2174 case ARM::VST4d16_UPD:
2175 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2176 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2177 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2178 break;
2179 case ARM::VST4q8:
2180 case ARM::VST4q16:
2181 case ARM::VST4q32:
2182 case ARM::VST4q8_UPD:
2183 case ARM::VST4q16_UPD:
2184 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2185 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2186 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2187 break;
2188 default:
2189 break;
2190 }
2191
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2192 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2193}
2194
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2195static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2196 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2197 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2198
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2199 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2200 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2201 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2202 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2203 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2204 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2205 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2206
2207 align *= (1 << size);
2208
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2209 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2210 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2211 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2212 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2213 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2214 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2215 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2217 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2218 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2219
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2221 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2222 Inst.addOperand(MCOperand::CreateImm(align));
2223
2224 if (Rm == 0xD)
2225 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2226 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2228 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2229 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2230
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2231 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2232}
2233
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2234static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2235 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2236 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2237
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2238 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2239 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2240 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2241 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2242 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2243 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2244 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2245 align *= 2*size;
2246
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2247 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2248 return MCDisassembler::Fail;
2249 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2250 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2251 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2252 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2253 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2254 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2255
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2257 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2258 Inst.addOperand(MCOperand::CreateImm(align));
2259
2260 if (Rm == 0xD)
2261 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2262 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2264 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2265 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2266
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2267 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2268}
2269
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2270static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2271 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2272 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2273
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2274 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2275 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2276 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2277 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2278 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2279
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2280 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2281 return MCDisassembler::Fail;
2282 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2283 return MCDisassembler::Fail;
2284 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2285 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2286 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2288 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2289 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2290
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2292 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2293 Inst.addOperand(MCOperand::CreateImm(0));
2294
2295 if (Rm == 0xD)
2296 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2297 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2299 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2300 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2301
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2302 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2303}
2304
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2305static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2306 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2307 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2308
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2309 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2310 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2311 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2312 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2313 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2314 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2315 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2316
2317 if (size == 0x3) {
2318 size = 4;
2319 align = 16;
2320 } else {
2321 if (size == 2) {
2322 size = 1 << size;
2323 align *= 8;
2324 } else {
2325 size = 1 << size;
2326 align *= 4*size;
2327 }
2328 }
2329
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2330 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2331 return MCDisassembler::Fail;
2332 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2333 return MCDisassembler::Fail;
2334 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2335 return MCDisassembler::Fail;
2336 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2337 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2338 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2340 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2341 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2342
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2343 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2344 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2345 Inst.addOperand(MCOperand::CreateImm(align));
2346
2347 if (Rm == 0xD)
2348 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2349 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2351 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2352 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2353
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2354 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2355}
2356
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2357static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2358DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2359 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2360 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2361
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2362 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2363 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2364 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2365 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2366 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2367 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2368 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2369 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2370
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2371 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2372 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2373 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2374 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2375 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2376 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2377 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2378
2379 Inst.addOperand(MCOperand::CreateImm(imm));
2380
2381 switch (Inst.getOpcode()) {
2382 case ARM::VORRiv4i16:
2383 case ARM::VORRiv2i32:
2384 case ARM::VBICiv4i16:
2385 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2386 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2387 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2388 break;
2389 case ARM::VORRiv8i16:
2390 case ARM::VORRiv4i32:
2391 case ARM::VBICiv8i16:
2392 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2393 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2394 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2395 break;
2396 default:
2397 break;
2398 }
2399
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2400 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2401}
2402
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2403static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2404 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2405 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2406
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2407 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2408 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2409 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2410 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2411 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2412
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2413 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2414 return MCDisassembler::Fail;
2415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2416 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2417 Inst.addOperand(MCOperand::CreateImm(8 << size));
2418
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2419 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2420}
2421
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2422static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2423 uint64_t Address, const void *Decoder) {
2424 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2425 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2426}
2427
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2428static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2429 uint64_t Address, const void *Decoder) {
2430 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2431 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2432}
2433
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2434static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2435 uint64_t Address, const void *Decoder) {
2436 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2437 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2438}
2439
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2440static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2441 uint64_t Address, const void *Decoder) {
2442 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2443 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2444}
2445
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2446static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2447 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2448 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2449
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2450 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2451 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2452 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2453 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2454 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2455 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2456 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2457 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2458
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2460 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2461 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2462 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2463 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2464 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2465
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2466 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2467 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2468 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2469 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2470
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2471 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2472 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2473
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2474 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2475}
2476
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2477static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2478 uint64_t Address, const void *Decoder) {
2479 // The immediate needs to be a fully instantiated float. However, the
2480 // auto-generated decoder is only able to fill in some of the bits
2481 // necessary. For instance, the 'b' bit is replicated multiple times,
2482 // and is even present in inverted form in one bit. We do a little
2483 // binary parsing here to fill in those missing bits, and then
2484 // reinterpret it all as a float.
2485 union {
2486 uint32_t integer;
2487 float fp;
2488 } fp_conv;
2489
2490 fp_conv.integer = Val;
2491 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2492 fp_conv.integer |= b << 26;
2493 fp_conv.integer |= b << 27;
2494 fp_conv.integer |= b << 28;
2495 fp_conv.integer |= b << 29;
2496 fp_conv.integer |= (~b & 0x1) << 30;
2497
2498 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2499 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2500}
2501
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2502static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2503 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2504 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2505
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2506 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2507 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2508
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2509 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2510 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2511
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2512 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2513 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2514 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2515 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2516 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2517 case ARM::tADDrSPi:
2518 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2519 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2520 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521
2522 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2523 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524}
2525
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2526static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2527 uint64_t Address, const void *Decoder) {
2528 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2529 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2530}
2531
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2532static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2533 uint64_t Address, const void *Decoder) {
2534 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2535 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2536}
2537
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2538static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2539 uint64_t Address, const void *Decoder) {
2540 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2541 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2542}
2543
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2544static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2545 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2546 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2547
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2548 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2549 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2550
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2551 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2552 return MCDisassembler::Fail;
2553 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2554 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2555
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2556 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2557}
2558
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2559static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2560 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2561 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2562
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2563 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2564 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2565
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2566 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2567 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2568 Inst.addOperand(MCOperand::CreateImm(imm));
2569
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2570 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2571}
2572
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2573static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2574 uint64_t Address, const void *Decoder) {
2575 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2576
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2577 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2578}
2579
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2580static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2581 uint64_t Address, const void *Decoder) {
2582 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2583 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2584
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2585 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2586}
2587
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2588static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2589 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2590 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2591
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2592 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2593 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2594 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2595
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2597 return MCDisassembler::Fail;
2598 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2599 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2600 Inst.addOperand(MCOperand::CreateImm(imm));
2601
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2602 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2603}
2604
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2605static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2607 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2608
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2609 switch (Inst.getOpcode()) {
2610 case ARM::t2PLDs:
2611 case ARM::t2PLDWs:
2612 case ARM::t2PLIs:
2613 break;
2614 default: {
2615 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2617 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2618 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2619 }
2620
2621 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2622 if (Rn == 0xF) {
2623 switch (Inst.getOpcode()) {
2624 case ARM::t2LDRBs:
2625 Inst.setOpcode(ARM::t2LDRBpci);
2626 break;
2627 case ARM::t2LDRHs:
2628 Inst.setOpcode(ARM::t2LDRHpci);
2629 break;
2630 case ARM::t2LDRSHs:
2631 Inst.setOpcode(ARM::t2LDRSHpci);
2632 break;
2633 case ARM::t2LDRSBs:
2634 Inst.setOpcode(ARM::t2LDRSBpci);
2635 break;
2636 case ARM::t2PLDs:
2637 Inst.setOpcode(ARM::t2PLDi12);
2638 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2639 break;
2640 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2641 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2642 }
2643
2644 int imm = fieldFromInstruction32(Insn, 0, 12);
2645 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2646 Inst.addOperand(MCOperand::CreateImm(imm));
2647
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2648 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2649 }
2650
2651 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2652 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2653 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2654 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2655 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2656
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2657 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2658}
2659
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2660static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2661 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2662 int imm = Val & 0xFF;
2663 if (!(Val & 0x100)) imm *= -1;
2664 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2665
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2666 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2667}
2668
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2669static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2671 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2672
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2673 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2674 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2675
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2677 return MCDisassembler::Fail;
2678 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2679 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2680
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2681 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682}
2683
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2684static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2685 uint64_t Address, const void *Decoder) {
2686 DecodeStatus S = MCDisassembler::Success;
2687
2688 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2689 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2690
2691 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2692 return MCDisassembler::Fail;
2693
2694 Inst.addOperand(MCOperand::CreateImm(imm));
2695
2696 return S;
2697}
2698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2699static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2700 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2701 int imm = Val & 0xFF;
2702 if (!(Val & 0x100)) imm *= -1;
2703 Inst.addOperand(MCOperand::CreateImm(imm));
2704
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2705 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2706}
2707
2708
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2709static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2710 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2711 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2712
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2713 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2714 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2715
2716 // Some instructions always use an additive offset.
2717 switch (Inst.getOpcode()) {
2718 case ARM::t2LDRT:
2719 case ARM::t2LDRBT:
2720 case ARM::t2LDRHT:
2721 case ARM::t2LDRSBT:
2722 case ARM::t2LDRSHT:
2723 imm |= 0x100;
2724 break;
2725 default:
2726 break;
2727 }
2728
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2730 return MCDisassembler::Fail;
2731 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2732 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2733
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2734 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2735}
2736
2737
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2738static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2739 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2740 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2741
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2742 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2743 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2744
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2746 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2747 Inst.addOperand(MCOperand::CreateImm(imm));
2748
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2749 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2750}
2751
2752
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2753static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2754 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2755 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2756
2757 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2758 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2759 Inst.addOperand(MCOperand::CreateImm(imm));
2760
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2761 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2762}
2763
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2764static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2765 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2766 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2767
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2768 if (Inst.getOpcode() == ARM::tADDrSP) {
2769 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2770 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2771
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2773 return MCDisassembler::Fail;
2774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2775 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2776 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2777 } else if (Inst.getOpcode() == ARM::tADDspr) {
2778 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2779
2780 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2781 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2783 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2784 }
2785
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2786 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2787}
2788
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2789static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2790 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2791 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2792 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2793
2794 Inst.addOperand(MCOperand::CreateImm(imod));
2795 Inst.addOperand(MCOperand::CreateImm(flags));
2796
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2797 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2798}
2799
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2800static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2801 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2802 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2803 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2804 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2805
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2807 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808 Inst.addOperand(MCOperand::CreateImm(add));
2809
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2810 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2811}
2812
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2813static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2814 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2815 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2816 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817}
2818
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2819static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2820 uint64_t Address, const void *Decoder) {
2821 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2822 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2823
2824 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2825 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2826}
2827
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2828static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2829DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2830 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2831 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2832
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2833 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2834 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2835 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2836 switch (opc) {
2837 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2838 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2839 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2840 Inst.setOpcode(ARM::t2DSB);
2841 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2842 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2843 Inst.setOpcode(ARM::t2DMB);
2844 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2845 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2846 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2847 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2848 }
2849
2850 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2851 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2852 }
2853
2854 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2855 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2856 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2857 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2858 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2859
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2860 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2861 return MCDisassembler::Fail;
2862 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2863 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2864
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2865 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2866}
2867
2868// Decode a shifted immediate operand. These basically consist
2869// of an 8-bit value, and a 4-bit directive that specifies either
2870// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2871static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2872 uint64_t Address, const void *Decoder) {
2873 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2874 if (ctrl == 0) {
2875 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2876 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2877 switch (byte) {
2878 case 0:
2879 Inst.addOperand(MCOperand::CreateImm(imm));
2880 break;
2881 case 1:
2882 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2883 break;
2884 case 2:
2885 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2886 break;
2887 case 3:
2888 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2889 (imm << 8) | imm));
2890 break;
2891 }
2892 } else {
2893 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2894 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2895 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2896 Inst.addOperand(MCOperand::CreateImm(imm));
2897 }
2898
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2899 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900}
2901
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2902static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2903DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2904 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2905 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2906 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907}
2908
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2909static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2910 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2911 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2912 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2913}
2914
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2915static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2916 uint64_t Address, const void *Decoder) {
2917 switch (Val) {
2918 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2919 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2920 case 0xF: // SY
2921 case 0xE: // ST
2922 case 0xB: // ISH
2923 case 0xA: // ISHST
2924 case 0x7: // NSH
2925 case 0x6: // NSHST
2926 case 0x3: // OSH
2927 case 0x2: // OSHST
2928 break;
2929 }
2930
2931 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2932 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2933}
2934
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2935static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2936 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2937 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2938 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2939 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2940}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2941
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2942static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2943 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2944 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2945
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2946 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2947 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2948 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2949
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2950 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2951
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2953 return MCDisassembler::Fail;
2954 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2955 return MCDisassembler::Fail;
2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2957 return MCDisassembler::Fail;
2958 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2959 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2960
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2961 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2962}
2963
2964
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2965static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2966 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2967 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2968
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2969 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2970 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2971 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]2972 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2973
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2974 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2975 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2976
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2977 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
2978 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2979
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2981 return MCDisassembler::Fail;
2982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2983 return MCDisassembler::Fail;
2984 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2985 return MCDisassembler::Fail;
2986 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2987 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2988
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2989 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2990}
2991
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2992static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2993 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2994 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2995
2996 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2997 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2998 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2999 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3000 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3001 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3002
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3003 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3004
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3006 return MCDisassembler::Fail;
3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3008 return MCDisassembler::Fail;
3009 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3010 return MCDisassembler::Fail;
3011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3012 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3013
3014 return S;
3015}
3016
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3017static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3018 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3019 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3020
3021 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3022 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3023 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3024 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3025 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3026 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3027 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3028
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3029 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3030 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3031
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3032 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3033 return MCDisassembler::Fail;
3034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3035 return MCDisassembler::Fail;
3036 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3037 return MCDisassembler::Fail;
3038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3039 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3040
3041 return S;
3042}
3043
3044
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3045static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3046 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3047 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3048
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3049 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3050 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3051 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3052 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3053 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3054 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3055
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3056 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3057
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3059 return MCDisassembler::Fail;
3060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3061 return MCDisassembler::Fail;
3062 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3063 return MCDisassembler::Fail;
3064 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3065 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3066
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3067 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3068}
3069
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3070static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3071 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3072 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3073
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3074 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3075 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3076 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3077 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3078 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3079 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3080
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3081 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3082
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3084 return MCDisassembler::Fail;
3085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3086 return MCDisassembler::Fail;
3087 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3088 return MCDisassembler::Fail;
3089 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3090 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3091
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3092 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3093}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3094
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3095static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3096 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3097 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3098
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3099 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3100 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3101 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3102 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3103 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3104
3105 unsigned align = 0;
3106 unsigned index = 0;
3107 switch (size) {
3108 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3109 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3110 case 0:
3111 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3112 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3113 index = fieldFromInstruction32(Insn, 5, 3);
3114 break;
3115 case 1:
3116 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3117 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3118 index = fieldFromInstruction32(Insn, 6, 2);
3119 if (fieldFromInstruction32(Insn, 4, 1))
3120 align = 2;
3121 break;
3122 case 2:
3123 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3124 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3125 index = fieldFromInstruction32(Insn, 7, 1);
3126 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3127 align = 4;
3128 }
3129
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3130 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3131 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3132 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3134 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3135 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3136 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3137 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3138 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3139 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3140 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3142 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3143 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3144 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3145 }
3146
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3147 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3148 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3149 Inst.addOperand(MCOperand::CreateImm(index));
3150
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3151 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3152}
3153
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3154static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3155 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3156 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3157
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3158 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3159 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3160 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3161 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3162 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3163
3164 unsigned align = 0;
3165 unsigned index = 0;
3166 switch (size) {
3167 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3168 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3169 case 0:
3170 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3171 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3172 index = fieldFromInstruction32(Insn, 5, 3);
3173 break;
3174 case 1:
3175 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3176 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3177 index = fieldFromInstruction32(Insn, 6, 2);
3178 if (fieldFromInstruction32(Insn, 4, 1))
3179 align = 2;
3180 break;
3181 case 2:
3182 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3183 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3184 index = fieldFromInstruction32(Insn, 7, 1);
3185 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3186 align = 4;
3187 }
3188
3189 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3190 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3191 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3192 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3193 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3194 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3195 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3196 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3197 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3199 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3200 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3201 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3202 }
3203
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3205 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3206 Inst.addOperand(MCOperand::CreateImm(index));
3207
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3208 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3209}
3210
3211
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3212static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3213 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3214 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3215
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3216 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3217 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3218 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3219 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3220 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3221
3222 unsigned align = 0;
3223 unsigned index = 0;
3224 unsigned inc = 1;
3225 switch (size) {
3226 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3227 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3228 case 0:
3229 index = fieldFromInstruction32(Insn, 5, 3);
3230 if (fieldFromInstruction32(Insn, 4, 1))
3231 align = 2;
3232 break;
3233 case 1:
3234 index = fieldFromInstruction32(Insn, 6, 2);
3235 if (fieldFromInstruction32(Insn, 4, 1))
3236 align = 4;
3237 if (fieldFromInstruction32(Insn, 5, 1))
3238 inc = 2;
3239 break;
3240 case 2:
3241 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3242 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3243 index = fieldFromInstruction32(Insn, 7, 1);
3244 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3245 align = 8;
3246 if (fieldFromInstruction32(Insn, 6, 1))
3247 inc = 2;
3248 break;
3249 }
3250
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3251 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3252 return MCDisassembler::Fail;
3253 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3254 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3255 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3257 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3258 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3260 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3261 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3262 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3263 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3265 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3266 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3267 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3268 }
3269
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3270 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3271 return MCDisassembler::Fail;
3272 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3273 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3274 Inst.addOperand(MCOperand::CreateImm(index));
3275
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3276 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3277}
3278
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3279static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3280 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3281 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3282
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3283 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3284 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3285 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3286 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3287 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3288
3289 unsigned align = 0;
3290 unsigned index = 0;
3291 unsigned inc = 1;
3292 switch (size) {
3293 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3294 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3295 case 0:
3296 index = fieldFromInstruction32(Insn, 5, 3);
3297 if (fieldFromInstruction32(Insn, 4, 1))
3298 align = 2;
3299 break;
3300 case 1:
3301 index = fieldFromInstruction32(Insn, 6, 2);
3302 if (fieldFromInstruction32(Insn, 4, 1))
3303 align = 4;
3304 if (fieldFromInstruction32(Insn, 5, 1))
3305 inc = 2;
3306 break;
3307 case 2:
3308 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3309 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3310 index = fieldFromInstruction32(Insn, 7, 1);
3311 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3312 align = 8;
3313 if (fieldFromInstruction32(Insn, 6, 1))
3314 inc = 2;
3315 break;
3316 }
3317
3318 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3320 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3321 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3323 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3324 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3325 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3326 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3328 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3329 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3330 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3331 }
3332
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3333 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3334 return MCDisassembler::Fail;
3335 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3336 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3337 Inst.addOperand(MCOperand::CreateImm(index));
3338
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3339 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3340}
3341
3342
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3343static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3344 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3345 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3346
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3347 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3348 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3349 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3350 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3351 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3352
3353 unsigned align = 0;
3354 unsigned index = 0;
3355 unsigned inc = 1;
3356 switch (size) {
3357 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3358 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3359 case 0:
3360 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3361 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3362 index = fieldFromInstruction32(Insn, 5, 3);
3363 break;
3364 case 1:
3365 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3366 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3367 index = fieldFromInstruction32(Insn, 6, 2);
3368 if (fieldFromInstruction32(Insn, 5, 1))
3369 inc = 2;
3370 break;
3371 case 2:
3372 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3373 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3374 index = fieldFromInstruction32(Insn, 7, 1);
3375 if (fieldFromInstruction32(Insn, 6, 1))
3376 inc = 2;
3377 break;
3378 }
3379
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3380 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3381 return MCDisassembler::Fail;
3382 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3383 return MCDisassembler::Fail;
3384 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3385 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3386
3387 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3389 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3390 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3392 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3393 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3394 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3395 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3397 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3398 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3399 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3400 }
3401
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3402 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3403 return MCDisassembler::Fail;
3404 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3405 return MCDisassembler::Fail;
3406 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3407 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3408 Inst.addOperand(MCOperand::CreateImm(index));
3409
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3410 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3411}
3412
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3413static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3414 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3415 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3416
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3417 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3418 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3419 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3420 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3421 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3422
3423 unsigned align = 0;
3424 unsigned index = 0;
3425 unsigned inc = 1;
3426 switch (size) {
3427 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3428 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3429 case 0:
3430 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3431 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3432 index = fieldFromInstruction32(Insn, 5, 3);
3433 break;
3434 case 1:
3435 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3436 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3437 index = fieldFromInstruction32(Insn, 6, 2);
3438 if (fieldFromInstruction32(Insn, 5, 1))
3439 inc = 2;
3440 break;
3441 case 2:
3442 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3443 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3444 index = fieldFromInstruction32(Insn, 7, 1);
3445 if (fieldFromInstruction32(Insn, 6, 1))
3446 inc = 2;
3447 break;
3448 }
3449
3450 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3452 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3453 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3455 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3456 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3457 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3458 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3460 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3461 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3462 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3463 }
3464
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3466 return MCDisassembler::Fail;
3467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3468 return MCDisassembler::Fail;
3469 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3470 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3471 Inst.addOperand(MCOperand::CreateImm(index));
3472
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3473 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3474}
3475
3476
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3477static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3478 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3479 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3480
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3481 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3482 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3483 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3484 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3485 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3486
3487 unsigned align = 0;
3488 unsigned index = 0;
3489 unsigned inc = 1;
3490 switch (size) {
3491 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3492 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3493 case 0:
3494 if (fieldFromInstruction32(Insn, 4, 1))
3495 align = 4;
3496 index = fieldFromInstruction32(Insn, 5, 3);
3497 break;
3498 case 1:
3499 if (fieldFromInstruction32(Insn, 4, 1))
3500 align = 8;
3501 index = fieldFromInstruction32(Insn, 6, 2);
3502 if (fieldFromInstruction32(Insn, 5, 1))
3503 inc = 2;
3504 break;
3505 case 2:
3506 if (fieldFromInstruction32(Insn, 4, 2))
3507 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3508 index = fieldFromInstruction32(Insn, 7, 1);
3509 if (fieldFromInstruction32(Insn, 6, 1))
3510 inc = 2;
3511 break;
3512 }
3513
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3514 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3515 return MCDisassembler::Fail;
3516 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3517 return MCDisassembler::Fail;
3518 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3519 return MCDisassembler::Fail;
3520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3521 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3522
3523 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3525 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3526 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3528 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3529 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3530 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3531 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3533 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3534 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3535 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3536 }
3537
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3539 return MCDisassembler::Fail;
3540 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3541 return MCDisassembler::Fail;
3542 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3543 return MCDisassembler::Fail;
3544 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3545 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3546 Inst.addOperand(MCOperand::CreateImm(index));
3547
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3548 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3549}
3550
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3551static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3552 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3553 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3554
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3555 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3556 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3557 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3558 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3559 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3560
3561 unsigned align = 0;
3562 unsigned index = 0;
3563 unsigned inc = 1;
3564 switch (size) {
3565 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3566 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3567 case 0:
3568 if (fieldFromInstruction32(Insn, 4, 1))
3569 align = 4;
3570 index = fieldFromInstruction32(Insn, 5, 3);
3571 break;
3572 case 1:
3573 if (fieldFromInstruction32(Insn, 4, 1))
3574 align = 8;
3575 index = fieldFromInstruction32(Insn, 6, 2);
3576 if (fieldFromInstruction32(Insn, 5, 1))
3577 inc = 2;
3578 break;
3579 case 2:
3580 if (fieldFromInstruction32(Insn, 4, 2))
3581 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3582 index = fieldFromInstruction32(Insn, 7, 1);
3583 if (fieldFromInstruction32(Insn, 6, 1))
3584 inc = 2;
3585 break;
3586 }
3587
3588 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3589 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3590 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3591 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3593 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3594 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3595 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3596 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3598 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3599 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3600 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3601 }
3602
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3603 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3604 return MCDisassembler::Fail;
3605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3606 return MCDisassembler::Fail;
3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3608 return MCDisassembler::Fail;
3609 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3610 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3611 Inst.addOperand(MCOperand::CreateImm(index));
3612
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3613 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3614}
3615
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3616static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3617 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3618 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3619 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3620 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3621 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3622 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3623 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3624
3625 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3626 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3627
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3628 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3629 return MCDisassembler::Fail;
3630 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3631 return MCDisassembler::Fail;
3632 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3633 return MCDisassembler::Fail;
3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3635 return MCDisassembler::Fail;
3636 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3637 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3638
3639 return S;
3640}
3641
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3642static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3643 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3644 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3645 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3646 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3647 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3648 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3649 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3650
3651 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3652 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3653
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3655 return MCDisassembler::Fail;
3656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3657 return MCDisassembler::Fail;
3658 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3659 return MCDisassembler::Fail;
3660 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3661 return MCDisassembler::Fail;
3662 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3663 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3664
3665 return S;
3666}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3667
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3668static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3669 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3670 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3671 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3672 // The InstPrinter needs to have the low bit of the predicate in
3673 // the mask operand to be able to print it properly.
3674 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3675
3676 if (pred == 0xF) {
3677 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3678 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3679 }
3680
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3681 if ((mask & 0xF) == 0) {
3682 // Preserve the high bit of the mask, which is the low bit of
3683 // the predicate.
3684 mask &= 0x10;
3685 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3686 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3687 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3688
3689 Inst.addOperand(MCOperand::CreateImm(pred));
3690 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3691 return S;
3692}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3693
3694static DecodeStatus
3695DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3696 uint64_t Address, const void *Decoder) {
3697 DecodeStatus S = MCDisassembler::Success;
3698
3699 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3700 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3701 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3702 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3703 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3704 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3705 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3706 bool writeback = (W == 1) | (P == 0);
3707
3708 addr |= (U << 8) | (Rn << 9);
3709
3710 if (writeback && (Rn == Rt || Rn == Rt2))
3711 Check(S, MCDisassembler::SoftFail);
3712 if (Rt == Rt2)
3713 Check(S, MCDisassembler::SoftFail);
3714
3715 // Rt
3716 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3717 return MCDisassembler::Fail;
3718 // Rt2
3719 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3720 return MCDisassembler::Fail;
3721 // Writeback operand
3722 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3723 return MCDisassembler::Fail;
3724 // addr
3725 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3726 return MCDisassembler::Fail;
3727
3728 return S;
3729}
3730
3731static DecodeStatus
3732DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3733 uint64_t Address, const void *Decoder) {
3734 DecodeStatus S = MCDisassembler::Success;
3735
3736 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3737 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3738 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3739 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3740 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3741 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3742 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3743 bool writeback = (W == 1) | (P == 0);
3744
3745 addr |= (U << 8) | (Rn << 9);
3746
3747 if (writeback && (Rn == Rt || Rn == Rt2))
3748 Check(S, MCDisassembler::SoftFail);
3749
3750 // Writeback operand
3751 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3752 return MCDisassembler::Fail;
3753 // Rt
3754 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3755 return MCDisassembler::Fail;
3756 // Rt2
3757 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3758 return MCDisassembler::Fail;
3759 // addr
3760 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3761 return MCDisassembler::Fail;
3762
3763 return S;
3764}