| Reid Spencer | addd11d | 2007-04-04 23:48:25 +0000 | [diff] [blame] | 1 | ; Make sure this testcase is supported by all code generators. Either the |
| 2 | ; intrinsic is supported natively or IntrinsicLowering provides it. |
| 3 | ; RUN: llvm-as < %s | llc |
| 4 | |
| 5 | |
| 6 | declare i32 @llvm.bit.part.select.i32.i32(i32 %x, i32 %hi, i32 %lo) |
| 7 | declare i16 @llvm.bit.part.select.i16.i16(i16 %x, i32 %hi, i32 %lo) |
| 8 | define i32 @bit_part_select(i32 %A, i16 %B) { |
| 9 | %a = call i32 @llvm.bit.part.select.i32.i32(i32 %A, i32 8, i32 0) |
| 10 | %b = call i16 @llvm.bit.part.select.i16.i16(i16 %B, i32 8, i32 0) |
| 11 | %c = zext i16 %b to i32 |
| 12 | %d = add i32 %a, %c |
| 13 | ret i32 %d |
| 14 | } |