Blame - lib/Target/ARM/Disassembler/ARMDisassembler.cpp - platform/external/llvm

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Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	1	//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ------ C++ --===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	12	#include "ARM.h"
				13	#include "ARMRegisterInfo.h"
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	14	#include "ARMSubtarget.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	15	#include "MCTargetDesc/ARMAddressingModes.h"
				16	#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	17	#include "llvm/MC/EDInstInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	18	#include "llvm/MC/MCInst.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	19	#include "llvm/MC/MCExpr.h"
				20	#include "llvm/MC/MCContext.h"
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	21	#include "llvm/MC/MCDisassembler.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/Debug.h"
				23	#include "llvm/Support/MemoryObject.h"
				24	#include "llvm/Support/ErrorHandling.h"
Evan Cheng	3e74d6f	2011-08-24 18:08:43 +0000	[diff] [blame]	25	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	26	#include "llvm/Support/raw_ostream.h"
				27
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	28	using namespace llvm;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	29
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	30	typedef MCDisassembler::DecodeStatus DecodeStatus;
				31
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	32	namespace {
				33	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				34	class ARMDisassembler : public MCDisassembler {
				35	public:
				36	/// Constructor - Initializes the disassembler.
				37	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	38	ARMDisassembler(const MCSubtargetInfo &STI) :
				39	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	40	}
				41
				42	~ARMDisassembler() {
				43	}
				44
				45	/// getInstruction - See MCDisassembler.
				46	DecodeStatus getInstruction(MCInst &instr,
				47	uint64_t &size,
				48	const MemoryObject &region,
				49	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	50	raw_ostream &vStream,
				51	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	52
				53	/// getEDInfo - See MCDisassembler.
				54	EDInstInfo *getEDInfo() const;
				55	private:
				56	};
				57
				58	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				59	class ThumbDisassembler : public MCDisassembler {
				60	public:
				61	/// Constructor - Initializes the disassembler.
				62	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	63	ThumbDisassembler(const MCSubtargetInfo &STI) :
				64	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	65	}
				66
				67	~ThumbDisassembler() {
				68	}
				69
				70	/// getInstruction - See MCDisassembler.
				71	DecodeStatus getInstruction(MCInst &instr,
				72	uint64_t &size,
				73	const MemoryObject &region,
				74	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	75	raw_ostream &vStream,
				76	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	77
				78	/// getEDInfo - See MCDisassembler.
				79	EDInstInfo *getEDInfo() const;
				80	private:
				81	mutable std::vector<unsigned> ITBlock;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	82	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	83	void UpdateThumbVFPPredicate(MCInst&) const;
				84	};
				85	}
				86
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	87	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	88	switch (In) {
				89	case MCDisassembler::Success:
				90	// Out stays the same.
				91	return true;
				92	case MCDisassembler::SoftFail:
				93	Out = In;
				94	return true;
				95	case MCDisassembler::Fail:
				96	Out = In;
				97	return false;
				98	}
				99	return false;
				100	}
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	101
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	102
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	103	// Forward declare these because the autogenerated code will reference them.
				104	// Definitions are further down.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	105	static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	106	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	107	static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	108	unsigned RegNo, uint64_t Address,
				109	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	110	static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	111	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	112	static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	113	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	114	static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	115	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	116	static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	117	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	118	static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	119	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	120	static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	121	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	122	static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	123	unsigned RegNo,
				124	uint64_t Address,
				125	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	126	static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	127	uint64_t Address, const void *Decoder);
Johnny Chen	270159f	2010-08-12 01:40:54 +0000	[diff] [blame]	128
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	129	static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	130	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	131	static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	132	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	133	static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	134	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	135	static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	136	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	137	static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	138	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	139	static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	140	uint64_t Address, const void *Decoder);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	141
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	142	static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	143	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	144	static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	145	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	146	static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	147	unsigned Insn,
				148	uint64_t Address,
				149	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	150	static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	151	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	152	static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	153	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	154	static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	155	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	156	static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	157	uint64_t Address, const void *Decoder);
				158
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	159	static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	160	unsigned Insn,
				161	uint64_t Adddress,
				162	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	163	static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	164	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	165	static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	166	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	167	static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	168	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	169	static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	170	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	171	static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	172	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	173	static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	174	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	175	static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	176	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	177	static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	178	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	179	static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	180	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	181	static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	182	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	183	static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	184	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	185	static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	186	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	187	static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	188	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	189	static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	190	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	191	static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	192	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	193	static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	194	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	195	static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	196	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	197	static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	198	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	199	static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	200	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	201	static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	202	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	203	static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	205	static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	206	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	207	static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	209	static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	211	static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	213	static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	215	static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	217	static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	218	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	219	static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	220	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	221	static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	222	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	223	static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	224	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	225	static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	226	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	227	static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	228	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	229	static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	230	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	231	static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	232	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	233	static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	234	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	235	static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	236	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	237	static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	238	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	239	static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	240	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	241	static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	242	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	243	static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	244	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	245	static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	246	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	247	static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	248	uint64_t Address, const void *Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	249
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	250	static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	251	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	252	static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	254	static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	256	static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	258	static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	260	static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	262	static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	264	static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	266	static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	268	static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	270	static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	272	static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	274	static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
				275	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	276	static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	278	static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	280	static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	282	static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	284	static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	285	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	286	static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	288	static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	290	static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	292	static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	294	static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	296	static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	298	static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	300	static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
				301	uint64_t Address, const void *Decoder);
				302	static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
				303	uint64_t Address, const void *Decoder);
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	304	static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
				305	uint64_t Address, const void *Decoder);
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	306	static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
				307	uint64_t Address, const void *Decoder);
				308
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	309
				310	#include "ARMGenDisassemblerTables.inc"
				311	#include "ARMGenInstrInfo.inc"
Oscar Fuentes	38e1390	2010-09-28 11:48:19 +0000	[diff] [blame]	312	#include "ARMGenEDInfo.inc"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	313
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	314	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				315	return new ARMDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	316	}
				317
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	318	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				319	return new ThumbDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	320	}
				321
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	322	EDInstInfo *ARMDisassembler::getEDInfo() const {
				323	return instInfoARM;
				324	}
				325
				326	EDInstInfo *ThumbDisassembler::getEDInfo() const {
				327	return instInfoARM;
				328	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	329
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	330	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	331	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	332	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	333	raw_ostream &os,
				334	raw_ostream &cs) const {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint8_t bytes[4];
				336
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	337	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				338	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				339
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	340	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	341	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				342	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	343	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	344	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	345
				346	// Encoded as a small-endian 32-bit word in the stream.
				347	uint32_t insn = (bytes[3] << 24) \|
				348	(bytes[2] << 16) \|
				349	(bytes[1] << 8) \|
				350	(bytes[0] << 0);
				351
				352	// Calling the auto-generated decoder function.
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	353	DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	354	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	355	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	356	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	357	}
				358
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	359	// VFP and NEON instructions, similarly, are shared between ARM
				360	// and Thumb modes.
				361	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	362	result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	363	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	364	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	365	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	366	}
				367
				368	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	369	result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	370	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	371	Size = 4;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	372	// Add a fake predicate operand, because we share these instruction
				373	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	374	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				375	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	376	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	377	}
				378
				379	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	380	result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	381	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	382	Size = 4;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	383	// Add a fake predicate operand, because we share these instruction
				384	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	385	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				386	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	387	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	388	}
				389
				390	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	391	result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	392	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	393	Size = 4;
				394	// Add a fake predicate operand, because we share these instruction
				395	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	396	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				397	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	398	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	399	}
				400
				401	MI.clear();
				402
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	403	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	404	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	405	}
				406
				407	namespace llvm {
				408	extern MCInstrDesc ARMInsts[];
				409	}
				410
				411	// Thumb1 instructions don't have explicit S bits. Rather, they
				412	// implicitly set CPSR. Since it's not represented in the encoding, the
				413	// auto-generated decoder won't inject the CPSR operand. We need to fix
				414	// that as a post-pass.
				415	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				416	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	417	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	418	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	419	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				420	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	421	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	422	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	423	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				424	return;
				425	}
				426	}
				427
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	428	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	429	}
				430
				431	// Most Thumb instructions don't have explicit predicates in the
				432	// encoding, but rather get their predicates from IT context. We need
				433	// to fix up the predicate operands using this context information as a
				434	// post-pass.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	435	MCDisassembler::DecodeStatus
				436	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	437	MCDisassembler::DecodeStatus S = Success;
				438
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	439	// A few instructions actually have predicates encoded in them. Don't
				440	// try to overwrite it if we're seeing one of those.
				441	switch (MI.getOpcode()) {
				442	case ARM::tBcc:
				443	case ARM::t2Bcc:
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	444	case ARM::tCBZ:
				445	case ARM::tCBNZ:
Owen Anderson	441462f	2011-09-08 22:48:37 +0000	[diff] [blame]	446	// Some instructions (mostly conditional branches) are not
				447	// allowed in IT blocks.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	448	if (!ITBlock.empty())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	449	S = SoftFail;
				450	else
				451	return Success;
				452	break;
				453	case ARM::tB:
				454	case ARM::t2B:
				455	// Some instructions (mostly unconditional branches) can
				456	// only appears at the end of, or outside of, an IT.
				457	if (ITBlock.size() > 1)
				458	S = SoftFail;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	459	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	460	default:
				461	break;
				462	}
				463
				464	// If we're in an IT block, base the predicate on that. Otherwise,
				465	// assume a predicate of AL.
				466	unsigned CC;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	467	if (!ITBlock.empty()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	468	CC = ITBlock.back();
Owen Anderson	9bd655d	2011-08-26 06:19:51 +0000	[diff] [blame]	469	if (CC == 0xF)
				470	CC = ARMCC::AL;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	471	ITBlock.pop_back();
				472	} else
				473	CC = ARMCC::AL;
				474
				475	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	476	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	477	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	478	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				479	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	480	if (OpInfo[i].isPredicate()) {
				481	I = MI.insert(I, MCOperand::CreateImm(CC));
				482	++I;
				483	if (CC == ARMCC::AL)
				484	MI.insert(I, MCOperand::CreateReg(0));
				485	else
				486	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	487	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	488	}
				489	}
				490
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	491	I = MI.insert(I, MCOperand::CreateImm(CC));
				492	++I;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	493	if (CC == ARMCC::AL)
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	494	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	495	else
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	496	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	497
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	498	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	499	}
				500
				501	// Thumb VFP instructions are a special case. Because we share their
				502	// encodings between ARM and Thumb modes, and they are predicable in ARM
				503	// mode, the auto-generated decoder will give them an (incorrect)
				504	// predicate operand. We need to rewrite these operands based on the IT
				505	// context as a post-pass.
				506	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				507	unsigned CC;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	508	if (!ITBlock.empty()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	509	CC = ITBlock.back();
				510	ITBlock.pop_back();
				511	} else
				512	CC = ARMCC::AL;
				513
				514	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				515	MCInst::iterator I = MI.begin();
Owen Anderson	12a1e3b	2011-08-24 21:35:46 +0000	[diff] [blame]	516	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				517	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	518	if (OpInfo[i].isPredicate() ) {
				519	I->setImm(CC);
				520	++I;
				521	if (CC == ARMCC::AL)
				522	I->setReg(0);
				523	else
				524	I->setReg(ARM::CPSR);
				525	return;
				526	}
				527	}
				528	}
				529
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	530	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	531	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	532	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	533	raw_ostream &os,
				534	raw_ostream &cs) const {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	535	uint8_t bytes[4];
				536
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	537	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				538	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				539
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	540	// We want to read exactly 2 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	541	if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
				542	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	543	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	544	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	545
				546	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	547	DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	548	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	549	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	550	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	551	return result;
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	552	}
				553
				554	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	555	result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	556	if (result) {
				557	Size = 2;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	558	bool InITBlock = !ITBlock.empty();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	559	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	560	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	561	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	562	}
				563
				564	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	565	result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	566	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	567	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	568	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	569
				570	// If we find an IT instruction, we need to parse its condition
				571	// code and mask operands so that we can apply them correctly
				572	// to the subsequent instructions.
				573	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	34626ac	2011-09-14 21:06:21 +0000	[diff] [blame]	574	// Nested IT blocks are UNPREDICTABLE.
				575	if (!ITBlock.empty())
				576	return MCDisassembler::SoftFail;
				577
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	578	// (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	579	unsigned firstcond = MI.getOperand(0).getImm();
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	580	unsigned Mask = MI.getOperand(1).getImm();
				581	unsigned CondBit0 = Mask >> 4 & 1;
				582	unsigned NumTZ = CountTrailingZeros_32(Mask);
				583	assert(NumTZ <= 3 && "Invalid IT mask!");
				584	for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
				585	bool T = ((Mask >> Pos) & 1) == CondBit0;
				586	if (T)
				587	ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	588	else
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	589	ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	590	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	591
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	592	ITBlock.push_back(firstcond);
				593	}
				594
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	595	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	596	}
				597
				598	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	599	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				600	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	601	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	602	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	603
				604	uint32_t insn32 = (bytes[3] << 8) \|
				605	(bytes[2] << 0) \|
				606	(bytes[1] << 24) \|
				607	(bytes[0] << 16);
				608	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	609	result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	610	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	611	Size = 4;
				612	bool InITBlock = ITBlock.size();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	613	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	614	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	615	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	616	}
				617
				618	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	619	result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	620	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	621	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	622	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	623	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	624	}
				625
				626	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	627	result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	628	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	629	Size = 4;
				630	UpdateThumbVFPPredicate(MI);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	631	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	632	}
				633
				634	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	635	result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	636	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	637	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	638	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	639	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	640	}
				641
				642	if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
				643	MI.clear();
				644	uint32_t NEONLdStInsn = insn32;
				645	NEONLdStInsn &= 0xF0FFFFFF;
				646	NEONLdStInsn \|= 0x04000000;
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	647	result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	648	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	649	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	650	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	651	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	652	}
				653	}
				654
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	655	if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	656	MI.clear();
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	657	uint32_t NEONDataInsn = insn32;
				658	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				659	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				660	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	661	result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	662	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	663	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	664	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	665	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	666	}
				667	}
				668
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	669	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	670	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	671	}
				672
				673
				674	extern "C" void LLVMInitializeARMDisassembler() {
				675	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				676	createARMDisassembler);
				677	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				678	createThumbDisassembler);
				679	}
				680
				681	static const unsigned GPRDecoderTable[] = {
				682	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				683	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				684	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				685	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				686	};
				687
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	688	static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	689	uint64_t Address, const void *Decoder) {
				690	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	691	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	692
				693	unsigned Register = GPRDecoderTable[RegNo];
				694	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	695	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	696	}
				697
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	698	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	699	DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
				700	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	701	if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	51c9805	2011-08-09 22:48:45 +0000	[diff] [blame]	702	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				703	}
				704
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	705	static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	706	uint64_t Address, const void *Decoder) {
				707	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	708	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	709	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				710	}
				711
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	712	static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	713	uint64_t Address, const void *Decoder) {
				714	unsigned Register = 0;
				715	switch (RegNo) {
				716	case 0:
				717	Register = ARM::R0;
				718	break;
				719	case 1:
				720	Register = ARM::R1;
				721	break;
				722	case 2:
				723	Register = ARM::R2;
				724	break;
				725	case 3:
				726	Register = ARM::R3;
				727	break;
				728	case 9:
				729	Register = ARM::R9;
				730	break;
				731	case 12:
				732	Register = ARM::R12;
				733	break;
				734	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	735	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	736	}
				737
				738	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	739	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	740	}
				741
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	742	static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	743	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	744	if (RegNo == 13 \|\| RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	745	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				746	}
				747
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	748	static const unsigned SPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	749	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				750	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				751	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				752	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				753	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				754	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				755	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				756	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				757	};
				758
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	759	static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	760	uint64_t Address, const void *Decoder) {
				761	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	762	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	763
				764	unsigned Register = SPRDecoderTable[RegNo];
				765	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	766	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	767	}
				768
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	769	static const unsigned DPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	770	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				771	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				772	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				773	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				774	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				775	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				776	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				777	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				778	};
				779
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	780	static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	781	uint64_t Address, const void *Decoder) {
				782	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	783	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	784
				785	unsigned Register = DPRDecoderTable[RegNo];
				786	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	787	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	788	}
				789
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	790	static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	791	uint64_t Address, const void *Decoder) {
				792	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	793	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	794	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				795	}
				796
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	797	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	798	DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
				799	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	800	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	801	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	802	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				803	}
				804
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	805	static const unsigned QPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	806	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				807	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				808	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				809	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				810	};
				811
				812
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	813	static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	814	uint64_t Address, const void *Decoder) {
				815	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	816	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	817	RegNo >>= 1;
				818
				819	unsigned Register = QPRDecoderTable[RegNo];
				820	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	821	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	822	}
				823
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	824	static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	825	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	826	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	bd9091c	2011-08-09 21:07:45 +0000	[diff] [blame]	827	// AL predicate is not allowed on Thumb1 branches.
				828	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	829	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	830	Inst.addOperand(MCOperand::CreateImm(Val));
				831	if (Val == ARMCC::AL) {
				832	Inst.addOperand(MCOperand::CreateReg(0));
				833	} else
				834	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	835	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	836	}
				837
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	838	static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	839	uint64_t Address, const void *Decoder) {
				840	if (Val)
				841	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				842	else
				843	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	844	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	845	}
				846
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	847	static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	848	uint64_t Address, const void *Decoder) {
				849	uint32_t imm = Val & 0xFF;
				850	uint32_t rot = (Val & 0xF00) >> 7;
				851	uint32_t rot_imm = (imm >> rot) \| (imm << (32-rot));
				852	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	853	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	854	}
				855
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	856	static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	857	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	858	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	859
				860	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				861	unsigned type = fieldFromInstruction32(Val, 5, 2);
				862	unsigned imm = fieldFromInstruction32(Val, 7, 5);
				863
				864	// Register-immediate
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	865	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				866	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	867
				868	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				869	switch (type) {
				870	case 0:
				871	Shift = ARM_AM::lsl;
				872	break;
				873	case 1:
				874	Shift = ARM_AM::lsr;
				875	break;
				876	case 2:
				877	Shift = ARM_AM::asr;
				878	break;
				879	case 3:
				880	Shift = ARM_AM::ror;
				881	break;
				882	}
				883
				884	if (Shift == ARM_AM::ror && imm == 0)
				885	Shift = ARM_AM::rrx;
				886
				887	unsigned Op = Shift \| (imm << 3);
				888	Inst.addOperand(MCOperand::CreateImm(Op));
				889
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	890	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	891	}
				892
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	893	static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	894	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	895	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	896
				897	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				898	unsigned type = fieldFromInstruction32(Val, 5, 2);
				899	unsigned Rs = fieldFromInstruction32(Val, 8, 4);
				900
				901	// Register-register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	902	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				903	return MCDisassembler::Fail;
				904	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				905	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	906
				907	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				908	switch (type) {
				909	case 0:
				910	Shift = ARM_AM::lsl;
				911	break;
				912	case 1:
				913	Shift = ARM_AM::lsr;
				914	break;
				915	case 2:
				916	Shift = ARM_AM::asr;
				917	break;
				918	case 3:
				919	Shift = ARM_AM::ror;
				920	break;
				921	}
				922
				923	Inst.addOperand(MCOperand::CreateImm(Shift));
				924
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	925	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	926	}
				927
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	928	static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	929	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	930	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	931
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	932	bool writebackLoad = false;
				933	unsigned writebackReg = 0;
				934	switch (Inst.getOpcode()) {
				935	default:
				936	break;
				937	case ARM::LDMIA_UPD:
				938	case ARM::LDMDB_UPD:
				939	case ARM::LDMIB_UPD:
				940	case ARM::LDMDA_UPD:
				941	case ARM::t2LDMIA_UPD:
				942	case ARM::t2LDMDB_UPD:
				943	writebackLoad = true;
				944	writebackReg = Inst.getOperand(0).getReg();
				945	break;
				946	}
				947
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	948	// Empty register lists are not allowed.
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	949	if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	950	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	951	if (Val & (1 << i)) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	952	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				953	return MCDisassembler::Fail;
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	954	// Writeback not allowed if Rn is in the target list.
				955	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				956	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	957	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	958	}
				959
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	960	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	961	}
				962
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	963	static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	964	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	965	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	966
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	967	unsigned Vd = fieldFromInstruction32(Val, 8, 4);
				968	unsigned regs = Val & 0xFF;
				969
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	970	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				971	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	972	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	973	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				974	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	975	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	976
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	977	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	978	}
				979
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	980	static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	981	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	982	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	983
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	984	unsigned Vd = fieldFromInstruction32(Val, 8, 4);
				985	unsigned regs = (Val & 0xFF) / 2;
				986
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	987	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				988	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	989	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	990	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				991	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	992	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	993
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	994	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	995	}
				996
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	997	static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	998	uint64_t Address, const void *Decoder) {
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	999	// This operand encodes a mask of contiguous zeros between a specified MSB
				1000	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1001	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1002	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1003	// create the final mask.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1004	unsigned msb = fieldFromInstruction32(Val, 5, 5);
				1005	unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1006
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1007	uint32_t msb_mask = (1 << (msb+1)) - 1;
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1008	if (msb == 31) msb_mask = 0xFFFFFFFF;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1009	uint32_t lsb_mask = (1 << lsb) - 1;
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1010	if (lsb == 31) lsb_mask = 0xFFFFFFFF;
				1011
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1012	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1013	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1014	}
				1015
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1016	static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1017	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1018	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1019
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1020	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1021	unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
				1022	unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
				1023	unsigned imm = fieldFromInstruction32(Insn, 0, 8);
				1024	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1025	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				1026
				1027	switch (Inst.getOpcode()) {
				1028	case ARM::LDC_OFFSET:
				1029	case ARM::LDC_PRE:
				1030	case ARM::LDC_POST:
				1031	case ARM::LDC_OPTION:
				1032	case ARM::LDCL_OFFSET:
				1033	case ARM::LDCL_PRE:
				1034	case ARM::LDCL_POST:
				1035	case ARM::LDCL_OPTION:
				1036	case ARM::STC_OFFSET:
				1037	case ARM::STC_PRE:
				1038	case ARM::STC_POST:
				1039	case ARM::STC_OPTION:
				1040	case ARM::STCL_OFFSET:
				1041	case ARM::STCL_PRE:
				1042	case ARM::STCL_POST:
				1043	case ARM::STCL_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1044	case ARM::t2LDC_OFFSET:
				1045	case ARM::t2LDC_PRE:
				1046	case ARM::t2LDC_POST:
				1047	case ARM::t2LDC_OPTION:
				1048	case ARM::t2LDCL_OFFSET:
				1049	case ARM::t2LDCL_PRE:
				1050	case ARM::t2LDCL_POST:
				1051	case ARM::t2LDCL_OPTION:
				1052	case ARM::t2STC_OFFSET:
				1053	case ARM::t2STC_PRE:
				1054	case ARM::t2STC_POST:
				1055	case ARM::t2STC_OPTION:
				1056	case ARM::t2STCL_OFFSET:
				1057	case ARM::t2STCL_PRE:
				1058	case ARM::t2STCL_POST:
				1059	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1060	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1061	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1062	break;
				1063	default:
				1064	break;
				1065	}
				1066
				1067	Inst.addOperand(MCOperand::CreateImm(coproc));
				1068	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1069	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1070	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1071	switch (Inst.getOpcode()) {
				1072	case ARM::LDC_OPTION:
				1073	case ARM::LDCL_OPTION:
				1074	case ARM::LDC2_OPTION:
				1075	case ARM::LDC2L_OPTION:
				1076	case ARM::STC_OPTION:
				1077	case ARM::STCL_OPTION:
				1078	case ARM::STC2_OPTION:
				1079	case ARM::STC2L_OPTION:
				1080	case ARM::LDCL_POST:
				1081	case ARM::STCL_POST:
Owen Anderson	78affc9	2011-08-18 22:47:44 +0000	[diff] [blame]	1082	case ARM::LDC2L_POST:
				1083	case ARM::STC2L_POST:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1084	case ARM::t2LDC_OPTION:
				1085	case ARM::t2LDCL_OPTION:
				1086	case ARM::t2STC_OPTION:
				1087	case ARM::t2STCL_OPTION:
				1088	case ARM::t2LDCL_POST:
				1089	case ARM::t2STCL_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1090	break;
				1091	default:
				1092	Inst.addOperand(MCOperand::CreateReg(0));
				1093	break;
				1094	}
				1095
				1096	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1097	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1098
				1099	bool writeback = (P == 0) \|\| (W == 1);
				1100	unsigned idx_mode = 0;
				1101	if (P && writeback)
				1102	idx_mode = ARMII::IndexModePre;
				1103	else if (!P && writeback)
				1104	idx_mode = ARMII::IndexModePost;
				1105
				1106	switch (Inst.getOpcode()) {
				1107	case ARM::LDCL_POST:
				1108	case ARM::STCL_POST:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1109	case ARM::t2LDCL_POST:
				1110	case ARM::t2STCL_POST:
Owen Anderson	78affc9	2011-08-18 22:47:44 +0000	[diff] [blame]	1111	case ARM::LDC2L_POST:
				1112	case ARM::STC2L_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1113	imm \|= U << 8;
				1114	case ARM::LDC_OPTION:
				1115	case ARM::LDCL_OPTION:
				1116	case ARM::LDC2_OPTION:
				1117	case ARM::LDC2L_OPTION:
				1118	case ARM::STC_OPTION:
				1119	case ARM::STCL_OPTION:
				1120	case ARM::STC2_OPTION:
				1121	case ARM::STC2L_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1122	case ARM::t2LDC_OPTION:
				1123	case ARM::t2LDCL_OPTION:
				1124	case ARM::t2STC_OPTION:
				1125	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1126	Inst.addOperand(MCOperand::CreateImm(imm));
				1127	break;
				1128	default:
				1129	if (U)
				1130	Inst.addOperand(MCOperand::CreateImm(
				1131	ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
				1132	else
				1133	Inst.addOperand(MCOperand::CreateImm(
				1134	ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
				1135	break;
				1136	}
				1137
				1138	switch (Inst.getOpcode()) {
				1139	case ARM::LDC_OFFSET:
				1140	case ARM::LDC_PRE:
				1141	case ARM::LDC_POST:
				1142	case ARM::LDC_OPTION:
				1143	case ARM::LDCL_OFFSET:
				1144	case ARM::LDCL_PRE:
				1145	case ARM::LDCL_POST:
				1146	case ARM::LDCL_OPTION:
				1147	case ARM::STC_OFFSET:
				1148	case ARM::STC_PRE:
				1149	case ARM::STC_POST:
				1150	case ARM::STC_OPTION:
				1151	case ARM::STCL_OFFSET:
				1152	case ARM::STCL_PRE:
				1153	case ARM::STCL_POST:
				1154	case ARM::STCL_OPTION:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1155	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1156	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1157	break;
				1158	default:
				1159	break;
				1160	}
				1161
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1162	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1163	}
				1164
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1165	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1166	DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
				1167	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1168	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1169
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1170	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1171	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				1172	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1173	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				1174	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1175	unsigned reg = fieldFromInstruction32(Insn, 25, 1);
				1176	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1177	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1178
				1179	// On stores, the writeback operand precedes Rt.
				1180	switch (Inst.getOpcode()) {
				1181	case ARM::STR_POST_IMM:
				1182	case ARM::STR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1183	case ARM::STRB_POST_IMM:
				1184	case ARM::STRB_POST_REG:
Jim Grosbach	342ebd5	2011-08-11 22:18:00 +0000	[diff] [blame]	1185	case ARM::STRT_POST_REG:
				1186	case ARM::STRT_POST_IMM:
Jim Grosbach	10348e7	2011-08-11 20:04:56 +0000	[diff] [blame]	1187	case ARM::STRBT_POST_REG:
				1188	case ARM::STRBT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1189	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1190	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1191	break;
				1192	default:
				1193	break;
				1194	}
				1195
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1196	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1197	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1198
				1199	// On loads, the writeback operand comes after Rt.
				1200	switch (Inst.getOpcode()) {
				1201	case ARM::LDR_POST_IMM:
				1202	case ARM::LDR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1203	case ARM::LDRB_POST_IMM:
				1204	case ARM::LDRB_POST_REG:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1205	case ARM::LDRBT_POST_REG:
				1206	case ARM::LDRBT_POST_IMM:
Jim Grosbach	5999926	2011-08-10 23:43:54 +0000	[diff] [blame]	1207	case ARM::LDRT_POST_REG:
				1208	case ARM::LDRT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1209	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1210	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1211	break;
				1212	default:
				1213	break;
				1214	}
				1215
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1216	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1217	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1218
				1219	ARM_AM::AddrOpc Op = ARM_AM::add;
				1220	if (!fieldFromInstruction32(Insn, 23, 1))
				1221	Op = ARM_AM::sub;
				1222
				1223	bool writeback = (P == 0) \|\| (W == 1);
				1224	unsigned idx_mode = 0;
				1225	if (P && writeback)
				1226	idx_mode = ARMII::IndexModePre;
				1227	else if (!P && writeback)
				1228	idx_mode = ARMII::IndexModePost;
				1229
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1230	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1231	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	71156a6	2011-08-11 19:00:18 +0000	[diff] [blame]	1232
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1233	if (reg) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1234	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1235	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1236	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
				1237	switch( fieldFromInstruction32(Insn, 5, 2)) {
				1238	case 0:
				1239	Opc = ARM_AM::lsl;
				1240	break;
				1241	case 1:
				1242	Opc = ARM_AM::lsr;
				1243	break;
				1244	case 2:
				1245	Opc = ARM_AM::asr;
				1246	break;
				1247	case 3:
				1248	Opc = ARM_AM::ror;
				1249	break;
				1250	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1251	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1252	}
				1253	unsigned amt = fieldFromInstruction32(Insn, 7, 5);
				1254	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1255
				1256	Inst.addOperand(MCOperand::CreateImm(imm));
				1257	} else {
				1258	Inst.addOperand(MCOperand::CreateReg(0));
				1259	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1260	Inst.addOperand(MCOperand::CreateImm(tmp));
				1261	}
				1262
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1263	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1264	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1265
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1266	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1267	}
				1268
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1269	static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1270	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1271	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1272
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1273	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				1274	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				1275	unsigned type = fieldFromInstruction32(Val, 5, 2);
				1276	unsigned imm = fieldFromInstruction32(Val, 7, 5);
				1277	unsigned U = fieldFromInstruction32(Val, 12, 1);
				1278
Owen Anderson	51157d2	2011-08-09 21:38:14 +0000	[diff] [blame]	1279	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1280	switch (type) {
				1281	case 0:
				1282	ShOp = ARM_AM::lsl;
				1283	break;
				1284	case 1:
				1285	ShOp = ARM_AM::lsr;
				1286	break;
				1287	case 2:
				1288	ShOp = ARM_AM::asr;
				1289	break;
				1290	case 3:
				1291	ShOp = ARM_AM::ror;
				1292	break;
				1293	}
				1294
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1295	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1296	return MCDisassembler::Fail;
				1297	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1298	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1299	unsigned shift;
				1300	if (U)
				1301	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1302	else
				1303	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1304	Inst.addOperand(MCOperand::CreateImm(shift));
				1305
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1306	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1307	}
				1308
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1309	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1310	DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
				1311	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1312	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1313
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1314	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				1315	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1316	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1317	unsigned type = fieldFromInstruction32(Insn, 22, 1);
				1318	unsigned imm = fieldFromInstruction32(Insn, 8, 4);
				1319	unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
				1320	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1321	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1322	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1323
				1324	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1325
				1326	// For {LD,ST}RD, Rt must be even, else undefined.
				1327	switch (Inst.getOpcode()) {
				1328	case ARM::STRD:
				1329	case ARM::STRD_PRE:
				1330	case ARM::STRD_POST:
				1331	case ARM::LDRD:
				1332	case ARM::LDRD_PRE:
				1333	case ARM::LDRD_POST:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1334	if (Rt & 0x1) return MCDisassembler::Fail;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1335	break;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1336	default:
				1337	break;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1338	}
				1339
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1340	if (writeback) { // Writeback
				1341	if (P)
				1342	U \|= ARMII::IndexModePre << 9;
				1343	else
				1344	U \|= ARMII::IndexModePost << 9;
				1345
				1346	// On stores, the writeback operand precedes Rt.
				1347	switch (Inst.getOpcode()) {
				1348	case ARM::STRD:
				1349	case ARM::STRD_PRE:
				1350	case ARM::STRD_POST:
Owen Anderson	79628e9	2011-08-12 20:02:50 +0000	[diff] [blame]	1351	case ARM::STRH:
				1352	case ARM::STRH_PRE:
				1353	case ARM::STRH_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1354	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1355	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1356	break;
				1357	default:
				1358	break;
				1359	}
				1360	}
				1361
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1362	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1363	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1364	switch (Inst.getOpcode()) {
				1365	case ARM::STRD:
				1366	case ARM::STRD_PRE:
				1367	case ARM::STRD_POST:
				1368	case ARM::LDRD:
				1369	case ARM::LDRD_PRE:
				1370	case ARM::LDRD_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1371	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1372	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1373	break;
				1374	default:
				1375	break;
				1376	}
				1377
				1378	if (writeback) {
				1379	// On loads, the writeback operand comes after Rt.
				1380	switch (Inst.getOpcode()) {
				1381	case ARM::LDRD:
				1382	case ARM::LDRD_PRE:
				1383	case ARM::LDRD_POST:
Owen Anderson	0d09499	2011-08-12 20:36:11 +0000	[diff] [blame]	1384	case ARM::LDRH:
				1385	case ARM::LDRH_PRE:
				1386	case ARM::LDRH_POST:
				1387	case ARM::LDRSH:
				1388	case ARM::LDRSH_PRE:
				1389	case ARM::LDRSH_POST:
				1390	case ARM::LDRSB:
				1391	case ARM::LDRSB_PRE:
				1392	case ARM::LDRSB_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1393	case ARM::LDRHTr:
				1394	case ARM::LDRSBTr:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1395	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1396	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1397	break;
				1398	default:
				1399	break;
				1400	}
				1401	}
				1402
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1403	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1404	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1405
				1406	if (type) {
				1407	Inst.addOperand(MCOperand::CreateReg(0));
				1408	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1409	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1410	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1411	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1412	Inst.addOperand(MCOperand::CreateImm(U));
				1413	}
				1414
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1415	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1416	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1417
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1418	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1419	}
				1420
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1421	static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1422	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1423	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1424
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1425	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1426	unsigned mode = fieldFromInstruction32(Insn, 23, 2);
				1427
				1428	switch (mode) {
				1429	case 0:
				1430	mode = ARM_AM::da;
				1431	break;
				1432	case 1:
				1433	mode = ARM_AM::ia;
				1434	break;
				1435	case 2:
				1436	mode = ARM_AM::db;
				1437	break;
				1438	case 3:
				1439	mode = ARM_AM::ib;
				1440	break;
				1441	}
				1442
				1443	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1444	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1445	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1446
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1447	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1448	}
				1449
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1450	static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1451	unsigned Insn,
				1452	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1453	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1454
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1455	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1456	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1457	unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
				1458
				1459	if (pred == 0xF) {
				1460	switch (Inst.getOpcode()) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1461	case ARM::LDMDA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1462	Inst.setOpcode(ARM::RFEDA);
				1463	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1464	case ARM::LDMDA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1465	Inst.setOpcode(ARM::RFEDA_UPD);
				1466	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1467	case ARM::LDMDB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1468	Inst.setOpcode(ARM::RFEDB);
				1469	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1470	case ARM::LDMDB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1471	Inst.setOpcode(ARM::RFEDB_UPD);
				1472	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1473	case ARM::LDMIA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1474	Inst.setOpcode(ARM::RFEIA);
				1475	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1476	case ARM::LDMIA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1477	Inst.setOpcode(ARM::RFEIA_UPD);
				1478	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1479	case ARM::LDMIB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1480	Inst.setOpcode(ARM::RFEIB);
				1481	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1482	case ARM::LDMIB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1483	Inst.setOpcode(ARM::RFEIB_UPD);
				1484	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1485	case ARM::STMDA:
				1486	Inst.setOpcode(ARM::SRSDA);
				1487	break;
				1488	case ARM::STMDA_UPD:
				1489	Inst.setOpcode(ARM::SRSDA_UPD);
				1490	break;
				1491	case ARM::STMDB:
				1492	Inst.setOpcode(ARM::SRSDB);
				1493	break;
				1494	case ARM::STMDB_UPD:
				1495	Inst.setOpcode(ARM::SRSDB_UPD);
				1496	break;
				1497	case ARM::STMIA:
				1498	Inst.setOpcode(ARM::SRSIA);
				1499	break;
				1500	case ARM::STMIA_UPD:
				1501	Inst.setOpcode(ARM::SRSIA_UPD);
				1502	break;
				1503	case ARM::STMIB:
				1504	Inst.setOpcode(ARM::SRSIB);
				1505	break;
				1506	case ARM::STMIB_UPD:
				1507	Inst.setOpcode(ARM::SRSIB_UPD);
				1508	break;
				1509	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1510	if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1511	}
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1512
				1513	// For stores (which become SRS's, the only operand is the mode.
				1514	if (fieldFromInstruction32(Insn, 20, 1) == 0) {
				1515	Inst.addOperand(
				1516	MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
				1517	return S;
				1518	}
				1519
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1520	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1521	}
				1522
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1523	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1524	return MCDisassembler::Fail;
				1525	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1526	return MCDisassembler::Fail; // Tied
				1527	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1528	return MCDisassembler::Fail;
				1529	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1530	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1531
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1532	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1533	}
				1534
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1535	static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1536	uint64_t Address, const void *Decoder) {
				1537	unsigned imod = fieldFromInstruction32(Insn, 18, 2);
				1538	unsigned M = fieldFromInstruction32(Insn, 17, 1);
				1539	unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
				1540	unsigned mode = fieldFromInstruction32(Insn, 0, 5);
				1541
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1542	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	1543
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1544	// imod == '01' --> UNPREDICTABLE
				1545	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1546	// return failure here. The '01' imod value is unprintable, so there's
				1547	// nothing useful we could do even if we returned UNPREDICTABLE.
				1548
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1549	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1550
				1551	if (imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1552	Inst.setOpcode(ARM::CPS3p);
				1553	Inst.addOperand(MCOperand::CreateImm(imod));
				1554	Inst.addOperand(MCOperand::CreateImm(iflags));
				1555	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1556	} else if (imod && !M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1557	Inst.setOpcode(ARM::CPS2p);
				1558	Inst.addOperand(MCOperand::CreateImm(imod));
				1559	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1560	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1561	} else if (!imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1562	Inst.setOpcode(ARM::CPS1p);
				1563	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1564	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1565	} else {
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1566	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1567	Inst.setOpcode(ARM::CPS1p);
				1568	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1569	S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1570	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1571
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1572	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1573	}
				1574
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1575	static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1576	uint64_t Address, const void *Decoder) {
				1577	unsigned imod = fieldFromInstruction32(Insn, 9, 2);
				1578	unsigned M = fieldFromInstruction32(Insn, 8, 1);
				1579	unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
				1580	unsigned mode = fieldFromInstruction32(Insn, 0, 5);
				1581
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1582	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1583
				1584	// imod == '01' --> UNPREDICTABLE
				1585	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1586	// return failure here. The '01' imod value is unprintable, so there's
				1587	// nothing useful we could do even if we returned UNPREDICTABLE.
				1588
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1589	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1590
				1591	if (imod && M) {
				1592	Inst.setOpcode(ARM::t2CPS3p);
				1593	Inst.addOperand(MCOperand::CreateImm(imod));
				1594	Inst.addOperand(MCOperand::CreateImm(iflags));
				1595	Inst.addOperand(MCOperand::CreateImm(mode));
				1596	} else if (imod && !M) {
				1597	Inst.setOpcode(ARM::t2CPS2p);
				1598	Inst.addOperand(MCOperand::CreateImm(imod));
				1599	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1600	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1601	} else if (!imod && M) {
				1602	Inst.setOpcode(ARM::t2CPS1p);
				1603	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1604	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1605	} else {
				1606	// imod == '00' && M == '0' --> UNPREDICTABLE
				1607	Inst.setOpcode(ARM::t2CPS1p);
				1608	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1609	S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1610	}
				1611
				1612	return S;
				1613	}
				1614
				1615
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1616	static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1617	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1618	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1619
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1620	unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
				1621	unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
				1622	unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
				1623	unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
				1624	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1625
				1626	if (pred == 0xF)
				1627	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1628
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1629	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1630	return MCDisassembler::Fail;
				1631	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1632	return MCDisassembler::Fail;
				1633	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1634	return MCDisassembler::Fail;
				1635	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				1636	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1637
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1638	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1639	return MCDisassembler::Fail;
Owen Anderson	1fb6673	2011-08-11 22:05:38 +0000	[diff] [blame]	1640
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1641	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1642	}
				1643
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1644	static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1645	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1646	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1647
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1648	unsigned add = fieldFromInstruction32(Val, 12, 1);
				1649	unsigned imm = fieldFromInstruction32(Val, 0, 12);
				1650	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				1651
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1652	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1653	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1654
				1655	if (!add) imm *= -1;
				1656	if (imm == 0 && !add) imm = INT32_MIN;
				1657	Inst.addOperand(MCOperand::CreateImm(imm));
				1658
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1659	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1660	}
				1661
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1662	static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1663	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1664	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1665
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1666	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				1667	unsigned U = fieldFromInstruction32(Val, 8, 1);
				1668	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				1669
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1670	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1671	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1672
				1673	if (U)
				1674	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				1675	else
				1676	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				1677
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1678	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1679	}
				1680
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1681	static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1682	uint64_t Address, const void *Decoder) {
				1683	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				1684	}
				1685
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1686	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1687	DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
				1688	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1689	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1690
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1691	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1692	unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
				1693
				1694	if (pred == 0xF) {
				1695	Inst.setOpcode(ARM::BLXi);
				1696	imm \|= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	1697	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1698	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1699	}
				1700
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	1701	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1702	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1703	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1704
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1705	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1706	}
				1707
				1708
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1709	static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1710	uint64_t Address, const void *Decoder) {
				1711	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1712	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1713	}
				1714
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1715	static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1716	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1717	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1718
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1719	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				1720	unsigned align = fieldFromInstruction32(Val, 4, 2);
				1721
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1722	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1723	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1724	if (!align)
				1725	Inst.addOperand(MCOperand::CreateImm(0));
				1726	else
				1727	Inst.addOperand(MCOperand::CreateImm(4 << align));
				1728
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1729	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1730	}
				1731
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1732	static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1733	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1734	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1735
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1736	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				1737	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				1738	unsigned wb = fieldFromInstruction32(Insn, 16, 4);
				1739	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1740	Rn \|= fieldFromInstruction32(Insn, 4, 2) << 4;
				1741	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1742
				1743	// First output register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1744	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				1745	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1746
				1747	// Second output register
				1748	switch (Inst.getOpcode()) {
				1749	case ARM::VLD1q8:
				1750	case ARM::VLD1q16:
				1751	case ARM::VLD1q32:
				1752	case ARM::VLD1q64:
				1753	case ARM::VLD1q8_UPD:
				1754	case ARM::VLD1q16_UPD:
				1755	case ARM::VLD1q32_UPD:
				1756	case ARM::VLD1q64_UPD:
				1757	case ARM::VLD1d8T:
				1758	case ARM::VLD1d16T:
				1759	case ARM::VLD1d32T:
				1760	case ARM::VLD1d64T:
				1761	case ARM::VLD1d8T_UPD:
				1762	case ARM::VLD1d16T_UPD:
				1763	case ARM::VLD1d32T_UPD:
				1764	case ARM::VLD1d64T_UPD:
				1765	case ARM::VLD1d8Q:
				1766	case ARM::VLD1d16Q:
				1767	case ARM::VLD1d32Q:
				1768	case ARM::VLD1d64Q:
				1769	case ARM::VLD1d8Q_UPD:
				1770	case ARM::VLD1d16Q_UPD:
				1771	case ARM::VLD1d32Q_UPD:
				1772	case ARM::VLD1d64Q_UPD:
				1773	case ARM::VLD2d8:
				1774	case ARM::VLD2d16:
				1775	case ARM::VLD2d32:
				1776	case ARM::VLD2d8_UPD:
				1777	case ARM::VLD2d16_UPD:
				1778	case ARM::VLD2d32_UPD:
				1779	case ARM::VLD2q8:
				1780	case ARM::VLD2q16:
				1781	case ARM::VLD2q32:
				1782	case ARM::VLD2q8_UPD:
				1783	case ARM::VLD2q16_UPD:
				1784	case ARM::VLD2q32_UPD:
				1785	case ARM::VLD3d8:
				1786	case ARM::VLD3d16:
				1787	case ARM::VLD3d32:
				1788	case ARM::VLD3d8_UPD:
				1789	case ARM::VLD3d16_UPD:
				1790	case ARM::VLD3d32_UPD:
				1791	case ARM::VLD4d8:
				1792	case ARM::VLD4d16:
				1793	case ARM::VLD4d32:
				1794	case ARM::VLD4d8_UPD:
				1795	case ARM::VLD4d16_UPD:
				1796	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1797	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				1798	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1799	break;
				1800	case ARM::VLD2b8:
				1801	case ARM::VLD2b16:
				1802	case ARM::VLD2b32:
				1803	case ARM::VLD2b8_UPD:
				1804	case ARM::VLD2b16_UPD:
				1805	case ARM::VLD2b32_UPD:
				1806	case ARM::VLD3q8:
				1807	case ARM::VLD3q16:
				1808	case ARM::VLD3q32:
				1809	case ARM::VLD3q8_UPD:
				1810	case ARM::VLD3q16_UPD:
				1811	case ARM::VLD3q32_UPD:
				1812	case ARM::VLD4q8:
				1813	case ARM::VLD4q16:
				1814	case ARM::VLD4q32:
				1815	case ARM::VLD4q8_UPD:
				1816	case ARM::VLD4q16_UPD:
				1817	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1818	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				1819	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1820	default:
				1821	break;
				1822	}
				1823
				1824	// Third output register
				1825	switch(Inst.getOpcode()) {
				1826	case ARM::VLD1d8T:
				1827	case ARM::VLD1d16T:
				1828	case ARM::VLD1d32T:
				1829	case ARM::VLD1d64T:
				1830	case ARM::VLD1d8T_UPD:
				1831	case ARM::VLD1d16T_UPD:
				1832	case ARM::VLD1d32T_UPD:
				1833	case ARM::VLD1d64T_UPD:
				1834	case ARM::VLD1d8Q:
				1835	case ARM::VLD1d16Q:
				1836	case ARM::VLD1d32Q:
				1837	case ARM::VLD1d64Q:
				1838	case ARM::VLD1d8Q_UPD:
				1839	case ARM::VLD1d16Q_UPD:
				1840	case ARM::VLD1d32Q_UPD:
				1841	case ARM::VLD1d64Q_UPD:
				1842	case ARM::VLD2q8:
				1843	case ARM::VLD2q16:
				1844	case ARM::VLD2q32:
				1845	case ARM::VLD2q8_UPD:
				1846	case ARM::VLD2q16_UPD:
				1847	case ARM::VLD2q32_UPD:
				1848	case ARM::VLD3d8:
				1849	case ARM::VLD3d16:
				1850	case ARM::VLD3d32:
				1851	case ARM::VLD3d8_UPD:
				1852	case ARM::VLD3d16_UPD:
				1853	case ARM::VLD3d32_UPD:
				1854	case ARM::VLD4d8:
				1855	case ARM::VLD4d16:
				1856	case ARM::VLD4d32:
				1857	case ARM::VLD4d8_UPD:
				1858	case ARM::VLD4d16_UPD:
				1859	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1860	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				1861	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1862	break;
				1863	case ARM::VLD3q8:
				1864	case ARM::VLD3q16:
				1865	case ARM::VLD3q32:
				1866	case ARM::VLD3q8_UPD:
				1867	case ARM::VLD3q16_UPD:
				1868	case ARM::VLD3q32_UPD:
				1869	case ARM::VLD4q8:
				1870	case ARM::VLD4q16:
				1871	case ARM::VLD4q32:
				1872	case ARM::VLD4q8_UPD:
				1873	case ARM::VLD4q16_UPD:
				1874	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1875	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				1876	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1877	break;
				1878	default:
				1879	break;
				1880	}
				1881
				1882	// Fourth output register
				1883	switch (Inst.getOpcode()) {
				1884	case ARM::VLD1d8Q:
				1885	case ARM::VLD1d16Q:
				1886	case ARM::VLD1d32Q:
				1887	case ARM::VLD1d64Q:
				1888	case ARM::VLD1d8Q_UPD:
				1889	case ARM::VLD1d16Q_UPD:
				1890	case ARM::VLD1d32Q_UPD:
				1891	case ARM::VLD1d64Q_UPD:
				1892	case ARM::VLD2q8:
				1893	case ARM::VLD2q16:
				1894	case ARM::VLD2q32:
				1895	case ARM::VLD2q8_UPD:
				1896	case ARM::VLD2q16_UPD:
				1897	case ARM::VLD2q32_UPD:
				1898	case ARM::VLD4d8:
				1899	case ARM::VLD4d16:
				1900	case ARM::VLD4d32:
				1901	case ARM::VLD4d8_UPD:
				1902	case ARM::VLD4d16_UPD:
				1903	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1904	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				1905	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1906	break;
				1907	case ARM::VLD4q8:
				1908	case ARM::VLD4q16:
				1909	case ARM::VLD4q32:
				1910	case ARM::VLD4q8_UPD:
				1911	case ARM::VLD4q16_UPD:
				1912	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1913	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				1914	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1915	break;
				1916	default:
				1917	break;
				1918	}
				1919
				1920	// Writeback operand
				1921	switch (Inst.getOpcode()) {
				1922	case ARM::VLD1d8_UPD:
				1923	case ARM::VLD1d16_UPD:
				1924	case ARM::VLD1d32_UPD:
				1925	case ARM::VLD1d64_UPD:
				1926	case ARM::VLD1q8_UPD:
				1927	case ARM::VLD1q16_UPD:
				1928	case ARM::VLD1q32_UPD:
				1929	case ARM::VLD1q64_UPD:
				1930	case ARM::VLD1d8T_UPD:
				1931	case ARM::VLD1d16T_UPD:
				1932	case ARM::VLD1d32T_UPD:
				1933	case ARM::VLD1d64T_UPD:
				1934	case ARM::VLD1d8Q_UPD:
				1935	case ARM::VLD1d16Q_UPD:
				1936	case ARM::VLD1d32Q_UPD:
				1937	case ARM::VLD1d64Q_UPD:
				1938	case ARM::VLD2d8_UPD:
				1939	case ARM::VLD2d16_UPD:
				1940	case ARM::VLD2d32_UPD:
				1941	case ARM::VLD2q8_UPD:
				1942	case ARM::VLD2q16_UPD:
				1943	case ARM::VLD2q32_UPD:
				1944	case ARM::VLD2b8_UPD:
				1945	case ARM::VLD2b16_UPD:
				1946	case ARM::VLD2b32_UPD:
				1947	case ARM::VLD3d8_UPD:
				1948	case ARM::VLD3d16_UPD:
				1949	case ARM::VLD3d32_UPD:
				1950	case ARM::VLD3q8_UPD:
				1951	case ARM::VLD3q16_UPD:
				1952	case ARM::VLD3q32_UPD:
				1953	case ARM::VLD4d8_UPD:
				1954	case ARM::VLD4d16_UPD:
				1955	case ARM::VLD4d32_UPD:
				1956	case ARM::VLD4q8_UPD:
				1957	case ARM::VLD4q16_UPD:
				1958	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1959	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				1960	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1961	break;
				1962	default:
				1963	break;
				1964	}
				1965
				1966	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1967	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				1968	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1969
				1970	// AddrMode6 Offset (register)
				1971	if (Rm == 0xD)
				1972	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1973	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1974	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1975	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1976	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1977
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1978	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1979	}
				1980
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1981	static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1982	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1983	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1984
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1985	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				1986	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				1987	unsigned wb = fieldFromInstruction32(Insn, 16, 4);
				1988	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1989	Rn \|= fieldFromInstruction32(Insn, 4, 2) << 4;
				1990	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1991
				1992	// Writeback Operand
				1993	switch (Inst.getOpcode()) {
				1994	case ARM::VST1d8_UPD:
				1995	case ARM::VST1d16_UPD:
				1996	case ARM::VST1d32_UPD:
				1997	case ARM::VST1d64_UPD:
				1998	case ARM::VST1q8_UPD:
				1999	case ARM::VST1q16_UPD:
				2000	case ARM::VST1q32_UPD:
				2001	case ARM::VST1q64_UPD:
				2002	case ARM::VST1d8T_UPD:
				2003	case ARM::VST1d16T_UPD:
				2004	case ARM::VST1d32T_UPD:
				2005	case ARM::VST1d64T_UPD:
				2006	case ARM::VST1d8Q_UPD:
				2007	case ARM::VST1d16Q_UPD:
				2008	case ARM::VST1d32Q_UPD:
				2009	case ARM::VST1d64Q_UPD:
				2010	case ARM::VST2d8_UPD:
				2011	case ARM::VST2d16_UPD:
				2012	case ARM::VST2d32_UPD:
				2013	case ARM::VST2q8_UPD:
				2014	case ARM::VST2q16_UPD:
				2015	case ARM::VST2q32_UPD:
				2016	case ARM::VST2b8_UPD:
				2017	case ARM::VST2b16_UPD:
				2018	case ARM::VST2b32_UPD:
				2019	case ARM::VST3d8_UPD:
				2020	case ARM::VST3d16_UPD:
				2021	case ARM::VST3d32_UPD:
				2022	case ARM::VST3q8_UPD:
				2023	case ARM::VST3q16_UPD:
				2024	case ARM::VST3q32_UPD:
				2025	case ARM::VST4d8_UPD:
				2026	case ARM::VST4d16_UPD:
				2027	case ARM::VST4d32_UPD:
				2028	case ARM::VST4q8_UPD:
				2029	case ARM::VST4q16_UPD:
				2030	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2031	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2032	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2033	break;
				2034	default:
				2035	break;
				2036	}
				2037
				2038	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2039	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2040	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2041
				2042	// AddrMode6 Offset (register)
				2043	if (Rm == 0xD)
				2044	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2045	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2046	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2047	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2048	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2049
				2050	// First input register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2051	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2052	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2053
				2054	// Second input register
				2055	switch (Inst.getOpcode()) {
				2056	case ARM::VST1q8:
				2057	case ARM::VST1q16:
				2058	case ARM::VST1q32:
				2059	case ARM::VST1q64:
				2060	case ARM::VST1q8_UPD:
				2061	case ARM::VST1q16_UPD:
				2062	case ARM::VST1q32_UPD:
				2063	case ARM::VST1q64_UPD:
				2064	case ARM::VST1d8T:
				2065	case ARM::VST1d16T:
				2066	case ARM::VST1d32T:
				2067	case ARM::VST1d64T:
				2068	case ARM::VST1d8T_UPD:
				2069	case ARM::VST1d16T_UPD:
				2070	case ARM::VST1d32T_UPD:
				2071	case ARM::VST1d64T_UPD:
				2072	case ARM::VST1d8Q:
				2073	case ARM::VST1d16Q:
				2074	case ARM::VST1d32Q:
				2075	case ARM::VST1d64Q:
				2076	case ARM::VST1d8Q_UPD:
				2077	case ARM::VST1d16Q_UPD:
				2078	case ARM::VST1d32Q_UPD:
				2079	case ARM::VST1d64Q_UPD:
				2080	case ARM::VST2d8:
				2081	case ARM::VST2d16:
				2082	case ARM::VST2d32:
				2083	case ARM::VST2d8_UPD:
				2084	case ARM::VST2d16_UPD:
				2085	case ARM::VST2d32_UPD:
				2086	case ARM::VST2q8:
				2087	case ARM::VST2q16:
				2088	case ARM::VST2q32:
				2089	case ARM::VST2q8_UPD:
				2090	case ARM::VST2q16_UPD:
				2091	case ARM::VST2q32_UPD:
				2092	case ARM::VST3d8:
				2093	case ARM::VST3d16:
				2094	case ARM::VST3d32:
				2095	case ARM::VST3d8_UPD:
				2096	case ARM::VST3d16_UPD:
				2097	case ARM::VST3d32_UPD:
				2098	case ARM::VST4d8:
				2099	case ARM::VST4d16:
				2100	case ARM::VST4d32:
				2101	case ARM::VST4d8_UPD:
				2102	case ARM::VST4d16_UPD:
				2103	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2104	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2105	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2106	break;
				2107	case ARM::VST2b8:
				2108	case ARM::VST2b16:
				2109	case ARM::VST2b32:
				2110	case ARM::VST2b8_UPD:
				2111	case ARM::VST2b16_UPD:
				2112	case ARM::VST2b32_UPD:
				2113	case ARM::VST3q8:
				2114	case ARM::VST3q16:
				2115	case ARM::VST3q32:
				2116	case ARM::VST3q8_UPD:
				2117	case ARM::VST3q16_UPD:
				2118	case ARM::VST3q32_UPD:
				2119	case ARM::VST4q8:
				2120	case ARM::VST4q16:
				2121	case ARM::VST4q32:
				2122	case ARM::VST4q8_UPD:
				2123	case ARM::VST4q16_UPD:
				2124	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2125	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2126	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2127	break;
				2128	default:
				2129	break;
				2130	}
				2131
				2132	// Third input register
				2133	switch (Inst.getOpcode()) {
				2134	case ARM::VST1d8T:
				2135	case ARM::VST1d16T:
				2136	case ARM::VST1d32T:
				2137	case ARM::VST1d64T:
				2138	case ARM::VST1d8T_UPD:
				2139	case ARM::VST1d16T_UPD:
				2140	case ARM::VST1d32T_UPD:
				2141	case ARM::VST1d64T_UPD:
				2142	case ARM::VST1d8Q:
				2143	case ARM::VST1d16Q:
				2144	case ARM::VST1d32Q:
				2145	case ARM::VST1d64Q:
				2146	case ARM::VST1d8Q_UPD:
				2147	case ARM::VST1d16Q_UPD:
				2148	case ARM::VST1d32Q_UPD:
				2149	case ARM::VST1d64Q_UPD:
				2150	case ARM::VST2q8:
				2151	case ARM::VST2q16:
				2152	case ARM::VST2q32:
				2153	case ARM::VST2q8_UPD:
				2154	case ARM::VST2q16_UPD:
				2155	case ARM::VST2q32_UPD:
				2156	case ARM::VST3d8:
				2157	case ARM::VST3d16:
				2158	case ARM::VST3d32:
				2159	case ARM::VST3d8_UPD:
				2160	case ARM::VST3d16_UPD:
				2161	case ARM::VST3d32_UPD:
				2162	case ARM::VST4d8:
				2163	case ARM::VST4d16:
				2164	case ARM::VST4d32:
				2165	case ARM::VST4d8_UPD:
				2166	case ARM::VST4d16_UPD:
				2167	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2168	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2169	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2170	break;
				2171	case ARM::VST3q8:
				2172	case ARM::VST3q16:
				2173	case ARM::VST3q32:
				2174	case ARM::VST3q8_UPD:
				2175	case ARM::VST3q16_UPD:
				2176	case ARM::VST3q32_UPD:
				2177	case ARM::VST4q8:
				2178	case ARM::VST4q16:
				2179	case ARM::VST4q32:
				2180	case ARM::VST4q8_UPD:
				2181	case ARM::VST4q16_UPD:
				2182	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2183	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2184	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2185	break;
				2186	default:
				2187	break;
				2188	}
				2189
				2190	// Fourth input register
				2191	switch (Inst.getOpcode()) {
				2192	case ARM::VST1d8Q:
				2193	case ARM::VST1d16Q:
				2194	case ARM::VST1d32Q:
				2195	case ARM::VST1d64Q:
				2196	case ARM::VST1d8Q_UPD:
				2197	case ARM::VST1d16Q_UPD:
				2198	case ARM::VST1d32Q_UPD:
				2199	case ARM::VST1d64Q_UPD:
				2200	case ARM::VST2q8:
				2201	case ARM::VST2q16:
				2202	case ARM::VST2q32:
				2203	case ARM::VST2q8_UPD:
				2204	case ARM::VST2q16_UPD:
				2205	case ARM::VST2q32_UPD:
				2206	case ARM::VST4d8:
				2207	case ARM::VST4d16:
				2208	case ARM::VST4d32:
				2209	case ARM::VST4d8_UPD:
				2210	case ARM::VST4d16_UPD:
				2211	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2212	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2213	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2214	break;
				2215	case ARM::VST4q8:
				2216	case ARM::VST4q16:
				2217	case ARM::VST4q32:
				2218	case ARM::VST4q8_UPD:
				2219	case ARM::VST4q16_UPD:
				2220	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2221	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2222	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2223	break;
				2224	default:
				2225	break;
				2226	}
				2227
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2228	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2229	}
				2230
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2231	static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2232	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2233	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2234
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2235	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2236	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2237	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2238	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2239	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2240	unsigned size = fieldFromInstruction32(Insn, 6, 2);
				2241	unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
				2242
				2243	align *= (1 << size);
				2244
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2245	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2246	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2247	if (regs == 2) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2248	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2249	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2250	}
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2251	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2252	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2253	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2254	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2255
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2256	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2257	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2258	Inst.addOperand(MCOperand::CreateImm(align));
				2259
				2260	if (Rm == 0xD)
				2261	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2262	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2263	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2264	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2265	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2266
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2267	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2268	}
				2269
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2270	static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2271	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2272	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2273
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2274	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2275	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2276	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2277	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2278	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2279	unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
				2280	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2281	align = 2size;
				2282
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2283	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2284	return MCDisassembler::Fail;
				2285	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2286	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2287	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2288	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2289	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2290	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2291
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2292	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2293	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2294	Inst.addOperand(MCOperand::CreateImm(align));
				2295
				2296	if (Rm == 0xD)
				2297	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2298	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2299	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2300	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2301	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2302
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2303	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2304	}
				2305
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2306	static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2307	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2308	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2309
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2310	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2311	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2312	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2313	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2314	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2315
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2316	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2317	return MCDisassembler::Fail;
				2318	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2319	return MCDisassembler::Fail;
				2320	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2321	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2322	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2323	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2324	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2325	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2326
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2327	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2328	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2329	Inst.addOperand(MCOperand::CreateImm(0));
				2330
				2331	if (Rm == 0xD)
				2332	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2333	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2334	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2335	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2336	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2337
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2338	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2339	}
				2340
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2341	static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2342	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2343	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2344
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2345	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2346	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2347	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2348	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2349	unsigned size = fieldFromInstruction32(Insn, 6, 2);
				2350	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2351	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2352
				2353	if (size == 0x3) {
				2354	size = 4;
				2355	align = 16;
				2356	} else {
				2357	if (size == 2) {
				2358	size = 1 << size;
				2359	align *= 8;
				2360	} else {
				2361	size = 1 << size;
				2362	align = 4size;
				2363	}
				2364	}
				2365
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2366	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2367	return MCDisassembler::Fail;
				2368	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2369	return MCDisassembler::Fail;
				2370	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2371	return MCDisassembler::Fail;
				2372	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2373	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2374	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2375	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2376	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2377	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2378
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2379	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2380	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2381	Inst.addOperand(MCOperand::CreateImm(align));
				2382
				2383	if (Rm == 0xD)
				2384	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2385	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2386	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2387	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2388	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2389
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2390	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2391	}
				2392
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2393	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2394	DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
				2395	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2396	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2397
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2398	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2399	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2400	unsigned imm = fieldFromInstruction32(Insn, 0, 4);
				2401	imm \|= fieldFromInstruction32(Insn, 16, 3) << 4;
				2402	imm \|= fieldFromInstruction32(Insn, 24, 1) << 7;
				2403	imm \|= fieldFromInstruction32(Insn, 8, 4) << 8;
				2404	imm \|= fieldFromInstruction32(Insn, 5, 1) << 12;
				2405	unsigned Q = fieldFromInstruction32(Insn, 6, 1);
				2406
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2407	if (Q) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2408	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2409	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2410	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2411	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2412	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2413	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2414
				2415	Inst.addOperand(MCOperand::CreateImm(imm));
				2416
				2417	switch (Inst.getOpcode()) {
				2418	case ARM::VORRiv4i16:
				2419	case ARM::VORRiv2i32:
				2420	case ARM::VBICiv4i16:
				2421	case ARM::VBICiv2i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2422	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2423	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2424	break;
				2425	case ARM::VORRiv8i16:
				2426	case ARM::VORRiv4i32:
				2427	case ARM::VBICiv8i16:
				2428	case ARM::VBICiv4i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2429	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2430	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2431	break;
				2432	default:
				2433	break;
				2434	}
				2435
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2436	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2437	}
				2438
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2439	static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2440	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2441	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2442
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2443	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2444	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2445	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2446	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				2447	unsigned size = fieldFromInstruction32(Insn, 18, 2);
				2448
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2449	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2450	return MCDisassembler::Fail;
				2451	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2452	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2453	Inst.addOperand(MCOperand::CreateImm(8 << size));
				2454
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2455	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2456	}
				2457
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2458	static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2459	uint64_t Address, const void *Decoder) {
				2460	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2461	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2462	}
				2463
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2464	static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2465	uint64_t Address, const void *Decoder) {
				2466	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2467	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2468	}
				2469
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2470	static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2471	uint64_t Address, const void *Decoder) {
				2472	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2473	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2474	}
				2475
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2476	static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2477	uint64_t Address, const void *Decoder) {
				2478	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2479	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2480	}
				2481
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2482	static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2483	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2484	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2485
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2486	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2487	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2488	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2489	Rn \|= fieldFromInstruction32(Insn, 7, 1) << 4;
				2490	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2491	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				2492	unsigned op = fieldFromInstruction32(Insn, 6, 1);
				2493	unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
				2494
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2495	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2496	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2497	if (op) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2498	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2499	return MCDisassembler::Fail; // Writeback
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2500	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2501
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2502	for (unsigned i = 0; i < length; ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2503	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
				2504	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2505	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2506
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2507	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2508	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2509
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2510	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2511	}
				2512
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2513	static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2514	uint64_t Address, const void *Decoder) {
				2515	// The immediate needs to be a fully instantiated float. However, the
				2516	// auto-generated decoder is only able to fill in some of the bits
				2517	// necessary. For instance, the 'b' bit is replicated multiple times,
				2518	// and is even present in inverted form in one bit. We do a little
				2519	// binary parsing here to fill in those missing bits, and then
				2520	// reinterpret it all as a float.
				2521	union {
				2522	uint32_t integer;
				2523	float fp;
				2524	} fp_conv;
				2525
				2526	fp_conv.integer = Val;
				2527	uint32_t b = fieldFromInstruction32(Val, 25, 1);
				2528	fp_conv.integer \|= b << 26;
				2529	fp_conv.integer \|= b << 27;
				2530	fp_conv.integer \|= b << 28;
				2531	fp_conv.integer \|= b << 29;
				2532	fp_conv.integer \|= (~b & 0x1) << 30;
				2533
				2534	Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2535	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2536	}
				2537
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2538	static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2539	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2540	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2541
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2542	unsigned dst = fieldFromInstruction16(Insn, 8, 3);
				2543	unsigned imm = fieldFromInstruction16(Insn, 0, 8);
				2544
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2545	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				2546	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2547
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2548	switch(Inst.getOpcode()) {
Owen Anderson	1af7f72	2011-08-26 19:39:26 +0000	[diff] [blame]	2549	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2550	return MCDisassembler::Fail;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2551	case ARM::tADR:
Owen Anderson	9f7e831	2011-08-26 21:47:57 +0000	[diff] [blame]	2552	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2553	case ARM::tADDrSPi:
				2554	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2555	break;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2556	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2557
				2558	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2559	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2560	}
				2561
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2562	static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2563	uint64_t Address, const void *Decoder) {
				2564	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2565	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2566	}
				2567
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2568	static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2569	uint64_t Address, const void *Decoder) {
				2570	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2571	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2572	}
				2573
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2574	static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2575	uint64_t Address, const void *Decoder) {
				2576	Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2577	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2578	}
				2579
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2580	static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2581	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2582	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2583
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2584	unsigned Rn = fieldFromInstruction32(Val, 0, 3);
				2585	unsigned Rm = fieldFromInstruction32(Val, 3, 3);
				2586
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2587	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2588	return MCDisassembler::Fail;
				2589	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2590	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2591
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2592	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2593	}
				2594
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2595	static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2596	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2597	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2598
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2599	unsigned Rn = fieldFromInstruction32(Val, 0, 3);
				2600	unsigned imm = fieldFromInstruction32(Val, 3, 5);
				2601
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2602	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2603	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2604	Inst.addOperand(MCOperand::CreateImm(imm));
				2605
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2606	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2607	}
				2608
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2609	static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2610	uint64_t Address, const void *Decoder) {
				2611	Inst.addOperand(MCOperand::CreateImm(Val << 2));
				2612
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2613	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2614	}
				2615
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2616	static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2617	uint64_t Address, const void *Decoder) {
				2618	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b113ec5	2011-08-22 17:56:58 +0000	[diff] [blame]	2619	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2620
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2621	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2622	}
				2623
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2624	static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2625	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2626	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2627
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2628	unsigned Rn = fieldFromInstruction32(Val, 6, 4);
				2629	unsigned Rm = fieldFromInstruction32(Val, 2, 4);
				2630	unsigned imm = fieldFromInstruction32(Val, 0, 2);
				2631
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2632	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2633	return MCDisassembler::Fail;
				2634	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2635	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2636	Inst.addOperand(MCOperand::CreateImm(imm));
				2637
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2638	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2639	}
				2640
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2641	static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2642	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2643	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2644
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	2645	switch (Inst.getOpcode()) {
				2646	case ARM::t2PLDs:
				2647	case ARM::t2PLDWs:
				2648	case ARM::t2PLIs:
				2649	break;
				2650	default: {
				2651	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2652	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				2653	return MCDisassembler::Fail;
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	2654	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2655	}
				2656
				2657	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2658	if (Rn == 0xF) {
				2659	switch (Inst.getOpcode()) {
				2660	case ARM::t2LDRBs:
				2661	Inst.setOpcode(ARM::t2LDRBpci);
				2662	break;
				2663	case ARM::t2LDRHs:
				2664	Inst.setOpcode(ARM::t2LDRHpci);
				2665	break;
				2666	case ARM::t2LDRSHs:
				2667	Inst.setOpcode(ARM::t2LDRSHpci);
				2668	break;
				2669	case ARM::t2LDRSBs:
				2670	Inst.setOpcode(ARM::t2LDRSBpci);
				2671	break;
				2672	case ARM::t2PLDs:
				2673	Inst.setOpcode(ARM::t2PLDi12);
				2674	Inst.addOperand(MCOperand::CreateReg(ARM::PC));
				2675	break;
				2676	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2677	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2678	}
				2679
				2680	int imm = fieldFromInstruction32(Insn, 0, 12);
				2681	if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
				2682	Inst.addOperand(MCOperand::CreateImm(imm));
				2683
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2684	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2685	}
				2686
				2687	unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
				2688	addrmode \|= fieldFromInstruction32(Insn, 0, 4) << 2;
				2689	addrmode \|= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2690	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				2691	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2692
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2693	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2694	}
				2695
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2696	static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2697	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2698	int imm = Val & 0xFF;
				2699	if (!(Val & 0x100)) imm *= -1;
				2700	Inst.addOperand(MCOperand::CreateImm(imm << 2));
				2701
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2702	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2703	}
				2704
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2705	static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2706	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2707	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2708
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2709	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				2710	unsigned imm = fieldFromInstruction32(Val, 0, 9);
				2711
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2712	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2713	return MCDisassembler::Fail;
				2714	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				2715	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2716
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2717	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2718	}
				2719
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	2720	static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
				2721	uint64_t Address, const void *Decoder) {
				2722	DecodeStatus S = MCDisassembler::Success;
				2723
				2724	unsigned Rn = fieldFromInstruction32(Val, 8, 4);
				2725	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				2726
				2727	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2728	return MCDisassembler::Fail;
				2729
				2730	Inst.addOperand(MCOperand::CreateImm(imm));
				2731
				2732	return S;
				2733	}
				2734
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2735	static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2736	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2737	int imm = Val & 0xFF;
Owen Anderson	705b48f	2011-09-16 21:08:33 +0000	[diff] [blame]	2738	if (Val == 0)
				2739	imm = INT32_MIN;
				2740	else if (!(Val & 0x100))
				2741	imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2742	Inst.addOperand(MCOperand::CreateImm(imm));
				2743
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2744	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2745	}
				2746
				2747
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2748	static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2749	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2750	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2751
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2752	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				2753	unsigned imm = fieldFromInstruction32(Val, 0, 9);
				2754
				2755	// Some instructions always use an additive offset.
				2756	switch (Inst.getOpcode()) {
				2757	case ARM::t2LDRT:
				2758	case ARM::t2LDRBT:
				2759	case ARM::t2LDRHT:
				2760	case ARM::t2LDRSBT:
				2761	case ARM::t2LDRSHT:
				2762	imm \|= 0x100;
				2763	break;
				2764	default:
				2765	break;
				2766	}
				2767
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2768	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2769	return MCDisassembler::Fail;
				2770	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				2771	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2772
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2773	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2774	}
				2775
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	2776	static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
				2777	uint64_t Address, const void *Decoder) {
				2778	DecodeStatus S = MCDisassembler::Success;
				2779
				2780	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				2781	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2782	unsigned addr = fieldFromInstruction32(Insn, 0, 8);
				2783	addr \|= fieldFromInstruction32(Insn, 9, 1) << 8;
				2784	addr \|= Rn << 9;
				2785	unsigned load = fieldFromInstruction32(Insn, 20, 1);
				2786
				2787	if (!load) {
				2788	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2789	return MCDisassembler::Fail;
				2790	}
				2791
Owen Anderson	e4f2df9	2011-09-16 22:42:36 +0000	[diff] [blame]	2792	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	2793	return MCDisassembler::Fail;
				2794
				2795	if (load) {
				2796	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2797	return MCDisassembler::Fail;
				2798	}
				2799
				2800	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				2801	return MCDisassembler::Fail;
				2802
				2803	return S;
				2804	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2805
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2806	static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2807	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2808	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2809
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2810	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				2811	unsigned imm = fieldFromInstruction32(Val, 0, 12);
				2812
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2813	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2814	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2815	Inst.addOperand(MCOperand::CreateImm(imm));
				2816
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2817	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2818	}
				2819
				2820
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2821	static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2822	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2823	unsigned imm = fieldFromInstruction16(Insn, 0, 7);
				2824
				2825	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2826	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2827	Inst.addOperand(MCOperand::CreateImm(imm));
				2828
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2829	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2830	}
				2831
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2832	static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2833	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2834	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2835
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2836	if (Inst.getOpcode() == ARM::tADDrSP) {
				2837	unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
				2838	Rdm \|= fieldFromInstruction16(Insn, 7, 1) << 3;
				2839
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2840	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				2841	return MCDisassembler::Fail;
				2842	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				2843	return MCDisassembler::Fail;
Owen Anderson	9990683	2011-08-25 18:30:18 +0000	[diff] [blame]	2844	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2845	} else if (Inst.getOpcode() == ARM::tADDspr) {
				2846	unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
				2847
				2848	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2849	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2850	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2851	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2852	}
				2853
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2854	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2855	}
				2856
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2857	static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2858	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2859	unsigned imod = fieldFromInstruction16(Insn, 4, 1) \| 0x2;
				2860	unsigned flags = fieldFromInstruction16(Insn, 0, 3);
				2861
				2862	Inst.addOperand(MCOperand::CreateImm(imod));
				2863	Inst.addOperand(MCOperand::CreateImm(flags));
				2864
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2865	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2866	}
				2867
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2868	static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2869	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2870	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2871	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2872	unsigned add = fieldFromInstruction32(Insn, 4, 1);
				2873
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2874	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2875	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2876	Inst.addOperand(MCOperand::CreateImm(add));
				2877
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2878	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2879	}
				2880
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2881	static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2882	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2883	Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2884	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2885	}
				2886
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2887	static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2888	uint64_t Address, const void *Decoder) {
				2889	if (Val == 0xA \|\| Val == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2890	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2891
				2892	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2893	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2894	}
				2895
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2896	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2897	DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
				2898	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2899	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2900
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2901	unsigned pred = fieldFromInstruction32(Insn, 22, 4);
				2902	if (pred == 0xE \|\| pred == 0xF) {
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2903	unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2904	switch (opc) {
				2905	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2906	return MCDisassembler::Fail;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2907	case 0xf3bf8f4:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2908	Inst.setOpcode(ARM::t2DSB);
				2909	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2910	case 0xf3bf8f5:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2911	Inst.setOpcode(ARM::t2DMB);
				2912	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2913	case 0xf3bf8f6:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2914	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	6de3c6f	2011-09-07 17:55:19 +0000	[diff] [blame]	2915	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2916	}
				2917
				2918	unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2919	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2920	}
				2921
				2922	unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
				2923	brtarget \|= fieldFromInstruction32(Insn, 11, 1) << 19;
				2924	brtarget \|= fieldFromInstruction32(Insn, 13, 1) << 18;
				2925	brtarget \|= fieldFromInstruction32(Insn, 16, 6) << 12;
				2926	brtarget \|= fieldFromInstruction32(Insn, 26, 1) << 20;
				2927
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2928	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				2929	return MCDisassembler::Fail;
				2930	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2931	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2932
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2933	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2934	}
				2935
				2936	// Decode a shifted immediate operand. These basically consist
				2937	// of an 8-bit value, and a 4-bit directive that specifies either
				2938	// a splat operation or a rotation.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2939	static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2940	uint64_t Address, const void *Decoder) {
				2941	unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
				2942	if (ctrl == 0) {
				2943	unsigned byte = fieldFromInstruction32(Val, 8, 2);
				2944	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				2945	switch (byte) {
				2946	case 0:
				2947	Inst.addOperand(MCOperand::CreateImm(imm));
				2948	break;
				2949	case 1:
				2950	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				2951	break;
				2952	case 2:
				2953	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				2954	break;
				2955	case 3:
				2956	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				2957	(imm << 8) \| imm));
				2958	break;
				2959	}
				2960	} else {
				2961	unsigned unrot = fieldFromInstruction32(Val, 0, 7) \| 0x80;
				2962	unsigned rot = fieldFromInstruction32(Val, 7, 5);
				2963	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				2964	Inst.addOperand(MCOperand::CreateImm(imm));
				2965	}
				2966
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2967	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2968	}
				2969
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2970	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2971	DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
				2972	uint64_t Address, const void *Decoder){
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2973	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2974	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2975	}
				2976
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2977	static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2978	uint64_t Address, const void *Decoder){
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2979	Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2980	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2981	}
				2982
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2983	static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2984	uint64_t Address, const void *Decoder) {
				2985	switch (Val) {
				2986	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2987	return MCDisassembler::Fail;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2988	case 0xF: // SY
				2989	case 0xE: // ST
				2990	case 0xB: // ISH
				2991	case 0xA: // ISHST
				2992	case 0x7: // NSH
				2993	case 0x6: // NSHST
				2994	case 0x3: // OSH
				2995	case 0x2: // OSHST
				2996	break;
				2997	}
				2998
				2999	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3000	return MCDisassembler::Success;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3001	}
				3002
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3003	static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3004	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3005	if (!Val) return MCDisassembler::Fail;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3006	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3007	return MCDisassembler::Success;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3008	}
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3009
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3010	static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3011	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3012	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3013
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3014	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3015	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3016	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3017
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3018	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3019
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3020	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3021	return MCDisassembler::Fail;
				3022	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3023	return MCDisassembler::Fail;
				3024	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3025	return MCDisassembler::Fail;
				3026	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3027	return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3028
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3029	return S;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3030	}
				3031
				3032
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3033	static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3034	uint64_t Address, const void *Decoder){
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3035	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3036
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3037	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3038	unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
				3039	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Anderson	adf2b09	2011-08-11 22:08:38 +0000	[diff] [blame]	3040	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3041
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3042	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				3043	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3044
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3045	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
				3046	if (Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1) return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3047
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3048	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3049	return MCDisassembler::Fail;
				3050	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3051	return MCDisassembler::Fail;
				3052	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3053	return MCDisassembler::Fail;
				3054	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3055	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3056
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3057	return S;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3058	}
				3059
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3060	static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3061	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3062	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3063
				3064	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3065	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3066	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3067	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3068	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3069	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3070
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3071	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3072
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3073	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3074	return MCDisassembler::Fail;
				3075	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3076	return MCDisassembler::Fail;
				3077	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3078	return MCDisassembler::Fail;
				3079	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3080	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3081
				3082	return S;
				3083	}
				3084
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3085	static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3086	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3087	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3088
				3089	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3090	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3091	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3092	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3093	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3094	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3095	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3096
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3097	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				3098	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3099
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3100	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3101	return MCDisassembler::Fail;
				3102	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3103	return MCDisassembler::Fail;
				3104	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3105	return MCDisassembler::Fail;
				3106	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3107	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3108
				3109	return S;
				3110	}
				3111
				3112
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3113	static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3114	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3115	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3116
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3117	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3118	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3119	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3120	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3121	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3122	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3123
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3124	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3125
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3126	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3127	return MCDisassembler::Fail;
				3128	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3129	return MCDisassembler::Fail;
				3130	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3131	return MCDisassembler::Fail;
				3132	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3133	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3134
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3135	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3136	}
				3137
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3138	static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3139	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3140	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3141
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3142	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3143	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3144	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3145	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3146	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3147	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3148
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3149	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3150
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3151	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3152	return MCDisassembler::Fail;
				3153	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3154	return MCDisassembler::Fail;
				3155	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3156	return MCDisassembler::Fail;
				3157	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3158	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3159
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3160	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3161	}
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3162
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3163	static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3164	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3165	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3166
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3167	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3168	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3169	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3170	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3171	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3172
				3173	unsigned align = 0;
				3174	unsigned index = 0;
				3175	switch (size) {
				3176	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3177	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3178	case 0:
				3179	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3180	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3181	index = fieldFromInstruction32(Insn, 5, 3);
				3182	break;
				3183	case 1:
				3184	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3185	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3186	index = fieldFromInstruction32(Insn, 6, 2);
				3187	if (fieldFromInstruction32(Insn, 4, 1))
				3188	align = 2;
				3189	break;
				3190	case 2:
				3191	if (fieldFromInstruction32(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3192	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3193	index = fieldFromInstruction32(Insn, 7, 1);
				3194	if (fieldFromInstruction32(Insn, 4, 2) != 0)
				3195	align = 4;
				3196	}
				3197
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3198	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3199	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3200	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3201	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3202	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3203	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3204	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3205	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3206	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3207	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3208	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3209	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3210	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3211	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3212	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3213	}
				3214
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3215	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3216	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3217	Inst.addOperand(MCOperand::CreateImm(index));
				3218
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3219	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3220	}
				3221
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3222	static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3223	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3224	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3225
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3226	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3227	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3228	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3229	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3230	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3231
				3232	unsigned align = 0;
				3233	unsigned index = 0;
				3234	switch (size) {
				3235	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3236	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3237	case 0:
				3238	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3239	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3240	index = fieldFromInstruction32(Insn, 5, 3);
				3241	break;
				3242	case 1:
				3243	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3244	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3245	index = fieldFromInstruction32(Insn, 6, 2);
				3246	if (fieldFromInstruction32(Insn, 4, 1))
				3247	align = 2;
				3248	break;
				3249	case 2:
				3250	if (fieldFromInstruction32(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3251	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3252	index = fieldFromInstruction32(Insn, 7, 1);
				3253	if (fieldFromInstruction32(Insn, 4, 2) != 0)
				3254	align = 4;
				3255	}
				3256
				3257	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3258	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3259	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3260	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3261	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3262	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3263	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3264	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3265	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3266	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3267	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3268	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3269	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3270	}
				3271
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3272	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3273	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3274	Inst.addOperand(MCOperand::CreateImm(index));
				3275
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3276	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3277	}
				3278
				3279
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3280	static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3281	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3282	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3283
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3284	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3285	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3286	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3287	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3288	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3289
				3290	unsigned align = 0;
				3291	unsigned index = 0;
				3292	unsigned inc = 1;
				3293	switch (size) {
				3294	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3295	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3296	case 0:
				3297	index = fieldFromInstruction32(Insn, 5, 3);
				3298	if (fieldFromInstruction32(Insn, 4, 1))
				3299	align = 2;
				3300	break;
				3301	case 1:
				3302	index = fieldFromInstruction32(Insn, 6, 2);
				3303	if (fieldFromInstruction32(Insn, 4, 1))
				3304	align = 4;
				3305	if (fieldFromInstruction32(Insn, 5, 1))
				3306	inc = 2;
				3307	break;
				3308	case 2:
				3309	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3310	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3311	index = fieldFromInstruction32(Insn, 7, 1);
				3312	if (fieldFromInstruction32(Insn, 4, 1) != 0)
				3313	align = 8;
				3314	if (fieldFromInstruction32(Insn, 6, 1))
				3315	inc = 2;
				3316	break;
				3317	}
				3318
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3319	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3320	return MCDisassembler::Fail;
				3321	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3322	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3323	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3324	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3325	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3326	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3327	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3328	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3329	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3330	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3331	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3332	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3333	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3334	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3335	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3336	}
				3337
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3338	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3339	return MCDisassembler::Fail;
				3340	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3341	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3342	Inst.addOperand(MCOperand::CreateImm(index));
				3343
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3344	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3345	}
				3346
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3347	static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3348	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3349	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3350
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3351	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3352	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3353	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3354	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3355	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3356
				3357	unsigned align = 0;
				3358	unsigned index = 0;
				3359	unsigned inc = 1;
				3360	switch (size) {
				3361	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3362	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3363	case 0:
				3364	index = fieldFromInstruction32(Insn, 5, 3);
				3365	if (fieldFromInstruction32(Insn, 4, 1))
				3366	align = 2;
				3367	break;
				3368	case 1:
				3369	index = fieldFromInstruction32(Insn, 6, 2);
				3370	if (fieldFromInstruction32(Insn, 4, 1))
				3371	align = 4;
				3372	if (fieldFromInstruction32(Insn, 5, 1))
				3373	inc = 2;
				3374	break;
				3375	case 2:
				3376	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3377	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3378	index = fieldFromInstruction32(Insn, 7, 1);
				3379	if (fieldFromInstruction32(Insn, 4, 1) != 0)
				3380	align = 8;
				3381	if (fieldFromInstruction32(Insn, 6, 1))
				3382	inc = 2;
				3383	break;
				3384	}
				3385
				3386	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3387	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3388	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3389	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3390	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3391	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3392	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3393	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3394	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3395	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3396	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3397	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3398	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3399	}
				3400
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3401	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3402	return MCDisassembler::Fail;
				3403	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3404	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3405	Inst.addOperand(MCOperand::CreateImm(index));
				3406
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3407	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3408	}
				3409
				3410
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3411	static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3412	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3413	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3414
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3415	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3416	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3417	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3418	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3419	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3420
				3421	unsigned align = 0;
				3422	unsigned index = 0;
				3423	unsigned inc = 1;
				3424	switch (size) {
				3425	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3426	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3427	case 0:
				3428	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3429	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3430	index = fieldFromInstruction32(Insn, 5, 3);
				3431	break;
				3432	case 1:
				3433	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3434	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3435	index = fieldFromInstruction32(Insn, 6, 2);
				3436	if (fieldFromInstruction32(Insn, 5, 1))
				3437	inc = 2;
				3438	break;
				3439	case 2:
				3440	if (fieldFromInstruction32(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3441	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3442	index = fieldFromInstruction32(Insn, 7, 1);
				3443	if (fieldFromInstruction32(Insn, 6, 1))
				3444	inc = 2;
				3445	break;
				3446	}
				3447
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3448	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3449	return MCDisassembler::Fail;
				3450	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3451	return MCDisassembler::Fail;
				3452	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3453	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3454
				3455	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3456	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3457	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3458	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3459	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3460	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3461	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3462	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3463	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3464	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3465	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3466	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3467	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3468	}
				3469
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3470	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3471	return MCDisassembler::Fail;
				3472	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3473	return MCDisassembler::Fail;
				3474	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3475	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3476	Inst.addOperand(MCOperand::CreateImm(index));
				3477
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3478	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3479	}
				3480
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3481	static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3482	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3483	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3484
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3485	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3486	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3487	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3488	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3489	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3490
				3491	unsigned align = 0;
				3492	unsigned index = 0;
				3493	unsigned inc = 1;
				3494	switch (size) {
				3495	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3496	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3497	case 0:
				3498	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3499	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3500	index = fieldFromInstruction32(Insn, 5, 3);
				3501	break;
				3502	case 1:
				3503	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3504	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3505	index = fieldFromInstruction32(Insn, 6, 2);
				3506	if (fieldFromInstruction32(Insn, 5, 1))
				3507	inc = 2;
				3508	break;
				3509	case 2:
				3510	if (fieldFromInstruction32(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3511	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3512	index = fieldFromInstruction32(Insn, 7, 1);
				3513	if (fieldFromInstruction32(Insn, 6, 1))
				3514	inc = 2;
				3515	break;
				3516	}
				3517
				3518	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3519	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3520	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3521	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3522	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3523	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3524	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3525	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3526	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3527	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3528	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3529	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3530	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3531	}
				3532
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3533	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3534	return MCDisassembler::Fail;
				3535	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3536	return MCDisassembler::Fail;
				3537	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3538	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3539	Inst.addOperand(MCOperand::CreateImm(index));
				3540
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3541	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3542	}
				3543
				3544
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3545	static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3546	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3547	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3548
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3549	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3550	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3551	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3552	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3553	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3554
				3555	unsigned align = 0;
				3556	unsigned index = 0;
				3557	unsigned inc = 1;
				3558	switch (size) {
				3559	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3560	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3561	case 0:
				3562	if (fieldFromInstruction32(Insn, 4, 1))
				3563	align = 4;
				3564	index = fieldFromInstruction32(Insn, 5, 3);
				3565	break;
				3566	case 1:
				3567	if (fieldFromInstruction32(Insn, 4, 1))
				3568	align = 8;
				3569	index = fieldFromInstruction32(Insn, 6, 2);
				3570	if (fieldFromInstruction32(Insn, 5, 1))
				3571	inc = 2;
				3572	break;
				3573	case 2:
				3574	if (fieldFromInstruction32(Insn, 4, 2))
				3575	align = 4 << fieldFromInstruction32(Insn, 4, 2);
				3576	index = fieldFromInstruction32(Insn, 7, 1);
				3577	if (fieldFromInstruction32(Insn, 6, 1))
				3578	inc = 2;
				3579	break;
				3580	}
				3581
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3582	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3583	return MCDisassembler::Fail;
				3584	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3585	return MCDisassembler::Fail;
				3586	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3587	return MCDisassembler::Fail;
				3588	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3589	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3590
				3591	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3592	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3593	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3594	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3595	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3596	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3597	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3598	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3599	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3600	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3601	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3602	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3603	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3604	}
				3605
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3606	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3607	return MCDisassembler::Fail;
				3608	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3609	return MCDisassembler::Fail;
				3610	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3611	return MCDisassembler::Fail;
				3612	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3613	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3614	Inst.addOperand(MCOperand::CreateImm(index));
				3615
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3616	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3617	}
				3618
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3619	static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3620	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3621	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3622
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3623	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3624	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3625	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3626	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3627	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3628
				3629	unsigned align = 0;
				3630	unsigned index = 0;
				3631	unsigned inc = 1;
				3632	switch (size) {
				3633	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3634	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3635	case 0:
				3636	if (fieldFromInstruction32(Insn, 4, 1))
				3637	align = 4;
				3638	index = fieldFromInstruction32(Insn, 5, 3);
				3639	break;
				3640	case 1:
				3641	if (fieldFromInstruction32(Insn, 4, 1))
				3642	align = 8;
				3643	index = fieldFromInstruction32(Insn, 6, 2);
				3644	if (fieldFromInstruction32(Insn, 5, 1))
				3645	inc = 2;
				3646	break;
				3647	case 2:
				3648	if (fieldFromInstruction32(Insn, 4, 2))
				3649	align = 4 << fieldFromInstruction32(Insn, 4, 2);
				3650	index = fieldFromInstruction32(Insn, 7, 1);
				3651	if (fieldFromInstruction32(Insn, 6, 1))
				3652	inc = 2;
				3653	break;
				3654	}
				3655
				3656	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3657	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3658	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3659	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3660	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3661	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3662	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3663	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3664	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3665	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3666	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3667	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3668	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3669	}
				3670
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3671	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3672	return MCDisassembler::Fail;
				3673	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3674	return MCDisassembler::Fail;
				3675	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3676	return MCDisassembler::Fail;
				3677	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3678	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3679	Inst.addOperand(MCOperand::CreateImm(index));
				3680
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3681	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3682	}
				3683
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3684	static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3685	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3686	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3687	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3688	unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
				3689	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3690	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3691	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				3692
				3693	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3694	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3695
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3696	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				3697	return MCDisassembler::Fail;
				3698	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				3699	return MCDisassembler::Fail;
				3700	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				3701	return MCDisassembler::Fail;
				3702	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				3703	return MCDisassembler::Fail;
				3704	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3705	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3706
				3707	return S;
				3708	}
				3709
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3710	static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3711	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3712	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3713	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3714	unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
				3715	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3716	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3717	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				3718
				3719	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3720	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3721
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3722	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				3723	return MCDisassembler::Fail;
				3724	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				3725	return MCDisassembler::Fail;
				3726	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				3727	return MCDisassembler::Fail;
				3728	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				3729	return MCDisassembler::Fail;
				3730	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3731	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3732
				3733	return S;
				3734	}
Owen Anderson	8e1e60b	2011-08-22 23:44:04 +0000	[diff] [blame]	3735
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3736	static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3737	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3738	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3739	unsigned pred = fieldFromInstruction16(Insn, 4, 4);
				3740	// The InstPrinter needs to have the low bit of the predicate in
				3741	// the mask operand to be able to print it properly.
				3742	unsigned mask = fieldFromInstruction16(Insn, 0, 5);
				3743
				3744	if (pred == 0xF) {
				3745	pred = 0xE;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3746	S = MCDisassembler::SoftFail;
Owen Anderson	e234d02	2011-08-24 17:21:43 +0000	[diff] [blame]	3747	}
				3748
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3749	if ((mask & 0xF) == 0) {
				3750	// Preserve the high bit of the mask, which is the low bit of
				3751	// the predicate.
				3752	mask &= 0x10;
				3753	mask \|= 0x8;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3754	S = MCDisassembler::SoftFail;
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	3755	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3756
				3757	Inst.addOperand(MCOperand::CreateImm(pred));
				3758	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	3759	return S;
				3760	}
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	3761
				3762	static DecodeStatus
				3763	DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
				3764	uint64_t Address, const void *Decoder) {
				3765	DecodeStatus S = MCDisassembler::Success;
				3766
				3767	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3768	unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
				3769	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3770	unsigned addr = fieldFromInstruction32(Insn, 0, 8);
				3771	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				3772	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				3773	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				3774	bool writeback = (W == 1) \| (P == 0);
				3775
				3776	addr \|= (U << 8) \| (Rn << 9);
				3777
				3778	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				3779	Check(S, MCDisassembler::SoftFail);
				3780	if (Rt == Rt2)
				3781	Check(S, MCDisassembler::SoftFail);
				3782
				3783	// Rt
				3784	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3785	return MCDisassembler::Fail;
				3786	// Rt2
				3787	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				3788	return MCDisassembler::Fail;
				3789	// Writeback operand
				3790	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3791	return MCDisassembler::Fail;
				3792	// addr
				3793	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				3794	return MCDisassembler::Fail;
				3795
				3796	return S;
				3797	}
				3798
				3799	static DecodeStatus
				3800	DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
				3801	uint64_t Address, const void *Decoder) {
				3802	DecodeStatus S = MCDisassembler::Success;
				3803
				3804	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3805	unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
				3806	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3807	unsigned addr = fieldFromInstruction32(Insn, 0, 8);
				3808	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				3809	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				3810	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				3811	bool writeback = (W == 1) \| (P == 0);
				3812
				3813	addr \|= (U << 8) \| (Rn << 9);
				3814
				3815	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				3816	Check(S, MCDisassembler::SoftFail);
				3817
				3818	// Writeback operand
				3819	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3820	return MCDisassembler::Fail;
				3821	// Rt
				3822	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3823	return MCDisassembler::Fail;
				3824	// Rt2
				3825	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				3826	return MCDisassembler::Fail;
				3827	// addr
				3828	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				3829	return MCDisassembler::Fail;
				3830
				3831	return S;
				3832	}
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	3833
				3834	static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
				3835	uint64_t Address, const void *Decoder) {
				3836	unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
				3837	unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
				3838	if (sign1 != sign2) return MCDisassembler::Fail;
				3839
				3840	unsigned Val = fieldFromInstruction32(Insn, 0, 8);
				3841	Val \|= fieldFromInstruction32(Insn, 12, 3) << 8;
				3842	Val \|= fieldFromInstruction32(Insn, 26, 1) << 11;
				3843	Val \|= sign1 << 12;
				3844	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				3845
				3846	return MCDisassembler::Success;
				3847	}
				3848