Chris Lattner | fadc83c | 2009-06-19 00:47:59 +0000 | [diff] [blame] | 1 | //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file includes code for rendering MCInst instances as AT&T-style |
| 11 | // assembly. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #define DEBUG_TYPE "asm-printer" |
| 16 | #include "llvm/MC/MCInst.h" |
| 17 | #include "X86ATTAsmPrinter.h" |
Chris Lattner | c124306 | 2009-06-20 07:03:18 +0000 | [diff] [blame] | 18 | #include "llvm/Target/TargetAsmInfo.h" |
Chris Lattner | d5fb790 | 2009-06-19 23:59:57 +0000 | [diff] [blame] | 19 | #include "llvm/Support/raw_ostream.h" |
Chris Lattner | fadc83c | 2009-06-19 00:47:59 +0000 | [diff] [blame] | 20 | using namespace llvm; |
| 21 | |
Chris Lattner | d5fb790 | 2009-06-19 23:59:57 +0000 | [diff] [blame] | 22 | // Include the auto-generated portion of the assembly writer. |
| 23 | #define MachineInstr MCInst |
| 24 | #define NO_ASM_WRITER_BOILERPLATE |
| 25 | #include "X86GenAsmWriter.inc" |
| 26 | #undef MachineInstr |
| 27 | |
| 28 | void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) { |
Chris Lattner | c124306 | 2009-06-20 07:03:18 +0000 | [diff] [blame] | 29 | switch (MI->getOperand(Op).getImm()) { |
| 30 | default: assert(0 && "Invalid ssecc argument!"); |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 31 | case 0: O << "eq"; break; |
| 32 | case 1: O << "lt"; break; |
| 33 | case 2: O << "le"; break; |
| 34 | case 3: O << "unord"; break; |
| 35 | case 4: O << "neq"; break; |
| 36 | case 5: O << "nlt"; break; |
| 37 | case 6: O << "nle"; break; |
| 38 | case 7: O << "ord"; break; |
Chris Lattner | d5fb790 | 2009-06-19 23:59:57 +0000 | [diff] [blame] | 39 | } |
| 40 | } |
| 41 | |
| 42 | |
| 43 | void X86ATTAsmPrinter::printPICLabel(const MCInst *MI, unsigned Op) { |
| 44 | assert(0 && |
| 45 | "This is only used for MOVPC32r, should lower before asm printing!"); |
| 46 | } |
| 47 | |
| 48 | |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 49 | /// print_pcrel_imm - This is used to print an immediate value that ends up |
| 50 | /// being encoded as a pc-relative value. These print slightly differently, for |
| 51 | /// example, a $ is not emitted. |
| 52 | void X86ATTAsmPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { |
| 53 | const MCOperand &Op = MI->getOperand(OpNo); |
| 54 | |
| 55 | if (Op.isImm()) |
| 56 | O << Op.getImm(); |
| 57 | else if (Op.isMBBLabel()) |
| 58 | // FIXME: Keep in sync with printBasicBlockLabel. printBasicBlockLabel |
| 59 | // should eventually call into this code, not the other way around. |
| 60 | O << TAI->getPrivateGlobalPrefix() << "BB" << Op.getMBBLabelFunction() |
| 61 | << '_' << Op.getMBBLabelBlock(); |
| 62 | else |
| 63 | assert(0 && "Unknown pcrel immediate operand"); |
| 64 | } |
| 65 | |
| 66 | |
Chris Lattner | d5fb790 | 2009-06-19 23:59:57 +0000 | [diff] [blame] | 67 | void X86ATTAsmPrinter::printOperand(const MCInst *MI, unsigned OpNo, |
| 68 | const char *Modifier, bool NotRIPRel) { |
Chris Lattner | c124306 | 2009-06-20 07:03:18 +0000 | [diff] [blame] | 69 | assert(Modifier == 0 && "Modifiers should not be used"); |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 70 | |
| 71 | const MCOperand &Op = MI->getOperand(OpNo); |
| 72 | if (Op.isReg()) { |
| 73 | O << '%'; |
| 74 | unsigned Reg = Op.getReg(); |
| 75 | #if 0 |
| 76 | if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { |
| 77 | MVT VT = (strcmp(Modifier+6,"64") == 0) ? |
| 78 | MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 : |
| 79 | ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8)); |
| 80 | Reg = getX86SubSuperRegister(Reg, VT); |
| 81 | } |
| 82 | #endif |
| 83 | O << TRI->getAsmName(Reg); |
| 84 | return; |
| 85 | } else if (Op.isImm()) { |
Chris Lattner | 2f429e5 | 2009-06-21 01:48:49 +0000 | [diff] [blame] | 86 | //if (!Modifier || (strcmp(Modifier, "debug") && strcmp(Modifier, "mem"))) |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 87 | O << '$'; |
| 88 | O << Op.getImm(); |
| 89 | return; |
| 90 | } |
| 91 | |
| 92 | O << "<<UNKNOWN OPERAND KIND>>"; |
Chris Lattner | d5fb790 | 2009-06-19 23:59:57 +0000 | [diff] [blame] | 93 | } |
| 94 | |
Chris Lattner | c124306 | 2009-06-20 07:03:18 +0000 | [diff] [blame] | 95 | void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { |
Chris Lattner | c124306 | 2009-06-20 07:03:18 +0000 | [diff] [blame] | 96 | bool NotRIPRel = false; |
| 97 | |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 98 | const MCOperand &BaseReg = MI->getOperand(Op); |
| 99 | const MCOperand &IndexReg = MI->getOperand(Op+2); |
| 100 | const MCOperand &DispSpec = MI->getOperand(Op+3); |
| 101 | |
| 102 | NotRIPRel |= IndexReg.getReg() || BaseReg.getReg(); |
| 103 | if (DispSpec.isImm()) { |
| 104 | int64_t DispVal = DispSpec.getImm(); |
| 105 | if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) |
| 106 | O << DispVal; |
| 107 | } else { |
| 108 | abort(); |
| 109 | //assert(DispSpec.isGlobal() || DispSpec.isCPI() || |
| 110 | // DispSpec.isJTI() || DispSpec.isSymbol()); |
| 111 | //printOperand(MI, Op+3, "mem", NotRIPRel); |
| 112 | } |
| 113 | |
| 114 | if (IndexReg.getReg() || BaseReg.getReg()) { |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 115 | // There are cases where we can end up with ESP/RSP in the indexreg slot. |
| 116 | // If this happens, swap the base/index register to support assemblers that |
| 117 | // don't work when the index is *SP. |
| 118 | // FIXME: REMOVE THIS. |
Chris Lattner | dc479f6 | 2009-06-20 07:59:10 +0000 | [diff] [blame] | 119 | assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP); |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 120 | |
| 121 | O << '('; |
| 122 | if (BaseReg.getReg()) |
Chris Lattner | dc479f6 | 2009-06-20 07:59:10 +0000 | [diff] [blame] | 123 | printOperand(MI, Op); |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 124 | |
| 125 | if (IndexReg.getReg()) { |
| 126 | O << ','; |
Chris Lattner | dc479f6 | 2009-06-20 07:59:10 +0000 | [diff] [blame] | 127 | printOperand(MI, Op+2); |
Chris Lattner | 7f8217f | 2009-06-20 08:13:12 +0000 | [diff] [blame] | 128 | unsigned ScaleVal = MI->getOperand(Op+1).getImm(); |
| 129 | if (ScaleVal != 1) |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 130 | O << ',' << ScaleVal; |
| 131 | } |
| 132 | O << ')'; |
| 133 | } |
Chris Lattner | d5fb790 | 2009-06-19 23:59:57 +0000 | [diff] [blame] | 134 | } |
| 135 | |
Chris Lattner | c124306 | 2009-06-20 07:03:18 +0000 | [diff] [blame] | 136 | void X86ATTAsmPrinter::printMemReference(const MCInst *MI, unsigned Op) { |
Chris Lattner | ad48be0 | 2009-06-20 00:50:32 +0000 | [diff] [blame] | 137 | const MCOperand &Segment = MI->getOperand(Op+4); |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 138 | if (Segment.getReg()) { |
Chris Lattner | c124306 | 2009-06-20 07:03:18 +0000 | [diff] [blame] | 139 | printOperand(MI, Op+4); |
Chris Lattner | f38c03af | 2009-06-20 00:49:26 +0000 | [diff] [blame] | 140 | O << ':'; |
| 141 | } |
Chris Lattner | c124306 | 2009-06-20 07:03:18 +0000 | [diff] [blame] | 142 | printLeaMemReference(MI, Op); |
Chris Lattner | d5fb790 | 2009-06-19 23:59:57 +0000 | [diff] [blame] | 143 | } |