Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1 | //===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 081ce94 | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | //3.3: |
| 14 | //Memory |
| 15 | //Branch |
| 16 | //Operate |
| 17 | //Floating-point |
| 18 | //PALcode |
| 19 | |
| 20 | def u8imm : Operand<i64>; |
| 21 | def s14imm : Operand<i64>; |
| 22 | def s16imm : Operand<i64>; |
| 23 | def s21imm : Operand<i64>; |
| 24 | def s64imm : Operand<i64>; |
| 25 | def u64imm : Operand<i64>; |
| 26 | |
| 27 | //===----------------------------------------------------------------------===// |
| 28 | // Instruction format superclass |
| 29 | //===----------------------------------------------------------------------===// |
| 30 | // Alpha instruction baseline |
| 31 | class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction { |
| 32 | field bits<32> Inst; |
| 33 | let Namespace = "Alpha"; |
| 34 | let AsmString = asmstr; |
| 35 | let Inst{31-26} = op; |
| 36 | let Itinerary = itin; |
| 37 | } |
| 38 | |
| 39 | |
| 40 | //3.3.1 |
Chris Lattner | ef8d608 | 2008-01-06 06:44:58 +0000 | [diff] [blame] | 41 | class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 42 | : InstAlpha<opcode, asmstr, itin> { |
| 43 | let Pattern = pattern; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 44 | let isLoad = load; |
| 45 | let Defs = [R28]; //We may use this for frame index calculations, so reserve it here |
| 46 | |
| 47 | bits<5> Ra; |
| 48 | bits<16> disp; |
| 49 | bits<5> Rb; |
| 50 | |
| 51 | let Inst{25-21} = Ra; |
| 52 | let Inst{20-16} = Rb; |
| 53 | let Inst{15-0} = disp; |
| 54 | } |
| 55 | class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin> |
| 56 | : InstAlpha<opcode, asmstr, itin> { |
| 57 | bits<5> Ra; |
| 58 | |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 59 | let OutOperandList = (ops GPRC:$RA); |
| 60 | let InOperandList = (ops); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 61 | let Inst{25-21} = Ra; |
| 62 | let Inst{20-16} = 0; |
| 63 | let Inst{15-0} = fc; |
| 64 | } |
| 65 | |
| 66 | class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin> |
| 67 | : InstAlpha<opcode, asmstr, itin> { |
| 68 | bits<5> Ra; |
| 69 | bits<5> Rb; |
| 70 | bits<14> disp; |
| 71 | |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 72 | let OutOperandList = (ops); |
| 73 | let InOperandList = OL; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 74 | |
| 75 | let Inst{25-21} = Ra; |
| 76 | let Inst{20-16} = Rb; |
| 77 | let Inst{15-14} = TB; |
| 78 | let Inst{13-0} = disp; |
| 79 | } |
| 80 | class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 81 | : InstAlpha<opcode, asmstr, itin> { |
| 82 | let Pattern=pattern; |
| 83 | bits<5> Ra; |
| 84 | bits<5> Rb; |
| 85 | bits<14> disp; |
| 86 | |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 87 | let OutOperandList = (ops); |
| 88 | let InOperandList = OL; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 89 | |
| 90 | let Inst{25-21} = Ra; |
| 91 | let Inst{20-16} = Rb; |
| 92 | let Inst{15-14} = TB; |
| 93 | let Inst{13-0} = disp; |
| 94 | } |
| 95 | |
| 96 | //3.3.2 |
| 97 | def target : Operand<OtherVT> {} |
| 98 | |
Evan Cheng | 37e7c75 | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 99 | let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 100 | class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> |
| 101 | : InstAlpha<opcode, asmstr, itin> { |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 102 | let OutOperandList = (ops); |
| 103 | let InOperandList = OL; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 104 | bits<64> Opc; //dummy |
| 105 | bits<5> Ra; |
| 106 | bits<21> disp; |
| 107 | |
| 108 | let Inst{25-21} = Ra; |
| 109 | let Inst{20-0} = disp; |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | let isBranch = 1, isTerminator = 1 in |
| 114 | class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 115 | : InstAlpha<opcode, asmstr, itin> { |
| 116 | let Pattern = pattern; |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 117 | let OutOperandList = (ops); |
| 118 | let InOperandList = (ops target:$DISP); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 119 | bits<5> Ra; |
| 120 | bits<21> disp; |
| 121 | |
| 122 | let Inst{25-21} = Ra; |
| 123 | let Inst{20-0} = disp; |
| 124 | } |
| 125 | |
| 126 | //3.3.3 |
| 127 | class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 128 | : InstAlpha<opcode, asmstr, itin> { |
| 129 | let Pattern = pattern; |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 130 | let OutOperandList = (outs GPRC:$RC); |
| 131 | let InOperandList = (ins GPRC:$RA, GPRC:$RB); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 132 | |
| 133 | bits<5> Rc; |
| 134 | bits<5> Ra; |
| 135 | bits<5> Rb; |
| 136 | bits<7> Function = fun; |
| 137 | |
| 138 | let Inst{25-21} = Ra; |
| 139 | let Inst{20-16} = Rb; |
| 140 | let Inst{15-13} = 0; |
| 141 | let Inst{12} = 0; |
| 142 | let Inst{11-5} = Function; |
| 143 | let Inst{4-0} = Rc; |
| 144 | } |
| 145 | |
| 146 | class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 147 | : InstAlpha<opcode, asmstr, itin> { |
| 148 | let Pattern = pattern; |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 149 | let OutOperandList = (outs GPRC:$RC); |
| 150 | let InOperandList = (ins GPRC:$RB); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 151 | |
| 152 | bits<5> Rc; |
| 153 | bits<5> Rb; |
| 154 | bits<7> Function = fun; |
| 155 | |
| 156 | let Inst{25-21} = 31; |
| 157 | let Inst{20-16} = Rb; |
| 158 | let Inst{15-13} = 0; |
| 159 | let Inst{12} = 0; |
| 160 | let Inst{11-5} = Function; |
| 161 | let Inst{4-0} = Rc; |
| 162 | } |
| 163 | |
| 164 | class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 165 | : InstAlpha<opcode, asmstr, itin> { |
| 166 | let Pattern = pattern; |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 167 | let OutOperandList = (outs GPRC:$RDEST); |
| 168 | let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 169 | let Constraints = "$RFALSE = $RDEST"; |
| 170 | let DisableEncoding = "$RFALSE"; |
| 171 | |
| 172 | bits<5> Rc; |
| 173 | bits<5> Ra; |
| 174 | bits<5> Rb; |
| 175 | bits<7> Function = fun; |
| 176 | |
| 177 | // let isTwoAddress = 1; |
| 178 | let Inst{25-21} = Ra; |
| 179 | let Inst{20-16} = Rb; |
| 180 | let Inst{15-13} = 0; |
| 181 | let Inst{12} = 0; |
| 182 | let Inst{11-5} = Function; |
| 183 | let Inst{4-0} = Rc; |
| 184 | } |
| 185 | |
| 186 | |
| 187 | class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 188 | : InstAlpha<opcode, asmstr, itin> { |
| 189 | let Pattern = pattern; |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 190 | let OutOperandList = (outs GPRC:$RC); |
| 191 | let InOperandList = (ins GPRC:$RA, u8imm:$L); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 192 | |
| 193 | bits<5> Rc; |
| 194 | bits<5> Ra; |
| 195 | bits<8> LIT; |
| 196 | bits<7> Function = fun; |
| 197 | |
| 198 | let Inst{25-21} = Ra; |
| 199 | let Inst{20-13} = LIT; |
| 200 | let Inst{12} = 1; |
| 201 | let Inst{11-5} = Function; |
| 202 | let Inst{4-0} = Rc; |
| 203 | } |
| 204 | |
| 205 | class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 206 | : InstAlpha<opcode, asmstr, itin> { |
| 207 | let Pattern = pattern; |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 208 | let OutOperandList = (outs GPRC:$RDEST); |
| 209 | let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE); |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 210 | let Constraints = "$RFALSE = $RDEST"; |
| 211 | let DisableEncoding = "$RFALSE"; |
| 212 | |
| 213 | bits<5> Rc; |
| 214 | bits<5> Ra; |
| 215 | bits<8> LIT; |
| 216 | bits<7> Function = fun; |
| 217 | |
| 218 | // let isTwoAddress = 1; |
| 219 | let Inst{25-21} = Ra; |
| 220 | let Inst{20-13} = LIT; |
| 221 | let Inst{12} = 1; |
| 222 | let Inst{11-5} = Function; |
| 223 | let Inst{4-0} = Rc; |
| 224 | } |
| 225 | |
| 226 | //3.3.4 |
| 227 | class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin> |
| 228 | : InstAlpha<opcode, asmstr, itin> { |
| 229 | let Pattern = pattern; |
| 230 | |
| 231 | bits<5> Fc; |
| 232 | bits<5> Fa; |
| 233 | bits<5> Fb; |
| 234 | bits<11> Function = fun; |
| 235 | |
| 236 | let Inst{25-21} = Fa; |
| 237 | let Inst{20-16} = Fb; |
| 238 | let Inst{15-5} = Function; |
| 239 | let Inst{4-0} = Fc; |
| 240 | } |
| 241 | |
| 242 | //3.3.5 |
| 243 | class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> |
| 244 | : InstAlpha<opcode, asmstr, itin> { |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 245 | let OutOperandList = (ops); |
| 246 | let InOperandList = OL; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 247 | bits<26> Function; |
| 248 | |
| 249 | let Inst{25-0} = Function; |
| 250 | } |
| 251 | |
| 252 | |
| 253 | // Pseudo instructions. |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 254 | class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin> |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 255 | : InstAlpha<0, nm, itin> { |
Evan Cheng | b783fa3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 256 | let OutOperandList = OOL; |
| 257 | let InOperandList = IOL; |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 258 | let Pattern = pattern; |
| 259 | |
| 260 | } |