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Arnold Schwaighofer92226dd2007-10-12 21:53:12 +00001//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that X86 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
Evan Cheng0cc39452006-01-16 21:21:29 +000016#include "X86InstrBuilder.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000017#include "X86ISelLowering.h"
Evan Chenge8bd0a32006-06-06 23:30:24 +000018#include "X86MachineFunctionInfo.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000019#include "X86TargetMachine.h"
20#include "llvm/CallingConv.h"
Evan Cheng223547a2006-01-31 22:28:30 +000021#include "llvm/Constants.h"
Evan Cheng347d5f72006-04-28 21:29:37 +000022#include "llvm/DerivedTypes.h"
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +000023#include "llvm/GlobalVariable.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000024#include "llvm/Function.h"
Evan Cheng6be2c582006-04-05 23:38:46 +000025#include "llvm/Intrinsics.h"
Evan Cheng14b32e12007-12-11 01:46:18 +000026#include "llvm/ADT/BitVector.h"
Evan Cheng30b37b52006-03-13 23:18:16 +000027#include "llvm/ADT/VectorExtras.h"
28#include "llvm/Analysis/ScalarEvolutionExpressions.h"
Chris Lattner362e98a2007-02-27 04:43:02 +000029#include "llvm/CodeGen/CallingConvLower.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000030#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Cheng4a460802006-01-11 00:33:36 +000031#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000033#include "llvm/CodeGen/MachineRegisterInfo.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000034#include "llvm/CodeGen/SelectionDAG.h"
Evan Chengef6ffb12006-01-31 03:14:29 +000035#include "llvm/Support/MathExtras.h"
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +000036#include "llvm/Support/Debug.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000037#include "llvm/Target/TargetOptions.h"
Evan Cheng14b32e12007-12-11 01:46:18 +000038#include "llvm/ADT/SmallSet.h"
Chris Lattner1a60aa72006-10-31 19:42:44 +000039#include "llvm/ADT/StringExtras.h"
Duncan Sandsb116fac2007-07-27 20:02:49 +000040#include "llvm/ParameterAttributes.h"
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000041using namespace llvm;
42
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000043X86TargetLowering::X86TargetLowering(TargetMachine &TM)
44 : TargetLowering(TM) {
Evan Cheng559806f2006-01-27 08:10:46 +000045 Subtarget = &TM.getSubtarget<X86Subtarget>();
Dale Johannesenf1fc3a82007-09-23 14:52:20 +000046 X86ScalarSSEf64 = Subtarget->hasSSE2();
47 X86ScalarSSEf32 = Subtarget->hasSSE1();
Evan Cheng25ab6902006-09-08 06:48:29 +000048 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +000049
Evan Cheng559806f2006-01-27 08:10:46 +000050
Anton Korobeynikov2365f512007-07-14 14:06:15 +000051 RegInfo = TM.getRegisterInfo();
52
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000053 // Set up the TargetLowering object.
54
55 // X86 is weird, it always uses i8 for shift amounts and setcc results.
56 setShiftAmountType(MVT::i8);
57 setSetCCResultType(MVT::i8);
58 setSetCCResultContents(ZeroOrOneSetCCResult);
Evan Cheng0b2afbd2006-01-25 09:15:17 +000059 setSchedulingPreference(SchedulingForRegPressure);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000060 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
Evan Cheng25ab6902006-09-08 06:48:29 +000061 setStackPointerRegisterToSaveRestore(X86StackPtr);
Evan Cheng714554d2006-03-16 21:47:42 +000062
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000063 if (Subtarget->isTargetDarwin()) {
Evan Chengdf57fa02006-03-17 20:31:41 +000064 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000065 setUseUnderscoreSetJmp(false);
66 setUseUnderscoreLongJmp(false);
Anton Korobeynikov317848f2007-01-03 11:43:14 +000067 } else if (Subtarget->isTargetMingw()) {
Anton Korobeynikovd27a2582006-12-10 23:12:42 +000068 // MS runtime is weird: it exports _setjmp, but longjmp!
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(false);
71 } else {
72 setUseUnderscoreSetJmp(true);
73 setUseUnderscoreLongJmp(true);
74 }
75
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000076 // Set up the register classes.
Evan Cheng069287d2006-05-16 07:21:53 +000077 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
78 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
79 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
Evan Cheng25ab6902006-09-08 06:48:29 +000080 if (Subtarget->is64Bit())
81 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000082
Evan Chengc5484282006-10-04 00:56:09 +000083 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
84
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +000085 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
86 // operation.
87 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
88 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
89 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
Evan Cheng6892f282006-01-17 02:32:49 +000090
Evan Cheng25ab6902006-09-08 06:48:29 +000091 if (Subtarget->is64Bit()) {
92 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
Evan Cheng6892f282006-01-17 02:32:49 +000093 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
Evan Cheng25ab6902006-09-08 06:48:29 +000094 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +000095 if (X86ScalarSSEf64)
Evan Cheng25ab6902006-09-08 06:48:29 +000096 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
97 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
98 else
99 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
100 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000101
102 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
103 // this operation.
104 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
105 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000106 // SSE has no i16 to fp conversion, only i32
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000107 if (X86ScalarSSEf32) {
Evan Cheng02568ff2006-01-30 22:13:22 +0000108 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000109 // f32 and f64 cases are Legal, f80 case is not
110 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
111 } else {
Evan Cheng5298bcc2006-02-17 07:01:52 +0000112 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
113 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
114 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000115
Dale Johannesen73328d12007-09-19 23:55:34 +0000116 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
117 // are Legal, f80 is custom lowered.
118 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
119 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
Evan Cheng6dab0532006-01-30 08:02:57 +0000120
Evan Cheng02568ff2006-01-30 22:13:22 +0000121 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
122 // this operation.
123 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
124 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
125
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000126 if (X86ScalarSSEf32) {
Evan Cheng02568ff2006-01-30 22:13:22 +0000127 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000128 // f32 and f64 cases are Legal, f80 case is not
129 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
Evan Cheng02568ff2006-01-30 22:13:22 +0000130 } else {
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000131 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
Evan Cheng02568ff2006-01-30 22:13:22 +0000132 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000133 }
134
135 // Handle FP_TO_UINT by promoting the destination to a larger signed
136 // conversion.
137 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
138 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
139 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
140
Evan Cheng25ab6902006-09-08 06:48:29 +0000141 if (Subtarget->is64Bit()) {
142 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000143 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
Evan Cheng25ab6902006-09-08 06:48:29 +0000144 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000145 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
Evan Cheng25ab6902006-09-08 06:48:29 +0000146 // Expand FP_TO_UINT into a select.
147 // FIXME: We would like to use a Custom expander here eventually to do
148 // the optimal thing for SSE vs. the default expansion in the legalizer.
149 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
150 else
151 // With SSE3 we can use fisttpll to convert to a signed i64.
152 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
153 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000154
Chris Lattner399610a2006-12-05 18:22:22 +0000155 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000156 if (!X86ScalarSSEf64) {
Chris Lattnerf3597a12006-12-05 18:45:06 +0000157 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
158 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
159 }
Chris Lattner21f66852005-12-23 05:15:23 +0000160
Dan Gohman525178c2007-10-08 18:33:35 +0000161 // Scalar integer multiply, multiply-high, divide, and remainder are
162 // lowered to use operations that produce two results, to match the
163 // available instructions. This exposes the two-result form to trivial
164 // CSE, which is able to combine x/y and x%y into a single instruction,
165 // for example. The single-result multiply instructions are introduced
166 // in X86ISelDAGToDAG.cpp, after CSE, for uses where the the high part
167 // is not needed.
168 setOperationAction(ISD::MUL , MVT::i8 , Expand);
169 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
170 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
171 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
172 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
173 setOperationAction(ISD::SREM , MVT::i8 , Expand);
174 setOperationAction(ISD::UREM , MVT::i8 , Expand);
175 setOperationAction(ISD::MUL , MVT::i16 , Expand);
176 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
177 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
178 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
179 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
180 setOperationAction(ISD::SREM , MVT::i16 , Expand);
181 setOperationAction(ISD::UREM , MVT::i16 , Expand);
182 setOperationAction(ISD::MUL , MVT::i32 , Expand);
183 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
187 setOperationAction(ISD::SREM , MVT::i32 , Expand);
188 setOperationAction(ISD::UREM , MVT::i32 , Expand);
189 setOperationAction(ISD::MUL , MVT::i64 , Expand);
190 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
191 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
192 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
193 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
194 setOperationAction(ISD::SREM , MVT::i64 , Expand);
195 setOperationAction(ISD::UREM , MVT::i64 , Expand);
Dan Gohmana37c9f72007-09-25 18:23:27 +0000196
Evan Chengc35497f2006-10-30 08:02:39 +0000197 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000198 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
Nate Begeman750ac1b2006-02-01 07:19:44 +0000199 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
200 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000201 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
Evan Cheng25ab6902006-09-08 06:48:29 +0000202 if (Subtarget->is64Bit())
Christopher Lambc59e5212007-08-10 21:48:46 +0000203 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
205 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000206 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
207 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000208 setOperationAction(ISD::FREM , MVT::f64 , Expand);
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +0000209 setOperationAction(ISD::FLT_ROUNDS , MVT::i32 , Custom);
210
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000211 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000212 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
213 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000214 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000215 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
216 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000217 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000218 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
219 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000220 if (Subtarget->is64Bit()) {
221 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
Evan Cheng18efe262007-12-14 02:13:44 +0000222 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
223 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000224 }
225
Andrew Lenharthb873ff32005-11-20 21:41:10 +0000226 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
Nate Begemand88fc032006-01-14 03:14:10 +0000227 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
Nate Begeman35ef9132006-01-11 21:21:00 +0000228
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000229 // These should be promoted to a larger select which is supported.
230 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
231 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000232 // X86 wants to expand cmov itself.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000233 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
234 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
235 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
236 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000237 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000238 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
239 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
240 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
241 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
242 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000243 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
246 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
247 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000248 // X86 ret instruction may pop stack.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000249 setOperationAction(ISD::RET , MVT::Other, Custom);
Anton Korobeynikov2365f512007-07-14 14:06:15 +0000250 if (!Subtarget->is64Bit())
251 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
252
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000253 // Darwin ABI issue.
Evan Cheng7ccced62006-02-18 00:15:05 +0000254 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
Nate Begeman37efe672006-04-22 18:53:45 +0000255 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
Evan Cheng5298bcc2006-02-17 07:01:52 +0000256 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +0000257 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
Evan Cheng020d2e82006-02-23 20:41:18 +0000258 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
Evan Cheng25ab6902006-09-08 06:48:29 +0000259 if (Subtarget->is64Bit()) {
260 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
261 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
262 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
263 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
264 }
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000265 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
Evan Cheng5298bcc2006-02-17 07:01:52 +0000266 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
267 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
268 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
Nate Begeman4c5dcf52006-02-17 00:03:04 +0000269 // X86 wants to expand memset / memcpy itself.
Evan Cheng5298bcc2006-02-17 07:01:52 +0000270 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
271 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000272
Dan Gohmanc3b0b5c2007-09-25 15:10:49 +0000273 // Use the default ISD::LOCATION expansion.
Chris Lattnerf73bae12005-11-29 06:16:21 +0000274 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
Evan Cheng3c992d22006-03-07 02:02:57 +0000275 // FIXME - use subtarget debug flags
Anton Korobeynikovab4022f2006-10-31 08:31:24 +0000276 if (!Subtarget->isTargetDarwin() &&
277 !Subtarget->isTargetELF() &&
Anton Korobeynikov317848f2007-01-03 11:43:14 +0000278 !Subtarget->isTargetCygMing())
Jim Laskey1ee29252007-01-26 14:34:52 +0000279 setOperationAction(ISD::LABEL, MVT::Other, Expand);
Chris Lattnerf73bae12005-11-29 06:16:21 +0000280
Anton Korobeynikovce3b4652007-05-02 19:53:33 +0000281 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
282 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
283 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
284 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
285 if (Subtarget->is64Bit()) {
286 // FIXME: Verify
287 setExceptionPointerRegister(X86::RAX);
288 setExceptionSelectorRegister(X86::RDX);
289 } else {
290 setExceptionPointerRegister(X86::EAX);
291 setExceptionSelectorRegister(X86::EDX);
292 }
Anton Korobeynikov38252622007-09-03 00:36:06 +0000293 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
Anton Korobeynikovce3b4652007-05-02 19:53:33 +0000294
Duncan Sandsf7331b32007-09-11 14:10:23 +0000295 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
Duncan Sandsb116fac2007-07-27 20:02:49 +0000296
Nate Begemanacc398c2006-01-25 18:21:52 +0000297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
Nate Begemanacc398c2006-01-25 18:21:52 +0000299 setOperationAction(ISD::VAARG , MVT::Other, Expand);
Nate Begemanacc398c2006-01-25 18:21:52 +0000300 setOperationAction(ISD::VAEND , MVT::Other, Expand);
Evan Chengae642192007-03-02 23:16:35 +0000301 if (Subtarget->is64Bit())
302 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
303 else
304 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
305
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000306 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
Chris Lattnere1125522006-01-15 09:00:21 +0000307 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Evan Cheng25ab6902006-09-08 06:48:29 +0000308 if (Subtarget->is64Bit())
309 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +0000310 if (Subtarget->isTargetCygMing())
311 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
312 else
313 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
Chris Lattnerb99329e2006-01-13 02:42:53 +0000314
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000315 if (X86ScalarSSEf64) {
316 // f32 and f64 use SSE.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000317 // Set up the FP register classes.
Evan Cheng5ee4ccc2006-01-12 08:27:59 +0000318 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
319 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000320
Evan Cheng223547a2006-01-31 22:28:30 +0000321 // Use ANDPD to simulate FABS.
322 setOperationAction(ISD::FABS , MVT::f64, Custom);
323 setOperationAction(ISD::FABS , MVT::f32, Custom);
324
325 // Use XORP to simulate FNEG.
326 setOperationAction(ISD::FNEG , MVT::f64, Custom);
327 setOperationAction(ISD::FNEG , MVT::f32, Custom);
328
Evan Cheng68c47cb2007-01-05 07:55:56 +0000329 // Use ANDPD and ORPD to simulate FCOPYSIGN.
330 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
331 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
332
Evan Chengd25e9e82006-02-02 00:28:23 +0000333 // We don't support sin/cos/fmod
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000334 setOperationAction(ISD::FSIN , MVT::f64, Expand);
335 setOperationAction(ISD::FCOS , MVT::f64, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000336 setOperationAction(ISD::FREM , MVT::f64, Expand);
337 setOperationAction(ISD::FSIN , MVT::f32, Expand);
338 setOperationAction(ISD::FCOS , MVT::f32, Expand);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000339 setOperationAction(ISD::FREM , MVT::f32, Expand);
340
Chris Lattnera54aa942006-01-29 06:26:08 +0000341 // Expand FP immediates into loads from the stack, except for the special
342 // cases we handle.
343 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
344 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000345 addLegalFPImmediate(APFloat(+0.0)); // xorpd
346 addLegalFPImmediate(APFloat(+0.0f)); // xorps
Dale Johannesen5411a392007-08-09 01:04:01 +0000347
348 // Conversions to long double (in X87) go through memory.
349 setConvertAction(MVT::f32, MVT::f80, Expand);
350 setConvertAction(MVT::f64, MVT::f80, Expand);
351
352 // Conversions from long double (in X87) go through memory.
353 setConvertAction(MVT::f80, MVT::f32, Expand);
354 setConvertAction(MVT::f80, MVT::f64, Expand);
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000355 } else if (X86ScalarSSEf32) {
356 // Use SSE for f32, x87 for f64.
357 // Set up the FP register classes.
358 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
359 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
360
361 // Use ANDPS to simulate FABS.
362 setOperationAction(ISD::FABS , MVT::f32, Custom);
363
364 // Use XORP to simulate FNEG.
365 setOperationAction(ISD::FNEG , MVT::f32, Custom);
366
367 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
368
369 // Use ANDPS and ORPS to simulate FCOPYSIGN.
370 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
371 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
372
373 // We don't support sin/cos/fmod
374 setOperationAction(ISD::FSIN , MVT::f32, Expand);
375 setOperationAction(ISD::FCOS , MVT::f32, Expand);
376 setOperationAction(ISD::FREM , MVT::f32, Expand);
377
378 // Expand FP immediates into loads from the stack, except for the special
379 // cases we handle.
380 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
381 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
382 addLegalFPImmediate(APFloat(+0.0f)); // xorps
383 addLegalFPImmediate(APFloat(+0.0)); // FLD0
384 addLegalFPImmediate(APFloat(+1.0)); // FLD1
385 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
386 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
387
388 // SSE->x87 conversions go through memory.
389 setConvertAction(MVT::f32, MVT::f64, Expand);
390 setConvertAction(MVT::f32, MVT::f80, Expand);
391
392 // x87->SSE truncations need to go through memory.
393 setConvertAction(MVT::f80, MVT::f32, Expand);
394 setConvertAction(MVT::f64, MVT::f32, Expand);
395 // And x87->x87 truncations also.
396 setConvertAction(MVT::f80, MVT::f64, Expand);
397
398 if (!UnsafeFPMath) {
399 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
400 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
401 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000402 } else {
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000403 // f32 and f64 in x87.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000404 // Set up the FP register classes.
Dale Johannesen849f2142007-07-03 00:53:03 +0000405 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
406 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000407
Evan Cheng68c47cb2007-01-05 07:55:56 +0000408 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
Dale Johannesen849f2142007-07-03 00:53:03 +0000409 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
Evan Cheng68c47cb2007-01-05 07:55:56 +0000410 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
411 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
Dale Johannesen5411a392007-08-09 01:04:01 +0000412
413 // Floating truncations need to go through memory.
414 setConvertAction(MVT::f80, MVT::f32, Expand);
415 setConvertAction(MVT::f64, MVT::f32, Expand);
416 setConvertAction(MVT::f80, MVT::f64, Expand);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000417
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000418 if (!UnsafeFPMath) {
419 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
420 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
421 }
422
Chris Lattnera54aa942006-01-29 06:26:08 +0000423 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
Dale Johannesen849f2142007-07-03 00:53:03 +0000424 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
Dale Johannesenf04afdb2007-08-30 00:23:21 +0000425 addLegalFPImmediate(APFloat(+0.0)); // FLD0
426 addLegalFPImmediate(APFloat(+1.0)); // FLD1
427 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
428 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000429 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
430 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
431 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
432 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000433 }
Evan Cheng470a6ad2006-02-22 02:26:30 +0000434
Dale Johannesen59a58732007-08-05 18:49:15 +0000435 // Long double always uses X87.
436 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +0000437 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
438 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
439 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Dale Johannesen2f429012007-09-26 21:10:55 +0000440 if (!UnsafeFPMath) {
441 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
442 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
443 }
Dale Johannesen59a58732007-08-05 18:49:15 +0000444
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000445 // Always use a library call for pow.
446 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
447 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
448 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
449
Evan Chengd30bf012006-03-01 01:11:20 +0000450 // First set operation action for all vector types to expand. Then we
451 // will selectively turn on ones that can be effectively codegen'd.
Dan Gohmanfa0f77d2007-05-18 18:44:07 +0000452 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
453 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
Evan Chengd30bf012006-03-01 01:11:20 +0000454 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
455 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000456 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
Evan Chenga72cb0e2007-06-29 00:18:15 +0000457 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000458 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
Evan Chengd30bf012006-03-01 01:11:20 +0000459 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000460 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
461 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
462 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
463 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
464 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
465 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
Evan Chengd30bf012006-03-01 01:11:20 +0000466 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
Evan Chengb067a1e2006-03-31 19:22:53 +0000467 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
Chris Lattner9b3bd462006-03-21 20:51:05 +0000468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
Evan Chengb067a1e2006-03-31 19:22:53 +0000469 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
Dan Gohman20382522007-07-10 00:05:58 +0000470 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
471 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
472 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
473 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
474 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
475 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
476 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
Dan Gohman525178c2007-10-08 18:33:35 +0000477 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
478 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
479 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
480 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000481 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
Dan Gohmanf0d00892007-10-12 14:09:42 +0000482 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
483 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
484 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
Dan Gohman89081322007-12-12 22:21:26 +0000485 setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
486 setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
487 setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
488 setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
489 setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
490 setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
Evan Chengd30bf012006-03-01 01:11:20 +0000491 }
492
Evan Chenga88973f2006-03-22 19:22:18 +0000493 if (Subtarget->hasMMX()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000494 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
495 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
496 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000497 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000498
Evan Chengd30bf012006-03-01 01:11:20 +0000499 // FIXME: add MMX packed arithmetics
Bill Wendlingbc9bffa2007-03-07 05:43:18 +0000500
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000501 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
502 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
503 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
Chris Lattner6c284d72007-04-12 04:14:49 +0000504 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000505
Bill Wendlingc1fb0472007-03-10 09:57:05 +0000506 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
507 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
508 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
Dale Johannesen8d26e592007-10-30 01:18:38 +0000509 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
Bill Wendlingc1fb0472007-03-10 09:57:05 +0000510
Bill Wendling74027e92007-03-15 21:24:36 +0000511 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
512 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
513
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000514 setOperationAction(ISD::AND, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000515 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000516 setOperationAction(ISD::AND, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000517 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
518 setOperationAction(ISD::AND, MVT::v2i32, Promote);
519 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
520 setOperationAction(ISD::AND, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000521
522 setOperationAction(ISD::OR, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000523 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000524 setOperationAction(ISD::OR, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000525 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
526 setOperationAction(ISD::OR, MVT::v2i32, Promote);
527 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
528 setOperationAction(ISD::OR, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000529
530 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000531 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000532 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
Bill Wendlingab5b49d2007-03-26 08:03:33 +0000533 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
534 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
535 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
536 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
Bill Wendling1b7a81d2007-03-16 09:44:46 +0000537
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000538 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000539 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000540 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Bill Wendlingeebc8a12007-03-26 07:53:08 +0000541 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
542 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
543 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
544 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
Bill Wendling2f88dcd2007-03-08 22:09:11 +0000545
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000546 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
547 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
548 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
549 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
Bill Wendlinga348c562007-03-22 18:42:45 +0000550
551 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
552 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
553 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
Bill Wendlingccc44ad2007-03-27 20:22:40 +0000554 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
Bill Wendling826f36f2007-03-28 00:57:11 +0000555
556 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
557 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
Bill Wendling2f9bb1a2007-04-24 21:16:55 +0000558 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
559 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000560 }
561
Evan Chenga88973f2006-03-22 19:22:18 +0000562 if (Subtarget->hasSSE1()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000563 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
564
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000565 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
566 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
567 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
568 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
Dan Gohman20382522007-07-10 00:05:58 +0000569 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
570 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000571 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
572 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
573 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
Evan Cheng11e15b32006-04-03 20:53:28 +0000574 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000575 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000576 }
577
Evan Chenga88973f2006-03-22 19:22:18 +0000578 if (Subtarget->hasSSE2()) {
Evan Cheng470a6ad2006-02-22 02:26:30 +0000579 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
580 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
581 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
582 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
583 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
584
Evan Chengf7c378e2006-04-10 07:23:14 +0000585 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
586 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
587 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
Evan Cheng37e88562007-03-12 22:58:52 +0000588 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
Evan Chengf7c378e2006-04-10 07:23:14 +0000589 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
590 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
591 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
Evan Cheng37e88562007-03-12 22:58:52 +0000592 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
Evan Chengf9989842006-04-13 05:10:25 +0000593 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
Evan Cheng6bdb3f62006-10-27 18:49:08 +0000594 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
595 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
596 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
597 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
Dan Gohman20382522007-07-10 00:05:58 +0000598 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
599 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000600
Evan Chengf7c378e2006-04-10 07:23:14 +0000601 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
602 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
Evan Chengb067a1e2006-03-31 19:22:53 +0000603 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
Evan Cheng5edb8d22006-04-17 22:04:06 +0000604 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
605 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
606 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
Evan Chengf7c378e2006-04-10 07:23:14 +0000607
Evan Cheng2c3ae372006-04-12 21:21:57 +0000608 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
609 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
Nate Begeman844e0f92007-12-11 01:41:33 +0000610 // Do not attempt to custom lower non-power-of-2 vectors
611 if (!isPowerOf2_32(MVT::getVectorNumElements(VT)))
612 continue;
Evan Cheng2c3ae372006-04-12 21:21:57 +0000613 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
614 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
615 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
616 }
617 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
618 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
619 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
620 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
621 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
Dale Johannesen25f1d082007-10-31 00:32:36 +0000622 if (Subtarget->is64Bit())
623 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000624
Anton Korobeynikov12c49af2006-11-21 00:01:06 +0000625 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
Evan Cheng2c3ae372006-04-12 21:21:57 +0000626 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
627 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
628 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
629 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
630 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
631 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
632 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
Evan Cheng91b740d2006-04-12 17:12:36 +0000633 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
634 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000635 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
636 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
Evan Chengf7c378e2006-04-10 07:23:14 +0000637 }
Evan Cheng2c3ae372006-04-12 21:21:57 +0000638
639 // Custom lower v2i64 and v2f64 selects.
640 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
Evan Cheng91b740d2006-04-12 17:12:36 +0000641 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
Evan Chengf7c378e2006-04-10 07:23:14 +0000642 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
Evan Cheng2c3ae372006-04-12 21:21:57 +0000643 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
Evan Cheng470a6ad2006-02-22 02:26:30 +0000644 }
645
Evan Cheng6be2c582006-04-05 23:38:46 +0000646 // We want to custom lower some of our intrinsics.
647 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
648
Evan Cheng206ee9d2006-07-07 08:33:52 +0000649 // We have target-specific dag combine patterns for the following nodes:
650 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
Chris Lattner83e6c992006-10-04 06:57:07 +0000651 setTargetDAGCombine(ISD::SELECT);
Evan Cheng206ee9d2006-07-07 08:33:52 +0000652
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000653 computeRegisterProperties();
654
Evan Cheng87ed7162006-02-14 08:25:08 +0000655 // FIXME: These should be based on subtarget info. Plus, the values should
656 // be smaller when we are in optimizing for size mode.
Evan Chenga03a5dc2006-02-14 08:38:30 +0000657 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
658 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
659 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000660 allowUnalignedMemoryAccesses = true; // x86 supports it!
661}
662
Chris Lattner2b02a442007-02-25 08:29:00 +0000663
Evan Chengcc415862007-11-09 01:32:10 +0000664/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
665/// jumptable.
666SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
667 SelectionDAG &DAG) const {
668 if (usesGlobalOffsetTable())
669 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
670 if (!Subtarget->isPICStyleRIPRel())
671 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
672 return Table;
673}
674
Chris Lattner2b02a442007-02-25 08:29:00 +0000675//===----------------------------------------------------------------------===//
676// Return Value Calling Convention Implementation
677//===----------------------------------------------------------------------===//
678
Chris Lattner59ed56b2007-02-28 04:55:35 +0000679#include "X86GenCallingConv.inc"
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000680
681/// GetPossiblePreceedingTailCall - Get preceeding X86ISD::TAILCALL node if it
682/// exists skip possible ISD:TokenFactor.
683static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain) {
684 if (Chain.getOpcode()==X86ISD::TAILCALL) {
685 return Chain;
686 } else if (Chain.getOpcode()==ISD::TokenFactor) {
687 if (Chain.getNumOperands() &&
688 Chain.getOperand(0).getOpcode()==X86ISD::TAILCALL)
689 return Chain.getOperand(0);
690 }
691 return Chain;
692}
Chris Lattner9774c912007-02-27 05:28:59 +0000693
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000694/// LowerRET - Lower an ISD::RET node.
695SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
696 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
697
Chris Lattner9774c912007-02-27 05:28:59 +0000698 SmallVector<CCValAssign, 16> RVLocs;
699 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
Chris Lattner52387be2007-06-19 00:13:10 +0000700 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
701 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
Chris Lattnere32bbf62007-02-28 07:09:55 +0000702 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000703
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000704 // If this is the first return lowered for this function, add the regs to the
705 // liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +0000706 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Chris Lattner9774c912007-02-27 05:28:59 +0000707 for (unsigned i = 0; i != RVLocs.size(); ++i)
708 if (RVLocs[i].isRegLoc())
Chris Lattner84bc5422007-12-31 04:13:23 +0000709 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000710 }
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000711 SDOperand Chain = Op.getOperand(0);
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000712
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000713 // Handle tail call return.
714 Chain = GetPossiblePreceedingTailCall(Chain);
715 if (Chain.getOpcode() == X86ISD::TAILCALL) {
716 SDOperand TailCall = Chain;
717 SDOperand TargetAddress = TailCall.getOperand(1);
718 SDOperand StackAdjustment = TailCall.getOperand(2);
719 assert ( ((TargetAddress.getOpcode() == ISD::Register &&
720 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
721 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
722 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
723 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
724 "Expecting an global address, external symbol, or register");
725 assert( StackAdjustment.getOpcode() == ISD::Constant &&
726 "Expecting a const value");
727
728 SmallVector<SDOperand,8> Operands;
729 Operands.push_back(Chain.getOperand(0));
730 Operands.push_back(TargetAddress);
731 Operands.push_back(StackAdjustment);
732 // Copy registers used by the call. Last operand is a flag so it is not
733 // copied.
Arnold Schwaighofer448175f2007-10-16 09:05:00 +0000734 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000735 Operands.push_back(Chain.getOperand(i));
736 }
Arnold Schwaighofer448175f2007-10-16 09:05:00 +0000737 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
738 Operands.size());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000739 }
740
741 // Regular return.
742 SDOperand Flag;
743
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000744 // Copy the result values into the output registers.
Chris Lattner9774c912007-02-27 05:28:59 +0000745 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
746 RVLocs[0].getLocReg() != X86::ST0) {
747 for (unsigned i = 0; i != RVLocs.size(); ++i) {
748 CCValAssign &VA = RVLocs[i];
749 assert(VA.isRegLoc() && "Can only return in registers!");
750 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
751 Flag);
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000752 Flag = Chain.getValue(1);
753 }
754 } else {
755 // We need to handle a destination of ST0 specially, because it isn't really
756 // a register.
757 SDOperand Value = Op.getOperand(1);
758
759 // If this is an FP return with ScalarSSE, we need to move the value from
760 // an XMM register onto the fp-stack.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000761 if ((X86ScalarSSEf32 && RVLocs[0].getValVT()==MVT::f32) ||
762 (X86ScalarSSEf64 && RVLocs[0].getValVT()==MVT::f64)) {
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000763 SDOperand MemLoc;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000764
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000765 // If this is a load into a scalarsse value, don't store the loaded value
766 // back to the stack, only to reload it: just replace the scalar-sse load.
767 if (ISD::isNON_EXTLoad(Value.Val) &&
768 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
769 Chain = Value.getOperand(0);
770 MemLoc = Value.getOperand(1);
771 } else {
772 // Spill the value to memory and reload it into top of stack.
Chris Lattner9774c912007-02-27 05:28:59 +0000773 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000774 MachineFunction &MF = DAG.getMachineFunction();
775 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
776 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
777 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
778 }
Dale Johannesen849f2142007-07-03 00:53:03 +0000779 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other);
Chris Lattner9774c912007-02-27 05:28:59 +0000780 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
Chris Lattner2a9bdd72007-02-25 09:12:39 +0000781 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
782 Chain = Value.getValue(1);
783 }
784
785 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
786 SDOperand Ops[] = { Chain, Value };
787 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
788 Flag = Chain.getValue(1);
789 }
790
791 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
792 if (Flag.Val)
793 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
794 else
795 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
796}
797
798
Chris Lattner3085e152007-02-25 08:59:22 +0000799/// LowerCallResult - Lower the result values of an ISD::CALL into the
800/// appropriate copies out of appropriate physical registers. This assumes that
801/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
802/// being lowered. The returns a SDNode with the same number of values as the
803/// ISD::CALL.
804SDNode *X86TargetLowering::
805LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
806 unsigned CallingConv, SelectionDAG &DAG) {
Chris Lattnere32bbf62007-02-28 07:09:55 +0000807
808 // Assign locations to each value returned by this call.
Chris Lattner9774c912007-02-27 05:28:59 +0000809 SmallVector<CCValAssign, 16> RVLocs;
Chris Lattner52387be2007-06-19 00:13:10 +0000810 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
811 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
Chris Lattnere32bbf62007-02-28 07:09:55 +0000812 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
813
Chris Lattnere32bbf62007-02-28 07:09:55 +0000814 SmallVector<SDOperand, 8> ResultVals;
Chris Lattner3085e152007-02-25 08:59:22 +0000815
816 // Copy all of the result registers out of their specified physreg.
Chris Lattner9774c912007-02-27 05:28:59 +0000817 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
818 for (unsigned i = 0; i != RVLocs.size(); ++i) {
819 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
820 RVLocs[i].getValVT(), InFlag).getValue(1);
Chris Lattner3085e152007-02-25 08:59:22 +0000821 InFlag = Chain.getValue(2);
822 ResultVals.push_back(Chain.getValue(0));
823 }
824 } else {
825 // Copies from the FP stack are special, as ST0 isn't a valid register
826 // before the fp stackifier runs.
827
828 // Copy ST0 into an RFP register with FP_GET_RESULT.
Dale Johannesen849f2142007-07-03 00:53:03 +0000829 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other, MVT::Flag);
Chris Lattner3085e152007-02-25 08:59:22 +0000830 SDOperand GROps[] = { Chain, InFlag };
831 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
832 Chain = RetVal.getValue(1);
833 InFlag = RetVal.getValue(2);
834
835 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
836 // an XMM register.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000837 if ((X86ScalarSSEf32 && RVLocs[0].getValVT() == MVT::f32) ||
838 (X86ScalarSSEf64 && RVLocs[0].getValVT() == MVT::f64)) {
Chris Lattner112dedc2007-12-29 06:41:28 +0000839 SDOperand StoreLoc;
840 const Value *SrcVal = 0;
841 int SrcValOffset = 0;
Chris Lattnerd60eedc2007-12-29 06:57:38 +0000842 MVT::ValueType RetStoreVT = RVLocs[0].getValVT();
Chris Lattner112dedc2007-12-29 06:41:28 +0000843
844 // Determine where to store the value. If the call result is directly
845 // used by a store, see if we can store directly into the location. In
846 // this case, we'll end up producing a fst + movss[load] + movss[store] to
847 // the same location, and the two movss's will be nuked as dead. This
848 // optimizes common things like "*D = atof(..)" to not need an
849 // intermediate stack slot.
850 if (SDOperand(TheCall, 0).hasOneUse() &&
851 SDOperand(TheCall, 1).hasOneUse()) {
Chris Lattnerd60eedc2007-12-29 06:57:38 +0000852 // In addition to direct uses, we also support a FP_ROUND that uses the
853 // value, if it is directly stored somewhere.
854 SDNode *User = *TheCall->use_begin();
855 if (User->getOpcode() == ISD::FP_ROUND && User->hasOneUse())
856 User = *User->use_begin();
857
Chris Lattner112dedc2007-12-29 06:41:28 +0000858 // Ok, we have one use of the value and one use of the chain. See if
859 // they are the same node: a store.
Chris Lattnerd60eedc2007-12-29 06:57:38 +0000860 if (StoreSDNode *N = dyn_cast<StoreSDNode>(User)) {
861 // Verify that the value being stored is either the call or a
862 // truncation of the call.
863 SDNode *StoreVal = N->getValue().Val;
864 if (StoreVal == TheCall)
865 ; // ok.
866 else if (StoreVal->getOpcode() == ISD::FP_ROUND &&
867 StoreVal->hasOneUse() &&
868 StoreVal->getOperand(0).Val == TheCall)
869 ; // ok.
870 else
871 N = 0; // not ok.
872
873 if (N && N->getChain().Val == TheCall &&
Chris Lattner112dedc2007-12-29 06:41:28 +0000874 !N->isVolatile() && !N->isTruncatingStore() &&
875 N->getAddressingMode() == ISD::UNINDEXED) {
876 StoreLoc = N->getBasePtr();
877 SrcVal = N->getSrcValue();
878 SrcValOffset = N->getSrcValueOffset();
Chris Lattnerd60eedc2007-12-29 06:57:38 +0000879 RetStoreVT = N->getValue().getValueType();
Chris Lattner112dedc2007-12-29 06:41:28 +0000880 }
881 }
882 }
883
884 // If we weren't able to optimize the result, just create a temporary
885 // stack slot.
886 if (StoreLoc.Val == 0) {
887 MachineFunction &MF = DAG.getMachineFunction();
888 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
889 StoreLoc = DAG.getFrameIndex(SSFI, getPointerTy());
890 }
891
Chris Lattner3085e152007-02-25 08:59:22 +0000892 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
893 // shouldn't be necessary except that RFP cannot be live across
Chris Lattner112dedc2007-12-29 06:41:28 +0000894 // multiple blocks (which could happen if a select gets lowered into
895 // multiple blocks and scheduled in between them). When stackifier is
896 // fixed, they can be uncoupled.
Chris Lattner3085e152007-02-25 08:59:22 +0000897 SDOperand Ops[] = {
Chris Lattnerd60eedc2007-12-29 06:57:38 +0000898 Chain, RetVal, StoreLoc, DAG.getValueType(RetStoreVT), InFlag
Chris Lattner3085e152007-02-25 08:59:22 +0000899 };
900 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
Chris Lattnerd60eedc2007-12-29 06:57:38 +0000901 RetVal = DAG.getLoad(RetStoreVT, Chain,
Chris Lattner112dedc2007-12-29 06:41:28 +0000902 StoreLoc, SrcVal, SrcValOffset);
Chris Lattner3085e152007-02-25 08:59:22 +0000903 Chain = RetVal.getValue(1);
Chris Lattnerd60eedc2007-12-29 06:57:38 +0000904
905 // If we optimized a truncate, then extend the result back to its desired
906 // type.
907 if (RVLocs[0].getValVT() != RetStoreVT)
908 RetVal = DAG.getNode(ISD::FP_EXTEND, RVLocs[0].getValVT(), RetVal);
Chris Lattner3085e152007-02-25 08:59:22 +0000909 }
Chris Lattner3085e152007-02-25 08:59:22 +0000910 ResultVals.push_back(RetVal);
911 }
912
913 // Merge everything together with a MERGE_VALUES node.
914 ResultVals.push_back(Chain);
915 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
916 &ResultVals[0], ResultVals.size()).Val;
Chris Lattner2b02a442007-02-25 08:29:00 +0000917}
918
919
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000920//===----------------------------------------------------------------------===//
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000921// C & StdCall & Fast Calling Convention implementation
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000922//===----------------------------------------------------------------------===//
Anton Korobeynikovb10308e2007-01-28 13:31:35 +0000923// StdCall calling convention seems to be standard for many Windows' API
924// routines and around. It differs from C calling convention just a little:
925// callee should clean up the stack, not caller. Symbols should be also
926// decorated in some fancy way :) It doesn't support any vector arguments.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000927// For info on fast calling convention see Fast Calling Convention (tail call)
928// implementation LowerX86_32FastCCCallTo.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +0000929
Evan Cheng85e38002006-04-27 05:35:28 +0000930/// AddLiveIn - This helper function adds the specified physical register to the
931/// MachineFunction as a live in value. It also creates a corresponding virtual
932/// register for it.
933static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
Anton Korobeynikovb10308e2007-01-28 13:31:35 +0000934 const TargetRegisterClass *RC) {
Evan Cheng85e38002006-04-27 05:35:28 +0000935 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000936 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
937 MF.getRegInfo().addLiveIn(PReg, VReg);
Evan Cheng85e38002006-04-27 05:35:28 +0000938 return VReg;
939}
940
Gordon Henriksen86737662008-01-05 16:56:59 +0000941// Determines whether a CALL node uses struct return semantics.
942static bool CallIsStructReturn(SDOperand Op) {
943 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
944 if (!NumOps)
945 return false;
946
947 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(6));
948 return Flags->getValue() & ISD::ParamFlags::StructReturn;
949}
950
951// Determines whether a FORMAL_ARGUMENTS node uses struct return semantics.
952static bool ArgsAreStructReturn(SDOperand Op) {
953 unsigned NumArgs = Op.Val->getNumValues() - 1;
954 if (!NumArgs)
955 return false;
956
957 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(3));
958 return Flags->getValue() & ISD::ParamFlags::StructReturn;
959}
960
961// Determines whether a CALL or FORMAL_ARGUMENTS node requires the callee to pop
962// its own arguments. Callee pop is necessary to support tail calls.
963bool X86TargetLowering::IsCalleePop(SDOperand Op) {
964 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
965 if (IsVarArg)
966 return false;
967
968 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
969 default:
970 return false;
971 case CallingConv::X86_StdCall:
972 return !Subtarget->is64Bit();
973 case CallingConv::X86_FastCall:
974 return !Subtarget->is64Bit();
975 case CallingConv::Fast:
976 return PerformTailCallOpt;
977 }
978}
979
980// Selects the correct CCAssignFn for a CALL or FORMAL_ARGUMENTS node.
981CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
982 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
983
984 if (Subtarget->is64Bit())
985 if (CC == CallingConv::Fast && PerformTailCallOpt)
986 return CC_X86_64_TailCall;
987 else
988 return CC_X86_64_C;
989
990 if (CC == CallingConv::X86_FastCall)
991 return CC_X86_32_FastCall;
992 else if (CC == CallingConv::Fast && PerformTailCallOpt)
993 return CC_X86_32_TailCall;
994 else
995 return CC_X86_32_C;
996}
997
998// Selects the appropriate decoration to apply to a MachineFunction containing a
999// given FORMAL_ARGUMENTS node.
1000NameDecorationStyle
1001X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
1002 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1003 if (CC == CallingConv::X86_FastCall)
1004 return FastCall;
1005 else if (CC == CallingConv::X86_StdCall)
1006 return StdCall;
1007 return None;
1008}
1009
Rafael Espindola7effac52007-09-14 15:48:13 +00001010SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1011 const CCValAssign &VA,
1012 MachineFrameInfo *MFI,
1013 SDOperand Root, unsigned i) {
1014 // Create the nodes corresponding to a load from this parameter slot.
1015 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1016 VA.getLocMemOffset());
1017 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1018
1019 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
1020
1021 if (Flags & ISD::ParamFlags::ByVal)
1022 return FIN;
1023 else
1024 return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0);
1025}
1026
Gordon Henriksen86737662008-01-05 16:56:59 +00001027SDOperand
1028X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng1bc78042006-04-26 01:20:17 +00001029 MachineFunction &MF = DAG.getMachineFunction();
Gordon Henriksen86737662008-01-05 16:56:59 +00001030 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1031
1032 const Function* Fn = MF.getFunction();
1033 if (Fn->hasExternalLinkage() &&
1034 Subtarget->isTargetCygMing() &&
1035 Fn->getName() == "main")
1036 FuncInfo->setForceFramePointer(true);
1037
1038 // Decorate the function name.
1039 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1040
Evan Cheng1bc78042006-04-26 01:20:17 +00001041 MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng25caf632006-05-23 21:06:34 +00001042 SDOperand Root = Op.getOperand(0);
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001043 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001044 unsigned CC = MF.getFunction()->getCallingConv();
Gordon Henriksen86737662008-01-05 16:56:59 +00001045 bool Is64Bit = Subtarget->is64Bit();
Gordon Henriksenae636f82008-01-03 16:47:34 +00001046
1047 assert(!(isVarArg && CC == CallingConv::Fast) &&
1048 "Var args not supported with calling convention fastcc");
1049
Chris Lattner638402b2007-02-28 07:00:42 +00001050 // Assign locations to all of the incoming arguments.
Chris Lattnerf39f7712007-02-28 05:46:49 +00001051 SmallVector<CCValAssign, 16> ArgLocs;
Gordon Henriksenae636f82008-01-03 16:47:34 +00001052 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
Gordon Henriksen86737662008-01-05 16:56:59 +00001053 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001054
Chris Lattnerf39f7712007-02-28 05:46:49 +00001055 SmallVector<SDOperand, 8> ArgValues;
1056 unsigned LastVal = ~0U;
1057 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1058 CCValAssign &VA = ArgLocs[i];
1059 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1060 // places.
1061 assert(VA.getValNo() != LastVal &&
1062 "Don't support value assigned to multiple locs yet");
1063 LastVal = VA.getValNo();
1064
1065 if (VA.isRegLoc()) {
1066 MVT::ValueType RegVT = VA.getLocVT();
1067 TargetRegisterClass *RC;
1068 if (RegVT == MVT::i32)
1069 RC = X86::GR32RegisterClass;
Gordon Henriksen86737662008-01-05 16:56:59 +00001070 else if (Is64Bit && RegVT == MVT::i64)
1071 RC = X86::GR64RegisterClass;
1072 else if (Is64Bit && RegVT == MVT::f32)
1073 RC = X86::FR32RegisterClass;
1074 else if (Is64Bit && RegVT == MVT::f64)
1075 RC = X86::FR64RegisterClass;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001076 else {
1077 assert(MVT::isVector(RegVT));
Gordon Henriksen86737662008-01-05 16:56:59 +00001078 if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) {
1079 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1080 RegVT = MVT::i64;
1081 } else
1082 RC = X86::VR128RegisterClass;
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001083 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001084
Chris Lattner82932a52007-03-02 05:12:29 +00001085 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1086 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
Chris Lattnerf39f7712007-02-28 05:46:49 +00001087
1088 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1089 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1090 // right size.
1091 if (VA.getLocInfo() == CCValAssign::SExt)
1092 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1093 DAG.getValueType(VA.getValVT()));
1094 else if (VA.getLocInfo() == CCValAssign::ZExt)
1095 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1096 DAG.getValueType(VA.getValVT()));
1097
1098 if (VA.getLocInfo() != CCValAssign::Full)
1099 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1100
Gordon Henriksen86737662008-01-05 16:56:59 +00001101 // Handle MMX values passed in GPRs.
1102 if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1103 MVT::getSizeInBits(RegVT) == 64)
1104 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1105
Chris Lattnerf39f7712007-02-28 05:46:49 +00001106 ArgValues.push_back(ArgValue);
1107 } else {
1108 assert(VA.isMemLoc());
Rafael Espindola7effac52007-09-14 15:48:13 +00001109 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
Evan Cheng1bc78042006-04-26 01:20:17 +00001110 }
Evan Cheng1bc78042006-04-26 01:20:17 +00001111 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001112
Chris Lattnerf39f7712007-02-28 05:46:49 +00001113 unsigned StackSize = CCInfo.getNextStackOffset();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001114 // align stack specially for tail calls
Gordon Henriksenae636f82008-01-03 16:47:34 +00001115 if (CC == CallingConv::Fast)
1116 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
Evan Cheng25caf632006-05-23 21:06:34 +00001117
Evan Cheng1bc78042006-04-26 01:20:17 +00001118 // If the function takes variable number of arguments, make a frame index for
1119 // the start of the first vararg value... for expansion of llvm.va_start.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001120 if (isVarArg) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001121 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1122 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1123 }
1124 if (Is64Bit) {
1125 static const unsigned GPR64ArgRegs[] = {
1126 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1127 };
1128 static const unsigned XMMArgRegs[] = {
1129 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1130 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1131 };
1132
1133 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1134 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1135
1136 // For X86-64, if there are vararg parameters that are passed via
1137 // registers, then we must store them to their spots on the stack so they
1138 // may be loaded by deferencing the result of va_next.
1139 VarArgsGPOffset = NumIntRegs * 8;
1140 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1141 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1142
1143 // Store the integer parameter registers.
1144 SmallVector<SDOperand, 8> MemOps;
1145 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1146 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1147 DAG.getConstant(VarArgsGPOffset,
1148 getPointerTy()));
1149 for (; NumIntRegs != 6; ++NumIntRegs) {
1150 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1151 X86::GR64RegisterClass);
1152 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1153 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1154 MemOps.push_back(Store);
1155 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1156 DAG.getConstant(8, getPointerTy()));
1157 }
1158
1159 // Now store the XMM (fp + vector) parameter registers.
1160 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1161 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1162 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1163 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1164 X86::VR128RegisterClass);
1165 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1166 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1167 MemOps.push_back(Store);
1168 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1169 DAG.getConstant(16, getPointerTy()));
1170 }
1171 if (!MemOps.empty())
1172 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1173 &MemOps[0], MemOps.size());
1174 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001175 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001176
1177 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1178 // arguments and the arguments after the retaddr has been pushed are
1179 // aligned.
1180 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1181 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1182 (StackSize & 7) == 0)
1183 StackSize += 4;
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001184
Gordon Henriksenae636f82008-01-03 16:47:34 +00001185 ArgValues.push_back(Root);
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001186
Gordon Henriksen86737662008-01-05 16:56:59 +00001187 // Some CCs need callee pop.
1188 if (IsCalleePop(Op)) {
1189 BytesToPopOnReturn = StackSize; // Callee pops everything.
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001190 BytesCallerReserves = 0;
1191 } else {
Anton Korobeynikov1d9bacc2007-03-06 08:12:33 +00001192 BytesToPopOnReturn = 0; // Callee pops nothing.
Chris Lattnerf39f7712007-02-28 05:46:49 +00001193 // If this is an sret function, the return should pop the hidden pointer.
Gordon Henriksen86737662008-01-05 16:56:59 +00001194 if (!Is64Bit && ArgsAreStructReturn(Op))
Chris Lattnerf39f7712007-02-28 05:46:49 +00001195 BytesToPopOnReturn = 4;
Chris Lattnerf39f7712007-02-28 05:46:49 +00001196 BytesCallerReserves = StackSize;
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001197 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001198
Gordon Henriksen86737662008-01-05 16:56:59 +00001199 if (!Is64Bit) {
1200 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1201 if (CC == CallingConv::X86_FastCall)
1202 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1203 }
Evan Cheng25caf632006-05-23 21:06:34 +00001204
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001205 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
Evan Cheng1bc78042006-04-26 01:20:17 +00001206
Evan Cheng25caf632006-05-23 21:06:34 +00001207 // Return the new list of results.
Chris Lattner5a88b832007-02-25 07:10:00 +00001208 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
Chris Lattner14dd4c92007-02-26 07:50:02 +00001209 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001210}
1211
Gordon Henriksen86737662008-01-05 16:56:59 +00001212SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1213 MachineFunction &MF = DAG.getMachineFunction();
Evan Cheng32fe1032006-05-25 00:59:30 +00001214 SDOperand Chain = Op.getOperand(0);
Gordon Henriksen86737662008-01-05 16:56:59 +00001215 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001216 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
Gordon Henriksen86737662008-01-05 16:56:59 +00001217 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1218 && CC == CallingConv::Fast && PerformTailCallOpt;
Evan Cheng32fe1032006-05-25 00:59:30 +00001219 SDOperand Callee = Op.getOperand(4);
Gordon Henriksen86737662008-01-05 16:56:59 +00001220 bool Is64Bit = Subtarget->is64Bit();
Gordon Henriksenae636f82008-01-03 16:47:34 +00001221
1222 assert(!(isVarArg && CC == CallingConv::Fast) &&
1223 "Var args not supported with calling convention fastcc");
1224
Chris Lattner638402b2007-02-28 07:00:42 +00001225 // Analyze operands of the call, assigning locations to each operand.
Chris Lattner423c5f42007-02-28 05:31:48 +00001226 SmallVector<CCValAssign, 16> ArgLocs;
Chris Lattner52387be2007-06-19 00:13:10 +00001227 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
Gordon Henriksen86737662008-01-05 16:56:59 +00001228 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001229
Chris Lattner423c5f42007-02-28 05:31:48 +00001230 // Get a count of how many bytes are to be pushed on the stack.
1231 unsigned NumBytes = CCInfo.getNextStackOffset();
Gordon Henriksenae636f82008-01-03 16:47:34 +00001232 if (CC == CallingConv::Fast)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001233 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001234
Gordon Henriksen86737662008-01-05 16:56:59 +00001235 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1236 // arguments and the arguments after the retaddr has been pushed are aligned.
1237 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1238 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1239 (NumBytes & 7) == 0)
1240 NumBytes += 4;
1241
1242 int FPDiff = 0;
1243 if (IsTailCall) {
1244 // Lower arguments at fp - stackoffset + fpdiff.
1245 unsigned NumBytesCallerPushed =
1246 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1247 FPDiff = NumBytesCallerPushed - NumBytes;
1248
1249 // Set the delta of movement of the returnaddr stackslot.
1250 // But only set if delta is greater than previous delta.
1251 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1252 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1253 }
1254
Evan Cheng32fe1032006-05-25 00:59:30 +00001255 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001256
Gordon Henriksen86737662008-01-05 16:56:59 +00001257 SDOperand RetAddrFrIdx, NewRetAddrFrIdx;
1258 if (IsTailCall) {
1259 // Adjust the Return address stack slot.
1260 if (FPDiff) {
1261 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1262 RetAddrFrIdx = getReturnAddressFrameIndex(DAG);
1263 // Load the "old" Return address.
1264 RetAddrFrIdx =
1265 DAG.getLoad(VT, Chain,RetAddrFrIdx, NULL, 0);
1266 // Calculate the new stack slot for the return address.
1267 int SlotSize = Is64Bit ? 8 : 4;
1268 int NewReturnAddrFI =
1269 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1270 NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1271 Chain = SDOperand(RetAddrFrIdx.Val, 1);
1272 }
1273 }
1274
Chris Lattner5a88b832007-02-25 07:10:00 +00001275 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1276 SmallVector<SDOperand, 8> MemOpChains;
Evan Cheng32fe1032006-05-25 00:59:30 +00001277
Chris Lattner423c5f42007-02-28 05:31:48 +00001278 SDOperand StackPtr;
Chris Lattner423c5f42007-02-28 05:31:48 +00001279
1280 // Walk the register/memloc assignments, inserting copies/loads.
Gordon Henriksen86737662008-01-05 16:56:59 +00001281 // For tail calls, lower arguments first to the stack slot where they would
1282 // normally - in case of a normal function call - be.
Chris Lattner423c5f42007-02-28 05:31:48 +00001283 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1284 CCValAssign &VA = ArgLocs[i];
1285 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001286
Chris Lattner423c5f42007-02-28 05:31:48 +00001287 // Promote the value if needed.
1288 switch (VA.getLocInfo()) {
1289 default: assert(0 && "Unknown loc info!");
1290 case CCValAssign::Full: break;
1291 case CCValAssign::SExt:
1292 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1293 break;
1294 case CCValAssign::ZExt:
1295 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1296 break;
1297 case CCValAssign::AExt:
1298 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1299 break;
Evan Cheng6b5783d2006-05-25 18:56:34 +00001300 }
Chris Lattner423c5f42007-02-28 05:31:48 +00001301
1302 if (VA.isRegLoc()) {
1303 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1304 } else {
1305 assert(VA.isMemLoc());
1306 if (StackPtr.Val == 0)
1307 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
Rafael Espindolaa37ac9f2007-09-21 15:50:22 +00001308
1309 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1310 Arg));
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001311 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001312 }
Chris Lattnerc0bdf342007-02-28 05:39:26 +00001313
Evan Cheng32fe1032006-05-25 00:59:30 +00001314 if (!MemOpChains.empty())
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001315 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1316 &MemOpChains[0], MemOpChains.size());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001317
Evan Cheng347d5f72006-04-28 21:29:37 +00001318 // Build a sequence of copy-to-reg nodes chained together with token chain
1319 // and flag operands which copy the outgoing args into registers.
1320 SDOperand InFlag;
Evan Cheng32fe1032006-05-25 00:59:30 +00001321 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1322 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1323 InFlag);
Evan Cheng347d5f72006-04-28 21:29:37 +00001324 InFlag = Chain.getValue(1);
1325 }
Gordon Henriksen86737662008-01-05 16:56:59 +00001326
1327 if (IsTailCall)
1328 InFlag = SDOperand(); // ??? Isn't this nuking the preceding loop's output?
1329
Evan Chengf4684712007-02-21 21:18:14 +00001330 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1331 // GOT pointer.
Gordon Henriksen86737662008-01-05 16:56:59 +00001332 // Does not work with tail call since ebx is not restored correctly by
1333 // tailcaller. TODO: at least for x86 - verify for x86-64
1334 if (!IsTailCall && !Is64Bit &&
1335 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
Evan Cheng706535d2007-01-22 21:34:25 +00001336 Subtarget->isPICStyleGOT()) {
Anton Korobeynikov7f705592007-01-12 19:20:47 +00001337 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1338 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1339 InFlag);
1340 InFlag = Chain.getValue(1);
1341 }
Gordon Henriksenae636f82008-01-03 16:47:34 +00001342
Gordon Henriksen86737662008-01-05 16:56:59 +00001343 if (Is64Bit && isVarArg) {
1344 // From AMD64 ABI document:
1345 // For calls that may call functions that use varargs or stdargs
1346 // (prototype-less calls or calls to functions containing ellipsis (...) in
1347 // the declaration) %al is used as hidden argument to specify the number
1348 // of SSE registers used. The contents of %al do not need to match exactly
1349 // the number of registers, but must be an ubound on the number of SSE
1350 // registers used and is in the range 0 - 8 inclusive.
1351
1352 // Count the number of XMM registers allocated.
1353 static const unsigned XMMArgRegs[] = {
1354 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1355 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1356 };
1357 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1358
1359 Chain = DAG.getCopyToReg(Chain, X86::AL,
1360 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1361 InFlag = Chain.getValue(1);
1362 }
1363
1364 // Copy from stack slots to stack slot of a tail called function. This needs
1365 // to be done because if we would lower the arguments directly to their real
1366 // stack slot we might end up overwriting each other.
1367 // TODO: To make this more efficient (sometimes saving a store/load) we could
1368 // analyse the arguments and emit this store/load/store sequence only for
1369 // arguments which would be overwritten otherwise.
1370 if (IsTailCall) {
1371 SmallVector<SDOperand, 8> MemOpChains2;
1372 SDOperand PtrOff;
1373 SDOperand FIN;
1374 int FI = 0;
1375 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1376 CCValAssign &VA = ArgLocs[i];
1377 if (!VA.isRegLoc()) {
1378 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1379 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1380
1381 // Get source stack slot.
1382 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(),
1383 getPointerTy());
1384 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1385 // Create frame index.
1386 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1387 uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1388 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1389 FIN = DAG.getFrameIndex(FI, MVT::i32);
1390 if (Flags & ISD::ParamFlags::ByVal) {
1391 // Copy relative to framepointer.
1392 unsigned Align = 1 << ((Flags & ISD::ParamFlags::ByValAlign) >>
1393 ISD::ParamFlags::ByValAlignOffs);
1394
1395 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1396 ISD::ParamFlags::ByValSizeOffs;
1397
1398 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1399 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1400 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i1);
1401
1402 MemOpChains2.push_back(DAG.getMemcpy(Chain, FIN, PtrOff, SizeNode,
1403 AlignNode,AlwaysInline));
1404 } else {
1405 SDOperand LoadedArg = DAG.getLoad(VA.getValVT(), Chain, PtrOff,
1406 NULL, 0);
1407 // Store relative to framepointer.
1408 MemOpChains2.push_back(DAG.getStore(Chain, LoadedArg, FIN, NULL, 0));
1409 }
1410 }
1411 }
1412
1413 if (!MemOpChains2.empty())
1414 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1415 &MemOpChains2[0], MemOpChains.size());
1416
1417 // Store the return address to the appropriate stack slot.
1418 if (FPDiff)
1419 Chain = DAG.getStore(Chain,RetAddrFrIdx, NewRetAddrFrIdx, NULL, 0);
1420 }
1421
Evan Cheng32fe1032006-05-25 00:59:30 +00001422 // If the callee is a GlobalAddress node (quite common, every direct call is)
1423 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
Anton Korobeynikova5986852006-11-20 10:46:14 +00001424 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00001425 // We should use extra load for direct calls to dllimported functions in
1426 // non-JIT mode.
Gordon Henriksen86737662008-01-05 16:56:59 +00001427 if ((IsTailCall || !Is64Bit ||
1428 getTargetMachine().getCodeModel() != CodeModel::Large)
1429 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1430 getTargetMachine(), true))
Anton Korobeynikova5986852006-11-20 10:46:14 +00001431 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
Gordon Henriksenae636f82008-01-03 16:47:34 +00001432 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Gordon Henriksen86737662008-01-05 16:56:59 +00001433 if (IsTailCall || !Is64Bit ||
1434 getTargetMachine().getCodeModel() != CodeModel::Large)
1435 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1436 } else if (IsTailCall) {
1437 assert(Callee.getOpcode() == ISD::LOAD &&
1438 "Function destination must be loaded into virtual register");
1439 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1440
1441 Chain = DAG.getCopyToReg(Chain,
1442 DAG.getRegister(Opc, getPointerTy()) ,
1443 Callee,InFlag);
1444 Callee = DAG.getRegister(Opc, getPointerTy());
1445 // Add register as live out.
1446 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001447 }
1448
Chris Lattnerd96d0722007-02-25 06:40:16 +00001449 // Returns a chain & a flag for retval copy to use.
1450 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Chris Lattner5a88b832007-02-25 07:10:00 +00001451 SmallVector<SDOperand, 8> Ops;
Gordon Henriksen86737662008-01-05 16:56:59 +00001452
1453 if (IsTailCall) {
1454 Ops.push_back(Chain);
1455 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1456 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1457 if (InFlag.Val)
1458 Ops.push_back(InFlag);
1459 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1460 InFlag = Chain.getValue(1);
1461
1462 // Returns a chain & a flag for retval copy to use.
1463 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1464 Ops.clear();
1465 }
1466
Nate Begeman4c5dcf52006-02-17 00:03:04 +00001467 Ops.push_back(Chain);
1468 Ops.push_back(Callee);
Evan Chengb69d1132006-06-14 18:17:40 +00001469
Gordon Henriksen86737662008-01-05 16:56:59 +00001470 if (IsTailCall)
1471 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
Evan Chengf4684712007-02-21 21:18:14 +00001472
1473 // Add an implicit use GOT pointer in EBX.
Gordon Henriksen86737662008-01-05 16:56:59 +00001474 if (!IsTailCall && !Is64Bit &&
1475 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
Evan Chengf4684712007-02-21 21:18:14 +00001476 Subtarget->isPICStyleGOT())
1477 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
Gordon Henriksenae636f82008-01-03 16:47:34 +00001478
Gordon Henriksen86737662008-01-05 16:56:59 +00001479 // Add argument registers to the end of the list so that they are known live
1480 // into the call.
1481 if (IsTailCall)
1482 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1483 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1484 RegsToPass[i].second.getValueType()));
1485
Evan Cheng347d5f72006-04-28 21:29:37 +00001486 if (InFlag.Val)
1487 Ops.push_back(InFlag);
Gordon Henriksenae636f82008-01-03 16:47:34 +00001488
Gordon Henriksen86737662008-01-05 16:56:59 +00001489 if (IsTailCall) {
1490 assert(InFlag.Val &&
1491 "Flag must be set. Depend on flag being set in LowerRET");
1492 Chain = DAG.getNode(X86ISD::TAILCALL,
1493 Op.Val->getVTList(), &Ops[0], Ops.size());
1494
1495 return SDOperand(Chain.Val, Op.ResNo);
1496 }
1497
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001498 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
Evan Cheng347d5f72006-04-28 21:29:37 +00001499 InFlag = Chain.getValue(1);
Evan Chengd90eb7f2006-01-05 00:27:02 +00001500
Chris Lattner2d297092006-05-23 18:50:38 +00001501 // Create the CALLSEQ_END node.
Gordon Henriksen86737662008-01-05 16:56:59 +00001502 unsigned NumBytesForCalleeToPush;
1503 if (IsCalleePop(Op))
1504 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1505 else if (!Is64Bit && CallIsStructReturn(Op))
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001506 // If this is is a call to a struct-return function, the callee
1507 // pops the hidden struct pointer, so we have to push it back.
1508 // This is common for Darwin/X86, Linux & Mingw32 targets.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001509 NumBytesForCalleeToPush = 4;
Gordon Henriksen86737662008-01-05 16:56:59 +00001510 else
Gordon Henriksenae636f82008-01-03 16:47:34 +00001511 NumBytesForCalleeToPush = 0; // Callee pops nothing.
Gordon Henriksen86737662008-01-05 16:56:59 +00001512
Gordon Henriksenae636f82008-01-03 16:47:34 +00001513 // Returns a flag for retval copy to use.
Bill Wendling0f8d9c02007-11-13 00:44:25 +00001514 Chain = DAG.getCALLSEQ_END(Chain,
1515 DAG.getConstant(NumBytes, getPointerTy()),
1516 DAG.getConstant(NumBytesForCalleeToPush,
1517 getPointerTy()),
1518 InFlag);
Chris Lattner3085e152007-02-25 08:59:22 +00001519 InFlag = Chain.getValue(1);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00001520
Chris Lattner3085e152007-02-25 08:59:22 +00001521 // Handle result values, copying them out of physregs into vregs that we
1522 // return.
Chris Lattner09c75a42007-02-25 09:06:15 +00001523 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001524}
1525
Evan Cheng25ab6902006-09-08 06:48:29 +00001526
1527//===----------------------------------------------------------------------===//
Chris Lattnerfcf1a3d2007-02-28 06:10:12 +00001528// FastCall Calling Convention implementation
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001529//===----------------------------------------------------------------------===//
1530//
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00001531// The X86 'fastcall' calling convention passes up to two integer arguments in
1532// registers (an appropriate portion of ECX/EDX), passes arguments in C order,
1533// and requires that the callee pop its arguments off the stack (allowing proper
1534// tail calls), and has the same return value conventions as C calling convs.
1535//
1536// This calling convention always arranges for the callee pop value to be 8n+4
1537// bytes, which is needed for tail recursion elimination and stack alignment
1538// reasons.
Gordon Henriksenae636f82008-01-03 16:47:34 +00001539
Evan Cheng25caf632006-05-23 21:06:34 +00001540SDOperand
Rafael Espindola1b5dcc32007-08-31 15:06:30 +00001541X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1542 const SDOperand &StackPtr,
1543 const CCValAssign &VA,
1544 SDOperand Chain,
1545 SDOperand Arg) {
1546 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1547 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1548 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1549 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1550 if (Flags & ISD::ParamFlags::ByVal) {
1551 unsigned Align = 1 << ((Flags & ISD::ParamFlags::ByValAlign) >>
1552 ISD::ParamFlags::ByValAlignOffs);
1553
Rafael Espindola1b5dcc32007-08-31 15:06:30 +00001554 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1555 ISD::ParamFlags::ByValSizeOffs;
1556
1557 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1558 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
Chris Lattner27a6c732007-11-24 07:07:01 +00001559 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32);
Rafael Espindola1b5dcc32007-08-31 15:06:30 +00001560
Rafael Espindola5c0d6ed2007-10-19 10:41:11 +00001561 return DAG.getMemcpy(Chain, PtrOff, Arg, SizeNode, AlignNode,
1562 AlwaysInline);
Rafael Espindola1b5dcc32007-08-31 15:06:30 +00001563 } else {
1564 return DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1565 }
1566}
1567
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001568//===----------------------------------------------------------------------===//
1569// Fast Calling Convention (tail call) implementation
1570//===----------------------------------------------------------------------===//
1571
1572// Like std call, callee cleans arguments, convention except that ECX is
1573// reserved for storing the tail called function address. Only 2 registers are
1574// free for argument passing (inreg). Tail call optimization is performed
1575// provided:
1576// * tailcallopt is enabled
1577// * caller/callee are fastcc
1578// * elf/pic is disabled OR
1579// * elf/pic enabled + callee is in module + callee has
1580// visibility protected or hidden
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00001581// To keep the stack aligned according to platform abi the function
1582// GetAlignedArgumentStackSize ensures that argument delta is always multiples
1583// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001584// If a tail called function callee has more arguments than the caller the
1585// caller needs to make sure that there is room to move the RETADDR to. This is
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00001586// achieved by reserving an area the size of the argument delta right after the
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001587// original REtADDR, but before the saved framepointer or the spilled registers
1588// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1589// stack layout:
1590// arg1
1591// arg2
1592// RETADDR
1593// [ new RETADDR
1594// move area ]
1595// (possible EBP)
1596// ESI
1597// EDI
1598// local1 ..
1599
1600/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1601/// for a 16 byte align requirement.
1602unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1603 SelectionDAG& DAG) {
1604 if (PerformTailCallOpt) {
1605 MachineFunction &MF = DAG.getMachineFunction();
1606 const TargetMachine &TM = MF.getTarget();
1607 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1608 unsigned StackAlignment = TFI.getStackAlignment();
1609 uint64_t AlignMask = StackAlignment - 1;
1610 int64_t Offset = StackSize;
1611 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1612 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1613 // Number smaller than 12 so just add the difference.
1614 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1615 } else {
1616 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1617 Offset = ((~AlignMask) & Offset) + StackAlignment +
1618 (StackAlignment-SlotSize);
1619 }
1620 StackSize = Offset;
1621 }
1622 return StackSize;
1623}
1624
1625/// IsEligibleForTailCallElimination - Check to see whether the next instruction
Evan Cheng9df7dc52007-11-02 01:26:22 +00001626/// following the call is a return. A function is eligible if caller/callee
1627/// calling conventions match, currently only fastcc supports tail calls, and
1628/// the function CALL is immediatly followed by a RET.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001629bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1630 SDOperand Ret,
1631 SelectionDAG& DAG) const {
Evan Cheng9df7dc52007-11-02 01:26:22 +00001632 if (!PerformTailCallOpt)
1633 return false;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001634
1635 // Check whether CALL node immediatly preceeds the RET node and whether the
1636 // return uses the result of the node or is a void return.
Evan Cheng9df7dc52007-11-02 01:26:22 +00001637 unsigned NumOps = Ret.getNumOperands();
1638 if ((NumOps == 1 &&
1639 (Ret.getOperand(0) == SDOperand(Call.Val,1) ||
1640 Ret.getOperand(0) == SDOperand(Call.Val,0))) ||
Evan Chenga9d641e2007-11-02 17:45:40 +00001641 (NumOps > 1 &&
Evan Cheng9df7dc52007-11-02 01:26:22 +00001642 Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) &&
1643 Ret.getOperand(1) == SDOperand(Call.Val,0))) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001644 MachineFunction &MF = DAG.getMachineFunction();
1645 unsigned CallerCC = MF.getFunction()->getCallingConv();
1646 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1647 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1648 SDOperand Callee = Call.getOperand(4);
1649 // On elf/pic %ebx needs to be livein.
Evan Cheng9df7dc52007-11-02 01:26:22 +00001650 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1651 !Subtarget->isPICStyleGOT())
1652 return true;
1653
1654 // Can only do local tail calls with PIC.
Gordon Henriksen86737662008-01-05 16:56:59 +00001655 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1656 return G->getGlobal()->hasHiddenVisibility()
1657 || G->getGlobal()->hasProtectedVisibility();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001658 }
1659 }
Evan Cheng9df7dc52007-11-02 01:26:22 +00001660
1661 return false;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00001662}
1663
Chris Lattnerfcf1a3d2007-02-28 06:10:12 +00001664//===----------------------------------------------------------------------===//
1665// Other Lowering Hooks
1666//===----------------------------------------------------------------------===//
1667
1668
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001669SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001670 MachineFunction &MF = DAG.getMachineFunction();
1671 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1672 int ReturnAddrIndex = FuncInfo->getRAIndex();
1673
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001674 if (ReturnAddrIndex == 0) {
1675 // Set up a frame object for the return address.
Evan Cheng25ab6902006-09-08 06:48:29 +00001676 if (Subtarget->is64Bit())
1677 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1678 else
1679 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
Anton Korobeynikova2780e12007-08-15 17:12:32 +00001680
1681 FuncInfo->setRAIndex(ReturnAddrIndex);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001682 }
1683
Evan Cheng25ab6902006-09-08 06:48:29 +00001684 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00001685}
1686
1687
1688
Evan Cheng6dfa9992006-01-30 23:41:35 +00001689/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1690/// specific condition code. It returns a false if it cannot do a direct
Chris Lattnerf9570512006-09-13 03:22:10 +00001691/// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1692/// needed.
Evan Cheng6be2c582006-04-05 23:38:46 +00001693static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
Chris Lattnerf9570512006-09-13 03:22:10 +00001694 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1695 SelectionDAG &DAG) {
Chris Lattner7fbe9722006-10-20 17:42:20 +00001696 X86CC = X86::COND_INVALID;
Evan Chengd9558e02006-01-06 00:43:03 +00001697 if (!isFP) {
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001698 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1699 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1700 // X > -1 -> X == 0, jump !sign.
1701 RHS = DAG.getConstant(0, RHS.getValueType());
Chris Lattner7fbe9722006-10-20 17:42:20 +00001702 X86CC = X86::COND_NS;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001703 return true;
1704 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1705 // X < 0 -> X == 0, jump on sign.
Chris Lattner7fbe9722006-10-20 17:42:20 +00001706 X86CC = X86::COND_S;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001707 return true;
Dan Gohman5f6913c2007-09-17 14:49:27 +00001708 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1709 // X < 1 -> X <= 0
1710 RHS = DAG.getConstant(0, RHS.getValueType());
1711 X86CC = X86::COND_LE;
1712 return true;
Chris Lattnerbfd68a72006-09-13 17:04:54 +00001713 }
Chris Lattnerf9570512006-09-13 03:22:10 +00001714 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00001715
Evan Chengd9558e02006-01-06 00:43:03 +00001716 switch (SetCCOpcode) {
1717 default: break;
Chris Lattner7fbe9722006-10-20 17:42:20 +00001718 case ISD::SETEQ: X86CC = X86::COND_E; break;
1719 case ISD::SETGT: X86CC = X86::COND_G; break;
1720 case ISD::SETGE: X86CC = X86::COND_GE; break;
1721 case ISD::SETLT: X86CC = X86::COND_L; break;
1722 case ISD::SETLE: X86CC = X86::COND_LE; break;
1723 case ISD::SETNE: X86CC = X86::COND_NE; break;
1724 case ISD::SETULT: X86CC = X86::COND_B; break;
1725 case ISD::SETUGT: X86CC = X86::COND_A; break;
1726 case ISD::SETULE: X86CC = X86::COND_BE; break;
1727 case ISD::SETUGE: X86CC = X86::COND_AE; break;
Evan Chengd9558e02006-01-06 00:43:03 +00001728 }
1729 } else {
1730 // On a floating point condition, the flags are set as follows:
1731 // ZF PF CF op
1732 // 0 | 0 | 0 | X > Y
1733 // 0 | 0 | 1 | X < Y
1734 // 1 | 0 | 0 | X == Y
1735 // 1 | 1 | 1 | unordered
Chris Lattnerf9570512006-09-13 03:22:10 +00001736 bool Flip = false;
Evan Chengd9558e02006-01-06 00:43:03 +00001737 switch (SetCCOpcode) {
1738 default: break;
1739 case ISD::SETUEQ:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001740 case ISD::SETEQ: X86CC = X86::COND_E; break;
Evan Cheng5001ea12006-04-17 07:24:10 +00001741 case ISD::SETOLT: Flip = true; // Fallthrough
Evan Chengd9558e02006-01-06 00:43:03 +00001742 case ISD::SETOGT:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001743 case ISD::SETGT: X86CC = X86::COND_A; break;
Evan Cheng5001ea12006-04-17 07:24:10 +00001744 case ISD::SETOLE: Flip = true; // Fallthrough
Evan Chengd9558e02006-01-06 00:43:03 +00001745 case ISD::SETOGE:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001746 case ISD::SETGE: X86CC = X86::COND_AE; break;
Evan Cheng5001ea12006-04-17 07:24:10 +00001747 case ISD::SETUGT: Flip = true; // Fallthrough
Evan Chengd9558e02006-01-06 00:43:03 +00001748 case ISD::SETULT:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001749 case ISD::SETLT: X86CC = X86::COND_B; break;
Evan Cheng5001ea12006-04-17 07:24:10 +00001750 case ISD::SETUGE: Flip = true; // Fallthrough
Evan Chengd9558e02006-01-06 00:43:03 +00001751 case ISD::SETULE:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001752 case ISD::SETLE: X86CC = X86::COND_BE; break;
Evan Chengd9558e02006-01-06 00:43:03 +00001753 case ISD::SETONE:
Chris Lattner7fbe9722006-10-20 17:42:20 +00001754 case ISD::SETNE: X86CC = X86::COND_NE; break;
1755 case ISD::SETUO: X86CC = X86::COND_P; break;
1756 case ISD::SETO: X86CC = X86::COND_NP; break;
Evan Chengd9558e02006-01-06 00:43:03 +00001757 }
Chris Lattnerf9570512006-09-13 03:22:10 +00001758 if (Flip)
1759 std::swap(LHS, RHS);
Evan Chengd9558e02006-01-06 00:43:03 +00001760 }
Evan Cheng6dfa9992006-01-30 23:41:35 +00001761
Chris Lattner7fbe9722006-10-20 17:42:20 +00001762 return X86CC != X86::COND_INVALID;
Evan Chengd9558e02006-01-06 00:43:03 +00001763}
1764
Evan Cheng4a460802006-01-11 00:33:36 +00001765/// hasFPCMov - is there a floating point cmov for the specific X86 condition
1766/// code. Current x86 isa includes the following FP cmov instructions:
Evan Chengaaca22c2006-01-10 20:26:56 +00001767/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
Evan Cheng4a460802006-01-11 00:33:36 +00001768static bool hasFPCMov(unsigned X86CC) {
Evan Chengaaca22c2006-01-10 20:26:56 +00001769 switch (X86CC) {
1770 default:
1771 return false;
Chris Lattner7fbe9722006-10-20 17:42:20 +00001772 case X86::COND_B:
1773 case X86::COND_BE:
1774 case X86::COND_E:
1775 case X86::COND_P:
1776 case X86::COND_A:
1777 case X86::COND_AE:
1778 case X86::COND_NE:
1779 case X86::COND_NP:
Evan Chengaaca22c2006-01-10 20:26:56 +00001780 return true;
1781 }
1782}
1783
Evan Cheng5ced1d82006-04-06 23:23:56 +00001784/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
Evan Chengc5cdff22006-04-07 21:53:05 +00001785/// true if Op is undef or if its value falls within the specified range (L, H].
Evan Cheng5ced1d82006-04-06 23:23:56 +00001786static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1787 if (Op.getOpcode() == ISD::UNDEF)
1788 return true;
1789
1790 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
Evan Chengc5cdff22006-04-07 21:53:05 +00001791 return (Val >= Low && Val < Hi);
1792}
1793
1794/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1795/// true if Op is undef or if its value equal to the specified value.
1796static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1797 if (Op.getOpcode() == ISD::UNDEF)
1798 return true;
1799 return cast<ConstantSDNode>(Op)->getValue() == Val;
Evan Cheng5ced1d82006-04-06 23:23:56 +00001800}
1801
Evan Cheng0188ecb2006-03-22 18:59:22 +00001802/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1803/// specifies a shuffle of elements that is suitable for input to PSHUFD.
1804bool X86::isPSHUFDMask(SDNode *N) {
1805 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1806
Dan Gohman7f55fcb2007-08-02 21:17:01 +00001807 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
Evan Cheng0188ecb2006-03-22 18:59:22 +00001808 return false;
1809
1810 // Check if the value doesn't reference the second vector.
Evan Cheng506d3df2006-03-29 23:07:14 +00001811 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00001812 SDOperand Arg = N->getOperand(i);
1813 if (Arg.getOpcode() == ISD::UNDEF) continue;
1814 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Dan Gohman7f55fcb2007-08-02 21:17:01 +00001815 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
Evan Cheng506d3df2006-03-29 23:07:14 +00001816 return false;
1817 }
1818
1819 return true;
1820}
1821
1822/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Chengc21a0532006-04-05 01:47:37 +00001823/// specifies a shuffle of elements that is suitable for input to PSHUFHW.
Evan Cheng506d3df2006-03-29 23:07:14 +00001824bool X86::isPSHUFHWMask(SDNode *N) {
1825 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1826
1827 if (N->getNumOperands() != 8)
1828 return false;
1829
1830 // Lower quadword copied in order.
1831 for (unsigned i = 0; i != 4; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00001832 SDOperand Arg = N->getOperand(i);
1833 if (Arg.getOpcode() == ISD::UNDEF) continue;
1834 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1835 if (cast<ConstantSDNode>(Arg)->getValue() != i)
Evan Cheng506d3df2006-03-29 23:07:14 +00001836 return false;
1837 }
1838
1839 // Upper quadword shuffled.
1840 for (unsigned i = 4; i != 8; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00001841 SDOperand Arg = N->getOperand(i);
1842 if (Arg.getOpcode() == ISD::UNDEF) continue;
1843 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1844 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00001845 if (Val < 4 || Val > 7)
1846 return false;
1847 }
1848
1849 return true;
1850}
1851
1852/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Chengc21a0532006-04-05 01:47:37 +00001853/// specifies a shuffle of elements that is suitable for input to PSHUFLW.
Evan Cheng506d3df2006-03-29 23:07:14 +00001854bool X86::isPSHUFLWMask(SDNode *N) {
1855 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1856
1857 if (N->getNumOperands() != 8)
1858 return false;
1859
1860 // Upper quadword copied in order.
Evan Chengc5cdff22006-04-07 21:53:05 +00001861 for (unsigned i = 4; i != 8; ++i)
1862 if (!isUndefOrEqual(N->getOperand(i), i))
Evan Cheng506d3df2006-03-29 23:07:14 +00001863 return false;
Evan Cheng506d3df2006-03-29 23:07:14 +00001864
1865 // Lower quadword shuffled.
Evan Chengc5cdff22006-04-07 21:53:05 +00001866 for (unsigned i = 0; i != 4; ++i)
1867 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
Evan Cheng506d3df2006-03-29 23:07:14 +00001868 return false;
Evan Cheng0188ecb2006-03-22 18:59:22 +00001869
1870 return true;
1871}
1872
Evan Cheng14aed5e2006-03-24 01:18:28 +00001873/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1874/// specifies a shuffle of elements that is suitable for input to SHUFP*.
Chris Lattner5a88b832007-02-25 07:10:00 +00001875static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
Evan Cheng39623da2006-04-20 08:58:49 +00001876 if (NumElems != 2 && NumElems != 4) return false;
Evan Cheng14aed5e2006-03-24 01:18:28 +00001877
Evan Cheng39623da2006-04-20 08:58:49 +00001878 unsigned Half = NumElems / 2;
1879 for (unsigned i = 0; i < Half; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00001880 if (!isUndefOrInRange(Elems[i], 0, NumElems))
Evan Cheng39623da2006-04-20 08:58:49 +00001881 return false;
1882 for (unsigned i = Half; i < NumElems; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00001883 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
Evan Cheng39623da2006-04-20 08:58:49 +00001884 return false;
Evan Cheng14aed5e2006-03-24 01:18:28 +00001885
1886 return true;
1887}
1888
Evan Cheng39623da2006-04-20 08:58:49 +00001889bool X86::isSHUFPMask(SDNode *N) {
1890 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00001891 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00001892}
1893
Evan Cheng213d2cf2007-05-17 18:45:50 +00001894/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
Evan Cheng39623da2006-04-20 08:58:49 +00001895/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1896/// half elements to come from vector 1 (which would equal the dest.) and
1897/// the upper half to come from vector 2.
Chris Lattner5a88b832007-02-25 07:10:00 +00001898static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1899 if (NumOps != 2 && NumOps != 4) return false;
Evan Cheng39623da2006-04-20 08:58:49 +00001900
Chris Lattner5a88b832007-02-25 07:10:00 +00001901 unsigned Half = NumOps / 2;
Evan Cheng39623da2006-04-20 08:58:49 +00001902 for (unsigned i = 0; i < Half; ++i)
Chris Lattner5a88b832007-02-25 07:10:00 +00001903 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
Evan Cheng39623da2006-04-20 08:58:49 +00001904 return false;
Chris Lattner5a88b832007-02-25 07:10:00 +00001905 for (unsigned i = Half; i < NumOps; ++i)
1906 if (!isUndefOrInRange(Ops[i], 0, NumOps))
Evan Cheng39623da2006-04-20 08:58:49 +00001907 return false;
1908 return true;
1909}
1910
1911static bool isCommutedSHUFP(SDNode *N) {
1912 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00001913 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00001914}
1915
Evan Cheng2c0dbd02006-03-24 02:58:06 +00001916/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1917/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1918bool X86::isMOVHLPSMask(SDNode *N) {
1919 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1920
Evan Cheng2064a2b2006-03-28 06:50:32 +00001921 if (N->getNumOperands() != 4)
Evan Cheng2c0dbd02006-03-24 02:58:06 +00001922 return false;
1923
Evan Cheng2064a2b2006-03-28 06:50:32 +00001924 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
Evan Chengc5cdff22006-04-07 21:53:05 +00001925 return isUndefOrEqual(N->getOperand(0), 6) &&
1926 isUndefOrEqual(N->getOperand(1), 7) &&
1927 isUndefOrEqual(N->getOperand(2), 2) &&
1928 isUndefOrEqual(N->getOperand(3), 3);
Evan Cheng2064a2b2006-03-28 06:50:32 +00001929}
1930
Evan Cheng6e56e2c2006-11-07 22:14:24 +00001931/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1932/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1933/// <2, 3, 2, 3>
1934bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1935 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1936
1937 if (N->getNumOperands() != 4)
1938 return false;
1939
1940 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1941 return isUndefOrEqual(N->getOperand(0), 2) &&
1942 isUndefOrEqual(N->getOperand(1), 3) &&
1943 isUndefOrEqual(N->getOperand(2), 2) &&
1944 isUndefOrEqual(N->getOperand(3), 3);
1945}
1946
Evan Cheng5ced1d82006-04-06 23:23:56 +00001947/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1948/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1949bool X86::isMOVLPMask(SDNode *N) {
1950 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1951
1952 unsigned NumElems = N->getNumOperands();
1953 if (NumElems != 2 && NumElems != 4)
1954 return false;
1955
Evan Chengc5cdff22006-04-07 21:53:05 +00001956 for (unsigned i = 0; i < NumElems/2; ++i)
1957 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1958 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00001959
Evan Chengc5cdff22006-04-07 21:53:05 +00001960 for (unsigned i = NumElems/2; i < NumElems; ++i)
1961 if (!isUndefOrEqual(N->getOperand(i), i))
1962 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00001963
1964 return true;
1965}
1966
1967/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
Evan Cheng533a0aa2006-04-19 20:35:22 +00001968/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1969/// and MOVLHPS.
Evan Cheng5ced1d82006-04-06 23:23:56 +00001970bool X86::isMOVHPMask(SDNode *N) {
1971 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1972
1973 unsigned NumElems = N->getNumOperands();
1974 if (NumElems != 2 && NumElems != 4)
1975 return false;
1976
Evan Chengc5cdff22006-04-07 21:53:05 +00001977 for (unsigned i = 0; i < NumElems/2; ++i)
1978 if (!isUndefOrEqual(N->getOperand(i), i))
1979 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00001980
1981 for (unsigned i = 0; i < NumElems/2; ++i) {
1982 SDOperand Arg = N->getOperand(i + NumElems/2);
Evan Chengc5cdff22006-04-07 21:53:05 +00001983 if (!isUndefOrEqual(Arg, i + NumElems))
1984 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00001985 }
1986
1987 return true;
1988}
1989
Evan Cheng0038e592006-03-28 00:39:58 +00001990/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1991/// specifies a shuffle of elements that is suitable for input to UNPCKL.
Chris Lattner5a88b832007-02-25 07:10:00 +00001992bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1993 bool V2IsSplat = false) {
1994 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
Evan Cheng0038e592006-03-28 00:39:58 +00001995 return false;
1996
Chris Lattner5a88b832007-02-25 07:10:00 +00001997 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1998 SDOperand BitI = Elts[i];
1999 SDOperand BitI1 = Elts[i+1];
Evan Chengc5cdff22006-04-07 21:53:05 +00002000 if (!isUndefOrEqual(BitI, j))
2001 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002002 if (V2IsSplat) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002003 if (isUndefOrEqual(BitI1, NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002004 return false;
2005 } else {
Chris Lattner5a88b832007-02-25 07:10:00 +00002006 if (!isUndefOrEqual(BitI1, j + NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002007 return false;
2008 }
Evan Cheng0038e592006-03-28 00:39:58 +00002009 }
2010
2011 return true;
2012}
2013
Evan Cheng39623da2006-04-20 08:58:49 +00002014bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2015 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002016 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
Evan Cheng39623da2006-04-20 08:58:49 +00002017}
2018
Evan Cheng4fcb9222006-03-28 02:43:26 +00002019/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2020/// specifies a shuffle of elements that is suitable for input to UNPCKH.
Chris Lattner5a88b832007-02-25 07:10:00 +00002021bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
2022 bool V2IsSplat = false) {
2023 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
Evan Cheng4fcb9222006-03-28 02:43:26 +00002024 return false;
2025
Chris Lattner5a88b832007-02-25 07:10:00 +00002026 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2027 SDOperand BitI = Elts[i];
2028 SDOperand BitI1 = Elts[i+1];
2029 if (!isUndefOrEqual(BitI, j + NumElts/2))
Evan Chengc5cdff22006-04-07 21:53:05 +00002030 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002031 if (V2IsSplat) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002032 if (isUndefOrEqual(BitI1, NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002033 return false;
2034 } else {
Chris Lattner5a88b832007-02-25 07:10:00 +00002035 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
Evan Cheng39623da2006-04-20 08:58:49 +00002036 return false;
2037 }
Evan Cheng4fcb9222006-03-28 02:43:26 +00002038 }
2039
2040 return true;
2041}
2042
Evan Cheng39623da2006-04-20 08:58:49 +00002043bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2044 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002045 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
Evan Cheng39623da2006-04-20 08:58:49 +00002046}
2047
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002048/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2049/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2050/// <0, 0, 1, 1>
2051bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2052 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2053
2054 unsigned NumElems = N->getNumOperands();
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002055 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002056 return false;
2057
2058 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2059 SDOperand BitI = N->getOperand(i);
2060 SDOperand BitI1 = N->getOperand(i+1);
2061
Evan Chengc5cdff22006-04-07 21:53:05 +00002062 if (!isUndefOrEqual(BitI, j))
2063 return false;
2064 if (!isUndefOrEqual(BitI1, j))
2065 return false;
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002066 }
2067
2068 return true;
2069}
2070
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002071/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2072/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2073/// <2, 2, 3, 3>
2074bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2075 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2076
2077 unsigned NumElems = N->getNumOperands();
2078 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2079 return false;
2080
2081 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2082 SDOperand BitI = N->getOperand(i);
2083 SDOperand BitI1 = N->getOperand(i + 1);
2084
2085 if (!isUndefOrEqual(BitI, j))
2086 return false;
2087 if (!isUndefOrEqual(BitI1, j))
2088 return false;
2089 }
2090
2091 return true;
2092}
2093
Evan Cheng017dcc62006-04-21 01:05:10 +00002094/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2095/// specifies a shuffle of elements that is suitable for input to MOVSS,
2096/// MOVSD, and MOVD, i.e. setting the lowest element.
Chris Lattner5a88b832007-02-25 07:10:00 +00002097static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
Evan Cheng10762102007-12-06 22:14:22 +00002098 if (NumElts != 2 && NumElts != 4)
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002099 return false;
2100
Chris Lattner5a88b832007-02-25 07:10:00 +00002101 if (!isUndefOrEqual(Elts[0], NumElts))
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002102 return false;
2103
Chris Lattner5a88b832007-02-25 07:10:00 +00002104 for (unsigned i = 1; i < NumElts; ++i) {
2105 if (!isUndefOrEqual(Elts[i], i))
Evan Chengd6d1cbd2006-04-11 00:19:04 +00002106 return false;
2107 }
2108
2109 return true;
2110}
Evan Cheng1d5a8cc2006-04-05 07:20:06 +00002111
Evan Cheng017dcc62006-04-21 01:05:10 +00002112bool X86::isMOVLMask(SDNode *N) {
Evan Cheng39623da2006-04-20 08:58:49 +00002113 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002114 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
Evan Cheng39623da2006-04-20 08:58:49 +00002115}
2116
Evan Cheng017dcc62006-04-21 01:05:10 +00002117/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2118/// of what x86 movss want. X86 movs requires the lowest element to be lowest
Evan Cheng39623da2006-04-20 08:58:49 +00002119/// element of vector 2 and the other elements to come from vector 1 in order.
Chris Lattner5a88b832007-02-25 07:10:00 +00002120static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2121 bool V2IsSplat = false,
Evan Cheng8cf723d2006-09-08 01:50:06 +00002122 bool V2IsUndef = false) {
Chris Lattner5a88b832007-02-25 07:10:00 +00002123 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
Evan Cheng39623da2006-04-20 08:58:49 +00002124 return false;
2125
2126 if (!isUndefOrEqual(Ops[0], 0))
2127 return false;
2128
Chris Lattner5a88b832007-02-25 07:10:00 +00002129 for (unsigned i = 1; i < NumOps; ++i) {
Evan Cheng39623da2006-04-20 08:58:49 +00002130 SDOperand Arg = Ops[i];
Chris Lattner5a88b832007-02-25 07:10:00 +00002131 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2132 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2133 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
Evan Cheng8cf723d2006-09-08 01:50:06 +00002134 return false;
Evan Cheng39623da2006-04-20 08:58:49 +00002135 }
2136
2137 return true;
2138}
2139
Evan Cheng8cf723d2006-09-08 01:50:06 +00002140static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2141 bool V2IsUndef = false) {
Evan Cheng39623da2006-04-20 08:58:49 +00002142 assert(N->getOpcode() == ISD::BUILD_VECTOR);
Chris Lattner5a88b832007-02-25 07:10:00 +00002143 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2144 V2IsSplat, V2IsUndef);
Evan Cheng39623da2006-04-20 08:58:49 +00002145}
2146
Evan Chengd9539472006-04-14 21:59:03 +00002147/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2148/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2149bool X86::isMOVSHDUPMask(SDNode *N) {
2150 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2151
2152 if (N->getNumOperands() != 4)
2153 return false;
2154
2155 // Expect 1, 1, 3, 3
2156 for (unsigned i = 0; i < 2; ++i) {
2157 SDOperand Arg = N->getOperand(i);
2158 if (Arg.getOpcode() == ISD::UNDEF) continue;
2159 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2160 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2161 if (Val != 1) return false;
2162 }
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002163
2164 bool HasHi = false;
Evan Chengd9539472006-04-14 21:59:03 +00002165 for (unsigned i = 2; i < 4; ++i) {
2166 SDOperand Arg = N->getOperand(i);
2167 if (Arg.getOpcode() == ISD::UNDEF) continue;
2168 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2169 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2170 if (Val != 3) return false;
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002171 HasHi = true;
Evan Chengd9539472006-04-14 21:59:03 +00002172 }
Evan Cheng39fc1452006-04-15 03:13:24 +00002173
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002174 // Don't use movshdup if it can be done with a shufps.
2175 return HasHi;
Evan Chengd9539472006-04-14 21:59:03 +00002176}
2177
2178/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2179/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2180bool X86::isMOVSLDUPMask(SDNode *N) {
2181 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2182
2183 if (N->getNumOperands() != 4)
2184 return false;
2185
2186 // Expect 0, 0, 2, 2
2187 for (unsigned i = 0; i < 2; ++i) {
2188 SDOperand Arg = N->getOperand(i);
2189 if (Arg.getOpcode() == ISD::UNDEF) continue;
2190 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2191 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2192 if (Val != 0) return false;
2193 }
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002194
2195 bool HasHi = false;
Evan Chengd9539472006-04-14 21:59:03 +00002196 for (unsigned i = 2; i < 4; ++i) {
2197 SDOperand Arg = N->getOperand(i);
2198 if (Arg.getOpcode() == ISD::UNDEF) continue;
2199 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2200 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2201 if (Val != 2) return false;
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002202 HasHi = true;
Evan Chengd9539472006-04-14 21:59:03 +00002203 }
Evan Cheng39fc1452006-04-15 03:13:24 +00002204
Evan Cheng57ebe9f2006-04-15 05:37:34 +00002205 // Don't use movshdup if it can be done with a shufps.
2206 return HasHi;
Evan Chengd9539472006-04-14 21:59:03 +00002207}
2208
Evan Cheng49892af2007-06-19 00:02:56 +00002209/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2210/// specifies a identity operation on the LHS or RHS.
2211static bool isIdentityMask(SDNode *N, bool RHS = false) {
2212 unsigned NumElems = N->getNumOperands();
2213 for (unsigned i = 0; i < NumElems; ++i)
2214 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2215 return false;
2216 return true;
2217}
2218
Evan Chengb9df0ca2006-03-22 02:53:00 +00002219/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2220/// a splat of a single element.
Evan Chengc575ca22006-04-17 20:43:08 +00002221static bool isSplatMask(SDNode *N) {
Evan Chengb9df0ca2006-03-22 02:53:00 +00002222 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2223
Evan Chengb9df0ca2006-03-22 02:53:00 +00002224 // This is a splat operation if each element of the permute is the same, and
2225 // if the value doesn't reference the second vector.
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002226 unsigned NumElems = N->getNumOperands();
2227 SDOperand ElementBase;
2228 unsigned i = 0;
2229 for (; i != NumElems; ++i) {
2230 SDOperand Elt = N->getOperand(i);
Reid Spencer3ed469c2006-11-02 20:25:50 +00002231 if (isa<ConstantSDNode>(Elt)) {
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002232 ElementBase = Elt;
2233 break;
2234 }
2235 }
2236
2237 if (!ElementBase.Val)
2238 return false;
2239
2240 for (; i != NumElems; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002241 SDOperand Arg = N->getOperand(i);
2242 if (Arg.getOpcode() == ISD::UNDEF) continue;
2243 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002244 if (Arg != ElementBase) return false;
Evan Chengb9df0ca2006-03-22 02:53:00 +00002245 }
2246
2247 // Make sure it is a splat of the first vector operand.
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002248 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
Evan Chengb9df0ca2006-03-22 02:53:00 +00002249}
2250
Evan Chengc575ca22006-04-17 20:43:08 +00002251/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2252/// a splat of a single element and it's a 2 or 4 element mask.
2253bool X86::isSplatMask(SDNode *N) {
2254 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2255
Evan Cheng94fe5eb2006-04-19 23:28:59 +00002256 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
Evan Chengc575ca22006-04-17 20:43:08 +00002257 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2258 return false;
2259 return ::isSplatMask(N);
2260}
2261
Evan Chengf686d9b2006-10-27 21:08:32 +00002262/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2263/// specifies a splat of zero element.
2264bool X86::isSplatLoMask(SDNode *N) {
2265 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2266
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002267 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
Evan Chengf686d9b2006-10-27 21:08:32 +00002268 if (!isUndefOrEqual(N->getOperand(i), 0))
2269 return false;
2270 return true;
2271}
2272
Evan Cheng63d33002006-03-22 08:01:21 +00002273/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2274/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2275/// instructions.
2276unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
Evan Chengb9df0ca2006-03-22 02:53:00 +00002277 unsigned NumOperands = N->getNumOperands();
2278 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2279 unsigned Mask = 0;
Evan Cheng36b27f32006-03-28 23:41:33 +00002280 for (unsigned i = 0; i < NumOperands; ++i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002281 unsigned Val = 0;
2282 SDOperand Arg = N->getOperand(NumOperands-i-1);
2283 if (Arg.getOpcode() != ISD::UNDEF)
2284 Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng14aed5e2006-03-24 01:18:28 +00002285 if (Val >= NumOperands) Val -= NumOperands;
Evan Cheng63d33002006-03-22 08:01:21 +00002286 Mask |= Val;
Evan Cheng36b27f32006-03-28 23:41:33 +00002287 if (i != NumOperands - 1)
2288 Mask <<= Shift;
2289 }
Evan Cheng63d33002006-03-22 08:01:21 +00002290
2291 return Mask;
2292}
2293
Evan Cheng506d3df2006-03-29 23:07:14 +00002294/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2295/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2296/// instructions.
2297unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2298 unsigned Mask = 0;
2299 // 8 nodes, but we only care about the last 4.
2300 for (unsigned i = 7; i >= 4; --i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002301 unsigned Val = 0;
2302 SDOperand Arg = N->getOperand(i);
2303 if (Arg.getOpcode() != ISD::UNDEF)
2304 Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00002305 Mask |= (Val - 4);
2306 if (i != 4)
2307 Mask <<= 2;
2308 }
2309
2310 return Mask;
2311}
2312
2313/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2314/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2315/// instructions.
2316unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2317 unsigned Mask = 0;
2318 // 8 nodes, but we only care about the first 4.
2319 for (int i = 3; i >= 0; --i) {
Evan Chengef698ca2006-03-31 00:30:29 +00002320 unsigned Val = 0;
2321 SDOperand Arg = N->getOperand(i);
2322 if (Arg.getOpcode() != ISD::UNDEF)
2323 Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng506d3df2006-03-29 23:07:14 +00002324 Mask |= Val;
2325 if (i != 0)
2326 Mask <<= 2;
2327 }
2328
2329 return Mask;
2330}
2331
Evan Chengc21a0532006-04-05 01:47:37 +00002332/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2333/// specifies a 8 element shuffle that can be broken into a pair of
2334/// PSHUFHW and PSHUFLW.
2335static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2336 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2337
2338 if (N->getNumOperands() != 8)
2339 return false;
2340
2341 // Lower quadword shuffled.
2342 for (unsigned i = 0; i != 4; ++i) {
2343 SDOperand Arg = N->getOperand(i);
2344 if (Arg.getOpcode() == ISD::UNDEF) continue;
2345 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2346 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
Evan Cheng14b32e12007-12-11 01:46:18 +00002347 if (Val >= 4)
Evan Chengc21a0532006-04-05 01:47:37 +00002348 return false;
2349 }
2350
2351 // Upper quadword shuffled.
2352 for (unsigned i = 4; i != 8; ++i) {
2353 SDOperand Arg = N->getOperand(i);
2354 if (Arg.getOpcode() == ISD::UNDEF) continue;
2355 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2356 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2357 if (Val < 4 || Val > 7)
2358 return false;
2359 }
2360
2361 return true;
2362}
2363
Chris Lattner8a594482007-11-25 00:24:49 +00002364/// CommuteVectorShuffle - Swap vector_shuffle operands as well as
Evan Cheng5ced1d82006-04-06 23:23:56 +00002365/// values in ther permute mask.
Evan Cheng9eca5e82006-10-25 21:49:50 +00002366static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2367 SDOperand &V2, SDOperand &Mask,
2368 SelectionDAG &DAG) {
Evan Cheng5ced1d82006-04-06 23:23:56 +00002369 MVT::ValueType VT = Op.getValueType();
2370 MVT::ValueType MaskVT = Mask.getValueType();
Dan Gohman51eaa862007-06-14 22:58:02 +00002371 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002372 unsigned NumElems = Mask.getNumOperands();
Chris Lattner5a88b832007-02-25 07:10:00 +00002373 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002374
2375 for (unsigned i = 0; i != NumElems; ++i) {
2376 SDOperand Arg = Mask.getOperand(i);
Evan Cheng80d428c2006-04-19 22:48:17 +00002377 if (Arg.getOpcode() == ISD::UNDEF) {
2378 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2379 continue;
2380 }
Evan Cheng5ced1d82006-04-06 23:23:56 +00002381 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2382 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2383 if (Val < NumElems)
2384 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2385 else
2386 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2387 }
2388
Evan Cheng9eca5e82006-10-25 21:49:50 +00002389 std::swap(V1, V2);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002390 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
Evan Cheng9eca5e82006-10-25 21:49:50 +00002391 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002392}
2393
Evan Cheng779ccea2007-12-07 21:30:01 +00002394/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2395/// the two vector operands have swapped position.
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002396static
2397SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2398 MVT::ValueType MaskVT = Mask.getValueType();
2399 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2400 unsigned NumElems = Mask.getNumOperands();
2401 SmallVector<SDOperand, 8> MaskVec;
2402 for (unsigned i = 0; i != NumElems; ++i) {
2403 SDOperand Arg = Mask.getOperand(i);
2404 if (Arg.getOpcode() == ISD::UNDEF) {
2405 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2406 continue;
2407 }
2408 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2409 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2410 if (Val < NumElems)
2411 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2412 else
2413 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2414 }
2415 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2416}
2417
2418
Evan Cheng533a0aa2006-04-19 20:35:22 +00002419/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2420/// match movhlps. The lower half elements should come from upper half of
2421/// V1 (and in order), and the upper half elements should come from the upper
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002422/// half of V2 (and in order).
Evan Cheng533a0aa2006-04-19 20:35:22 +00002423static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2424 unsigned NumElems = Mask->getNumOperands();
2425 if (NumElems != 4)
2426 return false;
2427 for (unsigned i = 0, e = 2; i != e; ++i)
2428 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2429 return false;
2430 for (unsigned i = 2; i != 4; ++i)
2431 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2432 return false;
2433 return true;
2434}
2435
Evan Cheng5ced1d82006-04-06 23:23:56 +00002436/// isScalarLoadToVector - Returns true if the node is a scalar load that
2437/// is promoted to a vector.
Evan Cheng533a0aa2006-04-19 20:35:22 +00002438static inline bool isScalarLoadToVector(SDNode *N) {
2439 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2440 N = N->getOperand(0).Val;
Evan Cheng466685d2006-10-09 20:57:25 +00002441 return ISD::isNON_EXTLoad(N);
Evan Cheng5ced1d82006-04-06 23:23:56 +00002442 }
2443 return false;
2444}
2445
Evan Cheng533a0aa2006-04-19 20:35:22 +00002446/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2447/// match movlp{s|d}. The lower half elements should come from lower half of
2448/// V1 (and in order), and the upper half elements should come from the upper
2449/// half of V2 (and in order). And since V1 will become the source of the
2450/// MOVLP, it must be either a vector load or a scalar load to vector.
Evan Cheng23425f52006-10-09 21:39:25 +00002451static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
Evan Cheng466685d2006-10-09 20:57:25 +00002452 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
Evan Cheng533a0aa2006-04-19 20:35:22 +00002453 return false;
Evan Cheng23425f52006-10-09 21:39:25 +00002454 // Is V2 is a vector load, don't do this transformation. We will try to use
2455 // load folding shufps op.
2456 if (ISD::isNON_EXTLoad(V2))
2457 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002458
Evan Cheng533a0aa2006-04-19 20:35:22 +00002459 unsigned NumElems = Mask->getNumOperands();
2460 if (NumElems != 2 && NumElems != 4)
2461 return false;
2462 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2463 if (!isUndefOrEqual(Mask->getOperand(i), i))
2464 return false;
2465 for (unsigned i = NumElems/2; i != NumElems; ++i)
2466 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2467 return false;
2468 return true;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002469}
2470
Evan Cheng39623da2006-04-20 08:58:49 +00002471/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2472/// all the same.
2473static bool isSplatVector(SDNode *N) {
2474 if (N->getOpcode() != ISD::BUILD_VECTOR)
2475 return false;
Evan Cheng5ced1d82006-04-06 23:23:56 +00002476
Evan Cheng39623da2006-04-20 08:58:49 +00002477 SDOperand SplatValue = N->getOperand(0);
2478 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2479 if (N->getOperand(i) != SplatValue)
Evan Cheng5ced1d82006-04-06 23:23:56 +00002480 return false;
2481 return true;
2482}
2483
Evan Cheng8cf723d2006-09-08 01:50:06 +00002484/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2485/// to an undef.
2486static bool isUndefShuffle(SDNode *N) {
Evan Cheng213d2cf2007-05-17 18:45:50 +00002487 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
Evan Cheng8cf723d2006-09-08 01:50:06 +00002488 return false;
2489
2490 SDOperand V1 = N->getOperand(0);
2491 SDOperand V2 = N->getOperand(1);
2492 SDOperand Mask = N->getOperand(2);
2493 unsigned NumElems = Mask.getNumOperands();
2494 for (unsigned i = 0; i != NumElems; ++i) {
2495 SDOperand Arg = Mask.getOperand(i);
2496 if (Arg.getOpcode() != ISD::UNDEF) {
2497 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2498 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2499 return false;
2500 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2501 return false;
2502 }
2503 }
2504 return true;
2505}
2506
Evan Cheng213d2cf2007-05-17 18:45:50 +00002507/// isZeroNode - Returns true if Elt is a constant zero or a floating point
2508/// constant +0.0.
2509static inline bool isZeroNode(SDOperand Elt) {
2510 return ((isa<ConstantSDNode>(Elt) &&
2511 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2512 (isa<ConstantFPSDNode>(Elt) &&
Dale Johanneseneaf08942007-08-31 04:03:46 +00002513 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
Evan Cheng213d2cf2007-05-17 18:45:50 +00002514}
2515
2516/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2517/// to an zero vector.
2518static bool isZeroShuffle(SDNode *N) {
2519 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2520 return false;
2521
2522 SDOperand V1 = N->getOperand(0);
2523 SDOperand V2 = N->getOperand(1);
2524 SDOperand Mask = N->getOperand(2);
2525 unsigned NumElems = Mask.getNumOperands();
2526 for (unsigned i = 0; i != NumElems; ++i) {
2527 SDOperand Arg = Mask.getOperand(i);
Chris Lattner8a594482007-11-25 00:24:49 +00002528 if (Arg.getOpcode() == ISD::UNDEF)
2529 continue;
2530
2531 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2532 if (Idx < NumElems) {
2533 unsigned Opc = V1.Val->getOpcode();
2534 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2535 continue;
2536 if (Opc != ISD::BUILD_VECTOR ||
2537 !isZeroNode(V1.Val->getOperand(Idx)))
2538 return false;
2539 } else if (Idx >= NumElems) {
2540 unsigned Opc = V2.Val->getOpcode();
2541 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2542 continue;
2543 if (Opc != ISD::BUILD_VECTOR ||
2544 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2545 return false;
Evan Cheng213d2cf2007-05-17 18:45:50 +00002546 }
2547 }
2548 return true;
2549}
2550
2551/// getZeroVector - Returns a vector of specified type with all zero elements.
2552///
2553static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2554 assert(MVT::isVector(VT) && "Expected a vector type");
Chris Lattner8a594482007-11-25 00:24:49 +00002555
2556 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2557 // type. This ensures they get CSE'd.
2558 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2559 SDOperand Vec;
2560 if (MVT::getSizeInBits(VT) == 64) // MMX
2561 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2562 else // SSE
2563 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2564 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
Evan Cheng213d2cf2007-05-17 18:45:50 +00002565}
2566
Chris Lattner8a594482007-11-25 00:24:49 +00002567/// getOnesVector - Returns a vector of specified type with all bits set.
2568///
2569static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) {
2570 assert(MVT::isVector(VT) && "Expected a vector type");
2571
2572 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2573 // type. This ensures they get CSE'd.
2574 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2575 SDOperand Vec;
2576 if (MVT::getSizeInBits(VT) == 64) // MMX
2577 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2578 else // SSE
2579 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2580 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2581}
2582
2583
Evan Cheng39623da2006-04-20 08:58:49 +00002584/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2585/// that point to V2 points to its first element.
2586static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2587 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2588
2589 bool Changed = false;
Chris Lattner5a88b832007-02-25 07:10:00 +00002590 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002591 unsigned NumElems = Mask.getNumOperands();
2592 for (unsigned i = 0; i != NumElems; ++i) {
2593 SDOperand Arg = Mask.getOperand(i);
2594 if (Arg.getOpcode() != ISD::UNDEF) {
2595 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2596 if (Val > NumElems) {
2597 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2598 Changed = true;
2599 }
2600 }
2601 MaskVec.push_back(Arg);
2602 }
2603
2604 if (Changed)
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002605 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2606 &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002607 return Mask;
2608}
2609
Evan Cheng017dcc62006-04-21 01:05:10 +00002610/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2611/// operation of specified width.
2612static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
Evan Cheng39623da2006-04-20 08:58:49 +00002613 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002614 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
Evan Cheng39623da2006-04-20 08:58:49 +00002615
Chris Lattner5a88b832007-02-25 07:10:00 +00002616 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002617 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2618 for (unsigned i = 1; i != NumElems; ++i)
2619 MaskVec.push_back(DAG.getConstant(i, BaseVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002620 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002621}
2622
Evan Chengc575ca22006-04-17 20:43:08 +00002623/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2624/// of specified width.
2625static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2626 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002627 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
Chris Lattner5a88b832007-02-25 07:10:00 +00002628 SmallVector<SDOperand, 8> MaskVec;
Evan Chengc575ca22006-04-17 20:43:08 +00002629 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2630 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2631 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2632 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002633 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Chengc575ca22006-04-17 20:43:08 +00002634}
2635
Evan Cheng39623da2006-04-20 08:58:49 +00002636/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2637/// of specified width.
2638static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2639 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002640 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
Evan Cheng39623da2006-04-20 08:58:49 +00002641 unsigned Half = NumElems/2;
Chris Lattner5a88b832007-02-25 07:10:00 +00002642 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng39623da2006-04-20 08:58:49 +00002643 for (unsigned i = 0; i != Half; ++i) {
2644 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2645 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2646 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002647 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
Evan Cheng39623da2006-04-20 08:58:49 +00002648}
2649
Evan Chengc575ca22006-04-17 20:43:08 +00002650/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2651///
2652static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2653 SDOperand V1 = Op.getOperand(0);
Evan Cheng017dcc62006-04-21 01:05:10 +00002654 SDOperand Mask = Op.getOperand(2);
Evan Chengc575ca22006-04-17 20:43:08 +00002655 MVT::ValueType VT = Op.getValueType();
Evan Cheng017dcc62006-04-21 01:05:10 +00002656 unsigned NumElems = Mask.getNumOperands();
2657 Mask = getUnpacklMask(NumElems, DAG);
Evan Chengc575ca22006-04-17 20:43:08 +00002658 while (NumElems != 4) {
Evan Cheng017dcc62006-04-21 01:05:10 +00002659 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
Evan Chengc575ca22006-04-17 20:43:08 +00002660 NumElems >>= 1;
2661 }
2662 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2663
Chris Lattner8a594482007-11-25 00:24:49 +00002664 Mask = getZeroVector(MVT::v4i32, DAG);
Evan Chengc575ca22006-04-17 20:43:08 +00002665 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
Evan Cheng017dcc62006-04-21 01:05:10 +00002666 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
Evan Chengc575ca22006-04-17 20:43:08 +00002667 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2668}
2669
Evan Chengba05f722006-04-21 23:03:30 +00002670/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
Chris Lattner8a594482007-11-25 00:24:49 +00002671/// vector of zero or undef vector. This produces a shuffle where the low
2672/// element of V2 is swizzled into the zero/undef vector, landing at element
2673/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
Evan Chengba05f722006-04-21 23:03:30 +00002674static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
Evan Cheng017dcc62006-04-21 01:05:10 +00002675 unsigned NumElems, unsigned Idx,
Evan Chengba05f722006-04-21 23:03:30 +00002676 bool isZero, SelectionDAG &DAG) {
2677 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
Evan Cheng017dcc62006-04-21 01:05:10 +00002678 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002679 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
Chris Lattner8a594482007-11-25 00:24:49 +00002680 SmallVector<SDOperand, 16> MaskVec;
2681 for (unsigned i = 0; i != NumElems; ++i)
2682 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2683 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2684 else
2685 MaskVec.push_back(DAG.getConstant(i, EVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002686 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2687 &MaskVec[0], MaskVec.size());
Evan Chengba05f722006-04-21 23:03:30 +00002688 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
Evan Cheng017dcc62006-04-21 01:05:10 +00002689}
2690
Evan Chengc78d3b42006-04-24 18:01:45 +00002691/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2692///
2693static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2694 unsigned NumNonZero, unsigned NumZero,
Evan Cheng25ab6902006-09-08 06:48:29 +00002695 SelectionDAG &DAG, TargetLowering &TLI) {
Evan Chengc78d3b42006-04-24 18:01:45 +00002696 if (NumNonZero > 8)
2697 return SDOperand();
2698
2699 SDOperand V(0, 0);
2700 bool First = true;
2701 for (unsigned i = 0; i < 16; ++i) {
2702 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2703 if (ThisIsNonZero && First) {
2704 if (NumZero)
2705 V = getZeroVector(MVT::v8i16, DAG);
2706 else
2707 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2708 First = false;
2709 }
2710
2711 if ((i & 1) != 0) {
2712 SDOperand ThisElt(0, 0), LastElt(0, 0);
2713 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2714 if (LastIsNonZero) {
2715 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2716 }
2717 if (ThisIsNonZero) {
2718 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2719 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2720 ThisElt, DAG.getConstant(8, MVT::i8));
2721 if (LastIsNonZero)
2722 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2723 } else
2724 ThisElt = LastElt;
2725
2726 if (ThisElt.Val)
2727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
Evan Cheng25ab6902006-09-08 06:48:29 +00002728 DAG.getConstant(i/2, TLI.getPointerTy()));
Evan Chengc78d3b42006-04-24 18:01:45 +00002729 }
2730 }
2731
2732 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2733}
2734
Bill Wendlinga348c562007-03-22 18:42:45 +00002735/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
Evan Chengc78d3b42006-04-24 18:01:45 +00002736///
2737static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2738 unsigned NumNonZero, unsigned NumZero,
Evan Cheng25ab6902006-09-08 06:48:29 +00002739 SelectionDAG &DAG, TargetLowering &TLI) {
Evan Chengc78d3b42006-04-24 18:01:45 +00002740 if (NumNonZero > 4)
2741 return SDOperand();
2742
2743 SDOperand V(0, 0);
2744 bool First = true;
2745 for (unsigned i = 0; i < 8; ++i) {
2746 bool isNonZero = (NonZeros & (1 << i)) != 0;
2747 if (isNonZero) {
2748 if (First) {
2749 if (NumZero)
2750 V = getZeroVector(MVT::v8i16, DAG);
2751 else
2752 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2753 First = false;
2754 }
2755 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
Evan Cheng25ab6902006-09-08 06:48:29 +00002756 DAG.getConstant(i, TLI.getPointerTy()));
Evan Chengc78d3b42006-04-24 18:01:45 +00002757 }
2758 }
2759
2760 return V;
2761}
2762
Evan Cheng0db9fe62006-04-25 20:13:52 +00002763SDOperand
2764X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner8a594482007-11-25 00:24:49 +00002765 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
2766 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
2767 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
2768 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
2769 // eliminated on x86-32 hosts.
2770 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
2771 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00002772
Chris Lattner8a594482007-11-25 00:24:49 +00002773 if (ISD::isBuildVectorAllOnes(Op.Val))
2774 return getOnesVector(Op.getValueType(), DAG);
2775 return getZeroVector(Op.getValueType(), DAG);
2776 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00002777
2778 MVT::ValueType VT = Op.getValueType();
Dan Gohman51eaa862007-06-14 22:58:02 +00002779 MVT::ValueType EVT = MVT::getVectorElementType(VT);
Evan Cheng0db9fe62006-04-25 20:13:52 +00002780 unsigned EVTBits = MVT::getSizeInBits(EVT);
2781
2782 unsigned NumElems = Op.getNumOperands();
2783 unsigned NumZero = 0;
2784 unsigned NumNonZero = 0;
2785 unsigned NonZeros = 0;
Evan Chengdb2d5242007-12-12 06:45:40 +00002786 bool HasNonImms = false;
Evan Cheng14b32e12007-12-11 01:46:18 +00002787 SmallSet<SDOperand, 8> Values;
Evan Cheng0db9fe62006-04-25 20:13:52 +00002788 for (unsigned i = 0; i < NumElems; ++i) {
2789 SDOperand Elt = Op.getOperand(i);
Evan Chengdb2d5242007-12-12 06:45:40 +00002790 if (Elt.getOpcode() == ISD::UNDEF)
2791 continue;
2792 Values.insert(Elt);
2793 if (Elt.getOpcode() != ISD::Constant &&
2794 Elt.getOpcode() != ISD::ConstantFP)
2795 HasNonImms = true;
2796 if (isZeroNode(Elt))
2797 NumZero++;
2798 else {
2799 NonZeros |= (1 << i);
2800 NumNonZero++;
Evan Cheng0db9fe62006-04-25 20:13:52 +00002801 }
2802 }
2803
Dan Gohman7f321562007-06-25 16:23:39 +00002804 if (NumNonZero == 0) {
Chris Lattner8a594482007-11-25 00:24:49 +00002805 // All undef vector. Return an UNDEF. All zero vectors were handled above.
2806 return DAG.getNode(ISD::UNDEF, VT);
Dan Gohman7f321562007-06-25 16:23:39 +00002807 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00002808
2809 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2810 if (Values.size() == 1)
2811 return SDOperand();
2812
2813 // Special case for single non-zero element.
Evan Chengdb2d5242007-12-12 06:45:40 +00002814 if (NumNonZero == 1 && NumElems <= 4) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00002815 unsigned Idx = CountTrailingZeros_32(NonZeros);
2816 SDOperand Item = Op.getOperand(Idx);
2817 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2818 if (Idx == 0)
2819 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2820 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2821 NumZero > 0, DAG);
Evan Chengdb2d5242007-12-12 06:45:40 +00002822 else if (!HasNonImms) // Otherwise, it's better to do a constpool load.
2823 return SDOperand();
Evan Cheng0db9fe62006-04-25 20:13:52 +00002824
2825 if (EVTBits == 32) {
2826 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2827 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2828 DAG);
2829 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002830 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
Chris Lattner5a88b832007-02-25 07:10:00 +00002831 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng0db9fe62006-04-25 20:13:52 +00002832 for (unsigned i = 0; i < NumElems; i++)
2833 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002834 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2835 &MaskVec[0], MaskVec.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00002836 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2837 DAG.getNode(ISD::UNDEF, VT), Mask);
2838 }
2839 }
2840
Dan Gohmana3941172007-07-24 22:55:08 +00002841 // A vector full of immediates; various special cases are already
2842 // handled, so this is best done with a single constant-pool load.
Evan Chengdb2d5242007-12-12 06:45:40 +00002843 if (!HasNonImms)
Dan Gohmana3941172007-07-24 22:55:08 +00002844 return SDOperand();
2845
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00002846 // Let legalizer expand 2-wide build_vectors.
Evan Cheng0db9fe62006-04-25 20:13:52 +00002847 if (EVTBits == 64)
2848 return SDOperand();
2849
2850 // If element VT is < 32 bits, convert it to inserts into a zero vector.
Bill Wendling826f36f2007-03-28 00:57:11 +00002851 if (EVTBits == 8 && NumElems == 16) {
Evan Cheng25ab6902006-09-08 06:48:29 +00002852 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2853 *this);
Evan Cheng0db9fe62006-04-25 20:13:52 +00002854 if (V.Val) return V;
2855 }
2856
Bill Wendling826f36f2007-03-28 00:57:11 +00002857 if (EVTBits == 16 && NumElems == 8) {
Evan Cheng25ab6902006-09-08 06:48:29 +00002858 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2859 *this);
Evan Cheng0db9fe62006-04-25 20:13:52 +00002860 if (V.Val) return V;
2861 }
2862
2863 // If element VT is == 32 bits, turn it into a number of shuffles.
Chris Lattner5a88b832007-02-25 07:10:00 +00002864 SmallVector<SDOperand, 8> V;
2865 V.resize(NumElems);
Evan Cheng0db9fe62006-04-25 20:13:52 +00002866 if (NumElems == 4 && NumZero > 0) {
2867 for (unsigned i = 0; i < 4; ++i) {
2868 bool isZero = !(NonZeros & (1 << i));
2869 if (isZero)
2870 V[i] = getZeroVector(VT, DAG);
2871 else
2872 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2873 }
2874
2875 for (unsigned i = 0; i < 2; ++i) {
2876 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2877 default: break;
2878 case 0:
2879 V[i] = V[i*2]; // Must be a zero vector.
2880 break;
2881 case 1:
2882 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2883 getMOVLMask(NumElems, DAG));
2884 break;
2885 case 2:
2886 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2887 getMOVLMask(NumElems, DAG));
2888 break;
2889 case 3:
2890 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2891 getUnpacklMask(NumElems, DAG));
2892 break;
2893 }
2894 }
2895
Evan Cheng069287d2006-05-16 07:21:53 +00002896 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00002897 // clears the upper bits.
Evan Cheng0db9fe62006-04-25 20:13:52 +00002898 // FIXME: we can do the same for v4f32 case when we know both parts of
2899 // the lower half come from scalar_to_vector (loadf32). We should do
2900 // that in post legalizer dag combiner with target specific hooks.
Evan Cheng9bbbb982006-10-25 20:48:19 +00002901 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
Evan Cheng0db9fe62006-04-25 20:13:52 +00002902 return V[0];
2903 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
Dan Gohman51eaa862007-06-14 22:58:02 +00002904 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
Chris Lattner5a88b832007-02-25 07:10:00 +00002905 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng0db9fe62006-04-25 20:13:52 +00002906 bool Reverse = (NonZeros & 0x3) == 2;
2907 for (unsigned i = 0; i < 2; ++i)
2908 if (Reverse)
2909 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2910 else
2911 MaskVec.push_back(DAG.getConstant(i, EVT));
2912 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2913 for (unsigned i = 0; i < 2; ++i)
2914 if (Reverse)
2915 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2916 else
2917 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
Chris Lattnere2199452006-08-11 17:38:39 +00002918 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2919 &MaskVec[0], MaskVec.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00002920 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2921 }
2922
2923 if (Values.size() > 2) {
2924 // Expand into a number of unpckl*.
2925 // e.g. for v4f32
2926 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2927 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2928 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2929 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2930 for (unsigned i = 0; i < NumElems; ++i)
2931 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2932 NumElems >>= 1;
2933 while (NumElems != 0) {
2934 for (unsigned i = 0; i < NumElems; ++i)
2935 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2936 UnpckMask);
2937 NumElems >>= 1;
2938 }
2939 return V[0];
2940 }
2941
2942 return SDOperand();
2943}
2944
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002945static
2946SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
2947 SDOperand PermMask, SelectionDAG &DAG,
2948 TargetLowering &TLI) {
Evan Cheng14b32e12007-12-11 01:46:18 +00002949 SDOperand NewV;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002950 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
2951 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
Evan Cheng14b32e12007-12-11 01:46:18 +00002952 MVT::ValueType PtrVT = TLI.getPointerTy();
2953 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
2954 PermMask.Val->op_end());
2955
2956 // First record which half of which vector the low elements come from.
2957 SmallVector<unsigned, 4> LowQuad(4);
2958 for (unsigned i = 0; i < 4; ++i) {
2959 SDOperand Elt = MaskElts[i];
2960 if (Elt.getOpcode() == ISD::UNDEF)
2961 continue;
2962 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
2963 int QuadIdx = EltIdx / 4;
2964 ++LowQuad[QuadIdx];
2965 }
2966 int BestLowQuad = -1;
2967 unsigned MaxQuad = 1;
2968 for (unsigned i = 0; i < 4; ++i) {
2969 if (LowQuad[i] > MaxQuad) {
2970 BestLowQuad = i;
2971 MaxQuad = LowQuad[i];
2972 }
Evan Cheng8a86c3f2007-12-07 08:07:39 +00002973 }
2974
Evan Cheng14b32e12007-12-11 01:46:18 +00002975 // Record which half of which vector the high elements come from.
2976 SmallVector<unsigned, 4> HighQuad(4);
2977 for (unsigned i = 4; i < 8; ++i) {
2978 SDOperand Elt = MaskElts[i];
2979 if (Elt.getOpcode() == ISD::UNDEF)
2980 continue;
2981 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
2982 int QuadIdx = EltIdx / 4;
2983 ++HighQuad[QuadIdx];
2984 }
2985 int BestHighQuad = -1;
2986 MaxQuad = 1;
2987 for (unsigned i = 0; i < 4; ++i) {
2988 if (HighQuad[i] > MaxQuad) {
2989 BestHighQuad = i;
2990 MaxQuad = HighQuad[i];
2991 }
2992 }
2993
2994 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
2995 if (BestLowQuad != -1 || BestHighQuad != -1) {
2996 // First sort the 4 chunks in order using shufpd.
2997 SmallVector<SDOperand, 8> MaskVec;
2998 if (BestLowQuad != -1)
2999 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3000 else
3001 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3002 if (BestHighQuad != -1)
3003 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3004 else
3005 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3006 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3007 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3008 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3009 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3010 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3011
3012 // Now sort high and low parts separately.
3013 BitVector InOrder(8);
3014 if (BestLowQuad != -1) {
3015 // Sort lower half in order using PSHUFLW.
3016 MaskVec.clear();
3017 bool AnyOutOrder = false;
3018 for (unsigned i = 0; i != 4; ++i) {
3019 SDOperand Elt = MaskElts[i];
3020 if (Elt.getOpcode() == ISD::UNDEF) {
3021 MaskVec.push_back(Elt);
3022 InOrder.set(i);
3023 } else {
3024 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3025 if (EltIdx != i)
3026 AnyOutOrder = true;
3027 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3028 // If this element is in the right place after this shuffle, then
3029 // remember it.
3030 if ((int)(EltIdx / 4) == BestLowQuad)
3031 InOrder.set(i);
3032 }
3033 }
3034 if (AnyOutOrder) {
3035 for (unsigned i = 4; i != 8; ++i)
3036 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3037 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3038 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3039 }
3040 }
3041
3042 if (BestHighQuad != -1) {
3043 // Sort high half in order using PSHUFHW if possible.
3044 MaskVec.clear();
3045 for (unsigned i = 0; i != 4; ++i)
3046 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3047 bool AnyOutOrder = false;
3048 for (unsigned i = 4; i != 8; ++i) {
3049 SDOperand Elt = MaskElts[i];
3050 if (Elt.getOpcode() == ISD::UNDEF) {
3051 MaskVec.push_back(Elt);
3052 InOrder.set(i);
3053 } else {
3054 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3055 if (EltIdx != i)
3056 AnyOutOrder = true;
3057 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3058 // If this element is in the right place after this shuffle, then
3059 // remember it.
3060 if ((int)(EltIdx / 4) == BestHighQuad)
3061 InOrder.set(i);
3062 }
3063 }
3064 if (AnyOutOrder) {
3065 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3066 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3067 }
3068 }
3069
3070 // The other elements are put in the right place using pextrw and pinsrw.
3071 for (unsigned i = 0; i != 8; ++i) {
3072 if (InOrder[i])
3073 continue;
3074 SDOperand Elt = MaskElts[i];
3075 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3076 if (EltIdx == i)
3077 continue;
3078 SDOperand ExtOp = (EltIdx < 8)
3079 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3080 DAG.getConstant(EltIdx, PtrVT))
3081 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3082 DAG.getConstant(EltIdx - 8, PtrVT));
3083 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3084 DAG.getConstant(i, PtrVT));
3085 }
3086 return NewV;
3087 }
3088
3089 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3090 ///as few as possible.
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003091 // First, let's find out how many elements are already in the right order.
3092 unsigned V1InOrder = 0;
3093 unsigned V1FromV1 = 0;
3094 unsigned V2InOrder = 0;
3095 unsigned V2FromV2 = 0;
Evan Cheng14b32e12007-12-11 01:46:18 +00003096 SmallVector<SDOperand, 8> V1Elts;
3097 SmallVector<SDOperand, 8> V2Elts;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003098 for (unsigned i = 0; i < 8; ++i) {
Evan Cheng14b32e12007-12-11 01:46:18 +00003099 SDOperand Elt = MaskElts[i];
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003100 if (Elt.getOpcode() == ISD::UNDEF) {
Evan Cheng14b32e12007-12-11 01:46:18 +00003101 V1Elts.push_back(Elt);
3102 V2Elts.push_back(Elt);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003103 ++V1InOrder;
3104 ++V2InOrder;
Evan Cheng14b32e12007-12-11 01:46:18 +00003105 continue;
3106 }
3107 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3108 if (EltIdx == i) {
3109 V1Elts.push_back(Elt);
3110 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3111 ++V1InOrder;
3112 } else if (EltIdx == i+8) {
3113 V1Elts.push_back(Elt);
3114 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3115 ++V2InOrder;
3116 } else if (EltIdx < 8) {
3117 V1Elts.push_back(Elt);
3118 ++V1FromV1;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003119 } else {
Evan Cheng14b32e12007-12-11 01:46:18 +00003120 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3121 ++V2FromV2;
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003122 }
3123 }
3124
3125 if (V2InOrder > V1InOrder) {
3126 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3127 std::swap(V1, V2);
3128 std::swap(V1Elts, V2Elts);
3129 std::swap(V1FromV1, V2FromV2);
3130 }
3131
Evan Cheng14b32e12007-12-11 01:46:18 +00003132 if ((V1FromV1 + V1InOrder) != 8) {
3133 // Some elements are from V2.
3134 if (V1FromV1) {
3135 // If there are elements that are from V1 but out of place,
3136 // then first sort them in place
3137 SmallVector<SDOperand, 8> MaskVec;
3138 for (unsigned i = 0; i < 8; ++i) {
3139 SDOperand Elt = V1Elts[i];
3140 if (Elt.getOpcode() == ISD::UNDEF) {
3141 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3142 continue;
3143 }
3144 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3145 if (EltIdx >= 8)
3146 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3147 else
3148 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3149 }
3150 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3151 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003152 }
Evan Cheng14b32e12007-12-11 01:46:18 +00003153
3154 NewV = V1;
3155 for (unsigned i = 0; i < 8; ++i) {
3156 SDOperand Elt = V1Elts[i];
3157 if (Elt.getOpcode() == ISD::UNDEF)
3158 continue;
3159 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3160 if (EltIdx < 8)
3161 continue;
3162 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3163 DAG.getConstant(EltIdx - 8, PtrVT));
3164 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3165 DAG.getConstant(i, PtrVT));
3166 }
3167 return NewV;
3168 } else {
3169 // All elements are from V1.
3170 NewV = V1;
3171 for (unsigned i = 0; i < 8; ++i) {
3172 SDOperand Elt = V1Elts[i];
3173 if (Elt.getOpcode() == ISD::UNDEF)
3174 continue;
3175 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3176 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3177 DAG.getConstant(EltIdx, PtrVT));
3178 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3179 DAG.getConstant(i, PtrVT));
3180 }
3181 return NewV;
3182 }
3183}
3184
Evan Cheng7a831ce2007-12-15 03:00:47 +00003185/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3186/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3187/// done when every pair / quad of shuffle mask elements point to elements in
3188/// the right sequence. e.g.
Evan Cheng14b32e12007-12-11 01:46:18 +00003189/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3190static
Evan Cheng7a831ce2007-12-15 03:00:47 +00003191SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3192 MVT::ValueType VT,
Evan Cheng14b32e12007-12-11 01:46:18 +00003193 SDOperand PermMask, SelectionDAG &DAG,
3194 TargetLowering &TLI) {
3195 unsigned NumElems = PermMask.getNumOperands();
Evan Cheng7a831ce2007-12-15 03:00:47 +00003196 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3197 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3198 MVT::ValueType NewVT = MaskVT;
3199 switch (VT) {
3200 case MVT::v4f32: NewVT = MVT::v2f64; break;
3201 case MVT::v4i32: NewVT = MVT::v2i64; break;
3202 case MVT::v8i16: NewVT = MVT::v4i32; break;
3203 case MVT::v16i8: NewVT = MVT::v4i32; break;
3204 default: assert(false && "Unexpected!");
3205 }
3206
3207 if (NewWidth == 2)
3208 if (MVT::isInteger(VT))
3209 NewVT = MVT::v2i64;
3210 else
3211 NewVT = MVT::v2f64;
3212 unsigned Scale = NumElems / NewWidth;
3213 SmallVector<SDOperand, 8> MaskVec;
Evan Cheng14b32e12007-12-11 01:46:18 +00003214 for (unsigned i = 0; i < NumElems; i += Scale) {
3215 unsigned StartIdx = ~0U;
3216 for (unsigned j = 0; j < Scale; ++j) {
3217 SDOperand Elt = PermMask.getOperand(i+j);
3218 if (Elt.getOpcode() == ISD::UNDEF)
3219 continue;
3220 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3221 if (StartIdx == ~0U)
3222 StartIdx = EltIdx - (EltIdx % Scale);
3223 if (EltIdx != StartIdx + j)
3224 return SDOperand();
3225 }
3226 if (StartIdx == ~0U)
3227 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3228 else
3229 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003230 }
3231
Evan Cheng7a831ce2007-12-15 03:00:47 +00003232 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3233 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3234 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3235 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3236 &MaskVec[0], MaskVec.size()));
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003237}
3238
Evan Cheng0db9fe62006-04-25 20:13:52 +00003239SDOperand
3240X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3241 SDOperand V1 = Op.getOperand(0);
3242 SDOperand V2 = Op.getOperand(1);
3243 SDOperand PermMask = Op.getOperand(2);
3244 MVT::ValueType VT = Op.getValueType();
3245 unsigned NumElems = PermMask.getNumOperands();
3246 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3247 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
Evan Chengd9b8e402006-10-16 06:36:00 +00003248 bool V1IsSplat = false;
3249 bool V2IsSplat = false;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003250
Evan Cheng8cf723d2006-09-08 01:50:06 +00003251 if (isUndefShuffle(Op.Val))
3252 return DAG.getNode(ISD::UNDEF, VT);
3253
Evan Cheng213d2cf2007-05-17 18:45:50 +00003254 if (isZeroShuffle(Op.Val))
3255 return getZeroVector(VT, DAG);
3256
Evan Cheng49892af2007-06-19 00:02:56 +00003257 if (isIdentityMask(PermMask.Val))
3258 return V1;
3259 else if (isIdentityMask(PermMask.Val, true))
3260 return V2;
3261
Evan Cheng0db9fe62006-04-25 20:13:52 +00003262 if (isSplatMask(PermMask.Val)) {
3263 if (NumElems <= 4) return Op;
3264 // Promote it to a v4i32 splat.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003265 return PromoteSplat(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003266 }
3267
Evan Cheng7a831ce2007-12-15 03:00:47 +00003268 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3269 // do it!
3270 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3271 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3272 if (NewOp.Val)
3273 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3274 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3275 // FIXME: Figure out a cleaner way to do this.
3276 // Try to make use of movq to zero out the top part.
3277 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3278 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3279 if (NewOp.Val) {
3280 SDOperand NewV1 = NewOp.getOperand(0);
3281 SDOperand NewV2 = NewOp.getOperand(1);
3282 SDOperand NewMask = NewOp.getOperand(2);
3283 if (isCommutedMOVL(NewMask.Val, true, false)) {
3284 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3285 NewOp = DAG.getNode(ISD::VECTOR_SHUFFLE, NewOp.getValueType(),
3286 NewV1, NewV2, getMOVLMask(2, DAG));
3287 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3288 }
3289 }
3290 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3291 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3292 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3293 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3294 }
3295 }
3296
Evan Cheng9bbbb982006-10-25 20:48:19 +00003297 if (X86::isMOVLMask(PermMask.Val))
3298 return (V1IsUndef) ? V2 : Op;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003299
Evan Cheng9bbbb982006-10-25 20:48:19 +00003300 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3301 X86::isMOVSLDUPMask(PermMask.Val) ||
3302 X86::isMOVHLPSMask(PermMask.Val) ||
3303 X86::isMOVHPMask(PermMask.Val) ||
3304 X86::isMOVLPMask(PermMask.Val))
3305 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003306
Evan Cheng9bbbb982006-10-25 20:48:19 +00003307 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3308 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
Evan Cheng9eca5e82006-10-25 21:49:50 +00003309 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003310
Evan Cheng9eca5e82006-10-25 21:49:50 +00003311 bool Commuted = false;
Chris Lattner8a594482007-11-25 00:24:49 +00003312 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3313 // 1,1,1,1 -> v8i16 though.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003314 V1IsSplat = isSplatVector(V1.Val);
3315 V2IsSplat = isSplatVector(V2.Val);
Chris Lattner8a594482007-11-25 00:24:49 +00003316
3317 // Canonicalize the splat or undef, if present, to be on the RHS.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003318 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
Evan Cheng9eca5e82006-10-25 21:49:50 +00003319 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng9bbbb982006-10-25 20:48:19 +00003320 std::swap(V1IsSplat, V2IsSplat);
3321 std::swap(V1IsUndef, V2IsUndef);
Evan Cheng9eca5e82006-10-25 21:49:50 +00003322 Commuted = true;
Evan Cheng9bbbb982006-10-25 20:48:19 +00003323 }
3324
Evan Cheng7a831ce2007-12-15 03:00:47 +00003325 // FIXME: Figure out a cleaner way to do this.
Evan Cheng9bbbb982006-10-25 20:48:19 +00003326 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3327 if (V2IsUndef) return V1;
Evan Cheng9eca5e82006-10-25 21:49:50 +00003328 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
Evan Cheng9bbbb982006-10-25 20:48:19 +00003329 if (V2IsSplat) {
3330 // V2 is a splat, so the mask may be malformed. That is, it may point
3331 // to any V2 element. The instruction selectior won't like this. Get
3332 // a corrected mask and commute to form a proper MOVS{S|D}.
3333 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3334 if (NewMask.Val != PermMask.Val)
3335 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003336 }
Evan Cheng9bbbb982006-10-25 20:48:19 +00003337 return Op;
Evan Chengd9b8e402006-10-16 06:36:00 +00003338 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003339
Evan Chengd9b8e402006-10-16 06:36:00 +00003340 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00003341 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
Evan Chengd9b8e402006-10-16 06:36:00 +00003342 X86::isUNPCKLMask(PermMask.Val) ||
3343 X86::isUNPCKHMask(PermMask.Val))
3344 return Op;
Evan Chenge1113032006-10-04 18:33:38 +00003345
Evan Cheng9bbbb982006-10-25 20:48:19 +00003346 if (V2IsSplat) {
3347 // Normalize mask so all entries that point to V2 points to its first
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003348 // element then try to match unpck{h|l} again. If match, return a
Evan Cheng9bbbb982006-10-25 20:48:19 +00003349 // new vector_shuffle with the corrected mask.
3350 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3351 if (NewMask.Val != PermMask.Val) {
3352 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3353 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3354 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3355 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3356 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3357 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003358 }
3359 }
3360 }
3361
3362 // Normalize the node to match x86 shuffle ops if needed
Evan Cheng9eca5e82006-10-25 21:49:50 +00003363 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3364 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3365
3366 if (Commuted) {
3367 // Commute is back and try unpck* again.
3368 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3369 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
Bill Wendling2f9bb1a2007-04-24 21:16:55 +00003370 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
Evan Cheng9eca5e82006-10-25 21:49:50 +00003371 X86::isUNPCKLMask(PermMask.Val) ||
3372 X86::isUNPCKHMask(PermMask.Val))
3373 return Op;
3374 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00003375
3376 // If VT is integer, try PSHUF* first, then SHUFP*.
3377 if (MVT::isInteger(VT)) {
Dan Gohman7f55fcb2007-08-02 21:17:01 +00003378 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
3379 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3380 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
3381 X86::isPSHUFDMask(PermMask.Val)) ||
Evan Cheng0db9fe62006-04-25 20:13:52 +00003382 X86::isPSHUFHWMask(PermMask.Val) ||
3383 X86::isPSHUFLWMask(PermMask.Val)) {
3384 if (V2.getOpcode() != ISD::UNDEF)
3385 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3386 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3387 return Op;
3388 }
3389
Chris Lattner07c70cd2007-05-17 17:13:13 +00003390 if (X86::isSHUFPMask(PermMask.Val) &&
3391 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003392 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003393 } else {
3394 // Floating point cases in the other order.
3395 if (X86::isSHUFPMask(PermMask.Val))
3396 return Op;
3397 if (X86::isPSHUFDMask(PermMask.Val) ||
3398 X86::isPSHUFHWMask(PermMask.Val) ||
3399 X86::isPSHUFLWMask(PermMask.Val)) {
3400 if (V2.getOpcode() != ISD::UNDEF)
3401 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3402 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3403 return Op;
3404 }
3405 }
3406
Evan Cheng14b32e12007-12-11 01:46:18 +00003407 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3408 if (VT == MVT::v8i16) {
3409 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3410 if (NewOp.Val)
3411 return NewOp;
3412 }
3413
3414 // Handle all 4 wide cases with a number of shuffles.
3415 if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) {
Evan Cheng8a86c3f2007-12-07 08:07:39 +00003416 // Don't do this for MMX.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003417 MVT::ValueType MaskVT = PermMask.getValueType();
Dan Gohman51eaa862007-06-14 22:58:02 +00003418 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
Chris Lattner5a88b832007-02-25 07:10:00 +00003419 SmallVector<std::pair<int, int>, 8> Locs;
Evan Cheng43f3bd32006-04-28 07:03:38 +00003420 Locs.reserve(NumElems);
Evan Cheng14b32e12007-12-11 01:46:18 +00003421 SmallVector<SDOperand, 8> Mask1(NumElems,
3422 DAG.getNode(ISD::UNDEF, MaskEVT));
3423 SmallVector<SDOperand, 8> Mask2(NumElems,
3424 DAG.getNode(ISD::UNDEF, MaskEVT));
Evan Cheng43f3bd32006-04-28 07:03:38 +00003425 unsigned NumHi = 0;
3426 unsigned NumLo = 0;
3427 // If no more than two elements come from either vector. This can be
3428 // implemented with two shuffles. First shuffle gather the elements.
3429 // The second shuffle, which takes the first shuffle as both of its
3430 // vector operands, put the elements into the right order.
3431 for (unsigned i = 0; i != NumElems; ++i) {
3432 SDOperand Elt = PermMask.getOperand(i);
3433 if (Elt.getOpcode() == ISD::UNDEF) {
3434 Locs[i] = std::make_pair(-1, -1);
3435 } else {
3436 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3437 if (Val < NumElems) {
3438 Locs[i] = std::make_pair(0, NumLo);
3439 Mask1[NumLo] = Elt;
3440 NumLo++;
3441 } else {
3442 Locs[i] = std::make_pair(1, NumHi);
3443 if (2+NumHi < NumElems)
3444 Mask1[2+NumHi] = Elt;
3445 NumHi++;
3446 }
3447 }
3448 }
3449 if (NumLo <= 2 && NumHi <= 2) {
3450 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
Chris Lattnere2199452006-08-11 17:38:39 +00003451 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3452 &Mask1[0], Mask1.size()));
Evan Cheng43f3bd32006-04-28 07:03:38 +00003453 for (unsigned i = 0; i != NumElems; ++i) {
3454 if (Locs[i].first == -1)
3455 continue;
3456 else {
3457 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3458 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3459 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3460 }
3461 }
3462
3463 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
Chris Lattnere2199452006-08-11 17:38:39 +00003464 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3465 &Mask2[0], Mask2.size()));
Evan Cheng43f3bd32006-04-28 07:03:38 +00003466 }
3467
3468 // Break it into (shuffle shuffle_hi, shuffle_lo).
3469 Locs.clear();
Chris Lattner5a88b832007-02-25 07:10:00 +00003470 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3471 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3472 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003473 unsigned MaskIdx = 0;
3474 unsigned LoIdx = 0;
3475 unsigned HiIdx = NumElems/2;
3476 for (unsigned i = 0; i != NumElems; ++i) {
3477 if (i == NumElems/2) {
3478 MaskPtr = &HiMask;
3479 MaskIdx = 1;
3480 LoIdx = 0;
3481 HiIdx = NumElems/2;
3482 }
3483 SDOperand Elt = PermMask.getOperand(i);
3484 if (Elt.getOpcode() == ISD::UNDEF) {
3485 Locs[i] = std::make_pair(-1, -1);
3486 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3487 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3488 (*MaskPtr)[LoIdx] = Elt;
3489 LoIdx++;
3490 } else {
3491 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3492 (*MaskPtr)[HiIdx] = Elt;
3493 HiIdx++;
3494 }
3495 }
3496
Chris Lattner8c0c10c2006-05-16 06:45:34 +00003497 SDOperand LoShuffle =
3498 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
Chris Lattnere2199452006-08-11 17:38:39 +00003499 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3500 &LoMask[0], LoMask.size()));
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003501 SDOperand HiShuffle =
Chris Lattner8c0c10c2006-05-16 06:45:34 +00003502 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
Chris Lattnere2199452006-08-11 17:38:39 +00003503 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3504 &HiMask[0], HiMask.size()));
Chris Lattner5a88b832007-02-25 07:10:00 +00003505 SmallVector<SDOperand, 8> MaskOps;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003506 for (unsigned i = 0; i != NumElems; ++i) {
3507 if (Locs[i].first == -1) {
3508 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3509 } else {
3510 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3511 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3512 }
3513 }
3514 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
Chris Lattnere2199452006-08-11 17:38:39 +00003515 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3516 &MaskOps[0], MaskOps.size()));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003517 }
3518
3519 return SDOperand();
3520}
3521
3522SDOperand
3523X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3524 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3525 return SDOperand();
3526
3527 MVT::ValueType VT = Op.getValueType();
3528 // TODO: handle v16i8.
3529 if (MVT::getSizeInBits(VT) == 16) {
Evan Cheng14b32e12007-12-11 01:46:18 +00003530 SDOperand Vec = Op.getOperand(0);
3531 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3532 if (Idx == 0)
3533 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
3534 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3535 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
3536 Op.getOperand(1)));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003537 // Transform it so it match pextrw which produces a 32-bit result.
3538 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3539 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3540 Op.getOperand(0), Op.getOperand(1));
3541 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3542 DAG.getValueType(VT));
3543 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3544 } else if (MVT::getSizeInBits(VT) == 32) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003545 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3546 if (Idx == 0)
3547 return Op;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003548 // SHUFPS the element to the lowest double word, then movss.
3549 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
Chris Lattner5a88b832007-02-25 07:10:00 +00003550 SmallVector<SDOperand, 8> IdxVec;
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00003551 IdxVec.
3552 push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3553 IdxVec.
3554 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3555 IdxVec.
3556 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3557 IdxVec.
3558 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
Chris Lattnere2199452006-08-11 17:38:39 +00003559 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3560 &IdxVec[0], IdxVec.size());
Evan Cheng14b32e12007-12-11 01:46:18 +00003561 SDOperand Vec = Op.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003562 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
Evan Cheng6e56e2c2006-11-07 22:14:24 +00003563 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003564 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
Evan Cheng015188f2006-06-15 08:14:54 +00003565 DAG.getConstant(0, getPointerTy()));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003566 } else if (MVT::getSizeInBits(VT) == 64) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003567 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3568 if (Idx == 0)
3569 return Op;
3570
3571 // UNPCKHPD the element to the lowest double word, then movsd.
3572 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3573 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3574 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
Chris Lattner5a88b832007-02-25 07:10:00 +00003575 SmallVector<SDOperand, 8> IdxVec;
Dan Gohman51eaa862007-06-14 22:58:02 +00003576 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00003577 IdxVec.
3578 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
Chris Lattnere2199452006-08-11 17:38:39 +00003579 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3580 &IdxVec[0], IdxVec.size());
Evan Cheng14b32e12007-12-11 01:46:18 +00003581 SDOperand Vec = Op.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003582 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3583 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3584 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
Evan Cheng015188f2006-06-15 08:14:54 +00003585 DAG.getConstant(0, getPointerTy()));
Evan Cheng0db9fe62006-04-25 20:13:52 +00003586 }
3587
3588 return SDOperand();
3589}
3590
3591SDOperand
3592X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003593 MVT::ValueType VT = Op.getValueType();
Evan Cheng794405e2007-12-12 07:55:34 +00003594 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3595 if (EVT == MVT::i8)
3596 return SDOperand();
3597
Evan Cheng0db9fe62006-04-25 20:13:52 +00003598 SDOperand N0 = Op.getOperand(0);
3599 SDOperand N1 = Op.getOperand(1);
3600 SDOperand N2 = Op.getOperand(2);
Evan Cheng794405e2007-12-12 07:55:34 +00003601
3602 if (MVT::getSizeInBits(EVT) == 16) {
3603 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3604 // as its second argument.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003605 if (N1.getValueType() != MVT::i32)
3606 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3607 if (N2.getValueType() != MVT::i32)
Evan Cheng0db58622007-06-29 00:01:20 +00003608 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003609 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003610 }
Nate Begeman219f67f2008-01-05 20:51:30 +00003611 return SDOperand();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003612}
3613
3614SDOperand
3615X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3616 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3617 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3618}
3619
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00003620// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
Evan Cheng0db9fe62006-04-25 20:13:52 +00003621// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3622// one of the above mentioned nodes. It has to be wrapped because otherwise
3623// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3624// be used to form addressing mode. These wrapped nodes will be selected
3625// into MOV32ri.
3626SDOperand
3627X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3628 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Evan Chengd0ff02c2006-11-29 23:19:46 +00003629 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3630 getPointerTy(),
3631 CP->getAlignment());
Evan Cheng19f2ffc2006-12-05 04:01:03 +00003632 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00003633 // With PIC, the address is actually $g + Offset.
3634 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3635 !Subtarget->isPICStyleRIPRel()) {
3636 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3637 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3638 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003639 }
3640
3641 return Result;
3642}
3643
3644SDOperand
3645X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3646 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Evan Chengd0ff02c2006-11-29 23:19:46 +00003647 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
Evan Cheng19f2ffc2006-12-05 04:01:03 +00003648 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00003649 // With PIC, the address is actually $g + Offset.
3650 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3651 !Subtarget->isPICStyleRIPRel()) {
3652 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3653 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3654 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003655 }
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00003656
3657 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3658 // load the value at address GV, not the value of GV itself. This means that
3659 // the GlobalAddress must be in the base or index register of the address, not
3660 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
Anton Korobeynikov7f705592007-01-12 19:20:47 +00003661 // The same applies for external symbols during PIC codegen
Anton Korobeynikov2b2bc682006-12-22 22:29:05 +00003662 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3663 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003664
3665 return Result;
3666}
3667
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00003668// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3669static SDOperand
3670LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3671 const MVT::ValueType PtrVT) {
3672 SDOperand InFlag;
3673 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3674 DAG.getNode(X86ISD::GlobalBaseReg,
3675 PtrVT), InFlag);
3676 InFlag = Chain.getValue(1);
3677
3678 // emit leal symbol@TLSGD(,%ebx,1), %eax
3679 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3680 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3681 GA->getValueType(0),
3682 GA->getOffset());
3683 SDOperand Ops[] = { Chain, TGA, InFlag };
3684 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3685 InFlag = Result.getValue(2);
3686 Chain = Result.getValue(1);
3687
3688 // call ___tls_get_addr. This function receives its argument in
3689 // the register EAX.
3690 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3691 InFlag = Chain.getValue(1);
3692
3693 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3694 SDOperand Ops1[] = { Chain,
3695 DAG.getTargetExternalSymbol("___tls_get_addr",
3696 PtrVT),
3697 DAG.getRegister(X86::EAX, PtrVT),
3698 DAG.getRegister(X86::EBX, PtrVT),
3699 InFlag };
3700 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3701 InFlag = Chain.getValue(1);
3702
3703 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3704}
3705
3706// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3707// "local exec" model.
3708static SDOperand
3709LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3710 const MVT::ValueType PtrVT) {
3711 // Get the Thread Pointer
3712 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3713 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3714 // exec)
3715 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3716 GA->getValueType(0),
3717 GA->getOffset());
3718 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
Lauro Ramos Venancio7d2cc2b2007-04-22 22:50:52 +00003719
3720 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3721 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3722
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00003723 // The address of the thread local variable is the add of the thread
3724 // pointer with the offset of the variable.
3725 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3726}
3727
3728SDOperand
3729X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3730 // TODO: implement the "local dynamic" model
Lauro Ramos Venancio2c5c1112007-04-21 20:56:26 +00003731 // TODO: implement the "initial exec"model for pic executables
3732 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3733 "TLS not implemented for non-ELF and 64-bit targets");
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00003734 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3735 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3736 // otherwise use the "Local Exec"TLS Model
3737 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3738 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3739 else
3740 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3741}
3742
Evan Cheng0db9fe62006-04-25 20:13:52 +00003743SDOperand
3744X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3745 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
Evan Chengd0ff02c2006-11-29 23:19:46 +00003746 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
Evan Cheng19f2ffc2006-12-05 04:01:03 +00003747 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
Anton Korobeynikov7f705592007-01-12 19:20:47 +00003748 // With PIC, the address is actually $g + Offset.
3749 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3750 !Subtarget->isPICStyleRIPRel()) {
3751 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3752 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3753 Result);
3754 }
3755
3756 return Result;
3757}
3758
3759SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3760 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3761 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3762 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3763 // With PIC, the address is actually $g + Offset.
3764 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3765 !Subtarget->isPICStyleRIPRel()) {
3766 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3767 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3768 Result);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003769 }
3770
3771 return Result;
3772}
3773
Chris Lattner2ff75ee2007-10-17 06:02:13 +00003774/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
3775/// take a 2 x i32 value to shift plus a shift amount.
Evan Cheng0db9fe62006-04-25 20:13:52 +00003776SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner2ff75ee2007-10-17 06:02:13 +00003777 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3778 "Not an i64 shift!");
3779 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3780 SDOperand ShOpLo = Op.getOperand(0);
3781 SDOperand ShOpHi = Op.getOperand(1);
3782 SDOperand ShAmt = Op.getOperand(2);
3783 SDOperand Tmp1 = isSRA ?
3784 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3785 DAG.getConstant(0, MVT::i32);
Evan Chenge3413162006-01-09 18:33:28 +00003786
Chris Lattner2ff75ee2007-10-17 06:02:13 +00003787 SDOperand Tmp2, Tmp3;
3788 if (Op.getOpcode() == ISD::SHL_PARTS) {
3789 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3790 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3791 } else {
3792 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3793 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3794 }
Evan Chenge3413162006-01-09 18:33:28 +00003795
Chris Lattner2ff75ee2007-10-17 06:02:13 +00003796 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3797 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3798 DAG.getConstant(32, MVT::i8));
3799 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32,
3800 AndNode, DAG.getConstant(0, MVT::i8));
Evan Chenge3413162006-01-09 18:33:28 +00003801
Chris Lattner2ff75ee2007-10-17 06:02:13 +00003802 SDOperand Hi, Lo;
3803 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3804 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3805 SmallVector<SDOperand, 4> Ops;
3806 if (Op.getOpcode() == ISD::SHL_PARTS) {
3807 Ops.push_back(Tmp2);
3808 Ops.push_back(Tmp3);
3809 Ops.push_back(CC);
3810 Ops.push_back(Cond);
3811 Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
Evan Chenge3413162006-01-09 18:33:28 +00003812
Evan Chenge3413162006-01-09 18:33:28 +00003813 Ops.clear();
Chris Lattner2ff75ee2007-10-17 06:02:13 +00003814 Ops.push_back(Tmp3);
3815 Ops.push_back(Tmp1);
3816 Ops.push_back(CC);
3817 Ops.push_back(Cond);
3818 Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3819 } else {
3820 Ops.push_back(Tmp2);
3821 Ops.push_back(Tmp3);
3822 Ops.push_back(CC);
3823 Ops.push_back(Cond);
3824 Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3825
3826 Ops.clear();
3827 Ops.push_back(Tmp3);
3828 Ops.push_back(Tmp1);
3829 Ops.push_back(CC);
3830 Ops.push_back(Cond);
3831 Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3832 }
3833
3834 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3835 Ops.clear();
3836 Ops.push_back(Lo);
3837 Ops.push_back(Hi);
3838 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003839}
Evan Chenga3195e82006-01-12 22:54:21 +00003840
Evan Cheng0db9fe62006-04-25 20:13:52 +00003841SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3842 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3843 Op.getOperand(0).getValueType() >= MVT::i16 &&
3844 "Unknown SINT_TO_FP to lower!");
3845
3846 SDOperand Result;
3847 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3848 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3849 MachineFunction &MF = DAG.getMachineFunction();
3850 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3851 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Evan Cheng786225a2006-10-05 23:01:46 +00003852 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
Evan Cheng8b2794a2006-10-13 21:14:26 +00003853 StackSlot, NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003854
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00003855 // These are really Legal; caller falls through into that case.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +00003856 if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f32 && X86ScalarSSEf32)
3857 return Result;
3858 if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f64 && X86ScalarSSEf64)
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00003859 return Result;
Dale Johannesen73328d12007-09-19 23:55:34 +00003860 if (SrcVT==MVT::i64 && Op.getValueType() != MVT::f80 &&
3861 Subtarget->is64Bit())
3862 return Result;
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00003863
Evan Cheng0db9fe62006-04-25 20:13:52 +00003864 // Build the FILD
Chris Lattner5a88b832007-02-25 07:10:00 +00003865 SDVTList Tys;
Dale Johannesenf1fc3a82007-09-23 14:52:20 +00003866 bool useSSE = (X86ScalarSSEf32 && Op.getValueType() == MVT::f32) ||
3867 (X86ScalarSSEf64 && Op.getValueType() == MVT::f64);
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00003868 if (useSSE)
Chris Lattner5a88b832007-02-25 07:10:00 +00003869 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3870 else
Dale Johannesen849f2142007-07-03 00:53:03 +00003871 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
Chris Lattner5a88b832007-02-25 07:10:00 +00003872 SmallVector<SDOperand, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003873 Ops.push_back(Chain);
3874 Ops.push_back(StackSlot);
3875 Ops.push_back(DAG.getValueType(SrcVT));
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00003876 Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003877 Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003878
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00003879 if (useSSE) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003880 Chain = Result.getValue(1);
3881 SDOperand InFlag = Result.getValue(2);
3882
3883 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3884 // shouldn't be necessary except that RFP cannot be live across
3885 // multiple blocks. When stackifier is fixed, they can be uncoupled.
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00003886 MachineFunction &MF = DAG.getMachineFunction();
Evan Cheng0db9fe62006-04-25 20:13:52 +00003887 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00003888 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Chris Lattner5a88b832007-02-25 07:10:00 +00003889 Tys = DAG.getVTList(MVT::Other);
3890 SmallVector<SDOperand, 8> Ops;
Evan Chenga3195e82006-01-12 22:54:21 +00003891 Ops.push_back(Chain);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003892 Ops.push_back(Result);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00003893 Ops.push_back(StackSlot);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003894 Ops.push_back(DAG.getValueType(Op.getValueType()));
3895 Ops.push_back(InFlag);
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003896 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
Evan Cheng466685d2006-10-09 20:57:25 +00003897 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00003898 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00003899
Evan Cheng0db9fe62006-04-25 20:13:52 +00003900 return Result;
3901}
3902
Chris Lattner27a6c732007-11-24 07:07:01 +00003903std::pair<SDOperand,SDOperand> X86TargetLowering::
3904FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003905 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3906 "Unknown FP_TO_SINT to lower!");
Evan Cheng0db9fe62006-04-25 20:13:52 +00003907
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00003908 // These are really Legal.
Dale Johannesenf1fc3a82007-09-23 14:52:20 +00003909 if (Op.getValueType() == MVT::i32 &&
3910 X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32)
Chris Lattner27a6c732007-11-24 07:07:01 +00003911 return std::make_pair(SDOperand(), SDOperand());
Dale Johannesenf1fc3a82007-09-23 14:52:20 +00003912 if (Op.getValueType() == MVT::i32 &&
3913 X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)
Chris Lattner27a6c732007-11-24 07:07:01 +00003914 return std::make_pair(SDOperand(), SDOperand());
Dale Johannesen73328d12007-09-19 23:55:34 +00003915 if (Subtarget->is64Bit() &&
3916 Op.getValueType() == MVT::i64 &&
3917 Op.getOperand(0).getValueType() != MVT::f80)
Chris Lattner27a6c732007-11-24 07:07:01 +00003918 return std::make_pair(SDOperand(), SDOperand());
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00003919
Evan Cheng87c89352007-10-15 20:11:21 +00003920 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3921 // stack slot.
3922 MachineFunction &MF = DAG.getMachineFunction();
3923 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3924 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3925 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
Evan Cheng0db9fe62006-04-25 20:13:52 +00003926 unsigned Opc;
3927 switch (Op.getValueType()) {
Chris Lattner27a6c732007-11-24 07:07:01 +00003928 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3929 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3930 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3931 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
Evan Cheng0db9fe62006-04-25 20:13:52 +00003932 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00003933
Evan Cheng0db9fe62006-04-25 20:13:52 +00003934 SDOperand Chain = DAG.getEntryNode();
3935 SDOperand Value = Op.getOperand(0);
Dale Johannesenf1fc3a82007-09-23 14:52:20 +00003936 if ((X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32) ||
3937 (X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00003938 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
Evan Cheng8b2794a2006-10-13 21:14:26 +00003939 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
Dale Johannesen849f2142007-07-03 00:53:03 +00003940 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
Chris Lattner5a88b832007-02-25 07:10:00 +00003941 SDOperand Ops[] = {
3942 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3943 };
3944 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003945 Chain = Value.getValue(1);
3946 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3947 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3948 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00003949
Evan Cheng0db9fe62006-04-25 20:13:52 +00003950 // Build the FP_TO_INT*_IN_MEM
Chris Lattner5a88b832007-02-25 07:10:00 +00003951 SDOperand Ops[] = { Chain, Value, StackSlot };
3952 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
Evan Chengd9558e02006-01-06 00:43:03 +00003953
Chris Lattner27a6c732007-11-24 07:07:01 +00003954 return std::make_pair(FIST, StackSlot);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003955}
3956
Chris Lattner27a6c732007-11-24 07:07:01 +00003957SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner27a6c732007-11-24 07:07:01 +00003958 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
3959 SDOperand FIST = Vals.first, StackSlot = Vals.second;
3960 if (FIST.Val == 0) return SDOperand();
3961
3962 // Load the result.
3963 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3964}
3965
3966SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
3967 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
3968 SDOperand FIST = Vals.first, StackSlot = Vals.second;
3969 if (FIST.Val == 0) return 0;
3970
3971 // Return an i64 load from the stack slot.
3972 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0);
3973
3974 // Use a MERGE_VALUES node to drop the chain result value.
3975 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val;
3976}
3977
Evan Cheng0db9fe62006-04-25 20:13:52 +00003978SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3979 MVT::ValueType VT = Op.getValueType();
Dan Gohman20382522007-07-10 00:05:58 +00003980 MVT::ValueType EltVT = VT;
3981 if (MVT::isVector(VT))
3982 EltVT = MVT::getVectorElementType(VT);
3983 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003984 std::vector<Constant*> CV;
Dan Gohman20382522007-07-10 00:05:58 +00003985 if (EltVT == MVT::f64) {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00003986 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63))));
Dan Gohman20382522007-07-10 00:05:58 +00003987 CV.push_back(C);
3988 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003989 } else {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00003990 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31))));
Dan Gohman20382522007-07-10 00:05:58 +00003991 CV.push_back(C);
3992 CV.push_back(C);
3993 CV.push_back(C);
3994 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00003995 }
Dan Gohmand3006222007-07-27 17:16:43 +00003996 Constant *C = ConstantVector::get(CV);
3997 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3998 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3999 false, 16);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004000 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4001}
4002
4003SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4004 MVT::ValueType VT = Op.getValueType();
Dan Gohman20382522007-07-10 00:05:58 +00004005 MVT::ValueType EltVT = VT;
Evan Chengd4d01b72007-07-19 23:36:01 +00004006 unsigned EltNum = 1;
4007 if (MVT::isVector(VT)) {
Dan Gohman20382522007-07-10 00:05:58 +00004008 EltVT = MVT::getVectorElementType(VT);
Evan Chengd4d01b72007-07-19 23:36:01 +00004009 EltNum = MVT::getVectorNumElements(VT);
4010 }
Dan Gohman20382522007-07-10 00:05:58 +00004011 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004012 std::vector<Constant*> CV;
Dan Gohman20382522007-07-10 00:05:58 +00004013 if (EltVT == MVT::f64) {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004014 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63)));
Dan Gohman20382522007-07-10 00:05:58 +00004015 CV.push_back(C);
4016 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004017 } else {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004018 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31)));
Dan Gohman20382522007-07-10 00:05:58 +00004019 CV.push_back(C);
4020 CV.push_back(C);
4021 CV.push_back(C);
4022 CV.push_back(C);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004023 }
Dan Gohmand3006222007-07-27 17:16:43 +00004024 Constant *C = ConstantVector::get(CV);
4025 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4026 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4027 false, 16);
Evan Chengd4d01b72007-07-19 23:36:01 +00004028 if (MVT::isVector(VT)) {
Evan Chengd4d01b72007-07-19 23:36:01 +00004029 return DAG.getNode(ISD::BIT_CONVERT, VT,
4030 DAG.getNode(ISD::XOR, MVT::v2i64,
4031 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4032 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4033 } else {
Evan Chengd4d01b72007-07-19 23:36:01 +00004034 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4035 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004036}
4037
Evan Cheng68c47cb2007-01-05 07:55:56 +00004038SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng73d6cf12007-01-05 21:37:56 +00004039 SDOperand Op0 = Op.getOperand(0);
4040 SDOperand Op1 = Op.getOperand(1);
Evan Cheng68c47cb2007-01-05 07:55:56 +00004041 MVT::ValueType VT = Op.getValueType();
Evan Cheng73d6cf12007-01-05 21:37:56 +00004042 MVT::ValueType SrcVT = Op1.getValueType();
Evan Cheng68c47cb2007-01-05 07:55:56 +00004043 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004044
4045 // If second operand is smaller, extend it first.
4046 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
4047 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4048 SrcVT = VT;
Dale Johannesen43421b32007-09-06 18:13:44 +00004049 SrcTy = MVT::getTypeForValueType(SrcVT);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004050 }
Dale Johannesen61c7ef32007-10-21 01:07:44 +00004051 // And if it is bigger, shrink it first.
4052 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4053 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1);
4054 SrcVT = VT;
4055 SrcTy = MVT::getTypeForValueType(SrcVT);
4056 }
4057
4058 // At this point the operands and the result should have the same
4059 // type, and that won't be f80 since that is not custom lowered.
Evan Cheng73d6cf12007-01-05 21:37:56 +00004060
Evan Cheng68c47cb2007-01-05 07:55:56 +00004061 // First get the sign bit of second operand.
4062 std::vector<Constant*> CV;
4063 if (SrcVT == MVT::f64) {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004064 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63))));
4065 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004066 } else {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004067 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31))));
4068 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4069 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4070 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004071 }
Dan Gohmand3006222007-07-27 17:16:43 +00004072 Constant *C = ConstantVector::get(CV);
4073 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4074 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
4075 false, 16);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004076 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
Evan Cheng68c47cb2007-01-05 07:55:56 +00004077
4078 // Shift sign bit right or left if the two operands have different types.
4079 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4080 // Op0 is MVT::f32, Op1 is MVT::f64.
4081 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4082 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4083 DAG.getConstant(32, MVT::i32));
4084 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4085 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4086 DAG.getConstant(0, getPointerTy()));
Evan Cheng68c47cb2007-01-05 07:55:56 +00004087 }
4088
Evan Cheng73d6cf12007-01-05 21:37:56 +00004089 // Clear first operand sign bit.
4090 CV.clear();
4091 if (VT == MVT::f64) {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004092 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63)))));
4093 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
Evan Cheng73d6cf12007-01-05 21:37:56 +00004094 } else {
Dale Johannesen3f6eb742007-09-11 18:32:33 +00004095 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31)))));
4096 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4097 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4098 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
Evan Cheng73d6cf12007-01-05 21:37:56 +00004099 }
Dan Gohmand3006222007-07-27 17:16:43 +00004100 C = ConstantVector::get(CV);
4101 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4102 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4103 false, 16);
Evan Cheng73d6cf12007-01-05 21:37:56 +00004104 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4105
4106 // Or the value with the sign bit.
4107 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
Evan Cheng68c47cb2007-01-05 07:55:56 +00004108}
4109
Evan Chenge5f62042007-09-29 00:00:36 +00004110SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng0488db92007-09-25 01:57:46 +00004111 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
Evan Cheng1a35edb2007-09-26 00:45:55 +00004112 SDOperand Cond;
Evan Cheng0488db92007-09-25 01:57:46 +00004113 SDOperand Op0 = Op.getOperand(0);
4114 SDOperand Op1 = Op.getOperand(1);
4115 SDOperand CC = Op.getOperand(2);
4116 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4117 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
4118 unsigned X86CC;
4119
Evan Cheng0488db92007-09-25 01:57:46 +00004120 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
Evan Cheng1a35edb2007-09-26 00:45:55 +00004121 Op0, Op1, DAG)) {
Evan Chenge5f62042007-09-29 00:00:36 +00004122 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4123 return DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004124 DAG.getConstant(X86CC, MVT::i8), Cond);
Evan Cheng1a35edb2007-09-26 00:45:55 +00004125 }
Evan Cheng0488db92007-09-25 01:57:46 +00004126
4127 assert(isFP && "Illegal integer SetCC!");
4128
Evan Chenge5f62042007-09-29 00:00:36 +00004129 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
Evan Cheng0488db92007-09-25 01:57:46 +00004130 switch (SetCCOpcode) {
4131 default: assert(false && "Illegal floating point SetCC!");
4132 case ISD::SETOEQ: { // !PF & ZF
Evan Chenge5f62042007-09-29 00:00:36 +00004133 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004134 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
Evan Chenge5f62042007-09-29 00:00:36 +00004135 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004136 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4137 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4138 }
4139 case ISD::SETUNE: { // PF | !ZF
Evan Chenge5f62042007-09-29 00:00:36 +00004140 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004141 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
Evan Chenge5f62042007-09-29 00:00:36 +00004142 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
Evan Cheng0488db92007-09-25 01:57:46 +00004143 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4144 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4145 }
4146 }
4147}
4148
4149
Evan Cheng0db9fe62006-04-25 20:13:52 +00004150SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng734503b2006-09-11 02:19:56 +00004151 bool addTest = true;
Evan Cheng734503b2006-09-11 02:19:56 +00004152 SDOperand Cond = Op.getOperand(0);
4153 SDOperand CC;
Evan Cheng9bba8942006-01-26 02:13:10 +00004154
Evan Cheng734503b2006-09-11 02:19:56 +00004155 if (Cond.getOpcode() == ISD::SETCC)
Evan Chenge5f62042007-09-29 00:00:36 +00004156 Cond = LowerSETCC(Cond, DAG);
Evan Cheng734503b2006-09-11 02:19:56 +00004157
Evan Cheng3f41d662007-10-08 22:16:29 +00004158 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4159 // setting operand in place of the X86ISD::SETCC.
Evan Cheng734503b2006-09-11 02:19:56 +00004160 if (Cond.getOpcode() == X86ISD::SETCC) {
4161 CC = Cond.getOperand(0);
4162
Evan Cheng734503b2006-09-11 02:19:56 +00004163 SDOperand Cmp = Cond.getOperand(1);
4164 unsigned Opc = Cmp.getOpcode();
Evan Cheng3f41d662007-10-08 22:16:29 +00004165 MVT::ValueType VT = Op.getValueType();
4166 bool IllegalFPCMov = false;
4167 if (VT == MVT::f32 && !X86ScalarSSEf32)
4168 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4169 else if (VT == MVT::f64 && !X86ScalarSSEf64)
4170 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
Dale Johannesenc274f542007-10-16 18:09:08 +00004171 else if (VT == MVT::f80)
4172 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
Evan Chenge5f62042007-09-29 00:00:36 +00004173 if ((Opc == X86ISD::CMP ||
4174 Opc == X86ISD::COMI ||
4175 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
Evan Cheng3f41d662007-10-08 22:16:29 +00004176 Cond = Cmp;
Evan Cheng0488db92007-09-25 01:57:46 +00004177 addTest = false;
4178 }
4179 }
4180
4181 if (addTest) {
4182 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Evan Cheng3f41d662007-10-08 22:16:29 +00004183 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
Evan Cheng0488db92007-09-25 01:57:46 +00004184 }
4185
4186 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4187 MVT::Flag);
4188 SmallVector<SDOperand, 4> Ops;
4189 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4190 // condition is true.
4191 Ops.push_back(Op.getOperand(2));
4192 Ops.push_back(Op.getOperand(1));
4193 Ops.push_back(CC);
4194 Ops.push_back(Cond);
Evan Chenge5f62042007-09-29 00:00:36 +00004195 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
Evan Cheng0488db92007-09-25 01:57:46 +00004196}
4197
Evan Cheng0db9fe62006-04-25 20:13:52 +00004198SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng734503b2006-09-11 02:19:56 +00004199 bool addTest = true;
4200 SDOperand Chain = Op.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004201 SDOperand Cond = Op.getOperand(1);
4202 SDOperand Dest = Op.getOperand(2);
4203 SDOperand CC;
Evan Cheng734503b2006-09-11 02:19:56 +00004204
Evan Cheng0db9fe62006-04-25 20:13:52 +00004205 if (Cond.getOpcode() == ISD::SETCC)
Evan Chenge5f62042007-09-29 00:00:36 +00004206 Cond = LowerSETCC(Cond, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004207
Evan Cheng3f41d662007-10-08 22:16:29 +00004208 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4209 // setting operand in place of the X86ISD::SETCC.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004210 if (Cond.getOpcode() == X86ISD::SETCC) {
Evan Cheng734503b2006-09-11 02:19:56 +00004211 CC = Cond.getOperand(0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004212
Evan Cheng734503b2006-09-11 02:19:56 +00004213 SDOperand Cmp = Cond.getOperand(1);
4214 unsigned Opc = Cmp.getOpcode();
Evan Chenge5f62042007-09-29 00:00:36 +00004215 if (Opc == X86ISD::CMP ||
4216 Opc == X86ISD::COMI ||
4217 Opc == X86ISD::UCOMI) {
Evan Cheng3f41d662007-10-08 22:16:29 +00004218 Cond = Cmp;
Evan Cheng0488db92007-09-25 01:57:46 +00004219 addTest = false;
4220 }
4221 }
4222
4223 if (addTest) {
4224 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
Evan Chenge5f62042007-09-29 00:00:36 +00004225 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
Evan Cheng0488db92007-09-25 01:57:46 +00004226 }
Evan Chenge5f62042007-09-29 00:00:36 +00004227 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
Evan Cheng0488db92007-09-25 01:57:46 +00004228 Chain, Op.getOperand(2), CC, Cond);
4229}
4230
Anton Korobeynikove060b532007-04-17 19:34:00 +00004231
4232// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4233// Calls to _alloca is needed to probe the stack when allocating more than 4k
4234// bytes in one go. Touching the stack at 4K increments is necessary to ensure
4235// that the guard pages used by the OS virtual memory manager are allocated in
4236// correct sequence.
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00004237SDOperand
4238X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4239 SelectionDAG &DAG) {
Anton Korobeynikove060b532007-04-17 19:34:00 +00004240 assert(Subtarget->isTargetCygMing() &&
4241 "This should be used only on Cygwin/Mingw targets");
4242
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004243 // Get the inputs.
4244 SDOperand Chain = Op.getOperand(0);
4245 SDOperand Size = Op.getOperand(1);
4246 // FIXME: Ensure alignment here
4247
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00004248 SDOperand Flag;
4249
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004250 MVT::ValueType IntPtr = getPointerTy();
4251 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004252
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00004253 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4254 Flag = Chain.getValue(1);
4255
4256 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4257 SDOperand Ops[] = { Chain,
4258 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4259 DAG.getRegister(X86::EAX, IntPtr),
4260 Flag };
4261 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
4262 Flag = Chain.getValue(1);
4263
4264 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004265
4266 std::vector<MVT::ValueType> Tys;
4267 Tys.push_back(SPTy);
4268 Tys.push_back(MVT::Other);
Anton Korobeynikov4304bcc2007-07-05 20:36:08 +00004269 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4270 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00004271}
4272
Evan Cheng0db9fe62006-04-25 20:13:52 +00004273SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4274 SDOperand InFlag(0, 0);
4275 SDOperand Chain = Op.getOperand(0);
4276 unsigned Align =
4277 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4278 if (Align == 0) Align = 1;
4279
4280 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
Rafael Espindola6b83b5d2007-08-27 10:18:20 +00004281 // If not DWORD aligned or size is more than the threshold, call memset.
Rafael Espindola44c82652007-08-27 17:48:26 +00004282 // The libc version is likely to be faster for these cases. It can use the
4283 // address value and run time information about the CPU.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004284 if ((Align & 3) != 0 ||
Rafael Espindolafc05f402007-10-31 11:52:06 +00004285 (I && I->getValue() > Subtarget->getMaxInlineSizeThreshold())) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004286 MVT::ValueType IntPtr = getPointerTy();
Owen Andersona69571c2006-05-03 01:29:57 +00004287 const Type *IntPtrTy = getTargetData()->getIntPtrType();
Reid Spencer47857812006-12-31 05:55:36 +00004288 TargetLowering::ArgListTy Args;
4289 TargetLowering::ArgListEntry Entry;
4290 Entry.Node = Op.getOperand(1);
4291 Entry.Ty = IntPtrTy;
Reid Spencer47857812006-12-31 05:55:36 +00004292 Args.push_back(Entry);
Reid Spenceraff93872007-01-03 17:24:59 +00004293 // Extend the unsigned i8 argument to be an int value for the call.
Reid Spencer47857812006-12-31 05:55:36 +00004294 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4295 Entry.Ty = IntPtrTy;
Reid Spencer47857812006-12-31 05:55:36 +00004296 Args.push_back(Entry);
4297 Entry.Node = Op.getOperand(3);
4298 Args.push_back(Entry);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004299 std::pair<SDOperand,SDOperand> CallResult =
Reid Spencer47857812006-12-31 05:55:36 +00004300 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
Evan Cheng0db9fe62006-04-25 20:13:52 +00004301 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
4302 return CallResult.second;
Evan Cheng48090aa2006-03-21 23:01:21 +00004303 }
Evan Chengb9df0ca2006-03-22 02:53:00 +00004304
Evan Cheng0db9fe62006-04-25 20:13:52 +00004305 MVT::ValueType AVT;
4306 SDOperand Count;
4307 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4308 unsigned BytesLeft = 0;
4309 bool TwoRepStos = false;
4310 if (ValC) {
4311 unsigned ValReg;
Evan Cheng25ab6902006-09-08 06:48:29 +00004312 uint64_t Val = ValC->getValue() & 255;
Evan Cheng5ced1d82006-04-06 23:23:56 +00004313
Evan Cheng0db9fe62006-04-25 20:13:52 +00004314 // If the value is a constant, then we can potentially use larger sets.
4315 switch (Align & 3) {
4316 case 2: // WORD aligned
4317 AVT = MVT::i16;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004318 ValReg = X86::AX;
Evan Cheng25ab6902006-09-08 06:48:29 +00004319 Val = (Val << 8) | Val;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004320 break;
Evan Cheng25ab6902006-09-08 06:48:29 +00004321 case 0: // DWORD aligned
Evan Cheng0db9fe62006-04-25 20:13:52 +00004322 AVT = MVT::i32;
Evan Cheng25ab6902006-09-08 06:48:29 +00004323 ValReg = X86::EAX;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004324 Val = (Val << 8) | Val;
4325 Val = (Val << 16) | Val;
Evan Cheng25ab6902006-09-08 06:48:29 +00004326 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4327 AVT = MVT::i64;
4328 ValReg = X86::RAX;
4329 Val = (Val << 32) | Val;
4330 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004331 break;
4332 default: // Byte aligned
4333 AVT = MVT::i8;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004334 ValReg = X86::AL;
Evan Cheng25ab6902006-09-08 06:48:29 +00004335 Count = Op.getOperand(3);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004336 break;
Evan Cheng80d428c2006-04-19 22:48:17 +00004337 }
4338
Evan Cheng25ab6902006-09-08 06:48:29 +00004339 if (AVT > MVT::i8) {
4340 if (I) {
4341 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4342 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4343 BytesLeft = I->getValue() % UBytes;
4344 } else {
4345 assert(AVT >= MVT::i32 &&
4346 "Do not use rep;stos if not at least DWORD aligned");
4347 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4348 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4349 TwoRepStos = true;
4350 }
4351 }
4352
Evan Cheng0db9fe62006-04-25 20:13:52 +00004353 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4354 InFlag);
4355 InFlag = Chain.getValue(1);
4356 } else {
4357 AVT = MVT::i8;
4358 Count = Op.getOperand(3);
4359 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4360 InFlag = Chain.getValue(1);
Evan Chengb9df0ca2006-03-22 02:53:00 +00004361 }
Evan Chengc78d3b42006-04-24 18:01:45 +00004362
Evan Cheng25ab6902006-09-08 06:48:29 +00004363 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4364 Count, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004365 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00004366 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4367 Op.getOperand(1), InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004368 InFlag = Chain.getValue(1);
Evan Chenga0b3afb2006-03-27 07:00:16 +00004369
Chris Lattnerd96d0722007-02-25 06:40:16 +00004370 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Chris Lattner5a88b832007-02-25 07:10:00 +00004371 SmallVector<SDOperand, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004372 Ops.push_back(Chain);
4373 Ops.push_back(DAG.getValueType(AVT));
4374 Ops.push_back(InFlag);
Evan Cheng311ace02006-08-11 07:35:45 +00004375 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
Evan Chengc78d3b42006-04-24 18:01:45 +00004376
Evan Cheng0db9fe62006-04-25 20:13:52 +00004377 if (TwoRepStos) {
4378 InFlag = Chain.getValue(1);
4379 Count = Op.getOperand(3);
4380 MVT::ValueType CVT = Count.getValueType();
4381 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
Evan Cheng25ab6902006-09-08 06:48:29 +00004382 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4383 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4384 Left, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004385 InFlag = Chain.getValue(1);
Chris Lattnerd96d0722007-02-25 06:40:16 +00004386 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004387 Ops.clear();
4388 Ops.push_back(Chain);
4389 Ops.push_back(DAG.getValueType(MVT::i8));
4390 Ops.push_back(InFlag);
Evan Cheng311ace02006-08-11 07:35:45 +00004391 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004392 } else if (BytesLeft) {
Evan Cheng25ab6902006-09-08 06:48:29 +00004393 // Issue stores for the last 1 - 7 bytes.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004394 SDOperand Value;
4395 unsigned Val = ValC->getValue() & 255;
4396 unsigned Offset = I->getValue() - BytesLeft;
4397 SDOperand DstAddr = Op.getOperand(1);
4398 MVT::ValueType AddrVT = DstAddr.getValueType();
Evan Cheng25ab6902006-09-08 06:48:29 +00004399 if (BytesLeft >= 4) {
4400 Val = (Val << 8) | Val;
4401 Val = (Val << 16) | Val;
4402 Value = DAG.getConstant(Val, MVT::i32);
Evan Cheng786225a2006-10-05 23:01:46 +00004403 Chain = DAG.getStore(Chain, Value,
4404 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4405 DAG.getConstant(Offset, AddrVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004406 NULL, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004407 BytesLeft -= 4;
4408 Offset += 4;
4409 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004410 if (BytesLeft >= 2) {
4411 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
Evan Cheng786225a2006-10-05 23:01:46 +00004412 Chain = DAG.getStore(Chain, Value,
4413 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4414 DAG.getConstant(Offset, AddrVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004415 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004416 BytesLeft -= 2;
4417 Offset += 2;
Evan Cheng386031a2006-03-24 07:29:27 +00004418 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004419 if (BytesLeft == 1) {
4420 Value = DAG.getConstant(Val, MVT::i8);
Evan Cheng786225a2006-10-05 23:01:46 +00004421 Chain = DAG.getStore(Chain, Value,
4422 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4423 DAG.getConstant(Offset, AddrVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004424 NULL, 0);
Evan Chengba05f722006-04-21 23:03:30 +00004425 }
Evan Cheng386031a2006-03-24 07:29:27 +00004426 }
Evan Cheng11e15b32006-04-03 20:53:28 +00004427
Evan Cheng0db9fe62006-04-25 20:13:52 +00004428 return Chain;
4429}
Evan Cheng11e15b32006-04-03 20:53:28 +00004430
Rafael Espindola068317b2007-09-28 12:53:01 +00004431SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
4432 SDOperand Dest,
4433 SDOperand Source,
4434 unsigned Size,
4435 unsigned Align,
4436 SelectionDAG &DAG) {
Evan Cheng0db9fe62006-04-25 20:13:52 +00004437 MVT::ValueType AVT;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004438 unsigned BytesLeft = 0;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004439 switch (Align & 3) {
4440 case 2: // WORD aligned
4441 AVT = MVT::i16;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004442 break;
Evan Cheng25ab6902006-09-08 06:48:29 +00004443 case 0: // DWORD aligned
Evan Cheng0db9fe62006-04-25 20:13:52 +00004444 AVT = MVT::i32;
Evan Cheng25ab6902006-09-08 06:48:29 +00004445 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4446 AVT = MVT::i64;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004447 break;
4448 default: // Byte aligned
4449 AVT = MVT::i8;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004450 break;
4451 }
4452
Rafael Espindola068317b2007-09-28 12:53:01 +00004453 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4454 SDOperand Count = DAG.getConstant(Size / UBytes, getPointerTy());
4455 BytesLeft = Size % UBytes;
Evan Cheng25ab6902006-09-08 06:48:29 +00004456
Evan Cheng0db9fe62006-04-25 20:13:52 +00004457 SDOperand InFlag(0, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004458 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4459 Count, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004460 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00004461 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
Rafael Espindola068317b2007-09-28 12:53:01 +00004462 Dest, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004463 InFlag = Chain.getValue(1);
Evan Cheng25ab6902006-09-08 06:48:29 +00004464 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
Rafael Espindola068317b2007-09-28 12:53:01 +00004465 Source, InFlag);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004466 InFlag = Chain.getValue(1);
4467
Chris Lattnerd96d0722007-02-25 06:40:16 +00004468 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Chris Lattner5a88b832007-02-25 07:10:00 +00004469 SmallVector<SDOperand, 8> Ops;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004470 Ops.push_back(Chain);
4471 Ops.push_back(DAG.getValueType(AVT));
4472 Ops.push_back(InFlag);
Evan Cheng311ace02006-08-11 07:35:45 +00004473 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004474
Rafael Espindola068317b2007-09-28 12:53:01 +00004475 if (BytesLeft) {
Evan Cheng25ab6902006-09-08 06:48:29 +00004476 // Issue loads and stores for the last 1 - 7 bytes.
Rafael Espindola068317b2007-09-28 12:53:01 +00004477 unsigned Offset = Size - BytesLeft;
4478 SDOperand DstAddr = Dest;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004479 MVT::ValueType DstVT = DstAddr.getValueType();
Rafael Espindola068317b2007-09-28 12:53:01 +00004480 SDOperand SrcAddr = Source;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004481 MVT::ValueType SrcVT = SrcAddr.getValueType();
4482 SDOperand Value;
Evan Cheng25ab6902006-09-08 06:48:29 +00004483 if (BytesLeft >= 4) {
4484 Value = DAG.getLoad(MVT::i32, Chain,
4485 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4486 DAG.getConstant(Offset, SrcVT)),
Evan Cheng466685d2006-10-09 20:57:25 +00004487 NULL, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004488 Chain = Value.getValue(1);
Evan Cheng786225a2006-10-05 23:01:46 +00004489 Chain = DAG.getStore(Chain, Value,
4490 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4491 DAG.getConstant(Offset, DstVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004492 NULL, 0);
Evan Cheng25ab6902006-09-08 06:48:29 +00004493 BytesLeft -= 4;
4494 Offset += 4;
4495 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004496 if (BytesLeft >= 2) {
4497 Value = DAG.getLoad(MVT::i16, Chain,
4498 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4499 DAG.getConstant(Offset, SrcVT)),
Evan Cheng466685d2006-10-09 20:57:25 +00004500 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004501 Chain = Value.getValue(1);
Evan Cheng786225a2006-10-05 23:01:46 +00004502 Chain = DAG.getStore(Chain, Value,
4503 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4504 DAG.getConstant(Offset, DstVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004505 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004506 BytesLeft -= 2;
4507 Offset += 2;
Evan Chengb067a1e2006-03-31 19:22:53 +00004508 }
4509
Evan Cheng0db9fe62006-04-25 20:13:52 +00004510 if (BytesLeft == 1) {
4511 Value = DAG.getLoad(MVT::i8, Chain,
4512 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4513 DAG.getConstant(Offset, SrcVT)),
Evan Cheng466685d2006-10-09 20:57:25 +00004514 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004515 Chain = Value.getValue(1);
Evan Cheng786225a2006-10-05 23:01:46 +00004516 Chain = DAG.getStore(Chain, Value,
4517 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4518 DAG.getConstant(Offset, DstVT)),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004519 NULL, 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00004520 }
Evan Chengb067a1e2006-03-31 19:22:53 +00004521 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00004522
4523 return Chain;
4524}
4525
Chris Lattner27a6c732007-11-24 07:07:01 +00004526/// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
4527SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
Chris Lattnerd96d0722007-02-25 06:40:16 +00004528 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
Chris Lattner27a6c732007-11-24 07:07:01 +00004529 SDOperand TheChain = N->getOperand(0);
4530 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
Evan Cheng3fa9dff2006-11-29 08:28:13 +00004531 if (Subtarget->is64Bit()) {
Chris Lattner27a6c732007-11-24 07:07:01 +00004532 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4533 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
4534 MVT::i64, rax.getValue(2));
4535 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
Evan Cheng3fa9dff2006-11-29 08:28:13 +00004536 DAG.getConstant(32, MVT::i8));
Chris Lattner5a88b832007-02-25 07:10:00 +00004537 SDOperand Ops[] = {
Chris Lattner27a6c732007-11-24 07:07:01 +00004538 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
Chris Lattner5a88b832007-02-25 07:10:00 +00004539 };
Chris Lattnerd96d0722007-02-25 06:40:16 +00004540
4541 Tys = DAG.getVTList(MVT::i64, MVT::Other);
Chris Lattner27a6c732007-11-24 07:07:01 +00004542 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
Evan Cheng3fa9dff2006-11-29 08:28:13 +00004543 }
Chris Lattner5a88b832007-02-25 07:10:00 +00004544
Chris Lattner27a6c732007-11-24 07:07:01 +00004545 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4546 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
4547 MVT::i32, eax.getValue(2));
4548 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
4549 SDOperand Ops[] = { eax, edx };
4550 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
4551
4552 // Use a MERGE_VALUES to return the value and chain.
4553 Ops[1] = edx.getValue(1);
4554 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4555 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
Evan Cheng0db9fe62006-04-25 20:13:52 +00004556}
4557
4558SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
Evan Cheng8b2794a2006-10-13 21:14:26 +00004559 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4560
Evan Cheng25ab6902006-09-08 06:48:29 +00004561 if (!Subtarget->is64Bit()) {
4562 // vastart just stores the address of the VarArgsFrameIndex slot into the
4563 // memory location argument.
4564 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Evan Cheng8b2794a2006-10-13 21:14:26 +00004565 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4566 SV->getOffset());
Evan Cheng25ab6902006-09-08 06:48:29 +00004567 }
4568
4569 // __va_list_tag:
4570 // gp_offset (0 - 6 * 8)
4571 // fp_offset (48 - 48 + 8 * 16)
4572 // overflow_arg_area (point to parameters coming in memory).
4573 // reg_save_area
Chris Lattner5a88b832007-02-25 07:10:00 +00004574 SmallVector<SDOperand, 8> MemOps;
Evan Cheng25ab6902006-09-08 06:48:29 +00004575 SDOperand FIN = Op.getOperand(1);
4576 // Store gp_offset
Evan Cheng786225a2006-10-05 23:01:46 +00004577 SDOperand Store = DAG.getStore(Op.getOperand(0),
4578 DAG.getConstant(VarArgsGPOffset, MVT::i32),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004579 FIN, SV->getValue(), SV->getOffset());
Evan Cheng25ab6902006-09-08 06:48:29 +00004580 MemOps.push_back(Store);
4581
4582 // Store fp_offset
4583 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4584 DAG.getConstant(4, getPointerTy()));
Evan Cheng786225a2006-10-05 23:01:46 +00004585 Store = DAG.getStore(Op.getOperand(0),
4586 DAG.getConstant(VarArgsFPOffset, MVT::i32),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004587 FIN, SV->getValue(), SV->getOffset());
Evan Cheng25ab6902006-09-08 06:48:29 +00004588 MemOps.push_back(Store);
4589
4590 // Store ptr to overflow_arg_area
4591 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4592 DAG.getConstant(4, getPointerTy()));
4593 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Evan Cheng8b2794a2006-10-13 21:14:26 +00004594 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4595 SV->getOffset());
Evan Cheng25ab6902006-09-08 06:48:29 +00004596 MemOps.push_back(Store);
4597
4598 // Store ptr to reg_save_area.
4599 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4600 DAG.getConstant(8, getPointerTy()));
4601 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
Evan Cheng8b2794a2006-10-13 21:14:26 +00004602 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4603 SV->getOffset());
Evan Cheng25ab6902006-09-08 06:48:29 +00004604 MemOps.push_back(Store);
4605 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
Evan Cheng0db9fe62006-04-25 20:13:52 +00004606}
4607
Evan Chengae642192007-03-02 23:16:35 +00004608SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4609 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4610 SDOperand Chain = Op.getOperand(0);
4611 SDOperand DstPtr = Op.getOperand(1);
4612 SDOperand SrcPtr = Op.getOperand(2);
4613 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4614 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4615
4616 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4617 SrcSV->getValue(), SrcSV->getOffset());
4618 Chain = SrcPtr.getValue(1);
4619 for (unsigned i = 0; i < 3; ++i) {
4620 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4621 SrcSV->getValue(), SrcSV->getOffset());
4622 Chain = Val.getValue(1);
4623 Chain = DAG.getStore(Chain, Val, DstPtr,
4624 DstSV->getValue(), DstSV->getOffset());
4625 if (i == 2)
4626 break;
4627 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4628 DAG.getConstant(8, getPointerTy()));
4629 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4630 DAG.getConstant(8, getPointerTy()));
4631 }
4632 return Chain;
4633}
4634
Evan Cheng0db9fe62006-04-25 20:13:52 +00004635SDOperand
4636X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4637 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4638 switch (IntNo) {
4639 default: return SDOperand(); // Don't custom lower most intrinsics.
Evan Cheng6be2c582006-04-05 23:38:46 +00004640 // Comparison intrinsics.
Evan Cheng0db9fe62006-04-25 20:13:52 +00004641 case Intrinsic::x86_sse_comieq_ss:
4642 case Intrinsic::x86_sse_comilt_ss:
4643 case Intrinsic::x86_sse_comile_ss:
4644 case Intrinsic::x86_sse_comigt_ss:
4645 case Intrinsic::x86_sse_comige_ss:
4646 case Intrinsic::x86_sse_comineq_ss:
4647 case Intrinsic::x86_sse_ucomieq_ss:
4648 case Intrinsic::x86_sse_ucomilt_ss:
4649 case Intrinsic::x86_sse_ucomile_ss:
4650 case Intrinsic::x86_sse_ucomigt_ss:
4651 case Intrinsic::x86_sse_ucomige_ss:
4652 case Intrinsic::x86_sse_ucomineq_ss:
4653 case Intrinsic::x86_sse2_comieq_sd:
4654 case Intrinsic::x86_sse2_comilt_sd:
4655 case Intrinsic::x86_sse2_comile_sd:
4656 case Intrinsic::x86_sse2_comigt_sd:
4657 case Intrinsic::x86_sse2_comige_sd:
4658 case Intrinsic::x86_sse2_comineq_sd:
4659 case Intrinsic::x86_sse2_ucomieq_sd:
4660 case Intrinsic::x86_sse2_ucomilt_sd:
4661 case Intrinsic::x86_sse2_ucomile_sd:
4662 case Intrinsic::x86_sse2_ucomigt_sd:
4663 case Intrinsic::x86_sse2_ucomige_sd:
4664 case Intrinsic::x86_sse2_ucomineq_sd: {
4665 unsigned Opc = 0;
4666 ISD::CondCode CC = ISD::SETCC_INVALID;
4667 switch (IntNo) {
4668 default: break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00004669 case Intrinsic::x86_sse_comieq_ss:
4670 case Intrinsic::x86_sse2_comieq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004671 Opc = X86ISD::COMI;
4672 CC = ISD::SETEQ;
4673 break;
Evan Cheng6be2c582006-04-05 23:38:46 +00004674 case Intrinsic::x86_sse_comilt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004675 case Intrinsic::x86_sse2_comilt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004676 Opc = X86ISD::COMI;
4677 CC = ISD::SETLT;
4678 break;
4679 case Intrinsic::x86_sse_comile_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004680 case Intrinsic::x86_sse2_comile_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004681 Opc = X86ISD::COMI;
4682 CC = ISD::SETLE;
4683 break;
4684 case Intrinsic::x86_sse_comigt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004685 case Intrinsic::x86_sse2_comigt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004686 Opc = X86ISD::COMI;
4687 CC = ISD::SETGT;
4688 break;
4689 case Intrinsic::x86_sse_comige_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004690 case Intrinsic::x86_sse2_comige_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004691 Opc = X86ISD::COMI;
4692 CC = ISD::SETGE;
4693 break;
4694 case Intrinsic::x86_sse_comineq_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004695 case Intrinsic::x86_sse2_comineq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004696 Opc = X86ISD::COMI;
4697 CC = ISD::SETNE;
4698 break;
4699 case Intrinsic::x86_sse_ucomieq_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004700 case Intrinsic::x86_sse2_ucomieq_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004701 Opc = X86ISD::UCOMI;
4702 CC = ISD::SETEQ;
4703 break;
4704 case Intrinsic::x86_sse_ucomilt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004705 case Intrinsic::x86_sse2_ucomilt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004706 Opc = X86ISD::UCOMI;
4707 CC = ISD::SETLT;
4708 break;
4709 case Intrinsic::x86_sse_ucomile_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004710 case Intrinsic::x86_sse2_ucomile_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004711 Opc = X86ISD::UCOMI;
4712 CC = ISD::SETLE;
4713 break;
4714 case Intrinsic::x86_sse_ucomigt_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004715 case Intrinsic::x86_sse2_ucomigt_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004716 Opc = X86ISD::UCOMI;
4717 CC = ISD::SETGT;
4718 break;
4719 case Intrinsic::x86_sse_ucomige_ss:
Evan Cheng6be2c582006-04-05 23:38:46 +00004720 case Intrinsic::x86_sse2_ucomige_sd:
Evan Cheng0db9fe62006-04-25 20:13:52 +00004721 Opc = X86ISD::UCOMI;
4722 CC = ISD::SETGE;
4723 break;
4724 case Intrinsic::x86_sse_ucomineq_ss:
4725 case Intrinsic::x86_sse2_ucomineq_sd:
4726 Opc = X86ISD::UCOMI;
4727 CC = ISD::SETNE;
4728 break;
Evan Cheng6be2c582006-04-05 23:38:46 +00004729 }
Evan Cheng734503b2006-09-11 02:19:56 +00004730
Evan Cheng0db9fe62006-04-25 20:13:52 +00004731 unsigned X86CC;
Chris Lattnerf9570512006-09-13 03:22:10 +00004732 SDOperand LHS = Op.getOperand(1);
4733 SDOperand RHS = Op.getOperand(2);
4734 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
Evan Cheng734503b2006-09-11 02:19:56 +00004735
Evan Chenge5f62042007-09-29 00:00:36 +00004736 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
4737 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
4738 DAG.getConstant(X86CC, MVT::i8), Cond);
4739 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
Evan Cheng6be2c582006-04-05 23:38:46 +00004740 }
Evan Cheng38bcbaf2005-12-23 07:31:11 +00004741 }
Chris Lattnerdbdbf0c2005-11-15 00:40:23 +00004742}
Evan Cheng72261582005-12-20 06:22:03 +00004743
Nate Begemanbcc5f362007-01-29 22:58:52 +00004744SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4745 // Depths > 0 not supported yet!
4746 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4747 return SDOperand();
4748
4749 // Just load the return address
4750 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4751 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4752}
4753
4754SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4755 // Depths > 0 not supported yet!
4756 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4757 return SDOperand();
4758
4759 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4760 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4761 DAG.getConstant(4, getPointerTy()));
4762}
4763
Anton Korobeynikov2365f512007-07-14 14:06:15 +00004764SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
4765 SelectionDAG &DAG) {
4766 // Is not yet supported on x86-64
4767 if (Subtarget->is64Bit())
4768 return SDOperand();
4769
4770 return DAG.getConstant(8, getPointerTy());
4771}
4772
4773SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
4774{
4775 assert(!Subtarget->is64Bit() &&
4776 "Lowering of eh_return builtin is not supported yet on x86-64");
4777
4778 MachineFunction &MF = DAG.getMachineFunction();
4779 SDOperand Chain = Op.getOperand(0);
4780 SDOperand Offset = Op.getOperand(1);
4781 SDOperand Handler = Op.getOperand(2);
4782
4783 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
4784 getPointerTy());
4785
4786 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
4787 DAG.getConstant(-4UL, getPointerTy()));
4788 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
4789 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
4790 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
Chris Lattner84bc5422007-12-31 04:13:23 +00004791 MF.getRegInfo().addLiveOut(X86::ECX);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00004792
4793 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
4794 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
4795}
4796
Duncan Sandsb116fac2007-07-27 20:02:49 +00004797SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
4798 SelectionDAG &DAG) {
4799 SDOperand Root = Op.getOperand(0);
4800 SDOperand Trmp = Op.getOperand(1); // trampoline
4801 SDOperand FPtr = Op.getOperand(2); // nested function
4802 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
4803
4804 SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4));
4805
4806 if (Subtarget->is64Bit()) {
4807 return SDOperand(); // not yet supported
4808 } else {
4809 Function *Func = (Function *)
4810 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
4811 unsigned CC = Func->getCallingConv();
Duncan Sandsee465742007-08-29 19:01:20 +00004812 unsigned NestReg;
Duncan Sandsb116fac2007-07-27 20:02:49 +00004813
4814 switch (CC) {
4815 default:
4816 assert(0 && "Unsupported calling convention");
4817 case CallingConv::C:
Duncan Sandsb116fac2007-07-27 20:02:49 +00004818 case CallingConv::X86_StdCall: {
4819 // Pass 'nest' parameter in ECX.
4820 // Must be kept in sync with X86CallingConv.td
Duncan Sandsee465742007-08-29 19:01:20 +00004821 NestReg = X86::ECX;
Duncan Sandsb116fac2007-07-27 20:02:49 +00004822
4823 // Check that ECX wasn't needed by an 'inreg' parameter.
4824 const FunctionType *FTy = Func->getFunctionType();
Duncan Sandsdc024672007-11-27 13:23:08 +00004825 const ParamAttrsList *Attrs = Func->getParamAttrs();
Duncan Sandsb116fac2007-07-27 20:02:49 +00004826
4827 if (Attrs && !Func->isVarArg()) {
4828 unsigned InRegCount = 0;
4829 unsigned Idx = 1;
4830
4831 for (FunctionType::param_iterator I = FTy->param_begin(),
4832 E = FTy->param_end(); I != E; ++I, ++Idx)
4833 if (Attrs->paramHasAttr(Idx, ParamAttr::InReg))
4834 // FIXME: should only count parameters that are lowered to integers.
4835 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
4836
4837 if (InRegCount > 2) {
4838 cerr << "Nest register in use - reduce number of inreg parameters!\n";
4839 abort();
4840 }
4841 }
4842 break;
4843 }
4844 case CallingConv::X86_FastCall:
4845 // Pass 'nest' parameter in EAX.
4846 // Must be kept in sync with X86CallingConv.td
Duncan Sandsee465742007-08-29 19:01:20 +00004847 NestReg = X86::EAX;
Duncan Sandsb116fac2007-07-27 20:02:49 +00004848 break;
4849 }
4850
Duncan Sandsee465742007-08-29 19:01:20 +00004851 const X86InstrInfo *TII =
4852 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
4853
Duncan Sandsb116fac2007-07-27 20:02:49 +00004854 SDOperand OutChains[4];
4855 SDOperand Addr, Disp;
4856
4857 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
4858 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
4859
Duncan Sandsee465742007-08-29 19:01:20 +00004860 unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
Chris Lattner48b01332007-12-16 20:26:54 +00004861 unsigned char N86Reg = ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
Duncan Sandsee465742007-08-29 19:01:20 +00004862 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Duncan Sandsb116fac2007-07-27 20:02:49 +00004863 Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
4864
4865 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
4866 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4867 TrmpSV->getOffset() + 1, false, 1);
4868
Duncan Sandsee465742007-08-29 19:01:20 +00004869 unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
Duncan Sandsb116fac2007-07-27 20:02:49 +00004870 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
4871 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
4872 TrmpSV->getValue() + 5, TrmpSV->getOffset());
4873
4874 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
4875 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(),
4876 TrmpSV->getOffset() + 6, false, 1);
4877
Duncan Sandsf7331b32007-09-11 14:10:23 +00004878 SDOperand Ops[] =
4879 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
4880 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
Duncan Sandsb116fac2007-07-27 20:02:49 +00004881 }
4882}
4883
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00004884SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) {
4885 /*
4886 The rounding mode is in bits 11:10 of FPSR, and has the following
4887 settings:
4888 00 Round to nearest
4889 01 Round to -inf
4890 10 Round to +inf
4891 11 Round to 0
4892
4893 FLT_ROUNDS, on the other hand, expects the following:
4894 -1 Undefined
4895 0 Round to 0
4896 1 Round to nearest
4897 2 Round to +inf
4898 3 Round to -inf
4899
4900 To perform the conversion, we do:
4901 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
4902 */
4903
4904 MachineFunction &MF = DAG.getMachineFunction();
4905 const TargetMachine &TM = MF.getTarget();
4906 const TargetFrameInfo &TFI = *TM.getFrameInfo();
4907 unsigned StackAlignment = TFI.getStackAlignment();
4908 MVT::ValueType VT = Op.getValueType();
4909
4910 // Save FP Control Word to stack slot
4911 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
4912 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4913
4914 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
4915 DAG.getEntryNode(), StackSlot);
4916
4917 // Load FP Control Word from stack slot
4918 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
4919
4920 // Transform as necessary
4921 SDOperand CWD1 =
4922 DAG.getNode(ISD::SRL, MVT::i16,
4923 DAG.getNode(ISD::AND, MVT::i16,
4924 CWD, DAG.getConstant(0x800, MVT::i16)),
4925 DAG.getConstant(11, MVT::i8));
4926 SDOperand CWD2 =
4927 DAG.getNode(ISD::SRL, MVT::i16,
4928 DAG.getNode(ISD::AND, MVT::i16,
4929 CWD, DAG.getConstant(0x400, MVT::i16)),
4930 DAG.getConstant(9, MVT::i8));
4931
4932 SDOperand RetVal =
4933 DAG.getNode(ISD::AND, MVT::i16,
4934 DAG.getNode(ISD::ADD, MVT::i16,
4935 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
4936 DAG.getConstant(1, MVT::i16)),
4937 DAG.getConstant(3, MVT::i16));
4938
4939
4940 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
4941 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
4942}
4943
Evan Cheng18efe262007-12-14 02:13:44 +00004944SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
4945 MVT::ValueType VT = Op.getValueType();
4946 MVT::ValueType OpVT = VT;
4947 unsigned NumBits = MVT::getSizeInBits(VT);
4948
4949 Op = Op.getOperand(0);
4950 if (VT == MVT::i8) {
Evan Cheng152804e2007-12-14 08:30:15 +00004951 // Zero extend to i32 since there is not an i8 bsr.
Evan Cheng18efe262007-12-14 02:13:44 +00004952 OpVT = MVT::i32;
4953 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
4954 }
Evan Cheng18efe262007-12-14 02:13:44 +00004955
Evan Cheng152804e2007-12-14 08:30:15 +00004956 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
4957 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
4958 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
4959
4960 // If src is zero (i.e. bsr sets ZF), returns NumBits.
4961 SmallVector<SDOperand, 4> Ops;
4962 Ops.push_back(Op);
4963 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
4964 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
4965 Ops.push_back(Op.getValue(1));
4966 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
4967
4968 // Finally xor with NumBits-1.
4969 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
4970
Evan Cheng18efe262007-12-14 02:13:44 +00004971 if (VT == MVT::i8)
4972 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
4973 return Op;
4974}
4975
4976SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
4977 MVT::ValueType VT = Op.getValueType();
4978 MVT::ValueType OpVT = VT;
Evan Cheng152804e2007-12-14 08:30:15 +00004979 unsigned NumBits = MVT::getSizeInBits(VT);
Evan Cheng18efe262007-12-14 02:13:44 +00004980
4981 Op = Op.getOperand(0);
4982 if (VT == MVT::i8) {
4983 OpVT = MVT::i32;
4984 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
4985 }
Evan Cheng152804e2007-12-14 08:30:15 +00004986
4987 // Issue a bsf (scan bits forward) which also sets EFLAGS.
4988 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
4989 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
4990
4991 // If src is zero (i.e. bsf sets ZF), returns NumBits.
4992 SmallVector<SDOperand, 4> Ops;
4993 Ops.push_back(Op);
4994 Ops.push_back(DAG.getConstant(NumBits, OpVT));
4995 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
4996 Ops.push_back(Op.getValue(1));
4997 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
4998
Evan Cheng18efe262007-12-14 02:13:44 +00004999 if (VT == MVT::i8)
5000 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5001 return Op;
5002}
5003
Evan Cheng0db9fe62006-04-25 20:13:52 +00005004/// LowerOperation - Provide custom lowering hooks for some operations.
5005///
5006SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5007 switch (Op.getOpcode()) {
5008 default: assert(0 && "Should not custom lower this!");
5009 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5010 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5011 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5012 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5013 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5014 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5015 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00005016 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005017 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5018 case ISD::SHL_PARTS:
5019 case ISD::SRA_PARTS:
5020 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5021 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5022 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5023 case ISD::FABS: return LowerFABS(Op, DAG);
5024 case ISD::FNEG: return LowerFNEG(Op, DAG);
Evan Cheng68c47cb2007-01-05 07:55:56 +00005025 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Evan Chenge5f62042007-09-29 00:00:36 +00005026 case ISD::SETCC: return LowerSETCC(Op, DAG);
5027 case ISD::SELECT: return LowerSELECT(Op, DAG);
5028 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005029 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Evan Cheng32fe1032006-05-25 00:59:30 +00005030 case ISD::CALL: return LowerCALL(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005031 case ISD::RET: return LowerRET(Op, DAG);
Evan Cheng1bc78042006-04-26 01:20:17 +00005032 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005033 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
5034 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005035 case ISD::VASTART: return LowerVASTART(Op, DAG);
Evan Chengae642192007-03-02 23:16:35 +00005036 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005037 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
Nate Begemanbcc5f362007-01-29 22:58:52 +00005038 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5039 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005040 case ISD::FRAME_TO_ARGS_OFFSET:
5041 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +00005042 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005043 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
Duncan Sandsb116fac2007-07-27 20:02:49 +00005044 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005045 case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
Evan Cheng18efe262007-12-14 02:13:44 +00005046 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5047 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
Chris Lattner27a6c732007-11-24 07:07:01 +00005048
5049 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5050 case ISD::READCYCLECOUNTER:
5051 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
Evan Cheng0db9fe62006-04-25 20:13:52 +00005052 }
Chris Lattner27a6c732007-11-24 07:07:01 +00005053}
5054
5055/// ExpandOperation - Provide custom lowering hooks for expanding operations.
5056SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
5057 switch (N->getOpcode()) {
5058 default: assert(0 && "Should not custom lower this!");
5059 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5060 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5061 }
Evan Cheng0db9fe62006-04-25 20:13:52 +00005062}
5063
Evan Cheng72261582005-12-20 06:22:03 +00005064const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5065 switch (Opcode) {
5066 default: return NULL;
Evan Cheng18efe262007-12-14 02:13:44 +00005067 case X86ISD::BSF: return "X86ISD::BSF";
5068 case X86ISD::BSR: return "X86ISD::BSR";
Evan Chenge3413162006-01-09 18:33:28 +00005069 case X86ISD::SHLD: return "X86ISD::SHLD";
5070 case X86ISD::SHRD: return "X86ISD::SHRD";
Evan Chengef6ffb12006-01-31 03:14:29 +00005071 case X86ISD::FAND: return "X86ISD::FAND";
Evan Cheng68c47cb2007-01-05 07:55:56 +00005072 case X86ISD::FOR: return "X86ISD::FOR";
Evan Cheng223547a2006-01-31 22:28:30 +00005073 case X86ISD::FXOR: return "X86ISD::FXOR";
Evan Cheng68c47cb2007-01-05 07:55:56 +00005074 case X86ISD::FSRL: return "X86ISD::FSRL";
Evan Chenga3195e82006-01-12 22:54:21 +00005075 case X86ISD::FILD: return "X86ISD::FILD";
Evan Chenge3de85b2006-02-04 02:20:30 +00005076 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
Evan Cheng72261582005-12-20 06:22:03 +00005077 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5078 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5079 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
Evan Chengb077b842005-12-21 02:39:21 +00005080 case X86ISD::FLD: return "X86ISD::FLD";
Evan Chengd90eb7f2006-01-05 00:27:02 +00005081 case X86ISD::FST: return "X86ISD::FST";
5082 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
Evan Chengb077b842005-12-21 02:39:21 +00005083 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
Evan Cheng72261582005-12-20 06:22:03 +00005084 case X86ISD::CALL: return "X86ISD::CALL";
5085 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5086 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5087 case X86ISD::CMP: return "X86ISD::CMP";
Evan Cheng6be2c582006-04-05 23:38:46 +00005088 case X86ISD::COMI: return "X86ISD::COMI";
5089 case X86ISD::UCOMI: return "X86ISD::UCOMI";
Evan Chengd5781fc2005-12-21 20:21:51 +00005090 case X86ISD::SETCC: return "X86ISD::SETCC";
Evan Cheng72261582005-12-20 06:22:03 +00005091 case X86ISD::CMOV: return "X86ISD::CMOV";
5092 case X86ISD::BRCOND: return "X86ISD::BRCOND";
Evan Chengb077b842005-12-21 02:39:21 +00005093 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
Evan Cheng8df346b2006-03-04 01:12:00 +00005094 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5095 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
Evan Cheng7ccced62006-02-18 00:15:05 +00005096 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
Evan Cheng020d2e82006-02-23 20:41:18 +00005097 case X86ISD::Wrapper: return "X86ISD::Wrapper";
Evan Chengbc4832b2006-03-24 23:15:12 +00005098 case X86ISD::S2VEC: return "X86ISD::S2VEC";
Evan Chengb067a1e2006-03-31 19:22:53 +00005099 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
Evan Cheng653159f2006-03-31 21:55:24 +00005100 case X86ISD::PINSRW: return "X86ISD::PINSRW";
Evan Cheng8ca29322006-11-10 21:43:37 +00005101 case X86ISD::FMAX: return "X86ISD::FMAX";
5102 case X86ISD::FMIN: return "X86ISD::FMIN";
Dan Gohman20382522007-07-10 00:05:58 +00005103 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5104 case X86ISD::FRCP: return "X86ISD::FRCP";
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00005105 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5106 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
Anton Korobeynikov2365f512007-07-14 14:06:15 +00005107 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005108 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
Anton Korobeynikov45b22fa2007-11-16 01:31:51 +00005109 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
Evan Cheng72261582005-12-20 06:22:03 +00005110 }
5111}
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005112
Chris Lattnerc9addb72007-03-30 23:15:24 +00005113// isLegalAddressingMode - Return true if the addressing mode represented
5114// by AM is legal for this target, for a load/store of the specified type.
5115bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5116 const Type *Ty) const {
5117 // X86 supports extremely general addressing modes.
5118
5119 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5120 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5121 return false;
5122
5123 if (AM.BaseGV) {
Evan Cheng52787842007-08-01 23:46:47 +00005124 // We can only fold this if we don't need an extra load.
Chris Lattnerc9addb72007-03-30 23:15:24 +00005125 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5126 return false;
Evan Cheng52787842007-08-01 23:46:47 +00005127
5128 // X86-64 only supports addr of globals in small code model.
5129 if (Subtarget->is64Bit()) {
5130 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5131 return false;
5132 // If lower 4G is not available, then we must use rip-relative addressing.
5133 if (AM.BaseOffs || AM.Scale > 1)
5134 return false;
5135 }
Chris Lattnerc9addb72007-03-30 23:15:24 +00005136 }
5137
5138 switch (AM.Scale) {
5139 case 0:
5140 case 1:
5141 case 2:
5142 case 4:
5143 case 8:
5144 // These scales always work.
5145 break;
5146 case 3:
5147 case 5:
5148 case 9:
5149 // These scales are formed with basereg+scalereg. Only accept if there is
5150 // no basereg yet.
5151 if (AM.HasBaseReg)
5152 return false;
5153 break;
5154 default: // Other stuff never works.
5155 return false;
5156 }
5157
5158 return true;
5159}
5160
5161
Evan Cheng2bd122c2007-10-26 01:56:11 +00005162bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5163 if (!Ty1->isInteger() || !Ty2->isInteger())
5164 return false;
Evan Chenge127a732007-10-29 07:57:50 +00005165 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5166 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5167 if (NumBits1 <= NumBits2)
5168 return false;
5169 return Subtarget->is64Bit() || NumBits1 < 64;
Evan Cheng2bd122c2007-10-26 01:56:11 +00005170}
5171
Evan Cheng3c3ddb32007-10-29 19:58:20 +00005172bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1,
5173 MVT::ValueType VT2) const {
5174 if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2))
5175 return false;
5176 unsigned NumBits1 = MVT::getSizeInBits(VT1);
5177 unsigned NumBits2 = MVT::getSizeInBits(VT2);
5178 if (NumBits1 <= NumBits2)
5179 return false;
5180 return Subtarget->is64Bit() || NumBits1 < 64;
5181}
Evan Cheng2bd122c2007-10-26 01:56:11 +00005182
Evan Cheng60c07e12006-07-05 22:17:51 +00005183/// isShuffleMaskLegal - Targets can use this to indicate that they only
5184/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5185/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5186/// are assumed to be legal.
5187bool
5188X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
5189 // Only do shuffles on 128-bit vector types for now.
5190 if (MVT::getSizeInBits(VT) == 64) return false;
5191 return (Mask.Val->getNumOperands() <= 4 ||
Evan Cheng49892af2007-06-19 00:02:56 +00005192 isIdentityMask(Mask.Val) ||
5193 isIdentityMask(Mask.Val, true) ||
Evan Cheng60c07e12006-07-05 22:17:51 +00005194 isSplatMask(Mask.Val) ||
5195 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5196 X86::isUNPCKLMask(Mask.Val) ||
Evan Cheng49892af2007-06-19 00:02:56 +00005197 X86::isUNPCKHMask(Mask.Val) ||
Evan Cheng60c07e12006-07-05 22:17:51 +00005198 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
Evan Cheng49892af2007-06-19 00:02:56 +00005199 X86::isUNPCKH_v_undef_Mask(Mask.Val));
Evan Cheng60c07e12006-07-05 22:17:51 +00005200}
5201
5202bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
5203 MVT::ValueType EVT,
5204 SelectionDAG &DAG) const {
5205 unsigned NumElts = BVOps.size();
5206 // Only do shuffles on 128-bit vector types for now.
5207 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
5208 if (NumElts == 2) return true;
5209 if (NumElts == 4) {
Chris Lattner5a88b832007-02-25 07:10:00 +00005210 return (isMOVLMask(&BVOps[0], 4) ||
5211 isCommutedMOVL(&BVOps[0], 4, true) ||
5212 isSHUFPMask(&BVOps[0], 4) ||
5213 isCommutedSHUFP(&BVOps[0], 4));
Evan Cheng60c07e12006-07-05 22:17:51 +00005214 }
5215 return false;
5216}
5217
5218//===----------------------------------------------------------------------===//
5219// X86 Scheduler Hooks
5220//===----------------------------------------------------------------------===//
5221
5222MachineBasicBlock *
5223X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
5224 MachineBasicBlock *BB) {
Evan Chengc0f64ff2006-11-27 23:37:22 +00005225 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Evan Cheng60c07e12006-07-05 22:17:51 +00005226 switch (MI->getOpcode()) {
5227 default: assert(false && "Unexpected instr type to insert");
5228 case X86::CMOV_FR32:
5229 case X86::CMOV_FR64:
5230 case X86::CMOV_V4F32:
5231 case X86::CMOV_V2F64:
Evan Chenge5f62042007-09-29 00:00:36 +00005232 case X86::CMOV_V2I64: {
Evan Cheng60c07e12006-07-05 22:17:51 +00005233 // To "insert" a SELECT_CC instruction, we actually have to insert the
5234 // diamond control-flow pattern. The incoming instruction knows the
5235 // destination vreg to set, the condition code register to branch on, the
5236 // true/false values to select between, and a branch opcode to use.
5237 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5238 ilist<MachineBasicBlock>::iterator It = BB;
5239 ++It;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005240
Evan Cheng60c07e12006-07-05 22:17:51 +00005241 // thisMBB:
5242 // ...
5243 // TrueVal = ...
5244 // cmpTY ccX, r1, r2
5245 // bCC copy1MBB
5246 // fallthrough --> copy0MBB
5247 MachineBasicBlock *thisMBB = BB;
5248 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
5249 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005250 unsigned Opc =
Chris Lattner7fbe9722006-10-20 17:42:20 +00005251 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
Evan Chengc0f64ff2006-11-27 23:37:22 +00005252 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
Evan Cheng60c07e12006-07-05 22:17:51 +00005253 MachineFunction *F = BB->getParent();
5254 F->getBasicBlockList().insert(It, copy0MBB);
5255 F->getBasicBlockList().insert(It, sinkMBB);
5256 // Update machine-CFG edges by first adding all successors of the current
5257 // block to the new block which will contain the Phi node for the select.
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005258 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
Evan Cheng60c07e12006-07-05 22:17:51 +00005259 e = BB->succ_end(); i != e; ++i)
5260 sinkMBB->addSuccessor(*i);
5261 // Next, remove all successors of the current block, and add the true
5262 // and fallthrough blocks as its successors.
5263 while(!BB->succ_empty())
5264 BB->removeSuccessor(BB->succ_begin());
5265 BB->addSuccessor(copy0MBB);
5266 BB->addSuccessor(sinkMBB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005267
Evan Cheng60c07e12006-07-05 22:17:51 +00005268 // copy0MBB:
5269 // %FalseValue = ...
5270 // # fallthrough to sinkMBB
5271 BB = copy0MBB;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005272
Evan Cheng60c07e12006-07-05 22:17:51 +00005273 // Update machine-CFG edges
5274 BB->addSuccessor(sinkMBB);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005275
Evan Cheng60c07e12006-07-05 22:17:51 +00005276 // sinkMBB:
5277 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5278 // ...
5279 BB = sinkMBB;
Evan Chengc0f64ff2006-11-27 23:37:22 +00005280 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
Evan Cheng60c07e12006-07-05 22:17:51 +00005281 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5282 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5283
5284 delete MI; // The pseudo instruction is gone now.
5285 return BB;
5286 }
5287
Dale Johannesen849f2142007-07-03 00:53:03 +00005288 case X86::FP32_TO_INT16_IN_MEM:
5289 case X86::FP32_TO_INT32_IN_MEM:
5290 case X86::FP32_TO_INT64_IN_MEM:
5291 case X86::FP64_TO_INT16_IN_MEM:
5292 case X86::FP64_TO_INT32_IN_MEM:
Dale Johannesena996d522007-08-07 01:17:37 +00005293 case X86::FP64_TO_INT64_IN_MEM:
5294 case X86::FP80_TO_INT16_IN_MEM:
5295 case X86::FP80_TO_INT32_IN_MEM:
5296 case X86::FP80_TO_INT64_IN_MEM: {
Evan Cheng60c07e12006-07-05 22:17:51 +00005297 // Change the floating point control register to use "round towards zero"
5298 // mode when truncating to an integer value.
5299 MachineFunction *F = BB->getParent();
5300 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
Evan Chengc0f64ff2006-11-27 23:37:22 +00005301 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00005302
5303 // Load the old value of the high byte of the control word...
5304 unsigned OldCW =
Chris Lattner84bc5422007-12-31 04:13:23 +00005305 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
Evan Chengc0f64ff2006-11-27 23:37:22 +00005306 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00005307
5308 // Set the high part to be round to zero...
Evan Chengc0f64ff2006-11-27 23:37:22 +00005309 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
5310 .addImm(0xC7F);
Evan Cheng60c07e12006-07-05 22:17:51 +00005311
5312 // Reload the modified control word now...
Evan Chengc0f64ff2006-11-27 23:37:22 +00005313 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00005314
5315 // Restore the memory image of control word to original value
Evan Chengc0f64ff2006-11-27 23:37:22 +00005316 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
5317 .addReg(OldCW);
Evan Cheng60c07e12006-07-05 22:17:51 +00005318
5319 // Get the X86 opcode to use.
5320 unsigned Opc;
5321 switch (MI->getOpcode()) {
5322 default: assert(0 && "illegal opcode!");
Dale Johannesene377d4d2007-07-04 21:07:47 +00005323 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
5324 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
5325 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
5326 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
5327 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
5328 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
Dale Johannesena996d522007-08-07 01:17:37 +00005329 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
5330 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
5331 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
Evan Cheng60c07e12006-07-05 22:17:51 +00005332 }
5333
5334 X86AddressMode AM;
5335 MachineOperand &Op = MI->getOperand(0);
5336 if (Op.isRegister()) {
5337 AM.BaseType = X86AddressMode::RegBase;
5338 AM.Base.Reg = Op.getReg();
5339 } else {
5340 AM.BaseType = X86AddressMode::FrameIndexBase;
Chris Lattner8aa797a2007-12-30 23:10:15 +00005341 AM.Base.FrameIndex = Op.getIndex();
Evan Cheng60c07e12006-07-05 22:17:51 +00005342 }
5343 Op = MI->getOperand(1);
5344 if (Op.isImmediate())
Chris Lattner7fbe9722006-10-20 17:42:20 +00005345 AM.Scale = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00005346 Op = MI->getOperand(2);
5347 if (Op.isImmediate())
Chris Lattner7fbe9722006-10-20 17:42:20 +00005348 AM.IndexReg = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00005349 Op = MI->getOperand(3);
5350 if (Op.isGlobalAddress()) {
5351 AM.GV = Op.getGlobal();
5352 } else {
Chris Lattner7fbe9722006-10-20 17:42:20 +00005353 AM.Disp = Op.getImm();
Evan Cheng60c07e12006-07-05 22:17:51 +00005354 }
Evan Chengc0f64ff2006-11-27 23:37:22 +00005355 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
5356 .addReg(MI->getOperand(4).getReg());
Evan Cheng60c07e12006-07-05 22:17:51 +00005357
5358 // Reload the original control word now.
Evan Chengc0f64ff2006-11-27 23:37:22 +00005359 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
Evan Cheng60c07e12006-07-05 22:17:51 +00005360
5361 delete MI; // The pseudo instruction is gone now.
5362 return BB;
5363 }
5364 }
5365}
5366
5367//===----------------------------------------------------------------------===//
5368// X86 Optimization Hooks
5369//===----------------------------------------------------------------------===//
5370
Nate Begeman368e18d2006-02-16 21:11:51 +00005371void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
5372 uint64_t Mask,
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005373 uint64_t &KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +00005374 uint64_t &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +00005375 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +00005376 unsigned Depth) const {
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005377 unsigned Opc = Op.getOpcode();
Evan Cheng865f0602006-04-05 06:11:20 +00005378 assert((Opc >= ISD::BUILTIN_OP_END ||
5379 Opc == ISD::INTRINSIC_WO_CHAIN ||
5380 Opc == ISD::INTRINSIC_W_CHAIN ||
5381 Opc == ISD::INTRINSIC_VOID) &&
5382 "Should use MaskedValueIsZero if you don't know whether Op"
5383 " is a target node!");
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005384
Evan Cheng865f0602006-04-05 06:11:20 +00005385 KnownZero = KnownOne = 0; // Don't know anything.
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005386 switch (Opc) {
Evan Cheng865f0602006-04-05 06:11:20 +00005387 default: break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005388 case X86ISD::SETCC:
Nate Begeman368e18d2006-02-16 21:11:51 +00005389 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
5390 break;
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005391 }
Evan Cheng3a03ebb2005-12-21 23:05:39 +00005392}
Chris Lattner259e97c2006-01-31 19:43:35 +00005393
Evan Cheng206ee9d2006-07-07 08:33:52 +00005394/// getShuffleScalarElt - Returns the scalar element that will make up the ith
5395/// element of the result of the vector shuffle.
5396static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
5397 MVT::ValueType VT = N->getValueType(0);
5398 SDOperand PermMask = N->getOperand(2);
5399 unsigned NumElems = PermMask.getNumOperands();
5400 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
5401 i %= NumElems;
5402 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5403 return (i == 0)
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00005404 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
Evan Cheng206ee9d2006-07-07 08:33:52 +00005405 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
5406 SDOperand Idx = PermMask.getOperand(i);
5407 if (Idx.getOpcode() == ISD::UNDEF)
Dan Gohman51eaa862007-06-14 22:58:02 +00005408 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
Evan Cheng206ee9d2006-07-07 08:33:52 +00005409 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
5410 }
5411 return SDOperand();
5412}
5413
5414/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
5415/// node is a GlobalAddress + an offset.
5416static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
Evan Cheng0085a282006-11-30 21:55:46 +00005417 unsigned Opc = N->getOpcode();
Evan Cheng19f2ffc2006-12-05 04:01:03 +00005418 if (Opc == X86ISD::Wrapper) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005419 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
5420 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
5421 return true;
5422 }
Evan Cheng0085a282006-11-30 21:55:46 +00005423 } else if (Opc == ISD::ADD) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005424 SDOperand N1 = N->getOperand(0);
5425 SDOperand N2 = N->getOperand(1);
5426 if (isGAPlusOffset(N1.Val, GA, Offset)) {
5427 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
5428 if (V) {
5429 Offset += V->getSignExtended();
5430 return true;
5431 }
5432 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
5433 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
5434 if (V) {
5435 Offset += V->getSignExtended();
5436 return true;
5437 }
5438 }
5439 }
5440 return false;
5441}
5442
5443/// isConsecutiveLoad - Returns true if N is loading from an address of Base
5444/// + Dist * Size.
5445static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
5446 MachineFrameInfo *MFI) {
5447 if (N->getOperand(0).Val != Base->getOperand(0).Val)
5448 return false;
5449
5450 SDOperand Loc = N->getOperand(1);
5451 SDOperand BaseLoc = Base->getOperand(1);
5452 if (Loc.getOpcode() == ISD::FrameIndex) {
5453 if (BaseLoc.getOpcode() != ISD::FrameIndex)
5454 return false;
Dan Gohman275769a2007-07-23 20:24:29 +00005455 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
5456 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
Evan Cheng206ee9d2006-07-07 08:33:52 +00005457 int FS = MFI->getObjectSize(FI);
5458 int BFS = MFI->getObjectSize(BFI);
5459 if (FS != BFS || FS != Size) return false;
5460 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
5461 } else {
5462 GlobalValue *GV1 = NULL;
5463 GlobalValue *GV2 = NULL;
5464 int64_t Offset1 = 0;
5465 int64_t Offset2 = 0;
5466 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
5467 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
5468 if (isGA1 && isGA2 && GV1 == GV2)
5469 return Offset1 == (Offset2 + Dist*Size);
5470 }
5471
5472 return false;
5473}
5474
Evan Cheng1e60c092006-07-10 21:37:44 +00005475static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
5476 const X86Subtarget *Subtarget) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005477 GlobalValue *GV;
5478 int64_t Offset;
5479 if (isGAPlusOffset(Base, GV, Offset))
5480 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
5481 else {
5482 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
Dan Gohman275769a2007-07-23 20:24:29 +00005483 int BFI = cast<FrameIndexSDNode>(Base)->getIndex();
Evan Cheng1e60c092006-07-10 21:37:44 +00005484 if (BFI < 0)
5485 // Fixed objects do not specify alignment, however the offsets are known.
5486 return ((Subtarget->getStackAlignment() % 16) == 0 &&
5487 (MFI->getObjectOffset(BFI) % 16) == 0);
5488 else
5489 return MFI->getObjectAlignment(BFI) >= 16;
Evan Cheng206ee9d2006-07-07 08:33:52 +00005490 }
5491 return false;
5492}
5493
5494
5495/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5496/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5497/// if the load addresses are consecutive, non-overlapping, and in the right
5498/// order.
Evan Cheng1e60c092006-07-10 21:37:44 +00005499static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5500 const X86Subtarget *Subtarget) {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005501 MachineFunction &MF = DAG.getMachineFunction();
5502 MachineFrameInfo *MFI = MF.getFrameInfo();
5503 MVT::ValueType VT = N->getValueType(0);
Dan Gohman51eaa862007-06-14 22:58:02 +00005504 MVT::ValueType EVT = MVT::getVectorElementType(VT);
Evan Cheng206ee9d2006-07-07 08:33:52 +00005505 SDOperand PermMask = N->getOperand(2);
5506 int NumElems = (int)PermMask.getNumOperands();
5507 SDNode *Base = NULL;
5508 for (int i = 0; i < NumElems; ++i) {
5509 SDOperand Idx = PermMask.getOperand(i);
5510 if (Idx.getOpcode() == ISD::UNDEF) {
5511 if (!Base) return SDOperand();
5512 } else {
5513 SDOperand Arg =
5514 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
Evan Cheng466685d2006-10-09 20:57:25 +00005515 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
Evan Cheng206ee9d2006-07-07 08:33:52 +00005516 return SDOperand();
5517 if (!Base)
5518 Base = Arg.Val;
5519 else if (!isConsecutiveLoad(Arg.Val, Base,
5520 i, MVT::getSizeInBits(EVT)/8,MFI))
5521 return SDOperand();
5522 }
5523 }
5524
Evan Cheng1e60c092006-07-10 21:37:44 +00005525 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
Dan Gohmand3006222007-07-27 17:16:43 +00005526 LoadSDNode *LD = cast<LoadSDNode>(Base);
Evan Cheng466685d2006-10-09 20:57:25 +00005527 if (isAlign16) {
Evan Cheng466685d2006-10-09 20:57:25 +00005528 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
Dan Gohmand3006222007-07-27 17:16:43 +00005529 LD->getSrcValueOffset(), LD->isVolatile());
Evan Cheng466685d2006-10-09 20:57:25 +00005530 } else {
Dan Gohmand3006222007-07-27 17:16:43 +00005531 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5532 LD->getSrcValueOffset(), LD->isVolatile(),
5533 LD->getAlignment());
Evan Cheng311ace02006-08-11 07:35:45 +00005534 }
Evan Cheng206ee9d2006-07-07 08:33:52 +00005535}
5536
Chris Lattner83e6c992006-10-04 06:57:07 +00005537/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
5538static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
5539 const X86Subtarget *Subtarget) {
5540 SDOperand Cond = N->getOperand(0);
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005541
Chris Lattner83e6c992006-10-04 06:57:07 +00005542 // If we have SSE[12] support, try to form min/max nodes.
5543 if (Subtarget->hasSSE2() &&
5544 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
5545 if (Cond.getOpcode() == ISD::SETCC) {
5546 // Get the LHS/RHS of the select.
5547 SDOperand LHS = N->getOperand(1);
5548 SDOperand RHS = N->getOperand(2);
5549 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005550
Evan Cheng8ca29322006-11-10 21:43:37 +00005551 unsigned Opcode = 0;
Chris Lattner83e6c992006-10-04 06:57:07 +00005552 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
Chris Lattner1907a7b2006-10-05 04:11:26 +00005553 switch (CC) {
5554 default: break;
5555 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
5556 case ISD::SETULE:
5557 case ISD::SETLE:
5558 if (!UnsafeFPMath) break;
5559 // FALL THROUGH.
5560 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
5561 case ISD::SETLT:
Evan Cheng8ca29322006-11-10 21:43:37 +00005562 Opcode = X86ISD::FMIN;
Chris Lattner1907a7b2006-10-05 04:11:26 +00005563 break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005564
Chris Lattner1907a7b2006-10-05 04:11:26 +00005565 case ISD::SETOGT: // (X > Y) ? X : Y -> max
5566 case ISD::SETUGT:
5567 case ISD::SETGT:
5568 if (!UnsafeFPMath) break;
5569 // FALL THROUGH.
5570 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
5571 case ISD::SETGE:
Evan Cheng8ca29322006-11-10 21:43:37 +00005572 Opcode = X86ISD::FMAX;
Chris Lattner1907a7b2006-10-05 04:11:26 +00005573 break;
5574 }
Chris Lattner83e6c992006-10-04 06:57:07 +00005575 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
Chris Lattner1907a7b2006-10-05 04:11:26 +00005576 switch (CC) {
5577 default: break;
5578 case ISD::SETOGT: // (X > Y) ? Y : X -> min
5579 case ISD::SETUGT:
5580 case ISD::SETGT:
5581 if (!UnsafeFPMath) break;
5582 // FALL THROUGH.
5583 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
5584 case ISD::SETGE:
Evan Cheng8ca29322006-11-10 21:43:37 +00005585 Opcode = X86ISD::FMIN;
Chris Lattner1907a7b2006-10-05 04:11:26 +00005586 break;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005587
Chris Lattner1907a7b2006-10-05 04:11:26 +00005588 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
5589 case ISD::SETULE:
5590 case ISD::SETLE:
5591 if (!UnsafeFPMath) break;
5592 // FALL THROUGH.
5593 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
5594 case ISD::SETLT:
Evan Cheng8ca29322006-11-10 21:43:37 +00005595 Opcode = X86ISD::FMAX;
Chris Lattner1907a7b2006-10-05 04:11:26 +00005596 break;
5597 }
Chris Lattner83e6c992006-10-04 06:57:07 +00005598 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005599
Evan Cheng8ca29322006-11-10 21:43:37 +00005600 if (Opcode)
5601 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
Chris Lattner83e6c992006-10-04 06:57:07 +00005602 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005603
Chris Lattner83e6c992006-10-04 06:57:07 +00005604 }
5605
5606 return SDOperand();
5607}
5608
5609
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005610SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
Evan Cheng206ee9d2006-07-07 08:33:52 +00005611 DAGCombinerInfo &DCI) const {
Evan Cheng206ee9d2006-07-07 08:33:52 +00005612 SelectionDAG &DAG = DCI.DAG;
5613 switch (N->getOpcode()) {
5614 default: break;
5615 case ISD::VECTOR_SHUFFLE:
Evan Cheng1e60c092006-07-10 21:37:44 +00005616 return PerformShuffleCombine(N, DAG, Subtarget);
Chris Lattner83e6c992006-10-04 06:57:07 +00005617 case ISD::SELECT:
5618 return PerformSELECTCombine(N, DAG, Subtarget);
Evan Cheng206ee9d2006-07-07 08:33:52 +00005619 }
5620
5621 return SDOperand();
5622}
5623
Evan Cheng60c07e12006-07-05 22:17:51 +00005624//===----------------------------------------------------------------------===//
5625// X86 Inline Assembly Support
5626//===----------------------------------------------------------------------===//
5627
Chris Lattnerf4dff842006-07-11 02:54:03 +00005628/// getConstraintType - Given a constraint letter, return the type of
5629/// constraint it is for this target.
5630X86TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +00005631X86TargetLowering::getConstraintType(const std::string &Constraint) const {
5632 if (Constraint.size() == 1) {
5633 switch (Constraint[0]) {
5634 case 'A':
5635 case 'r':
5636 case 'R':
5637 case 'l':
5638 case 'q':
5639 case 'Q':
5640 case 'x':
5641 case 'Y':
5642 return C_RegisterClass;
5643 default:
5644 break;
5645 }
Chris Lattnerf4dff842006-07-11 02:54:03 +00005646 }
Chris Lattner4234f572007-03-25 02:14:49 +00005647 return TargetLowering::getConstraintType(Constraint);
Chris Lattnerf4dff842006-07-11 02:54:03 +00005648}
5649
Chris Lattner48884cd2007-08-25 00:47:38 +00005650/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5651/// vector. If it is invalid, don't add anything to Ops.
5652void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
5653 char Constraint,
5654 std::vector<SDOperand>&Ops,
5655 SelectionDAG &DAG) {
5656 SDOperand Result(0, 0);
5657
Chris Lattner22aaf1d2006-10-31 20:13:11 +00005658 switch (Constraint) {
5659 default: break;
Devang Patel84f7fd22007-03-17 00:13:28 +00005660 case 'I':
Chris Lattner188b9fe2007-03-25 01:57:35 +00005661 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Chris Lattner48884cd2007-08-25 00:47:38 +00005662 if (C->getValue() <= 31) {
5663 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5664 break;
5665 }
Devang Patel84f7fd22007-03-17 00:13:28 +00005666 }
Chris Lattner48884cd2007-08-25 00:47:38 +00005667 return;
Chris Lattner188b9fe2007-03-25 01:57:35 +00005668 case 'N':
5669 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
Chris Lattner48884cd2007-08-25 00:47:38 +00005670 if (C->getValue() <= 255) {
5671 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5672 break;
5673 }
Chris Lattner188b9fe2007-03-25 01:57:35 +00005674 }
Chris Lattner48884cd2007-08-25 00:47:38 +00005675 return;
Chris Lattnerdc43a882007-05-03 16:52:29 +00005676 case 'i': {
Chris Lattner22aaf1d2006-10-31 20:13:11 +00005677 // Literal immediates are always ok.
Chris Lattner48884cd2007-08-25 00:47:38 +00005678 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
5679 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
5680 break;
5681 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005682
Chris Lattnerdc43a882007-05-03 16:52:29 +00005683 // If we are in non-pic codegen mode, we allow the address of a global (with
5684 // an optional displacement) to be used with 'i'.
5685 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
5686 int64_t Offset = 0;
5687
5688 // Match either (GA) or (GA+C)
5689 if (GA) {
5690 Offset = GA->getOffset();
5691 } else if (Op.getOpcode() == ISD::ADD) {
5692 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5693 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5694 if (C && GA) {
5695 Offset = GA->getOffset()+C->getValue();
5696 } else {
5697 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5698 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5699 if (C && GA)
5700 Offset = GA->getOffset()+C->getValue();
5701 else
5702 C = 0, GA = 0;
5703 }
5704 }
5705
5706 if (GA) {
5707 // If addressing this global requires a load (e.g. in PIC mode), we can't
5708 // match.
5709 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
5710 false))
Chris Lattner48884cd2007-08-25 00:47:38 +00005711 return;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005712
Chris Lattnerdc43a882007-05-03 16:52:29 +00005713 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5714 Offset);
Chris Lattner48884cd2007-08-25 00:47:38 +00005715 Result = Op;
5716 break;
Chris Lattner22aaf1d2006-10-31 20:13:11 +00005717 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005718
Chris Lattner22aaf1d2006-10-31 20:13:11 +00005719 // Otherwise, not valid for this mode.
Chris Lattner48884cd2007-08-25 00:47:38 +00005720 return;
Chris Lattner22aaf1d2006-10-31 20:13:11 +00005721 }
Chris Lattnerdc43a882007-05-03 16:52:29 +00005722 }
Chris Lattner48884cd2007-08-25 00:47:38 +00005723
5724 if (Result.Val) {
5725 Ops.push_back(Result);
5726 return;
5727 }
5728 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
Chris Lattner22aaf1d2006-10-31 20:13:11 +00005729}
5730
Chris Lattner259e97c2006-01-31 19:43:35 +00005731std::vector<unsigned> X86TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +00005732getRegClassForInlineAsmConstraint(const std::string &Constraint,
5733 MVT::ValueType VT) const {
Chris Lattner259e97c2006-01-31 19:43:35 +00005734 if (Constraint.size() == 1) {
5735 // FIXME: not handling fp-stack yet!
Chris Lattner259e97c2006-01-31 19:43:35 +00005736 switch (Constraint[0]) { // GCC X86 Constraint Letters
Chris Lattnerf4dff842006-07-11 02:54:03 +00005737 default: break; // Unknown constraint letter
5738 case 'A': // EAX/EDX
5739 if (VT == MVT::i32 || VT == MVT::i64)
5740 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5741 break;
Chris Lattner259e97c2006-01-31 19:43:35 +00005742 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5743 case 'Q': // Q_REGS
Chris Lattner80a7ecc2006-05-06 00:29:37 +00005744 if (VT == MVT::i32)
5745 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5746 else if (VT == MVT::i16)
5747 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5748 else if (VT == MVT::i8)
Evan Cheng12914382007-08-13 23:27:11 +00005749 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
Chris Lattner03e6c702007-11-04 06:51:12 +00005750 else if (VT == MVT::i64)
5751 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
5752 break;
Chris Lattner259e97c2006-01-31 19:43:35 +00005753 }
5754 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005755
Chris Lattner1efa40f2006-02-22 00:56:39 +00005756 return std::vector<unsigned>();
Chris Lattner259e97c2006-01-31 19:43:35 +00005757}
Chris Lattnerf76d1802006-07-31 23:26:50 +00005758
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005759std::pair<unsigned, const TargetRegisterClass*>
Chris Lattnerf76d1802006-07-31 23:26:50 +00005760X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5761 MVT::ValueType VT) const {
Chris Lattnerad043e82007-04-09 05:11:28 +00005762 // First, see if this is a constraint that directly corresponds to an LLVM
5763 // register class.
5764 if (Constraint.size() == 1) {
5765 // GCC Constraint Letters
5766 switch (Constraint[0]) {
5767 default: break;
Chris Lattner0f65cad2007-04-09 05:49:22 +00005768 case 'r': // GENERAL_REGS
5769 case 'R': // LEGACY_REGS
5770 case 'l': // INDEX_REGS
5771 if (VT == MVT::i64 && Subtarget->is64Bit())
5772 return std::make_pair(0U, X86::GR64RegisterClass);
5773 if (VT == MVT::i32)
5774 return std::make_pair(0U, X86::GR32RegisterClass);
5775 else if (VT == MVT::i16)
5776 return std::make_pair(0U, X86::GR16RegisterClass);
5777 else if (VT == MVT::i8)
5778 return std::make_pair(0U, X86::GR8RegisterClass);
5779 break;
Chris Lattner6c284d72007-04-12 04:14:49 +00005780 case 'y': // MMX_REGS if MMX allowed.
5781 if (!Subtarget->hasMMX()) break;
5782 return std::make_pair(0U, X86::VR64RegisterClass);
5783 break;
Chris Lattner0f65cad2007-04-09 05:49:22 +00005784 case 'Y': // SSE_REGS if SSE2 allowed
5785 if (!Subtarget->hasSSE2()) break;
5786 // FALL THROUGH.
5787 case 'x': // SSE_REGS if SSE1 allowed
5788 if (!Subtarget->hasSSE1()) break;
5789
5790 switch (VT) {
5791 default: break;
5792 // Scalar SSE types.
5793 case MVT::f32:
5794 case MVT::i32:
Chris Lattnerad043e82007-04-09 05:11:28 +00005795 return std::make_pair(0U, X86::FR32RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00005796 case MVT::f64:
5797 case MVT::i64:
Chris Lattnerad043e82007-04-09 05:11:28 +00005798 return std::make_pair(0U, X86::FR64RegisterClass);
Chris Lattner0f65cad2007-04-09 05:49:22 +00005799 // Vector types.
Chris Lattner0f65cad2007-04-09 05:49:22 +00005800 case MVT::v16i8:
5801 case MVT::v8i16:
5802 case MVT::v4i32:
5803 case MVT::v2i64:
5804 case MVT::v4f32:
5805 case MVT::v2f64:
5806 return std::make_pair(0U, X86::VR128RegisterClass);
5807 }
Chris Lattnerad043e82007-04-09 05:11:28 +00005808 break;
5809 }
5810 }
5811
Chris Lattnerf76d1802006-07-31 23:26:50 +00005812 // Use the default implementation in TargetLowering to convert the register
5813 // constraint into a member of a register class.
5814 std::pair<unsigned, const TargetRegisterClass*> Res;
5815 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
Chris Lattner1a60aa72006-10-31 19:42:44 +00005816
5817 // Not found as a standard register?
5818 if (Res.second == 0) {
5819 // GCC calls "st(0)" just plain "st".
5820 if (StringsEqualNoCase("{st}", Constraint)) {
5821 Res.first = X86::ST0;
Chris Lattner9b4baf12007-09-24 05:27:37 +00005822 Res.second = X86::RFP80RegisterClass;
Chris Lattner1a60aa72006-10-31 19:42:44 +00005823 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005824
Chris Lattner1a60aa72006-10-31 19:42:44 +00005825 return Res;
5826 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005827
Chris Lattnerf76d1802006-07-31 23:26:50 +00005828 // Otherwise, check to see if this is a register class of the wrong value
5829 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5830 // turn into {ax},{dx}.
5831 if (Res.second->hasType(VT))
5832 return Res; // Correct type already, nothing to do.
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005833
Chris Lattnerf76d1802006-07-31 23:26:50 +00005834 // All of the single-register GCC register classes map their values onto
5835 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5836 // really want an 8-bit or 32-bit register, map to the appropriate register
5837 // class and return the appropriate register.
5838 if (Res.second != X86::GR16RegisterClass)
5839 return Res;
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005840
Chris Lattnerf76d1802006-07-31 23:26:50 +00005841 if (VT == MVT::i8) {
5842 unsigned DestReg = 0;
5843 switch (Res.first) {
5844 default: break;
5845 case X86::AX: DestReg = X86::AL; break;
5846 case X86::DX: DestReg = X86::DL; break;
5847 case X86::CX: DestReg = X86::CL; break;
5848 case X86::BX: DestReg = X86::BL; break;
5849 }
5850 if (DestReg) {
5851 Res.first = DestReg;
5852 Res.second = Res.second = X86::GR8RegisterClass;
5853 }
5854 } else if (VT == MVT::i32) {
5855 unsigned DestReg = 0;
5856 switch (Res.first) {
5857 default: break;
5858 case X86::AX: DestReg = X86::EAX; break;
5859 case X86::DX: DestReg = X86::EDX; break;
5860 case X86::CX: DestReg = X86::ECX; break;
5861 case X86::BX: DestReg = X86::EBX; break;
5862 case X86::SI: DestReg = X86::ESI; break;
5863 case X86::DI: DestReg = X86::EDI; break;
5864 case X86::BP: DestReg = X86::EBP; break;
5865 case X86::SP: DestReg = X86::ESP; break;
5866 }
5867 if (DestReg) {
5868 Res.first = DestReg;
5869 Res.second = Res.second = X86::GR32RegisterClass;
5870 }
Evan Cheng25ab6902006-09-08 06:48:29 +00005871 } else if (VT == MVT::i64) {
5872 unsigned DestReg = 0;
5873 switch (Res.first) {
5874 default: break;
5875 case X86::AX: DestReg = X86::RAX; break;
5876 case X86::DX: DestReg = X86::RDX; break;
5877 case X86::CX: DestReg = X86::RCX; break;
5878 case X86::BX: DestReg = X86::RBX; break;
5879 case X86::SI: DestReg = X86::RSI; break;
5880 case X86::DI: DestReg = X86::RDI; break;
5881 case X86::BP: DestReg = X86::RBP; break;
5882 case X86::SP: DestReg = X86::RSP; break;
5883 }
5884 if (DestReg) {
5885 Res.first = DestReg;
5886 Res.second = Res.second = X86::GR64RegisterClass;
5887 }
Chris Lattnerf76d1802006-07-31 23:26:50 +00005888 }
Anton Korobeynikov12c49af2006-11-21 00:01:06 +00005889
Chris Lattnerf76d1802006-07-31 23:26:50 +00005890 return Res;
5891}