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gerrit-public.fairphone.software / platform / external / llvm / 244006db5c4d48878dc5fdc86976acdaff96cfaa / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 6927d2d053ce2e022c7659829e1be38af4216362 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]16#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]17#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]18#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]22#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]39 ARMDisassembler(const MCSubtargetInfo &STI) :
40 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]41 }
42
43 ~ARMDisassembler() {
44 }
45
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
48 uint64_t &size,
49 const MemoryObject &region,
50 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]51 raw_ostream &vStream,
52 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]53
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62 /// Constructor - Initializes the disassembler.
63 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]64 ThumbDisassembler(const MCSubtargetInfo &STI) :
65 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]66 }
67
68 ~ThumbDisassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
74 const MemoryObject &region,
75 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]78
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
81private:
82 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]83 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]84 void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]88static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]89 switch (In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
92 return true;
93 case MCDisassembler::SoftFail:
94 Out = In;
95 return true;
96 case MCDisassembler::Fail:
97 Out = In;
98 return false;
99 }
100 return false;
101}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]102
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]103
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]120 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]122 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]129
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]148 unsigned Insn,
149 uint64_t Address,
150 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]154 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 unsigned Insn,
162 uint64_t Adddress,
163 const void *Decoder);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]182static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]184static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]186static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]188static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]190static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]192static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]194static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]196static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]198static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]200static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]202static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]204static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]210static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]212static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]214static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]216static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]218static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]224static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]226static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]228static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]230static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]232static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]234static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]236static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]238static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]240static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]242static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]244static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]246static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]252static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
253 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]255static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]257static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]259static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]261static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]277static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]278 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]279static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]287static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]293static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]294 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]295static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
296 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]297static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]299static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]301static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]303static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]304 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]305static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]306 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]307static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
309static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
310 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]311static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]313static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]315static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
316 uint64_t Address, const void *Decoder);
317
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]318
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]319
320#include "ARMGenDisassemblerTables.inc"
321#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]322#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]323
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]324static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
325 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]326}
327
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]328static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
329 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]330}
331
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]332EDInstInfo *ARMDisassembler::getEDInfo() const {
333 return instInfoARM;
334}
335
336EDInstInfo *ThumbDisassembler::getEDInfo() const {
337 return instInfoARM;
338}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]340DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]341 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]342 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]343 raw_ostream &os,
344 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]345 CommentStream = &cs;
346
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 uint8_t bytes[4];
348
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]349 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
350 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
351
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]352 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]353 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
354 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]355 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]356 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357
358 // Encoded as a small-endian 32-bit word in the stream.
359 uint32_t insn = (bytes[3] << 24) |
360 (bytes[2] << 16) |
361 (bytes[1] << 8) |
362 (bytes[0] << 0);
363
364 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]365 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]366 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]368 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 }
370
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]371 // VFP and NEON instructions, similarly, are shared between ARM
372 // and Thumb modes.
373 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]374 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]375 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]377 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]378 }
379
380 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]381 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]382 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]383 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]384 // Add a fake predicate operand, because we share these instruction
385 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]386 if (!DecodePredicateOperand(MI, 0xE, Address, this))
387 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]388 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]389 }
390
391 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]392 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]393 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]394 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]395 // Add a fake predicate operand, because we share these instruction
396 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]397 if (!DecodePredicateOperand(MI, 0xE, Address, this))
398 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]399 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]400 }
401
402 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]403 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]404 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]405 Size = 4;
406 // Add a fake predicate operand, because we share these instruction
407 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]408 if (!DecodePredicateOperand(MI, 0xE, Address, this))
409 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]410 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]411 }
412
413 MI.clear();
414
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]415 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]416 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]417}
418
419namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]420extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]421}
422
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]423/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
424/// immediate Value in the MCInst. The immediate Value has had any PC
425/// adjustment made by the caller. If the instruction is a branch instruction
426/// then isBranch is true, else false. If the getOpInfo() function was set as
427/// part of the setupForSymbolicDisassembly() call then that function is called
428/// to get any symbolic information at the Address for this instruction. If
429/// that returns non-zero then the symbolic information it returns is used to
430/// create an MCExpr and that is added as an operand to the MCInst. If
431/// getOpInfo() returns zero and isBranch is true then a symbol look up for
432/// Value is done and if a symbol is found an MCExpr is created with that, else
433/// an MCExpr with Value is created. This function returns true if it adds an
434/// operand to the MCInst and false otherwise.
435static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
436 bool isBranch, uint64_t InstSize,
437 MCInst &MI, const void *Decoder) {
438 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
439 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
440 if (!getOpInfo)
441 return false;
442
443 struct LLVMOpInfo1 SymbolicOp;
444 SymbolicOp.Value = Value;
445 void *DisInfo = Dis->getDisInfoBlock();
446 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
447 if (isBranch) {
448 LLVMSymbolLookupCallback SymbolLookUp =
449 Dis->getLLVMSymbolLookupCallback();
450 if (SymbolLookUp) {
451 uint64_t ReferenceType;
452 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
453 const char *ReferenceName;
454 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
455 &ReferenceName);
456 if (Name) {
457 SymbolicOp.AddSymbol.Name = Name;
458 SymbolicOp.AddSymbol.Present = true;
459 SymbolicOp.Value = 0;
460 }
461 else {
462 SymbolicOp.Value = Value;
463 }
464 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
465 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
466 }
467 else {
468 return false;
469 }
470 }
471 else {
472 return false;
473 }
474 }
475
476 MCContext *Ctx = Dis->getMCContext();
477 const MCExpr *Add = NULL;
478 if (SymbolicOp.AddSymbol.Present) {
479 if (SymbolicOp.AddSymbol.Name) {
480 StringRef Name(SymbolicOp.AddSymbol.Name);
481 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
482 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
483 } else {
484 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
485 }
486 }
487
488 const MCExpr *Sub = NULL;
489 if (SymbolicOp.SubtractSymbol.Present) {
490 if (SymbolicOp.SubtractSymbol.Name) {
491 StringRef Name(SymbolicOp.SubtractSymbol.Name);
492 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
493 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
494 } else {
495 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
496 }
497 }
498
499 const MCExpr *Off = NULL;
500 if (SymbolicOp.Value != 0)
501 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
502
503 const MCExpr *Expr;
504 if (Sub) {
505 const MCExpr *LHS;
506 if (Add)
507 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
508 else
509 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
510 if (Off != 0)
511 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
512 else
513 Expr = LHS;
514 } else if (Add) {
515 if (Off != 0)
516 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
517 else
518 Expr = Add;
519 } else {
520 if (Off != 0)
521 Expr = Off;
522 else
523 Expr = MCConstantExpr::Create(0, *Ctx);
524 }
525
526 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
529 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
530 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
531 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]532 else
Richard Trieu8223e452011-10-14 20:50:26 +0000[diff] [blame]533 assert(0 && "bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]534
535 return true;
536}
537
538/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
539/// referenced by a load instruction with the base register that is the Pc.
540/// These can often be values in a literal pool near the Address of the
541/// instruction. The Address of the instruction and its immediate Value are
542/// used as a possible literal pool entry. The SymbolLookUp call back will
543/// return the name of a symbol referenced by the the literal pool's entry if
544/// the referenced address is that of a symbol. Or it will return a pointer to
545/// a literal 'C' string if the referenced address of the literal pool's entry
546/// is an address into a section with 'C' string literals.
547static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
548 const void *Decoder) {
549 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
550 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
551 if (SymbolLookUp) {
552 void *DisInfo = Dis->getDisInfoBlock();
553 uint64_t ReferenceType;
554 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
555 const char *ReferenceName;
556 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
557 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
558 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
559 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
560 }
561}
562
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]563// Thumb1 instructions don't have explicit S bits. Rather, they
564// implicitly set CPSR. Since it's not represented in the encoding, the
565// auto-generated decoder won't inject the CPSR operand. We need to fix
566// that as a post-pass.
567static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
568 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]569 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]570 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]571 for (unsigned i = 0; i < NumOps; ++i, ++I) {
572 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]573 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]574 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]575 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
576 return;
577 }
578 }
579
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]580 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]581}
582
583// Most Thumb instructions don't have explicit predicates in the
584// encoding, but rather get their predicates from IT context. We need
585// to fix up the predicate operands using this context information as a
586// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]587MCDisassembler::DecodeStatus
588ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]589 MCDisassembler::DecodeStatus S = Success;
590
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]591 // A few instructions actually have predicates encoded in them. Don't
592 // try to overwrite it if we're seeing one of those.
593 switch (MI.getOpcode()) {
594 case ARM::tBcc:
595 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]596 case ARM::tCBZ:
597 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]598 case ARM::tCPS:
599 case ARM::t2CPS3p:
600 case ARM::t2CPS2p:
601 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]602 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]603 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]604 // Some instructions (mostly conditional branches) are not
605 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]606 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]607 S = SoftFail;
608 else
609 return Success;
610 break;
611 case ARM::tB:
612 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]613 case ARM::t2TBB:
614 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]615 // Some instructions (mostly unconditional branches) can
616 // only appears at the end of, or outside of, an IT.
617 if (ITBlock.size() > 1)
618 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]619 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]620 default:
621 break;
622 }
623
624 // If we're in an IT block, base the predicate on that. Otherwise,
625 // assume a predicate of AL.
626 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]627 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]628 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]629 if (CC == 0xF)
630 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]631 ITBlock.pop_back();
632 } else
633 CC = ARMCC::AL;
634
635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]636 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]638 for (unsigned i = 0; i < NumOps; ++i, ++I) {
639 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]640 if (OpInfo[i].isPredicate()) {
641 I = MI.insert(I, MCOperand::CreateImm(CC));
642 ++I;
643 if (CC == ARMCC::AL)
644 MI.insert(I, MCOperand::CreateReg(0));
645 else
646 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]647 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]648 }
649 }
650
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]651 I = MI.insert(I, MCOperand::CreateImm(CC));
652 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]653 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]654 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]655 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]656 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]657
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]658 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]659}
660
661// Thumb VFP instructions are a special case. Because we share their
662// encodings between ARM and Thumb modes, and they are predicable in ARM
663// mode, the auto-generated decoder will give them an (incorrect)
664// predicate operand. We need to rewrite these operands based on the IT
665// context as a post-pass.
666void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
667 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]668 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]669 CC = ITBlock.back();
670 ITBlock.pop_back();
671 } else
672 CC = ARMCC::AL;
673
674 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
675 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]676 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
677 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]678 if (OpInfo[i].isPredicate() ) {
679 I->setImm(CC);
680 ++I;
681 if (CC == ARMCC::AL)
682 I->setReg(0);
683 else
684 I->setReg(ARM::CPSR);
685 return;
686 }
687 }
688}
689
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]690DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]691 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]692 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]693 raw_ostream &os,
694 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]695 CommentStream = &cs;
696
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]697 uint8_t bytes[4];
698
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]699 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
700 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
701
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]702 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]703 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
704 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]705 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]706 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]707
708 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]709 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]710 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]711 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]712 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]713 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]714 }
715
716 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]717 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]718 if (result) {
719 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]720 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]721 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]722 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]723 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]724 }
725
726 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]727 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]728 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]729 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]730
731 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
732 // the Thumb predicate.
733 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
734 result = MCDisassembler::SoftFail;
735
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]736 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]737
738 // If we find an IT instruction, we need to parse its condition
739 // code and mask operands so that we can apply them correctly
740 // to the subsequent instructions.
741 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]742
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]743 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]744 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]745 unsigned Mask = MI.getOperand(1).getImm();
746 unsigned CondBit0 = Mask >> 4 & 1;
747 unsigned NumTZ = CountTrailingZeros_32(Mask);
748 assert(NumTZ <= 3 && "Invalid IT mask!");
749 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
750 bool T = ((Mask >> Pos) & 1) == CondBit0;
751 if (T)
752 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]754 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]755 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]756
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]757 ITBlock.push_back(firstcond);
758 }
759
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]760 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]761 }
762
763 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]764 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
765 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]766 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]767 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]768
769 uint32_t insn32 = (bytes[3] << 8) |
770 (bytes[2] << 0) |
771 (bytes[1] << 24) |
772 (bytes[0] << 16);
773 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]774 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]775 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]776 Size = 4;
777 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]778 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]779 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]780 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]781 }
782
783 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]784 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]785 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]787 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]788 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]789 }
790
791 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]792 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]793 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 Size = 4;
795 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]796 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]797 }
798
799 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]800 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]801 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]802 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]803 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]804 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]805 }
806
807 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
808 MI.clear();
809 uint32_t NEONLdStInsn = insn32;
810 NEONLdStInsn &= 0xF0FFFFFF;
811 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]812 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]813 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]814 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]815 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]816 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]817 }
818 }
819
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]820 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]821 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]822 uint32_t NEONDataInsn = insn32;
823 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
824 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
825 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]826 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]827 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]828 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]829 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]830 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]831 }
832 }
833
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]834 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]835 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836}
837
838
839extern "C" void LLVMInitializeARMDisassembler() {
840 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
841 createARMDisassembler);
842 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
843 createThumbDisassembler);
844}
845
846static const unsigned GPRDecoderTable[] = {
847 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
848 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
849 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
850 ARM::R12, ARM::SP, ARM::LR, ARM::PC
851};
852
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]853static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854 uint64_t Address, const void *Decoder) {
855 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]856 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]857
858 unsigned Register = GPRDecoderTable[RegNo];
859 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]860 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]861}
862
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]863static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]864DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
865 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]866 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]867 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
868}
869
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]870static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]871 uint64_t Address, const void *Decoder) {
872 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]873 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]874 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
875}
876
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]877static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]878 uint64_t Address, const void *Decoder) {
879 unsigned Register = 0;
880 switch (RegNo) {
881 case 0:
882 Register = ARM::R0;
883 break;
884 case 1:
885 Register = ARM::R1;
886 break;
887 case 2:
888 Register = ARM::R2;
889 break;
890 case 3:
891 Register = ARM::R3;
892 break;
893 case 9:
894 Register = ARM::R9;
895 break;
896 case 12:
897 Register = ARM::R12;
898 break;
899 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]900 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]901 }
902
903 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]904 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]905}
906
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]907static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]909 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]910 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
911}
912
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]913static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]914 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
915 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
916 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
917 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
918 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
919 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
920 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
921 ARM::S28, ARM::S29, ARM::S30, ARM::S31
922};
923
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]924static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925 uint64_t Address, const void *Decoder) {
926 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]927 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]928
929 unsigned Register = SPRDecoderTable[RegNo];
930 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]931 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]932}
933
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]934static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]935 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
936 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
937 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
938 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
939 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
940 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
941 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
942 ARM::D28, ARM::D29, ARM::D30, ARM::D31
943};
944
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]945static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946 uint64_t Address, const void *Decoder) {
947 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]948 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]949
950 unsigned Register = DPRDecoderTable[RegNo];
951 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]952 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]953}
954
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]955static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]956 uint64_t Address, const void *Decoder) {
957 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]958 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]959 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
960}
961
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]962static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]963DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
964 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]965 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]966 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
968}
969
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]970static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]971 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
972 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
973 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
974 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
975};
976
977
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]978static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]979 uint64_t Address, const void *Decoder) {
980 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]981 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]982 RegNo >>= 1;
983
984 unsigned Register = QPRDecoderTable[RegNo];
985 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]986 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]987}
988
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]989static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]990 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]991 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]992 // AL predicate is not allowed on Thumb1 branches.
993 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]994 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995 Inst.addOperand(MCOperand::CreateImm(Val));
996 if (Val == ARMCC::AL) {
997 Inst.addOperand(MCOperand::CreateReg(0));
998 } else
999 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1000 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1001}
1002
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1003static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1004 uint64_t Address, const void *Decoder) {
1005 if (Val)
1006 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1007 else
1008 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1009 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1010}
1011
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1012static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1013 uint64_t Address, const void *Decoder) {
1014 uint32_t imm = Val & 0xFF;
1015 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1016 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1017 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1018 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1019}
1020
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1021static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1022 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1023 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024
1025 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1026 unsigned type = fieldFromInstruction32(Val, 5, 2);
1027 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1028
1029 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1031 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1032
1033 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1034 switch (type) {
1035 case 0:
1036 Shift = ARM_AM::lsl;
1037 break;
1038 case 1:
1039 Shift = ARM_AM::lsr;
1040 break;
1041 case 2:
1042 Shift = ARM_AM::asr;
1043 break;
1044 case 3:
1045 Shift = ARM_AM::ror;
1046 break;
1047 }
1048
1049 if (Shift == ARM_AM::ror && imm == 0)
1050 Shift = ARM_AM::rrx;
1051
1052 unsigned Op = Shift | (imm << 3);
1053 Inst.addOperand(MCOperand::CreateImm(Op));
1054
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1055 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1056}
1057
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1058static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1059 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1060 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1061
1062 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1063 unsigned type = fieldFromInstruction32(Val, 5, 2);
1064 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1065
1066 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1068 return MCDisassembler::Fail;
1069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1070 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1071
1072 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1073 switch (type) {
1074 case 0:
1075 Shift = ARM_AM::lsl;
1076 break;
1077 case 1:
1078 Shift = ARM_AM::lsr;
1079 break;
1080 case 2:
1081 Shift = ARM_AM::asr;
1082 break;
1083 case 3:
1084 Shift = ARM_AM::ror;
1085 break;
1086 }
1087
1088 Inst.addOperand(MCOperand::CreateImm(Shift));
1089
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1090 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1091}
1092
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1093static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1094 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1095 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1096
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1097 bool writebackLoad = false;
1098 unsigned writebackReg = 0;
1099 switch (Inst.getOpcode()) {
1100 default:
1101 break;
1102 case ARM::LDMIA_UPD:
1103 case ARM::LDMDB_UPD:
1104 case ARM::LDMIB_UPD:
1105 case ARM::LDMDA_UPD:
1106 case ARM::t2LDMIA_UPD:
1107 case ARM::t2LDMDB_UPD:
1108 writebackLoad = true;
1109 writebackReg = Inst.getOperand(0).getReg();
1110 break;
1111 }
1112
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1113 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame^]1114 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1115 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1116 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1117 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1118 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1119 // Writeback not allowed if Rn is in the target list.
1120 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1121 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1122 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1123 }
1124
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1125 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1126}
1127
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1128static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1129 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1130 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1131
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1132 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1133 unsigned regs = Val & 0xFF;
1134
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1135 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1136 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1137 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1138 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1139 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1140 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1141
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1142 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1143}
1144
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1145static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1146 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1147 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1148
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1149 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1150 unsigned regs = (Val & 0xFF) / 2;
1151
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1152 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1153 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1154 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1155 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1156 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1157 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1158
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1159 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1160}
1161
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1162static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1163 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1164 // This operand encodes a mask of contiguous zeros between a specified MSB
1165 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1166 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1167 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1168 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1169 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1170 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1171
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1172 DecodeStatus S = MCDisassembler::Success;
1173 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1174
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1175 uint32_t msb_mask = 0xFFFFFFFF;
1176 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1177 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1178
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1179 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1180 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1181}
1182
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1183static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1184 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1185 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1186
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1187 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1188 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1189 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1190 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1191 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1192 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1193
1194 switch (Inst.getOpcode()) {
1195 case ARM::LDC_OFFSET:
1196 case ARM::LDC_PRE:
1197 case ARM::LDC_POST:
1198 case ARM::LDC_OPTION:
1199 case ARM::LDCL_OFFSET:
1200 case ARM::LDCL_PRE:
1201 case ARM::LDCL_POST:
1202 case ARM::LDCL_OPTION:
1203 case ARM::STC_OFFSET:
1204 case ARM::STC_PRE:
1205 case ARM::STC_POST:
1206 case ARM::STC_OPTION:
1207 case ARM::STCL_OFFSET:
1208 case ARM::STCL_PRE:
1209 case ARM::STCL_POST:
1210 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1211 case ARM::t2LDC_OFFSET:
1212 case ARM::t2LDC_PRE:
1213 case ARM::t2LDC_POST:
1214 case ARM::t2LDC_OPTION:
1215 case ARM::t2LDCL_OFFSET:
1216 case ARM::t2LDCL_PRE:
1217 case ARM::t2LDCL_POST:
1218 case ARM::t2LDCL_OPTION:
1219 case ARM::t2STC_OFFSET:
1220 case ARM::t2STC_PRE:
1221 case ARM::t2STC_POST:
1222 case ARM::t2STC_OPTION:
1223 case ARM::t2STCL_OFFSET:
1224 case ARM::t2STCL_PRE:
1225 case ARM::t2STCL_POST:
1226 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1227 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1228 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1229 break;
1230 default:
1231 break;
1232 }
1233
1234 Inst.addOperand(MCOperand::CreateImm(coproc));
1235 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1237 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1239 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1240 case ARM::t2LDC2_OFFSET:
1241 case ARM::t2LDC2L_OFFSET:
1242 case ARM::t2LDC2_PRE:
1243 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1244 case ARM::t2STC2_OFFSET:
1245 case ARM::t2STC2L_OFFSET:
1246 case ARM::t2STC2_PRE:
1247 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1248 case ARM::LDC2_OFFSET:
1249 case ARM::LDC2L_OFFSET:
1250 case ARM::LDC2_PRE:
1251 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1252 case ARM::STC2_OFFSET:
1253 case ARM::STC2L_OFFSET:
1254 case ARM::STC2_PRE:
1255 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1256 case ARM::t2LDC_OFFSET:
1257 case ARM::t2LDCL_OFFSET:
1258 case ARM::t2LDC_PRE:
1259 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1260 case ARM::t2STC_OFFSET:
1261 case ARM::t2STCL_OFFSET:
1262 case ARM::t2STC_PRE:
1263 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1264 case ARM::LDC_OFFSET:
1265 case ARM::LDCL_OFFSET:
1266 case ARM::LDC_PRE:
1267 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1268 case ARM::STC_OFFSET:
1269 case ARM::STCL_OFFSET:
1270 case ARM::STC_PRE:
1271 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1272 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1273 Inst.addOperand(MCOperand::CreateImm(imm));
1274 break;
1275 case ARM::t2LDC2_POST:
1276 case ARM::t2LDC2L_POST:
1277 case ARM::t2STC2_POST:
1278 case ARM::t2STC2L_POST:
1279 case ARM::LDC2_POST:
1280 case ARM::LDC2L_POST:
1281 case ARM::STC2_POST:
1282 case ARM::STC2L_POST:
1283 case ARM::t2LDC_POST:
1284 case ARM::t2LDCL_POST:
1285 case ARM::t2STC_POST:
1286 case ARM::t2STCL_POST:
1287 case ARM::LDC_POST:
1288 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1289 case ARM::STC_POST:
1290 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1291 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1292 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1293 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1294 // The 'option' variant doesn't encode 'U' in the immediate since
1295 // the immediate is unsigned [0,255].
1296 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1297 break;
1298 }
1299
1300 switch (Inst.getOpcode()) {
1301 case ARM::LDC_OFFSET:
1302 case ARM::LDC_PRE:
1303 case ARM::LDC_POST:
1304 case ARM::LDC_OPTION:
1305 case ARM::LDCL_OFFSET:
1306 case ARM::LDCL_PRE:
1307 case ARM::LDCL_POST:
1308 case ARM::LDCL_OPTION:
1309 case ARM::STC_OFFSET:
1310 case ARM::STC_PRE:
1311 case ARM::STC_POST:
1312 case ARM::STC_OPTION:
1313 case ARM::STCL_OFFSET:
1314 case ARM::STCL_PRE:
1315 case ARM::STCL_POST:
1316 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1317 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1318 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1319 break;
1320 default:
1321 break;
1322 }
1323
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1324 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1325}
1326
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1327static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1328DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1329 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1330 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1331
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1332 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1333 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1334 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1335 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1336 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1337 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1338 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1339 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1340
1341 // On stores, the writeback operand precedes Rt.
1342 switch (Inst.getOpcode()) {
1343 case ARM::STR_POST_IMM:
1344 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1345 case ARM::STRB_POST_IMM:
1346 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1347 case ARM::STRT_POST_REG:
1348 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1349 case ARM::STRBT_POST_REG:
1350 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1352 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1353 break;
1354 default:
1355 break;
1356 }
1357
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1359 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1360
1361 // On loads, the writeback operand comes after Rt.
1362 switch (Inst.getOpcode()) {
1363 case ARM::LDR_POST_IMM:
1364 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1365 case ARM::LDRB_POST_IMM:
1366 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1367 case ARM::LDRBT_POST_REG:
1368 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1369 case ARM::LDRT_POST_REG:
1370 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1372 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1373 break;
1374 default:
1375 break;
1376 }
1377
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1379 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1380
1381 ARM_AM::AddrOpc Op = ARM_AM::add;
1382 if (!fieldFromInstruction32(Insn, 23, 1))
1383 Op = ARM_AM::sub;
1384
1385 bool writeback = (P == 0) || (W == 1);
1386 unsigned idx_mode = 0;
1387 if (P && writeback)
1388 idx_mode = ARMII::IndexModePre;
1389 else if (!P && writeback)
1390 idx_mode = ARMII::IndexModePost;
1391
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1392 if (writeback && (Rn == 15 || Rn == Rt))
1393 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1394
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1395 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1396 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1397 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1398 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1399 switch( fieldFromInstruction32(Insn, 5, 2)) {
1400 case 0:
1401 Opc = ARM_AM::lsl;
1402 break;
1403 case 1:
1404 Opc = ARM_AM::lsr;
1405 break;
1406 case 2:
1407 Opc = ARM_AM::asr;
1408 break;
1409 case 3:
1410 Opc = ARM_AM::ror;
1411 break;
1412 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1413 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1414 }
1415 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1416 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1417
1418 Inst.addOperand(MCOperand::CreateImm(imm));
1419 } else {
1420 Inst.addOperand(MCOperand::CreateReg(0));
1421 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1422 Inst.addOperand(MCOperand::CreateImm(tmp));
1423 }
1424
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1425 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1426 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1427
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1428 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1429}
1430
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1431static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1432 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1433 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1434
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1435 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1436 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1437 unsigned type = fieldFromInstruction32(Val, 5, 2);
1438 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1439 unsigned U = fieldFromInstruction32(Val, 12, 1);
1440
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1441 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1442 switch (type) {
1443 case 0:
1444 ShOp = ARM_AM::lsl;
1445 break;
1446 case 1:
1447 ShOp = ARM_AM::lsr;
1448 break;
1449 case 2:
1450 ShOp = ARM_AM::asr;
1451 break;
1452 case 3:
1453 ShOp = ARM_AM::ror;
1454 break;
1455 }
1456
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1458 return MCDisassembler::Fail;
1459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1460 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1461 unsigned shift;
1462 if (U)
1463 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1464 else
1465 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1466 Inst.addOperand(MCOperand::CreateImm(shift));
1467
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1468 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1469}
1470
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1471static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1472DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1473 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1474 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1475
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1476 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1477 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1478 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1479 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1480 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1481 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1482 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1483 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1484 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1485
1486 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1487
1488 // For {LD,ST}RD, Rt must be even, else undefined.
1489 switch (Inst.getOpcode()) {
1490 case ARM::STRD:
1491 case ARM::STRD_PRE:
1492 case ARM::STRD_POST:
1493 case ARM::LDRD:
1494 case ARM::LDRD_PRE:
1495 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1496 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1497 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1498 default:
1499 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1500 }
1501
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1502 if (writeback) { // Writeback
1503 if (P)
1504 U |= ARMII::IndexModePre << 9;
1505 else
1506 U |= ARMII::IndexModePost << 9;
1507
1508 // On stores, the writeback operand precedes Rt.
1509 switch (Inst.getOpcode()) {
1510 case ARM::STRD:
1511 case ARM::STRD_PRE:
1512 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1513 case ARM::STRH:
1514 case ARM::STRH_PRE:
1515 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1517 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1518 break;
1519 default:
1520 break;
1521 }
1522 }
1523
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1525 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1526 switch (Inst.getOpcode()) {
1527 case ARM::STRD:
1528 case ARM::STRD_PRE:
1529 case ARM::STRD_POST:
1530 case ARM::LDRD:
1531 case ARM::LDRD_PRE:
1532 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1534 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1535 break;
1536 default:
1537 break;
1538 }
1539
1540 if (writeback) {
1541 // On loads, the writeback operand comes after Rt.
1542 switch (Inst.getOpcode()) {
1543 case ARM::LDRD:
1544 case ARM::LDRD_PRE:
1545 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1546 case ARM::LDRH:
1547 case ARM::LDRH_PRE:
1548 case ARM::LDRH_POST:
1549 case ARM::LDRSH:
1550 case ARM::LDRSH_PRE:
1551 case ARM::LDRSH_POST:
1552 case ARM::LDRSB:
1553 case ARM::LDRSB_PRE:
1554 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1555 case ARM::LDRHTr:
1556 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1558 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1559 break;
1560 default:
1561 break;
1562 }
1563 }
1564
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1566 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1567
1568 if (type) {
1569 Inst.addOperand(MCOperand::CreateReg(0));
1570 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1571 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1573 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1574 Inst.addOperand(MCOperand::CreateImm(U));
1575 }
1576
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1577 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1578 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1579
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1580 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1581}
1582
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1583static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1584 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1585 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1586
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1587 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1588 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1589
1590 switch (mode) {
1591 case 0:
1592 mode = ARM_AM::da;
1593 break;
1594 case 1:
1595 mode = ARM_AM::ia;
1596 break;
1597 case 2:
1598 mode = ARM_AM::db;
1599 break;
1600 case 3:
1601 mode = ARM_AM::ib;
1602 break;
1603 }
1604
1605 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1607 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1608
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1609 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1610}
1611
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1612static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1613 unsigned Insn,
1614 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1615 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1616
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1617 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1618 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1619 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1620
1621 if (pred == 0xF) {
1622 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1623 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1624 Inst.setOpcode(ARM::RFEDA);
1625 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1626 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1627 Inst.setOpcode(ARM::RFEDA_UPD);
1628 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1629 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1630 Inst.setOpcode(ARM::RFEDB);
1631 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1632 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1633 Inst.setOpcode(ARM::RFEDB_UPD);
1634 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1635 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1636 Inst.setOpcode(ARM::RFEIA);
1637 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1638 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1639 Inst.setOpcode(ARM::RFEIA_UPD);
1640 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1641 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1642 Inst.setOpcode(ARM::RFEIB);
1643 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1644 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1645 Inst.setOpcode(ARM::RFEIB_UPD);
1646 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1647 case ARM::STMDA:
1648 Inst.setOpcode(ARM::SRSDA);
1649 break;
1650 case ARM::STMDA_UPD:
1651 Inst.setOpcode(ARM::SRSDA_UPD);
1652 break;
1653 case ARM::STMDB:
1654 Inst.setOpcode(ARM::SRSDB);
1655 break;
1656 case ARM::STMDB_UPD:
1657 Inst.setOpcode(ARM::SRSDB_UPD);
1658 break;
1659 case ARM::STMIA:
1660 Inst.setOpcode(ARM::SRSIA);
1661 break;
1662 case ARM::STMIA_UPD:
1663 Inst.setOpcode(ARM::SRSIA_UPD);
1664 break;
1665 case ARM::STMIB:
1666 Inst.setOpcode(ARM::SRSIB);
1667 break;
1668 case ARM::STMIB_UPD:
1669 Inst.setOpcode(ARM::SRSIB_UPD);
1670 break;
1671 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1672 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1673 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1674
1675 // For stores (which become SRS's, the only operand is the mode.
1676 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1677 Inst.addOperand(
1678 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1679 return S;
1680 }
1681
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1682 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1683 }
1684
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1686 return MCDisassembler::Fail;
1687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1688 return MCDisassembler::Fail; // Tied
1689 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1690 return MCDisassembler::Fail;
1691 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1692 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1693
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1694 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1695}
1696
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1697static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1698 uint64_t Address, const void *Decoder) {
1699 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1700 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1701 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1702 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1703
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1704 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1705
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1706 // imod == '01' --> UNPREDICTABLE
1707 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1708 // return failure here. The '01' imod value is unprintable, so there's
1709 // nothing useful we could do even if we returned UNPREDICTABLE.
1710
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1711 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1712
1713 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1714 Inst.setOpcode(ARM::CPS3p);
1715 Inst.addOperand(MCOperand::CreateImm(imod));
1716 Inst.addOperand(MCOperand::CreateImm(iflags));
1717 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1718 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1719 Inst.setOpcode(ARM::CPS2p);
1720 Inst.addOperand(MCOperand::CreateImm(imod));
1721 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1722 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1723 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1724 Inst.setOpcode(ARM::CPS1p);
1725 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1726 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1727 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1728 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1729 Inst.setOpcode(ARM::CPS1p);
1730 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1731 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1732 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1733
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1734 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1735}
1736
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1737static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1738 uint64_t Address, const void *Decoder) {
1739 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1740 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1741 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1742 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1743
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1744 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1745
1746 // imod == '01' --> UNPREDICTABLE
1747 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1748 // return failure here. The '01' imod value is unprintable, so there's
1749 // nothing useful we could do even if we returned UNPREDICTABLE.
1750
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1751 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1752
1753 if (imod && M) {
1754 Inst.setOpcode(ARM::t2CPS3p);
1755 Inst.addOperand(MCOperand::CreateImm(imod));
1756 Inst.addOperand(MCOperand::CreateImm(iflags));
1757 Inst.addOperand(MCOperand::CreateImm(mode));
1758 } else if (imod && !M) {
1759 Inst.setOpcode(ARM::t2CPS2p);
1760 Inst.addOperand(MCOperand::CreateImm(imod));
1761 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1762 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1763 } else if (!imod && M) {
1764 Inst.setOpcode(ARM::t2CPS1p);
1765 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1766 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1767 } else {
1768 // imod == '00' && M == '0' --> UNPREDICTABLE
1769 Inst.setOpcode(ARM::t2CPS1p);
1770 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1771 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1772 }
1773
1774 return S;
1775}
1776
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1777static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1778 uint64_t Address, const void *Decoder) {
1779 DecodeStatus S = MCDisassembler::Success;
1780
1781 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1782 unsigned imm = 0;
1783
1784 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1785 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1786 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1787 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1788
1789 if (Inst.getOpcode() == ARM::t2MOVTi16)
1790 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1791 return MCDisassembler::Fail;
1792 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1793 return MCDisassembler::Fail;
1794
1795 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1796 Inst.addOperand(MCOperand::CreateImm(imm));
1797
1798 return S;
1799}
1800
1801static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1802 uint64_t Address, const void *Decoder) {
1803 DecodeStatus S = MCDisassembler::Success;
1804
1805 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1806 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1807 unsigned imm = 0;
1808
1809 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1810 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1811
1812 if (Inst.getOpcode() == ARM::MOVTi16)
1813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1814 return MCDisassembler::Fail;
1815 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1816 return MCDisassembler::Fail;
1817
1818 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1819 Inst.addOperand(MCOperand::CreateImm(imm));
1820
1821 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1822 return MCDisassembler::Fail;
1823
1824 return S;
1825}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1826
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1827static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1828 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1829 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1830
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1831 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1832 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1833 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1834 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1835 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1836
1837 if (pred == 0xF)
1838 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1839
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1841 return MCDisassembler::Fail;
1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1843 return MCDisassembler::Fail;
1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1847 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1848
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1849 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1850 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1851
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1852 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1853}
1854
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1855static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1856 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1857 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1858
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1859 unsigned add = fieldFromInstruction32(Val, 12, 1);
1860 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1861 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1862
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1864 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1865
1866 if (!add) imm *= -1;
1867 if (imm == 0 && !add) imm = INT32_MIN;
1868 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1869 if (Rn == 15)
1870 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1871
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1872 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1873}
1874
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1875static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1876 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1877 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1878
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1879 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1880 unsigned U = fieldFromInstruction32(Val, 8, 1);
1881 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1882
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1884 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1885
1886 if (U)
1887 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1888 else
1889 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1890
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1891 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1892}
1893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1894static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1895 uint64_t Address, const void *Decoder) {
1896 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1897}
1898
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1899static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1900DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1901 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1902 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1903
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1904 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1905 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1906
1907 if (pred == 0xF) {
1908 Inst.setOpcode(ARM::BLXi);
1909 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1910 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1911 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1912 }
1913
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1914 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1915 4, Inst, Decoder))
1916 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1917 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1918 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1919
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1920 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1921}
1922
1923
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1924static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1925 uint64_t Address, const void *Decoder) {
1926 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1927 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1928}
1929
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1930static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1931 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1932 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1933
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1934 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1935 unsigned align = fieldFromInstruction32(Val, 4, 2);
1936
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1938 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1939 if (!align)
1940 Inst.addOperand(MCOperand::CreateImm(0));
1941 else
1942 Inst.addOperand(MCOperand::CreateImm(4 << align));
1943
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1944 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1945}
1946
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1947static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1948 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1949 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1950
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1951 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1952 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1953 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1954 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1955 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1956 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1957
1958 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1960 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1961
1962 // Second output register
1963 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1964 case ARM::VLD3d8:
1965 case ARM::VLD3d16:
1966 case ARM::VLD3d32:
1967 case ARM::VLD3d8_UPD:
1968 case ARM::VLD3d16_UPD:
1969 case ARM::VLD3d32_UPD:
1970 case ARM::VLD4d8:
1971 case ARM::VLD4d16:
1972 case ARM::VLD4d32:
1973 case ARM::VLD4d8_UPD:
1974 case ARM::VLD4d16_UPD:
1975 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1976 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1977 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1978 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1979 case ARM::VLD3q8:
1980 case ARM::VLD3q16:
1981 case ARM::VLD3q32:
1982 case ARM::VLD3q8_UPD:
1983 case ARM::VLD3q16_UPD:
1984 case ARM::VLD3q32_UPD:
1985 case ARM::VLD4q8:
1986 case ARM::VLD4q16:
1987 case ARM::VLD4q32:
1988 case ARM::VLD4q8_UPD:
1989 case ARM::VLD4q16_UPD:
1990 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1991 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1992 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1993 default:
1994 break;
1995 }
1996
1997 // Third output register
1998 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1999 case ARM::VLD3d8:
2000 case ARM::VLD3d16:
2001 case ARM::VLD3d32:
2002 case ARM::VLD3d8_UPD:
2003 case ARM::VLD3d16_UPD:
2004 case ARM::VLD3d32_UPD:
2005 case ARM::VLD4d8:
2006 case ARM::VLD4d16:
2007 case ARM::VLD4d32:
2008 case ARM::VLD4d8_UPD:
2009 case ARM::VLD4d16_UPD:
2010 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2011 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2012 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2013 break;
2014 case ARM::VLD3q8:
2015 case ARM::VLD3q16:
2016 case ARM::VLD3q32:
2017 case ARM::VLD3q8_UPD:
2018 case ARM::VLD3q16_UPD:
2019 case ARM::VLD3q32_UPD:
2020 case ARM::VLD4q8:
2021 case ARM::VLD4q16:
2022 case ARM::VLD4q32:
2023 case ARM::VLD4q8_UPD:
2024 case ARM::VLD4q16_UPD:
2025 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2026 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2027 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2028 break;
2029 default:
2030 break;
2031 }
2032
2033 // Fourth output register
2034 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2035 case ARM::VLD4d8:
2036 case ARM::VLD4d16:
2037 case ARM::VLD4d32:
2038 case ARM::VLD4d8_UPD:
2039 case ARM::VLD4d16_UPD:
2040 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2041 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2042 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2043 break;
2044 case ARM::VLD4q8:
2045 case ARM::VLD4q16:
2046 case ARM::VLD4q32:
2047 case ARM::VLD4q8_UPD:
2048 case ARM::VLD4q16_UPD:
2049 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2050 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2051 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2052 break;
2053 default:
2054 break;
2055 }
2056
2057 // Writeback operand
2058 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2059 case ARM::VLD1d8wb_fixed:
2060 case ARM::VLD1d16wb_fixed:
2061 case ARM::VLD1d32wb_fixed:
2062 case ARM::VLD1d64wb_fixed:
2063 case ARM::VLD1d8wb_register:
2064 case ARM::VLD1d16wb_register:
2065 case ARM::VLD1d32wb_register:
2066 case ARM::VLD1d64wb_register:
2067 case ARM::VLD1q8wb_fixed:
2068 case ARM::VLD1q16wb_fixed:
2069 case ARM::VLD1q32wb_fixed:
2070 case ARM::VLD1q64wb_fixed:
2071 case ARM::VLD1q8wb_register:
2072 case ARM::VLD1q16wb_register:
2073 case ARM::VLD1q32wb_register:
2074 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2075 case ARM::VLD1d8Twb_fixed:
2076 case ARM::VLD1d8Twb_register:
2077 case ARM::VLD1d16Twb_fixed:
2078 case ARM::VLD1d16Twb_register:
2079 case ARM::VLD1d32Twb_fixed:
2080 case ARM::VLD1d32Twb_register:
2081 case ARM::VLD1d64Twb_fixed:
2082 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2083 case ARM::VLD1d8Qwb_fixed:
2084 case ARM::VLD1d8Qwb_register:
2085 case ARM::VLD1d16Qwb_fixed:
2086 case ARM::VLD1d16Qwb_register:
2087 case ARM::VLD1d32Qwb_fixed:
2088 case ARM::VLD1d32Qwb_register:
2089 case ARM::VLD1d64Qwb_fixed:
2090 case ARM::VLD1d64Qwb_register:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2091 case ARM::VLD2d8_UPD:
2092 case ARM::VLD2d16_UPD:
2093 case ARM::VLD2d32_UPD:
2094 case ARM::VLD2q8_UPD:
2095 case ARM::VLD2q16_UPD:
2096 case ARM::VLD2q32_UPD:
2097 case ARM::VLD2b8_UPD:
2098 case ARM::VLD2b16_UPD:
2099 case ARM::VLD2b32_UPD:
2100 case ARM::VLD3d8_UPD:
2101 case ARM::VLD3d16_UPD:
2102 case ARM::VLD3d32_UPD:
2103 case ARM::VLD3q8_UPD:
2104 case ARM::VLD3q16_UPD:
2105 case ARM::VLD3q32_UPD:
2106 case ARM::VLD4d8_UPD:
2107 case ARM::VLD4d16_UPD:
2108 case ARM::VLD4d32_UPD:
2109 case ARM::VLD4q8_UPD:
2110 case ARM::VLD4q16_UPD:
2111 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2112 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2113 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2114 break;
2115 default:
2116 break;
2117 }
2118
2119 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2120 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2121 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2122
2123 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2124 switch (Inst.getOpcode()) {
2125 default:
2126 // The below have been updated to have explicit am6offset split
2127 // between fixed and register offset. For those instructions not
2128 // yet updated, we need to add an additional reg0 operand for the
2129 // fixed variant.
2130 //
2131 // The fixed offset encodes as Rm == 0xd, so we check for that.
2132 if (Rm == 0xd) {
2133 Inst.addOperand(MCOperand::CreateReg(0));
2134 break;
2135 }
2136 // Fall through to handle the register offset variant.
2137 case ARM::VLD1d8wb_fixed:
2138 case ARM::VLD1d16wb_fixed:
2139 case ARM::VLD1d32wb_fixed:
2140 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2141 case ARM::VLD1d8Twb_fixed:
2142 case ARM::VLD1d16Twb_fixed:
2143 case ARM::VLD1d32Twb_fixed:
2144 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2145 case ARM::VLD1d8Qwb_fixed:
2146 case ARM::VLD1d16Qwb_fixed:
2147 case ARM::VLD1d32Qwb_fixed:
2148 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2149 case ARM::VLD1d8wb_register:
2150 case ARM::VLD1d16wb_register:
2151 case ARM::VLD1d32wb_register:
2152 case ARM::VLD1d64wb_register:
2153 case ARM::VLD1q8wb_fixed:
2154 case ARM::VLD1q16wb_fixed:
2155 case ARM::VLD1q32wb_fixed:
2156 case ARM::VLD1q64wb_fixed:
2157 case ARM::VLD1q8wb_register:
2158 case ARM::VLD1q16wb_register:
2159 case ARM::VLD1q32wb_register:
2160 case ARM::VLD1q64wb_register:
2161 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2162 // variant encodes Rm == 0xf. Anything else is a register offset post-
2163 // increment and we need to add the register operand to the instruction.
2164 if (Rm != 0xD && Rm != 0xF &&
2165 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2166 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2167 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2168 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2169
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2170 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2171}
2172
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2173static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2174 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2175 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2176
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2177 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2178 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2179 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2180 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2181 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2182 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2183
2184 // Writeback Operand
2185 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2186 case ARM::VST1d8wb_fixed:
2187 case ARM::VST1d16wb_fixed:
2188 case ARM::VST1d32wb_fixed:
2189 case ARM::VST1d64wb_fixed:
2190 case ARM::VST1d8wb_register:
2191 case ARM::VST1d16wb_register:
2192 case ARM::VST1d32wb_register:
2193 case ARM::VST1d64wb_register:
2194 case ARM::VST1q8wb_fixed:
2195 case ARM::VST1q16wb_fixed:
2196 case ARM::VST1q32wb_fixed:
2197 case ARM::VST1q64wb_fixed:
2198 case ARM::VST1q8wb_register:
2199 case ARM::VST1q16wb_register:
2200 case ARM::VST1q32wb_register:
2201 case ARM::VST1q64wb_register:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2202 case ARM::VST1d8T_UPD:
2203 case ARM::VST1d16T_UPD:
2204 case ARM::VST1d32T_UPD:
2205 case ARM::VST1d64T_UPD:
2206 case ARM::VST1d8Q_UPD:
2207 case ARM::VST1d16Q_UPD:
2208 case ARM::VST1d32Q_UPD:
2209 case ARM::VST1d64Q_UPD:
2210 case ARM::VST2d8_UPD:
2211 case ARM::VST2d16_UPD:
2212 case ARM::VST2d32_UPD:
2213 case ARM::VST2q8_UPD:
2214 case ARM::VST2q16_UPD:
2215 case ARM::VST2q32_UPD:
2216 case ARM::VST2b8_UPD:
2217 case ARM::VST2b16_UPD:
2218 case ARM::VST2b32_UPD:
2219 case ARM::VST3d8_UPD:
2220 case ARM::VST3d16_UPD:
2221 case ARM::VST3d32_UPD:
2222 case ARM::VST3q8_UPD:
2223 case ARM::VST3q16_UPD:
2224 case ARM::VST3q32_UPD:
2225 case ARM::VST4d8_UPD:
2226 case ARM::VST4d16_UPD:
2227 case ARM::VST4d32_UPD:
2228 case ARM::VST4q8_UPD:
2229 case ARM::VST4q16_UPD:
2230 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2231 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2232 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2233 break;
2234 default:
2235 break;
2236 }
2237
2238 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2239 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2240 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2241
2242 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2243 switch (Inst.getOpcode()) {
2244 default:
2245 if (Rm == 0xD)
2246 Inst.addOperand(MCOperand::CreateReg(0));
2247 else if (Rm != 0xF) {
2248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2249 return MCDisassembler::Fail;
2250 }
2251 break;
2252 case ARM::VST1d8wb_fixed:
2253 case ARM::VST1d16wb_fixed:
2254 case ARM::VST1d32wb_fixed:
2255 case ARM::VST1d64wb_fixed:
2256 case ARM::VST1q8wb_fixed:
2257 case ARM::VST1q16wb_fixed:
2258 case ARM::VST1q32wb_fixed:
2259 case ARM::VST1q64wb_fixed:
2260 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2261 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2262
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2263
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2264 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2265 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2266 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2267
2268 // Second input register
2269 switch (Inst.getOpcode()) {
2270 case ARM::VST1q8:
2271 case ARM::VST1q16:
2272 case ARM::VST1q32:
2273 case ARM::VST1q64:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2274 case ARM::VST1d8T:
2275 case ARM::VST1d16T:
2276 case ARM::VST1d32T:
2277 case ARM::VST1d64T:
2278 case ARM::VST1d8T_UPD:
2279 case ARM::VST1d16T_UPD:
2280 case ARM::VST1d32T_UPD:
2281 case ARM::VST1d64T_UPD:
2282 case ARM::VST1d8Q:
2283 case ARM::VST1d16Q:
2284 case ARM::VST1d32Q:
2285 case ARM::VST1d64Q:
2286 case ARM::VST1d8Q_UPD:
2287 case ARM::VST1d16Q_UPD:
2288 case ARM::VST1d32Q_UPD:
2289 case ARM::VST1d64Q_UPD:
2290 case ARM::VST2d8:
2291 case ARM::VST2d16:
2292 case ARM::VST2d32:
2293 case ARM::VST2d8_UPD:
2294 case ARM::VST2d16_UPD:
2295 case ARM::VST2d32_UPD:
2296 case ARM::VST2q8:
2297 case ARM::VST2q16:
2298 case ARM::VST2q32:
2299 case ARM::VST2q8_UPD:
2300 case ARM::VST2q16_UPD:
2301 case ARM::VST2q32_UPD:
2302 case ARM::VST3d8:
2303 case ARM::VST3d16:
2304 case ARM::VST3d32:
2305 case ARM::VST3d8_UPD:
2306 case ARM::VST3d16_UPD:
2307 case ARM::VST3d32_UPD:
2308 case ARM::VST4d8:
2309 case ARM::VST4d16:
2310 case ARM::VST4d32:
2311 case ARM::VST4d8_UPD:
2312 case ARM::VST4d16_UPD:
2313 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2314 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2315 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2316 break;
2317 case ARM::VST2b8:
2318 case ARM::VST2b16:
2319 case ARM::VST2b32:
2320 case ARM::VST2b8_UPD:
2321 case ARM::VST2b16_UPD:
2322 case ARM::VST2b32_UPD:
2323 case ARM::VST3q8:
2324 case ARM::VST3q16:
2325 case ARM::VST3q32:
2326 case ARM::VST3q8_UPD:
2327 case ARM::VST3q16_UPD:
2328 case ARM::VST3q32_UPD:
2329 case ARM::VST4q8:
2330 case ARM::VST4q16:
2331 case ARM::VST4q32:
2332 case ARM::VST4q8_UPD:
2333 case ARM::VST4q16_UPD:
2334 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2335 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2336 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2337 break;
2338 default:
2339 break;
2340 }
2341
2342 // Third input register
2343 switch (Inst.getOpcode()) {
2344 case ARM::VST1d8T:
2345 case ARM::VST1d16T:
2346 case ARM::VST1d32T:
2347 case ARM::VST1d64T:
2348 case ARM::VST1d8T_UPD:
2349 case ARM::VST1d16T_UPD:
2350 case ARM::VST1d32T_UPD:
2351 case ARM::VST1d64T_UPD:
2352 case ARM::VST1d8Q:
2353 case ARM::VST1d16Q:
2354 case ARM::VST1d32Q:
2355 case ARM::VST1d64Q:
2356 case ARM::VST1d8Q_UPD:
2357 case ARM::VST1d16Q_UPD:
2358 case ARM::VST1d32Q_UPD:
2359 case ARM::VST1d64Q_UPD:
2360 case ARM::VST2q8:
2361 case ARM::VST2q16:
2362 case ARM::VST2q32:
2363 case ARM::VST2q8_UPD:
2364 case ARM::VST2q16_UPD:
2365 case ARM::VST2q32_UPD:
2366 case ARM::VST3d8:
2367 case ARM::VST3d16:
2368 case ARM::VST3d32:
2369 case ARM::VST3d8_UPD:
2370 case ARM::VST3d16_UPD:
2371 case ARM::VST3d32_UPD:
2372 case ARM::VST4d8:
2373 case ARM::VST4d16:
2374 case ARM::VST4d32:
2375 case ARM::VST4d8_UPD:
2376 case ARM::VST4d16_UPD:
2377 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2378 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2379 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2380 break;
2381 case ARM::VST3q8:
2382 case ARM::VST3q16:
2383 case ARM::VST3q32:
2384 case ARM::VST3q8_UPD:
2385 case ARM::VST3q16_UPD:
2386 case ARM::VST3q32_UPD:
2387 case ARM::VST4q8:
2388 case ARM::VST4q16:
2389 case ARM::VST4q32:
2390 case ARM::VST4q8_UPD:
2391 case ARM::VST4q16_UPD:
2392 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2393 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2394 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2395 break;
2396 default:
2397 break;
2398 }
2399
2400 // Fourth input register
2401 switch (Inst.getOpcode()) {
2402 case ARM::VST1d8Q:
2403 case ARM::VST1d16Q:
2404 case ARM::VST1d32Q:
2405 case ARM::VST1d64Q:
2406 case ARM::VST1d8Q_UPD:
2407 case ARM::VST1d16Q_UPD:
2408 case ARM::VST1d32Q_UPD:
2409 case ARM::VST1d64Q_UPD:
2410 case ARM::VST2q8:
2411 case ARM::VST2q16:
2412 case ARM::VST2q32:
2413 case ARM::VST2q8_UPD:
2414 case ARM::VST2q16_UPD:
2415 case ARM::VST2q32_UPD:
2416 case ARM::VST4d8:
2417 case ARM::VST4d16:
2418 case ARM::VST4d32:
2419 case ARM::VST4d8_UPD:
2420 case ARM::VST4d16_UPD:
2421 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2422 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2423 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2424 break;
2425 case ARM::VST4q8:
2426 case ARM::VST4q16:
2427 case ARM::VST4q32:
2428 case ARM::VST4q8_UPD:
2429 case ARM::VST4q16_UPD:
2430 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2431 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2432 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2433 break;
2434 default:
2435 break;
2436 }
2437
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2438 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2439}
2440
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2441static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2442 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2443 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2444
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2445 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2446 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2447 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2448 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2449 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2450 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2451 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2452
2453 align *= (1 << size);
2454
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2456 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2457 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2458 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2459 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2460 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2461 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2463 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2464 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2465
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2467 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2468 Inst.addOperand(MCOperand::CreateImm(align));
2469
2470 if (Rm == 0xD)
2471 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2472 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2474 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2475 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2476
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2477 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2478}
2479
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2480static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2481 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2482 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2483
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2484 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2485 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2486 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2487 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2488 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2489 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2490 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2491 align *= 2*size;
2492
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2493 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2494 return MCDisassembler::Fail;
2495 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2496 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2497 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2499 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2500 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2501
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2503 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2504 Inst.addOperand(MCOperand::CreateImm(align));
2505
2506 if (Rm == 0xD)
2507 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2508 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2510 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2511 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2512
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2513 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2514}
2515
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2516static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2517 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2518 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2519
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2520 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2521 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2522 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2523 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2524 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2525
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2527 return MCDisassembler::Fail;
2528 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2529 return MCDisassembler::Fail;
2530 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2531 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2532 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2534 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2535 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2536
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2538 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2539 Inst.addOperand(MCOperand::CreateImm(0));
2540
2541 if (Rm == 0xD)
2542 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2543 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2545 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2546 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2547
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2548 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2549}
2550
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2551static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2552 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2553 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2554
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2555 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2556 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2557 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2558 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2559 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2560 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2561 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2562
2563 if (size == 0x3) {
2564 size = 4;
2565 align = 16;
2566 } else {
2567 if (size == 2) {
2568 size = 1 << size;
2569 align *= 8;
2570 } else {
2571 size = 1 << size;
2572 align *= 4*size;
2573 }
2574 }
2575
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2577 return MCDisassembler::Fail;
2578 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2579 return MCDisassembler::Fail;
2580 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2581 return MCDisassembler::Fail;
2582 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2583 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2584 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2586 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2587 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2588
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2589 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2590 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2591 Inst.addOperand(MCOperand::CreateImm(align));
2592
2593 if (Rm == 0xD)
2594 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2595 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2597 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2598 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2599
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2600 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2601}
2602
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2603static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2604DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2605 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2606 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2607
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2608 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2609 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2610 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2611 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2612 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2613 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2614 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2615 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2616
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2617 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2618 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2619 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2620 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2621 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2622 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2623 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2624
2625 Inst.addOperand(MCOperand::CreateImm(imm));
2626
2627 switch (Inst.getOpcode()) {
2628 case ARM::VORRiv4i16:
2629 case ARM::VORRiv2i32:
2630 case ARM::VBICiv4i16:
2631 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2632 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2633 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2634 break;
2635 case ARM::VORRiv8i16:
2636 case ARM::VORRiv4i32:
2637 case ARM::VBICiv8i16:
2638 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2639 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2640 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2641 break;
2642 default:
2643 break;
2644 }
2645
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2646 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2647}
2648
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2649static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2650 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2651 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2652
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2653 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2654 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2655 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2656 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2657 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2658
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2659 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2660 return MCDisassembler::Fail;
2661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2662 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2663 Inst.addOperand(MCOperand::CreateImm(8 << size));
2664
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2665 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2666}
2667
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2668static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2669 uint64_t Address, const void *Decoder) {
2670 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2671 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2672}
2673
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2674static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2675 uint64_t Address, const void *Decoder) {
2676 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2677 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2678}
2679
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2680static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2681 uint64_t Address, const void *Decoder) {
2682 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2683 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684}
2685
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2686static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2687 uint64_t Address, const void *Decoder) {
2688 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2689 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2690}
2691
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2692static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2693 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2694 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2695
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2696 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2697 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2698 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2699 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2700 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2701 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2702 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2703 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2704
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2705 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2706 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2707 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2709 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2710 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2711
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2712 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2713 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2714 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2715 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2716
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2718 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2719
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2720 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2721}
2722
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2723static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2724 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2725 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2726
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2727 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2728 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2729
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2730 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2731 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2732
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2733 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2734 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2735 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2736 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2737 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2738 case ARM::tADDrSPi:
2739 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2740 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2741 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2742
2743 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2744 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2745}
2746
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2747static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2748 uint64_t Address, const void *Decoder) {
2749 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2750 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2751}
2752
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2753static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2754 uint64_t Address, const void *Decoder) {
2755 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2756 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757}
2758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2759static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2760 uint64_t Address, const void *Decoder) {
2761 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2762 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2763}
2764
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2765static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2766 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2767 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2768
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2769 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2770 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2771
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2772 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2773 return MCDisassembler::Fail;
2774 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2775 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2776
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2777 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2778}
2779
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2780static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2781 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2782 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2783
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2784 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2785 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2786
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2787 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2788 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2789 Inst.addOperand(MCOperand::CreateImm(imm));
2790
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2791 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2792}
2793
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2794static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2795 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2796 unsigned imm = Val << 2;
2797
2798 Inst.addOperand(MCOperand::CreateImm(imm));
2799 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2800
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2801 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2802}
2803
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2804static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2805 uint64_t Address, const void *Decoder) {
2806 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2807 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2809 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2810}
2811
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2812static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2813 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2814 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2815
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2816 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2817 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2818 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2819
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2821 return MCDisassembler::Fail;
2822 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2823 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2824 Inst.addOperand(MCOperand::CreateImm(imm));
2825
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2826 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2827}
2828
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2829static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2830 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2831 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2832
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2833 switch (Inst.getOpcode()) {
2834 case ARM::t2PLDs:
2835 case ARM::t2PLDWs:
2836 case ARM::t2PLIs:
2837 break;
2838 default: {
2839 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2840 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2841 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2842 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2843 }
2844
2845 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2846 if (Rn == 0xF) {
2847 switch (Inst.getOpcode()) {
2848 case ARM::t2LDRBs:
2849 Inst.setOpcode(ARM::t2LDRBpci);
2850 break;
2851 case ARM::t2LDRHs:
2852 Inst.setOpcode(ARM::t2LDRHpci);
2853 break;
2854 case ARM::t2LDRSHs:
2855 Inst.setOpcode(ARM::t2LDRSHpci);
2856 break;
2857 case ARM::t2LDRSBs:
2858 Inst.setOpcode(ARM::t2LDRSBpci);
2859 break;
2860 case ARM::t2PLDs:
2861 Inst.setOpcode(ARM::t2PLDi12);
2862 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2863 break;
2864 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2865 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2866 }
2867
2868 int imm = fieldFromInstruction32(Insn, 0, 12);
2869 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2870 Inst.addOperand(MCOperand::CreateImm(imm));
2871
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2872 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2873 }
2874
2875 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2876 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2877 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2878 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2879 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2880
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2881 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2882}
2883
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2884static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2885 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2886 int imm = Val & 0xFF;
2887 if (!(Val & 0x100)) imm *= -1;
2888 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2889
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2890 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2891}
2892
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2893static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2894 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2895 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2896
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2897 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2898 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2899
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2901 return MCDisassembler::Fail;
2902 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2903 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2904
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2905 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2906}
2907
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2908static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2909 uint64_t Address, const void *Decoder) {
2910 DecodeStatus S = MCDisassembler::Success;
2911
2912 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2913 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2914
2915 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2916 return MCDisassembler::Fail;
2917
2918 Inst.addOperand(MCOperand::CreateImm(imm));
2919
2920 return S;
2921}
2922
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2923static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2924 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2925 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2926 if (Val == 0)
2927 imm = INT32_MIN;
2928 else if (!(Val & 0x100))
2929 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2930 Inst.addOperand(MCOperand::CreateImm(imm));
2931
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2932 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2933}
2934
2935
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2936static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2937 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2938 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2939
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2940 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2941 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2942
2943 // Some instructions always use an additive offset.
2944 switch (Inst.getOpcode()) {
2945 case ARM::t2LDRT:
2946 case ARM::t2LDRBT:
2947 case ARM::t2LDRHT:
2948 case ARM::t2LDRSBT:
2949 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2950 case ARM::t2STRT:
2951 case ARM::t2STRBT:
2952 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2953 imm |= 0x100;
2954 break;
2955 default:
2956 break;
2957 }
2958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2960 return MCDisassembler::Fail;
2961 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2962 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2963
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2964 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2965}
2966
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2967static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2968 uint64_t Address, const void *Decoder) {
2969 DecodeStatus S = MCDisassembler::Success;
2970
2971 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2972 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2973 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2974 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2975 addr |= Rn << 9;
2976 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2977
2978 if (!load) {
2979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2980 return MCDisassembler::Fail;
2981 }
2982
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2983 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2984 return MCDisassembler::Fail;
2985
2986 if (load) {
2987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2988 return MCDisassembler::Fail;
2989 }
2990
2991 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2992 return MCDisassembler::Fail;
2993
2994 return S;
2995}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2996
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2997static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2998 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2999 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3000
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3001 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3002 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3003
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3005 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3006 Inst.addOperand(MCOperand::CreateImm(imm));
3007
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3008 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3009}
3010
3011
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3012static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3013 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3014 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3015
3016 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3017 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3018 Inst.addOperand(MCOperand::CreateImm(imm));
3019
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3020 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3021}
3022
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3023static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3024 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3025 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3026
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3027 if (Inst.getOpcode() == ARM::tADDrSP) {
3028 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3029 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3030
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3032 return MCDisassembler::Fail;
3033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3034 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3035 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3036 } else if (Inst.getOpcode() == ARM::tADDspr) {
3037 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3038
3039 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3040 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3041 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3042 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3043 }
3044
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3045 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3046}
3047
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3048static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3049 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3050 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3051 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3052
3053 Inst.addOperand(MCOperand::CreateImm(imod));
3054 Inst.addOperand(MCOperand::CreateImm(flags));
3055
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3056 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3057}
3058
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3059static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3060 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3061 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3062 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3063 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3064
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3066 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3067 Inst.addOperand(MCOperand::CreateImm(add));
3068
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3069 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3070}
3071
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3072static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3073 uint64_t Address, const void *Decoder) {
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3074 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3075 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3076 true, 4, Inst, Decoder))
3077 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3078 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3079}
3080
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3081static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3082 uint64_t Address, const void *Decoder) {
3083 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3084 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3085
3086 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3087 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3088}
3089
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3090static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3091DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3092 uint64_t Address, const void *Decoder) {
3093 DecodeStatus S = MCDisassembler::Success;
3094
3095 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3096 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3097
3098 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3100 return MCDisassembler::Fail;
3101 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3102 return MCDisassembler::Fail;
3103 return S;
3104}
3105
3106static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3107DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3108 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3109 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3110
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3111 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3112 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3113 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3114 switch (opc) {
3115 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3116 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3117 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3118 Inst.setOpcode(ARM::t2DSB);
3119 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3120 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3121 Inst.setOpcode(ARM::t2DMB);
3122 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3123 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3124 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3125 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3126 }
3127
3128 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3129 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3130 }
3131
3132 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3133 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3134 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3135 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3136 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3137
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3138 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3139 return MCDisassembler::Fail;
3140 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3141 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3142
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3143 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3144}
3145
3146// Decode a shifted immediate operand. These basically consist
3147// of an 8-bit value, and a 4-bit directive that specifies either
3148// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3149static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3150 uint64_t Address, const void *Decoder) {
3151 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3152 if (ctrl == 0) {
3153 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3154 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3155 switch (byte) {
3156 case 0:
3157 Inst.addOperand(MCOperand::CreateImm(imm));
3158 break;
3159 case 1:
3160 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3161 break;
3162 case 2:
3163 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3164 break;
3165 case 3:
3166 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3167 (imm << 8) | imm));
3168 break;
3169 }
3170 } else {
3171 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3172 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3173 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3174 Inst.addOperand(MCOperand::CreateImm(imm));
3175 }
3176
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3177 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3178}
3179
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3180static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3181DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3182 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3183 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3184 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3185}
3186
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3187static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3188 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3189 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3190 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3191}
3192
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3193static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3194 uint64_t Address, const void *Decoder) {
3195 switch (Val) {
3196 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3197 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3198 case 0xF: // SY
3199 case 0xE: // ST
3200 case 0xB: // ISH
3201 case 0xA: // ISHST
3202 case 0x7: // NSH
3203 case 0x6: // NSHST
3204 case 0x3: // OSH
3205 case 0x2: // OSHST
3206 break;
3207 }
3208
3209 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3210 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3211}
3212
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3213static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3214 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3215 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3216 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3217 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3218}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3219
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3221 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3222 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3223
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3224 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3225 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3226 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3227
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3228 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3231 return MCDisassembler::Fail;
3232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3233 return MCDisassembler::Fail;
3234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3235 return MCDisassembler::Fail;
3236 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3237 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3238
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3239 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3240}
3241
3242
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3243static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3244 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3245 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3246
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3247 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3248 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3249 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3250 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3251
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3252 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3253 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3254
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3255 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3256 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3257
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3259 return MCDisassembler::Fail;
3260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3261 return MCDisassembler::Fail;
3262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3263 return MCDisassembler::Fail;
3264 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3265 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3266
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3267 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3268}
3269
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3270static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3271 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3272 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3273
3274 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3275 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3276 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3277 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3278 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3279 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3280
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3281 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3282
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3284 return MCDisassembler::Fail;
3285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3286 return MCDisassembler::Fail;
3287 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3288 return MCDisassembler::Fail;
3289 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3290 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3291
3292 return S;
3293}
3294
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3295static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3296 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3297 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3298
3299 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3300 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3301 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3302 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3303 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3304 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3305 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3306
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3307 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3308 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3309
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3311 return MCDisassembler::Fail;
3312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3313 return MCDisassembler::Fail;
3314 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3315 return MCDisassembler::Fail;
3316 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3317 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3318
3319 return S;
3320}
3321
3322
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3323static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3324 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3325 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3326
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3327 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3328 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3329 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3330 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3331 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3332 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3333
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3334 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3335
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3337 return MCDisassembler::Fail;
3338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3339 return MCDisassembler::Fail;
3340 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3341 return MCDisassembler::Fail;
3342 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3343 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3344
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3345 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3346}
3347
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3348static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3349 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3350 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3351
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3352 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3353 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3354 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3355 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3356 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3357 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3358
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3359 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3360
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3362 return MCDisassembler::Fail;
3363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3364 return MCDisassembler::Fail;
3365 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3366 return MCDisassembler::Fail;
3367 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3368 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3369
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3370 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3371}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3372
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3373static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3374 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3375 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3376
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3377 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3378 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3379 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3380 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3381 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3382
3383 unsigned align = 0;
3384 unsigned index = 0;
3385 switch (size) {
3386 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3387 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3388 case 0:
3389 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3390 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3391 index = fieldFromInstruction32(Insn, 5, 3);
3392 break;
3393 case 1:
3394 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3395 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3396 index = fieldFromInstruction32(Insn, 6, 2);
3397 if (fieldFromInstruction32(Insn, 4, 1))
3398 align = 2;
3399 break;
3400 case 2:
3401 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3402 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3403 index = fieldFromInstruction32(Insn, 7, 1);
3404 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3405 align = 4;
3406 }
3407
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3408 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3409 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3410 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3412 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3413 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3415 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3416 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3417 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3418 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3420 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3421 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3422 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3423 }
3424
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3425 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3426 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3427 Inst.addOperand(MCOperand::CreateImm(index));
3428
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3429 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3430}
3431
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3432static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3433 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3434 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3435
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3436 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3437 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3438 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3439 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3440 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3441
3442 unsigned align = 0;
3443 unsigned index = 0;
3444 switch (size) {
3445 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3446 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3447 case 0:
3448 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3449 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3450 index = fieldFromInstruction32(Insn, 5, 3);
3451 break;
3452 case 1:
3453 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3454 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3455 index = fieldFromInstruction32(Insn, 6, 2);
3456 if (fieldFromInstruction32(Insn, 4, 1))
3457 align = 2;
3458 break;
3459 case 2:
3460 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3461 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3462 index = fieldFromInstruction32(Insn, 7, 1);
3463 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3464 align = 4;
3465 }
3466
3467 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3469 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3470 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3472 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3473 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3474 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3475 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3476 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3477 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3478 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3479 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3480 }
3481
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3482 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3483 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3484 Inst.addOperand(MCOperand::CreateImm(index));
3485
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3486 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3487}
3488
3489
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3490static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3491 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3492 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3493
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3494 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3495 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3496 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3497 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3498 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3499
3500 unsigned align = 0;
3501 unsigned index = 0;
3502 unsigned inc = 1;
3503 switch (size) {
3504 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3505 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3506 case 0:
3507 index = fieldFromInstruction32(Insn, 5, 3);
3508 if (fieldFromInstruction32(Insn, 4, 1))
3509 align = 2;
3510 break;
3511 case 1:
3512 index = fieldFromInstruction32(Insn, 6, 2);
3513 if (fieldFromInstruction32(Insn, 4, 1))
3514 align = 4;
3515 if (fieldFromInstruction32(Insn, 5, 1))
3516 inc = 2;
3517 break;
3518 case 2:
3519 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3520 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3521 index = fieldFromInstruction32(Insn, 7, 1);
3522 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3523 align = 8;
3524 if (fieldFromInstruction32(Insn, 6, 1))
3525 inc = 2;
3526 break;
3527 }
3528
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3529 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3530 return MCDisassembler::Fail;
3531 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3532 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3533 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3535 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3536 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3538 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3539 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3540 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3541 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3543 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3544 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3545 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3546 }
3547
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3548 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3549 return MCDisassembler::Fail;
3550 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3551 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3552 Inst.addOperand(MCOperand::CreateImm(index));
3553
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3554 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3555}
3556
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3557static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3558 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3559 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3560
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3561 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3562 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3563 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3564 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3565 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3566
3567 unsigned align = 0;
3568 unsigned index = 0;
3569 unsigned inc = 1;
3570 switch (size) {
3571 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3572 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3573 case 0:
3574 index = fieldFromInstruction32(Insn, 5, 3);
3575 if (fieldFromInstruction32(Insn, 4, 1))
3576 align = 2;
3577 break;
3578 case 1:
3579 index = fieldFromInstruction32(Insn, 6, 2);
3580 if (fieldFromInstruction32(Insn, 4, 1))
3581 align = 4;
3582 if (fieldFromInstruction32(Insn, 5, 1))
3583 inc = 2;
3584 break;
3585 case 2:
3586 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3587 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3588 index = fieldFromInstruction32(Insn, 7, 1);
3589 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3590 align = 8;
3591 if (fieldFromInstruction32(Insn, 6, 1))
3592 inc = 2;
3593 break;
3594 }
3595
3596 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3598 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3599 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3600 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3601 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3602 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3603 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3604 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3606 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3607 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3608 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3609 }
3610
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3611 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3612 return MCDisassembler::Fail;
3613 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3614 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3615 Inst.addOperand(MCOperand::CreateImm(index));
3616
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3617 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3618}
3619
3620
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3621static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3622 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3623 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3624
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3625 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3626 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3627 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3628 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3629 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3630
3631 unsigned align = 0;
3632 unsigned index = 0;
3633 unsigned inc = 1;
3634 switch (size) {
3635 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3636 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3637 case 0:
3638 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3639 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3640 index = fieldFromInstruction32(Insn, 5, 3);
3641 break;
3642 case 1:
3643 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3644 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3645 index = fieldFromInstruction32(Insn, 6, 2);
3646 if (fieldFromInstruction32(Insn, 5, 1))
3647 inc = 2;
3648 break;
3649 case 2:
3650 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3651 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3652 index = fieldFromInstruction32(Insn, 7, 1);
3653 if (fieldFromInstruction32(Insn, 6, 1))
3654 inc = 2;
3655 break;
3656 }
3657
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3659 return MCDisassembler::Fail;
3660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3661 return MCDisassembler::Fail;
3662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3663 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3664
3665 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3667 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3668 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3670 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3671 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3672 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3673 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3675 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3676 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3677 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3678 }
3679
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3681 return MCDisassembler::Fail;
3682 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3683 return MCDisassembler::Fail;
3684 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3685 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3686 Inst.addOperand(MCOperand::CreateImm(index));
3687
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3688 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3689}
3690
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3691static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3692 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3693 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3694
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3695 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3696 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3697 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3698 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3699 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3700
3701 unsigned align = 0;
3702 unsigned index = 0;
3703 unsigned inc = 1;
3704 switch (size) {
3705 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3706 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3707 case 0:
3708 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3709 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3710 index = fieldFromInstruction32(Insn, 5, 3);
3711 break;
3712 case 1:
3713 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3714 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3715 index = fieldFromInstruction32(Insn, 6, 2);
3716 if (fieldFromInstruction32(Insn, 5, 1))
3717 inc = 2;
3718 break;
3719 case 2:
3720 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3721 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3722 index = fieldFromInstruction32(Insn, 7, 1);
3723 if (fieldFromInstruction32(Insn, 6, 1))
3724 inc = 2;
3725 break;
3726 }
3727
3728 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3730 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3731 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3733 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3734 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3735 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3736 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3738 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3739 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3740 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3741 }
3742
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3744 return MCDisassembler::Fail;
3745 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3746 return MCDisassembler::Fail;
3747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3748 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3749 Inst.addOperand(MCOperand::CreateImm(index));
3750
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3751 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3752}
3753
3754
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3755static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3756 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3757 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3758
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3759 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3760 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3761 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3762 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3763 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3764
3765 unsigned align = 0;
3766 unsigned index = 0;
3767 unsigned inc = 1;
3768 switch (size) {
3769 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3770 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3771 case 0:
3772 if (fieldFromInstruction32(Insn, 4, 1))
3773 align = 4;
3774 index = fieldFromInstruction32(Insn, 5, 3);
3775 break;
3776 case 1:
3777 if (fieldFromInstruction32(Insn, 4, 1))
3778 align = 8;
3779 index = fieldFromInstruction32(Insn, 6, 2);
3780 if (fieldFromInstruction32(Insn, 5, 1))
3781 inc = 2;
3782 break;
3783 case 2:
3784 if (fieldFromInstruction32(Insn, 4, 2))
3785 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3786 index = fieldFromInstruction32(Insn, 7, 1);
3787 if (fieldFromInstruction32(Insn, 6, 1))
3788 inc = 2;
3789 break;
3790 }
3791
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3793 return MCDisassembler::Fail;
3794 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3795 return MCDisassembler::Fail;
3796 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3797 return MCDisassembler::Fail;
3798 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3799 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3800
3801 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3803 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3804 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3806 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3807 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3808 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3809 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3811 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3812 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3813 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3814 }
3815
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3816 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3817 return MCDisassembler::Fail;
3818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3819 return MCDisassembler::Fail;
3820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3821 return MCDisassembler::Fail;
3822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3823 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3824 Inst.addOperand(MCOperand::CreateImm(index));
3825
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3826 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3827}
3828
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3829static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3830 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3831 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3832
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3833 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3834 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3835 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3836 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3837 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3838
3839 unsigned align = 0;
3840 unsigned index = 0;
3841 unsigned inc = 1;
3842 switch (size) {
3843 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3844 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3845 case 0:
3846 if (fieldFromInstruction32(Insn, 4, 1))
3847 align = 4;
3848 index = fieldFromInstruction32(Insn, 5, 3);
3849 break;
3850 case 1:
3851 if (fieldFromInstruction32(Insn, 4, 1))
3852 align = 8;
3853 index = fieldFromInstruction32(Insn, 6, 2);
3854 if (fieldFromInstruction32(Insn, 5, 1))
3855 inc = 2;
3856 break;
3857 case 2:
3858 if (fieldFromInstruction32(Insn, 4, 2))
3859 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3860 index = fieldFromInstruction32(Insn, 7, 1);
3861 if (fieldFromInstruction32(Insn, 6, 1))
3862 inc = 2;
3863 break;
3864 }
3865
3866 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3868 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3869 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3871 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3872 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3873 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3874 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3876 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3877 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3878 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3879 }
3880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3882 return MCDisassembler::Fail;
3883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3884 return MCDisassembler::Fail;
3885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3886 return MCDisassembler::Fail;
3887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3888 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3889 Inst.addOperand(MCOperand::CreateImm(index));
3890
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3891 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3892}
3893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3894static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3895 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3896 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3897 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3898 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3899 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3900 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3901 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3902
3903 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3904 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3905
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3906 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3907 return MCDisassembler::Fail;
3908 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3909 return MCDisassembler::Fail;
3910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3911 return MCDisassembler::Fail;
3912 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3913 return MCDisassembler::Fail;
3914 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3915 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3916
3917 return S;
3918}
3919
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3920static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3921 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3922 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3923 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3924 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3925 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3926 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3927 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3928
3929 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3930 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3931
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3933 return MCDisassembler::Fail;
3934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3935 return MCDisassembler::Fail;
3936 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3937 return MCDisassembler::Fail;
3938 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3939 return MCDisassembler::Fail;
3940 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3941 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3942
3943 return S;
3944}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3945
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3946static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3947 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3948 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3949 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3950 // The InstPrinter needs to have the low bit of the predicate in
3951 // the mask operand to be able to print it properly.
3952 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3953
3954 if (pred == 0xF) {
3955 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3956 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3957 }
3958
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3959 if ((mask & 0xF) == 0) {
3960 // Preserve the high bit of the mask, which is the low bit of
3961 // the predicate.
3962 mask &= 0x10;
3963 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3964 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3965 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3966
3967 Inst.addOperand(MCOperand::CreateImm(pred));
3968 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3969 return S;
3970}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3971
3972static DecodeStatus
3973DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3974 uint64_t Address, const void *Decoder) {
3975 DecodeStatus S = MCDisassembler::Success;
3976
3977 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3978 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3979 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3980 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3981 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3982 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3983 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3984 bool writeback = (W == 1) | (P == 0);
3985
3986 addr |= (U << 8) | (Rn << 9);
3987
3988 if (writeback && (Rn == Rt || Rn == Rt2))
3989 Check(S, MCDisassembler::SoftFail);
3990 if (Rt == Rt2)
3991 Check(S, MCDisassembler::SoftFail);
3992
3993 // Rt
3994 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3995 return MCDisassembler::Fail;
3996 // Rt2
3997 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3998 return MCDisassembler::Fail;
3999 // Writeback operand
4000 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4001 return MCDisassembler::Fail;
4002 // addr
4003 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4004 return MCDisassembler::Fail;
4005
4006 return S;
4007}
4008
4009static DecodeStatus
4010DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4011 uint64_t Address, const void *Decoder) {
4012 DecodeStatus S = MCDisassembler::Success;
4013
4014 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4015 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4016 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4017 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4018 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4019 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4020 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4021 bool writeback = (W == 1) | (P == 0);
4022
4023 addr |= (U << 8) | (Rn << 9);
4024
4025 if (writeback && (Rn == Rt || Rn == Rt2))
4026 Check(S, MCDisassembler::SoftFail);
4027
4028 // Writeback operand
4029 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4030 return MCDisassembler::Fail;
4031 // Rt
4032 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4033 return MCDisassembler::Fail;
4034 // Rt2
4035 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4036 return MCDisassembler::Fail;
4037 // addr
4038 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4039 return MCDisassembler::Fail;
4040
4041 return S;
4042}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4043
4044static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4045 uint64_t Address, const void *Decoder) {
4046 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4047 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4048 if (sign1 != sign2) return MCDisassembler::Fail;
4049
4050 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4051 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4052 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4053 Val |= sign1 << 12;
4054 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4055
4056 return MCDisassembler::Success;
4057}
4058
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4059static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4060 uint64_t Address,
4061 const void *Decoder) {
4062 DecodeStatus S = MCDisassembler::Success;
4063
4064 // Shift of "asr #32" is not allowed in Thumb2 mode.
4065 if (Val == 0x20) S = MCDisassembler::SoftFail;
4066 Inst.addOperand(MCOperand::CreateImm(Val));
4067 return S;
4068}
4069
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4070static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
4071 uint64_t Address, const void *Decoder) {
4072 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4073 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4074 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4075 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4076
4077 if (pred == 0xF)
4078 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4079
4080 DecodeStatus S = MCDisassembler::Success;
4081 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4082 return MCDisassembler::Fail;
4083 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4084 return MCDisassembler::Fail;
4085 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4086 return MCDisassembler::Fail;
4087 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4088 return MCDisassembler::Fail;
4089
4090 return S;
4091}