Misha Brukman | a85d6bc | 2002-11-22 22:42:50 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 2 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 7 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 9 | // |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 10 | // This file contains the X86 implementation of the TargetInstrInfo class. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Chris Lattner | 055c965 | 2002-10-29 21:05:24 +0000 | [diff] [blame] | 14 | #include "X86InstrInfo.h" |
Chris Lattner | 4ce42a7 | 2002-12-03 05:42:53 +0000 | [diff] [blame] | 15 | #include "X86.h" |
Chris Lattner | abf05b2 | 2003-08-03 21:55:55 +0000 | [diff] [blame] | 16 | #include "X86GenInstrInfo.inc" |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 17 | #include "X86InstrBuilder.h" |
Owen Anderson | d94b6a1 | 2008-01-04 23:57:37 +0000 | [diff] [blame] | 18 | #include "X86MachineFunctionInfo.h" |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 19 | #include "X86Subtarget.h" |
| 20 | #include "X86TargetMachine.h" |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 21 | #include "llvm/ADT/STLExtras.h" |
Owen Anderson | d94b6a1 | 2008-01-04 23:57:37 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/LiveVariables.h" |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 26 | #include "llvm/Support/CommandLine.h" |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 27 | #include "llvm/Target/TargetOptions.h" |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 28 | |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 29 | using namespace llvm; |
| 30 | |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 31 | namespace { |
| 32 | cl::opt<bool> |
| 33 | NoFusing("disable-spill-fusing", |
| 34 | cl::desc("Disable fusing of spill code into instructions")); |
| 35 | cl::opt<bool> |
| 36 | PrintFailedFusing("print-failed-fuse-candidates", |
| 37 | cl::desc("Print instructions that the allocator wants to" |
| 38 | " fuse, but the X86 backend currently can't"), |
| 39 | cl::Hidden); |
Evan Cheng | d8850a5 | 2008-02-22 09:25:47 +0000 | [diff] [blame] | 40 | cl::opt<bool> |
| 41 | ReMatPICLoad("remat-pic-load", |
| 42 | cl::desc("Allow rematerializing pic load"), |
Evan Cheng | c19eca3 | 2008-02-23 02:07:42 +0000 | [diff] [blame] | 43 | cl::init(true), cl::Hidden); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 44 | } |
| 45 | |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 46 | X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) |
Chris Lattner | 6410552 | 2008-01-01 01:03:04 +0000 | [diff] [blame] | 47 | : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 48 | TM(tm), RI(tm, *this) { |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 49 | SmallVector<unsigned,16> AmbEntries; |
| 50 | static const unsigned OpTbl2Addr[][2] = { |
| 51 | { X86::ADC32ri, X86::ADC32mi }, |
| 52 | { X86::ADC32ri8, X86::ADC32mi8 }, |
| 53 | { X86::ADC32rr, X86::ADC32mr }, |
| 54 | { X86::ADC64ri32, X86::ADC64mi32 }, |
| 55 | { X86::ADC64ri8, X86::ADC64mi8 }, |
| 56 | { X86::ADC64rr, X86::ADC64mr }, |
| 57 | { X86::ADD16ri, X86::ADD16mi }, |
| 58 | { X86::ADD16ri8, X86::ADD16mi8 }, |
| 59 | { X86::ADD16rr, X86::ADD16mr }, |
| 60 | { X86::ADD32ri, X86::ADD32mi }, |
| 61 | { X86::ADD32ri8, X86::ADD32mi8 }, |
| 62 | { X86::ADD32rr, X86::ADD32mr }, |
| 63 | { X86::ADD64ri32, X86::ADD64mi32 }, |
| 64 | { X86::ADD64ri8, X86::ADD64mi8 }, |
| 65 | { X86::ADD64rr, X86::ADD64mr }, |
| 66 | { X86::ADD8ri, X86::ADD8mi }, |
| 67 | { X86::ADD8rr, X86::ADD8mr }, |
| 68 | { X86::AND16ri, X86::AND16mi }, |
| 69 | { X86::AND16ri8, X86::AND16mi8 }, |
| 70 | { X86::AND16rr, X86::AND16mr }, |
| 71 | { X86::AND32ri, X86::AND32mi }, |
| 72 | { X86::AND32ri8, X86::AND32mi8 }, |
| 73 | { X86::AND32rr, X86::AND32mr }, |
| 74 | { X86::AND64ri32, X86::AND64mi32 }, |
| 75 | { X86::AND64ri8, X86::AND64mi8 }, |
| 76 | { X86::AND64rr, X86::AND64mr }, |
| 77 | { X86::AND8ri, X86::AND8mi }, |
| 78 | { X86::AND8rr, X86::AND8mr }, |
| 79 | { X86::DEC16r, X86::DEC16m }, |
| 80 | { X86::DEC32r, X86::DEC32m }, |
| 81 | { X86::DEC64_16r, X86::DEC64_16m }, |
| 82 | { X86::DEC64_32r, X86::DEC64_32m }, |
| 83 | { X86::DEC64r, X86::DEC64m }, |
| 84 | { X86::DEC8r, X86::DEC8m }, |
| 85 | { X86::INC16r, X86::INC16m }, |
| 86 | { X86::INC32r, X86::INC32m }, |
| 87 | { X86::INC64_16r, X86::INC64_16m }, |
| 88 | { X86::INC64_32r, X86::INC64_32m }, |
| 89 | { X86::INC64r, X86::INC64m }, |
| 90 | { X86::INC8r, X86::INC8m }, |
| 91 | { X86::NEG16r, X86::NEG16m }, |
| 92 | { X86::NEG32r, X86::NEG32m }, |
| 93 | { X86::NEG64r, X86::NEG64m }, |
| 94 | { X86::NEG8r, X86::NEG8m }, |
| 95 | { X86::NOT16r, X86::NOT16m }, |
| 96 | { X86::NOT32r, X86::NOT32m }, |
| 97 | { X86::NOT64r, X86::NOT64m }, |
| 98 | { X86::NOT8r, X86::NOT8m }, |
| 99 | { X86::OR16ri, X86::OR16mi }, |
| 100 | { X86::OR16ri8, X86::OR16mi8 }, |
| 101 | { X86::OR16rr, X86::OR16mr }, |
| 102 | { X86::OR32ri, X86::OR32mi }, |
| 103 | { X86::OR32ri8, X86::OR32mi8 }, |
| 104 | { X86::OR32rr, X86::OR32mr }, |
| 105 | { X86::OR64ri32, X86::OR64mi32 }, |
| 106 | { X86::OR64ri8, X86::OR64mi8 }, |
| 107 | { X86::OR64rr, X86::OR64mr }, |
| 108 | { X86::OR8ri, X86::OR8mi }, |
| 109 | { X86::OR8rr, X86::OR8mr }, |
| 110 | { X86::ROL16r1, X86::ROL16m1 }, |
| 111 | { X86::ROL16rCL, X86::ROL16mCL }, |
| 112 | { X86::ROL16ri, X86::ROL16mi }, |
| 113 | { X86::ROL32r1, X86::ROL32m1 }, |
| 114 | { X86::ROL32rCL, X86::ROL32mCL }, |
| 115 | { X86::ROL32ri, X86::ROL32mi }, |
| 116 | { X86::ROL64r1, X86::ROL64m1 }, |
| 117 | { X86::ROL64rCL, X86::ROL64mCL }, |
| 118 | { X86::ROL64ri, X86::ROL64mi }, |
| 119 | { X86::ROL8r1, X86::ROL8m1 }, |
| 120 | { X86::ROL8rCL, X86::ROL8mCL }, |
| 121 | { X86::ROL8ri, X86::ROL8mi }, |
| 122 | { X86::ROR16r1, X86::ROR16m1 }, |
| 123 | { X86::ROR16rCL, X86::ROR16mCL }, |
| 124 | { X86::ROR16ri, X86::ROR16mi }, |
| 125 | { X86::ROR32r1, X86::ROR32m1 }, |
| 126 | { X86::ROR32rCL, X86::ROR32mCL }, |
| 127 | { X86::ROR32ri, X86::ROR32mi }, |
| 128 | { X86::ROR64r1, X86::ROR64m1 }, |
| 129 | { X86::ROR64rCL, X86::ROR64mCL }, |
| 130 | { X86::ROR64ri, X86::ROR64mi }, |
| 131 | { X86::ROR8r1, X86::ROR8m1 }, |
| 132 | { X86::ROR8rCL, X86::ROR8mCL }, |
| 133 | { X86::ROR8ri, X86::ROR8mi }, |
| 134 | { X86::SAR16r1, X86::SAR16m1 }, |
| 135 | { X86::SAR16rCL, X86::SAR16mCL }, |
| 136 | { X86::SAR16ri, X86::SAR16mi }, |
| 137 | { X86::SAR32r1, X86::SAR32m1 }, |
| 138 | { X86::SAR32rCL, X86::SAR32mCL }, |
| 139 | { X86::SAR32ri, X86::SAR32mi }, |
| 140 | { X86::SAR64r1, X86::SAR64m1 }, |
| 141 | { X86::SAR64rCL, X86::SAR64mCL }, |
| 142 | { X86::SAR64ri, X86::SAR64mi }, |
| 143 | { X86::SAR8r1, X86::SAR8m1 }, |
| 144 | { X86::SAR8rCL, X86::SAR8mCL }, |
| 145 | { X86::SAR8ri, X86::SAR8mi }, |
| 146 | { X86::SBB32ri, X86::SBB32mi }, |
| 147 | { X86::SBB32ri8, X86::SBB32mi8 }, |
| 148 | { X86::SBB32rr, X86::SBB32mr }, |
| 149 | { X86::SBB64ri32, X86::SBB64mi32 }, |
| 150 | { X86::SBB64ri8, X86::SBB64mi8 }, |
| 151 | { X86::SBB64rr, X86::SBB64mr }, |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 152 | { X86::SHL16rCL, X86::SHL16mCL }, |
| 153 | { X86::SHL16ri, X86::SHL16mi }, |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 154 | { X86::SHL32rCL, X86::SHL32mCL }, |
| 155 | { X86::SHL32ri, X86::SHL32mi }, |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 156 | { X86::SHL64rCL, X86::SHL64mCL }, |
| 157 | { X86::SHL64ri, X86::SHL64mi }, |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 158 | { X86::SHL8rCL, X86::SHL8mCL }, |
| 159 | { X86::SHL8ri, X86::SHL8mi }, |
| 160 | { X86::SHLD16rrCL, X86::SHLD16mrCL }, |
| 161 | { X86::SHLD16rri8, X86::SHLD16mri8 }, |
| 162 | { X86::SHLD32rrCL, X86::SHLD32mrCL }, |
| 163 | { X86::SHLD32rri8, X86::SHLD32mri8 }, |
| 164 | { X86::SHLD64rrCL, X86::SHLD64mrCL }, |
| 165 | { X86::SHLD64rri8, X86::SHLD64mri8 }, |
| 166 | { X86::SHR16r1, X86::SHR16m1 }, |
| 167 | { X86::SHR16rCL, X86::SHR16mCL }, |
| 168 | { X86::SHR16ri, X86::SHR16mi }, |
| 169 | { X86::SHR32r1, X86::SHR32m1 }, |
| 170 | { X86::SHR32rCL, X86::SHR32mCL }, |
| 171 | { X86::SHR32ri, X86::SHR32mi }, |
| 172 | { X86::SHR64r1, X86::SHR64m1 }, |
| 173 | { X86::SHR64rCL, X86::SHR64mCL }, |
| 174 | { X86::SHR64ri, X86::SHR64mi }, |
| 175 | { X86::SHR8r1, X86::SHR8m1 }, |
| 176 | { X86::SHR8rCL, X86::SHR8mCL }, |
| 177 | { X86::SHR8ri, X86::SHR8mi }, |
| 178 | { X86::SHRD16rrCL, X86::SHRD16mrCL }, |
| 179 | { X86::SHRD16rri8, X86::SHRD16mri8 }, |
| 180 | { X86::SHRD32rrCL, X86::SHRD32mrCL }, |
| 181 | { X86::SHRD32rri8, X86::SHRD32mri8 }, |
| 182 | { X86::SHRD64rrCL, X86::SHRD64mrCL }, |
| 183 | { X86::SHRD64rri8, X86::SHRD64mri8 }, |
| 184 | { X86::SUB16ri, X86::SUB16mi }, |
| 185 | { X86::SUB16ri8, X86::SUB16mi8 }, |
| 186 | { X86::SUB16rr, X86::SUB16mr }, |
| 187 | { X86::SUB32ri, X86::SUB32mi }, |
| 188 | { X86::SUB32ri8, X86::SUB32mi8 }, |
| 189 | { X86::SUB32rr, X86::SUB32mr }, |
| 190 | { X86::SUB64ri32, X86::SUB64mi32 }, |
| 191 | { X86::SUB64ri8, X86::SUB64mi8 }, |
| 192 | { X86::SUB64rr, X86::SUB64mr }, |
| 193 | { X86::SUB8ri, X86::SUB8mi }, |
| 194 | { X86::SUB8rr, X86::SUB8mr }, |
| 195 | { X86::XOR16ri, X86::XOR16mi }, |
| 196 | { X86::XOR16ri8, X86::XOR16mi8 }, |
| 197 | { X86::XOR16rr, X86::XOR16mr }, |
| 198 | { X86::XOR32ri, X86::XOR32mi }, |
| 199 | { X86::XOR32ri8, X86::XOR32mi8 }, |
| 200 | { X86::XOR32rr, X86::XOR32mr }, |
| 201 | { X86::XOR64ri32, X86::XOR64mi32 }, |
| 202 | { X86::XOR64ri8, X86::XOR64mi8 }, |
| 203 | { X86::XOR64rr, X86::XOR64mr }, |
| 204 | { X86::XOR8ri, X86::XOR8mi }, |
| 205 | { X86::XOR8rr, X86::XOR8mr } |
| 206 | }; |
| 207 | |
| 208 | for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { |
| 209 | unsigned RegOp = OpTbl2Addr[i][0]; |
| 210 | unsigned MemOp = OpTbl2Addr[i][1]; |
| 211 | if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 212 | assert(false && "Duplicated entries?"); |
| 213 | unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store |
| 214 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 215 | std::make_pair(RegOp, AuxInfo)))) |
| 216 | AmbEntries.push_back(MemOp); |
| 217 | } |
| 218 | |
| 219 | // If the third value is 1, then it's folding either a load or a store. |
| 220 | static const unsigned OpTbl0[][3] = { |
| 221 | { X86::CALL32r, X86::CALL32m, 1 }, |
| 222 | { X86::CALL64r, X86::CALL64m, 1 }, |
| 223 | { X86::CMP16ri, X86::CMP16mi, 1 }, |
| 224 | { X86::CMP16ri8, X86::CMP16mi8, 1 }, |
| 225 | { X86::CMP32ri, X86::CMP32mi, 1 }, |
| 226 | { X86::CMP32ri8, X86::CMP32mi8, 1 }, |
| 227 | { X86::CMP64ri32, X86::CMP64mi32, 1 }, |
| 228 | { X86::CMP64ri8, X86::CMP64mi8, 1 }, |
| 229 | { X86::CMP8ri, X86::CMP8mi, 1 }, |
| 230 | { X86::DIV16r, X86::DIV16m, 1 }, |
| 231 | { X86::DIV32r, X86::DIV32m, 1 }, |
| 232 | { X86::DIV64r, X86::DIV64m, 1 }, |
| 233 | { X86::DIV8r, X86::DIV8m, 1 }, |
| 234 | { X86::FsMOVAPDrr, X86::MOVSDmr, 0 }, |
| 235 | { X86::FsMOVAPSrr, X86::MOVSSmr, 0 }, |
| 236 | { X86::IDIV16r, X86::IDIV16m, 1 }, |
| 237 | { X86::IDIV32r, X86::IDIV32m, 1 }, |
| 238 | { X86::IDIV64r, X86::IDIV64m, 1 }, |
| 239 | { X86::IDIV8r, X86::IDIV8m, 1 }, |
| 240 | { X86::IMUL16r, X86::IMUL16m, 1 }, |
| 241 | { X86::IMUL32r, X86::IMUL32m, 1 }, |
| 242 | { X86::IMUL64r, X86::IMUL64m, 1 }, |
| 243 | { X86::IMUL8r, X86::IMUL8m, 1 }, |
| 244 | { X86::JMP32r, X86::JMP32m, 1 }, |
| 245 | { X86::JMP64r, X86::JMP64m, 1 }, |
| 246 | { X86::MOV16ri, X86::MOV16mi, 0 }, |
| 247 | { X86::MOV16rr, X86::MOV16mr, 0 }, |
| 248 | { X86::MOV16to16_, X86::MOV16_mr, 0 }, |
| 249 | { X86::MOV32ri, X86::MOV32mi, 0 }, |
| 250 | { X86::MOV32rr, X86::MOV32mr, 0 }, |
| 251 | { X86::MOV32to32_, X86::MOV32_mr, 0 }, |
| 252 | { X86::MOV64ri32, X86::MOV64mi32, 0 }, |
| 253 | { X86::MOV64rr, X86::MOV64mr, 0 }, |
| 254 | { X86::MOV8ri, X86::MOV8mi, 0 }, |
| 255 | { X86::MOV8rr, X86::MOV8mr, 0 }, |
| 256 | { X86::MOVAPDrr, X86::MOVAPDmr, 0 }, |
| 257 | { X86::MOVAPSrr, X86::MOVAPSmr, 0 }, |
| 258 | { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 }, |
| 259 | { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 }, |
| 260 | { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 }, |
| 261 | { X86::MOVSDrr, X86::MOVSDmr, 0 }, |
| 262 | { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 }, |
| 263 | { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 }, |
| 264 | { X86::MOVSSrr, X86::MOVSSmr, 0 }, |
| 265 | { X86::MOVUPDrr, X86::MOVUPDmr, 0 }, |
| 266 | { X86::MOVUPSrr, X86::MOVUPSmr, 0 }, |
| 267 | { X86::MUL16r, X86::MUL16m, 1 }, |
| 268 | { X86::MUL32r, X86::MUL32m, 1 }, |
| 269 | { X86::MUL64r, X86::MUL64m, 1 }, |
| 270 | { X86::MUL8r, X86::MUL8m, 1 }, |
| 271 | { X86::SETAEr, X86::SETAEm, 0 }, |
| 272 | { X86::SETAr, X86::SETAm, 0 }, |
| 273 | { X86::SETBEr, X86::SETBEm, 0 }, |
| 274 | { X86::SETBr, X86::SETBm, 0 }, |
| 275 | { X86::SETEr, X86::SETEm, 0 }, |
| 276 | { X86::SETGEr, X86::SETGEm, 0 }, |
| 277 | { X86::SETGr, X86::SETGm, 0 }, |
| 278 | { X86::SETLEr, X86::SETLEm, 0 }, |
| 279 | { X86::SETLr, X86::SETLm, 0 }, |
| 280 | { X86::SETNEr, X86::SETNEm, 0 }, |
| 281 | { X86::SETNPr, X86::SETNPm, 0 }, |
| 282 | { X86::SETNSr, X86::SETNSm, 0 }, |
| 283 | { X86::SETPr, X86::SETPm, 0 }, |
| 284 | { X86::SETSr, X86::SETSm, 0 }, |
| 285 | { X86::TAILJMPr, X86::TAILJMPm, 1 }, |
| 286 | { X86::TEST16ri, X86::TEST16mi, 1 }, |
| 287 | { X86::TEST32ri, X86::TEST32mi, 1 }, |
| 288 | { X86::TEST64ri32, X86::TEST64mi32, 1 }, |
Chris Lattner | f9b3f37 | 2008-01-11 18:00:50 +0000 | [diff] [blame] | 289 | { X86::TEST8ri, X86::TEST8mi, 1 } |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { |
| 293 | unsigned RegOp = OpTbl0[i][0]; |
| 294 | unsigned MemOp = OpTbl0[i][1]; |
| 295 | if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 296 | assert(false && "Duplicated entries?"); |
| 297 | unsigned FoldedLoad = OpTbl0[i][2]; |
| 298 | // Index 0, folded load or store. |
| 299 | unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); |
| 300 | if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) |
| 301 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 302 | std::make_pair(RegOp, AuxInfo)))) |
| 303 | AmbEntries.push_back(MemOp); |
| 304 | } |
| 305 | |
| 306 | static const unsigned OpTbl1[][2] = { |
| 307 | { X86::CMP16rr, X86::CMP16rm }, |
| 308 | { X86::CMP32rr, X86::CMP32rm }, |
| 309 | { X86::CMP64rr, X86::CMP64rm }, |
| 310 | { X86::CMP8rr, X86::CMP8rm }, |
| 311 | { X86::CVTSD2SSrr, X86::CVTSD2SSrm }, |
| 312 | { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm }, |
| 313 | { X86::CVTSI2SDrr, X86::CVTSI2SDrm }, |
| 314 | { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm }, |
| 315 | { X86::CVTSI2SSrr, X86::CVTSI2SSrm }, |
| 316 | { X86::CVTSS2SDrr, X86::CVTSS2SDrm }, |
| 317 | { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm }, |
| 318 | { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm }, |
| 319 | { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm }, |
| 320 | { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm }, |
| 321 | { X86::FsMOVAPDrr, X86::MOVSDrm }, |
| 322 | { X86::FsMOVAPSrr, X86::MOVSSrm }, |
| 323 | { X86::IMUL16rri, X86::IMUL16rmi }, |
| 324 | { X86::IMUL16rri8, X86::IMUL16rmi8 }, |
| 325 | { X86::IMUL32rri, X86::IMUL32rmi }, |
| 326 | { X86::IMUL32rri8, X86::IMUL32rmi8 }, |
| 327 | { X86::IMUL64rri32, X86::IMUL64rmi32 }, |
| 328 | { X86::IMUL64rri8, X86::IMUL64rmi8 }, |
| 329 | { X86::Int_CMPSDrr, X86::Int_CMPSDrm }, |
| 330 | { X86::Int_CMPSSrr, X86::Int_CMPSSrm }, |
| 331 | { X86::Int_COMISDrr, X86::Int_COMISDrm }, |
| 332 | { X86::Int_COMISSrr, X86::Int_COMISSrm }, |
| 333 | { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm }, |
| 334 | { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm }, |
| 335 | { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm }, |
| 336 | { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm }, |
| 337 | { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm }, |
| 338 | { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm }, |
| 339 | { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm }, |
| 340 | { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm }, |
| 341 | { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm }, |
| 342 | { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm }, |
| 343 | { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm }, |
| 344 | { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm }, |
| 345 | { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm }, |
| 346 | { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm }, |
| 347 | { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm }, |
| 348 | { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm }, |
| 349 | { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm }, |
| 350 | { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm }, |
| 351 | { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm }, |
| 352 | { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm }, |
| 353 | { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm }, |
| 354 | { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm }, |
| 355 | { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm }, |
| 356 | { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm }, |
| 357 | { X86::MOV16rr, X86::MOV16rm }, |
| 358 | { X86::MOV16to16_, X86::MOV16_rm }, |
| 359 | { X86::MOV32rr, X86::MOV32rm }, |
| 360 | { X86::MOV32to32_, X86::MOV32_rm }, |
| 361 | { X86::MOV64rr, X86::MOV64rm }, |
| 362 | { X86::MOV64toPQIrr, X86::MOVQI2PQIrm }, |
| 363 | { X86::MOV64toSDrr, X86::MOV64toSDrm }, |
| 364 | { X86::MOV8rr, X86::MOV8rm }, |
| 365 | { X86::MOVAPDrr, X86::MOVAPDrm }, |
| 366 | { X86::MOVAPSrr, X86::MOVAPSrm }, |
| 367 | { X86::MOVDDUPrr, X86::MOVDDUPrm }, |
| 368 | { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm }, |
| 369 | { X86::MOVDI2SSrr, X86::MOVDI2SSrm }, |
| 370 | { X86::MOVSD2PDrr, X86::MOVSD2PDrm }, |
| 371 | { X86::MOVSDrr, X86::MOVSDrm }, |
| 372 | { X86::MOVSHDUPrr, X86::MOVSHDUPrm }, |
| 373 | { X86::MOVSLDUPrr, X86::MOVSLDUPrm }, |
| 374 | { X86::MOVSS2PSrr, X86::MOVSS2PSrm }, |
| 375 | { X86::MOVSSrr, X86::MOVSSrm }, |
| 376 | { X86::MOVSX16rr8, X86::MOVSX16rm8 }, |
| 377 | { X86::MOVSX32rr16, X86::MOVSX32rm16 }, |
| 378 | { X86::MOVSX32rr8, X86::MOVSX32rm8 }, |
| 379 | { X86::MOVSX64rr16, X86::MOVSX64rm16 }, |
| 380 | { X86::MOVSX64rr32, X86::MOVSX64rm32 }, |
| 381 | { X86::MOVSX64rr8, X86::MOVSX64rm8 }, |
| 382 | { X86::MOVUPDrr, X86::MOVUPDrm }, |
| 383 | { X86::MOVUPSrr, X86::MOVUPSrm }, |
| 384 | { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm }, |
| 385 | { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm }, |
| 386 | { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm }, |
| 387 | { X86::MOVZX16rr8, X86::MOVZX16rm8 }, |
| 388 | { X86::MOVZX32rr16, X86::MOVZX32rm16 }, |
| 389 | { X86::MOVZX32rr8, X86::MOVZX32rm8 }, |
| 390 | { X86::MOVZX64rr16, X86::MOVZX64rm16 }, |
| 391 | { X86::MOVZX64rr8, X86::MOVZX64rm8 }, |
| 392 | { X86::PSHUFDri, X86::PSHUFDmi }, |
| 393 | { X86::PSHUFHWri, X86::PSHUFHWmi }, |
| 394 | { X86::PSHUFLWri, X86::PSHUFLWmi }, |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 395 | { X86::RCPPSr, X86::RCPPSm }, |
| 396 | { X86::RCPPSr_Int, X86::RCPPSm_Int }, |
| 397 | { X86::RSQRTPSr, X86::RSQRTPSm }, |
| 398 | { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int }, |
| 399 | { X86::RSQRTSSr, X86::RSQRTSSm }, |
| 400 | { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int }, |
| 401 | { X86::SQRTPDr, X86::SQRTPDm }, |
| 402 | { X86::SQRTPDr_Int, X86::SQRTPDm_Int }, |
| 403 | { X86::SQRTPSr, X86::SQRTPSm }, |
| 404 | { X86::SQRTPSr_Int, X86::SQRTPSm_Int }, |
| 405 | { X86::SQRTSDr, X86::SQRTSDm }, |
| 406 | { X86::SQRTSDr_Int, X86::SQRTSDm_Int }, |
| 407 | { X86::SQRTSSr, X86::SQRTSSm }, |
| 408 | { X86::SQRTSSr_Int, X86::SQRTSSm_Int }, |
| 409 | { X86::TEST16rr, X86::TEST16rm }, |
| 410 | { X86::TEST32rr, X86::TEST32rm }, |
| 411 | { X86::TEST64rr, X86::TEST64rm }, |
| 412 | { X86::TEST8rr, X86::TEST8rm }, |
| 413 | // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 |
| 414 | { X86::UCOMISDrr, X86::UCOMISDrm }, |
Chris Lattner | f9b3f37 | 2008-01-11 18:00:50 +0000 | [diff] [blame] | 415 | { X86::UCOMISSrr, X86::UCOMISSrm } |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 416 | }; |
| 417 | |
| 418 | for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { |
| 419 | unsigned RegOp = OpTbl1[i][0]; |
| 420 | unsigned MemOp = OpTbl1[i][1]; |
| 421 | if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 422 | assert(false && "Duplicated entries?"); |
| 423 | unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load |
| 424 | if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) |
| 425 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 426 | std::make_pair(RegOp, AuxInfo)))) |
| 427 | AmbEntries.push_back(MemOp); |
| 428 | } |
| 429 | |
| 430 | static const unsigned OpTbl2[][2] = { |
| 431 | { X86::ADC32rr, X86::ADC32rm }, |
| 432 | { X86::ADC64rr, X86::ADC64rm }, |
| 433 | { X86::ADD16rr, X86::ADD16rm }, |
| 434 | { X86::ADD32rr, X86::ADD32rm }, |
| 435 | { X86::ADD64rr, X86::ADD64rm }, |
| 436 | { X86::ADD8rr, X86::ADD8rm }, |
| 437 | { X86::ADDPDrr, X86::ADDPDrm }, |
| 438 | { X86::ADDPSrr, X86::ADDPSrm }, |
| 439 | { X86::ADDSDrr, X86::ADDSDrm }, |
| 440 | { X86::ADDSSrr, X86::ADDSSrm }, |
| 441 | { X86::ADDSUBPDrr, X86::ADDSUBPDrm }, |
| 442 | { X86::ADDSUBPSrr, X86::ADDSUBPSrm }, |
| 443 | { X86::AND16rr, X86::AND16rm }, |
| 444 | { X86::AND32rr, X86::AND32rm }, |
| 445 | { X86::AND64rr, X86::AND64rm }, |
| 446 | { X86::AND8rr, X86::AND8rm }, |
| 447 | { X86::ANDNPDrr, X86::ANDNPDrm }, |
| 448 | { X86::ANDNPSrr, X86::ANDNPSrm }, |
| 449 | { X86::ANDPDrr, X86::ANDPDrm }, |
| 450 | { X86::ANDPSrr, X86::ANDPSrm }, |
| 451 | { X86::CMOVA16rr, X86::CMOVA16rm }, |
| 452 | { X86::CMOVA32rr, X86::CMOVA32rm }, |
| 453 | { X86::CMOVA64rr, X86::CMOVA64rm }, |
| 454 | { X86::CMOVAE16rr, X86::CMOVAE16rm }, |
| 455 | { X86::CMOVAE32rr, X86::CMOVAE32rm }, |
| 456 | { X86::CMOVAE64rr, X86::CMOVAE64rm }, |
| 457 | { X86::CMOVB16rr, X86::CMOVB16rm }, |
| 458 | { X86::CMOVB32rr, X86::CMOVB32rm }, |
| 459 | { X86::CMOVB64rr, X86::CMOVB64rm }, |
| 460 | { X86::CMOVBE16rr, X86::CMOVBE16rm }, |
| 461 | { X86::CMOVBE32rr, X86::CMOVBE32rm }, |
| 462 | { X86::CMOVBE64rr, X86::CMOVBE64rm }, |
| 463 | { X86::CMOVE16rr, X86::CMOVE16rm }, |
| 464 | { X86::CMOVE32rr, X86::CMOVE32rm }, |
| 465 | { X86::CMOVE64rr, X86::CMOVE64rm }, |
| 466 | { X86::CMOVG16rr, X86::CMOVG16rm }, |
| 467 | { X86::CMOVG32rr, X86::CMOVG32rm }, |
| 468 | { X86::CMOVG64rr, X86::CMOVG64rm }, |
| 469 | { X86::CMOVGE16rr, X86::CMOVGE16rm }, |
| 470 | { X86::CMOVGE32rr, X86::CMOVGE32rm }, |
| 471 | { X86::CMOVGE64rr, X86::CMOVGE64rm }, |
| 472 | { X86::CMOVL16rr, X86::CMOVL16rm }, |
| 473 | { X86::CMOVL32rr, X86::CMOVL32rm }, |
| 474 | { X86::CMOVL64rr, X86::CMOVL64rm }, |
| 475 | { X86::CMOVLE16rr, X86::CMOVLE16rm }, |
| 476 | { X86::CMOVLE32rr, X86::CMOVLE32rm }, |
| 477 | { X86::CMOVLE64rr, X86::CMOVLE64rm }, |
| 478 | { X86::CMOVNE16rr, X86::CMOVNE16rm }, |
| 479 | { X86::CMOVNE32rr, X86::CMOVNE32rm }, |
| 480 | { X86::CMOVNE64rr, X86::CMOVNE64rm }, |
| 481 | { X86::CMOVNP16rr, X86::CMOVNP16rm }, |
| 482 | { X86::CMOVNP32rr, X86::CMOVNP32rm }, |
| 483 | { X86::CMOVNP64rr, X86::CMOVNP64rm }, |
| 484 | { X86::CMOVNS16rr, X86::CMOVNS16rm }, |
| 485 | { X86::CMOVNS32rr, X86::CMOVNS32rm }, |
| 486 | { X86::CMOVNS64rr, X86::CMOVNS64rm }, |
| 487 | { X86::CMOVP16rr, X86::CMOVP16rm }, |
| 488 | { X86::CMOVP32rr, X86::CMOVP32rm }, |
| 489 | { X86::CMOVP64rr, X86::CMOVP64rm }, |
| 490 | { X86::CMOVS16rr, X86::CMOVS16rm }, |
| 491 | { X86::CMOVS32rr, X86::CMOVS32rm }, |
| 492 | { X86::CMOVS64rr, X86::CMOVS64rm }, |
| 493 | { X86::CMPPDrri, X86::CMPPDrmi }, |
| 494 | { X86::CMPPSrri, X86::CMPPSrmi }, |
| 495 | { X86::CMPSDrr, X86::CMPSDrm }, |
| 496 | { X86::CMPSSrr, X86::CMPSSrm }, |
| 497 | { X86::DIVPDrr, X86::DIVPDrm }, |
| 498 | { X86::DIVPSrr, X86::DIVPSrm }, |
| 499 | { X86::DIVSDrr, X86::DIVSDrm }, |
| 500 | { X86::DIVSSrr, X86::DIVSSrm }, |
Evan Cheng | 33663fc | 2008-02-08 00:12:56 +0000 | [diff] [blame] | 501 | { X86::FsANDNPDrr, X86::FsANDNPDrm }, |
| 502 | { X86::FsANDNPSrr, X86::FsANDNPSrm }, |
| 503 | { X86::FsANDPDrr, X86::FsANDPDrm }, |
| 504 | { X86::FsANDPSrr, X86::FsANDPSrm }, |
| 505 | { X86::FsORPDrr, X86::FsORPDrm }, |
| 506 | { X86::FsORPSrr, X86::FsORPSrm }, |
| 507 | { X86::FsXORPDrr, X86::FsXORPDrm }, |
| 508 | { X86::FsXORPSrr, X86::FsXORPSrm }, |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 509 | { X86::HADDPDrr, X86::HADDPDrm }, |
| 510 | { X86::HADDPSrr, X86::HADDPSrm }, |
| 511 | { X86::HSUBPDrr, X86::HSUBPDrm }, |
| 512 | { X86::HSUBPSrr, X86::HSUBPSrm }, |
| 513 | { X86::IMUL16rr, X86::IMUL16rm }, |
| 514 | { X86::IMUL32rr, X86::IMUL32rm }, |
| 515 | { X86::IMUL64rr, X86::IMUL64rm }, |
| 516 | { X86::MAXPDrr, X86::MAXPDrm }, |
| 517 | { X86::MAXPDrr_Int, X86::MAXPDrm_Int }, |
| 518 | { X86::MAXPSrr, X86::MAXPSrm }, |
| 519 | { X86::MAXPSrr_Int, X86::MAXPSrm_Int }, |
| 520 | { X86::MAXSDrr, X86::MAXSDrm }, |
| 521 | { X86::MAXSDrr_Int, X86::MAXSDrm_Int }, |
| 522 | { X86::MAXSSrr, X86::MAXSSrm }, |
| 523 | { X86::MAXSSrr_Int, X86::MAXSSrm_Int }, |
| 524 | { X86::MINPDrr, X86::MINPDrm }, |
| 525 | { X86::MINPDrr_Int, X86::MINPDrm_Int }, |
| 526 | { X86::MINPSrr, X86::MINPSrm }, |
| 527 | { X86::MINPSrr_Int, X86::MINPSrm_Int }, |
| 528 | { X86::MINSDrr, X86::MINSDrm }, |
| 529 | { X86::MINSDrr_Int, X86::MINSDrm_Int }, |
| 530 | { X86::MINSSrr, X86::MINSSrm }, |
| 531 | { X86::MINSSrr_Int, X86::MINSSrm_Int }, |
| 532 | { X86::MULPDrr, X86::MULPDrm }, |
| 533 | { X86::MULPSrr, X86::MULPSrm }, |
| 534 | { X86::MULSDrr, X86::MULSDrm }, |
| 535 | { X86::MULSSrr, X86::MULSSrm }, |
| 536 | { X86::OR16rr, X86::OR16rm }, |
| 537 | { X86::OR32rr, X86::OR32rm }, |
| 538 | { X86::OR64rr, X86::OR64rm }, |
| 539 | { X86::OR8rr, X86::OR8rm }, |
| 540 | { X86::ORPDrr, X86::ORPDrm }, |
| 541 | { X86::ORPSrr, X86::ORPSrm }, |
| 542 | { X86::PACKSSDWrr, X86::PACKSSDWrm }, |
| 543 | { X86::PACKSSWBrr, X86::PACKSSWBrm }, |
| 544 | { X86::PACKUSWBrr, X86::PACKUSWBrm }, |
| 545 | { X86::PADDBrr, X86::PADDBrm }, |
| 546 | { X86::PADDDrr, X86::PADDDrm }, |
| 547 | { X86::PADDQrr, X86::PADDQrm }, |
| 548 | { X86::PADDSBrr, X86::PADDSBrm }, |
| 549 | { X86::PADDSWrr, X86::PADDSWrm }, |
| 550 | { X86::PADDWrr, X86::PADDWrm }, |
| 551 | { X86::PANDNrr, X86::PANDNrm }, |
| 552 | { X86::PANDrr, X86::PANDrm }, |
| 553 | { X86::PAVGBrr, X86::PAVGBrm }, |
| 554 | { X86::PAVGWrr, X86::PAVGWrm }, |
| 555 | { X86::PCMPEQBrr, X86::PCMPEQBrm }, |
| 556 | { X86::PCMPEQDrr, X86::PCMPEQDrm }, |
| 557 | { X86::PCMPEQWrr, X86::PCMPEQWrm }, |
| 558 | { X86::PCMPGTBrr, X86::PCMPGTBrm }, |
| 559 | { X86::PCMPGTDrr, X86::PCMPGTDrm }, |
| 560 | { X86::PCMPGTWrr, X86::PCMPGTWrm }, |
| 561 | { X86::PINSRWrri, X86::PINSRWrmi }, |
| 562 | { X86::PMADDWDrr, X86::PMADDWDrm }, |
| 563 | { X86::PMAXSWrr, X86::PMAXSWrm }, |
| 564 | { X86::PMAXUBrr, X86::PMAXUBrm }, |
| 565 | { X86::PMINSWrr, X86::PMINSWrm }, |
| 566 | { X86::PMINUBrr, X86::PMINUBrm }, |
| 567 | { X86::PMULHUWrr, X86::PMULHUWrm }, |
| 568 | { X86::PMULHWrr, X86::PMULHWrm }, |
| 569 | { X86::PMULLWrr, X86::PMULLWrm }, |
| 570 | { X86::PMULUDQrr, X86::PMULUDQrm }, |
| 571 | { X86::PORrr, X86::PORrm }, |
| 572 | { X86::PSADBWrr, X86::PSADBWrm }, |
| 573 | { X86::PSLLDrr, X86::PSLLDrm }, |
| 574 | { X86::PSLLQrr, X86::PSLLQrm }, |
| 575 | { X86::PSLLWrr, X86::PSLLWrm }, |
| 576 | { X86::PSRADrr, X86::PSRADrm }, |
| 577 | { X86::PSRAWrr, X86::PSRAWrm }, |
| 578 | { X86::PSRLDrr, X86::PSRLDrm }, |
| 579 | { X86::PSRLQrr, X86::PSRLQrm }, |
| 580 | { X86::PSRLWrr, X86::PSRLWrm }, |
| 581 | { X86::PSUBBrr, X86::PSUBBrm }, |
| 582 | { X86::PSUBDrr, X86::PSUBDrm }, |
| 583 | { X86::PSUBSBrr, X86::PSUBSBrm }, |
| 584 | { X86::PSUBSWrr, X86::PSUBSWrm }, |
| 585 | { X86::PSUBWrr, X86::PSUBWrm }, |
| 586 | { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm }, |
| 587 | { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm }, |
| 588 | { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm }, |
| 589 | { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm }, |
| 590 | { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm }, |
| 591 | { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm }, |
| 592 | { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm }, |
| 593 | { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm }, |
| 594 | { X86::PXORrr, X86::PXORrm }, |
| 595 | { X86::SBB32rr, X86::SBB32rm }, |
| 596 | { X86::SBB64rr, X86::SBB64rm }, |
| 597 | { X86::SHUFPDrri, X86::SHUFPDrmi }, |
| 598 | { X86::SHUFPSrri, X86::SHUFPSrmi }, |
| 599 | { X86::SUB16rr, X86::SUB16rm }, |
| 600 | { X86::SUB32rr, X86::SUB32rm }, |
| 601 | { X86::SUB64rr, X86::SUB64rm }, |
| 602 | { X86::SUB8rr, X86::SUB8rm }, |
| 603 | { X86::SUBPDrr, X86::SUBPDrm }, |
| 604 | { X86::SUBPSrr, X86::SUBPSrm }, |
| 605 | { X86::SUBSDrr, X86::SUBSDrm }, |
| 606 | { X86::SUBSSrr, X86::SUBSSrm }, |
| 607 | // FIXME: TEST*rr -> swapped operand of TEST*mr. |
| 608 | { X86::UNPCKHPDrr, X86::UNPCKHPDrm }, |
| 609 | { X86::UNPCKHPSrr, X86::UNPCKHPSrm }, |
| 610 | { X86::UNPCKLPDrr, X86::UNPCKLPDrm }, |
| 611 | { X86::UNPCKLPSrr, X86::UNPCKLPSrm }, |
| 612 | { X86::XOR16rr, X86::XOR16rm }, |
| 613 | { X86::XOR32rr, X86::XOR32rm }, |
| 614 | { X86::XOR64rr, X86::XOR64rm }, |
| 615 | { X86::XOR8rr, X86::XOR8rm }, |
| 616 | { X86::XORPDrr, X86::XORPDrm }, |
| 617 | { X86::XORPSrr, X86::XORPSrm } |
| 618 | }; |
| 619 | |
| 620 | for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { |
| 621 | unsigned RegOp = OpTbl2[i][0]; |
| 622 | unsigned MemOp = OpTbl2[i][1]; |
| 623 | if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 624 | assert(false && "Duplicated entries?"); |
| 625 | unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load |
| 626 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 627 | std::make_pair(RegOp, AuxInfo)))) |
| 628 | AmbEntries.push_back(MemOp); |
| 629 | } |
| 630 | |
| 631 | // Remove ambiguous entries. |
| 632 | assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 633 | } |
| 634 | |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 635 | bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, |
| 636 | unsigned& sourceReg, |
| 637 | unsigned& destReg) const { |
Chris Lattner | 07f7cc3 | 2008-03-11 19:28:17 +0000 | [diff] [blame] | 638 | switch (MI.getOpcode()) { |
| 639 | default: |
| 640 | return false; |
| 641 | case X86::MOV8rr: |
| 642 | case X86::MOV16rr: |
| 643 | case X86::MOV32rr: |
| 644 | case X86::MOV64rr: |
| 645 | case X86::MOV16to16_: |
| 646 | case X86::MOV32to32_: |
Chris Lattner | 07f7cc3 | 2008-03-11 19:28:17 +0000 | [diff] [blame] | 647 | case X86::MOVSSrr: |
| 648 | case X86::MOVSDrr: |
Chris Lattner | 1d38677 | 2008-03-11 19:30:09 +0000 | [diff] [blame] | 649 | |
| 650 | // FP Stack register class copies |
| 651 | case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: |
| 652 | case X86::MOV_Fp3264: case X86::MOV_Fp3280: |
| 653 | case X86::MOV_Fp6432: case X86::MOV_Fp8032: |
| 654 | |
Chris Lattner | 07f7cc3 | 2008-03-11 19:28:17 +0000 | [diff] [blame] | 655 | case X86::FsMOVAPSrr: |
| 656 | case X86::FsMOVAPDrr: |
| 657 | case X86::MOVAPSrr: |
| 658 | case X86::MOVAPDrr: |
| 659 | case X86::MOVSS2PSrr: |
| 660 | case X86::MOVSD2PDrr: |
| 661 | case X86::MOVPS2SSrr: |
| 662 | case X86::MOVPD2SDrr: |
| 663 | case X86::MMX_MOVD64rr: |
| 664 | case X86::MMX_MOVQ64rr: |
| 665 | assert(MI.getNumOperands() >= 2 && |
| 666 | MI.getOperand(0).isRegister() && |
| 667 | MI.getOperand(1).isRegister() && |
| 668 | "invalid register-register move instruction"); |
| 669 | sourceReg = MI.getOperand(1).getReg(); |
| 670 | destReg = MI.getOperand(0).getReg(); |
| 671 | return true; |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 672 | } |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 673 | } |
Alkis Evlogimenos | 36f506e | 2004-07-31 09:38:47 +0000 | [diff] [blame] | 674 | |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 675 | unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, |
| 676 | int &FrameIndex) const { |
| 677 | switch (MI->getOpcode()) { |
| 678 | default: break; |
| 679 | case X86::MOV8rm: |
| 680 | case X86::MOV16rm: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 681 | case X86::MOV16_rm: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 682 | case X86::MOV32rm: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 683 | case X86::MOV32_rm: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 684 | case X86::MOV64rm: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 685 | case X86::LD_Fp64m: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 686 | case X86::MOVSSrm: |
| 687 | case X86::MOVSDrm: |
Chris Lattner | 993c897 | 2006-04-18 16:44:51 +0000 | [diff] [blame] | 688 | case X86::MOVAPSrm: |
| 689 | case X86::MOVAPDrm: |
Bill Wendling | 823efee | 2007-04-03 06:00:37 +0000 | [diff] [blame] | 690 | case X86::MMX_MOVD64rm: |
| 691 | case X86::MMX_MOVQ64rm: |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 692 | if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && |
| 693 | MI->getOperand(3).isReg() && MI->getOperand(4).isImm() && |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 694 | MI->getOperand(2).getImm() == 1 && |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 695 | MI->getOperand(3).getReg() == 0 && |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 696 | MI->getOperand(4).getImm() == 0) { |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 697 | FrameIndex = MI->getOperand(1).getIndex(); |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 698 | return MI->getOperand(0).getReg(); |
| 699 | } |
| 700 | break; |
| 701 | } |
| 702 | return 0; |
| 703 | } |
| 704 | |
| 705 | unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, |
| 706 | int &FrameIndex) const { |
| 707 | switch (MI->getOpcode()) { |
| 708 | default: break; |
| 709 | case X86::MOV8mr: |
| 710 | case X86::MOV16mr: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 711 | case X86::MOV16_mr: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 712 | case X86::MOV32mr: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 713 | case X86::MOV32_mr: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 714 | case X86::MOV64mr: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 715 | case X86::ST_FpP64m: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 716 | case X86::MOVSSmr: |
| 717 | case X86::MOVSDmr: |
Chris Lattner | 993c897 | 2006-04-18 16:44:51 +0000 | [diff] [blame] | 718 | case X86::MOVAPSmr: |
| 719 | case X86::MOVAPDmr: |
Bill Wendling | 823efee | 2007-04-03 06:00:37 +0000 | [diff] [blame] | 720 | case X86::MMX_MOVD64mr: |
| 721 | case X86::MMX_MOVQ64mr: |
Bill Wendling | 71bfd11 | 2007-04-03 23:48:32 +0000 | [diff] [blame] | 722 | case X86::MMX_MOVNTQmr: |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 723 | if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && |
| 724 | MI->getOperand(2).isReg() && MI->getOperand(3).isImm() && |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 725 | MI->getOperand(1).getImm() == 1 && |
Chris Lattner | 1c07e72 | 2006-02-02 20:38:12 +0000 | [diff] [blame] | 726 | MI->getOperand(2).getReg() == 0 && |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 727 | MI->getOperand(3).getImm() == 0) { |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 728 | FrameIndex = MI->getOperand(0).getIndex(); |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 729 | return MI->getOperand(4).getReg(); |
| 730 | } |
| 731 | break; |
| 732 | } |
| 733 | return 0; |
| 734 | } |
| 735 | |
| 736 | |
Bill Wendling | 041b3f8 | 2007-12-08 23:58:46 +0000 | [diff] [blame] | 737 | bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const { |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 738 | switch (MI->getOpcode()) { |
| 739 | default: break; |
| 740 | case X86::MOV8rm: |
| 741 | case X86::MOV16rm: |
| 742 | case X86::MOV16_rm: |
| 743 | case X86::MOV32rm: |
| 744 | case X86::MOV32_rm: |
| 745 | case X86::MOV64rm: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 746 | case X86::LD_Fp64m: |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 747 | case X86::MOVSSrm: |
| 748 | case X86::MOVSDrm: |
| 749 | case X86::MOVAPSrm: |
| 750 | case X86::MOVAPDrm: |
| 751 | case X86::MMX_MOVD64rm: |
| 752 | case X86::MMX_MOVQ64rm: |
Dan Gohman | 82a87a0 | 2007-06-19 01:48:05 +0000 | [diff] [blame] | 753 | // Loads from constant pools are trivially rematerializable. |
Chris Lattner | 3b5a221 | 2008-01-05 05:28:30 +0000 | [diff] [blame] | 754 | if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() && |
| 755 | MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() && |
Chris Lattner | 3b5a221 | 2008-01-05 05:28:30 +0000 | [diff] [blame] | 756 | MI->getOperand(2).getImm() == 1 && |
Evan Cheng | d8850a5 | 2008-02-22 09:25:47 +0000 | [diff] [blame] | 757 | MI->getOperand(3).getReg() == 0) { |
| 758 | unsigned BaseReg = MI->getOperand(1).getReg(); |
| 759 | if (BaseReg == 0) |
| 760 | return true; |
| 761 | if (!ReMatPICLoad) |
| 762 | return false; |
| 763 | // Allow re-materialization of PIC load. |
| 764 | MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); |
| 765 | bool isPICBase = false; |
| 766 | for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), |
| 767 | E = MRI.def_end(); I != E; ++I) { |
| 768 | MachineInstr *DefMI = I.getOperand().getParent(); |
| 769 | if (DefMI->getOpcode() != X86::MOVPC32r) |
| 770 | return false; |
| 771 | assert(!isPICBase && "More than one PIC base?"); |
| 772 | isPICBase = true; |
| 773 | } |
| 774 | return isPICBase; |
| 775 | } |
Chris Lattner | f29495a | 2008-01-05 06:10:42 +0000 | [diff] [blame] | 776 | |
Chris Lattner | 3b5a221 | 2008-01-05 05:28:30 +0000 | [diff] [blame] | 777 | return false; |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 778 | } |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 779 | // All other instructions marked M_REMATERIALIZABLE are always trivially |
| 780 | // rematerializable. |
| 781 | return true; |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 782 | } |
| 783 | |
Chris Lattner | a22edc8 | 2008-01-10 23:08:24 +0000 | [diff] [blame] | 784 | /// isInvariantLoad - Return true if the specified instruction (which is marked |
| 785 | /// mayLoad) is loading from a location whose value is invariant across the |
| 786 | /// function. For example, loading a value from the constant pool or from |
| 787 | /// from the argument area of a function if it does not change. This should |
| 788 | /// only return true of *all* loads the instruction does are invariant (if it |
| 789 | /// does multiple loads). |
| 790 | bool X86InstrInfo::isInvariantLoad(MachineInstr *MI) const { |
Chris Lattner | 828bb6c | 2008-01-12 00:35:08 +0000 | [diff] [blame] | 791 | // This code cares about loads from three cases: constant pool entries, |
| 792 | // invariant argument slots, and global stubs. In order to handle these cases |
| 793 | // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV |
Chris Lattner | 144ad58 | 2008-01-12 00:53:16 +0000 | [diff] [blame] | 794 | // operand and base our analysis on it. This is safe because the address of |
Chris Lattner | 828bb6c | 2008-01-12 00:35:08 +0000 | [diff] [blame] | 795 | // none of these three cases is ever used as anything other than a load base |
| 796 | // and X86 doesn't have any instructions that load from multiple places. |
| 797 | |
| 798 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 799 | const MachineOperand &MO = MI->getOperand(i); |
Chris Lattner | a22edc8 | 2008-01-10 23:08:24 +0000 | [diff] [blame] | 800 | // Loads from constant pools are trivially invariant. |
Chris Lattner | 828bb6c | 2008-01-12 00:35:08 +0000 | [diff] [blame] | 801 | if (MO.isCPI()) |
Chris Lattner | 3b5a221 | 2008-01-05 05:28:30 +0000 | [diff] [blame] | 802 | return true; |
Chris Lattner | 828bb6c | 2008-01-12 00:35:08 +0000 | [diff] [blame] | 803 | |
| 804 | if (MO.isGlobal()) { |
| 805 | if (TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(MO.getGlobal(), |
| 806 | TM, false)) |
| 807 | return true; |
| 808 | return false; |
| 809 | } |
| 810 | |
| 811 | // If this is a load from an invariant stack slot, the load is a constant. |
| 812 | if (MO.isFI()) { |
| 813 | const MachineFrameInfo &MFI = |
| 814 | *MI->getParent()->getParent()->getFrameInfo(); |
| 815 | int Idx = MO.getIndex(); |
Chris Lattner | 8794390 | 2008-01-10 04:16:31 +0000 | [diff] [blame] | 816 | return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx); |
| 817 | } |
Bill Wendling | 627c00b | 2007-12-17 23:07:56 +0000 | [diff] [blame] | 818 | } |
Chris Lattner | 828bb6c | 2008-01-12 00:35:08 +0000 | [diff] [blame] | 819 | |
Chris Lattner | a22edc8 | 2008-01-10 23:08:24 +0000 | [diff] [blame] | 820 | // All other instances of these instructions are presumed to have other |
| 821 | // issues. |
Chris Lattner | a83b34b | 2008-01-05 05:26:26 +0000 | [diff] [blame] | 822 | return false; |
Bill Wendling | 627c00b | 2007-12-17 23:07:56 +0000 | [diff] [blame] | 823 | } |
| 824 | |
Evan Cheng | 3f411c7 | 2007-10-05 08:04:01 +0000 | [diff] [blame] | 825 | /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that |
| 826 | /// is not marked dead. |
| 827 | static bool hasLiveCondCodeDef(MachineInstr *MI) { |
Evan Cheng | 3f411c7 | 2007-10-05 08:04:01 +0000 | [diff] [blame] | 828 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 829 | MachineOperand &MO = MI->getOperand(i); |
| 830 | if (MO.isRegister() && MO.isDef() && |
| 831 | MO.getReg() == X86::EFLAGS && !MO.isDead()) { |
| 832 | return true; |
| 833 | } |
| 834 | } |
| 835 | return false; |
| 836 | } |
| 837 | |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 838 | /// convertToThreeAddress - This method must be implemented by targets that |
| 839 | /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target |
| 840 | /// may be able to convert a two-address instruction into a true |
| 841 | /// three-address instruction on demand. This allows the X86 target (for |
| 842 | /// example) to convert ADD and SHL instructions into LEA instructions if they |
| 843 | /// would require register copies due to two-addressness. |
| 844 | /// |
| 845 | /// This method returns a null pointer if the transformation cannot be |
| 846 | /// performed, otherwise it returns the new instruction. |
| 847 | /// |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 848 | MachineInstr * |
| 849 | X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, |
| 850 | MachineBasicBlock::iterator &MBBI, |
| 851 | LiveVariables &LV) const { |
| 852 | MachineInstr *MI = MBBI; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 853 | // All instructions input are two-addr instructions. Get the known operands. |
| 854 | unsigned Dest = MI->getOperand(0).getReg(); |
| 855 | unsigned Src = MI->getOperand(1).getReg(); |
| 856 | |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 857 | MachineInstr *NewMI = NULL; |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 858 | // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 859 | // we have better subtarget support, enable the 16-bit LEA generation here. |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 860 | bool DisableLEA16 = true; |
| 861 | |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 862 | unsigned MIOpc = MI->getOpcode(); |
| 863 | switch (MIOpc) { |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 864 | case X86::SHUFPSrri: { |
| 865 | assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 866 | if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; |
| 867 | |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 868 | unsigned A = MI->getOperand(0).getReg(); |
| 869 | unsigned B = MI->getOperand(1).getReg(); |
| 870 | unsigned C = MI->getOperand(2).getReg(); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 871 | unsigned M = MI->getOperand(3).getImm(); |
| 872 | if (B != C) return 0; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 873 | NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 874 | break; |
| 875 | } |
Chris Lattner | 995f550 | 2007-03-28 18:12:31 +0000 | [diff] [blame] | 876 | case X86::SHL64ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 877 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Chris Lattner | 995f550 | 2007-03-28 18:12:31 +0000 | [diff] [blame] | 878 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 879 | // the flags produced by a shift yet, so this is safe. |
| 880 | unsigned Dest = MI->getOperand(0).getReg(); |
| 881 | unsigned Src = MI->getOperand(1).getReg(); |
| 882 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 883 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
| 884 | |
| 885 | NewMI = BuildMI(get(X86::LEA64r), Dest) |
| 886 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 887 | break; |
| 888 | } |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 889 | case X86::SHL32ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 890 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 891 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 892 | // the flags produced by a shift yet, so this is safe. |
| 893 | unsigned Dest = MI->getOperand(0).getReg(); |
| 894 | unsigned Src = MI->getOperand(1).getReg(); |
| 895 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 896 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
| 897 | |
Chris Lattner | f2177b8 | 2007-03-28 00:58:40 +0000 | [diff] [blame] | 898 | unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? |
| 899 | X86::LEA64_32r : X86::LEA32r; |
| 900 | NewMI = BuildMI(get(Opc), Dest) |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 901 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 902 | break; |
| 903 | } |
| 904 | case X86::SHL16ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 905 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 906 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 907 | // the flags produced by a shift yet, so this is safe. |
| 908 | unsigned Dest = MI->getOperand(0).getReg(); |
| 909 | unsigned Src = MI->getOperand(1).getReg(); |
| 910 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 911 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 912 | |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 913 | if (DisableLEA16) { |
| 914 | // If 16-bit LEA is disabled, use 32-bit LEA via subregisters. |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 915 | MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 916 | unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() |
| 917 | ? X86::LEA64_32r : X86::LEA32r; |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 918 | unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); |
| 919 | unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); |
Evan Cheng | 4499e49 | 2008-03-10 19:31:26 +0000 | [diff] [blame] | 920 | |
Christopher Lamb | 1bc1008 | 2008-03-11 10:27:36 +0000 | [diff] [blame] | 921 | // Build and insert into an implicit UNDEF value. This is OK because |
| 922 | // well be shifting and then extracting the lower 16-bits. |
Christopher Lamb | c929823 | 2008-03-16 03:12:01 +0000 | [diff] [blame] | 923 | MachineInstr *Undef = BuildMI(get(X86::IMPLICIT_DEF), leaInReg); |
| 924 | |
Christopher Lamb | 1bc1008 | 2008-03-11 10:27:36 +0000 | [diff] [blame] | 925 | MachineInstr *Ins = |
Christopher Lamb | 6634e26 | 2008-03-13 05:47:01 +0000 | [diff] [blame] | 926 | BuildMI(get(X86::INSERT_SUBREG),leaInReg) |
Christopher Lamb | c929823 | 2008-03-16 03:12:01 +0000 | [diff] [blame] | 927 | .addReg(leaInReg).addReg(Src).addImm(X86::SUBREG_16BIT); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 928 | |
| 929 | NewMI = BuildMI(get(Opc), leaOutReg) |
| 930 | .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0); |
| 931 | |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 932 | MachineInstr *Ext = |
Christopher Lamb | 1bc1008 | 2008-03-11 10:27:36 +0000 | [diff] [blame] | 933 | BuildMI(get(X86::EXTRACT_SUBREG), Dest) |
| 934 | .addReg(leaOutReg).addImm(X86::SUBREG_16BIT); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 935 | Ext->copyKillDeadInfo(MI); |
| 936 | |
Christopher Lamb | c929823 | 2008-03-16 03:12:01 +0000 | [diff] [blame] | 937 | MFI->insert(MBBI, Undef); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 938 | MFI->insert(MBBI, Ins); // Insert the insert_subreg |
| 939 | LV.instructionChanged(MI, NewMI); // Update live variables |
| 940 | LV.addVirtualRegisterKilled(leaInReg, NewMI); |
| 941 | MFI->insert(MBBI, NewMI); // Insert the new inst |
| 942 | LV.addVirtualRegisterKilled(leaOutReg, Ext); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 943 | MFI->insert(MBBI, Ext); // Insert the extract_subreg |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 944 | return Ext; |
| 945 | } else { |
| 946 | NewMI = BuildMI(get(X86::LEA16r), Dest) |
| 947 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 948 | } |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 949 | break; |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 950 | } |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 951 | default: { |
| 952 | // The following opcodes also sets the condition code register(s). Only |
| 953 | // convert them to equivalent lea if the condition code register def's |
| 954 | // are dead! |
| 955 | if (hasLiveCondCodeDef(MI)) |
| 956 | return 0; |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 957 | |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 958 | bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 959 | switch (MIOpc) { |
| 960 | default: return 0; |
| 961 | case X86::INC64r: |
Evan Cheng | b75ed32 | 2007-10-05 21:55:32 +0000 | [diff] [blame] | 962 | case X86::INC32r: { |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 963 | assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 964 | unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r |
| 965 | : (is64Bit ? X86::LEA64_32r : X86::LEA32r); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 966 | NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1); |
| 967 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 968 | } |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 969 | case X86::INC16r: |
| 970 | case X86::INC64_16r: |
| 971 | if (DisableLEA16) return 0; |
| 972 | assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); |
| 973 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1); |
| 974 | break; |
| 975 | case X86::DEC64r: |
Evan Cheng | b75ed32 | 2007-10-05 21:55:32 +0000 | [diff] [blame] | 976 | case X86::DEC32r: { |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 977 | assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 978 | unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r |
| 979 | : (is64Bit ? X86::LEA64_32r : X86::LEA32r); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 980 | NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1); |
| 981 | break; |
| 982 | } |
| 983 | case X86::DEC16r: |
| 984 | case X86::DEC64_16r: |
| 985 | if (DisableLEA16) return 0; |
| 986 | assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); |
| 987 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1); |
| 988 | break; |
| 989 | case X86::ADD64rr: |
| 990 | case X86::ADD32rr: { |
| 991 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 992 | unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r |
| 993 | : (is64Bit ? X86::LEA64_32r : X86::LEA32r); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 994 | NewMI = addRegReg(BuildMI(get(Opc), Dest), Src, |
| 995 | MI->getOperand(2).getReg()); |
| 996 | break; |
| 997 | } |
| 998 | case X86::ADD16rr: |
| 999 | if (DisableLEA16) return 0; |
| 1000 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
| 1001 | NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src, |
| 1002 | MI->getOperand(2).getReg()); |
| 1003 | break; |
| 1004 | case X86::ADD64ri32: |
| 1005 | case X86::ADD64ri8: |
| 1006 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
| 1007 | if (MI->getOperand(2).isImmediate()) |
| 1008 | NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src, |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 1009 | MI->getOperand(2).getImm()); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 1010 | break; |
| 1011 | case X86::ADD32ri: |
| 1012 | case X86::ADD32ri8: |
| 1013 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 1014 | if (MI->getOperand(2).isImmediate()) { |
| 1015 | unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; |
| 1016 | NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 1017 | MI->getOperand(2).getImm()); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 1018 | } |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 1019 | break; |
| 1020 | case X86::ADD16ri: |
| 1021 | case X86::ADD16ri8: |
| 1022 | if (DisableLEA16) return 0; |
| 1023 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
| 1024 | if (MI->getOperand(2).isImmediate()) |
| 1025 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 1026 | MI->getOperand(2).getImm()); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 1027 | break; |
| 1028 | case X86::SHL16ri: |
| 1029 | if (DisableLEA16) return 0; |
| 1030 | case X86::SHL32ri: |
| 1031 | case X86::SHL64ri: { |
| 1032 | assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() && |
| 1033 | "Unknown shl instruction!"); |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 1034 | unsigned ShAmt = MI->getOperand(2).getImm(); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 1035 | if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { |
| 1036 | X86AddressMode AM; |
| 1037 | AM.Scale = 1 << ShAmt; |
| 1038 | AM.IndexReg = Src; |
| 1039 | unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 1040 | : (MIOpc == X86::SHL32ri |
| 1041 | ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 1042 | NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM); |
| 1043 | } |
| 1044 | break; |
| 1045 | } |
| 1046 | } |
| 1047 | } |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 1048 | } |
| 1049 | |
Evan Cheng | 1524673 | 2008-02-07 08:29:53 +0000 | [diff] [blame] | 1050 | if (!NewMI) return 0; |
| 1051 | |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 1052 | NewMI->copyKillDeadInfo(MI); |
| 1053 | LV.instructionChanged(MI, NewMI); // Update live variables |
| 1054 | MFI->insert(MBBI, NewMI); // Insert the new inst |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1055 | return NewMI; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 1056 | } |
| 1057 | |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1058 | /// commuteInstruction - We have a few instructions that must be hacked on to |
| 1059 | /// commute them. |
| 1060 | /// |
| 1061 | MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { |
| 1062 | switch (MI->getOpcode()) { |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1063 | case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) |
| 1064 | case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1065 | case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 1066 | case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) |
| 1067 | case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) |
| 1068 | case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1069 | unsigned Opc; |
| 1070 | unsigned Size; |
| 1071 | switch (MI->getOpcode()) { |
| 1072 | default: assert(0 && "Unreachable!"); |
| 1073 | case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; |
| 1074 | case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; |
| 1075 | case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; |
| 1076 | case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 1077 | case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; |
| 1078 | case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1079 | } |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 1080 | unsigned Amt = MI->getOperand(3).getImm(); |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1081 | unsigned A = MI->getOperand(0).getReg(); |
| 1082 | unsigned B = MI->getOperand(1).getReg(); |
| 1083 | unsigned C = MI->getOperand(2).getReg(); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1084 | bool BisKill = MI->getOperand(1).isKill(); |
| 1085 | bool CisKill = MI->getOperand(2).isKill(); |
Evan Cheng | a4d16a1 | 2008-02-13 02:46:49 +0000 | [diff] [blame] | 1086 | // If machine instrs are no longer in two-address forms, update |
| 1087 | // destination register as well. |
| 1088 | if (A == B) { |
| 1089 | // Must be two address instruction! |
| 1090 | assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && |
| 1091 | "Expecting a two-address instruction!"); |
| 1092 | A = C; |
| 1093 | CisKill = false; |
| 1094 | } |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1095 | return BuildMI(get(Opc), A).addReg(C, false, false, CisKill) |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1096 | .addReg(B, false, false, BisKill).addImm(Size-Amt); |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1097 | } |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1098 | case X86::CMOVB16rr: |
| 1099 | case X86::CMOVB32rr: |
| 1100 | case X86::CMOVB64rr: |
| 1101 | case X86::CMOVAE16rr: |
| 1102 | case X86::CMOVAE32rr: |
| 1103 | case X86::CMOVAE64rr: |
| 1104 | case X86::CMOVE16rr: |
| 1105 | case X86::CMOVE32rr: |
| 1106 | case X86::CMOVE64rr: |
| 1107 | case X86::CMOVNE16rr: |
| 1108 | case X86::CMOVNE32rr: |
| 1109 | case X86::CMOVNE64rr: |
| 1110 | case X86::CMOVBE16rr: |
| 1111 | case X86::CMOVBE32rr: |
| 1112 | case X86::CMOVBE64rr: |
| 1113 | case X86::CMOVA16rr: |
| 1114 | case X86::CMOVA32rr: |
| 1115 | case X86::CMOVA64rr: |
| 1116 | case X86::CMOVL16rr: |
| 1117 | case X86::CMOVL32rr: |
| 1118 | case X86::CMOVL64rr: |
| 1119 | case X86::CMOVGE16rr: |
| 1120 | case X86::CMOVGE32rr: |
| 1121 | case X86::CMOVGE64rr: |
| 1122 | case X86::CMOVLE16rr: |
| 1123 | case X86::CMOVLE32rr: |
| 1124 | case X86::CMOVLE64rr: |
| 1125 | case X86::CMOVG16rr: |
| 1126 | case X86::CMOVG32rr: |
| 1127 | case X86::CMOVG64rr: |
| 1128 | case X86::CMOVS16rr: |
| 1129 | case X86::CMOVS32rr: |
| 1130 | case X86::CMOVS64rr: |
| 1131 | case X86::CMOVNS16rr: |
| 1132 | case X86::CMOVNS32rr: |
| 1133 | case X86::CMOVNS64rr: |
| 1134 | case X86::CMOVP16rr: |
| 1135 | case X86::CMOVP32rr: |
| 1136 | case X86::CMOVP64rr: |
| 1137 | case X86::CMOVNP16rr: |
| 1138 | case X86::CMOVNP32rr: |
| 1139 | case X86::CMOVNP64rr: { |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1140 | unsigned Opc = 0; |
| 1141 | switch (MI->getOpcode()) { |
| 1142 | default: break; |
| 1143 | case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; |
| 1144 | case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; |
| 1145 | case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; |
| 1146 | case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; |
| 1147 | case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; |
| 1148 | case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; |
| 1149 | case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; |
| 1150 | case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; |
| 1151 | case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; |
| 1152 | case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; |
| 1153 | case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; |
| 1154 | case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; |
| 1155 | case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; |
| 1156 | case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; |
| 1157 | case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; |
| 1158 | case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; |
| 1159 | case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; |
| 1160 | case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; |
| 1161 | case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; |
| 1162 | case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; |
| 1163 | case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; |
| 1164 | case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; |
| 1165 | case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; |
| 1166 | case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; |
| 1167 | case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; |
| 1168 | case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; |
| 1169 | case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; |
| 1170 | case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; |
| 1171 | case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; |
| 1172 | case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; |
| 1173 | case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; |
| 1174 | case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; |
| 1175 | case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break; |
| 1176 | case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; |
| 1177 | case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; |
| 1178 | case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; |
| 1179 | case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; |
| 1180 | case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; |
| 1181 | case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break; |
| 1182 | case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; |
| 1183 | case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; |
| 1184 | case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; |
| 1185 | } |
| 1186 | |
Chris Lattner | 5080f4d | 2008-01-11 18:10:50 +0000 | [diff] [blame] | 1187 | MI->setDesc(get(Opc)); |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1188 | // Fallthrough intended. |
| 1189 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1190 | default: |
Chris Lattner | 264e6fe | 2008-01-01 01:05:34 +0000 | [diff] [blame] | 1191 | return TargetInstrInfoImpl::commuteInstruction(MI); |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1192 | } |
| 1193 | } |
| 1194 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1195 | static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { |
| 1196 | switch (BrOpc) { |
| 1197 | default: return X86::COND_INVALID; |
| 1198 | case X86::JE: return X86::COND_E; |
| 1199 | case X86::JNE: return X86::COND_NE; |
| 1200 | case X86::JL: return X86::COND_L; |
| 1201 | case X86::JLE: return X86::COND_LE; |
| 1202 | case X86::JG: return X86::COND_G; |
| 1203 | case X86::JGE: return X86::COND_GE; |
| 1204 | case X86::JB: return X86::COND_B; |
| 1205 | case X86::JBE: return X86::COND_BE; |
| 1206 | case X86::JA: return X86::COND_A; |
| 1207 | case X86::JAE: return X86::COND_AE; |
| 1208 | case X86::JS: return X86::COND_S; |
| 1209 | case X86::JNS: return X86::COND_NS; |
| 1210 | case X86::JP: return X86::COND_P; |
| 1211 | case X86::JNP: return X86::COND_NP; |
| 1212 | case X86::JO: return X86::COND_O; |
| 1213 | case X86::JNO: return X86::COND_NO; |
| 1214 | } |
| 1215 | } |
| 1216 | |
| 1217 | unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { |
| 1218 | switch (CC) { |
| 1219 | default: assert(0 && "Illegal condition code!"); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1220 | case X86::COND_E: return X86::JE; |
| 1221 | case X86::COND_NE: return X86::JNE; |
| 1222 | case X86::COND_L: return X86::JL; |
| 1223 | case X86::COND_LE: return X86::JLE; |
| 1224 | case X86::COND_G: return X86::JG; |
| 1225 | case X86::COND_GE: return X86::JGE; |
| 1226 | case X86::COND_B: return X86::JB; |
| 1227 | case X86::COND_BE: return X86::JBE; |
| 1228 | case X86::COND_A: return X86::JA; |
| 1229 | case X86::COND_AE: return X86::JAE; |
| 1230 | case X86::COND_S: return X86::JS; |
| 1231 | case X86::COND_NS: return X86::JNS; |
| 1232 | case X86::COND_P: return X86::JP; |
| 1233 | case X86::COND_NP: return X86::JNP; |
| 1234 | case X86::COND_O: return X86::JO; |
| 1235 | case X86::COND_NO: return X86::JNO; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1236 | } |
| 1237 | } |
| 1238 | |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 1239 | /// GetOppositeBranchCondition - Return the inverse of the specified condition, |
| 1240 | /// e.g. turning COND_E to COND_NE. |
| 1241 | X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { |
| 1242 | switch (CC) { |
| 1243 | default: assert(0 && "Illegal condition code!"); |
| 1244 | case X86::COND_E: return X86::COND_NE; |
| 1245 | case X86::COND_NE: return X86::COND_E; |
| 1246 | case X86::COND_L: return X86::COND_GE; |
| 1247 | case X86::COND_LE: return X86::COND_G; |
| 1248 | case X86::COND_G: return X86::COND_LE; |
| 1249 | case X86::COND_GE: return X86::COND_L; |
| 1250 | case X86::COND_B: return X86::COND_AE; |
| 1251 | case X86::COND_BE: return X86::COND_A; |
| 1252 | case X86::COND_A: return X86::COND_BE; |
| 1253 | case X86::COND_AE: return X86::COND_B; |
| 1254 | case X86::COND_S: return X86::COND_NS; |
| 1255 | case X86::COND_NS: return X86::COND_S; |
| 1256 | case X86::COND_P: return X86::COND_NP; |
| 1257 | case X86::COND_NP: return X86::COND_P; |
| 1258 | case X86::COND_O: return X86::COND_NO; |
| 1259 | case X86::COND_NO: return X86::COND_O; |
| 1260 | } |
| 1261 | } |
| 1262 | |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 1263 | bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1264 | const TargetInstrDesc &TID = MI->getDesc(); |
| 1265 | if (!TID.isTerminator()) return false; |
Chris Lattner | 6924430 | 2008-01-07 01:56:04 +0000 | [diff] [blame] | 1266 | |
| 1267 | // Conditional branch is a special case. |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1268 | if (TID.isBranch() && !TID.isBarrier()) |
Chris Lattner | 6924430 | 2008-01-07 01:56:04 +0000 | [diff] [blame] | 1269 | return true; |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1270 | if (!TID.isPredicable()) |
Chris Lattner | 6924430 | 2008-01-07 01:56:04 +0000 | [diff] [blame] | 1271 | return true; |
| 1272 | return !isPredicated(MI); |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 1273 | } |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 1274 | |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 1275 | // For purposes of branch analysis do not count FP_REG_KILL as a terminator. |
| 1276 | static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, |
| 1277 | const X86InstrInfo &TII) { |
| 1278 | if (MI->getOpcode() == X86::FP_REG_KILL) |
| 1279 | return false; |
| 1280 | return TII.isUnpredicatedTerminator(MI); |
| 1281 | } |
| 1282 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1283 | bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, |
| 1284 | MachineBasicBlock *&TBB, |
| 1285 | MachineBasicBlock *&FBB, |
| 1286 | std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1287 | // If the block has no terminators, it just falls into the block after it. |
| 1288 | MachineBasicBlock::iterator I = MBB.end(); |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 1289 | if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1290 | return false; |
| 1291 | |
| 1292 | // Get the last instruction in the block. |
| 1293 | MachineInstr *LastInst = I; |
| 1294 | |
| 1295 | // If there is only one terminator instruction, process it. |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 1296 | if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) { |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1297 | if (!LastInst->getDesc().isBranch()) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1298 | return true; |
| 1299 | |
| 1300 | // If the block ends with a branch there are 3 possibilities: |
| 1301 | // it's an unconditional, conditional, or indirect branch. |
| 1302 | |
| 1303 | if (LastInst->getOpcode() == X86::JMP) { |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 1304 | TBB = LastInst->getOperand(0).getMBB(); |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1305 | return false; |
| 1306 | } |
| 1307 | X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); |
| 1308 | if (BranchCode == X86::COND_INVALID) |
| 1309 | return true; // Can't handle indirect branch. |
| 1310 | |
| 1311 | // Otherwise, block ends with fall-through condbranch. |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 1312 | TBB = LastInst->getOperand(0).getMBB(); |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1313 | Cond.push_back(MachineOperand::CreateImm(BranchCode)); |
| 1314 | return false; |
| 1315 | } |
| 1316 | |
| 1317 | // Get the instruction before it if it's a terminator. |
| 1318 | MachineInstr *SecondLastInst = I; |
| 1319 | |
| 1320 | // If there are three terminators, we don't know what sort of block this is. |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 1321 | if (SecondLastInst && I != MBB.begin() && |
| 1322 | isBrAnalysisUnpredicatedTerminator(--I, *this)) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1323 | return true; |
| 1324 | |
Chris Lattner | 6ce6443 | 2006-10-30 22:27:23 +0000 | [diff] [blame] | 1325 | // If the block ends with X86::JMP and a conditional branch, handle it. |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1326 | X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode()); |
| 1327 | if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) { |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 1328 | TBB = SecondLastInst->getOperand(0).getMBB(); |
Chris Lattner | 6ce6443 | 2006-10-30 22:27:23 +0000 | [diff] [blame] | 1329 | Cond.push_back(MachineOperand::CreateImm(BranchCode)); |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 1330 | FBB = LastInst->getOperand(0).getMBB(); |
Chris Lattner | 6ce6443 | 2006-10-30 22:27:23 +0000 | [diff] [blame] | 1331 | return false; |
| 1332 | } |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1333 | |
Dale Johannesen | 13e8b51 | 2007-06-13 17:59:52 +0000 | [diff] [blame] | 1334 | // If the block ends with two X86::JMPs, handle it. The second one is not |
| 1335 | // executed, so remove it. |
| 1336 | if (SecondLastInst->getOpcode() == X86::JMP && |
| 1337 | LastInst->getOpcode() == X86::JMP) { |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 1338 | TBB = SecondLastInst->getOperand(0).getMBB(); |
Dale Johannesen | 13e8b51 | 2007-06-13 17:59:52 +0000 | [diff] [blame] | 1339 | I = LastInst; |
| 1340 | I->eraseFromParent(); |
| 1341 | return false; |
| 1342 | } |
| 1343 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1344 | // Otherwise, can't handle this. |
| 1345 | return true; |
| 1346 | } |
| 1347 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1348 | unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1349 | MachineBasicBlock::iterator I = MBB.end(); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1350 | if (I == MBB.begin()) return 0; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1351 | --I; |
| 1352 | if (I->getOpcode() != X86::JMP && |
| 1353 | GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1354 | return 0; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1355 | |
| 1356 | // Remove the branch. |
| 1357 | I->eraseFromParent(); |
| 1358 | |
| 1359 | I = MBB.end(); |
| 1360 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1361 | if (I == MBB.begin()) return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1362 | --I; |
| 1363 | if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1364 | return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1365 | |
| 1366 | // Remove the branch. |
| 1367 | I->eraseFromParent(); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1368 | return 2; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1369 | } |
| 1370 | |
Owen Anderson | f6372aa | 2008-01-01 21:11:32 +0000 | [diff] [blame] | 1371 | static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB, |
| 1372 | MachineOperand &MO) { |
| 1373 | if (MO.isRegister()) |
| 1374 | MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(), |
| 1375 | false, false, MO.getSubReg()); |
| 1376 | else if (MO.isImmediate()) |
| 1377 | MIB = MIB.addImm(MO.getImm()); |
| 1378 | else if (MO.isFrameIndex()) |
| 1379 | MIB = MIB.addFrameIndex(MO.getIndex()); |
| 1380 | else if (MO.isGlobalAddress()) |
| 1381 | MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset()); |
| 1382 | else if (MO.isConstantPoolIndex()) |
| 1383 | MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset()); |
| 1384 | else if (MO.isJumpTableIndex()) |
| 1385 | MIB = MIB.addJumpTableIndex(MO.getIndex()); |
| 1386 | else if (MO.isExternalSymbol()) |
| 1387 | MIB = MIB.addExternalSymbol(MO.getSymbolName()); |
| 1388 | else |
| 1389 | assert(0 && "Unknown operand for X86InstrAddOperand!"); |
| 1390 | |
| 1391 | return MIB; |
| 1392 | } |
| 1393 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1394 | unsigned |
| 1395 | X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 1396 | MachineBasicBlock *FBB, |
| 1397 | const std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1398 | // Shouldn't be a fall through. |
| 1399 | assert(TBB && "InsertBranch must not be told to insert a fallthrough"); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 1400 | assert((Cond.size() == 1 || Cond.size() == 0) && |
| 1401 | "X86 branch conditions have one component!"); |
| 1402 | |
| 1403 | if (FBB == 0) { // One way branch. |
| 1404 | if (Cond.empty()) { |
| 1405 | // Unconditional branch? |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1406 | BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 1407 | } else { |
| 1408 | // Conditional branch. |
| 1409 | unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1410 | BuildMI(&MBB, get(Opc)).addMBB(TBB); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 1411 | } |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1412 | return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1413 | } |
| 1414 | |
Chris Lattner | 879d09c | 2006-10-21 05:42:09 +0000 | [diff] [blame] | 1415 | // Two-way Conditional branch. |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1416 | unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1417 | BuildMI(&MBB, get(Opc)).addMBB(TBB); |
| 1418 | BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 1419 | return 2; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1420 | } |
| 1421 | |
Owen Anderson | d10fd97 | 2007-12-31 06:32:00 +0000 | [diff] [blame] | 1422 | void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, |
Chris Lattner | 5c92750 | 2008-03-09 08:46:19 +0000 | [diff] [blame] | 1423 | MachineBasicBlock::iterator MI, |
| 1424 | unsigned DestReg, unsigned SrcReg, |
| 1425 | const TargetRegisterClass *DestRC, |
| 1426 | const TargetRegisterClass *SrcRC) const { |
Chris Lattner | 90b347d | 2008-03-09 07:58:04 +0000 | [diff] [blame] | 1427 | if (DestRC == SrcRC) { |
| 1428 | unsigned Opc; |
| 1429 | if (DestRC == &X86::GR64RegClass) { |
| 1430 | Opc = X86::MOV64rr; |
| 1431 | } else if (DestRC == &X86::GR32RegClass) { |
| 1432 | Opc = X86::MOV32rr; |
| 1433 | } else if (DestRC == &X86::GR16RegClass) { |
| 1434 | Opc = X86::MOV16rr; |
| 1435 | } else if (DestRC == &X86::GR8RegClass) { |
| 1436 | Opc = X86::MOV8rr; |
| 1437 | } else if (DestRC == &X86::GR32_RegClass) { |
| 1438 | Opc = X86::MOV32_rr; |
| 1439 | } else if (DestRC == &X86::GR16_RegClass) { |
| 1440 | Opc = X86::MOV16_rr; |
| 1441 | } else if (DestRC == &X86::RFP32RegClass) { |
| 1442 | Opc = X86::MOV_Fp3232; |
| 1443 | } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { |
| 1444 | Opc = X86::MOV_Fp6464; |
| 1445 | } else if (DestRC == &X86::RFP80RegClass) { |
| 1446 | Opc = X86::MOV_Fp8080; |
| 1447 | } else if (DestRC == &X86::FR32RegClass) { |
| 1448 | Opc = X86::FsMOVAPSrr; |
| 1449 | } else if (DestRC == &X86::FR64RegClass) { |
| 1450 | Opc = X86::FsMOVAPDrr; |
| 1451 | } else if (DestRC == &X86::VR128RegClass) { |
| 1452 | Opc = X86::MOVAPSrr; |
| 1453 | } else if (DestRC == &X86::VR64RegClass) { |
| 1454 | Opc = X86::MMX_MOVQ64rr; |
| 1455 | } else { |
| 1456 | assert(0 && "Unknown regclass"); |
| 1457 | abort(); |
Owen Anderson | d10fd97 | 2007-12-31 06:32:00 +0000 | [diff] [blame] | 1458 | } |
Chris Lattner | 90b347d | 2008-03-09 07:58:04 +0000 | [diff] [blame] | 1459 | BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); |
| 1460 | return; |
Owen Anderson | d10fd97 | 2007-12-31 06:32:00 +0000 | [diff] [blame] | 1461 | } |
Chris Lattner | 90b347d | 2008-03-09 07:58:04 +0000 | [diff] [blame] | 1462 | |
| 1463 | // Moving EFLAGS to / from another register requires a push and a pop. |
| 1464 | if (SrcRC == &X86::CCRRegClass) { |
| 1465 | assert(SrcReg == X86::EFLAGS); |
| 1466 | if (DestRC == &X86::GR64RegClass) { |
| 1467 | BuildMI(MBB, MI, get(X86::PUSHFQ)); |
| 1468 | BuildMI(MBB, MI, get(X86::POP64r), DestReg); |
| 1469 | return; |
| 1470 | } else if (DestRC == &X86::GR32RegClass) { |
| 1471 | BuildMI(MBB, MI, get(X86::PUSHFD)); |
| 1472 | BuildMI(MBB, MI, get(X86::POP32r), DestReg); |
| 1473 | return; |
| 1474 | } |
| 1475 | } else if (DestRC == &X86::CCRRegClass) { |
| 1476 | assert(DestReg == X86::EFLAGS); |
| 1477 | if (SrcRC == &X86::GR64RegClass) { |
| 1478 | BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg); |
| 1479 | BuildMI(MBB, MI, get(X86::POPFQ)); |
| 1480 | return; |
| 1481 | } else if (SrcRC == &X86::GR32RegClass) { |
| 1482 | BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg); |
| 1483 | BuildMI(MBB, MI, get(X86::POPFD)); |
| 1484 | return; |
| 1485 | } |
Owen Anderson | d10fd97 | 2007-12-31 06:32:00 +0000 | [diff] [blame] | 1486 | } |
Chris Lattner | 5c92750 | 2008-03-09 08:46:19 +0000 | [diff] [blame] | 1487 | |
Chris Lattner | f30e1cf | 2008-03-09 09:15:31 +0000 | [diff] [blame] | 1488 | // Moving from ST(0) turns into FpGET_ST0_32 etc. |
Chris Lattner | 5c92750 | 2008-03-09 08:46:19 +0000 | [diff] [blame] | 1489 | if (SrcRC == &X86::RSTRegClass) { |
| 1490 | // Copying from ST(0). FIXME: handle ST(1) also |
| 1491 | assert(SrcReg == X86::ST0 && "Can only copy from TOS right now"); |
| 1492 | unsigned Opc; |
| 1493 | if (DestRC == &X86::RFP32RegClass) |
| 1494 | Opc = X86::FpGET_ST0_32; |
| 1495 | else if (DestRC == &X86::RFP64RegClass) |
| 1496 | Opc = X86::FpGET_ST0_64; |
| 1497 | else { |
| 1498 | assert(DestRC == &X86::RFP80RegClass); |
| 1499 | Opc = X86::FpGET_ST0_80; |
| 1500 | } |
| 1501 | BuildMI(MBB, MI, get(Opc), DestReg); |
| 1502 | return; |
| 1503 | } |
Chris Lattner | f30e1cf | 2008-03-09 09:15:31 +0000 | [diff] [blame] | 1504 | |
| 1505 | // Moving to ST(0) turns into FpSET_ST0_32 etc. |
| 1506 | if (DestRC == &X86::RSTRegClass) { |
| 1507 | // Copying to ST(0). FIXME: handle ST(1) also |
| 1508 | assert(DestReg == X86::ST0 && "Can only copy to TOS right now"); |
| 1509 | unsigned Opc; |
| 1510 | if (SrcRC == &X86::RFP32RegClass) |
| 1511 | Opc = X86::FpSET_ST0_32; |
| 1512 | else if (SrcRC == &X86::RFP64RegClass) |
| 1513 | Opc = X86::FpSET_ST0_64; |
| 1514 | else { |
| 1515 | assert(SrcRC == &X86::RFP80RegClass); |
| 1516 | Opc = X86::FpSET_ST0_80; |
| 1517 | } |
| 1518 | BuildMI(MBB, MI, get(Opc)).addReg(SrcReg); |
| 1519 | return; |
| 1520 | } |
Chris Lattner | 5c92750 | 2008-03-09 08:46:19 +0000 | [diff] [blame] | 1521 | |
Chris Lattner | 183275a | 2008-03-10 23:56:08 +0000 | [diff] [blame] | 1522 | assert(0 && "Not yet supported!"); |
Chris Lattner | 90b347d | 2008-03-09 07:58:04 +0000 | [diff] [blame] | 1523 | abort(); |
Owen Anderson | d10fd97 | 2007-12-31 06:32:00 +0000 | [diff] [blame] | 1524 | } |
| 1525 | |
Owen Anderson | f6372aa | 2008-01-01 21:11:32 +0000 | [diff] [blame] | 1526 | static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, |
| 1527 | unsigned StackAlign) { |
| 1528 | unsigned Opc = 0; |
| 1529 | if (RC == &X86::GR64RegClass) { |
| 1530 | Opc = X86::MOV64mr; |
| 1531 | } else if (RC == &X86::GR32RegClass) { |
| 1532 | Opc = X86::MOV32mr; |
| 1533 | } else if (RC == &X86::GR16RegClass) { |
| 1534 | Opc = X86::MOV16mr; |
| 1535 | } else if (RC == &X86::GR8RegClass) { |
| 1536 | Opc = X86::MOV8mr; |
| 1537 | } else if (RC == &X86::GR32_RegClass) { |
| 1538 | Opc = X86::MOV32_mr; |
| 1539 | } else if (RC == &X86::GR16_RegClass) { |
| 1540 | Opc = X86::MOV16_mr; |
| 1541 | } else if (RC == &X86::RFP80RegClass) { |
| 1542 | Opc = X86::ST_FpP80m; // pops |
| 1543 | } else if (RC == &X86::RFP64RegClass) { |
| 1544 | Opc = X86::ST_Fp64m; |
| 1545 | } else if (RC == &X86::RFP32RegClass) { |
| 1546 | Opc = X86::ST_Fp32m; |
| 1547 | } else if (RC == &X86::FR32RegClass) { |
| 1548 | Opc = X86::MOVSSmr; |
| 1549 | } else if (RC == &X86::FR64RegClass) { |
| 1550 | Opc = X86::MOVSDmr; |
| 1551 | } else if (RC == &X86::VR128RegClass) { |
| 1552 | // FIXME: Use movaps once we are capable of selectively |
| 1553 | // aligning functions that spill SSE registers on 16-byte boundaries. |
| 1554 | Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr; |
| 1555 | } else if (RC == &X86::VR64RegClass) { |
| 1556 | Opc = X86::MMX_MOVQ64mr; |
| 1557 | } else { |
| 1558 | assert(0 && "Unknown regclass"); |
| 1559 | abort(); |
| 1560 | } |
| 1561 | |
| 1562 | return Opc; |
| 1563 | } |
| 1564 | |
| 1565 | void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| 1566 | MachineBasicBlock::iterator MI, |
| 1567 | unsigned SrcReg, bool isKill, int FrameIdx, |
| 1568 | const TargetRegisterClass *RC) const { |
| 1569 | unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment()); |
| 1570 | addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx) |
| 1571 | .addReg(SrcReg, false, false, isKill); |
| 1572 | } |
| 1573 | |
| 1574 | void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, |
| 1575 | bool isKill, |
| 1576 | SmallVectorImpl<MachineOperand> &Addr, |
| 1577 | const TargetRegisterClass *RC, |
| 1578 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
| 1579 | unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment()); |
| 1580 | MachineInstrBuilder MIB = BuildMI(get(Opc)); |
| 1581 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) |
| 1582 | MIB = X86InstrAddOperand(MIB, Addr[i]); |
| 1583 | MIB.addReg(SrcReg, false, false, isKill); |
| 1584 | NewMIs.push_back(MIB); |
| 1585 | } |
| 1586 | |
| 1587 | static unsigned getLoadRegOpcode(const TargetRegisterClass *RC, |
| 1588 | unsigned StackAlign) { |
| 1589 | unsigned Opc = 0; |
| 1590 | if (RC == &X86::GR64RegClass) { |
| 1591 | Opc = X86::MOV64rm; |
| 1592 | } else if (RC == &X86::GR32RegClass) { |
| 1593 | Opc = X86::MOV32rm; |
| 1594 | } else if (RC == &X86::GR16RegClass) { |
| 1595 | Opc = X86::MOV16rm; |
| 1596 | } else if (RC == &X86::GR8RegClass) { |
| 1597 | Opc = X86::MOV8rm; |
| 1598 | } else if (RC == &X86::GR32_RegClass) { |
| 1599 | Opc = X86::MOV32_rm; |
| 1600 | } else if (RC == &X86::GR16_RegClass) { |
| 1601 | Opc = X86::MOV16_rm; |
| 1602 | } else if (RC == &X86::RFP80RegClass) { |
| 1603 | Opc = X86::LD_Fp80m; |
| 1604 | } else if (RC == &X86::RFP64RegClass) { |
| 1605 | Opc = X86::LD_Fp64m; |
| 1606 | } else if (RC == &X86::RFP32RegClass) { |
| 1607 | Opc = X86::LD_Fp32m; |
| 1608 | } else if (RC == &X86::FR32RegClass) { |
| 1609 | Opc = X86::MOVSSrm; |
| 1610 | } else if (RC == &X86::FR64RegClass) { |
| 1611 | Opc = X86::MOVSDrm; |
| 1612 | } else if (RC == &X86::VR128RegClass) { |
| 1613 | // FIXME: Use movaps once we are capable of selectively |
| 1614 | // aligning functions that spill SSE registers on 16-byte boundaries. |
| 1615 | Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm; |
| 1616 | } else if (RC == &X86::VR64RegClass) { |
| 1617 | Opc = X86::MMX_MOVQ64rm; |
| 1618 | } else { |
| 1619 | assert(0 && "Unknown regclass"); |
| 1620 | abort(); |
| 1621 | } |
| 1622 | |
| 1623 | return Opc; |
| 1624 | } |
| 1625 | |
| 1626 | void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 1627 | MachineBasicBlock::iterator MI, |
| 1628 | unsigned DestReg, int FrameIdx, |
| 1629 | const TargetRegisterClass *RC) const{ |
| 1630 | unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment()); |
| 1631 | addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx); |
| 1632 | } |
| 1633 | |
| 1634 | void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
| 1635 | SmallVectorImpl<MachineOperand> &Addr, |
| 1636 | const TargetRegisterClass *RC, |
| 1637 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
| 1638 | unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment()); |
| 1639 | MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); |
| 1640 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) |
| 1641 | MIB = X86InstrAddOperand(MIB, Addr[i]); |
| 1642 | NewMIs.push_back(MIB); |
| 1643 | } |
| 1644 | |
Owen Anderson | d94b6a1 | 2008-01-04 23:57:37 +0000 | [diff] [blame] | 1645 | bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 1646 | MachineBasicBlock::iterator MI, |
| 1647 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 1648 | if (CSI.empty()) |
| 1649 | return false; |
| 1650 | |
| 1651 | bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); |
| 1652 | unsigned SlotSize = is64Bit ? 8 : 4; |
| 1653 | |
| 1654 | MachineFunction &MF = *MBB.getParent(); |
| 1655 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
| 1656 | X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize); |
| 1657 | |
| 1658 | unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; |
| 1659 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 1660 | unsigned Reg = CSI[i-1].getReg(); |
| 1661 | // Add the callee-saved register as live-in. It's killed at the spill. |
| 1662 | MBB.addLiveIn(Reg); |
| 1663 | BuildMI(MBB, MI, get(Opc)).addReg(Reg); |
| 1664 | } |
| 1665 | return true; |
| 1666 | } |
| 1667 | |
| 1668 | bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 1669 | MachineBasicBlock::iterator MI, |
| 1670 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 1671 | if (CSI.empty()) |
| 1672 | return false; |
| 1673 | |
| 1674 | bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); |
| 1675 | |
| 1676 | unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; |
| 1677 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 1678 | unsigned Reg = CSI[i].getReg(); |
| 1679 | BuildMI(MBB, MI, get(Opc), Reg); |
| 1680 | } |
| 1681 | return true; |
| 1682 | } |
| 1683 | |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1684 | static MachineInstr *FuseTwoAddrInst(unsigned Opcode, |
| 1685 | SmallVector<MachineOperand,4> &MOs, |
| 1686 | MachineInstr *MI, const TargetInstrInfo &TII) { |
| 1687 | // Create the base instruction with the memory operand as the first part. |
| 1688 | MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true); |
| 1689 | MachineInstrBuilder MIB(NewMI); |
| 1690 | unsigned NumAddrOps = MOs.size(); |
| 1691 | for (unsigned i = 0; i != NumAddrOps; ++i) |
| 1692 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
| 1693 | if (NumAddrOps < 4) // FrameIndex only |
| 1694 | MIB.addImm(1).addReg(0).addImm(0); |
| 1695 | |
| 1696 | // Loop over the rest of the ri operands, converting them over. |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1697 | unsigned NumOps = MI->getDesc().getNumOperands()-2; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1698 | for (unsigned i = 0; i != NumOps; ++i) { |
| 1699 | MachineOperand &MO = MI->getOperand(i+2); |
| 1700 | MIB = X86InstrAddOperand(MIB, MO); |
| 1701 | } |
| 1702 | for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { |
| 1703 | MachineOperand &MO = MI->getOperand(i); |
| 1704 | MIB = X86InstrAddOperand(MIB, MO); |
| 1705 | } |
| 1706 | return MIB; |
| 1707 | } |
| 1708 | |
| 1709 | static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, |
| 1710 | SmallVector<MachineOperand,4> &MOs, |
| 1711 | MachineInstr *MI, const TargetInstrInfo &TII) { |
| 1712 | MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true); |
| 1713 | MachineInstrBuilder MIB(NewMI); |
| 1714 | |
| 1715 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 1716 | MachineOperand &MO = MI->getOperand(i); |
| 1717 | if (i == OpNo) { |
| 1718 | assert(MO.isRegister() && "Expected to fold into reg operand!"); |
| 1719 | unsigned NumAddrOps = MOs.size(); |
| 1720 | for (unsigned i = 0; i != NumAddrOps; ++i) |
| 1721 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
| 1722 | if (NumAddrOps < 4) // FrameIndex only |
| 1723 | MIB.addImm(1).addReg(0).addImm(0); |
| 1724 | } else { |
| 1725 | MIB = X86InstrAddOperand(MIB, MO); |
| 1726 | } |
| 1727 | } |
| 1728 | return MIB; |
| 1729 | } |
| 1730 | |
| 1731 | static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, |
| 1732 | SmallVector<MachineOperand,4> &MOs, |
| 1733 | MachineInstr *MI) { |
| 1734 | MachineInstrBuilder MIB = BuildMI(TII.get(Opcode)); |
| 1735 | |
| 1736 | unsigned NumAddrOps = MOs.size(); |
| 1737 | for (unsigned i = 0; i != NumAddrOps; ++i) |
| 1738 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
| 1739 | if (NumAddrOps < 4) // FrameIndex only |
| 1740 | MIB.addImm(1).addReg(0).addImm(0); |
| 1741 | return MIB.addImm(0); |
| 1742 | } |
| 1743 | |
| 1744 | MachineInstr* |
| 1745 | X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, |
Evan Cheng | 5fd79d0 | 2008-02-08 21:20:40 +0000 | [diff] [blame] | 1746 | SmallVector<MachineOperand,4> &MOs) const { |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1747 | const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; |
| 1748 | bool isTwoAddrFold = false; |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1749 | unsigned NumOps = MI->getDesc().getNumOperands(); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1750 | bool isTwoAddr = NumOps > 1 && |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1751 | MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1752 | |
| 1753 | MachineInstr *NewMI = NULL; |
| 1754 | // Folding a memory location into the two-address part of a two-address |
| 1755 | // instruction is different than folding it other places. It requires |
| 1756 | // replacing the *two* registers with the memory location. |
| 1757 | if (isTwoAddr && NumOps >= 2 && i < 2 && |
| 1758 | MI->getOperand(0).isRegister() && |
| 1759 | MI->getOperand(1).isRegister() && |
| 1760 | MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { |
| 1761 | OpcodeTablePtr = &RegOp2MemOpTable2Addr; |
| 1762 | isTwoAddrFold = true; |
| 1763 | } else if (i == 0) { // If operand 0 |
| 1764 | if (MI->getOpcode() == X86::MOV16r0) |
| 1765 | NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); |
| 1766 | else if (MI->getOpcode() == X86::MOV32r0) |
| 1767 | NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); |
| 1768 | else if (MI->getOpcode() == X86::MOV64r0) |
| 1769 | NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); |
| 1770 | else if (MI->getOpcode() == X86::MOV8r0) |
| 1771 | NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); |
| 1772 | if (NewMI) { |
| 1773 | NewMI->copyKillDeadInfo(MI); |
| 1774 | return NewMI; |
| 1775 | } |
| 1776 | |
| 1777 | OpcodeTablePtr = &RegOp2MemOpTable0; |
| 1778 | } else if (i == 1) { |
| 1779 | OpcodeTablePtr = &RegOp2MemOpTable1; |
| 1780 | } else if (i == 2) { |
| 1781 | OpcodeTablePtr = &RegOp2MemOpTable2; |
| 1782 | } |
| 1783 | |
| 1784 | // If table selected... |
| 1785 | if (OpcodeTablePtr) { |
| 1786 | // Find the Opcode to fuse |
| 1787 | DenseMap<unsigned*, unsigned>::iterator I = |
| 1788 | OpcodeTablePtr->find((unsigned*)MI->getOpcode()); |
| 1789 | if (I != OpcodeTablePtr->end()) { |
| 1790 | if (isTwoAddrFold) |
| 1791 | NewMI = FuseTwoAddrInst(I->second, MOs, MI, *this); |
| 1792 | else |
| 1793 | NewMI = FuseInst(I->second, i, MOs, MI, *this); |
| 1794 | NewMI->copyKillDeadInfo(MI); |
| 1795 | return NewMI; |
| 1796 | } |
| 1797 | } |
| 1798 | |
| 1799 | // No fusion |
| 1800 | if (PrintFailedFusing) |
Chris Lattner | 269f059 | 2008-01-09 00:37:18 +0000 | [diff] [blame] | 1801 | cerr << "We failed to fuse operand " << i << *MI; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1802 | return NULL; |
| 1803 | } |
| 1804 | |
| 1805 | |
Evan Cheng | 5fd79d0 | 2008-02-08 21:20:40 +0000 | [diff] [blame] | 1806 | MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, |
| 1807 | MachineInstr *MI, |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1808 | SmallVectorImpl<unsigned> &Ops, |
| 1809 | int FrameIndex) const { |
| 1810 | // Check switch flag |
| 1811 | if (NoFusing) return NULL; |
| 1812 | |
Evan Cheng | 5fd79d0 | 2008-02-08 21:20:40 +0000 | [diff] [blame] | 1813 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1814 | unsigned Alignment = MFI->getObjectAlignment(FrameIndex); |
| 1815 | // FIXME: Move alignment requirement into tables? |
| 1816 | if (Alignment < 16) { |
| 1817 | switch (MI->getOpcode()) { |
| 1818 | default: break; |
| 1819 | // Not always safe to fold movsd into these instructions since their load |
| 1820 | // folding variants expects the address to be 16 byte aligned. |
| 1821 | case X86::FsANDNPDrr: |
| 1822 | case X86::FsANDNPSrr: |
| 1823 | case X86::FsANDPDrr: |
| 1824 | case X86::FsANDPSrr: |
| 1825 | case X86::FsORPDrr: |
| 1826 | case X86::FsORPSrr: |
| 1827 | case X86::FsXORPDrr: |
| 1828 | case X86::FsXORPSrr: |
| 1829 | return NULL; |
| 1830 | } |
| 1831 | } |
| 1832 | |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1833 | if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { |
| 1834 | unsigned NewOpc = 0; |
| 1835 | switch (MI->getOpcode()) { |
| 1836 | default: return NULL; |
| 1837 | case X86::TEST8rr: NewOpc = X86::CMP8ri; break; |
| 1838 | case X86::TEST16rr: NewOpc = X86::CMP16ri; break; |
| 1839 | case X86::TEST32rr: NewOpc = X86::CMP32ri; break; |
| 1840 | case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; |
| 1841 | } |
| 1842 | // Change to CMPXXri r, 0 first. |
Chris Lattner | 5080f4d | 2008-01-11 18:10:50 +0000 | [diff] [blame] | 1843 | MI->setDesc(get(NewOpc)); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1844 | MI->getOperand(1).ChangeToImmediate(0); |
| 1845 | } else if (Ops.size() != 1) |
| 1846 | return NULL; |
| 1847 | |
| 1848 | SmallVector<MachineOperand,4> MOs; |
| 1849 | MOs.push_back(MachineOperand::CreateFI(FrameIndex)); |
| 1850 | return foldMemoryOperand(MI, Ops[0], MOs); |
| 1851 | } |
| 1852 | |
Evan Cheng | 5fd79d0 | 2008-02-08 21:20:40 +0000 | [diff] [blame] | 1853 | MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, |
| 1854 | MachineInstr *MI, |
Chris Lattner | 269f059 | 2008-01-09 00:37:18 +0000 | [diff] [blame] | 1855 | SmallVectorImpl<unsigned> &Ops, |
| 1856 | MachineInstr *LoadMI) const { |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1857 | // Check switch flag |
| 1858 | if (NoFusing) return NULL; |
| 1859 | |
Evan Cheng | 5fd79d0 | 2008-02-08 21:20:40 +0000 | [diff] [blame] | 1860 | unsigned Alignment = 0; |
| 1861 | for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; ++i) { |
| 1862 | const MemOperand &MRO = LoadMI->getMemOperand(i); |
| 1863 | unsigned Align = MRO.getAlignment(); |
| 1864 | if (Align > Alignment) |
| 1865 | Alignment = Align; |
| 1866 | } |
| 1867 | |
| 1868 | // FIXME: Move alignment requirement into tables? |
| 1869 | if (Alignment < 16) { |
| 1870 | switch (MI->getOpcode()) { |
| 1871 | default: break; |
| 1872 | // Not always safe to fold movsd into these instructions since their load |
| 1873 | // folding variants expects the address to be 16 byte aligned. |
| 1874 | case X86::FsANDNPDrr: |
| 1875 | case X86::FsANDNPSrr: |
| 1876 | case X86::FsANDPDrr: |
| 1877 | case X86::FsANDPSrr: |
| 1878 | case X86::FsORPDrr: |
| 1879 | case X86::FsORPSrr: |
| 1880 | case X86::FsXORPDrr: |
| 1881 | case X86::FsXORPSrr: |
| 1882 | return NULL; |
| 1883 | } |
| 1884 | } |
| 1885 | |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1886 | if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { |
| 1887 | unsigned NewOpc = 0; |
| 1888 | switch (MI->getOpcode()) { |
| 1889 | default: return NULL; |
| 1890 | case X86::TEST8rr: NewOpc = X86::CMP8ri; break; |
| 1891 | case X86::TEST16rr: NewOpc = X86::CMP16ri; break; |
| 1892 | case X86::TEST32rr: NewOpc = X86::CMP32ri; break; |
| 1893 | case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; |
| 1894 | } |
| 1895 | // Change to CMPXXri r, 0 first. |
Chris Lattner | 5080f4d | 2008-01-11 18:10:50 +0000 | [diff] [blame] | 1896 | MI->setDesc(get(NewOpc)); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1897 | MI->getOperand(1).ChangeToImmediate(0); |
| 1898 | } else if (Ops.size() != 1) |
| 1899 | return NULL; |
| 1900 | |
| 1901 | SmallVector<MachineOperand,4> MOs; |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1902 | unsigned NumOps = LoadMI->getDesc().getNumOperands(); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1903 | for (unsigned i = NumOps - 4; i != NumOps; ++i) |
| 1904 | MOs.push_back(LoadMI->getOperand(i)); |
| 1905 | return foldMemoryOperand(MI, Ops[0], MOs); |
| 1906 | } |
| 1907 | |
| 1908 | |
| 1909 | bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI, |
Chris Lattner | 269f059 | 2008-01-09 00:37:18 +0000 | [diff] [blame] | 1910 | SmallVectorImpl<unsigned> &Ops) const { |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1911 | // Check switch flag |
| 1912 | if (NoFusing) return 0; |
| 1913 | |
| 1914 | if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { |
| 1915 | switch (MI->getOpcode()) { |
| 1916 | default: return false; |
| 1917 | case X86::TEST8rr: |
| 1918 | case X86::TEST16rr: |
| 1919 | case X86::TEST32rr: |
| 1920 | case X86::TEST64rr: |
| 1921 | return true; |
| 1922 | } |
| 1923 | } |
| 1924 | |
| 1925 | if (Ops.size() != 1) |
| 1926 | return false; |
| 1927 | |
| 1928 | unsigned OpNum = Ops[0]; |
| 1929 | unsigned Opc = MI->getOpcode(); |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1930 | unsigned NumOps = MI->getDesc().getNumOperands(); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1931 | bool isTwoAddr = NumOps > 1 && |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1932 | MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1933 | |
| 1934 | // Folding a memory location into the two-address part of a two-address |
| 1935 | // instruction is different than folding it other places. It requires |
| 1936 | // replacing the *two* registers with the memory location. |
| 1937 | const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; |
| 1938 | if (isTwoAddr && NumOps >= 2 && OpNum < 2) { |
| 1939 | OpcodeTablePtr = &RegOp2MemOpTable2Addr; |
| 1940 | } else if (OpNum == 0) { // If operand 0 |
| 1941 | switch (Opc) { |
| 1942 | case X86::MOV16r0: |
| 1943 | case X86::MOV32r0: |
| 1944 | case X86::MOV64r0: |
| 1945 | case X86::MOV8r0: |
| 1946 | return true; |
| 1947 | default: break; |
| 1948 | } |
| 1949 | OpcodeTablePtr = &RegOp2MemOpTable0; |
| 1950 | } else if (OpNum == 1) { |
| 1951 | OpcodeTablePtr = &RegOp2MemOpTable1; |
| 1952 | } else if (OpNum == 2) { |
| 1953 | OpcodeTablePtr = &RegOp2MemOpTable2; |
| 1954 | } |
| 1955 | |
| 1956 | if (OpcodeTablePtr) { |
| 1957 | // Find the Opcode to fuse |
| 1958 | DenseMap<unsigned*, unsigned>::iterator I = |
| 1959 | OpcodeTablePtr->find((unsigned*)Opc); |
| 1960 | if (I != OpcodeTablePtr->end()) |
| 1961 | return true; |
| 1962 | } |
| 1963 | return false; |
| 1964 | } |
| 1965 | |
| 1966 | bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, |
| 1967 | unsigned Reg, bool UnfoldLoad, bool UnfoldStore, |
| 1968 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
| 1969 | DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = |
| 1970 | MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); |
| 1971 | if (I == MemOp2RegOpTable.end()) |
| 1972 | return false; |
| 1973 | unsigned Opc = I->second.first; |
| 1974 | unsigned Index = I->second.second & 0xf; |
| 1975 | bool FoldedLoad = I->second.second & (1 << 4); |
| 1976 | bool FoldedStore = I->second.second & (1 << 5); |
| 1977 | if (UnfoldLoad && !FoldedLoad) |
| 1978 | return false; |
| 1979 | UnfoldLoad &= FoldedLoad; |
| 1980 | if (UnfoldStore && !FoldedStore) |
| 1981 | return false; |
| 1982 | UnfoldStore &= FoldedStore; |
| 1983 | |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 1984 | const TargetInstrDesc &TID = get(Opc); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1985 | const TargetOperandInfo &TOI = TID.OpInfo[Index]; |
Chris Lattner | 8ca5c67 | 2008-01-07 02:39:19 +0000 | [diff] [blame] | 1986 | const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 1987 | ? getPointerRegClass() : RI.getRegClass(TOI.RegClass); |
| 1988 | SmallVector<MachineOperand,4> AddrOps; |
| 1989 | SmallVector<MachineOperand,2> BeforeOps; |
| 1990 | SmallVector<MachineOperand,2> AfterOps; |
| 1991 | SmallVector<MachineOperand,4> ImpOps; |
| 1992 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 1993 | MachineOperand &Op = MI->getOperand(i); |
| 1994 | if (i >= Index && i < Index+4) |
| 1995 | AddrOps.push_back(Op); |
| 1996 | else if (Op.isRegister() && Op.isImplicit()) |
| 1997 | ImpOps.push_back(Op); |
| 1998 | else if (i < Index) |
| 1999 | BeforeOps.push_back(Op); |
| 2000 | else if (i > Index) |
| 2001 | AfterOps.push_back(Op); |
| 2002 | } |
| 2003 | |
| 2004 | // Emit the load instruction. |
| 2005 | if (UnfoldLoad) { |
| 2006 | loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs); |
| 2007 | if (UnfoldStore) { |
| 2008 | // Address operands cannot be marked isKill. |
| 2009 | for (unsigned i = 1; i != 5; ++i) { |
| 2010 | MachineOperand &MO = NewMIs[0]->getOperand(i); |
| 2011 | if (MO.isRegister()) |
| 2012 | MO.setIsKill(false); |
| 2013 | } |
| 2014 | } |
| 2015 | } |
| 2016 | |
| 2017 | // Emit the data processing instruction. |
| 2018 | MachineInstr *DataMI = new MachineInstr(TID, true); |
| 2019 | MachineInstrBuilder MIB(DataMI); |
| 2020 | |
| 2021 | if (FoldedStore) |
| 2022 | MIB.addReg(Reg, true); |
| 2023 | for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) |
| 2024 | MIB = X86InstrAddOperand(MIB, BeforeOps[i]); |
| 2025 | if (FoldedLoad) |
| 2026 | MIB.addReg(Reg); |
| 2027 | for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) |
| 2028 | MIB = X86InstrAddOperand(MIB, AfterOps[i]); |
| 2029 | for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { |
| 2030 | MachineOperand &MO = ImpOps[i]; |
| 2031 | MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead()); |
| 2032 | } |
| 2033 | // Change CMP32ri r, 0 back to TEST32rr r, r, etc. |
| 2034 | unsigned NewOpc = 0; |
| 2035 | switch (DataMI->getOpcode()) { |
| 2036 | default: break; |
| 2037 | case X86::CMP64ri32: |
| 2038 | case X86::CMP32ri: |
| 2039 | case X86::CMP16ri: |
| 2040 | case X86::CMP8ri: { |
| 2041 | MachineOperand &MO0 = DataMI->getOperand(0); |
| 2042 | MachineOperand &MO1 = DataMI->getOperand(1); |
| 2043 | if (MO1.getImm() == 0) { |
| 2044 | switch (DataMI->getOpcode()) { |
| 2045 | default: break; |
| 2046 | case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; |
| 2047 | case X86::CMP32ri: NewOpc = X86::TEST32rr; break; |
| 2048 | case X86::CMP16ri: NewOpc = X86::TEST16rr; break; |
| 2049 | case X86::CMP8ri: NewOpc = X86::TEST8rr; break; |
| 2050 | } |
Chris Lattner | 5080f4d | 2008-01-11 18:10:50 +0000 | [diff] [blame] | 2051 | DataMI->setDesc(get(NewOpc)); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 2052 | MO1.ChangeToRegister(MO0.getReg(), false); |
| 2053 | } |
| 2054 | } |
| 2055 | } |
| 2056 | NewMIs.push_back(DataMI); |
| 2057 | |
| 2058 | // Emit the store instruction. |
| 2059 | if (UnfoldStore) { |
| 2060 | const TargetOperandInfo &DstTOI = TID.OpInfo[0]; |
Chris Lattner | 8ca5c67 | 2008-01-07 02:39:19 +0000 | [diff] [blame] | 2061 | const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass() |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 2062 | ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); |
| 2063 | storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs); |
| 2064 | } |
| 2065 | |
| 2066 | return true; |
| 2067 | } |
| 2068 | |
| 2069 | bool |
| 2070 | X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, |
| 2071 | SmallVectorImpl<SDNode*> &NewNodes) const { |
| 2072 | if (!N->isTargetOpcode()) |
| 2073 | return false; |
| 2074 | |
| 2075 | DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = |
| 2076 | MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode()); |
| 2077 | if (I == MemOp2RegOpTable.end()) |
| 2078 | return false; |
| 2079 | unsigned Opc = I->second.first; |
| 2080 | unsigned Index = I->second.second & 0xf; |
| 2081 | bool FoldedLoad = I->second.second & (1 << 4); |
| 2082 | bool FoldedStore = I->second.second & (1 << 5); |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 2083 | const TargetInstrDesc &TID = get(Opc); |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 2084 | const TargetOperandInfo &TOI = TID.OpInfo[Index]; |
Chris Lattner | 8ca5c67 | 2008-01-07 02:39:19 +0000 | [diff] [blame] | 2085 | const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 2086 | ? getPointerRegClass() : RI.getRegClass(TOI.RegClass); |
| 2087 | std::vector<SDOperand> AddrOps; |
| 2088 | std::vector<SDOperand> BeforeOps; |
| 2089 | std::vector<SDOperand> AfterOps; |
| 2090 | unsigned NumOps = N->getNumOperands(); |
| 2091 | for (unsigned i = 0; i != NumOps-1; ++i) { |
| 2092 | SDOperand Op = N->getOperand(i); |
| 2093 | if (i >= Index && i < Index+4) |
| 2094 | AddrOps.push_back(Op); |
| 2095 | else if (i < Index) |
| 2096 | BeforeOps.push_back(Op); |
| 2097 | else if (i > Index) |
| 2098 | AfterOps.push_back(Op); |
| 2099 | } |
| 2100 | SDOperand Chain = N->getOperand(NumOps-1); |
| 2101 | AddrOps.push_back(Chain); |
| 2102 | |
| 2103 | // Emit the load instruction. |
| 2104 | SDNode *Load = 0; |
| 2105 | if (FoldedLoad) { |
| 2106 | MVT::ValueType VT = *RC->vt_begin(); |
| 2107 | Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.getStackAlignment()), VT, |
| 2108 | MVT::Other, &AddrOps[0], AddrOps.size()); |
| 2109 | NewNodes.push_back(Load); |
| 2110 | } |
| 2111 | |
| 2112 | // Emit the data processing instruction. |
| 2113 | std::vector<MVT::ValueType> VTs; |
| 2114 | const TargetRegisterClass *DstRC = 0; |
Chris Lattner | 349c495 | 2008-01-07 03:13:06 +0000 | [diff] [blame] | 2115 | if (TID.getNumDefs() > 0) { |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 2116 | const TargetOperandInfo &DstTOI = TID.OpInfo[0]; |
Chris Lattner | 8ca5c67 | 2008-01-07 02:39:19 +0000 | [diff] [blame] | 2117 | DstRC = DstTOI.isLookupPtrRegClass() |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 2118 | ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); |
| 2119 | VTs.push_back(*DstRC->vt_begin()); |
| 2120 | } |
| 2121 | for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { |
| 2122 | MVT::ValueType VT = N->getValueType(i); |
Chris Lattner | 349c495 | 2008-01-07 03:13:06 +0000 | [diff] [blame] | 2123 | if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 2124 | VTs.push_back(VT); |
| 2125 | } |
| 2126 | if (Load) |
| 2127 | BeforeOps.push_back(SDOperand(Load, 0)); |
| 2128 | std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); |
| 2129 | SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size()); |
| 2130 | NewNodes.push_back(NewNode); |
| 2131 | |
| 2132 | // Emit the store instruction. |
| 2133 | if (FoldedStore) { |
| 2134 | AddrOps.pop_back(); |
| 2135 | AddrOps.push_back(SDOperand(NewNode, 0)); |
| 2136 | AddrOps.push_back(Chain); |
| 2137 | SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, RI.getStackAlignment()), |
| 2138 | MVT::Other, &AddrOps[0], AddrOps.size()); |
| 2139 | NewNodes.push_back(Store); |
| 2140 | } |
| 2141 | |
| 2142 | return true; |
| 2143 | } |
| 2144 | |
| 2145 | unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, |
| 2146 | bool UnfoldLoad, bool UnfoldStore) const { |
| 2147 | DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = |
| 2148 | MemOp2RegOpTable.find((unsigned*)Opc); |
| 2149 | if (I == MemOp2RegOpTable.end()) |
| 2150 | return 0; |
| 2151 | bool FoldedLoad = I->second.second & (1 << 4); |
| 2152 | bool FoldedStore = I->second.second & (1 << 5); |
| 2153 | if (UnfoldLoad && !FoldedLoad) |
| 2154 | return 0; |
| 2155 | if (UnfoldStore && !FoldedStore) |
| 2156 | return 0; |
| 2157 | return I->second.first; |
| 2158 | } |
| 2159 | |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 2160 | bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { |
| 2161 | if (MBB.empty()) return false; |
| 2162 | |
| 2163 | switch (MBB.back().getOpcode()) { |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 2164 | case X86::TCRETURNri: |
| 2165 | case X86::TCRETURNdi: |
Evan Cheng | 126f17a | 2007-05-21 18:44:17 +0000 | [diff] [blame] | 2166 | case X86::RET: // Return. |
| 2167 | case X86::RETI: |
| 2168 | case X86::TAILJMPd: |
| 2169 | case X86::TAILJMPr: |
| 2170 | case X86::TAILJMPm: |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 2171 | case X86::JMP: // Uncond branch. |
| 2172 | case X86::JMP32r: // Indirect branch. |
Dan Gohman | a0a7c1d | 2007-09-17 15:19:08 +0000 | [diff] [blame] | 2173 | case X86::JMP64r: // Indirect branch (64-bit). |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 2174 | case X86::JMP32m: // Indirect branch through mem. |
Dan Gohman | a0a7c1d | 2007-09-17 15:19:08 +0000 | [diff] [blame] | 2175 | case X86::JMP64m: // Indirect branch through mem (64-bit). |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 2176 | return true; |
| 2177 | default: return false; |
| 2178 | } |
| 2179 | } |
| 2180 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 2181 | bool X86InstrInfo:: |
| 2182 | ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 2183 | assert(Cond.size() == 1 && "Invalid X86 branch condition!"); |
| 2184 | Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm())); |
| 2185 | return false; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 2186 | } |
| 2187 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2188 | const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { |
| 2189 | const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); |
| 2190 | if (Subtarget->is64Bit()) |
| 2191 | return &X86::GR64RegClass; |
| 2192 | else |
| 2193 | return &X86::GR32RegClass; |
| 2194 | } |