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gerrit-public.fairphone.software / platform / external / llvm / 29da5e6855c59cb34e757790b88c4b309db2920a / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: da5b6b86aac5e13c33939aeda6acb911f4f3f2b2 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
50 raw_ostream &vStream) const;
51
52 /// getEDInfo - See MCDisassembler.
53 EDInstInfo *getEDInfo() const;
54private:
55};
56
57/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
58class ThumbDisassembler : public MCDisassembler {
59public:
60 /// Constructor - Initializes the disassembler.
61 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]62 ThumbDisassembler(const MCSubtargetInfo &STI) :
63 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]64 }
65
66 ~ThumbDisassembler() {
67 }
68
69 /// getInstruction - See MCDisassembler.
70 DecodeStatus getInstruction(MCInst &instr,
71 uint64_t &size,
72 const MemoryObject &region,
73 uint64_t address,
74 raw_ostream &vStream) const;
75
76 /// getEDInfo - See MCDisassembler.
77 EDInstInfo *getEDInfo() const;
78private:
79 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]80 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]81 void UpdateThumbVFPPredicate(MCInst&) const;
82};
83}
84
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]85static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]86 switch (In) {
87 case MCDisassembler::Success:
88 // Out stays the same.
89 return true;
90 case MCDisassembler::SoftFail:
91 Out = In;
92 return true;
93 case MCDisassembler::Fail:
94 Out = In;
95 return false;
96 }
97 return false;
98}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]99
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]100
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]101// Forward declare these because the autogenerated code will reference them.
102// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]103static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]106 unsigned RegNo, uint64_t Address,
107 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]109 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]121 unsigned RegNo,
122 uint64_t Address,
123 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]124static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]125 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]126
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]139
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]145 unsigned Insn,
146 uint64_t Address,
147 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]148static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]149 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
156
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 unsigned Insn,
159 uint64_t Adddress,
160 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]161static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
273 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]274static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]290static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]298static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
299 uint64_t Address, const void *Decoder);
300static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
301 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]302static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
303 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]304
305#include "ARMGenDisassemblerTables.inc"
306#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]307#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]308
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]309static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
310 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]311}
312
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]313static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
314 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]315}
316
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]317EDInstInfo *ARMDisassembler::getEDInfo() const {
318 return instInfoARM;
319}
320
321EDInstInfo *ThumbDisassembler::getEDInfo() const {
322 return instInfoARM;
323}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]324
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]325DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]326 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]327 uint64_t Address,
328 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329 uint8_t bytes[4];
330
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]331 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
332 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
333
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]334 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]335 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
336 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]337 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]338 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339
340 // Encoded as a small-endian 32-bit word in the stream.
341 uint32_t insn = (bytes[3] << 24) |
342 (bytes[2] << 16) |
343 (bytes[1] << 8) |
344 (bytes[0] << 0);
345
346 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]347 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]348 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]349 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]350 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]351 }
352
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]353 // VFP and NEON instructions, similarly, are shared between ARM
354 // and Thumb modes.
355 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]356 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]357 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]358 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]359 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]360 }
361
362 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]363 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]364 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]365 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]366 // Add a fake predicate operand, because we share these instruction
367 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]368 if (!DecodePredicateOperand(MI, 0xE, Address, this))
369 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]370 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]371 }
372
373 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]374 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]375 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]377 // Add a fake predicate operand, because we share these instruction
378 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]379 if (!DecodePredicateOperand(MI, 0xE, Address, this))
380 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]381 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]382 }
383
384 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]385 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]386 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]387 Size = 4;
388 // Add a fake predicate operand, because we share these instruction
389 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]390 if (!DecodePredicateOperand(MI, 0xE, Address, this))
391 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]392 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]393 }
394
395 MI.clear();
396
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]397 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]398 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]399}
400
401namespace llvm {
402extern MCInstrDesc ARMInsts[];
403}
404
405// Thumb1 instructions don't have explicit S bits. Rather, they
406// implicitly set CPSR. Since it's not represented in the encoding, the
407// auto-generated decoder won't inject the CPSR operand. We need to fix
408// that as a post-pass.
409static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
410 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]411 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]412 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]413 for (unsigned i = 0; i < NumOps; ++i, ++I) {
414 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]416 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]417 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
418 return;
419 }
420 }
421
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]422 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]423}
424
425// Most Thumb instructions don't have explicit predicates in the
426// encoding, but rather get their predicates from IT context. We need
427// to fix up the predicate operands using this context information as a
428// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]429MCDisassembler::DecodeStatus
430ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]431 MCDisassembler::DecodeStatus S = Success;
432
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]433 // A few instructions actually have predicates encoded in them. Don't
434 // try to overwrite it if we're seeing one of those.
435 switch (MI.getOpcode()) {
436 case ARM::tBcc:
437 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]438 case ARM::tCBZ:
439 case ARM::tCBNZ:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]440 // Some instructions (mostly conditional branches) are not
441 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]442 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]443 S = SoftFail;
444 else
445 return Success;
446 break;
447 case ARM::tB:
448 case ARM::t2B:
449 // Some instructions (mostly unconditional branches) can
450 // only appears at the end of, or outside of, an IT.
451 if (ITBlock.size() > 1)
452 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]453 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]454 default:
455 break;
456 }
457
458 // If we're in an IT block, base the predicate on that. Otherwise,
459 // assume a predicate of AL.
460 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]461 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]462 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]463 if (CC == 0xF)
464 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]465 ITBlock.pop_back();
466 } else
467 CC = ARMCC::AL;
468
469 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]470 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]471 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]472 for (unsigned i = 0; i < NumOps; ++i, ++I) {
473 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]474 if (OpInfo[i].isPredicate()) {
475 I = MI.insert(I, MCOperand::CreateImm(CC));
476 ++I;
477 if (CC == ARMCC::AL)
478 MI.insert(I, MCOperand::CreateReg(0));
479 else
480 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]481 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]482 }
483 }
484
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]485 I = MI.insert(I, MCOperand::CreateImm(CC));
486 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]487 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]488 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]489 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]490 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]491
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]492 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]493}
494
495// Thumb VFP instructions are a special case. Because we share their
496// encodings between ARM and Thumb modes, and they are predicable in ARM
497// mode, the auto-generated decoder will give them an (incorrect)
498// predicate operand. We need to rewrite these operands based on the IT
499// context as a post-pass.
500void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
501 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]502 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]503 CC = ITBlock.back();
504 ITBlock.pop_back();
505 } else
506 CC = ARMCC::AL;
507
508 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
509 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]510 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
511 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]512 if (OpInfo[i].isPredicate() ) {
513 I->setImm(CC);
514 ++I;
515 if (CC == ARMCC::AL)
516 I->setReg(0);
517 else
518 I->setReg(ARM::CPSR);
519 return;
520 }
521 }
522}
523
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]524DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]525 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]526 uint64_t Address,
527 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]528 uint8_t bytes[4];
529
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]530 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
531 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
532
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]533 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]534 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
535 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]536 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]537 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]538
539 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]540 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]541 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]542 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]543 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]544 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]545 }
546
547 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]548 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]549 if (result) {
550 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]551 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]552 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]553 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]554 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]555 }
556
557 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]558 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]559 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]560 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]561 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]562
563 // If we find an IT instruction, we need to parse its condition
564 // code and mask operands so that we can apply them correctly
565 // to the subsequent instructions.
566 if (MI.getOpcode() == ARM::t2IT) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]567 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]568 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]569 unsigned Mask = MI.getOperand(1).getImm();
570 unsigned CondBit0 = Mask >> 4 & 1;
571 unsigned NumTZ = CountTrailingZeros_32(Mask);
572 assert(NumTZ <= 3 && "Invalid IT mask!");
573 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
574 bool T = ((Mask >> Pos) & 1) == CondBit0;
575 if (T)
576 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]577 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]578 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]580
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]581 ITBlock.push_back(firstcond);
582 }
583
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]584 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]585 }
586
587 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]588 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
589 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]590 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]591 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]592
593 uint32_t insn32 = (bytes[3] << 8) |
594 (bytes[2] << 0) |
595 (bytes[1] << 24) |
596 (bytes[0] << 16);
597 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]598 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]599 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]600 Size = 4;
601 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]602 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]603 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]604 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]605 }
606
607 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]608 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]609 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]610 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]611 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]612 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]613 }
614
615 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]616 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]617 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]618 Size = 4;
619 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]620 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]621 }
622
623 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]624 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]625 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]626 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]627 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]628 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]629 }
630
631 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
632 MI.clear();
633 uint32_t NEONLdStInsn = insn32;
634 NEONLdStInsn &= 0xF0FFFFFF;
635 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]636 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]637 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]638 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]639 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]640 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]641 }
642 }
643
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]644 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]645 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]646 uint32_t NEONDataInsn = insn32;
647 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
648 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
649 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]650 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]651 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]652 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]653 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]654 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]655 }
656 }
657
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]658 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]659 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]660}
661
662
663extern "C" void LLVMInitializeARMDisassembler() {
664 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
665 createARMDisassembler);
666 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
667 createThumbDisassembler);
668}
669
670static const unsigned GPRDecoderTable[] = {
671 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
672 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
673 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
674 ARM::R12, ARM::SP, ARM::LR, ARM::PC
675};
676
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]677static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]678 uint64_t Address, const void *Decoder) {
679 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]680 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]681
682 unsigned Register = GPRDecoderTable[RegNo];
683 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]684 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]685}
686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]687static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]688DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
689 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]690 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]691 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
692}
693
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]694static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]695 uint64_t Address, const void *Decoder) {
696 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]697 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]698 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
699}
700
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]701static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]702 uint64_t Address, const void *Decoder) {
703 unsigned Register = 0;
704 switch (RegNo) {
705 case 0:
706 Register = ARM::R0;
707 break;
708 case 1:
709 Register = ARM::R1;
710 break;
711 case 2:
712 Register = ARM::R2;
713 break;
714 case 3:
715 Register = ARM::R3;
716 break;
717 case 9:
718 Register = ARM::R9;
719 break;
720 case 12:
721 Register = ARM::R12;
722 break;
723 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]724 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]725 }
726
727 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]728 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]729}
730
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]731static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]732 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]733 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]734 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
735}
736
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]737static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]738 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
739 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
740 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
741 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
742 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
743 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
744 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
745 ARM::S28, ARM::S29, ARM::S30, ARM::S31
746};
747
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]748static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]749 uint64_t Address, const void *Decoder) {
750 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]751 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]752
753 unsigned Register = SPRDecoderTable[RegNo];
754 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]755 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]756}
757
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]758static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]759 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
760 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
761 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
762 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
763 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
764 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
765 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
766 ARM::D28, ARM::D29, ARM::D30, ARM::D31
767};
768
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]769static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]770 uint64_t Address, const void *Decoder) {
771 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]772 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]773
774 unsigned Register = DPRDecoderTable[RegNo];
775 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]776 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777}
778
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]779static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]780 uint64_t Address, const void *Decoder) {
781 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]782 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
784}
785
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]786static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]787DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
788 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]789 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]790 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
792}
793
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]794static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]795 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
796 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
797 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
798 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
799};
800
801
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]802static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]803 uint64_t Address, const void *Decoder) {
804 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]805 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]806 RegNo >>= 1;
807
808 unsigned Register = QPRDecoderTable[RegNo];
809 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]810 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]811}
812
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]813static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]814 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]815 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]816 // AL predicate is not allowed on Thumb1 branches.
817 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]818 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]819 Inst.addOperand(MCOperand::CreateImm(Val));
820 if (Val == ARMCC::AL) {
821 Inst.addOperand(MCOperand::CreateReg(0));
822 } else
823 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]824 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]825}
826
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]827static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]828 uint64_t Address, const void *Decoder) {
829 if (Val)
830 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
831 else
832 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]833 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]834}
835
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]836static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]837 uint64_t Address, const void *Decoder) {
838 uint32_t imm = Val & 0xFF;
839 uint32_t rot = (Val & 0xF00) >> 7;
840 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
841 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]842 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]843}
844
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]845static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]846 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]847 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]848
849 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
850 unsigned type = fieldFromInstruction32(Val, 5, 2);
851 unsigned imm = fieldFromInstruction32(Val, 7, 5);
852
853 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
855 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]856
857 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
858 switch (type) {
859 case 0:
860 Shift = ARM_AM::lsl;
861 break;
862 case 1:
863 Shift = ARM_AM::lsr;
864 break;
865 case 2:
866 Shift = ARM_AM::asr;
867 break;
868 case 3:
869 Shift = ARM_AM::ror;
870 break;
871 }
872
873 if (Shift == ARM_AM::ror && imm == 0)
874 Shift = ARM_AM::rrx;
875
876 unsigned Op = Shift | (imm << 3);
877 Inst.addOperand(MCOperand::CreateImm(Op));
878
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]879 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]880}
881
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]882static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]883 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]884 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]885
886 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
887 unsigned type = fieldFromInstruction32(Val, 5, 2);
888 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
889
890 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]891 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
892 return MCDisassembler::Fail;
893 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
894 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]895
896 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
897 switch (type) {
898 case 0:
899 Shift = ARM_AM::lsl;
900 break;
901 case 1:
902 Shift = ARM_AM::lsr;
903 break;
904 case 2:
905 Shift = ARM_AM::asr;
906 break;
907 case 3:
908 Shift = ARM_AM::ror;
909 break;
910 }
911
912 Inst.addOperand(MCOperand::CreateImm(Shift));
913
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]914 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]915}
916
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]917static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]918 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]919 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]920
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]921 bool writebackLoad = false;
922 unsigned writebackReg = 0;
923 switch (Inst.getOpcode()) {
924 default:
925 break;
926 case ARM::LDMIA_UPD:
927 case ARM::LDMDB_UPD:
928 case ARM::LDMIB_UPD:
929 case ARM::LDMDA_UPD:
930 case ARM::t2LDMIA_UPD:
931 case ARM::t2LDMDB_UPD:
932 writebackLoad = true;
933 writebackReg = Inst.getOperand(0).getReg();
934 break;
935 }
936
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]937 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]938 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]939 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]940 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]941 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
942 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]943 // Writeback not allowed if Rn is in the target list.
944 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
945 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]946 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]947 }
948
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]949 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]950}
951
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]952static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]953 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]954 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]955
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]956 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
957 unsigned regs = Val & 0xFF;
958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]959 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
960 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]961 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]962 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
963 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]964 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]965
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]966 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967}
968
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]969static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]970 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]971 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]972
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]973 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
974 unsigned regs = (Val & 0xFF) / 2;
975
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]976 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
977 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]978 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]979 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
980 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]981 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]982
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]983 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984}
985
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]986static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]987 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]988 // This operand encodes a mask of contiguous zeros between a specified MSB
989 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
990 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]991 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]992 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]993 unsigned msb = fieldFromInstruction32(Val, 5, 5);
994 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
995 uint32_t msb_mask = (1 << (msb+1)) - 1;
996 uint32_t lsb_mask = (1 << lsb) - 1;
997 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]998 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999}
1000
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1001static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1003 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1004
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1005 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1006 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1007 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1008 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1009 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1010 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1011
1012 switch (Inst.getOpcode()) {
1013 case ARM::LDC_OFFSET:
1014 case ARM::LDC_PRE:
1015 case ARM::LDC_POST:
1016 case ARM::LDC_OPTION:
1017 case ARM::LDCL_OFFSET:
1018 case ARM::LDCL_PRE:
1019 case ARM::LDCL_POST:
1020 case ARM::LDCL_OPTION:
1021 case ARM::STC_OFFSET:
1022 case ARM::STC_PRE:
1023 case ARM::STC_POST:
1024 case ARM::STC_OPTION:
1025 case ARM::STCL_OFFSET:
1026 case ARM::STCL_PRE:
1027 case ARM::STCL_POST:
1028 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1029 case ARM::t2LDC_OFFSET:
1030 case ARM::t2LDC_PRE:
1031 case ARM::t2LDC_POST:
1032 case ARM::t2LDC_OPTION:
1033 case ARM::t2LDCL_OFFSET:
1034 case ARM::t2LDCL_PRE:
1035 case ARM::t2LDCL_POST:
1036 case ARM::t2LDCL_OPTION:
1037 case ARM::t2STC_OFFSET:
1038 case ARM::t2STC_PRE:
1039 case ARM::t2STC_POST:
1040 case ARM::t2STC_OPTION:
1041 case ARM::t2STCL_OFFSET:
1042 case ARM::t2STCL_PRE:
1043 case ARM::t2STCL_POST:
1044 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1045 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1046 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1047 break;
1048 default:
1049 break;
1050 }
1051
1052 Inst.addOperand(MCOperand::CreateImm(coproc));
1053 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1055 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1056 switch (Inst.getOpcode()) {
1057 case ARM::LDC_OPTION:
1058 case ARM::LDCL_OPTION:
1059 case ARM::LDC2_OPTION:
1060 case ARM::LDC2L_OPTION:
1061 case ARM::STC_OPTION:
1062 case ARM::STCL_OPTION:
1063 case ARM::STC2_OPTION:
1064 case ARM::STC2L_OPTION:
1065 case ARM::LDCL_POST:
1066 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1067 case ARM::LDC2L_POST:
1068 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1069 case ARM::t2LDC_OPTION:
1070 case ARM::t2LDCL_OPTION:
1071 case ARM::t2STC_OPTION:
1072 case ARM::t2STCL_OPTION:
1073 case ARM::t2LDCL_POST:
1074 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1075 break;
1076 default:
1077 Inst.addOperand(MCOperand::CreateReg(0));
1078 break;
1079 }
1080
1081 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1082 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1083
1084 bool writeback = (P == 0) || (W == 1);
1085 unsigned idx_mode = 0;
1086 if (P && writeback)
1087 idx_mode = ARMII::IndexModePre;
1088 else if (!P && writeback)
1089 idx_mode = ARMII::IndexModePost;
1090
1091 switch (Inst.getOpcode()) {
1092 case ARM::LDCL_POST:
1093 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1094 case ARM::t2LDCL_POST:
1095 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1096 case ARM::LDC2L_POST:
1097 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1098 imm |= U << 8;
1099 case ARM::LDC_OPTION:
1100 case ARM::LDCL_OPTION:
1101 case ARM::LDC2_OPTION:
1102 case ARM::LDC2L_OPTION:
1103 case ARM::STC_OPTION:
1104 case ARM::STCL_OPTION:
1105 case ARM::STC2_OPTION:
1106 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1107 case ARM::t2LDC_OPTION:
1108 case ARM::t2LDCL_OPTION:
1109 case ARM::t2STC_OPTION:
1110 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1111 Inst.addOperand(MCOperand::CreateImm(imm));
1112 break;
1113 default:
1114 if (U)
1115 Inst.addOperand(MCOperand::CreateImm(
1116 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1117 else
1118 Inst.addOperand(MCOperand::CreateImm(
1119 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1120 break;
1121 }
1122
1123 switch (Inst.getOpcode()) {
1124 case ARM::LDC_OFFSET:
1125 case ARM::LDC_PRE:
1126 case ARM::LDC_POST:
1127 case ARM::LDC_OPTION:
1128 case ARM::LDCL_OFFSET:
1129 case ARM::LDCL_PRE:
1130 case ARM::LDCL_POST:
1131 case ARM::LDCL_OPTION:
1132 case ARM::STC_OFFSET:
1133 case ARM::STC_PRE:
1134 case ARM::STC_POST:
1135 case ARM::STC_OPTION:
1136 case ARM::STCL_OFFSET:
1137 case ARM::STCL_PRE:
1138 case ARM::STCL_POST:
1139 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1140 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1141 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1142 break;
1143 default:
1144 break;
1145 }
1146
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1147 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1148}
1149
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1150static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1151DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1152 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1153 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1154
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1155 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1156 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1157 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1158 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1159 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1160 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1161 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1162 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1163
1164 // On stores, the writeback operand precedes Rt.
1165 switch (Inst.getOpcode()) {
1166 case ARM::STR_POST_IMM:
1167 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1168 case ARM::STRB_POST_IMM:
1169 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1170 case ARM::STRT_POST_REG:
1171 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1172 case ARM::STRBT_POST_REG:
1173 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1174 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1175 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1176 break;
1177 default:
1178 break;
1179 }
1180
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1182 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1183
1184 // On loads, the writeback operand comes after Rt.
1185 switch (Inst.getOpcode()) {
1186 case ARM::LDR_POST_IMM:
1187 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1188 case ARM::LDRB_POST_IMM:
1189 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1190 case ARM::LDRBT_POST_REG:
1191 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1192 case ARM::LDRT_POST_REG:
1193 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1194 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1195 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1196 break;
1197 default:
1198 break;
1199 }
1200
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1202 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1203
1204 ARM_AM::AddrOpc Op = ARM_AM::add;
1205 if (!fieldFromInstruction32(Insn, 23, 1))
1206 Op = ARM_AM::sub;
1207
1208 bool writeback = (P == 0) || (W == 1);
1209 unsigned idx_mode = 0;
1210 if (P && writeback)
1211 idx_mode = ARMII::IndexModePre;
1212 else if (!P && writeback)
1213 idx_mode = ARMII::IndexModePost;
1214
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1215 if (writeback && (Rn == 15 || Rn == Rt))
1216 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1217
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1218 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1219 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1220 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1221 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1222 switch( fieldFromInstruction32(Insn, 5, 2)) {
1223 case 0:
1224 Opc = ARM_AM::lsl;
1225 break;
1226 case 1:
1227 Opc = ARM_AM::lsr;
1228 break;
1229 case 2:
1230 Opc = ARM_AM::asr;
1231 break;
1232 case 3:
1233 Opc = ARM_AM::ror;
1234 break;
1235 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1236 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1237 }
1238 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1239 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1240
1241 Inst.addOperand(MCOperand::CreateImm(imm));
1242 } else {
1243 Inst.addOperand(MCOperand::CreateReg(0));
1244 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1245 Inst.addOperand(MCOperand::CreateImm(tmp));
1246 }
1247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1248 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1249 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1250
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1251 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1252}
1253
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1254static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1256 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1257
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1258 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1259 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1260 unsigned type = fieldFromInstruction32(Val, 5, 2);
1261 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1262 unsigned U = fieldFromInstruction32(Val, 12, 1);
1263
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1264 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1265 switch (type) {
1266 case 0:
1267 ShOp = ARM_AM::lsl;
1268 break;
1269 case 1:
1270 ShOp = ARM_AM::lsr;
1271 break;
1272 case 2:
1273 ShOp = ARM_AM::asr;
1274 break;
1275 case 3:
1276 ShOp = ARM_AM::ror;
1277 break;
1278 }
1279
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1281 return MCDisassembler::Fail;
1282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1283 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1284 unsigned shift;
1285 if (U)
1286 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1287 else
1288 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1289 Inst.addOperand(MCOperand::CreateImm(shift));
1290
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1291 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1292}
1293
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1294static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1295DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1296 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1297 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1298
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1299 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1300 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1301 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1302 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1303 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1304 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1305 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1306 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1307 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1308
1309 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1310
1311 // For {LD,ST}RD, Rt must be even, else undefined.
1312 switch (Inst.getOpcode()) {
1313 case ARM::STRD:
1314 case ARM::STRD_PRE:
1315 case ARM::STRD_POST:
1316 case ARM::LDRD:
1317 case ARM::LDRD_PRE:
1318 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1319 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1320 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1321 default:
1322 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1323 }
1324
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1325 if (writeback) { // Writeback
1326 if (P)
1327 U |= ARMII::IndexModePre << 9;
1328 else
1329 U |= ARMII::IndexModePost << 9;
1330
1331 // On stores, the writeback operand precedes Rt.
1332 switch (Inst.getOpcode()) {
1333 case ARM::STRD:
1334 case ARM::STRD_PRE:
1335 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1336 case ARM::STRH:
1337 case ARM::STRH_PRE:
1338 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1340 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1341 break;
1342 default:
1343 break;
1344 }
1345 }
1346
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1348 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1349 switch (Inst.getOpcode()) {
1350 case ARM::STRD:
1351 case ARM::STRD_PRE:
1352 case ARM::STRD_POST:
1353 case ARM::LDRD:
1354 case ARM::LDRD_PRE:
1355 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1357 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1358 break;
1359 default:
1360 break;
1361 }
1362
1363 if (writeback) {
1364 // On loads, the writeback operand comes after Rt.
1365 switch (Inst.getOpcode()) {
1366 case ARM::LDRD:
1367 case ARM::LDRD_PRE:
1368 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1369 case ARM::LDRH:
1370 case ARM::LDRH_PRE:
1371 case ARM::LDRH_POST:
1372 case ARM::LDRSH:
1373 case ARM::LDRSH_PRE:
1374 case ARM::LDRSH_POST:
1375 case ARM::LDRSB:
1376 case ARM::LDRSB_PRE:
1377 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1378 case ARM::LDRHTr:
1379 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1381 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1382 break;
1383 default:
1384 break;
1385 }
1386 }
1387
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1389 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1390
1391 if (type) {
1392 Inst.addOperand(MCOperand::CreateReg(0));
1393 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1394 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1396 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1397 Inst.addOperand(MCOperand::CreateImm(U));
1398 }
1399
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1400 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1401 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1402
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1403 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1404}
1405
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1406static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1407 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1408 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1409
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1410 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1411 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1412
1413 switch (mode) {
1414 case 0:
1415 mode = ARM_AM::da;
1416 break;
1417 case 1:
1418 mode = ARM_AM::ia;
1419 break;
1420 case 2:
1421 mode = ARM_AM::db;
1422 break;
1423 case 3:
1424 mode = ARM_AM::ib;
1425 break;
1426 }
1427
1428 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1430 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1431
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1432 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1433}
1434
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1435static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1436 unsigned Insn,
1437 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1438 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1439
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1440 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1441 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1442 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1443
1444 if (pred == 0xF) {
1445 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1446 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1447 Inst.setOpcode(ARM::RFEDA);
1448 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1449 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1450 Inst.setOpcode(ARM::RFEDA_UPD);
1451 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1452 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1453 Inst.setOpcode(ARM::RFEDB);
1454 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1455 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1456 Inst.setOpcode(ARM::RFEDB_UPD);
1457 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1458 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1459 Inst.setOpcode(ARM::RFEIA);
1460 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1461 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1462 Inst.setOpcode(ARM::RFEIA_UPD);
1463 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1464 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1465 Inst.setOpcode(ARM::RFEIB);
1466 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1467 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1468 Inst.setOpcode(ARM::RFEIB_UPD);
1469 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1470 case ARM::STMDA:
1471 Inst.setOpcode(ARM::SRSDA);
1472 break;
1473 case ARM::STMDA_UPD:
1474 Inst.setOpcode(ARM::SRSDA_UPD);
1475 break;
1476 case ARM::STMDB:
1477 Inst.setOpcode(ARM::SRSDB);
1478 break;
1479 case ARM::STMDB_UPD:
1480 Inst.setOpcode(ARM::SRSDB_UPD);
1481 break;
1482 case ARM::STMIA:
1483 Inst.setOpcode(ARM::SRSIA);
1484 break;
1485 case ARM::STMIA_UPD:
1486 Inst.setOpcode(ARM::SRSIA_UPD);
1487 break;
1488 case ARM::STMIB:
1489 Inst.setOpcode(ARM::SRSIB);
1490 break;
1491 case ARM::STMIB_UPD:
1492 Inst.setOpcode(ARM::SRSIB_UPD);
1493 break;
1494 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1495 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1496 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1497
1498 // For stores (which become SRS's, the only operand is the mode.
1499 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1500 Inst.addOperand(
1501 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1502 return S;
1503 }
1504
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1505 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1506 }
1507
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1509 return MCDisassembler::Fail;
1510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1511 return MCDisassembler::Fail; // Tied
1512 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1513 return MCDisassembler::Fail;
1514 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1515 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1516
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1517 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1518}
1519
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1520static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1521 uint64_t Address, const void *Decoder) {
1522 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1523 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1524 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1525 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1526
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1527 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1528
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1529 // imod == '01' --> UNPREDICTABLE
1530 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1531 // return failure here. The '01' imod value is unprintable, so there's
1532 // nothing useful we could do even if we returned UNPREDICTABLE.
1533
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1534 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1535
1536 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1537 Inst.setOpcode(ARM::CPS3p);
1538 Inst.addOperand(MCOperand::CreateImm(imod));
1539 Inst.addOperand(MCOperand::CreateImm(iflags));
1540 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1541 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1542 Inst.setOpcode(ARM::CPS2p);
1543 Inst.addOperand(MCOperand::CreateImm(imod));
1544 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1545 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1546 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1547 Inst.setOpcode(ARM::CPS1p);
1548 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1549 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1550 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1551 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1552 Inst.setOpcode(ARM::CPS1p);
1553 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1554 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1555 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1556
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1557 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1558}
1559
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1560static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1561 uint64_t Address, const void *Decoder) {
1562 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1563 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1564 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1565 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1566
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1567 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1568
1569 // imod == '01' --> UNPREDICTABLE
1570 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1571 // return failure here. The '01' imod value is unprintable, so there's
1572 // nothing useful we could do even if we returned UNPREDICTABLE.
1573
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1574 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1575
1576 if (imod && M) {
1577 Inst.setOpcode(ARM::t2CPS3p);
1578 Inst.addOperand(MCOperand::CreateImm(imod));
1579 Inst.addOperand(MCOperand::CreateImm(iflags));
1580 Inst.addOperand(MCOperand::CreateImm(mode));
1581 } else if (imod && !M) {
1582 Inst.setOpcode(ARM::t2CPS2p);
1583 Inst.addOperand(MCOperand::CreateImm(imod));
1584 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1585 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1586 } else if (!imod && M) {
1587 Inst.setOpcode(ARM::t2CPS1p);
1588 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1589 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1590 } else {
1591 // imod == '00' && M == '0' --> UNPREDICTABLE
1592 Inst.setOpcode(ARM::t2CPS1p);
1593 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1594 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1595 }
1596
1597 return S;
1598}
1599
1600
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1601static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1602 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1603 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1604
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1605 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1606 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1607 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1608 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1609 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1610
1611 if (pred == 0xF)
1612 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1613
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1614 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1615 return MCDisassembler::Fail;
1616 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1617 return MCDisassembler::Fail;
1618 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1619 return MCDisassembler::Fail;
1620 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1621 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1622
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1623 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1624 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1625
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1626 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1627}
1628
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1629static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1630 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1631 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1632
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1633 unsigned add = fieldFromInstruction32(Val, 12, 1);
1634 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1635 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1636
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1637 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1638 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1639
1640 if (!add) imm *= -1;
1641 if (imm == 0 && !add) imm = INT32_MIN;
1642 Inst.addOperand(MCOperand::CreateImm(imm));
1643
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1644 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1645}
1646
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1647static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1648 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1649 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1650
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1651 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1652 unsigned U = fieldFromInstruction32(Val, 8, 1);
1653 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1654
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1656 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1657
1658 if (U)
1659 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1660 else
1661 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1662
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1663 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1664}
1665
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1666static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1667 uint64_t Address, const void *Decoder) {
1668 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1669}
1670
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1671static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1672DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1673 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1674 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1675
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1676 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1677 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1678
1679 if (pred == 0xF) {
1680 Inst.setOpcode(ARM::BLXi);
1681 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1682 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1683 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1684 }
1685
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1686 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1687 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1688 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1689
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1690 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1691}
1692
1693
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1694static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1695 uint64_t Address, const void *Decoder) {
1696 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1697 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1698}
1699
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1700static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1701 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1702 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1703
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1704 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1705 unsigned align = fieldFromInstruction32(Val, 4, 2);
1706
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1708 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1709 if (!align)
1710 Inst.addOperand(MCOperand::CreateImm(0));
1711 else
1712 Inst.addOperand(MCOperand::CreateImm(4 << align));
1713
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1714 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1715}
1716
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1717static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1718 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1719 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1720
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1721 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1722 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1723 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1725 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1726 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1727
1728 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1730 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1731
1732 // Second output register
1733 switch (Inst.getOpcode()) {
1734 case ARM::VLD1q8:
1735 case ARM::VLD1q16:
1736 case ARM::VLD1q32:
1737 case ARM::VLD1q64:
1738 case ARM::VLD1q8_UPD:
1739 case ARM::VLD1q16_UPD:
1740 case ARM::VLD1q32_UPD:
1741 case ARM::VLD1q64_UPD:
1742 case ARM::VLD1d8T:
1743 case ARM::VLD1d16T:
1744 case ARM::VLD1d32T:
1745 case ARM::VLD1d64T:
1746 case ARM::VLD1d8T_UPD:
1747 case ARM::VLD1d16T_UPD:
1748 case ARM::VLD1d32T_UPD:
1749 case ARM::VLD1d64T_UPD:
1750 case ARM::VLD1d8Q:
1751 case ARM::VLD1d16Q:
1752 case ARM::VLD1d32Q:
1753 case ARM::VLD1d64Q:
1754 case ARM::VLD1d8Q_UPD:
1755 case ARM::VLD1d16Q_UPD:
1756 case ARM::VLD1d32Q_UPD:
1757 case ARM::VLD1d64Q_UPD:
1758 case ARM::VLD2d8:
1759 case ARM::VLD2d16:
1760 case ARM::VLD2d32:
1761 case ARM::VLD2d8_UPD:
1762 case ARM::VLD2d16_UPD:
1763 case ARM::VLD2d32_UPD:
1764 case ARM::VLD2q8:
1765 case ARM::VLD2q16:
1766 case ARM::VLD2q32:
1767 case ARM::VLD2q8_UPD:
1768 case ARM::VLD2q16_UPD:
1769 case ARM::VLD2q32_UPD:
1770 case ARM::VLD3d8:
1771 case ARM::VLD3d16:
1772 case ARM::VLD3d32:
1773 case ARM::VLD3d8_UPD:
1774 case ARM::VLD3d16_UPD:
1775 case ARM::VLD3d32_UPD:
1776 case ARM::VLD4d8:
1777 case ARM::VLD4d16:
1778 case ARM::VLD4d32:
1779 case ARM::VLD4d8_UPD:
1780 case ARM::VLD4d16_UPD:
1781 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1782 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1783 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1784 break;
1785 case ARM::VLD2b8:
1786 case ARM::VLD2b16:
1787 case ARM::VLD2b32:
1788 case ARM::VLD2b8_UPD:
1789 case ARM::VLD2b16_UPD:
1790 case ARM::VLD2b32_UPD:
1791 case ARM::VLD3q8:
1792 case ARM::VLD3q16:
1793 case ARM::VLD3q32:
1794 case ARM::VLD3q8_UPD:
1795 case ARM::VLD3q16_UPD:
1796 case ARM::VLD3q32_UPD:
1797 case ARM::VLD4q8:
1798 case ARM::VLD4q16:
1799 case ARM::VLD4q32:
1800 case ARM::VLD4q8_UPD:
1801 case ARM::VLD4q16_UPD:
1802 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1804 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1805 default:
1806 break;
1807 }
1808
1809 // Third output register
1810 switch(Inst.getOpcode()) {
1811 case ARM::VLD1d8T:
1812 case ARM::VLD1d16T:
1813 case ARM::VLD1d32T:
1814 case ARM::VLD1d64T:
1815 case ARM::VLD1d8T_UPD:
1816 case ARM::VLD1d16T_UPD:
1817 case ARM::VLD1d32T_UPD:
1818 case ARM::VLD1d64T_UPD:
1819 case ARM::VLD1d8Q:
1820 case ARM::VLD1d16Q:
1821 case ARM::VLD1d32Q:
1822 case ARM::VLD1d64Q:
1823 case ARM::VLD1d8Q_UPD:
1824 case ARM::VLD1d16Q_UPD:
1825 case ARM::VLD1d32Q_UPD:
1826 case ARM::VLD1d64Q_UPD:
1827 case ARM::VLD2q8:
1828 case ARM::VLD2q16:
1829 case ARM::VLD2q32:
1830 case ARM::VLD2q8_UPD:
1831 case ARM::VLD2q16_UPD:
1832 case ARM::VLD2q32_UPD:
1833 case ARM::VLD3d8:
1834 case ARM::VLD3d16:
1835 case ARM::VLD3d32:
1836 case ARM::VLD3d8_UPD:
1837 case ARM::VLD3d16_UPD:
1838 case ARM::VLD3d32_UPD:
1839 case ARM::VLD4d8:
1840 case ARM::VLD4d16:
1841 case ARM::VLD4d32:
1842 case ARM::VLD4d8_UPD:
1843 case ARM::VLD4d16_UPD:
1844 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1845 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1846 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1847 break;
1848 case ARM::VLD3q8:
1849 case ARM::VLD3q16:
1850 case ARM::VLD3q32:
1851 case ARM::VLD3q8_UPD:
1852 case ARM::VLD3q16_UPD:
1853 case ARM::VLD3q32_UPD:
1854 case ARM::VLD4q8:
1855 case ARM::VLD4q16:
1856 case ARM::VLD4q32:
1857 case ARM::VLD4q8_UPD:
1858 case ARM::VLD4q16_UPD:
1859 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1860 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1861 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1862 break;
1863 default:
1864 break;
1865 }
1866
1867 // Fourth output register
1868 switch (Inst.getOpcode()) {
1869 case ARM::VLD1d8Q:
1870 case ARM::VLD1d16Q:
1871 case ARM::VLD1d32Q:
1872 case ARM::VLD1d64Q:
1873 case ARM::VLD1d8Q_UPD:
1874 case ARM::VLD1d16Q_UPD:
1875 case ARM::VLD1d32Q_UPD:
1876 case ARM::VLD1d64Q_UPD:
1877 case ARM::VLD2q8:
1878 case ARM::VLD2q16:
1879 case ARM::VLD2q32:
1880 case ARM::VLD2q8_UPD:
1881 case ARM::VLD2q16_UPD:
1882 case ARM::VLD2q32_UPD:
1883 case ARM::VLD4d8:
1884 case ARM::VLD4d16:
1885 case ARM::VLD4d32:
1886 case ARM::VLD4d8_UPD:
1887 case ARM::VLD4d16_UPD:
1888 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1889 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1890 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1891 break;
1892 case ARM::VLD4q8:
1893 case ARM::VLD4q16:
1894 case ARM::VLD4q32:
1895 case ARM::VLD4q8_UPD:
1896 case ARM::VLD4q16_UPD:
1897 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1898 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1899 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1900 break;
1901 default:
1902 break;
1903 }
1904
1905 // Writeback operand
1906 switch (Inst.getOpcode()) {
1907 case ARM::VLD1d8_UPD:
1908 case ARM::VLD1d16_UPD:
1909 case ARM::VLD1d32_UPD:
1910 case ARM::VLD1d64_UPD:
1911 case ARM::VLD1q8_UPD:
1912 case ARM::VLD1q16_UPD:
1913 case ARM::VLD1q32_UPD:
1914 case ARM::VLD1q64_UPD:
1915 case ARM::VLD1d8T_UPD:
1916 case ARM::VLD1d16T_UPD:
1917 case ARM::VLD1d32T_UPD:
1918 case ARM::VLD1d64T_UPD:
1919 case ARM::VLD1d8Q_UPD:
1920 case ARM::VLD1d16Q_UPD:
1921 case ARM::VLD1d32Q_UPD:
1922 case ARM::VLD1d64Q_UPD:
1923 case ARM::VLD2d8_UPD:
1924 case ARM::VLD2d16_UPD:
1925 case ARM::VLD2d32_UPD:
1926 case ARM::VLD2q8_UPD:
1927 case ARM::VLD2q16_UPD:
1928 case ARM::VLD2q32_UPD:
1929 case ARM::VLD2b8_UPD:
1930 case ARM::VLD2b16_UPD:
1931 case ARM::VLD2b32_UPD:
1932 case ARM::VLD3d8_UPD:
1933 case ARM::VLD3d16_UPD:
1934 case ARM::VLD3d32_UPD:
1935 case ARM::VLD3q8_UPD:
1936 case ARM::VLD3q16_UPD:
1937 case ARM::VLD3q32_UPD:
1938 case ARM::VLD4d8_UPD:
1939 case ARM::VLD4d16_UPD:
1940 case ARM::VLD4d32_UPD:
1941 case ARM::VLD4q8_UPD:
1942 case ARM::VLD4q16_UPD:
1943 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1944 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1945 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1946 break;
1947 default:
1948 break;
1949 }
1950
1951 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1952 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1953 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1954
1955 // AddrMode6 Offset (register)
1956 if (Rm == 0xD)
1957 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1958 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1960 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1961 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1962
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1963 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1964}
1965
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1966static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1967 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1968 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1969
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1970 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1971 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1972 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1973 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1974 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1975 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1976
1977 // Writeback Operand
1978 switch (Inst.getOpcode()) {
1979 case ARM::VST1d8_UPD:
1980 case ARM::VST1d16_UPD:
1981 case ARM::VST1d32_UPD:
1982 case ARM::VST1d64_UPD:
1983 case ARM::VST1q8_UPD:
1984 case ARM::VST1q16_UPD:
1985 case ARM::VST1q32_UPD:
1986 case ARM::VST1q64_UPD:
1987 case ARM::VST1d8T_UPD:
1988 case ARM::VST1d16T_UPD:
1989 case ARM::VST1d32T_UPD:
1990 case ARM::VST1d64T_UPD:
1991 case ARM::VST1d8Q_UPD:
1992 case ARM::VST1d16Q_UPD:
1993 case ARM::VST1d32Q_UPD:
1994 case ARM::VST1d64Q_UPD:
1995 case ARM::VST2d8_UPD:
1996 case ARM::VST2d16_UPD:
1997 case ARM::VST2d32_UPD:
1998 case ARM::VST2q8_UPD:
1999 case ARM::VST2q16_UPD:
2000 case ARM::VST2q32_UPD:
2001 case ARM::VST2b8_UPD:
2002 case ARM::VST2b16_UPD:
2003 case ARM::VST2b32_UPD:
2004 case ARM::VST3d8_UPD:
2005 case ARM::VST3d16_UPD:
2006 case ARM::VST3d32_UPD:
2007 case ARM::VST3q8_UPD:
2008 case ARM::VST3q16_UPD:
2009 case ARM::VST3q32_UPD:
2010 case ARM::VST4d8_UPD:
2011 case ARM::VST4d16_UPD:
2012 case ARM::VST4d32_UPD:
2013 case ARM::VST4q8_UPD:
2014 case ARM::VST4q16_UPD:
2015 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2016 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2017 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2018 break;
2019 default:
2020 break;
2021 }
2022
2023 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2024 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2025 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2026
2027 // AddrMode6 Offset (register)
2028 if (Rm == 0xD)
2029 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2030 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2032 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2033 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2034
2035 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2036 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2037 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2038
2039 // Second input register
2040 switch (Inst.getOpcode()) {
2041 case ARM::VST1q8:
2042 case ARM::VST1q16:
2043 case ARM::VST1q32:
2044 case ARM::VST1q64:
2045 case ARM::VST1q8_UPD:
2046 case ARM::VST1q16_UPD:
2047 case ARM::VST1q32_UPD:
2048 case ARM::VST1q64_UPD:
2049 case ARM::VST1d8T:
2050 case ARM::VST1d16T:
2051 case ARM::VST1d32T:
2052 case ARM::VST1d64T:
2053 case ARM::VST1d8T_UPD:
2054 case ARM::VST1d16T_UPD:
2055 case ARM::VST1d32T_UPD:
2056 case ARM::VST1d64T_UPD:
2057 case ARM::VST1d8Q:
2058 case ARM::VST1d16Q:
2059 case ARM::VST1d32Q:
2060 case ARM::VST1d64Q:
2061 case ARM::VST1d8Q_UPD:
2062 case ARM::VST1d16Q_UPD:
2063 case ARM::VST1d32Q_UPD:
2064 case ARM::VST1d64Q_UPD:
2065 case ARM::VST2d8:
2066 case ARM::VST2d16:
2067 case ARM::VST2d32:
2068 case ARM::VST2d8_UPD:
2069 case ARM::VST2d16_UPD:
2070 case ARM::VST2d32_UPD:
2071 case ARM::VST2q8:
2072 case ARM::VST2q16:
2073 case ARM::VST2q32:
2074 case ARM::VST2q8_UPD:
2075 case ARM::VST2q16_UPD:
2076 case ARM::VST2q32_UPD:
2077 case ARM::VST3d8:
2078 case ARM::VST3d16:
2079 case ARM::VST3d32:
2080 case ARM::VST3d8_UPD:
2081 case ARM::VST3d16_UPD:
2082 case ARM::VST3d32_UPD:
2083 case ARM::VST4d8:
2084 case ARM::VST4d16:
2085 case ARM::VST4d32:
2086 case ARM::VST4d8_UPD:
2087 case ARM::VST4d16_UPD:
2088 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2089 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2090 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2091 break;
2092 case ARM::VST2b8:
2093 case ARM::VST2b16:
2094 case ARM::VST2b32:
2095 case ARM::VST2b8_UPD:
2096 case ARM::VST2b16_UPD:
2097 case ARM::VST2b32_UPD:
2098 case ARM::VST3q8:
2099 case ARM::VST3q16:
2100 case ARM::VST3q32:
2101 case ARM::VST3q8_UPD:
2102 case ARM::VST3q16_UPD:
2103 case ARM::VST3q32_UPD:
2104 case ARM::VST4q8:
2105 case ARM::VST4q16:
2106 case ARM::VST4q32:
2107 case ARM::VST4q8_UPD:
2108 case ARM::VST4q16_UPD:
2109 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2110 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2111 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2112 break;
2113 default:
2114 break;
2115 }
2116
2117 // Third input register
2118 switch (Inst.getOpcode()) {
2119 case ARM::VST1d8T:
2120 case ARM::VST1d16T:
2121 case ARM::VST1d32T:
2122 case ARM::VST1d64T:
2123 case ARM::VST1d8T_UPD:
2124 case ARM::VST1d16T_UPD:
2125 case ARM::VST1d32T_UPD:
2126 case ARM::VST1d64T_UPD:
2127 case ARM::VST1d8Q:
2128 case ARM::VST1d16Q:
2129 case ARM::VST1d32Q:
2130 case ARM::VST1d64Q:
2131 case ARM::VST1d8Q_UPD:
2132 case ARM::VST1d16Q_UPD:
2133 case ARM::VST1d32Q_UPD:
2134 case ARM::VST1d64Q_UPD:
2135 case ARM::VST2q8:
2136 case ARM::VST2q16:
2137 case ARM::VST2q32:
2138 case ARM::VST2q8_UPD:
2139 case ARM::VST2q16_UPD:
2140 case ARM::VST2q32_UPD:
2141 case ARM::VST3d8:
2142 case ARM::VST3d16:
2143 case ARM::VST3d32:
2144 case ARM::VST3d8_UPD:
2145 case ARM::VST3d16_UPD:
2146 case ARM::VST3d32_UPD:
2147 case ARM::VST4d8:
2148 case ARM::VST4d16:
2149 case ARM::VST4d32:
2150 case ARM::VST4d8_UPD:
2151 case ARM::VST4d16_UPD:
2152 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2153 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2154 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2155 break;
2156 case ARM::VST3q8:
2157 case ARM::VST3q16:
2158 case ARM::VST3q32:
2159 case ARM::VST3q8_UPD:
2160 case ARM::VST3q16_UPD:
2161 case ARM::VST3q32_UPD:
2162 case ARM::VST4q8:
2163 case ARM::VST4q16:
2164 case ARM::VST4q32:
2165 case ARM::VST4q8_UPD:
2166 case ARM::VST4q16_UPD:
2167 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2168 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2169 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2170 break;
2171 default:
2172 break;
2173 }
2174
2175 // Fourth input register
2176 switch (Inst.getOpcode()) {
2177 case ARM::VST1d8Q:
2178 case ARM::VST1d16Q:
2179 case ARM::VST1d32Q:
2180 case ARM::VST1d64Q:
2181 case ARM::VST1d8Q_UPD:
2182 case ARM::VST1d16Q_UPD:
2183 case ARM::VST1d32Q_UPD:
2184 case ARM::VST1d64Q_UPD:
2185 case ARM::VST2q8:
2186 case ARM::VST2q16:
2187 case ARM::VST2q32:
2188 case ARM::VST2q8_UPD:
2189 case ARM::VST2q16_UPD:
2190 case ARM::VST2q32_UPD:
2191 case ARM::VST4d8:
2192 case ARM::VST4d16:
2193 case ARM::VST4d32:
2194 case ARM::VST4d8_UPD:
2195 case ARM::VST4d16_UPD:
2196 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2197 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2198 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2199 break;
2200 case ARM::VST4q8:
2201 case ARM::VST4q16:
2202 case ARM::VST4q32:
2203 case ARM::VST4q8_UPD:
2204 case ARM::VST4q16_UPD:
2205 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2207 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2208 break;
2209 default:
2210 break;
2211 }
2212
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2213 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2214}
2215
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2216static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2217 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2218 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2219
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2220 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2221 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2222 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2223 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2224 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2225 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2226 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2227
2228 align *= (1 << size);
2229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2230 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2231 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2232 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2233 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2234 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2235 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2236 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2238 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2239 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2240
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2242 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2243 Inst.addOperand(MCOperand::CreateImm(align));
2244
2245 if (Rm == 0xD)
2246 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2247 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2249 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2250 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2251
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2252 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2253}
2254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2255static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2256 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2257 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2258
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2259 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2260 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2261 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2262 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2263 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2264 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2265 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2266 align *= 2*size;
2267
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2268 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2269 return MCDisassembler::Fail;
2270 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2271 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2272 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2274 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2275 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2276
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2278 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2279 Inst.addOperand(MCOperand::CreateImm(align));
2280
2281 if (Rm == 0xD)
2282 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2283 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2285 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2286 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2287
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2288 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2289}
2290
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2291static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2292 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2293 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2294
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2295 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2296 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2297 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2298 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2299 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2300
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2301 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2302 return MCDisassembler::Fail;
2303 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2304 return MCDisassembler::Fail;
2305 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2306 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2307 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2309 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2310 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2311
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2313 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2314 Inst.addOperand(MCOperand::CreateImm(0));
2315
2316 if (Rm == 0xD)
2317 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2318 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2320 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2321 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2322
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2323 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2324}
2325
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2326static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2327 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2328 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2329
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2330 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2331 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2332 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2333 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2334 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2335 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2336 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2337
2338 if (size == 0x3) {
2339 size = 4;
2340 align = 16;
2341 } else {
2342 if (size == 2) {
2343 size = 1 << size;
2344 align *= 8;
2345 } else {
2346 size = 1 << size;
2347 align *= 4*size;
2348 }
2349 }
2350
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2351 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2352 return MCDisassembler::Fail;
2353 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2354 return MCDisassembler::Fail;
2355 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2356 return MCDisassembler::Fail;
2357 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2358 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2359 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2361 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2362 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2363
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2365 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2366 Inst.addOperand(MCOperand::CreateImm(align));
2367
2368 if (Rm == 0xD)
2369 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2370 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2372 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2373 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2374
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2375 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2376}
2377
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2378static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2379DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2380 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2381 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2382
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2383 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2384 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2385 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2386 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2387 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2388 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2389 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2390 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2391
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2392 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2393 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2394 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2395 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2396 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2397 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2398 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2399
2400 Inst.addOperand(MCOperand::CreateImm(imm));
2401
2402 switch (Inst.getOpcode()) {
2403 case ARM::VORRiv4i16:
2404 case ARM::VORRiv2i32:
2405 case ARM::VBICiv4i16:
2406 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2407 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2408 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2409 break;
2410 case ARM::VORRiv8i16:
2411 case ARM::VORRiv4i32:
2412 case ARM::VBICiv8i16:
2413 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2414 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2415 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2416 break;
2417 default:
2418 break;
2419 }
2420
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2421 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2422}
2423
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2424static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2425 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2426 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2427
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2428 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2429 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2430 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2431 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2432 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2433
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2434 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2435 return MCDisassembler::Fail;
2436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2437 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2438 Inst.addOperand(MCOperand::CreateImm(8 << size));
2439
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2440 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2441}
2442
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2443static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2444 uint64_t Address, const void *Decoder) {
2445 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2446 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2447}
2448
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2449static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2450 uint64_t Address, const void *Decoder) {
2451 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2452 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2453}
2454
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2455static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2456 uint64_t Address, const void *Decoder) {
2457 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2458 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2459}
2460
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2461static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2462 uint64_t Address, const void *Decoder) {
2463 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2464 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2465}
2466
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2467static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2468 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2469 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2470
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2471 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2472 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2473 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2474 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2475 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2476 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2477 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2478 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2479
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2480 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2481 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2482 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2484 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2485 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2486
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2487 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2488 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2489 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2490 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2491
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2492 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2493 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2494
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2495 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2496}
2497
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2498static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2499 uint64_t Address, const void *Decoder) {
2500 // The immediate needs to be a fully instantiated float. However, the
2501 // auto-generated decoder is only able to fill in some of the bits
2502 // necessary. For instance, the 'b' bit is replicated multiple times,
2503 // and is even present in inverted form in one bit. We do a little
2504 // binary parsing here to fill in those missing bits, and then
2505 // reinterpret it all as a float.
2506 union {
2507 uint32_t integer;
2508 float fp;
2509 } fp_conv;
2510
2511 fp_conv.integer = Val;
2512 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2513 fp_conv.integer |= b << 26;
2514 fp_conv.integer |= b << 27;
2515 fp_conv.integer |= b << 28;
2516 fp_conv.integer |= b << 29;
2517 fp_conv.integer |= (~b & 0x1) << 30;
2518
2519 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2520 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521}
2522
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2523static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2525 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2526
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2527 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2528 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2530 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2531 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2532
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2533 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2534 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2535 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2536 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2537 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2538 case ARM::tADDrSPi:
2539 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2540 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2541 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2542
2543 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2544 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2545}
2546
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2547static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2548 uint64_t Address, const void *Decoder) {
2549 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2550 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2551}
2552
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2553static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2554 uint64_t Address, const void *Decoder) {
2555 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2556 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2557}
2558
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2559static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2560 uint64_t Address, const void *Decoder) {
2561 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2562 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2563}
2564
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2565static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2566 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2567 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2568
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2569 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2570 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2571
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2572 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2573 return MCDisassembler::Fail;
2574 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2575 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2576
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2577 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2578}
2579
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2580static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2581 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2582 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2583
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2584 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2585 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2587 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2588 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2589 Inst.addOperand(MCOperand::CreateImm(imm));
2590
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2591 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2592}
2593
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2594static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2595 uint64_t Address, const void *Decoder) {
2596 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2597
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2598 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2599}
2600
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2601static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2602 uint64_t Address, const void *Decoder) {
2603 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2604 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2605
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2606 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2607}
2608
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2609static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2610 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2611 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2612
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2613 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2614 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2615 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2616
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2618 return MCDisassembler::Fail;
2619 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2620 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2621 Inst.addOperand(MCOperand::CreateImm(imm));
2622
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2623 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2624}
2625
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2626static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2627 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2628 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2629
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2630 switch (Inst.getOpcode()) {
2631 case ARM::t2PLDs:
2632 case ARM::t2PLDWs:
2633 case ARM::t2PLIs:
2634 break;
2635 default: {
2636 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2637 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2638 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2639 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2640 }
2641
2642 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2643 if (Rn == 0xF) {
2644 switch (Inst.getOpcode()) {
2645 case ARM::t2LDRBs:
2646 Inst.setOpcode(ARM::t2LDRBpci);
2647 break;
2648 case ARM::t2LDRHs:
2649 Inst.setOpcode(ARM::t2LDRHpci);
2650 break;
2651 case ARM::t2LDRSHs:
2652 Inst.setOpcode(ARM::t2LDRSHpci);
2653 break;
2654 case ARM::t2LDRSBs:
2655 Inst.setOpcode(ARM::t2LDRSBpci);
2656 break;
2657 case ARM::t2PLDs:
2658 Inst.setOpcode(ARM::t2PLDi12);
2659 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2660 break;
2661 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2662 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2663 }
2664
2665 int imm = fieldFromInstruction32(Insn, 0, 12);
2666 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2667 Inst.addOperand(MCOperand::CreateImm(imm));
2668
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2669 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670 }
2671
2672 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2673 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2674 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2675 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2676 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2677
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2678 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2679}
2680
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2681static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2682 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2683 int imm = Val & 0xFF;
2684 if (!(Val & 0x100)) imm *= -1;
2685 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2686
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2687 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2688}
2689
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2690static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2691 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2692 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2693
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2695 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2696
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2698 return MCDisassembler::Fail;
2699 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2700 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2701
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2702 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2703}
2704
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2705static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2706 uint64_t Address, const void *Decoder) {
2707 DecodeStatus S = MCDisassembler::Success;
2708
2709 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2710 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2711
2712 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2713 return MCDisassembler::Fail;
2714
2715 Inst.addOperand(MCOperand::CreateImm(imm));
2716
2717 return S;
2718}
2719
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2720static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2721 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2722 int imm = Val & 0xFF;
2723 if (!(Val & 0x100)) imm *= -1;
2724 Inst.addOperand(MCOperand::CreateImm(imm));
2725
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2726 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2727}
2728
2729
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2730static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2731 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2732 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2733
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2734 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2735 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2736
2737 // Some instructions always use an additive offset.
2738 switch (Inst.getOpcode()) {
2739 case ARM::t2LDRT:
2740 case ARM::t2LDRBT:
2741 case ARM::t2LDRHT:
2742 case ARM::t2LDRSBT:
2743 case ARM::t2LDRSHT:
2744 imm |= 0x100;
2745 break;
2746 default:
2747 break;
2748 }
2749
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2751 return MCDisassembler::Fail;
2752 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2753 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2754
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2755 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2756}
2757
2758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2759static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2760 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2761 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2762
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2763 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2764 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2765
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2767 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2768 Inst.addOperand(MCOperand::CreateImm(imm));
2769
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2770 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2771}
2772
2773
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2774static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2775 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2776 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2777
2778 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2779 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2780 Inst.addOperand(MCOperand::CreateImm(imm));
2781
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2782 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2783}
2784
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2785static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2786 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2787 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2788
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2789 if (Inst.getOpcode() == ARM::tADDrSP) {
2790 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2791 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2792
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2794 return MCDisassembler::Fail;
2795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2796 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2797 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2798 } else if (Inst.getOpcode() == ARM::tADDspr) {
2799 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2800
2801 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2802 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2804 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2805 }
2806
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2807 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808}
2809
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2810static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2811 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2813 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2814
2815 Inst.addOperand(MCOperand::CreateImm(imod));
2816 Inst.addOperand(MCOperand::CreateImm(flags));
2817
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2818 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2819}
2820
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2821static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2822 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2823 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2824 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2825 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2826
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2828 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2829 Inst.addOperand(MCOperand::CreateImm(add));
2830
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2831 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2832}
2833
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2834static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2835 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2836 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2837 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2838}
2839
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2840static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2841 uint64_t Address, const void *Decoder) {
2842 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2843 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2844
2845 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2846 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2847}
2848
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2849static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2850DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2851 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2852 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2853
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2854 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2855 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2856 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2857 switch (opc) {
2858 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2859 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2860 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2861 Inst.setOpcode(ARM::t2DSB);
2862 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2863 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2864 Inst.setOpcode(ARM::t2DMB);
2865 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2866 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2867 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2868 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2869 }
2870
2871 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2872 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2873 }
2874
2875 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2876 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2877 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2878 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2879 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2881 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2882 return MCDisassembler::Fail;
2883 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2884 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2885
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2886 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2887}
2888
2889// Decode a shifted immediate operand. These basically consist
2890// of an 8-bit value, and a 4-bit directive that specifies either
2891// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2892static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893 uint64_t Address, const void *Decoder) {
2894 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2895 if (ctrl == 0) {
2896 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2897 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2898 switch (byte) {
2899 case 0:
2900 Inst.addOperand(MCOperand::CreateImm(imm));
2901 break;
2902 case 1:
2903 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2904 break;
2905 case 2:
2906 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2907 break;
2908 case 3:
2909 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2910 (imm << 8) | imm));
2911 break;
2912 }
2913 } else {
2914 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2915 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2916 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2917 Inst.addOperand(MCOperand::CreateImm(imm));
2918 }
2919
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2920 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2921}
2922
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2923static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2924DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2925 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2926 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2927 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2928}
2929
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2930static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2931 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2932 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2933 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2934}
2935
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2936static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2937 uint64_t Address, const void *Decoder) {
2938 switch (Val) {
2939 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2940 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2941 case 0xF: // SY
2942 case 0xE: // ST
2943 case 0xB: // ISH
2944 case 0xA: // ISHST
2945 case 0x7: // NSH
2946 case 0x6: // NSHST
2947 case 0x3: // OSH
2948 case 0x2: // OSHST
2949 break;
2950 }
2951
2952 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2953 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2954}
2955
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2956static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2957 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2958 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2959 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2960 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2961}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2962
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2963static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2964 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2965 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2966
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2967 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2968 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2969 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2970
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2971 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2972
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2973 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2974 return MCDisassembler::Fail;
2975 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2976 return MCDisassembler::Fail;
2977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2978 return MCDisassembler::Fail;
2979 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2980 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2981
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2982 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2983}
2984
2985
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2986static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2987 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2988 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2989
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2990 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2991 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2992 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]2993 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2994
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2995 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2996 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2997
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2998 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
2999 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3000
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3002 return MCDisassembler::Fail;
3003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3004 return MCDisassembler::Fail;
3005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3006 return MCDisassembler::Fail;
3007 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3008 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3009
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3010 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3011}
3012
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3013static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3014 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3015 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3016
3017 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3018 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3019 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3020 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3021 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3022 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3023
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3024 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3025
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3027 return MCDisassembler::Fail;
3028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3029 return MCDisassembler::Fail;
3030 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3031 return MCDisassembler::Fail;
3032 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3033 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3034
3035 return S;
3036}
3037
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3038static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3039 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3040 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3041
3042 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3043 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3044 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3045 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3046 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3047 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3048 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3049
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3050 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3051 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3052
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3054 return MCDisassembler::Fail;
3055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3056 return MCDisassembler::Fail;
3057 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3058 return MCDisassembler::Fail;
3059 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3060 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3061
3062 return S;
3063}
3064
3065
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3066static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3067 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3068 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3069
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3070 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3071 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3072 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3073 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3074 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3075 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3076
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3077 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3078
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3080 return MCDisassembler::Fail;
3081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3082 return MCDisassembler::Fail;
3083 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3084 return MCDisassembler::Fail;
3085 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3086 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3087
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3088 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3089}
3090
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3091static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3092 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3093 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3094
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3095 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3096 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3097 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3098 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3099 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3100 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3101
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3102 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3103
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3105 return MCDisassembler::Fail;
3106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3107 return MCDisassembler::Fail;
3108 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3109 return MCDisassembler::Fail;
3110 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3111 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3112
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3113 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3114}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3115
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3116static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3117 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3118 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3119
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3120 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3121 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3122 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3123 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3124 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3125
3126 unsigned align = 0;
3127 unsigned index = 0;
3128 switch (size) {
3129 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3130 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3131 case 0:
3132 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3133 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3134 index = fieldFromInstruction32(Insn, 5, 3);
3135 break;
3136 case 1:
3137 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3138 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3139 index = fieldFromInstruction32(Insn, 6, 2);
3140 if (fieldFromInstruction32(Insn, 4, 1))
3141 align = 2;
3142 break;
3143 case 2:
3144 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3145 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3146 index = fieldFromInstruction32(Insn, 7, 1);
3147 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3148 align = 4;
3149 }
3150
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3151 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3152 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3153 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3155 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3156 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3158 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3159 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3160 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3161 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3163 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3164 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3165 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3166 }
3167
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3168 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3169 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3170 Inst.addOperand(MCOperand::CreateImm(index));
3171
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3172 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3173}
3174
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3175static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3176 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3177 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3178
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3179 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3180 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3181 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3182 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3183 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3184
3185 unsigned align = 0;
3186 unsigned index = 0;
3187 switch (size) {
3188 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3189 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3190 case 0:
3191 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3192 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3193 index = fieldFromInstruction32(Insn, 5, 3);
3194 break;
3195 case 1:
3196 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3197 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3198 index = fieldFromInstruction32(Insn, 6, 2);
3199 if (fieldFromInstruction32(Insn, 4, 1))
3200 align = 2;
3201 break;
3202 case 2:
3203 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3204 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3205 index = fieldFromInstruction32(Insn, 7, 1);
3206 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3207 align = 4;
3208 }
3209
3210 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3212 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3213 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3215 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3216 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3217 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3218 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3220 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3221 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3222 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3223 }
3224
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3226 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3227 Inst.addOperand(MCOperand::CreateImm(index));
3228
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3229 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3230}
3231
3232
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3233static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3234 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3235 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3236
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3237 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3238 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3239 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3240 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3241 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3242
3243 unsigned align = 0;
3244 unsigned index = 0;
3245 unsigned inc = 1;
3246 switch (size) {
3247 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3248 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3249 case 0:
3250 index = fieldFromInstruction32(Insn, 5, 3);
3251 if (fieldFromInstruction32(Insn, 4, 1))
3252 align = 2;
3253 break;
3254 case 1:
3255 index = fieldFromInstruction32(Insn, 6, 2);
3256 if (fieldFromInstruction32(Insn, 4, 1))
3257 align = 4;
3258 if (fieldFromInstruction32(Insn, 5, 1))
3259 inc = 2;
3260 break;
3261 case 2:
3262 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3263 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3264 index = fieldFromInstruction32(Insn, 7, 1);
3265 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3266 align = 8;
3267 if (fieldFromInstruction32(Insn, 6, 1))
3268 inc = 2;
3269 break;
3270 }
3271
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3272 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3273 return MCDisassembler::Fail;
3274 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3275 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3276 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3278 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3279 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3281 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3282 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3283 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3284 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3286 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3287 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3288 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3289 }
3290
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3291 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3292 return MCDisassembler::Fail;
3293 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3294 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3295 Inst.addOperand(MCOperand::CreateImm(index));
3296
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3297 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3298}
3299
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3300static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3301 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3302 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3303
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3304 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3305 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3306 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3307 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3308 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3309
3310 unsigned align = 0;
3311 unsigned index = 0;
3312 unsigned inc = 1;
3313 switch (size) {
3314 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3315 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3316 case 0:
3317 index = fieldFromInstruction32(Insn, 5, 3);
3318 if (fieldFromInstruction32(Insn, 4, 1))
3319 align = 2;
3320 break;
3321 case 1:
3322 index = fieldFromInstruction32(Insn, 6, 2);
3323 if (fieldFromInstruction32(Insn, 4, 1))
3324 align = 4;
3325 if (fieldFromInstruction32(Insn, 5, 1))
3326 inc = 2;
3327 break;
3328 case 2:
3329 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3330 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3331 index = fieldFromInstruction32(Insn, 7, 1);
3332 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3333 align = 8;
3334 if (fieldFromInstruction32(Insn, 6, 1))
3335 inc = 2;
3336 break;
3337 }
3338
3339 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3341 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3342 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3343 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3344 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3345 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3346 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3347 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3349 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3350 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3351 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3352 }
3353
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3355 return MCDisassembler::Fail;
3356 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3357 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3358 Inst.addOperand(MCOperand::CreateImm(index));
3359
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3360 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3361}
3362
3363
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3364static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3365 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3366 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3367
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3368 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3369 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3370 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3371 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3372 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3373
3374 unsigned align = 0;
3375 unsigned index = 0;
3376 unsigned inc = 1;
3377 switch (size) {
3378 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3379 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3380 case 0:
3381 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3382 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3383 index = fieldFromInstruction32(Insn, 5, 3);
3384 break;
3385 case 1:
3386 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3387 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3388 index = fieldFromInstruction32(Insn, 6, 2);
3389 if (fieldFromInstruction32(Insn, 5, 1))
3390 inc = 2;
3391 break;
3392 case 2:
3393 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3394 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3395 index = fieldFromInstruction32(Insn, 7, 1);
3396 if (fieldFromInstruction32(Insn, 6, 1))
3397 inc = 2;
3398 break;
3399 }
3400
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3401 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3402 return MCDisassembler::Fail;
3403 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3404 return MCDisassembler::Fail;
3405 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3406 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3407
3408 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3410 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3411 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3413 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3414 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3415 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3416 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3418 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3419 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3420 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3421 }
3422
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3423 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3424 return MCDisassembler::Fail;
3425 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3426 return MCDisassembler::Fail;
3427 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3428 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3429 Inst.addOperand(MCOperand::CreateImm(index));
3430
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3431 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3432}
3433
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3434static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3435 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3436 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3437
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3438 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3439 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3440 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3441 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3442 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3443
3444 unsigned align = 0;
3445 unsigned index = 0;
3446 unsigned inc = 1;
3447 switch (size) {
3448 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3449 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3450 case 0:
3451 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3452 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3453 index = fieldFromInstruction32(Insn, 5, 3);
3454 break;
3455 case 1:
3456 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3457 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3458 index = fieldFromInstruction32(Insn, 6, 2);
3459 if (fieldFromInstruction32(Insn, 5, 1))
3460 inc = 2;
3461 break;
3462 case 2:
3463 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3464 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3465 index = fieldFromInstruction32(Insn, 7, 1);
3466 if (fieldFromInstruction32(Insn, 6, 1))
3467 inc = 2;
3468 break;
3469 }
3470
3471 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3473 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3474 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3476 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3477 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3478 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3479 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3481 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3482 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3483 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3484 }
3485
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3486 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3487 return MCDisassembler::Fail;
3488 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3489 return MCDisassembler::Fail;
3490 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3491 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3492 Inst.addOperand(MCOperand::CreateImm(index));
3493
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3494 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3495}
3496
3497
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3498static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3499 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3500 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3501
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3502 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3503 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3504 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3505 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3506 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3507
3508 unsigned align = 0;
3509 unsigned index = 0;
3510 unsigned inc = 1;
3511 switch (size) {
3512 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3513 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3514 case 0:
3515 if (fieldFromInstruction32(Insn, 4, 1))
3516 align = 4;
3517 index = fieldFromInstruction32(Insn, 5, 3);
3518 break;
3519 case 1:
3520 if (fieldFromInstruction32(Insn, 4, 1))
3521 align = 8;
3522 index = fieldFromInstruction32(Insn, 6, 2);
3523 if (fieldFromInstruction32(Insn, 5, 1))
3524 inc = 2;
3525 break;
3526 case 2:
3527 if (fieldFromInstruction32(Insn, 4, 2))
3528 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3529 index = fieldFromInstruction32(Insn, 7, 1);
3530 if (fieldFromInstruction32(Insn, 6, 1))
3531 inc = 2;
3532 break;
3533 }
3534
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3536 return MCDisassembler::Fail;
3537 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3538 return MCDisassembler::Fail;
3539 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3540 return MCDisassembler::Fail;
3541 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3542 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3543
3544 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3546 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3547 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3549 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3550 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3551 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3552 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3554 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3555 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3556 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3557 }
3558
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3559 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3560 return MCDisassembler::Fail;
3561 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3562 return MCDisassembler::Fail;
3563 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3564 return MCDisassembler::Fail;
3565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3566 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3567 Inst.addOperand(MCOperand::CreateImm(index));
3568
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3569 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3570}
3571
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3572static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3573 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3574 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3575
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3576 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3577 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3578 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3579 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3580 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3581
3582 unsigned align = 0;
3583 unsigned index = 0;
3584 unsigned inc = 1;
3585 switch (size) {
3586 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3587 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3588 case 0:
3589 if (fieldFromInstruction32(Insn, 4, 1))
3590 align = 4;
3591 index = fieldFromInstruction32(Insn, 5, 3);
3592 break;
3593 case 1:
3594 if (fieldFromInstruction32(Insn, 4, 1))
3595 align = 8;
3596 index = fieldFromInstruction32(Insn, 6, 2);
3597 if (fieldFromInstruction32(Insn, 5, 1))
3598 inc = 2;
3599 break;
3600 case 2:
3601 if (fieldFromInstruction32(Insn, 4, 2))
3602 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3603 index = fieldFromInstruction32(Insn, 7, 1);
3604 if (fieldFromInstruction32(Insn, 6, 1))
3605 inc = 2;
3606 break;
3607 }
3608
3609 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3611 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3612 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3614 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3615 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3616 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3617 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3619 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3620 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3621 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3622 }
3623
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3625 return MCDisassembler::Fail;
3626 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3627 return MCDisassembler::Fail;
3628 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3629 return MCDisassembler::Fail;
3630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3631 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3632 Inst.addOperand(MCOperand::CreateImm(index));
3633
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3634 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3635}
3636
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3637static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3638 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3639 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3640 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3641 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3642 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3643 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3644 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3645
3646 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3647 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3648
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3649 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3650 return MCDisassembler::Fail;
3651 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3652 return MCDisassembler::Fail;
3653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3654 return MCDisassembler::Fail;
3655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3656 return MCDisassembler::Fail;
3657 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3658 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3659
3660 return S;
3661}
3662
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3663static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3664 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3665 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3666 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3667 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3668 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3669 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3670 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3671
3672 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3673 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3674
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3676 return MCDisassembler::Fail;
3677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3678 return MCDisassembler::Fail;
3679 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3680 return MCDisassembler::Fail;
3681 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3682 return MCDisassembler::Fail;
3683 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3684 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3685
3686 return S;
3687}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3688
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3689static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3690 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3691 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3692 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3693 // The InstPrinter needs to have the low bit of the predicate in
3694 // the mask operand to be able to print it properly.
3695 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3696
3697 if (pred == 0xF) {
3698 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3699 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3700 }
3701
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3702 if ((mask & 0xF) == 0) {
3703 // Preserve the high bit of the mask, which is the low bit of
3704 // the predicate.
3705 mask &= 0x10;
3706 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3707 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3708 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3709
3710 Inst.addOperand(MCOperand::CreateImm(pred));
3711 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3712 return S;
3713}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3714
3715static DecodeStatus
3716DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3717 uint64_t Address, const void *Decoder) {
3718 DecodeStatus S = MCDisassembler::Success;
3719
3720 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3721 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3722 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3723 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3724 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3725 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3726 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3727 bool writeback = (W == 1) | (P == 0);
3728
3729 addr |= (U << 8) | (Rn << 9);
3730
3731 if (writeback && (Rn == Rt || Rn == Rt2))
3732 Check(S, MCDisassembler::SoftFail);
3733 if (Rt == Rt2)
3734 Check(S, MCDisassembler::SoftFail);
3735
3736 // Rt
3737 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3738 return MCDisassembler::Fail;
3739 // Rt2
3740 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3741 return MCDisassembler::Fail;
3742 // Writeback operand
3743 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3744 return MCDisassembler::Fail;
3745 // addr
3746 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3747 return MCDisassembler::Fail;
3748
3749 return S;
3750}
3751
3752static DecodeStatus
3753DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3754 uint64_t Address, const void *Decoder) {
3755 DecodeStatus S = MCDisassembler::Success;
3756
3757 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3758 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3759 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3760 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3761 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3762 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3763 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3764 bool writeback = (W == 1) | (P == 0);
3765
3766 addr |= (U << 8) | (Rn << 9);
3767
3768 if (writeback && (Rn == Rt || Rn == Rt2))
3769 Check(S, MCDisassembler::SoftFail);
3770
3771 // Writeback operand
3772 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3773 return MCDisassembler::Fail;
3774 // Rt
3775 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3776 return MCDisassembler::Fail;
3777 // Rt2
3778 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3779 return MCDisassembler::Fail;
3780 // addr
3781 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3782 return MCDisassembler::Fail;
3783
3784 return S;
3785}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]3786
3787static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3788 uint64_t Address, const void *Decoder) {
3789 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3790 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3791 if (sign1 != sign2) return MCDisassembler::Fail;
3792
3793 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3794 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3795 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3796 Val |= sign1 << 12;
3797 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3798
3799 return MCDisassembler::Success;
3800}
3801