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gerrit-public.fairphone.software / platform / external / llvm / 2a7d3a93735f97c2a4cabcc08a88d702c28cb0d4 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 2f504b756b1b34c57e76e3e5934c48cd889910cd [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]13#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]14#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]15#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]16#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]17#include "llvm/MC/MCInstrDesc.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]20#include "llvm/MC/MCDisassembler.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]21#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]48 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]49 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]50 raw_ostream &vStream,
51 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]52
53 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]54 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]55private:
56};
57
58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59class ThumbDisassembler : public MCDisassembler {
60public:
61 /// Constructor - Initializes the disassembler.
62 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]65 }
66
67 ~ThumbDisassembler() {
68 }
69
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
72 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]73 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]74 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]75 raw_ostream &vStream,
76 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]77
78 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]79 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]80private:
81 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]82 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]83 void UpdateThumbVFPPredicate(MCInst&) const;
84};
85}
86
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]87static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]88 switch (In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
91 return true;
92 case MCDisassembler::SoftFail:
93 Out = In;
94 return true;
95 case MCDisassembler::Fail:
96 Out = In;
97 return false;
98 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]99 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]100}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]101
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]102
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103// Forward declare these because the autogenerated code will reference them.
104// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]105static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]106 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]107static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]110static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]112static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]114static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]116static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]118static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]120static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]122static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]126static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]128static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]129 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]130static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]131 unsigned RegNo, uint64_t Address,
132 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]133
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]134static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]136static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]138static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]140static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]142static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]144static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]146
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]147static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]148 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]149static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]150 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]151static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]152 unsigned Insn,
153 uint64_t Address,
154 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]155static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]157static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]159static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]161static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
163
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]164static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]165 unsigned Insn,
166 uint64_t Adddress,
167 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]168static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]170static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]172static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]174static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]176static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]178static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]180static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]182static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame^]184static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
185 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]186static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]188static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]190static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]192static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]194static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]198static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]200static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]202static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]204static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]210static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]212static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]214static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]216static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]218static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]220static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]222static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]224static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]226static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]228static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]230static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]232static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]234static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]236static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]238static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]240static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]242static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]244static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]246static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]248static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]250static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]252static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]254static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]256static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]258static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]260static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
262
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]264static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]266static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]268static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]270static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]272static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]274static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]276static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]278static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]280static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]282static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]284static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]286static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]288static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]290static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]292static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]294static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]296static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]298static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]300static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]302static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]303 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]304static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]305 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]306static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]307 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]308static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]309 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]310static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]311 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]312static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]313 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]314static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]315 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]316static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]317 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]318static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]319 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]320static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]321 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]322static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]323 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]324static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]325 uint64_t Address, const void *Decoder);
326
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]327static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]328 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329#include "ARMGenDisassemblerTables.inc"
330#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]331#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]332
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]333static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
334 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]335}
336
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]337static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
338 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]339}
340
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]341const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]342 return instInfoARM;
343}
344
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]345const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]346 return instInfoARM;
347}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]348
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]349DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]350 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]351 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]352 raw_ostream &os,
353 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]354 CommentStream = &cs;
355
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]356 uint8_t bytes[4];
357
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]358 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
359 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
360
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]361 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]362 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
363 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]364 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]365 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]366
367 // Encoded as a small-endian 32-bit word in the stream.
368 uint32_t insn = (bytes[3] << 24) |
369 (bytes[2] << 16) |
370 (bytes[1] << 8) |
371 (bytes[0] << 0);
372
373 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]374 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]375 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]377 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]378 }
379
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]380 // VFP and NEON instructions, similarly, are shared between ARM
381 // and Thumb modes.
382 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]383 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]384 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]385 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]386 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]387 }
388
389 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]390 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]391 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]392 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]393 // Add a fake predicate operand, because we share these instruction
394 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]395 if (!DecodePredicateOperand(MI, 0xE, Address, this))
396 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]397 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]398 }
399
400 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]401 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]402 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]403 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]404 // Add a fake predicate operand, because we share these instruction
405 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]406 if (!DecodePredicateOperand(MI, 0xE, Address, this))
407 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]408 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]409 }
410
411 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]412 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]413 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]414 Size = 4;
415 // Add a fake predicate operand, because we share these instruction
416 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]417 if (!DecodePredicateOperand(MI, 0xE, Address, this))
418 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]419 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]420 }
421
422 MI.clear();
423
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]424 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]425 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]426}
427
428namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]429extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]430}
431
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]432/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
433/// immediate Value in the MCInst. The immediate Value has had any PC
434/// adjustment made by the caller. If the instruction is a branch instruction
435/// then isBranch is true, else false. If the getOpInfo() function was set as
436/// part of the setupForSymbolicDisassembly() call then that function is called
437/// to get any symbolic information at the Address for this instruction. If
438/// that returns non-zero then the symbolic information it returns is used to
439/// create an MCExpr and that is added as an operand to the MCInst. If
440/// getOpInfo() returns zero and isBranch is true then a symbol look up for
441/// Value is done and if a symbol is found an MCExpr is created with that, else
442/// an MCExpr with Value is created. This function returns true if it adds an
443/// operand to the MCInst and false otherwise.
444static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
445 bool isBranch, uint64_t InstSize,
446 MCInst &MI, const void *Decoder) {
447 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
448 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]449 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]450 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]451 SymbolicOp.Value = Value;
452 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]453
454 if (!getOpInfo ||
455 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
456 // Clear SymbolicOp.Value from above and also all other fields.
457 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
458 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
459 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]460 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]461 uint64_t ReferenceType;
462 if (isBranch)
463 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
464 else
465 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
466 const char *ReferenceName;
467 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
468 &ReferenceName);
469 if (Name) {
470 SymbolicOp.AddSymbol.Name = Name;
471 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]472 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]473 // For branches always create an MCExpr so it gets printed as hex address.
474 else if (isBranch) {
475 SymbolicOp.Value = Value;
476 }
477 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
478 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
479 if (!Name && !isBranch)
480 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]481 }
482
483 MCContext *Ctx = Dis->getMCContext();
484 const MCExpr *Add = NULL;
485 if (SymbolicOp.AddSymbol.Present) {
486 if (SymbolicOp.AddSymbol.Name) {
487 StringRef Name(SymbolicOp.AddSymbol.Name);
488 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
489 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
490 } else {
491 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
492 }
493 }
494
495 const MCExpr *Sub = NULL;
496 if (SymbolicOp.SubtractSymbol.Present) {
497 if (SymbolicOp.SubtractSymbol.Name) {
498 StringRef Name(SymbolicOp.SubtractSymbol.Name);
499 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
500 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
501 } else {
502 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
503 }
504 }
505
506 const MCExpr *Off = NULL;
507 if (SymbolicOp.Value != 0)
508 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
509
510 const MCExpr *Expr;
511 if (Sub) {
512 const MCExpr *LHS;
513 if (Add)
514 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
515 else
516 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
517 if (Off != 0)
518 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
519 else
520 Expr = LHS;
521 } else if (Add) {
522 if (Off != 0)
523 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
524 else
525 Expr = Add;
526 } else {
527 if (Off != 0)
528 Expr = Off;
529 else
530 Expr = MCConstantExpr::Create(0, *Ctx);
531 }
532
533 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
534 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
535 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
536 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
537 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
538 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]539 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]540 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]541
542 return true;
543}
544
545/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
546/// referenced by a load instruction with the base register that is the Pc.
547/// These can often be values in a literal pool near the Address of the
548/// instruction. The Address of the instruction and its immediate Value are
549/// used as a possible literal pool entry. The SymbolLookUp call back will
550/// return the name of a symbol referenced by the the literal pool's entry if
551/// the referenced address is that of a symbol. Or it will return a pointer to
552/// a literal 'C' string if the referenced address of the literal pool's entry
553/// is an address into a section with 'C' string literals.
554static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]555 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]556 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
557 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
558 if (SymbolLookUp) {
559 void *DisInfo = Dis->getDisInfoBlock();
560 uint64_t ReferenceType;
561 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
562 const char *ReferenceName;
563 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
564 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
565 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
566 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
567 }
568}
569
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]570// Thumb1 instructions don't have explicit S bits. Rather, they
571// implicitly set CPSR. Since it's not represented in the encoding, the
572// auto-generated decoder won't inject the CPSR operand. We need to fix
573// that as a post-pass.
574static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
575 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]576 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]577 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]578 for (unsigned i = 0; i < NumOps; ++i, ++I) {
579 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]580 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]581 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]582 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
583 return;
584 }
585 }
586
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]587 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]588}
589
590// Most Thumb instructions don't have explicit predicates in the
591// encoding, but rather get their predicates from IT context. We need
592// to fix up the predicate operands using this context information as a
593// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]594MCDisassembler::DecodeStatus
595ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]596 MCDisassembler::DecodeStatus S = Success;
597
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]598 // A few instructions actually have predicates encoded in them. Don't
599 // try to overwrite it if we're seeing one of those.
600 switch (MI.getOpcode()) {
601 case ARM::tBcc:
602 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]603 case ARM::tCBZ:
604 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]605 case ARM::tCPS:
606 case ARM::t2CPS3p:
607 case ARM::t2CPS2p:
608 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]609 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]610 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]611 // Some instructions (mostly conditional branches) are not
612 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]613 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]614 S = SoftFail;
615 else
616 return Success;
617 break;
618 case ARM::tB:
619 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]620 case ARM::t2TBB:
621 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]622 // Some instructions (mostly unconditional branches) can
623 // only appears at the end of, or outside of, an IT.
624 if (ITBlock.size() > 1)
625 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]626 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]627 default:
628 break;
629 }
630
631 // If we're in an IT block, base the predicate on that. Otherwise,
632 // assume a predicate of AL.
633 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]634 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]635 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]636 if (CC == 0xF)
637 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]638 ITBlock.pop_back();
639 } else
640 CC = ARMCC::AL;
641
642 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]643 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]644 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]645 for (unsigned i = 0; i < NumOps; ++i, ++I) {
646 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]647 if (OpInfo[i].isPredicate()) {
648 I = MI.insert(I, MCOperand::CreateImm(CC));
649 ++I;
650 if (CC == ARMCC::AL)
651 MI.insert(I, MCOperand::CreateReg(0));
652 else
653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]654 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]655 }
656 }
657
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]658 I = MI.insert(I, MCOperand::CreateImm(CC));
659 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]660 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]661 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]662 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]663 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]664
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]665 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]666}
667
668// Thumb VFP instructions are a special case. Because we share their
669// encodings between ARM and Thumb modes, and they are predicable in ARM
670// mode, the auto-generated decoder will give them an (incorrect)
671// predicate operand. We need to rewrite these operands based on the IT
672// context as a post-pass.
673void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
674 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]675 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]676 CC = ITBlock.back();
677 ITBlock.pop_back();
678 } else
679 CC = ARMCC::AL;
680
681 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
682 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]683 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
684 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]685 if (OpInfo[i].isPredicate() ) {
686 I->setImm(CC);
687 ++I;
688 if (CC == ARMCC::AL)
689 I->setReg(0);
690 else
691 I->setReg(ARM::CPSR);
692 return;
693 }
694 }
695}
696
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]697DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]698 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]699 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]700 raw_ostream &os,
701 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]702 CommentStream = &cs;
703
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704 uint8_t bytes[4];
705
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]706 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
707 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
708
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]709 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]710 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
711 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]712 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]713 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]714
715 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]716 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]717 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]718 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]719 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]720 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]721 }
722
723 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]724 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]725 if (result) {
726 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]727 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]728 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]729 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]730 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]731 }
732
733 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]734 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]735 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]736 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]737
738 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
739 // the Thumb predicate.
740 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
741 result = MCDisassembler::SoftFail;
742
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]743 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]744
745 // If we find an IT instruction, we need to parse its condition
746 // code and mask operands so that we can apply them correctly
747 // to the subsequent instructions.
748 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]749
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]750 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]751 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]752 unsigned Mask = MI.getOperand(1).getImm();
753 unsigned CondBit0 = Mask >> 4 & 1;
754 unsigned NumTZ = CountTrailingZeros_32(Mask);
755 assert(NumTZ <= 3 && "Invalid IT mask!");
756 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
757 bool T = ((Mask >> Pos) & 1) == CondBit0;
758 if (T)
759 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]760 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]761 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]762 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]763
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]764 ITBlock.push_back(firstcond);
765 }
766
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]767 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]768 }
769
770 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]771 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
772 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]773 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]774 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]775
776 uint32_t insn32 = (bytes[3] << 8) |
777 (bytes[2] << 0) |
778 (bytes[1] << 24) |
779 (bytes[0] << 16);
780 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]781 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]782 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 Size = 4;
784 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]785 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]787 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]788 }
789
790 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]791 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]792 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]793 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]794 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]795 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]796 }
797
798 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]799 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]800 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]801 Size = 4;
802 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]803 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]804 }
805
806 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]807 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]808 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]809 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]810 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]811 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]812 }
813
814 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
815 MI.clear();
816 uint32_t NEONLdStInsn = insn32;
817 NEONLdStInsn &= 0xF0FFFFFF;
818 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]819 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]820 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]821 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]822 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]823 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]824 }
825 }
826
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]827 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]828 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]829 uint32_t NEONDataInsn = insn32;
830 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
831 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
832 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]833 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]834 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]835 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]836 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]837 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]838 }
839 }
840
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]841 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]842 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]843}
844
845
846extern "C" void LLVMInitializeARMDisassembler() {
847 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
848 createARMDisassembler);
849 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
850 createThumbDisassembler);
851}
852
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]853static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
855 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
856 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
857 ARM::R12, ARM::SP, ARM::LR, ARM::PC
858};
859
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]860static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]861 uint64_t Address, const void *Decoder) {
862 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]863 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]864
865 unsigned Register = GPRDecoderTable[RegNo];
866 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]867 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]868}
869
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]870static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]871DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]872 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]873 DecodeStatus S = MCDisassembler::Success;
874
875 if (RegNo == 15)
876 S = MCDisassembler::SoftFail;
877
878 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
879
880 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]881}
882
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]883static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]884 uint64_t Address, const void *Decoder) {
885 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]886 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]887 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
888}
889
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]890static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]891 uint64_t Address, const void *Decoder) {
892 unsigned Register = 0;
893 switch (RegNo) {
894 case 0:
895 Register = ARM::R0;
896 break;
897 case 1:
898 Register = ARM::R1;
899 break;
900 case 2:
901 Register = ARM::R2;
902 break;
903 case 3:
904 Register = ARM::R3;
905 break;
906 case 9:
907 Register = ARM::R9;
908 break;
909 case 12:
910 Register = ARM::R12;
911 break;
912 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]913 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]914 }
915
916 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]917 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]918}
919
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]920static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]921 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]922 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]923 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
924}
925
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]926static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]927 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
928 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
929 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
930 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
931 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
932 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
933 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
934 ARM::S28, ARM::S29, ARM::S30, ARM::S31
935};
936
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]937static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]938 uint64_t Address, const void *Decoder) {
939 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]940 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]941
942 unsigned Register = SPRDecoderTable[RegNo];
943 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]944 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]945}
946
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]947static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]948 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
949 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
950 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
951 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
952 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
953 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
954 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
955 ARM::D28, ARM::D29, ARM::D30, ARM::D31
956};
957
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]958static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]959 uint64_t Address, const void *Decoder) {
960 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]961 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]962
963 unsigned Register = DPRDecoderTable[RegNo];
964 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]965 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]966}
967
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]968static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]969 uint64_t Address, const void *Decoder) {
970 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]971 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]972 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
973}
974
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]975static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]976DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]977 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]979 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]980 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
981}
982
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]983static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
985 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
986 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
987 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
988};
989
990
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]991static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]992 uint64_t Address, const void *Decoder) {
993 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]994 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995 RegNo >>= 1;
996
997 unsigned Register = QPRDecoderTable[RegNo];
998 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]999 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1000}
1001
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1002static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1003 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1004 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1005 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1006 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1007 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1008 ARM::Q15
1009};
1010
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1011static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1012 uint64_t Address, const void *Decoder) {
1013 if (RegNo > 30)
1014 return MCDisassembler::Fail;
1015
1016 unsigned Register = DPairDecoderTable[RegNo];
1017 Inst.addOperand(MCOperand::CreateReg(Register));
1018 return MCDisassembler::Success;
1019}
1020
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1021static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1022 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1023 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1024 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1025 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1026 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1027 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1028 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1029 ARM::D28_D30, ARM::D29_D31
1030};
1031
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1032static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1033 unsigned RegNo,
1034 uint64_t Address,
1035 const void *Decoder) {
1036 if (RegNo > 29)
1037 return MCDisassembler::Fail;
1038
1039 unsigned Register = DPairSpacedDecoderTable[RegNo];
1040 Inst.addOperand(MCOperand::CreateReg(Register));
1041 return MCDisassembler::Success;
1042}
1043
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1044static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1045 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1046 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1047 // AL predicate is not allowed on Thumb1 branches.
1048 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1049 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1050 Inst.addOperand(MCOperand::CreateImm(Val));
1051 if (Val == ARMCC::AL) {
1052 Inst.addOperand(MCOperand::CreateReg(0));
1053 } else
1054 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1055 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1056}
1057
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1058static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1059 uint64_t Address, const void *Decoder) {
1060 if (Val)
1061 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1062 else
1063 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1064 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1065}
1066
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1067static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1068 uint64_t Address, const void *Decoder) {
1069 uint32_t imm = Val & 0xFF;
1070 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1071 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1072 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1073 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1074}
1075
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1076static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1077 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1078 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1079
1080 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1081 unsigned type = fieldFromInstruction32(Val, 5, 2);
1082 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1083
1084 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1086 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1087
1088 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1089 switch (type) {
1090 case 0:
1091 Shift = ARM_AM::lsl;
1092 break;
1093 case 1:
1094 Shift = ARM_AM::lsr;
1095 break;
1096 case 2:
1097 Shift = ARM_AM::asr;
1098 break;
1099 case 3:
1100 Shift = ARM_AM::ror;
1101 break;
1102 }
1103
1104 if (Shift == ARM_AM::ror && imm == 0)
1105 Shift = ARM_AM::rrx;
1106
1107 unsigned Op = Shift | (imm << 3);
1108 Inst.addOperand(MCOperand::CreateImm(Op));
1109
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1110 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1111}
1112
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1113static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1114 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1115 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1116
1117 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1118 unsigned type = fieldFromInstruction32(Val, 5, 2);
1119 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1120
1121 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1123 return MCDisassembler::Fail;
1124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1125 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1126
1127 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1128 switch (type) {
1129 case 0:
1130 Shift = ARM_AM::lsl;
1131 break;
1132 case 1:
1133 Shift = ARM_AM::lsr;
1134 break;
1135 case 2:
1136 Shift = ARM_AM::asr;
1137 break;
1138 case 3:
1139 Shift = ARM_AM::ror;
1140 break;
1141 }
1142
1143 Inst.addOperand(MCOperand::CreateImm(Shift));
1144
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1145 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1146}
1147
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1148static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1149 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1150 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1151
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1152 bool writebackLoad = false;
1153 unsigned writebackReg = 0;
1154 switch (Inst.getOpcode()) {
1155 default:
1156 break;
1157 case ARM::LDMIA_UPD:
1158 case ARM::LDMDB_UPD:
1159 case ARM::LDMIB_UPD:
1160 case ARM::LDMDA_UPD:
1161 case ARM::t2LDMIA_UPD:
1162 case ARM::t2LDMDB_UPD:
1163 writebackLoad = true;
1164 writebackReg = Inst.getOperand(0).getReg();
1165 break;
1166 }
1167
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1168 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1169 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1170 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1171 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1172 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1173 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1174 // Writeback not allowed if Rn is in the target list.
1175 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1176 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1177 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1178 }
1179
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1180 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1181}
1182
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1183static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1184 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1185 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1186
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1187 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1188 unsigned regs = Val & 0xFF;
1189
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1190 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1191 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1192 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1193 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1194 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1195 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1196
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1197 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1198}
1199
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1200static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1201 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1202 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1203
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1204 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1205 unsigned regs = (Val & 0xFF) / 2;
1206
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1207 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1208 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1209 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1210 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1211 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1212 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1213
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1214 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1215}
1216
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1217static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1218 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1219 // This operand encodes a mask of contiguous zeros between a specified MSB
1220 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1221 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1222 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1223 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1225 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1226
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1227 DecodeStatus S = MCDisassembler::Success;
1228 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1229
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1230 uint32_t msb_mask = 0xFFFFFFFF;
1231 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1232 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1233
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1234 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1235 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1236}
1237
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1238static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1239 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1240 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1241
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1242 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1243 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1244 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1245 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1246 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1247 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1248
1249 switch (Inst.getOpcode()) {
1250 case ARM::LDC_OFFSET:
1251 case ARM::LDC_PRE:
1252 case ARM::LDC_POST:
1253 case ARM::LDC_OPTION:
1254 case ARM::LDCL_OFFSET:
1255 case ARM::LDCL_PRE:
1256 case ARM::LDCL_POST:
1257 case ARM::LDCL_OPTION:
1258 case ARM::STC_OFFSET:
1259 case ARM::STC_PRE:
1260 case ARM::STC_POST:
1261 case ARM::STC_OPTION:
1262 case ARM::STCL_OFFSET:
1263 case ARM::STCL_PRE:
1264 case ARM::STCL_POST:
1265 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1266 case ARM::t2LDC_OFFSET:
1267 case ARM::t2LDC_PRE:
1268 case ARM::t2LDC_POST:
1269 case ARM::t2LDC_OPTION:
1270 case ARM::t2LDCL_OFFSET:
1271 case ARM::t2LDCL_PRE:
1272 case ARM::t2LDCL_POST:
1273 case ARM::t2LDCL_OPTION:
1274 case ARM::t2STC_OFFSET:
1275 case ARM::t2STC_PRE:
1276 case ARM::t2STC_POST:
1277 case ARM::t2STC_OPTION:
1278 case ARM::t2STCL_OFFSET:
1279 case ARM::t2STCL_PRE:
1280 case ARM::t2STCL_POST:
1281 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1282 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1283 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1284 break;
1285 default:
1286 break;
1287 }
1288
1289 Inst.addOperand(MCOperand::CreateImm(coproc));
1290 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1292 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1293
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1294 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1295 case ARM::t2LDC2_OFFSET:
1296 case ARM::t2LDC2L_OFFSET:
1297 case ARM::t2LDC2_PRE:
1298 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1299 case ARM::t2STC2_OFFSET:
1300 case ARM::t2STC2L_OFFSET:
1301 case ARM::t2STC2_PRE:
1302 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1303 case ARM::LDC2_OFFSET:
1304 case ARM::LDC2L_OFFSET:
1305 case ARM::LDC2_PRE:
1306 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1307 case ARM::STC2_OFFSET:
1308 case ARM::STC2L_OFFSET:
1309 case ARM::STC2_PRE:
1310 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1311 case ARM::t2LDC_OFFSET:
1312 case ARM::t2LDCL_OFFSET:
1313 case ARM::t2LDC_PRE:
1314 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1315 case ARM::t2STC_OFFSET:
1316 case ARM::t2STCL_OFFSET:
1317 case ARM::t2STC_PRE:
1318 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1319 case ARM::LDC_OFFSET:
1320 case ARM::LDCL_OFFSET:
1321 case ARM::LDC_PRE:
1322 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1323 case ARM::STC_OFFSET:
1324 case ARM::STCL_OFFSET:
1325 case ARM::STC_PRE:
1326 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1327 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1328 Inst.addOperand(MCOperand::CreateImm(imm));
1329 break;
1330 case ARM::t2LDC2_POST:
1331 case ARM::t2LDC2L_POST:
1332 case ARM::t2STC2_POST:
1333 case ARM::t2STC2L_POST:
1334 case ARM::LDC2_POST:
1335 case ARM::LDC2L_POST:
1336 case ARM::STC2_POST:
1337 case ARM::STC2L_POST:
1338 case ARM::t2LDC_POST:
1339 case ARM::t2LDCL_POST:
1340 case ARM::t2STC_POST:
1341 case ARM::t2STCL_POST:
1342 case ARM::LDC_POST:
1343 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1344 case ARM::STC_POST:
1345 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1346 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1347 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1348 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1349 // The 'option' variant doesn't encode 'U' in the immediate since
1350 // the immediate is unsigned [0,255].
1351 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1352 break;
1353 }
1354
1355 switch (Inst.getOpcode()) {
1356 case ARM::LDC_OFFSET:
1357 case ARM::LDC_PRE:
1358 case ARM::LDC_POST:
1359 case ARM::LDC_OPTION:
1360 case ARM::LDCL_OFFSET:
1361 case ARM::LDCL_PRE:
1362 case ARM::LDCL_POST:
1363 case ARM::LDCL_OPTION:
1364 case ARM::STC_OFFSET:
1365 case ARM::STC_PRE:
1366 case ARM::STC_POST:
1367 case ARM::STC_OPTION:
1368 case ARM::STCL_OFFSET:
1369 case ARM::STCL_PRE:
1370 case ARM::STCL_POST:
1371 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1372 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1373 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1374 break;
1375 default:
1376 break;
1377 }
1378
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1379 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1380}
1381
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1382static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1383DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1384 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1385 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1386
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1387 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1388 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1389 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1390 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1391 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1392 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1393 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1394 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1395
1396 // On stores, the writeback operand precedes Rt.
1397 switch (Inst.getOpcode()) {
1398 case ARM::STR_POST_IMM:
1399 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1400 case ARM::STRB_POST_IMM:
1401 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1402 case ARM::STRT_POST_REG:
1403 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1404 case ARM::STRBT_POST_REG:
1405 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1407 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1408 break;
1409 default:
1410 break;
1411 }
1412
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1414 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1415
1416 // On loads, the writeback operand comes after Rt.
1417 switch (Inst.getOpcode()) {
1418 case ARM::LDR_POST_IMM:
1419 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1420 case ARM::LDRB_POST_IMM:
1421 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1422 case ARM::LDRBT_POST_REG:
1423 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1424 case ARM::LDRT_POST_REG:
1425 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1427 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1428 break;
1429 default:
1430 break;
1431 }
1432
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1434 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1435
1436 ARM_AM::AddrOpc Op = ARM_AM::add;
1437 if (!fieldFromInstruction32(Insn, 23, 1))
1438 Op = ARM_AM::sub;
1439
1440 bool writeback = (P == 0) || (W == 1);
1441 unsigned idx_mode = 0;
1442 if (P && writeback)
1443 idx_mode = ARMII::IndexModePre;
1444 else if (!P && writeback)
1445 idx_mode = ARMII::IndexModePost;
1446
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1447 if (writeback && (Rn == 15 || Rn == Rt))
1448 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1449
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1450 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1451 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1452 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1453 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1454 switch( fieldFromInstruction32(Insn, 5, 2)) {
1455 case 0:
1456 Opc = ARM_AM::lsl;
1457 break;
1458 case 1:
1459 Opc = ARM_AM::lsr;
1460 break;
1461 case 2:
1462 Opc = ARM_AM::asr;
1463 break;
1464 case 3:
1465 Opc = ARM_AM::ror;
1466 break;
1467 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1468 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1469 }
1470 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1471 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1472
1473 Inst.addOperand(MCOperand::CreateImm(imm));
1474 } else {
1475 Inst.addOperand(MCOperand::CreateReg(0));
1476 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1477 Inst.addOperand(MCOperand::CreateImm(tmp));
1478 }
1479
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1480 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1481 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1482
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1483 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1484}
1485
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1486static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1487 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1488 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1489
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1490 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1491 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1492 unsigned type = fieldFromInstruction32(Val, 5, 2);
1493 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1494 unsigned U = fieldFromInstruction32(Val, 12, 1);
1495
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1496 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1497 switch (type) {
1498 case 0:
1499 ShOp = ARM_AM::lsl;
1500 break;
1501 case 1:
1502 ShOp = ARM_AM::lsr;
1503 break;
1504 case 2:
1505 ShOp = ARM_AM::asr;
1506 break;
1507 case 3:
1508 ShOp = ARM_AM::ror;
1509 break;
1510 }
1511
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1513 return MCDisassembler::Fail;
1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1515 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1516 unsigned shift;
1517 if (U)
1518 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1519 else
1520 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1521 Inst.addOperand(MCOperand::CreateImm(shift));
1522
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1523 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1524}
1525
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1526static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1527DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1528 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1529 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1530
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1531 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1532 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1533 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1534 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1535 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1536 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1537 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1538 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1539 unsigned P = fieldFromInstruction32(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1540 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1541
1542 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1543
1544 // For {LD,ST}RD, Rt must be even, else undefined.
1545 switch (Inst.getOpcode()) {
1546 case ARM::STRD:
1547 case ARM::STRD_PRE:
1548 case ARM::STRD_POST:
1549 case ARM::LDRD:
1550 case ARM::LDRD_PRE:
1551 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1552 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1553 break;
1554 default:
1555 break;
1556 }
1557 switch (Inst.getOpcode()) {
1558 case ARM::STRD:
1559 case ARM::STRD_PRE:
1560 case ARM::STRD_POST:
1561 if (P == 0 && W == 1)
1562 S = MCDisassembler::SoftFail;
1563
1564 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1565 S = MCDisassembler::SoftFail;
1566 if (type && Rm == 15)
1567 S = MCDisassembler::SoftFail;
1568 if (Rt2 == 15)
1569 S = MCDisassembler::SoftFail;
1570 if (!type && fieldFromInstruction32(Insn, 8, 4))
1571 S = MCDisassembler::SoftFail;
1572 break;
1573 case ARM::STRH:
1574 case ARM::STRH_PRE:
1575 case ARM::STRH_POST:
1576 if (Rt == 15)
1577 S = MCDisassembler::SoftFail;
1578 if (writeback && (Rn == 15 || Rn == Rt))
1579 S = MCDisassembler::SoftFail;
1580 if (!type && Rm == 15)
1581 S = MCDisassembler::SoftFail;
1582 break;
1583 case ARM::LDRD:
1584 case ARM::LDRD_PRE:
1585 case ARM::LDRD_POST:
1586 if (type && Rn == 15){
1587 if (Rt2 == 15)
1588 S = MCDisassembler::SoftFail;
1589 break;
1590 }
1591 if (P == 0 && W == 1)
1592 S = MCDisassembler::SoftFail;
1593 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1594 S = MCDisassembler::SoftFail;
1595 if (!type && writeback && Rn == 15)
1596 S = MCDisassembler::SoftFail;
1597 if (writeback && (Rn == Rt || Rn == Rt2))
1598 S = MCDisassembler::SoftFail;
1599 break;
1600 case ARM::LDRH:
1601 case ARM::LDRH_PRE:
1602 case ARM::LDRH_POST:
1603 if (type && Rn == 15){
1604 if (Rt == 15)
1605 S = MCDisassembler::SoftFail;
1606 break;
1607 }
1608 if (Rt == 15)
1609 S = MCDisassembler::SoftFail;
1610 if (!type && Rm == 15)
1611 S = MCDisassembler::SoftFail;
1612 if (!type && writeback && (Rn == 15 || Rn == Rt))
1613 S = MCDisassembler::SoftFail;
1614 break;
1615 case ARM::LDRSH:
1616 case ARM::LDRSH_PRE:
1617 case ARM::LDRSH_POST:
1618 case ARM::LDRSB:
1619 case ARM::LDRSB_PRE:
1620 case ARM::LDRSB_POST:
1621 if (type && Rn == 15){
1622 if (Rt == 15)
1623 S = MCDisassembler::SoftFail;
1624 break;
1625 }
1626 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1627 S = MCDisassembler::SoftFail;
1628 if (!type && (Rt == 15 || Rm == 15))
1629 S = MCDisassembler::SoftFail;
1630 if (!type && writeback && (Rn == 15 || Rn == Rt))
1631 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1632 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1633 default:
1634 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1635 }
1636
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 if (writeback) { // Writeback
1638 if (P)
1639 U |= ARMII::IndexModePre << 9;
1640 else
1641 U |= ARMII::IndexModePost << 9;
1642
1643 // On stores, the writeback operand precedes Rt.
1644 switch (Inst.getOpcode()) {
1645 case ARM::STRD:
1646 case ARM::STRD_PRE:
1647 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1648 case ARM::STRH:
1649 case ARM::STRH_PRE:
1650 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1652 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1653 break;
1654 default:
1655 break;
1656 }
1657 }
1658
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1660 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1661 switch (Inst.getOpcode()) {
1662 case ARM::STRD:
1663 case ARM::STRD_PRE:
1664 case ARM::STRD_POST:
1665 case ARM::LDRD:
1666 case ARM::LDRD_PRE:
1667 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1669 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1670 break;
1671 default:
1672 break;
1673 }
1674
1675 if (writeback) {
1676 // On loads, the writeback operand comes after Rt.
1677 switch (Inst.getOpcode()) {
1678 case ARM::LDRD:
1679 case ARM::LDRD_PRE:
1680 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1681 case ARM::LDRH:
1682 case ARM::LDRH_PRE:
1683 case ARM::LDRH_POST:
1684 case ARM::LDRSH:
1685 case ARM::LDRSH_PRE:
1686 case ARM::LDRSH_POST:
1687 case ARM::LDRSB:
1688 case ARM::LDRSB_PRE:
1689 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1690 case ARM::LDRHTr:
1691 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1693 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1694 break;
1695 default:
1696 break;
1697 }
1698 }
1699
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1701 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1702
1703 if (type) {
1704 Inst.addOperand(MCOperand::CreateReg(0));
1705 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1706 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1708 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1709 Inst.addOperand(MCOperand::CreateImm(U));
1710 }
1711
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1712 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1713 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1714
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1715 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1716}
1717
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1718static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1719 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1720 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1721
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1722 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1723 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1724
1725 switch (mode) {
1726 case 0:
1727 mode = ARM_AM::da;
1728 break;
1729 case 1:
1730 mode = ARM_AM::ia;
1731 break;
1732 case 2:
1733 mode = ARM_AM::db;
1734 break;
1735 case 3:
1736 mode = ARM_AM::ib;
1737 break;
1738 }
1739
1740 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1742 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1743
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1744 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1745}
1746
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1747static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1748 unsigned Insn,
1749 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1750 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1751
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1752 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1753 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1754 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1755
1756 if (pred == 0xF) {
1757 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1758 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1759 Inst.setOpcode(ARM::RFEDA);
1760 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1761 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1762 Inst.setOpcode(ARM::RFEDA_UPD);
1763 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1764 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1765 Inst.setOpcode(ARM::RFEDB);
1766 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1767 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1768 Inst.setOpcode(ARM::RFEDB_UPD);
1769 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1770 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1771 Inst.setOpcode(ARM::RFEIA);
1772 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1773 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1774 Inst.setOpcode(ARM::RFEIA_UPD);
1775 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1776 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1777 Inst.setOpcode(ARM::RFEIB);
1778 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1779 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1780 Inst.setOpcode(ARM::RFEIB_UPD);
1781 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1782 case ARM::STMDA:
1783 Inst.setOpcode(ARM::SRSDA);
1784 break;
1785 case ARM::STMDA_UPD:
1786 Inst.setOpcode(ARM::SRSDA_UPD);
1787 break;
1788 case ARM::STMDB:
1789 Inst.setOpcode(ARM::SRSDB);
1790 break;
1791 case ARM::STMDB_UPD:
1792 Inst.setOpcode(ARM::SRSDB_UPD);
1793 break;
1794 case ARM::STMIA:
1795 Inst.setOpcode(ARM::SRSIA);
1796 break;
1797 case ARM::STMIA_UPD:
1798 Inst.setOpcode(ARM::SRSIA_UPD);
1799 break;
1800 case ARM::STMIB:
1801 Inst.setOpcode(ARM::SRSIB);
1802 break;
1803 case ARM::STMIB_UPD:
1804 Inst.setOpcode(ARM::SRSIB_UPD);
1805 break;
1806 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1807 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1808 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1809
1810 // For stores (which become SRS's, the only operand is the mode.
1811 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1812 Inst.addOperand(
1813 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1814 return S;
1815 }
1816
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1817 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1818 }
1819
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1821 return MCDisassembler::Fail;
1822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1823 return MCDisassembler::Fail; // Tied
1824 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1825 return MCDisassembler::Fail;
1826 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1827 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1828
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1829 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1830}
1831
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1832static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1833 uint64_t Address, const void *Decoder) {
1834 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1835 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1836 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1837 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1838
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1839 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1840
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1841 // imod == '01' --> UNPREDICTABLE
1842 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1843 // return failure here. The '01' imod value is unprintable, so there's
1844 // nothing useful we could do even if we returned UNPREDICTABLE.
1845
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1846 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1847
1848 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1849 Inst.setOpcode(ARM::CPS3p);
1850 Inst.addOperand(MCOperand::CreateImm(imod));
1851 Inst.addOperand(MCOperand::CreateImm(iflags));
1852 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1853 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1854 Inst.setOpcode(ARM::CPS2p);
1855 Inst.addOperand(MCOperand::CreateImm(imod));
1856 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1857 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1858 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1859 Inst.setOpcode(ARM::CPS1p);
1860 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1861 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1862 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1863 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1864 Inst.setOpcode(ARM::CPS1p);
1865 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1866 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1867 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1868
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1869 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1870}
1871
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1872static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1873 uint64_t Address, const void *Decoder) {
1874 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1875 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1876 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1877 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1878
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1879 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1880
1881 // imod == '01' --> UNPREDICTABLE
1882 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1883 // return failure here. The '01' imod value is unprintable, so there's
1884 // nothing useful we could do even if we returned UNPREDICTABLE.
1885
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1886 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1887
1888 if (imod && M) {
1889 Inst.setOpcode(ARM::t2CPS3p);
1890 Inst.addOperand(MCOperand::CreateImm(imod));
1891 Inst.addOperand(MCOperand::CreateImm(iflags));
1892 Inst.addOperand(MCOperand::CreateImm(mode));
1893 } else if (imod && !M) {
1894 Inst.setOpcode(ARM::t2CPS2p);
1895 Inst.addOperand(MCOperand::CreateImm(imod));
1896 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1897 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1898 } else if (!imod && M) {
1899 Inst.setOpcode(ARM::t2CPS1p);
1900 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1901 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1902 } else {
1903 // imod == '00' && M == '0' --> UNPREDICTABLE
1904 Inst.setOpcode(ARM::t2CPS1p);
1905 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1906 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1907 }
1908
1909 return S;
1910}
1911
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1912static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1913 uint64_t Address, const void *Decoder) {
1914 DecodeStatus S = MCDisassembler::Success;
1915
1916 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1917 unsigned imm = 0;
1918
1919 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1920 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1921 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1922 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1923
1924 if (Inst.getOpcode() == ARM::t2MOVTi16)
1925 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1926 return MCDisassembler::Fail;
1927 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1928 return MCDisassembler::Fail;
1929
1930 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1931 Inst.addOperand(MCOperand::CreateImm(imm));
1932
1933 return S;
1934}
1935
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1936static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1937 uint64_t Address, const void *Decoder) {
1938 DecodeStatus S = MCDisassembler::Success;
1939
1940 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1941 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1942 unsigned imm = 0;
1943
1944 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1945 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1946
1947 if (Inst.getOpcode() == ARM::MOVTi16)
1948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1949 return MCDisassembler::Fail;
1950 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1951 return MCDisassembler::Fail;
1952
1953 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1954 Inst.addOperand(MCOperand::CreateImm(imm));
1955
1956 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1957 return MCDisassembler::Fail;
1958
1959 return S;
1960}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1961
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1962static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1963 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1964 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1965
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1966 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1967 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1968 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1969 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1970 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1971
1972 if (pred == 0xF)
1973 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1974
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1975 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1976 return MCDisassembler::Fail;
1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1978 return MCDisassembler::Fail;
1979 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1980 return MCDisassembler::Fail;
1981 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1982 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1983
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1984 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1985 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1986
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1987 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1988}
1989
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1990static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1991 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1992 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1993
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1994 unsigned add = fieldFromInstruction32(Val, 12, 1);
1995 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1996 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1997
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1999 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2000
2001 if (!add) imm *= -1;
2002 if (imm == 0 && !add) imm = INT32_MIN;
2003 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2004 if (Rn == 15)
2005 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2006
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2007 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2008}
2009
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2010static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2011 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2012 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2013
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2014 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2015 unsigned U = fieldFromInstruction32(Val, 8, 1);
2016 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2017
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2018 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2019 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2020
2021 if (U)
2022 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2023 else
2024 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2025
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2026 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2027}
2028
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2029static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2030 uint64_t Address, const void *Decoder) {
2031 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2032}
2033
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2034static DecodeStatus
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame^]2035DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2036 uint64_t Address, const void *Decoder) {
2037 DecodeStatus S = MCDisassembler::Success;
2038 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) |
2039 (fieldFromInstruction32(Insn, 11, 1) << 18) |
2040 (fieldFromInstruction32(Insn, 13, 1) << 17) |
2041 (fieldFromInstruction32(Insn, 16, 6) << 11) |
2042 (fieldFromInstruction32(Insn, 26, 1) << 19);
2043 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2044 true, 4, Inst, Decoder))
2045 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2046 return S;
2047}
2048
2049static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2050DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2051 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2052 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2053
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2054 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2055 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2056
2057 if (pred == 0xF) {
2058 Inst.setOpcode(ARM::BLXi);
2059 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2060 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2061 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2062 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2063 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2064 }
2065
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2066 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2067 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2068 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2069 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2070 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2071
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2072 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2073}
2074
2075
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2076static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2077 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2078 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2079
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2080 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2081 unsigned align = fieldFromInstruction32(Val, 4, 2);
2082
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2084 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2085 if (!align)
2086 Inst.addOperand(MCOperand::CreateImm(0));
2087 else
2088 Inst.addOperand(MCOperand::CreateImm(4 << align));
2089
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2090 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2091}
2092
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2093static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2094 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2095 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2096
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2097 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2098 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2099 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2100 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2101 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2102 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2103
2104 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2105 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2106 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2107 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2108 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2109 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2110 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2111 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2112 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2113 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2114 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2115 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2116 return MCDisassembler::Fail;
2117 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2118 case ARM::VLD2b16:
2119 case ARM::VLD2b32:
2120 case ARM::VLD2b8:
2121 case ARM::VLD2b16wb_fixed:
2122 case ARM::VLD2b16wb_register:
2123 case ARM::VLD2b32wb_fixed:
2124 case ARM::VLD2b32wb_register:
2125 case ARM::VLD2b8wb_fixed:
2126 case ARM::VLD2b8wb_register:
2127 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2128 return MCDisassembler::Fail;
2129 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2130 default:
2131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2132 return MCDisassembler::Fail;
2133 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2134
2135 // Second output register
2136 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2137 case ARM::VLD3d8:
2138 case ARM::VLD3d16:
2139 case ARM::VLD3d32:
2140 case ARM::VLD3d8_UPD:
2141 case ARM::VLD3d16_UPD:
2142 case ARM::VLD3d32_UPD:
2143 case ARM::VLD4d8:
2144 case ARM::VLD4d16:
2145 case ARM::VLD4d32:
2146 case ARM::VLD4d8_UPD:
2147 case ARM::VLD4d16_UPD:
2148 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2149 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2150 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2151 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2152 case ARM::VLD3q8:
2153 case ARM::VLD3q16:
2154 case ARM::VLD3q32:
2155 case ARM::VLD3q8_UPD:
2156 case ARM::VLD3q16_UPD:
2157 case ARM::VLD3q32_UPD:
2158 case ARM::VLD4q8:
2159 case ARM::VLD4q16:
2160 case ARM::VLD4q32:
2161 case ARM::VLD4q8_UPD:
2162 case ARM::VLD4q16_UPD:
2163 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2164 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2165 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2166 default:
2167 break;
2168 }
2169
2170 // Third output register
2171 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2172 case ARM::VLD3d8:
2173 case ARM::VLD3d16:
2174 case ARM::VLD3d32:
2175 case ARM::VLD3d8_UPD:
2176 case ARM::VLD3d16_UPD:
2177 case ARM::VLD3d32_UPD:
2178 case ARM::VLD4d8:
2179 case ARM::VLD4d16:
2180 case ARM::VLD4d32:
2181 case ARM::VLD4d8_UPD:
2182 case ARM::VLD4d16_UPD:
2183 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2184 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2185 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2186 break;
2187 case ARM::VLD3q8:
2188 case ARM::VLD3q16:
2189 case ARM::VLD3q32:
2190 case ARM::VLD3q8_UPD:
2191 case ARM::VLD3q16_UPD:
2192 case ARM::VLD3q32_UPD:
2193 case ARM::VLD4q8:
2194 case ARM::VLD4q16:
2195 case ARM::VLD4q32:
2196 case ARM::VLD4q8_UPD:
2197 case ARM::VLD4q16_UPD:
2198 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2199 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2200 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2201 break;
2202 default:
2203 break;
2204 }
2205
2206 // Fourth output register
2207 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2208 case ARM::VLD4d8:
2209 case ARM::VLD4d16:
2210 case ARM::VLD4d32:
2211 case ARM::VLD4d8_UPD:
2212 case ARM::VLD4d16_UPD:
2213 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2215 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2216 break;
2217 case ARM::VLD4q8:
2218 case ARM::VLD4q16:
2219 case ARM::VLD4q32:
2220 case ARM::VLD4q8_UPD:
2221 case ARM::VLD4q16_UPD:
2222 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2224 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2225 break;
2226 default:
2227 break;
2228 }
2229
2230 // Writeback operand
2231 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2232 case ARM::VLD1d8wb_fixed:
2233 case ARM::VLD1d16wb_fixed:
2234 case ARM::VLD1d32wb_fixed:
2235 case ARM::VLD1d64wb_fixed:
2236 case ARM::VLD1d8wb_register:
2237 case ARM::VLD1d16wb_register:
2238 case ARM::VLD1d32wb_register:
2239 case ARM::VLD1d64wb_register:
2240 case ARM::VLD1q8wb_fixed:
2241 case ARM::VLD1q16wb_fixed:
2242 case ARM::VLD1q32wb_fixed:
2243 case ARM::VLD1q64wb_fixed:
2244 case ARM::VLD1q8wb_register:
2245 case ARM::VLD1q16wb_register:
2246 case ARM::VLD1q32wb_register:
2247 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2248 case ARM::VLD1d8Twb_fixed:
2249 case ARM::VLD1d8Twb_register:
2250 case ARM::VLD1d16Twb_fixed:
2251 case ARM::VLD1d16Twb_register:
2252 case ARM::VLD1d32Twb_fixed:
2253 case ARM::VLD1d32Twb_register:
2254 case ARM::VLD1d64Twb_fixed:
2255 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2256 case ARM::VLD1d8Qwb_fixed:
2257 case ARM::VLD1d8Qwb_register:
2258 case ARM::VLD1d16Qwb_fixed:
2259 case ARM::VLD1d16Qwb_register:
2260 case ARM::VLD1d32Qwb_fixed:
2261 case ARM::VLD1d32Qwb_register:
2262 case ARM::VLD1d64Qwb_fixed:
2263 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2264 case ARM::VLD2d8wb_fixed:
2265 case ARM::VLD2d16wb_fixed:
2266 case ARM::VLD2d32wb_fixed:
2267 case ARM::VLD2q8wb_fixed:
2268 case ARM::VLD2q16wb_fixed:
2269 case ARM::VLD2q32wb_fixed:
2270 case ARM::VLD2d8wb_register:
2271 case ARM::VLD2d16wb_register:
2272 case ARM::VLD2d32wb_register:
2273 case ARM::VLD2q8wb_register:
2274 case ARM::VLD2q16wb_register:
2275 case ARM::VLD2q32wb_register:
2276 case ARM::VLD2b8wb_fixed:
2277 case ARM::VLD2b16wb_fixed:
2278 case ARM::VLD2b32wb_fixed:
2279 case ARM::VLD2b8wb_register:
2280 case ARM::VLD2b16wb_register:
2281 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2282 Inst.addOperand(MCOperand::CreateImm(0));
2283 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2284 case ARM::VLD3d8_UPD:
2285 case ARM::VLD3d16_UPD:
2286 case ARM::VLD3d32_UPD:
2287 case ARM::VLD3q8_UPD:
2288 case ARM::VLD3q16_UPD:
2289 case ARM::VLD3q32_UPD:
2290 case ARM::VLD4d8_UPD:
2291 case ARM::VLD4d16_UPD:
2292 case ARM::VLD4d32_UPD:
2293 case ARM::VLD4q8_UPD:
2294 case ARM::VLD4q16_UPD:
2295 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2296 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2297 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2298 break;
2299 default:
2300 break;
2301 }
2302
2303 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2304 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2305 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2306
2307 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2308 switch (Inst.getOpcode()) {
2309 default:
2310 // The below have been updated to have explicit am6offset split
2311 // between fixed and register offset. For those instructions not
2312 // yet updated, we need to add an additional reg0 operand for the
2313 // fixed variant.
2314 //
2315 // The fixed offset encodes as Rm == 0xd, so we check for that.
2316 if (Rm == 0xd) {
2317 Inst.addOperand(MCOperand::CreateReg(0));
2318 break;
2319 }
2320 // Fall through to handle the register offset variant.
2321 case ARM::VLD1d8wb_fixed:
2322 case ARM::VLD1d16wb_fixed:
2323 case ARM::VLD1d32wb_fixed:
2324 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2325 case ARM::VLD1d8Twb_fixed:
2326 case ARM::VLD1d16Twb_fixed:
2327 case ARM::VLD1d32Twb_fixed:
2328 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2329 case ARM::VLD1d8Qwb_fixed:
2330 case ARM::VLD1d16Qwb_fixed:
2331 case ARM::VLD1d32Qwb_fixed:
2332 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2333 case ARM::VLD1d8wb_register:
2334 case ARM::VLD1d16wb_register:
2335 case ARM::VLD1d32wb_register:
2336 case ARM::VLD1d64wb_register:
2337 case ARM::VLD1q8wb_fixed:
2338 case ARM::VLD1q16wb_fixed:
2339 case ARM::VLD1q32wb_fixed:
2340 case ARM::VLD1q64wb_fixed:
2341 case ARM::VLD1q8wb_register:
2342 case ARM::VLD1q16wb_register:
2343 case ARM::VLD1q32wb_register:
2344 case ARM::VLD1q64wb_register:
2345 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2346 // variant encodes Rm == 0xf. Anything else is a register offset post-
2347 // increment and we need to add the register operand to the instruction.
2348 if (Rm != 0xD && Rm != 0xF &&
2349 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2350 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2351 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2352 case ARM::VLD2d8wb_fixed:
2353 case ARM::VLD2d16wb_fixed:
2354 case ARM::VLD2d32wb_fixed:
2355 case ARM::VLD2b8wb_fixed:
2356 case ARM::VLD2b16wb_fixed:
2357 case ARM::VLD2b32wb_fixed:
2358 case ARM::VLD2q8wb_fixed:
2359 case ARM::VLD2q16wb_fixed:
2360 case ARM::VLD2q32wb_fixed:
2361 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2362 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2363
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2364 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2365}
2366
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2367static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2368 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2369 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2370
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2371 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2372 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2373 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2374 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2375 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2376 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2377
2378 // Writeback Operand
2379 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2380 case ARM::VST1d8wb_fixed:
2381 case ARM::VST1d16wb_fixed:
2382 case ARM::VST1d32wb_fixed:
2383 case ARM::VST1d64wb_fixed:
2384 case ARM::VST1d8wb_register:
2385 case ARM::VST1d16wb_register:
2386 case ARM::VST1d32wb_register:
2387 case ARM::VST1d64wb_register:
2388 case ARM::VST1q8wb_fixed:
2389 case ARM::VST1q16wb_fixed:
2390 case ARM::VST1q32wb_fixed:
2391 case ARM::VST1q64wb_fixed:
2392 case ARM::VST1q8wb_register:
2393 case ARM::VST1q16wb_register:
2394 case ARM::VST1q32wb_register:
2395 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2396 case ARM::VST1d8Twb_fixed:
2397 case ARM::VST1d16Twb_fixed:
2398 case ARM::VST1d32Twb_fixed:
2399 case ARM::VST1d64Twb_fixed:
2400 case ARM::VST1d8Twb_register:
2401 case ARM::VST1d16Twb_register:
2402 case ARM::VST1d32Twb_register:
2403 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2404 case ARM::VST1d8Qwb_fixed:
2405 case ARM::VST1d16Qwb_fixed:
2406 case ARM::VST1d32Qwb_fixed:
2407 case ARM::VST1d64Qwb_fixed:
2408 case ARM::VST1d8Qwb_register:
2409 case ARM::VST1d16Qwb_register:
2410 case ARM::VST1d32Qwb_register:
2411 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2412 case ARM::VST2d8wb_fixed:
2413 case ARM::VST2d16wb_fixed:
2414 case ARM::VST2d32wb_fixed:
2415 case ARM::VST2d8wb_register:
2416 case ARM::VST2d16wb_register:
2417 case ARM::VST2d32wb_register:
2418 case ARM::VST2q8wb_fixed:
2419 case ARM::VST2q16wb_fixed:
2420 case ARM::VST2q32wb_fixed:
2421 case ARM::VST2q8wb_register:
2422 case ARM::VST2q16wb_register:
2423 case ARM::VST2q32wb_register:
2424 case ARM::VST2b8wb_fixed:
2425 case ARM::VST2b16wb_fixed:
2426 case ARM::VST2b32wb_fixed:
2427 case ARM::VST2b8wb_register:
2428 case ARM::VST2b16wb_register:
2429 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame]2430 if (Rm == 0xF)
2431 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2432 Inst.addOperand(MCOperand::CreateImm(0));
2433 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2434 case ARM::VST3d8_UPD:
2435 case ARM::VST3d16_UPD:
2436 case ARM::VST3d32_UPD:
2437 case ARM::VST3q8_UPD:
2438 case ARM::VST3q16_UPD:
2439 case ARM::VST3q32_UPD:
2440 case ARM::VST4d8_UPD:
2441 case ARM::VST4d16_UPD:
2442 case ARM::VST4d32_UPD:
2443 case ARM::VST4q8_UPD:
2444 case ARM::VST4q16_UPD:
2445 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2446 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2447 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2448 break;
2449 default:
2450 break;
2451 }
2452
2453 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2454 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2455 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2456
2457 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2458 switch (Inst.getOpcode()) {
2459 default:
2460 if (Rm == 0xD)
2461 Inst.addOperand(MCOperand::CreateReg(0));
2462 else if (Rm != 0xF) {
2463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2464 return MCDisassembler::Fail;
2465 }
2466 break;
2467 case ARM::VST1d8wb_fixed:
2468 case ARM::VST1d16wb_fixed:
2469 case ARM::VST1d32wb_fixed:
2470 case ARM::VST1d64wb_fixed:
2471 case ARM::VST1q8wb_fixed:
2472 case ARM::VST1q16wb_fixed:
2473 case ARM::VST1q32wb_fixed:
2474 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2475 case ARM::VST1d8Twb_fixed:
2476 case ARM::VST1d16Twb_fixed:
2477 case ARM::VST1d32Twb_fixed:
2478 case ARM::VST1d64Twb_fixed:
2479 case ARM::VST1d8Qwb_fixed:
2480 case ARM::VST1d16Qwb_fixed:
2481 case ARM::VST1d32Qwb_fixed:
2482 case ARM::VST1d64Qwb_fixed:
2483 case ARM::VST2d8wb_fixed:
2484 case ARM::VST2d16wb_fixed:
2485 case ARM::VST2d32wb_fixed:
2486 case ARM::VST2q8wb_fixed:
2487 case ARM::VST2q16wb_fixed:
2488 case ARM::VST2q32wb_fixed:
2489 case ARM::VST2b8wb_fixed:
2490 case ARM::VST2b16wb_fixed:
2491 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2492 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2493 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2494
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2495
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2496 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2497 switch (Inst.getOpcode()) {
2498 case ARM::VST1q16:
2499 case ARM::VST1q32:
2500 case ARM::VST1q64:
2501 case ARM::VST1q8:
2502 case ARM::VST1q16wb_fixed:
2503 case ARM::VST1q16wb_register:
2504 case ARM::VST1q32wb_fixed:
2505 case ARM::VST1q32wb_register:
2506 case ARM::VST1q64wb_fixed:
2507 case ARM::VST1q64wb_register:
2508 case ARM::VST1q8wb_fixed:
2509 case ARM::VST1q8wb_register:
2510 case ARM::VST2d16:
2511 case ARM::VST2d32:
2512 case ARM::VST2d8:
2513 case ARM::VST2d16wb_fixed:
2514 case ARM::VST2d16wb_register:
2515 case ARM::VST2d32wb_fixed:
2516 case ARM::VST2d32wb_register:
2517 case ARM::VST2d8wb_fixed:
2518 case ARM::VST2d8wb_register:
2519 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2520 return MCDisassembler::Fail;
2521 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2522 case ARM::VST2b16:
2523 case ARM::VST2b32:
2524 case ARM::VST2b8:
2525 case ARM::VST2b16wb_fixed:
2526 case ARM::VST2b16wb_register:
2527 case ARM::VST2b32wb_fixed:
2528 case ARM::VST2b32wb_register:
2529 case ARM::VST2b8wb_fixed:
2530 case ARM::VST2b8wb_register:
2531 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2532 return MCDisassembler::Fail;
2533 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2534 default:
2535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2536 return MCDisassembler::Fail;
2537 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2538
2539 // Second input register
2540 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2541 case ARM::VST3d8:
2542 case ARM::VST3d16:
2543 case ARM::VST3d32:
2544 case ARM::VST3d8_UPD:
2545 case ARM::VST3d16_UPD:
2546 case ARM::VST3d32_UPD:
2547 case ARM::VST4d8:
2548 case ARM::VST4d16:
2549 case ARM::VST4d32:
2550 case ARM::VST4d8_UPD:
2551 case ARM::VST4d16_UPD:
2552 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2553 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2554 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2555 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2556 case ARM::VST3q8:
2557 case ARM::VST3q16:
2558 case ARM::VST3q32:
2559 case ARM::VST3q8_UPD:
2560 case ARM::VST3q16_UPD:
2561 case ARM::VST3q32_UPD:
2562 case ARM::VST4q8:
2563 case ARM::VST4q16:
2564 case ARM::VST4q32:
2565 case ARM::VST4q8_UPD:
2566 case ARM::VST4q16_UPD:
2567 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2568 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2569 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2570 break;
2571 default:
2572 break;
2573 }
2574
2575 // Third input register
2576 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2577 case ARM::VST3d8:
2578 case ARM::VST3d16:
2579 case ARM::VST3d32:
2580 case ARM::VST3d8_UPD:
2581 case ARM::VST3d16_UPD:
2582 case ARM::VST3d32_UPD:
2583 case ARM::VST4d8:
2584 case ARM::VST4d16:
2585 case ARM::VST4d32:
2586 case ARM::VST4d8_UPD:
2587 case ARM::VST4d16_UPD:
2588 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2589 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2590 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2591 break;
2592 case ARM::VST3q8:
2593 case ARM::VST3q16:
2594 case ARM::VST3q32:
2595 case ARM::VST3q8_UPD:
2596 case ARM::VST3q16_UPD:
2597 case ARM::VST3q32_UPD:
2598 case ARM::VST4q8:
2599 case ARM::VST4q16:
2600 case ARM::VST4q32:
2601 case ARM::VST4q8_UPD:
2602 case ARM::VST4q16_UPD:
2603 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2604 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2605 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606 break;
2607 default:
2608 break;
2609 }
2610
2611 // Fourth input register
2612 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2613 case ARM::VST4d8:
2614 case ARM::VST4d16:
2615 case ARM::VST4d32:
2616 case ARM::VST4d8_UPD:
2617 case ARM::VST4d16_UPD:
2618 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2619 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2620 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2621 break;
2622 case ARM::VST4q8:
2623 case ARM::VST4q16:
2624 case ARM::VST4q32:
2625 case ARM::VST4q8_UPD:
2626 case ARM::VST4q16_UPD:
2627 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2628 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2629 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2630 break;
2631 default:
2632 break;
2633 }
2634
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2635 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2636}
2637
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2638static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2639 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2640 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2641
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2642 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2643 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2644 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2645 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2646 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2647 unsigned size = fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2648
2649 align *= (1 << size);
2650
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2651 switch (Inst.getOpcode()) {
2652 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2653 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2654 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2655 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2656 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2657 return MCDisassembler::Fail;
2658 break;
2659 default:
2660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2661 return MCDisassembler::Fail;
2662 break;
2663 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2664 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2666 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2667 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2668
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2670 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2671 Inst.addOperand(MCOperand::CreateImm(align));
2672
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2673 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2674 // variant encodes Rm == 0xf. Anything else is a register offset post-
2675 // increment and we need to add the register operand to the instruction.
2676 if (Rm != 0xD && Rm != 0xF &&
2677 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2678 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2679
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2680 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2681}
2682
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2683static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2685 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2686
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2687 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2688 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2689 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2690 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2691 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2692 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2693 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694 align *= 2*size;
2695
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2696 switch (Inst.getOpcode()) {
2697 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2698 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2699 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2700 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2701 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2702 return MCDisassembler::Fail;
2703 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2704 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2705 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2706 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2707 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2708 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2709 return MCDisassembler::Fail;
2710 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2711 default:
2712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2713 return MCDisassembler::Fail;
2714 break;
2715 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2716
2717 if (Rm != 0xF)
2718 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2719
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2721 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2722 Inst.addOperand(MCOperand::CreateImm(align));
2723
2724 if (Rm == 0xD)
2725 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2726 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2728 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2729 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2730
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2731 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2732 return MCDisassembler::Fail;
2733
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2734 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2735}
2736
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2737static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2738 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2739 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2740
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2741 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2742 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2743 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2744 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2745 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2746
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2748 return MCDisassembler::Fail;
2749 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2750 return MCDisassembler::Fail;
2751 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2752 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2753 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2755 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2756 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2759 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2760 Inst.addOperand(MCOperand::CreateImm(0));
2761
2762 if (Rm == 0xD)
2763 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2764 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2766 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2767 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2768
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2769 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2770}
2771
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2772static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2773 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2774 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2775
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2776 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2777 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2778 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2779 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2780 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2781 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2782 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2783
2784 if (size == 0x3) {
2785 size = 4;
2786 align = 16;
2787 } else {
2788 if (size == 2) {
2789 size = 1 << size;
2790 align *= 8;
2791 } else {
2792 size = 1 << size;
2793 align *= 4*size;
2794 }
2795 }
2796
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2797 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2798 return MCDisassembler::Fail;
2799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2800 return MCDisassembler::Fail;
2801 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2802 return MCDisassembler::Fail;
2803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2804 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2805 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2807 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2808 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2809
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2811 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812 Inst.addOperand(MCOperand::CreateImm(align));
2813
2814 if (Rm == 0xD)
2815 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2816 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2818 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2819 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2820
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2821 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2822}
2823
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2824static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2825DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2826 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2827 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2828
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2829 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2830 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2831 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2832 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2833 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2834 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2835 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2836 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2837
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2838 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2839 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2840 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2841 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2843 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2844 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2845
2846 Inst.addOperand(MCOperand::CreateImm(imm));
2847
2848 switch (Inst.getOpcode()) {
2849 case ARM::VORRiv4i16:
2850 case ARM::VORRiv2i32:
2851 case ARM::VBICiv4i16:
2852 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2853 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2854 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2855 break;
2856 case ARM::VORRiv8i16:
2857 case ARM::VORRiv4i32:
2858 case ARM::VBICiv8i16:
2859 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2860 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2861 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2862 break;
2863 default:
2864 break;
2865 }
2866
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2867 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2868}
2869
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2870static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2871 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2872 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2873
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2874 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2875 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2876 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2877 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2878 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2879
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2880 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2881 return MCDisassembler::Fail;
2882 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2883 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2884 Inst.addOperand(MCOperand::CreateImm(8 << size));
2885
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2886 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2887}
2888
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2889static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2890 uint64_t Address, const void *Decoder) {
2891 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2892 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893}
2894
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2895static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2896 uint64_t Address, const void *Decoder) {
2897 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2898 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2899}
2900
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2901static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2902 uint64_t Address, const void *Decoder) {
2903 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2904 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2905}
2906
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2907static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2908 uint64_t Address, const void *Decoder) {
2909 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2910 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2911}
2912
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2913static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2914 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2915 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2916
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2917 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2918 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2919 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2920 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2921 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2922 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2923 unsigned op = fieldFromInstruction32(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2924
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2925 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2926 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2927 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2928 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2929 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2930 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2931
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2932 switch (Inst.getOpcode()) {
2933 case ARM::VTBL2:
2934 case ARM::VTBX2:
2935 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2936 return MCDisassembler::Fail;
2937 break;
2938 default:
2939 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2940 return MCDisassembler::Fail;
2941 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2942
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2943 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2944 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2945
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2946 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2947}
2948
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2949static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2950 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2951 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2952
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2953 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2954 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2955
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2956 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2957 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2958
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2959 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2960 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2961 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2962 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2963 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2964 case ARM::tADDrSPi:
2965 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2966 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2967 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2968
2969 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2970 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2971}
2972
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2973static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2974 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame^]2975 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
2976 true, 2, Inst, Decoder))
2977 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2978 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2979}
2980
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2981static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2982 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame^]2983 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
2984 true, 4, Inst, Decoder))
2985 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2986 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2987}
2988
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2989static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2990 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame^]2991 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
2992 true, 2, Inst, Decoder))
2993 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2994 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2995}
2996
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2997static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2998 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2999 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3000
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3001 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3002 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
3003
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3004 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3005 return MCDisassembler::Fail;
3006 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3007 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3008
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3009 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3010}
3011
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3012static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3013 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3014 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3015
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3016 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3017 unsigned imm = fieldFromInstruction32(Val, 3, 5);
3018
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3019 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3020 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3021 Inst.addOperand(MCOperand::CreateImm(imm));
3022
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3023 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3024}
3025
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3026static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3027 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3028 unsigned imm = Val << 2;
3029
3030 Inst.addOperand(MCOperand::CreateImm(imm));
3031 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3032
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3033 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3034}
3035
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3036static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3037 uint64_t Address, const void *Decoder) {
3038 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3039 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3040
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3041 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3042}
3043
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3044static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3045 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3046 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3047
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3048 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3049 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3050 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3051
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3053 return MCDisassembler::Fail;
3054 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3055 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3056 Inst.addOperand(MCOperand::CreateImm(imm));
3057
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3058 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3059}
3060
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3061static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3062 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3063 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3064
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3065 switch (Inst.getOpcode()) {
3066 case ARM::t2PLDs:
3067 case ARM::t2PLDWs:
3068 case ARM::t2PLIs:
3069 break;
3070 default: {
3071 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3072 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3073 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3074 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3075 }
3076
3077 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3078 if (Rn == 0xF) {
3079 switch (Inst.getOpcode()) {
3080 case ARM::t2LDRBs:
3081 Inst.setOpcode(ARM::t2LDRBpci);
3082 break;
3083 case ARM::t2LDRHs:
3084 Inst.setOpcode(ARM::t2LDRHpci);
3085 break;
3086 case ARM::t2LDRSHs:
3087 Inst.setOpcode(ARM::t2LDRSHpci);
3088 break;
3089 case ARM::t2LDRSBs:
3090 Inst.setOpcode(ARM::t2LDRSBpci);
3091 break;
3092 case ARM::t2PLDs:
3093 Inst.setOpcode(ARM::t2PLDi12);
3094 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3095 break;
3096 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3097 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3098 }
3099
3100 int imm = fieldFromInstruction32(Insn, 0, 12);
3101 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3102 Inst.addOperand(MCOperand::CreateImm(imm));
3103
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3104 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3105 }
3106
3107 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3108 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3109 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3110 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3111 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3112
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3113 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3114}
3115
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3116static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3117 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3118 int imm = Val & 0xFF;
3119 if (!(Val & 0x100)) imm *= -1;
3120 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3121
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3122 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3123}
3124
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3125static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3126 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3127 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3128
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3129 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3130 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3131
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3133 return MCDisassembler::Fail;
3134 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3135 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3136
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3137 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3138}
3139
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3140static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3141 uint64_t Address, const void *Decoder) {
3142 DecodeStatus S = MCDisassembler::Success;
3143
3144 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3145 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3146
3147 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3148 return MCDisassembler::Fail;
3149
3150 Inst.addOperand(MCOperand::CreateImm(imm));
3151
3152 return S;
3153}
3154
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3155static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3156 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3157 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3158 if (Val == 0)
3159 imm = INT32_MIN;
3160 else if (!(Val & 0x100))
3161 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3162 Inst.addOperand(MCOperand::CreateImm(imm));
3163
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3164 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3165}
3166
3167
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3168static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3169 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3170 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3171
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3172 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3173 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3174
3175 // Some instructions always use an additive offset.
3176 switch (Inst.getOpcode()) {
3177 case ARM::t2LDRT:
3178 case ARM::t2LDRBT:
3179 case ARM::t2LDRHT:
3180 case ARM::t2LDRSBT:
3181 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3182 case ARM::t2STRT:
3183 case ARM::t2STRBT:
3184 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3185 imm |= 0x100;
3186 break;
3187 default:
3188 break;
3189 }
3190
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3192 return MCDisassembler::Fail;
3193 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3194 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3195
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3196 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3197}
3198
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3199static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3200 uint64_t Address, const void *Decoder) {
3201 DecodeStatus S = MCDisassembler::Success;
3202
3203 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3204 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3205 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3206 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3207 addr |= Rn << 9;
3208 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3209
3210 if (!load) {
3211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3212 return MCDisassembler::Fail;
3213 }
3214
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]3215 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3216 return MCDisassembler::Fail;
3217
3218 if (load) {
3219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3220 return MCDisassembler::Fail;
3221 }
3222
3223 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3224 return MCDisassembler::Fail;
3225
3226 return S;
3227}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3228
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3229static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3230 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3231 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3232
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3233 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3234 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3235
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3237 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3238 Inst.addOperand(MCOperand::CreateImm(imm));
3239
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3240 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3241}
3242
3243
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3244static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3245 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3246 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3247
3248 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3249 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3250 Inst.addOperand(MCOperand::CreateImm(imm));
3251
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3252 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3253}
3254
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3255static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3256 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3257 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3258
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3259 if (Inst.getOpcode() == ARM::tADDrSP) {
3260 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3261 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3262
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3264 return MCDisassembler::Fail;
3265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3266 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3267 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3268 } else if (Inst.getOpcode() == ARM::tADDspr) {
3269 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3270
3271 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3272 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3274 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3275 }
3276
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3277 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3278}
3279
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3280static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3281 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3282 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3283 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3284
3285 Inst.addOperand(MCOperand::CreateImm(imod));
3286 Inst.addOperand(MCOperand::CreateImm(flags));
3287
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3288 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3289}
3290
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3291static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3292 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3293 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3294 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3295 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3296
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3297 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3298 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3299 Inst.addOperand(MCOperand::CreateImm(add));
3300
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3301 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3302}
3303
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3304static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3305 uint64_t Address, const void *Decoder) {
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3306 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3307 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3308 true, 4, Inst, Decoder))
3309 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3310 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3311}
3312
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3313static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3314 uint64_t Address, const void *Decoder) {
3315 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3316 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3317
3318 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3319 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3320}
3321
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3322static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3323DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3324 uint64_t Address, const void *Decoder) {
3325 DecodeStatus S = MCDisassembler::Success;
3326
3327 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3328 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3329
3330 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3332 return MCDisassembler::Fail;
3333 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3334 return MCDisassembler::Fail;
3335 return S;
3336}
3337
3338static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3339DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3340 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3341 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3342
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3343 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3344 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3345 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3346 switch (opc) {
3347 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3348 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3349 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3350 Inst.setOpcode(ARM::t2DSB);
3351 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3352 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3353 Inst.setOpcode(ARM::t2DMB);
3354 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3355 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3356 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3357 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3358 }
3359
3360 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3361 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3362 }
3363
3364 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3365 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3366 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3367 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3368 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3369
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3370 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3371 return MCDisassembler::Fail;
3372 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3373 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3374
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3375 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3376}
3377
3378// Decode a shifted immediate operand. These basically consist
3379// of an 8-bit value, and a 4-bit directive that specifies either
3380// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3381static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3382 uint64_t Address, const void *Decoder) {
3383 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3384 if (ctrl == 0) {
3385 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3386 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3387 switch (byte) {
3388 case 0:
3389 Inst.addOperand(MCOperand::CreateImm(imm));
3390 break;
3391 case 1:
3392 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3393 break;
3394 case 2:
3395 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3396 break;
3397 case 3:
3398 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3399 (imm << 8) | imm));
3400 break;
3401 }
3402 } else {
3403 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3404 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3405 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3406 Inst.addOperand(MCOperand::CreateImm(imm));
3407 }
3408
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3409 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3410}
3411
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3412static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3413DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3414 uint64_t Address, const void *Decoder){
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame^]3415 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4,
3416 true, 2, Inst, Decoder))
3417 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3418 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3419}
3420
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3421static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3422 uint64_t Address, const void *Decoder){
Kevin Enderby09433032012-02-27 18:15:15 +0000[diff] [blame]3423 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3424 true, 4, Inst, Decoder))
3425 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3426 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3427}
3428
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3429static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3430 uint64_t Address, const void *Decoder) {
3431 switch (Val) {
3432 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3433 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3434 case 0xF: // SY
3435 case 0xE: // ST
3436 case 0xB: // ISH
3437 case 0xA: // ISHST
3438 case 0x7: // NSH
3439 case 0x6: // NSHST
3440 case 0x3: // OSH
3441 case 0x2: // OSHST
3442 break;
3443 }
3444
3445 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3446 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3447}
3448
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3449static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3450 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3451 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3452 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3453 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3454}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3455
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3456static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3457 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3458 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3459
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3460 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3461 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3462 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3463
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3464 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3465
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3467 return MCDisassembler::Fail;
3468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3469 return MCDisassembler::Fail;
3470 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3471 return MCDisassembler::Fail;
3472 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3473 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3474
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3475 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3476}
3477
3478
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3479static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3480 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3481 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3482
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3483 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3484 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3485 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3486 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3487
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3488 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3489 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3490
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3491 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3492 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3493
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3495 return MCDisassembler::Fail;
3496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3497 return MCDisassembler::Fail;
3498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3499 return MCDisassembler::Fail;
3500 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3501 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3502
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3503 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3504}
3505
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3506static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3507 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3508 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3509
3510 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3511 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3512 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3513 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3514 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3515 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3516
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3517 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3518
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3520 return MCDisassembler::Fail;
3521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3522 return MCDisassembler::Fail;
3523 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3524 return MCDisassembler::Fail;
3525 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3526 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3527
3528 return S;
3529}
3530
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3531static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3532 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3533 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3534
3535 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3536 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3537 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3538 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3539 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3540 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3541 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3542
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3543 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3544 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3545
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3546 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3547 return MCDisassembler::Fail;
3548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3549 return MCDisassembler::Fail;
3550 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3551 return MCDisassembler::Fail;
3552 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3553 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3554
3555 return S;
3556}
3557
3558
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3559static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3560 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3561 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3562
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3563 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3564 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3565 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3566 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3567 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3568 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3569
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3570 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3571
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3573 return MCDisassembler::Fail;
3574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3575 return MCDisassembler::Fail;
3576 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3577 return MCDisassembler::Fail;
3578 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3579 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3580
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3581 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3582}
3583
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3584static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3585 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3586 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3587
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3588 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3589 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3590 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3591 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3592 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3593 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3594
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3595 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3596
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3598 return MCDisassembler::Fail;
3599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3600 return MCDisassembler::Fail;
3601 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3602 return MCDisassembler::Fail;
3603 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3604 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3605
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3606 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3607}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3608
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3609static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3610 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3611 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3612
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3613 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3614 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3615 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3616 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3617 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3618
3619 unsigned align = 0;
3620 unsigned index = 0;
3621 switch (size) {
3622 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3623 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3624 case 0:
3625 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3626 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3627 index = fieldFromInstruction32(Insn, 5, 3);
3628 break;
3629 case 1:
3630 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3631 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3632 index = fieldFromInstruction32(Insn, 6, 2);
3633 if (fieldFromInstruction32(Insn, 4, 1))
3634 align = 2;
3635 break;
3636 case 2:
3637 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3638 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3639 index = fieldFromInstruction32(Insn, 7, 1);
3640 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3641 align = 4;
3642 }
3643
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3644 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3645 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3646 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3648 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3649 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3651 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3652 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3653 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3654 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3656 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3657 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3658 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3659 }
3660
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3662 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3663 Inst.addOperand(MCOperand::CreateImm(index));
3664
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3665 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3666}
3667
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3668static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3669 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3670 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3671
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3672 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3673 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3674 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3675 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3676 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3677
3678 unsigned align = 0;
3679 unsigned index = 0;
3680 switch (size) {
3681 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3682 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3683 case 0:
3684 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3685 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3686 index = fieldFromInstruction32(Insn, 5, 3);
3687 break;
3688 case 1:
3689 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3690 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3691 index = fieldFromInstruction32(Insn, 6, 2);
3692 if (fieldFromInstruction32(Insn, 4, 1))
3693 align = 2;
3694 break;
3695 case 2:
3696 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3697 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3698 index = fieldFromInstruction32(Insn, 7, 1);
3699 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3700 align = 4;
3701 }
3702
3703 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3705 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3706 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3708 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3709 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3710 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3711 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3713 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3714 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3715 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3716 }
3717
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3718 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3719 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3720 Inst.addOperand(MCOperand::CreateImm(index));
3721
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3722 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3723}
3724
3725
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3726static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3727 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3728 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3729
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3730 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3731 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3732 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3733 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3734 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3735
3736 unsigned align = 0;
3737 unsigned index = 0;
3738 unsigned inc = 1;
3739 switch (size) {
3740 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3741 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3742 case 0:
3743 index = fieldFromInstruction32(Insn, 5, 3);
3744 if (fieldFromInstruction32(Insn, 4, 1))
3745 align = 2;
3746 break;
3747 case 1:
3748 index = fieldFromInstruction32(Insn, 6, 2);
3749 if (fieldFromInstruction32(Insn, 4, 1))
3750 align = 4;
3751 if (fieldFromInstruction32(Insn, 5, 1))
3752 inc = 2;
3753 break;
3754 case 2:
3755 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3756 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3757 index = fieldFromInstruction32(Insn, 7, 1);
3758 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3759 align = 8;
3760 if (fieldFromInstruction32(Insn, 6, 1))
3761 inc = 2;
3762 break;
3763 }
3764
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3766 return MCDisassembler::Fail;
3767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3768 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3769 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3770 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3771 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3772 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3774 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3775 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3776 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3777 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3779 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3780 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3781 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3782 }
3783
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3785 return MCDisassembler::Fail;
3786 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3787 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3788 Inst.addOperand(MCOperand::CreateImm(index));
3789
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3790 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3791}
3792
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3793static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3794 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3795 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3796
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3797 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3798 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3799 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3800 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3801 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3802
3803 unsigned align = 0;
3804 unsigned index = 0;
3805 unsigned inc = 1;
3806 switch (size) {
3807 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3808 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3809 case 0:
3810 index = fieldFromInstruction32(Insn, 5, 3);
3811 if (fieldFromInstruction32(Insn, 4, 1))
3812 align = 2;
3813 break;
3814 case 1:
3815 index = fieldFromInstruction32(Insn, 6, 2);
3816 if (fieldFromInstruction32(Insn, 4, 1))
3817 align = 4;
3818 if (fieldFromInstruction32(Insn, 5, 1))
3819 inc = 2;
3820 break;
3821 case 2:
3822 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3823 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3824 index = fieldFromInstruction32(Insn, 7, 1);
3825 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3826 align = 8;
3827 if (fieldFromInstruction32(Insn, 6, 1))
3828 inc = 2;
3829 break;
3830 }
3831
3832 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3834 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3835 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3837 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3838 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3839 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3840 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3842 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3843 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3844 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3845 }
3846
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3847 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3848 return MCDisassembler::Fail;
3849 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3850 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3851 Inst.addOperand(MCOperand::CreateImm(index));
3852
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3853 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3854}
3855
3856
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3857static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3858 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3859 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3860
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3861 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3862 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3863 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3864 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3865 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3866
3867 unsigned align = 0;
3868 unsigned index = 0;
3869 unsigned inc = 1;
3870 switch (size) {
3871 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3872 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3873 case 0:
3874 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3875 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3876 index = fieldFromInstruction32(Insn, 5, 3);
3877 break;
3878 case 1:
3879 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3880 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3881 index = fieldFromInstruction32(Insn, 6, 2);
3882 if (fieldFromInstruction32(Insn, 5, 1))
3883 inc = 2;
3884 break;
3885 case 2:
3886 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3887 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3888 index = fieldFromInstruction32(Insn, 7, 1);
3889 if (fieldFromInstruction32(Insn, 6, 1))
3890 inc = 2;
3891 break;
3892 }
3893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3895 return MCDisassembler::Fail;
3896 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3897 return MCDisassembler::Fail;
3898 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3899 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3900
3901 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3902 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3903 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3904 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3906 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3907 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3908 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3909 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3911 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3912 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3913 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3914 }
3915
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3917 return MCDisassembler::Fail;
3918 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3919 return MCDisassembler::Fail;
3920 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3921 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3922 Inst.addOperand(MCOperand::CreateImm(index));
3923
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3924 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3925}
3926
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3927static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3928 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3929 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3930
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3931 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3932 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3933 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3934 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3935 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3936
3937 unsigned align = 0;
3938 unsigned index = 0;
3939 unsigned inc = 1;
3940 switch (size) {
3941 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3942 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3943 case 0:
3944 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3945 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3946 index = fieldFromInstruction32(Insn, 5, 3);
3947 break;
3948 case 1:
3949 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3950 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3951 index = fieldFromInstruction32(Insn, 6, 2);
3952 if (fieldFromInstruction32(Insn, 5, 1))
3953 inc = 2;
3954 break;
3955 case 2:
3956 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3957 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3958 index = fieldFromInstruction32(Insn, 7, 1);
3959 if (fieldFromInstruction32(Insn, 6, 1))
3960 inc = 2;
3961 break;
3962 }
3963
3964 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3966 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3967 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3969 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3970 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3971 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3972 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3973 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3974 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3975 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3976 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3977 }
3978
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3980 return MCDisassembler::Fail;
3981 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3982 return MCDisassembler::Fail;
3983 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3984 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3985 Inst.addOperand(MCOperand::CreateImm(index));
3986
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3987 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3988}
3989
3990
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3991static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3992 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3993 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3994
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3995 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3996 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3997 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3998 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3999 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4000
4001 unsigned align = 0;
4002 unsigned index = 0;
4003 unsigned inc = 1;
4004 switch (size) {
4005 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4006 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4007 case 0:
4008 if (fieldFromInstruction32(Insn, 4, 1))
4009 align = 4;
4010 index = fieldFromInstruction32(Insn, 5, 3);
4011 break;
4012 case 1:
4013 if (fieldFromInstruction32(Insn, 4, 1))
4014 align = 8;
4015 index = fieldFromInstruction32(Insn, 6, 2);
4016 if (fieldFromInstruction32(Insn, 5, 1))
4017 inc = 2;
4018 break;
4019 case 2:
4020 if (fieldFromInstruction32(Insn, 4, 2))
4021 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4022 index = fieldFromInstruction32(Insn, 7, 1);
4023 if (fieldFromInstruction32(Insn, 6, 1))
4024 inc = 2;
4025 break;
4026 }
4027
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4028 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4029 return MCDisassembler::Fail;
4030 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4031 return MCDisassembler::Fail;
4032 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4033 return MCDisassembler::Fail;
4034 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4035 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4036
4037 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4039 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4040 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4041 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4042 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4043 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4044 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4045 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4047 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4048 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4049 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4050 }
4051
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4052 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4053 return MCDisassembler::Fail;
4054 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4055 return MCDisassembler::Fail;
4056 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4057 return MCDisassembler::Fail;
4058 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4059 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4060 Inst.addOperand(MCOperand::CreateImm(index));
4061
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4062 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4063}
4064
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4065static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4066 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4067 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4068
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4069 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4070 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4071 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4072 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4073 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4074
4075 unsigned align = 0;
4076 unsigned index = 0;
4077 unsigned inc = 1;
4078 switch (size) {
4079 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4080 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4081 case 0:
4082 if (fieldFromInstruction32(Insn, 4, 1))
4083 align = 4;
4084 index = fieldFromInstruction32(Insn, 5, 3);
4085 break;
4086 case 1:
4087 if (fieldFromInstruction32(Insn, 4, 1))
4088 align = 8;
4089 index = fieldFromInstruction32(Insn, 6, 2);
4090 if (fieldFromInstruction32(Insn, 5, 1))
4091 inc = 2;
4092 break;
4093 case 2:
4094 if (fieldFromInstruction32(Insn, 4, 2))
4095 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4096 index = fieldFromInstruction32(Insn, 7, 1);
4097 if (fieldFromInstruction32(Insn, 6, 1))
4098 inc = 2;
4099 break;
4100 }
4101
4102 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4104 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4105 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4107 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4108 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4109 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4110 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4112 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4113 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4114 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4115 }
4116
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4117 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4118 return MCDisassembler::Fail;
4119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4120 return MCDisassembler::Fail;
4121 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4122 return MCDisassembler::Fail;
4123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4124 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4125 Inst.addOperand(MCOperand::CreateImm(index));
4126
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4127 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4128}
4129
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4130static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4131 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4132 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4133 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4134 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4135 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4136 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4137 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4138
4139 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4140 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4142 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4143 return MCDisassembler::Fail;
4144 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4145 return MCDisassembler::Fail;
4146 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4147 return MCDisassembler::Fail;
4148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4149 return MCDisassembler::Fail;
4150 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4151 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4152
4153 return S;
4154}
4155
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4156static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4157 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4158 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4159 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4160 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4161 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4162 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4163 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4164
4165 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4166 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4167
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4169 return MCDisassembler::Fail;
4170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4171 return MCDisassembler::Fail;
4172 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4173 return MCDisassembler::Fail;
4174 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4175 return MCDisassembler::Fail;
4176 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4177 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4178
4179 return S;
4180}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4181
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4182static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4183 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4184 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4185 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4186 // The InstPrinter needs to have the low bit of the predicate in
4187 // the mask operand to be able to print it properly.
4188 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4189
4190 if (pred == 0xF) {
4191 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4192 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4193 }
4194
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4195 if ((mask & 0xF) == 0) {
4196 // Preserve the high bit of the mask, which is the low bit of
4197 // the predicate.
4198 mask &= 0x10;
4199 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4200 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4201 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4202
4203 Inst.addOperand(MCOperand::CreateImm(pred));
4204 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4205 return S;
4206}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4207
4208static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4209DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4210 uint64_t Address, const void *Decoder) {
4211 DecodeStatus S = MCDisassembler::Success;
4212
4213 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4214 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4215 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4216 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4217 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4218 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4219 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4220 bool writeback = (W == 1) | (P == 0);
4221
4222 addr |= (U << 8) | (Rn << 9);
4223
4224 if (writeback && (Rn == Rt || Rn == Rt2))
4225 Check(S, MCDisassembler::SoftFail);
4226 if (Rt == Rt2)
4227 Check(S, MCDisassembler::SoftFail);
4228
4229 // Rt
4230 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 // Rt2
4233 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4234 return MCDisassembler::Fail;
4235 // Writeback operand
4236 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4237 return MCDisassembler::Fail;
4238 // addr
4239 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4240 return MCDisassembler::Fail;
4241
4242 return S;
4243}
4244
4245static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4246DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4247 uint64_t Address, const void *Decoder) {
4248 DecodeStatus S = MCDisassembler::Success;
4249
4250 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4251 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4252 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4253 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4254 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4255 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4256 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4257 bool writeback = (W == 1) | (P == 0);
4258
4259 addr |= (U << 8) | (Rn << 9);
4260
4261 if (writeback && (Rn == Rt || Rn == Rt2))
4262 Check(S, MCDisassembler::SoftFail);
4263
4264 // Writeback operand
4265 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4266 return MCDisassembler::Fail;
4267 // Rt
4268 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4269 return MCDisassembler::Fail;
4270 // Rt2
4271 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4272 return MCDisassembler::Fail;
4273 // addr
4274 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4275 return MCDisassembler::Fail;
4276
4277 return S;
4278}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4279
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4280static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4281 uint64_t Address, const void *Decoder) {
4282 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4283 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4284 if (sign1 != sign2) return MCDisassembler::Fail;
4285
4286 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4287 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4288 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4289 Val |= sign1 << 12;
4290 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4291
4292 return MCDisassembler::Success;
4293}
4294
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4295static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4296 uint64_t Address,
4297 const void *Decoder) {
4298 DecodeStatus S = MCDisassembler::Success;
4299
4300 // Shift of "asr #32" is not allowed in Thumb2 mode.
4301 if (Val == 0x20) S = MCDisassembler::SoftFail;
4302 Inst.addOperand(MCOperand::CreateImm(Val));
4303 return S;
4304}
4305
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4306static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4307 uint64_t Address, const void *Decoder) {
4308 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4309 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4310 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4311 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4312
4313 if (pred == 0xF)
4314 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4315
4316 DecodeStatus S = MCDisassembler::Success;
4317 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4318 return MCDisassembler::Fail;
4319 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4320 return MCDisassembler::Fail;
4321 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4322 return MCDisassembler::Fail;
4323 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4324 return MCDisassembler::Fail;
4325
4326 return S;
4327}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4328
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4329static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4330 uint64_t Address, const void *Decoder) {
4331 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4332 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4333 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4334 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4335 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4336 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4337
4338 DecodeStatus S = MCDisassembler::Success;
4339
4340 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4341 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4342 Inst.setOpcode(ARM::VMOVv2f32);
4343 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4344 }
4345
4346 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4347
4348 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4349 return MCDisassembler::Fail;
4350 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4351 return MCDisassembler::Fail;
4352 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4353
4354 return S;
4355}
4356
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4357static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4358 uint64_t Address, const void *Decoder) {
4359 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4360 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4361 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4362 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4363 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4364 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4365
4366 DecodeStatus S = MCDisassembler::Success;
4367
4368 // VMOVv4f32 is ambiguous with these decodings.
4369 if (!(imm & 0x38) && cmode == 0xF) {
4370 Inst.setOpcode(ARM::VMOVv4f32);
4371 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4372 }
4373
4374 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4375
4376 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4377 return MCDisassembler::Fail;
4378 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4379 return MCDisassembler::Fail;
4380 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4381
4382 return S;
4383}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4384
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4385static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4386 uint64_t Address, const void *Decoder) {
4387 DecodeStatus S = MCDisassembler::Success;
4388
4389 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4390 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4391 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4392 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4393 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4394
4395 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4396 S = MCDisassembler::SoftFail;
4397
4398 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4399 return MCDisassembler::Fail;
4400 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4401 return MCDisassembler::Fail;
4402 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4403 return MCDisassembler::Fail;
4404 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4405 return MCDisassembler::Fail;
4406 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4407 return MCDisassembler::Fail;
4408
4409 return S;
4410}
4411