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gerrit-public.fairphone.software / platform / external / llvm / 2d524b0765145f1c7888166c985a25452f16b2bc / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 80b2b235bed8efbbbcc2524e5ba76d916d82a3fd [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]13#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]14#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]15#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]16#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]17#include "llvm/MC/MCInstrDesc.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]20#include "llvm/MC/MCDisassembler.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]21#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]27#include <vector>
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]34 // Handles the condition code status of instructions in IT blocks
35 class ITStatus
36 {
37 public:
38 // Returns the condition code for instruction in IT block
39 unsigned getITCC() {
40 unsigned CC = ARMCC::AL;
41 if (instrInITBlock())
42 CC = ITStates.back();
43 return CC;
44 }
45
46 // Advances the IT block state to the next T or E
47 void advanceITState() {
48 ITStates.pop_back();
49 }
50
51 // Returns true if the current instruction is in an IT block
52 bool instrInITBlock() {
53 return !ITStates.empty();
54 }
55
56 // Returns true if current instruction is the last instruction in an IT block
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
59 }
60
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]66 unsigned CondBit0 = Firstcond & 1;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]67 unsigned NumTZ = CountTrailingZeros_32(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
73 if (T)
74 ITStates.push_back(CCBits);
75 else
76 ITStates.push_back(CCBits ^ 1);
77 }
78 ITStates.push_back(CCBits);
79 }
80
81 private:
82 std::vector<unsigned char> ITStates;
83 };
84}
85
86namespace {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]87/// ARMDisassembler - ARM disassembler for all ARM platforms.
88class ARMDisassembler : public MCDisassembler {
89public:
90 /// Constructor - Initializes the disassembler.
91 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]92 ARMDisassembler(const MCSubtargetInfo &STI) :
93 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]94 }
95
96 ~ARMDisassembler() {
97 }
98
99 /// getInstruction - See MCDisassembler.
100 DecodeStatus getInstruction(MCInst &instr,
101 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]102 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]103 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]104 raw_ostream &vStream,
105 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]106
107 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]108 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]109private:
110};
111
112/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
113class ThumbDisassembler : public MCDisassembler {
114public:
115 /// Constructor - Initializes the disassembler.
116 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]117 ThumbDisassembler(const MCSubtargetInfo &STI) :
118 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]119 }
120
121 ~ThumbDisassembler() {
122 }
123
124 /// getInstruction - See MCDisassembler.
125 DecodeStatus getInstruction(MCInst &instr,
126 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]127 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]128 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]129 raw_ostream &vStream,
130 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]131
132 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]133 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]134private:
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]135 mutable ITStatus ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]136 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]137 void UpdateThumbVFPPredicate(MCInst&) const;
138};
139}
140
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]141static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]142 switch (In) {
143 case MCDisassembler::Success:
144 // Out stays the same.
145 return true;
146 case MCDisassembler::SoftFail:
147 Out = In;
148 return true;
149 case MCDisassembler::Fail:
150 Out = In;
151 return false;
152 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]153 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]154}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]155
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]156
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157// Forward declare these because the autogenerated code will reference them.
158// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]159static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]161static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]162 unsigned RegNo, uint64_t Address,
163 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]164static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]165 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]166static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]167 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]168static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]170static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]172static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]174static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]176static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]177 unsigned RegNo,
178 uint64_t Address,
179 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]180static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]182static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]184static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]185 unsigned RegNo, uint64_t Address,
186 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]187
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]188static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]190static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]192static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]194static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]198static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]200
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]201static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]203static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]205static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]206 unsigned Insn,
207 uint64_t Address,
208 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]209static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]211static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]213static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]215static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
217
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]218static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]219 unsigned Insn,
220 uint64_t Adddress,
221 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]222static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]224static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]226static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]228static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]230static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]232static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]234static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]236static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]238static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]240static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]242static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]244static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]246static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]248static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]250static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]252static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]254static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]256static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]258static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]260static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]262static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]264static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]266static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]268static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]270static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]272static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]274static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]276static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]278static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]280static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]282static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]284static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]286static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]288static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]290static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]292static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]294static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]296static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]298static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]300static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]302static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]303 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]304static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]305 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]306static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]307 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]308static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]309 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]310static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]311 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]312static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]313 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]314static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]315 uint64_t Address, const void *Decoder);
316
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]317
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]318static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]319 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]320static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]321 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]322static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]323 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]324static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]325 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]326static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]328static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]330static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]332static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]333 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]334static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]335 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]336static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]338static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]340static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]341 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]342static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]343 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]344static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]346static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]348static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]349 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]350static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]351 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]352static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]353 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]354static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]356static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]358static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]359 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]360static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]361 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]362static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]363 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]364static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]366static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]368static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]369 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]370static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]371 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]372static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]373 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]374static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]375 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]376static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]377 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]378static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]379 uint64_t Address, const void *Decoder);
380
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]381static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]382 uint64_t Address, const void *Decoder);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]383static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]385#include "ARMGenDisassemblerTables.inc"
386#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]387#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]388
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]389static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
390 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]391}
392
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]393static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
394 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]395}
396
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]397const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]398 return instInfoARM;
399}
400
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]401const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]402 return instInfoARM;
403}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]404
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]405DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]406 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]407 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]408 raw_ostream &os,
409 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]410 CommentStream = &cs;
411
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]412 uint8_t bytes[4];
413
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]414 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
415 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
416
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]417 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]418 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
419 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]420 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]421 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]422
423 // Encoded as a small-endian 32-bit word in the stream.
424 uint32_t insn = (bytes[3] << 24) |
425 (bytes[2] << 16) |
426 (bytes[1] << 8) |
427 (bytes[0] << 0);
428
429 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]430 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]431 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]432 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]433 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]434 }
435
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]436 // VFP and NEON instructions, similarly, are shared between ARM
437 // and Thumb modes.
438 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]439 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]440 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]441 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]442 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]443 }
444
445 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]446 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]447 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]448 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]449 // Add a fake predicate operand, because we share these instruction
450 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]451 if (!DecodePredicateOperand(MI, 0xE, Address, this))
452 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]453 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]454 }
455
456 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]457 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]458 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]459 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]460 // Add a fake predicate operand, because we share these instruction
461 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]462 if (!DecodePredicateOperand(MI, 0xE, Address, this))
463 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]464 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]465 }
466
467 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]468 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]469 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]470 Size = 4;
471 // Add a fake predicate operand, because we share these instruction
472 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]473 if (!DecodePredicateOperand(MI, 0xE, Address, this))
474 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]475 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]476 }
477
478 MI.clear();
479
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]480 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]481 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]482}
483
484namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]485extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]486}
487
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]488/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
489/// immediate Value in the MCInst. The immediate Value has had any PC
490/// adjustment made by the caller. If the instruction is a branch instruction
491/// then isBranch is true, else false. If the getOpInfo() function was set as
492/// part of the setupForSymbolicDisassembly() call then that function is called
493/// to get any symbolic information at the Address for this instruction. If
494/// that returns non-zero then the symbolic information it returns is used to
495/// create an MCExpr and that is added as an operand to the MCInst. If
496/// getOpInfo() returns zero and isBranch is true then a symbol look up for
497/// Value is done and if a symbol is found an MCExpr is created with that, else
498/// an MCExpr with Value is created. This function returns true if it adds an
499/// operand to the MCInst and false otherwise.
500static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
501 bool isBranch, uint64_t InstSize,
502 MCInst &MI, const void *Decoder) {
503 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
504 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]505 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]506 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]507 SymbolicOp.Value = Value;
508 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]509
510 if (!getOpInfo ||
511 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
512 // Clear SymbolicOp.Value from above and also all other fields.
513 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
514 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
515 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]516 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]517 uint64_t ReferenceType;
518 if (isBranch)
519 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
520 else
521 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
522 const char *ReferenceName;
523 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
524 &ReferenceName);
525 if (Name) {
526 SymbolicOp.AddSymbol.Name = Name;
527 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]528 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]529 // For branches always create an MCExpr so it gets printed as hex address.
530 else if (isBranch) {
531 SymbolicOp.Value = Value;
532 }
533 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
534 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
535 if (!Name && !isBranch)
536 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]537 }
538
539 MCContext *Ctx = Dis->getMCContext();
540 const MCExpr *Add = NULL;
541 if (SymbolicOp.AddSymbol.Present) {
542 if (SymbolicOp.AddSymbol.Name) {
543 StringRef Name(SymbolicOp.AddSymbol.Name);
544 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
545 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
546 } else {
547 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
548 }
549 }
550
551 const MCExpr *Sub = NULL;
552 if (SymbolicOp.SubtractSymbol.Present) {
553 if (SymbolicOp.SubtractSymbol.Name) {
554 StringRef Name(SymbolicOp.SubtractSymbol.Name);
555 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
556 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
557 } else {
558 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
559 }
560 }
561
562 const MCExpr *Off = NULL;
563 if (SymbolicOp.Value != 0)
564 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
565
566 const MCExpr *Expr;
567 if (Sub) {
568 const MCExpr *LHS;
569 if (Add)
570 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
571 else
572 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
573 if (Off != 0)
574 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
575 else
576 Expr = LHS;
577 } else if (Add) {
578 if (Off != 0)
579 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
580 else
581 Expr = Add;
582 } else {
583 if (Off != 0)
584 Expr = Off;
585 else
586 Expr = MCConstantExpr::Create(0, *Ctx);
587 }
588
589 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
590 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
591 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
592 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
593 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
594 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]595 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]596 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]597
598 return true;
599}
600
601/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
602/// referenced by a load instruction with the base register that is the Pc.
603/// These can often be values in a literal pool near the Address of the
604/// instruction. The Address of the instruction and its immediate Value are
605/// used as a possible literal pool entry. The SymbolLookUp call back will
606/// return the name of a symbol referenced by the the literal pool's entry if
607/// the referenced address is that of a symbol. Or it will return a pointer to
608/// a literal 'C' string if the referenced address of the literal pool's entry
609/// is an address into a section with 'C' string literals.
610static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]611 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]612 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
613 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
614 if (SymbolLookUp) {
615 void *DisInfo = Dis->getDisInfoBlock();
616 uint64_t ReferenceType;
617 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
618 const char *ReferenceName;
619 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
620 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
621 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
622 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
623 }
624}
625
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]626// Thumb1 instructions don't have explicit S bits. Rather, they
627// implicitly set CPSR. Since it's not represented in the encoding, the
628// auto-generated decoder won't inject the CPSR operand. We need to fix
629// that as a post-pass.
630static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
631 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]632 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]633 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]634 for (unsigned i = 0; i < NumOps; ++i, ++I) {
635 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]636 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]637 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]638 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
639 return;
640 }
641 }
642
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]644}
645
646// Most Thumb instructions don't have explicit predicates in the
647// encoding, but rather get their predicates from IT context. We need
648// to fix up the predicate operands using this context information as a
649// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]650MCDisassembler::DecodeStatus
651ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]652 MCDisassembler::DecodeStatus S = Success;
653
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]654 // A few instructions actually have predicates encoded in them. Don't
655 // try to overwrite it if we're seeing one of those.
656 switch (MI.getOpcode()) {
657 case ARM::tBcc:
658 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]659 case ARM::tCBZ:
660 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]661 case ARM::tCPS:
662 case ARM::t2CPS3p:
663 case ARM::t2CPS2p:
664 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]665 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]666 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]667 // Some instructions (mostly conditional branches) are not
668 // allowed in IT blocks.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]669 if (ITBlock.instrInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]670 S = SoftFail;
671 else
672 return Success;
673 break;
674 case ARM::tB:
675 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]676 case ARM::t2TBB:
677 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]678 // Some instructions (mostly unconditional branches) can
679 // only appears at the end of, or outside of, an IT.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]680 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]681 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]682 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]683 default:
684 break;
685 }
686
687 // If we're in an IT block, base the predicate on that. Otherwise,
688 // assume a predicate of AL.
689 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]690 CC = ITBlock.getITCC();
691 if (CC == 0xF)
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]692 CC = ARMCC::AL;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]693 if (ITBlock.instrInITBlock())
694 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]695
696 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]697 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]698 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]699 for (unsigned i = 0; i < NumOps; ++i, ++I) {
700 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]701 if (OpInfo[i].isPredicate()) {
702 I = MI.insert(I, MCOperand::CreateImm(CC));
703 ++I;
704 if (CC == ARMCC::AL)
705 MI.insert(I, MCOperand::CreateReg(0));
706 else
707 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]708 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]709 }
710 }
711
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]712 I = MI.insert(I, MCOperand::CreateImm(CC));
713 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]714 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]715 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]716 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]717 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]718
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]719 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]720}
721
722// Thumb VFP instructions are a special case. Because we share their
723// encodings between ARM and Thumb modes, and they are predicable in ARM
724// mode, the auto-generated decoder will give them an (incorrect)
725// predicate operand. We need to rewrite these operands based on the IT
726// context as a post-pass.
727void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
728 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]729 CC = ITBlock.getITCC();
730 if (ITBlock.instrInITBlock())
731 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]732
733 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
734 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]735 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
736 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]737 if (OpInfo[i].isPredicate() ) {
738 I->setImm(CC);
739 ++I;
740 if (CC == ARMCC::AL)
741 I->setReg(0);
742 else
743 I->setReg(ARM::CPSR);
744 return;
745 }
746 }
747}
748
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]749DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]750 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]751 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]752 raw_ostream &os,
753 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]754 CommentStream = &cs;
755
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]756 uint8_t bytes[4];
757
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]758 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
759 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
760
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]761 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]762 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
763 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]764 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]765 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]766
767 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]768 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]769 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]770 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]771 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]772 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]773 }
774
775 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]776 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]777 if (result) {
778 Size = 2;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]779 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]780 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]781 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]782 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 }
784
785 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]786 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]787 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]788 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]789
790 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
791 // the Thumb predicate.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]792 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]793 result = MCDisassembler::SoftFail;
794
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]795 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]796
797 // If we find an IT instruction, we need to parse its condition
798 // code and mask operands so that we can apply them correctly
799 // to the subsequent instructions.
800 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]801
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]802 unsigned Firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]803 unsigned Mask = MI.getOperand(1).getImm();
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]804 ITBlock.setITState(Firstcond, Mask);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]805 }
806
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]807 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]808 }
809
810 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]811 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
812 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]813 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]814 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]815
816 uint32_t insn32 = (bytes[3] << 8) |
817 (bytes[2] << 0) |
818 (bytes[1] << 24) |
819 (bytes[0] << 16);
820 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]821 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]822 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]823 Size = 4;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]824 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]825 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]826 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]827 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]828 }
829
830 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]831 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]832 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]834 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]835 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836 }
837
838 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]839 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]840 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]841 Size = 4;
842 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]843 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]844 }
845
846 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]847 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]848 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]849 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]850 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]851 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]852 }
853
854 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
855 MI.clear();
856 uint32_t NEONLdStInsn = insn32;
857 NEONLdStInsn &= 0xF0FFFFFF;
858 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]859 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]860 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]861 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]862 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]863 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]864 }
865 }
866
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]867 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]868 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]869 uint32_t NEONDataInsn = insn32;
870 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
871 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
872 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]873 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]874 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]875 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]876 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]877 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]878 }
879 }
880
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]881 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]882 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]883}
884
885
886extern "C" void LLVMInitializeARMDisassembler() {
887 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
888 createARMDisassembler);
889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
890 createThumbDisassembler);
891}
892
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]893static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]894 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
895 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
896 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
897 ARM::R12, ARM::SP, ARM::LR, ARM::PC
898};
899
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]900static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]901 uint64_t Address, const void *Decoder) {
902 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]903 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]904
905 unsigned Register = GPRDecoderTable[RegNo];
906 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]907 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908}
909
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]910static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]911DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]912 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]913 DecodeStatus S = MCDisassembler::Success;
914
915 if (RegNo == 15)
916 S = MCDisassembler::SoftFail;
917
918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
919
920 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]921}
922
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]923static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]924 uint64_t Address, const void *Decoder) {
925 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]926 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
928}
929
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]930static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]931 uint64_t Address, const void *Decoder) {
932 unsigned Register = 0;
933 switch (RegNo) {
934 case 0:
935 Register = ARM::R0;
936 break;
937 case 1:
938 Register = ARM::R1;
939 break;
940 case 2:
941 Register = ARM::R2;
942 break;
943 case 3:
944 Register = ARM::R3;
945 break;
946 case 9:
947 Register = ARM::R9;
948 break;
949 case 12:
950 Register = ARM::R12;
951 break;
952 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]953 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]954 }
955
956 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]957 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958}
959
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]960static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]961 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
964}
965
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]966static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
968 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
969 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
970 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
971 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
972 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
973 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
974 ARM::S28, ARM::S29, ARM::S30, ARM::S31
975};
976
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]977static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978 uint64_t Address, const void *Decoder) {
979 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]980 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]981
982 unsigned Register = SPRDecoderTable[RegNo];
983 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]984 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]985}
986
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]987static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]988 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
989 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
990 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
991 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
992 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
993 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
994 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
995 ARM::D28, ARM::D29, ARM::D30, ARM::D31
996};
997
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]998static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999 uint64_t Address, const void *Decoder) {
1000 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1001 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002
1003 unsigned Register = DPRDecoderTable[RegNo];
1004 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1005 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1006}
1007
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1008static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1009 uint64_t Address, const void *Decoder) {
1010 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1011 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1013}
1014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1015static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1016DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1017 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1018 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1019 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1021}
1022
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1023static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1028};
1029
1030
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1031static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1032 uint64_t Address, const void *Decoder) {
1033 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1034 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1035 RegNo >>= 1;
1036
1037 unsigned Register = QPRDecoderTable[RegNo];
1038 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1039 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1040}
1041
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1042static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1048 ARM::Q15
1049};
1050
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1051static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1052 uint64_t Address, const void *Decoder) {
1053 if (RegNo > 30)
1054 return MCDisassembler::Fail;
1055
1056 unsigned Register = DPairDecoderTable[RegNo];
1057 Inst.addOperand(MCOperand::CreateReg(Register));
1058 return MCDisassembler::Success;
1059}
1060
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1061static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1069 ARM::D28_D30, ARM::D29_D31
1070};
1071
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1072static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1073 unsigned RegNo,
1074 uint64_t Address,
1075 const void *Decoder) {
1076 if (RegNo > 29)
1077 return MCDisassembler::Fail;
1078
1079 unsigned Register = DPairSpacedDecoderTable[RegNo];
1080 Inst.addOperand(MCOperand::CreateReg(Register));
1081 return MCDisassembler::Success;
1082}
1083
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1084static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1085 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1086 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1087 // AL predicate is not allowed on Thumb1 branches.
1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1089 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1090 Inst.addOperand(MCOperand::CreateImm(Val));
1091 if (Val == ARMCC::AL) {
1092 Inst.addOperand(MCOperand::CreateReg(0));
1093 } else
1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1095 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1096}
1097
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1098static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1099 uint64_t Address, const void *Decoder) {
1100 if (Val)
1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1102 else
1103 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1104 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1105}
1106
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1107static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1108 uint64_t Address, const void *Decoder) {
1109 uint32_t imm = Val & 0xFF;
1110 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1113 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1114}
1115
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1116static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1117 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1118 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1119
1120 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1121 unsigned type = fieldFromInstruction32(Val, 5, 2);
1122 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1123
1124 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1126 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1127
1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1129 switch (type) {
1130 case 0:
1131 Shift = ARM_AM::lsl;
1132 break;
1133 case 1:
1134 Shift = ARM_AM::lsr;
1135 break;
1136 case 2:
1137 Shift = ARM_AM::asr;
1138 break;
1139 case 3:
1140 Shift = ARM_AM::ror;
1141 break;
1142 }
1143
1144 if (Shift == ARM_AM::ror && imm == 0)
1145 Shift = ARM_AM::rrx;
1146
1147 unsigned Op = Shift | (imm << 3);
1148 Inst.addOperand(MCOperand::CreateImm(Op));
1149
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1150 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1151}
1152
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1153static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1154 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1155 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1156
1157 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1158 unsigned type = fieldFromInstruction32(Val, 5, 2);
1159 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1160
1161 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1163 return MCDisassembler::Fail;
1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1165 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1166
1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1168 switch (type) {
1169 case 0:
1170 Shift = ARM_AM::lsl;
1171 break;
1172 case 1:
1173 Shift = ARM_AM::lsr;
1174 break;
1175 case 2:
1176 Shift = ARM_AM::asr;
1177 break;
1178 case 3:
1179 Shift = ARM_AM::ror;
1180 break;
1181 }
1182
1183 Inst.addOperand(MCOperand::CreateImm(Shift));
1184
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1185 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1186}
1187
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1188static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1189 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1190 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1191
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1192 bool writebackLoad = false;
1193 unsigned writebackReg = 0;
1194 switch (Inst.getOpcode()) {
1195 default:
1196 break;
1197 case ARM::LDMIA_UPD:
1198 case ARM::LDMDB_UPD:
1199 case ARM::LDMIB_UPD:
1200 case ARM::LDMDA_UPD:
1201 case ARM::t2LDMIA_UPD:
1202 case ARM::t2LDMDB_UPD:
1203 writebackLoad = true;
1204 writebackReg = Inst.getOperand(0).getReg();
1205 break;
1206 }
1207
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1208 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1210 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1211 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1213 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1214 // Writeback not allowed if Rn is in the target list.
1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1216 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1217 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1218 }
1219
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1220 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1221}
1222
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1223static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1225 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1226
Silviu Barangab422d0b2012-05-03 16:38:40 +0000[diff] [blame]1227 unsigned Vd = fieldFromInstruction32(Val, 8, 5);
1228 unsigned regs = fieldFromInstruction32(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1231 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1232 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1234 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1235 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1236
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1237 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238}
1239
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1240static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1241 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1242 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1243
Silviu Barangab422d0b2012-05-03 16:38:40 +0000[diff] [blame]1244 unsigned Vd = fieldFromInstruction32(Val, 8, 5);
1245 unsigned regs = fieldFromInstruction32(Val, 0, 8);
1246
1247 regs = regs >> 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1248
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1249 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1250 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1251 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1252 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1253 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1254 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1256 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1257}
1258
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1259static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1260 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1261 // This operand encodes a mask of contiguous zeros between a specified MSB
1262 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1263 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1264 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1265 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1266 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1267 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1268
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1269 DecodeStatus S = MCDisassembler::Success;
1270 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1271
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1272 uint32_t msb_mask = 0xFFFFFFFF;
1273 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1274 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1275
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1276 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1277 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1278}
1279
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1280static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1281 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1282 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1283
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1284 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1285 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1286 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1287 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1288 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1289 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1290
1291 switch (Inst.getOpcode()) {
1292 case ARM::LDC_OFFSET:
1293 case ARM::LDC_PRE:
1294 case ARM::LDC_POST:
1295 case ARM::LDC_OPTION:
1296 case ARM::LDCL_OFFSET:
1297 case ARM::LDCL_PRE:
1298 case ARM::LDCL_POST:
1299 case ARM::LDCL_OPTION:
1300 case ARM::STC_OFFSET:
1301 case ARM::STC_PRE:
1302 case ARM::STC_POST:
1303 case ARM::STC_OPTION:
1304 case ARM::STCL_OFFSET:
1305 case ARM::STCL_PRE:
1306 case ARM::STCL_POST:
1307 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1308 case ARM::t2LDC_OFFSET:
1309 case ARM::t2LDC_PRE:
1310 case ARM::t2LDC_POST:
1311 case ARM::t2LDC_OPTION:
1312 case ARM::t2LDCL_OFFSET:
1313 case ARM::t2LDCL_PRE:
1314 case ARM::t2LDCL_POST:
1315 case ARM::t2LDCL_OPTION:
1316 case ARM::t2STC_OFFSET:
1317 case ARM::t2STC_PRE:
1318 case ARM::t2STC_POST:
1319 case ARM::t2STC_OPTION:
1320 case ARM::t2STCL_OFFSET:
1321 case ARM::t2STCL_PRE:
1322 case ARM::t2STCL_POST:
1323 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1324 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1325 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1326 break;
1327 default:
1328 break;
1329 }
1330
1331 Inst.addOperand(MCOperand::CreateImm(coproc));
1332 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1334 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1335
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1336 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1337 case ARM::t2LDC2_OFFSET:
1338 case ARM::t2LDC2L_OFFSET:
1339 case ARM::t2LDC2_PRE:
1340 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1341 case ARM::t2STC2_OFFSET:
1342 case ARM::t2STC2L_OFFSET:
1343 case ARM::t2STC2_PRE:
1344 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1345 case ARM::LDC2_OFFSET:
1346 case ARM::LDC2L_OFFSET:
1347 case ARM::LDC2_PRE:
1348 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1349 case ARM::STC2_OFFSET:
1350 case ARM::STC2L_OFFSET:
1351 case ARM::STC2_PRE:
1352 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1353 case ARM::t2LDC_OFFSET:
1354 case ARM::t2LDCL_OFFSET:
1355 case ARM::t2LDC_PRE:
1356 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1357 case ARM::t2STC_OFFSET:
1358 case ARM::t2STCL_OFFSET:
1359 case ARM::t2STC_PRE:
1360 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1361 case ARM::LDC_OFFSET:
1362 case ARM::LDCL_OFFSET:
1363 case ARM::LDC_PRE:
1364 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1365 case ARM::STC_OFFSET:
1366 case ARM::STCL_OFFSET:
1367 case ARM::STC_PRE:
1368 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1369 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1370 Inst.addOperand(MCOperand::CreateImm(imm));
1371 break;
1372 case ARM::t2LDC2_POST:
1373 case ARM::t2LDC2L_POST:
1374 case ARM::t2STC2_POST:
1375 case ARM::t2STC2L_POST:
1376 case ARM::LDC2_POST:
1377 case ARM::LDC2L_POST:
1378 case ARM::STC2_POST:
1379 case ARM::STC2L_POST:
1380 case ARM::t2LDC_POST:
1381 case ARM::t2LDCL_POST:
1382 case ARM::t2STC_POST:
1383 case ARM::t2STCL_POST:
1384 case ARM::LDC_POST:
1385 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1386 case ARM::STC_POST:
1387 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1388 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1389 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1390 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1391 // The 'option' variant doesn't encode 'U' in the immediate since
1392 // the immediate is unsigned [0,255].
1393 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1394 break;
1395 }
1396
1397 switch (Inst.getOpcode()) {
1398 case ARM::LDC_OFFSET:
1399 case ARM::LDC_PRE:
1400 case ARM::LDC_POST:
1401 case ARM::LDC_OPTION:
1402 case ARM::LDCL_OFFSET:
1403 case ARM::LDCL_PRE:
1404 case ARM::LDCL_POST:
1405 case ARM::LDCL_OPTION:
1406 case ARM::STC_OFFSET:
1407 case ARM::STC_PRE:
1408 case ARM::STC_POST:
1409 case ARM::STC_OPTION:
1410 case ARM::STCL_OFFSET:
1411 case ARM::STCL_PRE:
1412 case ARM::STCL_POST:
1413 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1414 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1415 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1416 break;
1417 default:
1418 break;
1419 }
1420
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1421 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1422}
1423
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1424static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1425DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1426 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1427 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1428
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1429 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1430 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1431 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1432 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1433 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1434 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1435 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1436 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1437
1438 // On stores, the writeback operand precedes Rt.
1439 switch (Inst.getOpcode()) {
1440 case ARM::STR_POST_IMM:
1441 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1442 case ARM::STRB_POST_IMM:
1443 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1444 case ARM::STRT_POST_REG:
1445 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1446 case ARM::STRBT_POST_REG:
1447 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1449 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1450 break;
1451 default:
1452 break;
1453 }
1454
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1456 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1457
1458 // On loads, the writeback operand comes after Rt.
1459 switch (Inst.getOpcode()) {
1460 case ARM::LDR_POST_IMM:
1461 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1462 case ARM::LDRB_POST_IMM:
1463 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1464 case ARM::LDRBT_POST_REG:
1465 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1466 case ARM::LDRT_POST_REG:
1467 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1469 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1470 break;
1471 default:
1472 break;
1473 }
1474
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1476 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1477
1478 ARM_AM::AddrOpc Op = ARM_AM::add;
1479 if (!fieldFromInstruction32(Insn, 23, 1))
1480 Op = ARM_AM::sub;
1481
1482 bool writeback = (P == 0) || (W == 1);
1483 unsigned idx_mode = 0;
1484 if (P && writeback)
1485 idx_mode = ARMII::IndexModePre;
1486 else if (!P && writeback)
1487 idx_mode = ARMII::IndexModePost;
1488
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1489 if (writeback && (Rn == 15 || Rn == Rt))
1490 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1491
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1492 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1493 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1494 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1495 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1496 switch( fieldFromInstruction32(Insn, 5, 2)) {
1497 case 0:
1498 Opc = ARM_AM::lsl;
1499 break;
1500 case 1:
1501 Opc = ARM_AM::lsr;
1502 break;
1503 case 2:
1504 Opc = ARM_AM::asr;
1505 break;
1506 case 3:
1507 Opc = ARM_AM::ror;
1508 break;
1509 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1510 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1511 }
1512 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1513 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1514
1515 Inst.addOperand(MCOperand::CreateImm(imm));
1516 } else {
1517 Inst.addOperand(MCOperand::CreateReg(0));
1518 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1519 Inst.addOperand(MCOperand::CreateImm(tmp));
1520 }
1521
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1522 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1523 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1524
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1525 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1526}
1527
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1528static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1529 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1530 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1531
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1532 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1533 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1534 unsigned type = fieldFromInstruction32(Val, 5, 2);
1535 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1536 unsigned U = fieldFromInstruction32(Val, 12, 1);
1537
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1538 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1539 switch (type) {
1540 case 0:
1541 ShOp = ARM_AM::lsl;
1542 break;
1543 case 1:
1544 ShOp = ARM_AM::lsr;
1545 break;
1546 case 2:
1547 ShOp = ARM_AM::asr;
1548 break;
1549 case 3:
1550 ShOp = ARM_AM::ror;
1551 break;
1552 }
1553
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1555 return MCDisassembler::Fail;
1556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1557 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1558 unsigned shift;
1559 if (U)
1560 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1561 else
1562 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1563 Inst.addOperand(MCOperand::CreateImm(shift));
1564
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1565 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1566}
1567
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1568static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1569DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1570 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1571 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1572
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1573 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1574 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1576 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1577 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1578 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1579 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1580 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1581 unsigned P = fieldFromInstruction32(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1582 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1583
1584 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1585
1586 // For {LD,ST}RD, Rt must be even, else undefined.
1587 switch (Inst.getOpcode()) {
1588 case ARM::STRD:
1589 case ARM::STRD_PRE:
1590 case ARM::STRD_POST:
1591 case ARM::LDRD:
1592 case ARM::LDRD_PRE:
1593 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1594 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1595 break;
1596 default:
1597 break;
1598 }
1599 switch (Inst.getOpcode()) {
1600 case ARM::STRD:
1601 case ARM::STRD_PRE:
1602 case ARM::STRD_POST:
1603 if (P == 0 && W == 1)
1604 S = MCDisassembler::SoftFail;
1605
1606 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1607 S = MCDisassembler::SoftFail;
1608 if (type && Rm == 15)
1609 S = MCDisassembler::SoftFail;
1610 if (Rt2 == 15)
1611 S = MCDisassembler::SoftFail;
1612 if (!type && fieldFromInstruction32(Insn, 8, 4))
1613 S = MCDisassembler::SoftFail;
1614 break;
1615 case ARM::STRH:
1616 case ARM::STRH_PRE:
1617 case ARM::STRH_POST:
1618 if (Rt == 15)
1619 S = MCDisassembler::SoftFail;
1620 if (writeback && (Rn == 15 || Rn == Rt))
1621 S = MCDisassembler::SoftFail;
1622 if (!type && Rm == 15)
1623 S = MCDisassembler::SoftFail;
1624 break;
1625 case ARM::LDRD:
1626 case ARM::LDRD_PRE:
1627 case ARM::LDRD_POST:
1628 if (type && Rn == 15){
1629 if (Rt2 == 15)
1630 S = MCDisassembler::SoftFail;
1631 break;
1632 }
1633 if (P == 0 && W == 1)
1634 S = MCDisassembler::SoftFail;
1635 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1636 S = MCDisassembler::SoftFail;
1637 if (!type && writeback && Rn == 15)
1638 S = MCDisassembler::SoftFail;
1639 if (writeback && (Rn == Rt || Rn == Rt2))
1640 S = MCDisassembler::SoftFail;
1641 break;
1642 case ARM::LDRH:
1643 case ARM::LDRH_PRE:
1644 case ARM::LDRH_POST:
1645 if (type && Rn == 15){
1646 if (Rt == 15)
1647 S = MCDisassembler::SoftFail;
1648 break;
1649 }
1650 if (Rt == 15)
1651 S = MCDisassembler::SoftFail;
1652 if (!type && Rm == 15)
1653 S = MCDisassembler::SoftFail;
1654 if (!type && writeback && (Rn == 15 || Rn == Rt))
1655 S = MCDisassembler::SoftFail;
1656 break;
1657 case ARM::LDRSH:
1658 case ARM::LDRSH_PRE:
1659 case ARM::LDRSH_POST:
1660 case ARM::LDRSB:
1661 case ARM::LDRSB_PRE:
1662 case ARM::LDRSB_POST:
1663 if (type && Rn == 15){
1664 if (Rt == 15)
1665 S = MCDisassembler::SoftFail;
1666 break;
1667 }
1668 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1669 S = MCDisassembler::SoftFail;
1670 if (!type && (Rt == 15 || Rm == 15))
1671 S = MCDisassembler::SoftFail;
1672 if (!type && writeback && (Rn == 15 || Rn == Rt))
1673 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1674 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1675 default:
1676 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1677 }
1678
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1679 if (writeback) { // Writeback
1680 if (P)
1681 U |= ARMII::IndexModePre << 9;
1682 else
1683 U |= ARMII::IndexModePost << 9;
1684
1685 // On stores, the writeback operand precedes Rt.
1686 switch (Inst.getOpcode()) {
1687 case ARM::STRD:
1688 case ARM::STRD_PRE:
1689 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1690 case ARM::STRH:
1691 case ARM::STRH_PRE:
1692 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1694 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1695 break;
1696 default:
1697 break;
1698 }
1699 }
1700
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1702 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1703 switch (Inst.getOpcode()) {
1704 case ARM::STRD:
1705 case ARM::STRD_PRE:
1706 case ARM::STRD_POST:
1707 case ARM::LDRD:
1708 case ARM::LDRD_PRE:
1709 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1711 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1712 break;
1713 default:
1714 break;
1715 }
1716
1717 if (writeback) {
1718 // On loads, the writeback operand comes after Rt.
1719 switch (Inst.getOpcode()) {
1720 case ARM::LDRD:
1721 case ARM::LDRD_PRE:
1722 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1723 case ARM::LDRH:
1724 case ARM::LDRH_PRE:
1725 case ARM::LDRH_POST:
1726 case ARM::LDRSH:
1727 case ARM::LDRSH_PRE:
1728 case ARM::LDRSH_POST:
1729 case ARM::LDRSB:
1730 case ARM::LDRSB_PRE:
1731 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1732 case ARM::LDRHTr:
1733 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1735 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1736 break;
1737 default:
1738 break;
1739 }
1740 }
1741
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1743 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1744
1745 if (type) {
1746 Inst.addOperand(MCOperand::CreateReg(0));
1747 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1748 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1750 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1751 Inst.addOperand(MCOperand::CreateImm(U));
1752 }
1753
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1754 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1755 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1756
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1757 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1758}
1759
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1760static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1761 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1762 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1763
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1764 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1765 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1766
1767 switch (mode) {
1768 case 0:
1769 mode = ARM_AM::da;
1770 break;
1771 case 1:
1772 mode = ARM_AM::ia;
1773 break;
1774 case 2:
1775 mode = ARM_AM::db;
1776 break;
1777 case 3:
1778 mode = ARM_AM::ib;
1779 break;
1780 }
1781
1782 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1784 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1785
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1786 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1787}
1788
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1789static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1790 unsigned Insn,
1791 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1792 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1793
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1794 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1795 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1796 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1797
1798 if (pred == 0xF) {
1799 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1800 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1801 Inst.setOpcode(ARM::RFEDA);
1802 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1803 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1804 Inst.setOpcode(ARM::RFEDA_UPD);
1805 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1806 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1807 Inst.setOpcode(ARM::RFEDB);
1808 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1809 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1810 Inst.setOpcode(ARM::RFEDB_UPD);
1811 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1812 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1813 Inst.setOpcode(ARM::RFEIA);
1814 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1815 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1816 Inst.setOpcode(ARM::RFEIA_UPD);
1817 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1818 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1819 Inst.setOpcode(ARM::RFEIB);
1820 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1821 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1822 Inst.setOpcode(ARM::RFEIB_UPD);
1823 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1824 case ARM::STMDA:
1825 Inst.setOpcode(ARM::SRSDA);
1826 break;
1827 case ARM::STMDA_UPD:
1828 Inst.setOpcode(ARM::SRSDA_UPD);
1829 break;
1830 case ARM::STMDB:
1831 Inst.setOpcode(ARM::SRSDB);
1832 break;
1833 case ARM::STMDB_UPD:
1834 Inst.setOpcode(ARM::SRSDB_UPD);
1835 break;
1836 case ARM::STMIA:
1837 Inst.setOpcode(ARM::SRSIA);
1838 break;
1839 case ARM::STMIA_UPD:
1840 Inst.setOpcode(ARM::SRSIA_UPD);
1841 break;
1842 case ARM::STMIB:
1843 Inst.setOpcode(ARM::SRSIB);
1844 break;
1845 case ARM::STMIB_UPD:
1846 Inst.setOpcode(ARM::SRSIB_UPD);
1847 break;
1848 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1849 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1850 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1851
1852 // For stores (which become SRS's, the only operand is the mode.
1853 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1854 Inst.addOperand(
1855 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1856 return S;
1857 }
1858
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1859 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1860 }
1861
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1863 return MCDisassembler::Fail;
1864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1865 return MCDisassembler::Fail; // Tied
1866 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1867 return MCDisassembler::Fail;
1868 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1869 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1870
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1871 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1872}
1873
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1874static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1875 uint64_t Address, const void *Decoder) {
1876 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1877 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1878 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1879 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1881 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1882
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1883 // imod == '01' --> UNPREDICTABLE
1884 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1885 // return failure here. The '01' imod value is unprintable, so there's
1886 // nothing useful we could do even if we returned UNPREDICTABLE.
1887
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1888 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1889
1890 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1891 Inst.setOpcode(ARM::CPS3p);
1892 Inst.addOperand(MCOperand::CreateImm(imod));
1893 Inst.addOperand(MCOperand::CreateImm(iflags));
1894 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1895 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1896 Inst.setOpcode(ARM::CPS2p);
1897 Inst.addOperand(MCOperand::CreateImm(imod));
1898 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1899 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1900 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1901 Inst.setOpcode(ARM::CPS1p);
1902 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1903 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1904 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1905 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1906 Inst.setOpcode(ARM::CPS1p);
1907 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1908 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1909 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1910
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1911 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1912}
1913
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1914static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1915 uint64_t Address, const void *Decoder) {
1916 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1917 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1918 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1919 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1920
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1921 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1922
1923 // imod == '01' --> UNPREDICTABLE
1924 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1925 // return failure here. The '01' imod value is unprintable, so there's
1926 // nothing useful we could do even if we returned UNPREDICTABLE.
1927
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1928 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1929
1930 if (imod && M) {
1931 Inst.setOpcode(ARM::t2CPS3p);
1932 Inst.addOperand(MCOperand::CreateImm(imod));
1933 Inst.addOperand(MCOperand::CreateImm(iflags));
1934 Inst.addOperand(MCOperand::CreateImm(mode));
1935 } else if (imod && !M) {
1936 Inst.setOpcode(ARM::t2CPS2p);
1937 Inst.addOperand(MCOperand::CreateImm(imod));
1938 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1939 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1940 } else if (!imod && M) {
1941 Inst.setOpcode(ARM::t2CPS1p);
1942 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1943 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1944 } else {
1945 // imod == '00' && M == '0' --> UNPREDICTABLE
1946 Inst.setOpcode(ARM::t2CPS1p);
1947 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1948 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1949 }
1950
1951 return S;
1952}
1953
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1954static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1955 uint64_t Address, const void *Decoder) {
1956 DecodeStatus S = MCDisassembler::Success;
1957
1958 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1959 unsigned imm = 0;
1960
1961 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1962 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1963 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1964 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1965
1966 if (Inst.getOpcode() == ARM::t2MOVTi16)
1967 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1968 return MCDisassembler::Fail;
1969 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1970 return MCDisassembler::Fail;
1971
1972 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1973 Inst.addOperand(MCOperand::CreateImm(imm));
1974
1975 return S;
1976}
1977
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1978static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1979 uint64_t Address, const void *Decoder) {
1980 DecodeStatus S = MCDisassembler::Success;
1981
1982 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1983 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1984 unsigned imm = 0;
1985
1986 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1987 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1988
1989 if (Inst.getOpcode() == ARM::MOVTi16)
1990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1991 return MCDisassembler::Fail;
1992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1993 return MCDisassembler::Fail;
1994
1995 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1996 Inst.addOperand(MCOperand::CreateImm(imm));
1997
1998 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1999 return MCDisassembler::Fail;
2000
2001 return S;
2002}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]2003
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2004static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2005 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2006 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2007
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2008 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
2009 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
2010 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
2011 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
2012 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2013
2014 if (pred == 0xF)
2015 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2016
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2017 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2018 return MCDisassembler::Fail;
2019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2020 return MCDisassembler::Fail;
2021 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2022 return MCDisassembler::Fail;
2023 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2024 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2025
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2026 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2027 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]2028
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2029 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2030}
2031
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2032static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2033 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2034 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2035
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2036 unsigned add = fieldFromInstruction32(Val, 12, 1);
2037 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2038 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2039
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2041 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2042
2043 if (!add) imm *= -1;
2044 if (imm == 0 && !add) imm = INT32_MIN;
2045 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2046 if (Rn == 15)
2047 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2048
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2049 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2050}
2051
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2052static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2053 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2054 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2055
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2056 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2057 unsigned U = fieldFromInstruction32(Val, 8, 1);
2058 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2059
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2061 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2062
2063 if (U)
2064 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2065 else
2066 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2067
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2068 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2069}
2070
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2071static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2072 uint64_t Address, const void *Decoder) {
2073 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2074}
2075
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2076static DecodeStatus
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2077DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2078 uint64_t Address, const void *Decoder) {
2079 DecodeStatus S = MCDisassembler::Success;
2080 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) |
2081 (fieldFromInstruction32(Insn, 11, 1) << 18) |
2082 (fieldFromInstruction32(Insn, 13, 1) << 17) |
2083 (fieldFromInstruction32(Insn, 16, 6) << 11) |
2084 (fieldFromInstruction32(Insn, 26, 1) << 19);
2085 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2086 true, 4, Inst, Decoder))
2087 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2088 return S;
2089}
2090
2091static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2092DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2093 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2094 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2095
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2096 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2097 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2098
2099 if (pred == 0xF) {
2100 Inst.setOpcode(ARM::BLXi);
2101 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2102 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2103 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2104 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2105 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2106 }
2107
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2108 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2109 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2110 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2112 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2113
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2114 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2115}
2116
2117
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2118static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2119 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2120 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2121
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2122 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2123 unsigned align = fieldFromInstruction32(Val, 4, 2);
2124
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2126 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2127 if (!align)
2128 Inst.addOperand(MCOperand::CreateImm(0));
2129 else
2130 Inst.addOperand(MCOperand::CreateImm(4 << align));
2131
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2132 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2133}
2134
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2135static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2136 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2137 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2138
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2139 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2140 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2141 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2142 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2143 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2144 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2145
2146 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2147 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2148 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2149 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2150 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2151 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2152 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2153 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2154 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2155 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2156 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2157 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2158 return MCDisassembler::Fail;
2159 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2160 case ARM::VLD2b16:
2161 case ARM::VLD2b32:
2162 case ARM::VLD2b8:
2163 case ARM::VLD2b16wb_fixed:
2164 case ARM::VLD2b16wb_register:
2165 case ARM::VLD2b32wb_fixed:
2166 case ARM::VLD2b32wb_register:
2167 case ARM::VLD2b8wb_fixed:
2168 case ARM::VLD2b8wb_register:
2169 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2170 return MCDisassembler::Fail;
2171 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2172 default:
2173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2174 return MCDisassembler::Fail;
2175 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2176
2177 // Second output register
2178 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2179 case ARM::VLD3d8:
2180 case ARM::VLD3d16:
2181 case ARM::VLD3d32:
2182 case ARM::VLD3d8_UPD:
2183 case ARM::VLD3d16_UPD:
2184 case ARM::VLD3d32_UPD:
2185 case ARM::VLD4d8:
2186 case ARM::VLD4d16:
2187 case ARM::VLD4d32:
2188 case ARM::VLD4d8_UPD:
2189 case ARM::VLD4d16_UPD:
2190 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2191 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2192 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2193 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2194 case ARM::VLD3q8:
2195 case ARM::VLD3q16:
2196 case ARM::VLD3q32:
2197 case ARM::VLD3q8_UPD:
2198 case ARM::VLD3q16_UPD:
2199 case ARM::VLD3q32_UPD:
2200 case ARM::VLD4q8:
2201 case ARM::VLD4q16:
2202 case ARM::VLD4q32:
2203 case ARM::VLD4q8_UPD:
2204 case ARM::VLD4q16_UPD:
2205 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2207 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2208 default:
2209 break;
2210 }
2211
2212 // Third output register
2213 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2214 case ARM::VLD3d8:
2215 case ARM::VLD3d16:
2216 case ARM::VLD3d32:
2217 case ARM::VLD3d8_UPD:
2218 case ARM::VLD3d16_UPD:
2219 case ARM::VLD3d32_UPD:
2220 case ARM::VLD4d8:
2221 case ARM::VLD4d16:
2222 case ARM::VLD4d32:
2223 case ARM::VLD4d8_UPD:
2224 case ARM::VLD4d16_UPD:
2225 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2226 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2227 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2228 break;
2229 case ARM::VLD3q8:
2230 case ARM::VLD3q16:
2231 case ARM::VLD3q32:
2232 case ARM::VLD3q8_UPD:
2233 case ARM::VLD3q16_UPD:
2234 case ARM::VLD3q32_UPD:
2235 case ARM::VLD4q8:
2236 case ARM::VLD4q16:
2237 case ARM::VLD4q32:
2238 case ARM::VLD4q8_UPD:
2239 case ARM::VLD4q16_UPD:
2240 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2241 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2242 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2243 break;
2244 default:
2245 break;
2246 }
2247
2248 // Fourth output register
2249 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2250 case ARM::VLD4d8:
2251 case ARM::VLD4d16:
2252 case ARM::VLD4d32:
2253 case ARM::VLD4d8_UPD:
2254 case ARM::VLD4d16_UPD:
2255 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2256 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2257 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2258 break;
2259 case ARM::VLD4q8:
2260 case ARM::VLD4q16:
2261 case ARM::VLD4q32:
2262 case ARM::VLD4q8_UPD:
2263 case ARM::VLD4q16_UPD:
2264 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2266 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2267 break;
2268 default:
2269 break;
2270 }
2271
2272 // Writeback operand
2273 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2274 case ARM::VLD1d8wb_fixed:
2275 case ARM::VLD1d16wb_fixed:
2276 case ARM::VLD1d32wb_fixed:
2277 case ARM::VLD1d64wb_fixed:
2278 case ARM::VLD1d8wb_register:
2279 case ARM::VLD1d16wb_register:
2280 case ARM::VLD1d32wb_register:
2281 case ARM::VLD1d64wb_register:
2282 case ARM::VLD1q8wb_fixed:
2283 case ARM::VLD1q16wb_fixed:
2284 case ARM::VLD1q32wb_fixed:
2285 case ARM::VLD1q64wb_fixed:
2286 case ARM::VLD1q8wb_register:
2287 case ARM::VLD1q16wb_register:
2288 case ARM::VLD1q32wb_register:
2289 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2290 case ARM::VLD1d8Twb_fixed:
2291 case ARM::VLD1d8Twb_register:
2292 case ARM::VLD1d16Twb_fixed:
2293 case ARM::VLD1d16Twb_register:
2294 case ARM::VLD1d32Twb_fixed:
2295 case ARM::VLD1d32Twb_register:
2296 case ARM::VLD1d64Twb_fixed:
2297 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2298 case ARM::VLD1d8Qwb_fixed:
2299 case ARM::VLD1d8Qwb_register:
2300 case ARM::VLD1d16Qwb_fixed:
2301 case ARM::VLD1d16Qwb_register:
2302 case ARM::VLD1d32Qwb_fixed:
2303 case ARM::VLD1d32Qwb_register:
2304 case ARM::VLD1d64Qwb_fixed:
2305 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2306 case ARM::VLD2d8wb_fixed:
2307 case ARM::VLD2d16wb_fixed:
2308 case ARM::VLD2d32wb_fixed:
2309 case ARM::VLD2q8wb_fixed:
2310 case ARM::VLD2q16wb_fixed:
2311 case ARM::VLD2q32wb_fixed:
2312 case ARM::VLD2d8wb_register:
2313 case ARM::VLD2d16wb_register:
2314 case ARM::VLD2d32wb_register:
2315 case ARM::VLD2q8wb_register:
2316 case ARM::VLD2q16wb_register:
2317 case ARM::VLD2q32wb_register:
2318 case ARM::VLD2b8wb_fixed:
2319 case ARM::VLD2b16wb_fixed:
2320 case ARM::VLD2b32wb_fixed:
2321 case ARM::VLD2b8wb_register:
2322 case ARM::VLD2b16wb_register:
2323 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2324 Inst.addOperand(MCOperand::CreateImm(0));
2325 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2326 case ARM::VLD3d8_UPD:
2327 case ARM::VLD3d16_UPD:
2328 case ARM::VLD3d32_UPD:
2329 case ARM::VLD3q8_UPD:
2330 case ARM::VLD3q16_UPD:
2331 case ARM::VLD3q32_UPD:
2332 case ARM::VLD4d8_UPD:
2333 case ARM::VLD4d16_UPD:
2334 case ARM::VLD4d32_UPD:
2335 case ARM::VLD4q8_UPD:
2336 case ARM::VLD4q16_UPD:
2337 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2338 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2339 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2340 break;
2341 default:
2342 break;
2343 }
2344
2345 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2346 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2347 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2348
2349 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2350 switch (Inst.getOpcode()) {
2351 default:
2352 // The below have been updated to have explicit am6offset split
2353 // between fixed and register offset. For those instructions not
2354 // yet updated, we need to add an additional reg0 operand for the
2355 // fixed variant.
2356 //
2357 // The fixed offset encodes as Rm == 0xd, so we check for that.
2358 if (Rm == 0xd) {
2359 Inst.addOperand(MCOperand::CreateReg(0));
2360 break;
2361 }
2362 // Fall through to handle the register offset variant.
2363 case ARM::VLD1d8wb_fixed:
2364 case ARM::VLD1d16wb_fixed:
2365 case ARM::VLD1d32wb_fixed:
2366 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2367 case ARM::VLD1d8Twb_fixed:
2368 case ARM::VLD1d16Twb_fixed:
2369 case ARM::VLD1d32Twb_fixed:
2370 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2371 case ARM::VLD1d8Qwb_fixed:
2372 case ARM::VLD1d16Qwb_fixed:
2373 case ARM::VLD1d32Qwb_fixed:
2374 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2375 case ARM::VLD1d8wb_register:
2376 case ARM::VLD1d16wb_register:
2377 case ARM::VLD1d32wb_register:
2378 case ARM::VLD1d64wb_register:
2379 case ARM::VLD1q8wb_fixed:
2380 case ARM::VLD1q16wb_fixed:
2381 case ARM::VLD1q32wb_fixed:
2382 case ARM::VLD1q64wb_fixed:
2383 case ARM::VLD1q8wb_register:
2384 case ARM::VLD1q16wb_register:
2385 case ARM::VLD1q32wb_register:
2386 case ARM::VLD1q64wb_register:
2387 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2388 // variant encodes Rm == 0xf. Anything else is a register offset post-
2389 // increment and we need to add the register operand to the instruction.
2390 if (Rm != 0xD && Rm != 0xF &&
2391 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2392 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2393 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2394 case ARM::VLD2d8wb_fixed:
2395 case ARM::VLD2d16wb_fixed:
2396 case ARM::VLD2d32wb_fixed:
2397 case ARM::VLD2b8wb_fixed:
2398 case ARM::VLD2b16wb_fixed:
2399 case ARM::VLD2b32wb_fixed:
2400 case ARM::VLD2q8wb_fixed:
2401 case ARM::VLD2q16wb_fixed:
2402 case ARM::VLD2q32wb_fixed:
2403 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2404 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2405
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2406 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2407}
2408
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2409static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2410 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2411 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2412
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2413 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2414 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2415 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2416 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2417 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2418 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2419
2420 // Writeback Operand
2421 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2422 case ARM::VST1d8wb_fixed:
2423 case ARM::VST1d16wb_fixed:
2424 case ARM::VST1d32wb_fixed:
2425 case ARM::VST1d64wb_fixed:
2426 case ARM::VST1d8wb_register:
2427 case ARM::VST1d16wb_register:
2428 case ARM::VST1d32wb_register:
2429 case ARM::VST1d64wb_register:
2430 case ARM::VST1q8wb_fixed:
2431 case ARM::VST1q16wb_fixed:
2432 case ARM::VST1q32wb_fixed:
2433 case ARM::VST1q64wb_fixed:
2434 case ARM::VST1q8wb_register:
2435 case ARM::VST1q16wb_register:
2436 case ARM::VST1q32wb_register:
2437 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2438 case ARM::VST1d8Twb_fixed:
2439 case ARM::VST1d16Twb_fixed:
2440 case ARM::VST1d32Twb_fixed:
2441 case ARM::VST1d64Twb_fixed:
2442 case ARM::VST1d8Twb_register:
2443 case ARM::VST1d16Twb_register:
2444 case ARM::VST1d32Twb_register:
2445 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2446 case ARM::VST1d8Qwb_fixed:
2447 case ARM::VST1d16Qwb_fixed:
2448 case ARM::VST1d32Qwb_fixed:
2449 case ARM::VST1d64Qwb_fixed:
2450 case ARM::VST1d8Qwb_register:
2451 case ARM::VST1d16Qwb_register:
2452 case ARM::VST1d32Qwb_register:
2453 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2454 case ARM::VST2d8wb_fixed:
2455 case ARM::VST2d16wb_fixed:
2456 case ARM::VST2d32wb_fixed:
2457 case ARM::VST2d8wb_register:
2458 case ARM::VST2d16wb_register:
2459 case ARM::VST2d32wb_register:
2460 case ARM::VST2q8wb_fixed:
2461 case ARM::VST2q16wb_fixed:
2462 case ARM::VST2q32wb_fixed:
2463 case ARM::VST2q8wb_register:
2464 case ARM::VST2q16wb_register:
2465 case ARM::VST2q32wb_register:
2466 case ARM::VST2b8wb_fixed:
2467 case ARM::VST2b16wb_fixed:
2468 case ARM::VST2b32wb_fixed:
2469 case ARM::VST2b8wb_register:
2470 case ARM::VST2b16wb_register:
2471 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame]2472 if (Rm == 0xF)
2473 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2474 Inst.addOperand(MCOperand::CreateImm(0));
2475 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2476 case ARM::VST3d8_UPD:
2477 case ARM::VST3d16_UPD:
2478 case ARM::VST3d32_UPD:
2479 case ARM::VST3q8_UPD:
2480 case ARM::VST3q16_UPD:
2481 case ARM::VST3q32_UPD:
2482 case ARM::VST4d8_UPD:
2483 case ARM::VST4d16_UPD:
2484 case ARM::VST4d32_UPD:
2485 case ARM::VST4q8_UPD:
2486 case ARM::VST4q16_UPD:
2487 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2488 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2489 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2490 break;
2491 default:
2492 break;
2493 }
2494
2495 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2496 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2497 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2498
2499 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2500 switch (Inst.getOpcode()) {
2501 default:
2502 if (Rm == 0xD)
2503 Inst.addOperand(MCOperand::CreateReg(0));
2504 else if (Rm != 0xF) {
2505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2506 return MCDisassembler::Fail;
2507 }
2508 break;
2509 case ARM::VST1d8wb_fixed:
2510 case ARM::VST1d16wb_fixed:
2511 case ARM::VST1d32wb_fixed:
2512 case ARM::VST1d64wb_fixed:
2513 case ARM::VST1q8wb_fixed:
2514 case ARM::VST1q16wb_fixed:
2515 case ARM::VST1q32wb_fixed:
2516 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2517 case ARM::VST1d8Twb_fixed:
2518 case ARM::VST1d16Twb_fixed:
2519 case ARM::VST1d32Twb_fixed:
2520 case ARM::VST1d64Twb_fixed:
2521 case ARM::VST1d8Qwb_fixed:
2522 case ARM::VST1d16Qwb_fixed:
2523 case ARM::VST1d32Qwb_fixed:
2524 case ARM::VST1d64Qwb_fixed:
2525 case ARM::VST2d8wb_fixed:
2526 case ARM::VST2d16wb_fixed:
2527 case ARM::VST2d32wb_fixed:
2528 case ARM::VST2q8wb_fixed:
2529 case ARM::VST2q16wb_fixed:
2530 case ARM::VST2q32wb_fixed:
2531 case ARM::VST2b8wb_fixed:
2532 case ARM::VST2b16wb_fixed:
2533 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2534 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2535 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2536
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2537
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2538 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2539 switch (Inst.getOpcode()) {
2540 case ARM::VST1q16:
2541 case ARM::VST1q32:
2542 case ARM::VST1q64:
2543 case ARM::VST1q8:
2544 case ARM::VST1q16wb_fixed:
2545 case ARM::VST1q16wb_register:
2546 case ARM::VST1q32wb_fixed:
2547 case ARM::VST1q32wb_register:
2548 case ARM::VST1q64wb_fixed:
2549 case ARM::VST1q64wb_register:
2550 case ARM::VST1q8wb_fixed:
2551 case ARM::VST1q8wb_register:
2552 case ARM::VST2d16:
2553 case ARM::VST2d32:
2554 case ARM::VST2d8:
2555 case ARM::VST2d16wb_fixed:
2556 case ARM::VST2d16wb_register:
2557 case ARM::VST2d32wb_fixed:
2558 case ARM::VST2d32wb_register:
2559 case ARM::VST2d8wb_fixed:
2560 case ARM::VST2d8wb_register:
2561 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2562 return MCDisassembler::Fail;
2563 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2564 case ARM::VST2b16:
2565 case ARM::VST2b32:
2566 case ARM::VST2b8:
2567 case ARM::VST2b16wb_fixed:
2568 case ARM::VST2b16wb_register:
2569 case ARM::VST2b32wb_fixed:
2570 case ARM::VST2b32wb_register:
2571 case ARM::VST2b8wb_fixed:
2572 case ARM::VST2b8wb_register:
2573 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2574 return MCDisassembler::Fail;
2575 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2576 default:
2577 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2578 return MCDisassembler::Fail;
2579 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2580
2581 // Second input register
2582 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2583 case ARM::VST3d8:
2584 case ARM::VST3d16:
2585 case ARM::VST3d32:
2586 case ARM::VST3d8_UPD:
2587 case ARM::VST3d16_UPD:
2588 case ARM::VST3d32_UPD:
2589 case ARM::VST4d8:
2590 case ARM::VST4d16:
2591 case ARM::VST4d32:
2592 case ARM::VST4d8_UPD:
2593 case ARM::VST4d16_UPD:
2594 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2595 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2596 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2597 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2598 case ARM::VST3q8:
2599 case ARM::VST3q16:
2600 case ARM::VST3q32:
2601 case ARM::VST3q8_UPD:
2602 case ARM::VST3q16_UPD:
2603 case ARM::VST3q32_UPD:
2604 case ARM::VST4q8:
2605 case ARM::VST4q16:
2606 case ARM::VST4q32:
2607 case ARM::VST4q8_UPD:
2608 case ARM::VST4q16_UPD:
2609 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2610 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2611 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2612 break;
2613 default:
2614 break;
2615 }
2616
2617 // Third input register
2618 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2619 case ARM::VST3d8:
2620 case ARM::VST3d16:
2621 case ARM::VST3d32:
2622 case ARM::VST3d8_UPD:
2623 case ARM::VST3d16_UPD:
2624 case ARM::VST3d32_UPD:
2625 case ARM::VST4d8:
2626 case ARM::VST4d16:
2627 case ARM::VST4d32:
2628 case ARM::VST4d8_UPD:
2629 case ARM::VST4d16_UPD:
2630 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2631 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2632 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2633 break;
2634 case ARM::VST3q8:
2635 case ARM::VST3q16:
2636 case ARM::VST3q32:
2637 case ARM::VST3q8_UPD:
2638 case ARM::VST3q16_UPD:
2639 case ARM::VST3q32_UPD:
2640 case ARM::VST4q8:
2641 case ARM::VST4q16:
2642 case ARM::VST4q32:
2643 case ARM::VST4q8_UPD:
2644 case ARM::VST4q16_UPD:
2645 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2646 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2647 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2648 break;
2649 default:
2650 break;
2651 }
2652
2653 // Fourth input register
2654 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2655 case ARM::VST4d8:
2656 case ARM::VST4d16:
2657 case ARM::VST4d32:
2658 case ARM::VST4d8_UPD:
2659 case ARM::VST4d16_UPD:
2660 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2661 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2662 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2663 break;
2664 case ARM::VST4q8:
2665 case ARM::VST4q16:
2666 case ARM::VST4q32:
2667 case ARM::VST4q8_UPD:
2668 case ARM::VST4q16_UPD:
2669 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2671 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2672 break;
2673 default:
2674 break;
2675 }
2676
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2677 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2678}
2679
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2680static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2681 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2682 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2683
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2685 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2686 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2687 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2688 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2689 unsigned size = fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2690
2691 align *= (1 << size);
2692
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2693 switch (Inst.getOpcode()) {
2694 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2695 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2696 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2697 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2698 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2699 return MCDisassembler::Fail;
2700 break;
2701 default:
2702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2703 return MCDisassembler::Fail;
2704 break;
2705 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2706 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2708 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2709 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2710
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2712 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2713 Inst.addOperand(MCOperand::CreateImm(align));
2714
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2715 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2716 // variant encodes Rm == 0xf. Anything else is a register offset post-
2717 // increment and we need to add the register operand to the instruction.
2718 if (Rm != 0xD && Rm != 0xF &&
2719 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2720 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2721
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2722 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2723}
2724
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2725static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2726 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2727 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2728
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2729 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2730 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2731 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2732 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2733 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2734 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2735 align *= 2*size;
2736
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2737 switch (Inst.getOpcode()) {
2738 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2739 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2740 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2741 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2742 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2743 return MCDisassembler::Fail;
2744 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2745 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2746 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2747 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2748 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2749 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2750 return MCDisassembler::Fail;
2751 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2752 default:
2753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2754 return MCDisassembler::Fail;
2755 break;
2756 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2757
2758 if (Rm != 0xF)
2759 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2760
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2762 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2763 Inst.addOperand(MCOperand::CreateImm(align));
2764
Kevin Enderbyc5a2a332012-04-17 00:49:27 +0000[diff] [blame]2765 if (Rm != 0xD && Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2767 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2768 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2769
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2770 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2771}
2772
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2773static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2774 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2775 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2776
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2777 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2778 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2779 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2780 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2781 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2782
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2784 return MCDisassembler::Fail;
2785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2786 return MCDisassembler::Fail;
2787 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2788 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2789 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2791 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2792 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2793
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2795 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2796 Inst.addOperand(MCOperand::CreateImm(0));
2797
2798 if (Rm == 0xD)
2799 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2800 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2802 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2803 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2805 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2806}
2807
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2808static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2809 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2810 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2811
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2813 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2814 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2815 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2816 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2817 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2818 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2819
2820 if (size == 0x3) {
2821 size = 4;
2822 align = 16;
2823 } else {
2824 if (size == 2) {
2825 size = 1 << size;
2826 align *= 8;
2827 } else {
2828 size = 1 << size;
2829 align *= 4*size;
2830 }
2831 }
2832
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2834 return MCDisassembler::Fail;
2835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2836 return MCDisassembler::Fail;
2837 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2838 return MCDisassembler::Fail;
2839 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2840 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2841 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2843 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2844 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2845
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2847 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2848 Inst.addOperand(MCOperand::CreateImm(align));
2849
2850 if (Rm == 0xD)
2851 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2852 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2854 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2855 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2856
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2857 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2858}
2859
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2860static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2861DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2862 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2863 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2864
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2865 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2866 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2867 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2868 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2869 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2870 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2871 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2872 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2873
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2874 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2875 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2876 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2877 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2879 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2880 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2881
2882 Inst.addOperand(MCOperand::CreateImm(imm));
2883
2884 switch (Inst.getOpcode()) {
2885 case ARM::VORRiv4i16:
2886 case ARM::VORRiv2i32:
2887 case ARM::VBICiv4i16:
2888 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2890 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2891 break;
2892 case ARM::VORRiv8i16:
2893 case ARM::VORRiv4i32:
2894 case ARM::VBICiv8i16:
2895 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2896 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2897 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2898 break;
2899 default:
2900 break;
2901 }
2902
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2903 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2904}
2905
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2906static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2908 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2909
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2910 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2911 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2912 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2913 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2914 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2915
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2916 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2917 return MCDisassembler::Fail;
2918 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2919 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2920 Inst.addOperand(MCOperand::CreateImm(8 << size));
2921
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2922 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2923}
2924
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2925static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2926 uint64_t Address, const void *Decoder) {
2927 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2928 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2929}
2930
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2931static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2932 uint64_t Address, const void *Decoder) {
2933 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2934 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2935}
2936
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2937static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2938 uint64_t Address, const void *Decoder) {
2939 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2940 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2941}
2942
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2943static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2944 uint64_t Address, const void *Decoder) {
2945 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2946 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2947}
2948
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2949static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2950 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2951 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2952
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2953 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2954 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2955 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2956 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2957 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2958 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2959 unsigned op = fieldFromInstruction32(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2960
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2961 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2962 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2963 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2965 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2966 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2967
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2968 switch (Inst.getOpcode()) {
2969 case ARM::VTBL2:
2970 case ARM::VTBX2:
2971 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2972 return MCDisassembler::Fail;
2973 break;
2974 default:
2975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2976 return MCDisassembler::Fail;
2977 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2978
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2980 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2981
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2982 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2983}
2984
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2985static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2986 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2987 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2988
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2989 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2990 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2991
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2992 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2993 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2994
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2995 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2996 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2997 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2998 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2999 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3000 case ARM::tADDrSPi:
3001 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3002 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3003 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3004
3005 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3006 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3007}
3008
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3009static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3010 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3011 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3012 true, 2, Inst, Decoder))
3013 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3014 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3015}
3016
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3017static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3018 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3019 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
3020 true, 4, Inst, Decoder))
3021 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3022 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3023}
3024
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3025static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3026 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3027 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
3028 true, 2, Inst, Decoder))
3029 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3030 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3031}
3032
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3033static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3034 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3035 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3036
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3037 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3038 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
3039
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3040 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3041 return MCDisassembler::Fail;
3042 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3043 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3044
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3045 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3046}
3047
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3048static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3049 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3050 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3051
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3052 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3053 unsigned imm = fieldFromInstruction32(Val, 3, 5);
3054
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3055 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3056 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3057 Inst.addOperand(MCOperand::CreateImm(imm));
3058
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3059 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3060}
3061
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3062static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3063 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3064 unsigned imm = Val << 2;
3065
3066 Inst.addOperand(MCOperand::CreateImm(imm));
3067 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3068
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3069 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3070}
3071
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3072static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3073 uint64_t Address, const void *Decoder) {
3074 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3075 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3076
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3077 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3078}
3079
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3080static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3081 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3082 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3083
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3084 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3085 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3086 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3087
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3089 return MCDisassembler::Fail;
3090 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3091 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3092 Inst.addOperand(MCOperand::CreateImm(imm));
3093
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3094 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3095}
3096
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3097static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3098 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3099 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3100
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3101 switch (Inst.getOpcode()) {
3102 case ARM::t2PLDs:
3103 case ARM::t2PLDWs:
3104 case ARM::t2PLIs:
3105 break;
3106 default: {
3107 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3108 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3109 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3110 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3111 }
3112
3113 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3114 if (Rn == 0xF) {
3115 switch (Inst.getOpcode()) {
3116 case ARM::t2LDRBs:
3117 Inst.setOpcode(ARM::t2LDRBpci);
3118 break;
3119 case ARM::t2LDRHs:
3120 Inst.setOpcode(ARM::t2LDRHpci);
3121 break;
3122 case ARM::t2LDRSHs:
3123 Inst.setOpcode(ARM::t2LDRSHpci);
3124 break;
3125 case ARM::t2LDRSBs:
3126 Inst.setOpcode(ARM::t2LDRSBpci);
3127 break;
3128 case ARM::t2PLDs:
3129 Inst.setOpcode(ARM::t2PLDi12);
3130 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3131 break;
3132 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3133 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3134 }
3135
3136 int imm = fieldFromInstruction32(Insn, 0, 12);
3137 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3138 Inst.addOperand(MCOperand::CreateImm(imm));
3139
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3140 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3141 }
3142
3143 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3144 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3145 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3146 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3147 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3148
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3149 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3150}
3151
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3152static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3153 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3154 int imm = Val & 0xFF;
3155 if (!(Val & 0x100)) imm *= -1;
3156 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3157
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3158 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3159}
3160
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3161static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3162 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3163 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3164
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3165 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3166 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3167
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3169 return MCDisassembler::Fail;
3170 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3171 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3172
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3173 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3174}
3175
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3176static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3177 uint64_t Address, const void *Decoder) {
3178 DecodeStatus S = MCDisassembler::Success;
3179
3180 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3181 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3182
3183 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3184 return MCDisassembler::Fail;
3185
3186 Inst.addOperand(MCOperand::CreateImm(imm));
3187
3188 return S;
3189}
3190
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3191static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3192 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3193 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3194 if (Val == 0)
3195 imm = INT32_MIN;
3196 else if (!(Val & 0x100))
3197 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3198 Inst.addOperand(MCOperand::CreateImm(imm));
3199
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3200 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3201}
3202
3203
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3204static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3205 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3206 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3207
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3208 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3209 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3210
3211 // Some instructions always use an additive offset.
3212 switch (Inst.getOpcode()) {
3213 case ARM::t2LDRT:
3214 case ARM::t2LDRBT:
3215 case ARM::t2LDRHT:
3216 case ARM::t2LDRSBT:
3217 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3218 case ARM::t2STRT:
3219 case ARM::t2STRBT:
3220 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3221 imm |= 0x100;
3222 break;
3223 default:
3224 break;
3225 }
3226
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3228 return MCDisassembler::Fail;
3229 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3230 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3231
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3232 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3233}
3234
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3235static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3236 uint64_t Address, const void *Decoder) {
3237 DecodeStatus S = MCDisassembler::Success;
3238
3239 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3240 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3241 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3242 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3243 addr |= Rn << 9;
3244 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3245
3246 if (!load) {
3247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3248 return MCDisassembler::Fail;
3249 }
3250
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]3251 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3252 return MCDisassembler::Fail;
3253
3254 if (load) {
3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3256 return MCDisassembler::Fail;
3257 }
3258
3259 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3260 return MCDisassembler::Fail;
3261
3262 return S;
3263}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3264
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3265static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3266 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3267 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3268
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3269 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3270 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3271
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3273 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3274 Inst.addOperand(MCOperand::CreateImm(imm));
3275
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3276 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3277}
3278
3279
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3280static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3281 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3282 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3283
3284 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3285 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3286 Inst.addOperand(MCOperand::CreateImm(imm));
3287
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3288 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3289}
3290
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3291static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3292 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3293 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3294
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3295 if (Inst.getOpcode() == ARM::tADDrSP) {
3296 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3297 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3298
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3300 return MCDisassembler::Fail;
Jim Grosbachbb32f1d2012-04-27 23:51:33 +0000[diff] [blame]3301 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3303 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3304 } else if (Inst.getOpcode() == ARM::tADDspr) {
3305 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3306
3307 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3308 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3310 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3311 }
3312
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3313 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3314}
3315
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3316static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3317 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3318 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3319 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3320
3321 Inst.addOperand(MCOperand::CreateImm(imod));
3322 Inst.addOperand(MCOperand::CreateImm(flags));
3323
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3324 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3325}
3326
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3327static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3328 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3329 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3330 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3331 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3332
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3333 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3334 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3335 Inst.addOperand(MCOperand::CreateImm(add));
3336
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3337 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3338}
3339
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3340static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3341 uint64_t Address, const void *Decoder) {
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame^]3342 // Val is passed in as S:J1:J2:imm10H:imm10L:’0’
3343 // Note only one trailing zero not two. Also the J1 and J2 values are from
3344 // the encoded instruction. So here change to I1 and I2 values via:
3345 // I1 = NOT(J1 EOR S);
3346 // I2 = NOT(J2 EOR S);
3347 // and build the imm32 with two trailing zeros as documented:
3348 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:’00’, 32);
3349 unsigned S = (Val >> 23) & 1;
3350 unsigned J1 = (Val >> 22) & 1;
3351 unsigned J2 = (Val >> 21) & 1;
3352 unsigned I1 = !(J1 ^ S);
3353 unsigned I2 = !(J2 ^ S);
3354 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3355 int imm32 = SignExtend32<25>(tmp << 1);
3356
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3357 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame^]3358 (Address & ~2u) + imm32 + 4,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3359 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame^]3360 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3361 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3362}
3363
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3364static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3365 uint64_t Address, const void *Decoder) {
3366 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3367 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3368
3369 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3370 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3371}
3372
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3373static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3374DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3375 uint64_t Address, const void *Decoder) {
3376 DecodeStatus S = MCDisassembler::Success;
3377
3378 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3379 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3380
3381 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3383 return MCDisassembler::Fail;
3384 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3385 return MCDisassembler::Fail;
3386 return S;
3387}
3388
3389static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3390DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3391 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3392 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3393
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3394 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3395 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3396 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3397 switch (opc) {
3398 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3399 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3400 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3401 Inst.setOpcode(ARM::t2DSB);
3402 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3403 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3404 Inst.setOpcode(ARM::t2DMB);
3405 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3406 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3407 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3408 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3409 }
3410
3411 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3412 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3413 }
3414
3415 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3416 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3417 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3418 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3419 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3420
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3421 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3422 return MCDisassembler::Fail;
3423 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3424 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3425
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3426 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3427}
3428
3429// Decode a shifted immediate operand. These basically consist
3430// of an 8-bit value, and a 4-bit directive that specifies either
3431// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3432static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3433 uint64_t Address, const void *Decoder) {
3434 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3435 if (ctrl == 0) {
3436 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3437 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3438 switch (byte) {
3439 case 0:
3440 Inst.addOperand(MCOperand::CreateImm(imm));
3441 break;
3442 case 1:
3443 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3444 break;
3445 case 2:
3446 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3447 break;
3448 case 3:
3449 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3450 (imm << 8) | imm));
3451 break;
3452 }
3453 } else {
3454 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3455 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3456 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3457 Inst.addOperand(MCOperand::CreateImm(imm));
3458 }
3459
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3460 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3461}
3462
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3463static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3464DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3465 uint64_t Address, const void *Decoder){
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3466 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4,
3467 true, 2, Inst, Decoder))
3468 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3469 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3470}
3471
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3472static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3473 uint64_t Address, const void *Decoder){
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame^]3474 // Val is passed in as S:J1:J2:imm10:imm11
3475 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3476 // the encoded instruction. So here change to I1 and I2 values via:
3477 // I1 = NOT(J1 EOR S);
3478 // I2 = NOT(J2 EOR S);
3479 // and build the imm32 with one trailing zero as documented:
3480 // imm32 = SignExtend(S:I1:I2:imm10:imm11:’0’, 32);
3481 unsigned S = (Val >> 23) & 1;
3482 unsigned J1 = (Val >> 22) & 1;
3483 unsigned J2 = (Val >> 21) & 1;
3484 unsigned I1 = !(J1 ^ S);
3485 unsigned I2 = !(J2 ^ S);
3486 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3487 int imm32 = SignExtend32<25>(tmp << 1);
3488
3489 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3490 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame^]3491 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3492 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3493}
3494
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3495static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3496 uint64_t Address, const void *Decoder) {
3497 switch (Val) {
3498 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3499 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3500 case 0xF: // SY
3501 case 0xE: // ST
3502 case 0xB: // ISH
3503 case 0xA: // ISHST
3504 case 0x7: // NSH
3505 case 0x6: // NSHST
3506 case 0x3: // OSH
3507 case 0x2: // OSHST
3508 break;
3509 }
3510
3511 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3512 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3513}
3514
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3515static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3516 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3517 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3518 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3519 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3520}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3521
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3522static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3523 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3524 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3525
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3526 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3527 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3528 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3529
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3530 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3531
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3533 return MCDisassembler::Fail;
3534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3535 return MCDisassembler::Fail;
3536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3537 return MCDisassembler::Fail;
3538 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3539 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3540
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3541 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3542}
3543
3544
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3545static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3546 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3547 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3548
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3549 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3550 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3551 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3552 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3553
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3554 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3555 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3556
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3557 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3558 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3559
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3561 return MCDisassembler::Fail;
3562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3563 return MCDisassembler::Fail;
3564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3565 return MCDisassembler::Fail;
3566 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3567 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3568
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3569 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3570}
3571
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3572static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3573 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3574 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3575
3576 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3577 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3578 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3579 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3580 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3581 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3582
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3583 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3584
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3586 return MCDisassembler::Fail;
3587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3588 return MCDisassembler::Fail;
3589 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3590 return MCDisassembler::Fail;
3591 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3592 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3593
3594 return S;
3595}
3596
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3597static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3598 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3599 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3600
3601 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3602 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3603 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3604 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3605 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3606 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3607 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3608
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3609 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3610 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3611
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3613 return MCDisassembler::Fail;
3614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3615 return MCDisassembler::Fail;
3616 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3617 return MCDisassembler::Fail;
3618 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3619 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3620
3621 return S;
3622}
3623
3624
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3625static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3626 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3627 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3628
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3629 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3630 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3631 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3632 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3633 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3634 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3635
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3636 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3637
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3639 return MCDisassembler::Fail;
3640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3641 return MCDisassembler::Fail;
3642 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3643 return MCDisassembler::Fail;
3644 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3645 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3646
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3647 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3648}
3649
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3650static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3651 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3652 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3653
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3654 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3655 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3656 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3657 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3658 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3659 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3660
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3661 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3662
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3664 return MCDisassembler::Fail;
3665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3666 return MCDisassembler::Fail;
3667 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3668 return MCDisassembler::Fail;
3669 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3670 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3671
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3672 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3673}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3674
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3675static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3676 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3677 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3678
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3679 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3680 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3681 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3682 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3683 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3684
3685 unsigned align = 0;
3686 unsigned index = 0;
3687 switch (size) {
3688 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3689 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3690 case 0:
3691 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3692 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3693 index = fieldFromInstruction32(Insn, 5, 3);
3694 break;
3695 case 1:
3696 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3697 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3698 index = fieldFromInstruction32(Insn, 6, 2);
3699 if (fieldFromInstruction32(Insn, 4, 1))
3700 align = 2;
3701 break;
3702 case 2:
3703 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3704 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3705 index = fieldFromInstruction32(Insn, 7, 1);
3706 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3707 align = 4;
3708 }
3709
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3711 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3712 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3714 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3715 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3717 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3718 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3719 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3720 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3722 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3723 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3724 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3725 }
3726
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3727 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3728 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3729 Inst.addOperand(MCOperand::CreateImm(index));
3730
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3731 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3732}
3733
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3734static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3735 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3736 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3737
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3738 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3739 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3740 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3741 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3742 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3743
3744 unsigned align = 0;
3745 unsigned index = 0;
3746 switch (size) {
3747 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3748 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3749 case 0:
3750 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3751 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3752 index = fieldFromInstruction32(Insn, 5, 3);
3753 break;
3754 case 1:
3755 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3756 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3757 index = fieldFromInstruction32(Insn, 6, 2);
3758 if (fieldFromInstruction32(Insn, 4, 1))
3759 align = 2;
3760 break;
3761 case 2:
3762 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3763 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3764 index = fieldFromInstruction32(Insn, 7, 1);
3765 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3766 align = 4;
3767 }
3768
3769 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3770 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3771 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3772 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3774 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3775 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3776 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3777 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3779 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3780 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3781 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3782 }
3783
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3785 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3786 Inst.addOperand(MCOperand::CreateImm(index));
3787
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3788 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3789}
3790
3791
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3792static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3793 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3794 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3795
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3796 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3797 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3798 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3799 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3800 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3801
3802 unsigned align = 0;
3803 unsigned index = 0;
3804 unsigned inc = 1;
3805 switch (size) {
3806 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3807 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3808 case 0:
3809 index = fieldFromInstruction32(Insn, 5, 3);
3810 if (fieldFromInstruction32(Insn, 4, 1))
3811 align = 2;
3812 break;
3813 case 1:
3814 index = fieldFromInstruction32(Insn, 6, 2);
3815 if (fieldFromInstruction32(Insn, 4, 1))
3816 align = 4;
3817 if (fieldFromInstruction32(Insn, 5, 1))
3818 inc = 2;
3819 break;
3820 case 2:
3821 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3822 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3823 index = fieldFromInstruction32(Insn, 7, 1);
3824 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3825 align = 8;
3826 if (fieldFromInstruction32(Insn, 6, 1))
3827 inc = 2;
3828 break;
3829 }
3830
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3832 return MCDisassembler::Fail;
3833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3834 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3835 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3837 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3838 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3840 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3841 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3842 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3843 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3845 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3846 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3847 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3848 }
3849
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3850 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3851 return MCDisassembler::Fail;
3852 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3853 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3854 Inst.addOperand(MCOperand::CreateImm(index));
3855
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3856 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3857}
3858
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3859static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3860 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3861 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3862
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3863 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3864 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3865 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3866 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3867 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3868
3869 unsigned align = 0;
3870 unsigned index = 0;
3871 unsigned inc = 1;
3872 switch (size) {
3873 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3874 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3875 case 0:
3876 index = fieldFromInstruction32(Insn, 5, 3);
3877 if (fieldFromInstruction32(Insn, 4, 1))
3878 align = 2;
3879 break;
3880 case 1:
3881 index = fieldFromInstruction32(Insn, 6, 2);
3882 if (fieldFromInstruction32(Insn, 4, 1))
3883 align = 4;
3884 if (fieldFromInstruction32(Insn, 5, 1))
3885 inc = 2;
3886 break;
3887 case 2:
3888 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3889 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3890 index = fieldFromInstruction32(Insn, 7, 1);
3891 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3892 align = 8;
3893 if (fieldFromInstruction32(Insn, 6, 1))
3894 inc = 2;
3895 break;
3896 }
3897
3898 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3900 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3901 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3902 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3903 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3904 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3905 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3906 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3908 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3909 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3910 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3911 }
3912
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3913 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3914 return MCDisassembler::Fail;
3915 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3916 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3917 Inst.addOperand(MCOperand::CreateImm(index));
3918
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3919 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3920}
3921
3922
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3923static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3924 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3925 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3926
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3927 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3928 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3929 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3930 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3931 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3932
3933 unsigned align = 0;
3934 unsigned index = 0;
3935 unsigned inc = 1;
3936 switch (size) {
3937 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3938 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3939 case 0:
3940 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3941 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3942 index = fieldFromInstruction32(Insn, 5, 3);
3943 break;
3944 case 1:
3945 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3946 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3947 index = fieldFromInstruction32(Insn, 6, 2);
3948 if (fieldFromInstruction32(Insn, 5, 1))
3949 inc = 2;
3950 break;
3951 case 2:
3952 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3953 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3954 index = fieldFromInstruction32(Insn, 7, 1);
3955 if (fieldFromInstruction32(Insn, 6, 1))
3956 inc = 2;
3957 break;
3958 }
3959
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3960 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3961 return MCDisassembler::Fail;
3962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3963 return MCDisassembler::Fail;
3964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3965 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3966
3967 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3969 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3970 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3971 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3972 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3973 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3974 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3975 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3976 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3977 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3978 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3979 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3980 }
3981
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3982 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3983 return MCDisassembler::Fail;
3984 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3985 return MCDisassembler::Fail;
3986 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3987 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3988 Inst.addOperand(MCOperand::CreateImm(index));
3989
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3990 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3991}
3992
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3993static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3994 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3995 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3996
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3997 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3998 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3999 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4000 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4001 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4002
4003 unsigned align = 0;
4004 unsigned index = 0;
4005 unsigned inc = 1;
4006 switch (size) {
4007 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4008 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4009 case 0:
4010 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4011 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4012 index = fieldFromInstruction32(Insn, 5, 3);
4013 break;
4014 case 1:
4015 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4016 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4017 index = fieldFromInstruction32(Insn, 6, 2);
4018 if (fieldFromInstruction32(Insn, 5, 1))
4019 inc = 2;
4020 break;
4021 case 2:
4022 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4023 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4024 index = fieldFromInstruction32(Insn, 7, 1);
4025 if (fieldFromInstruction32(Insn, 6, 1))
4026 inc = 2;
4027 break;
4028 }
4029
4030 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4032 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4033 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4035 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4036 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4037 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4038 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4040 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4041 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4042 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4043 }
4044
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4045 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4046 return MCDisassembler::Fail;
4047 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4048 return MCDisassembler::Fail;
4049 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4050 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4051 Inst.addOperand(MCOperand::CreateImm(index));
4052
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4053 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4054}
4055
4056
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4057static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4058 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4059 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4060
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4061 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4062 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4063 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4064 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4065 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4066
4067 unsigned align = 0;
4068 unsigned index = 0;
4069 unsigned inc = 1;
4070 switch (size) {
4071 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4072 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4073 case 0:
4074 if (fieldFromInstruction32(Insn, 4, 1))
4075 align = 4;
4076 index = fieldFromInstruction32(Insn, 5, 3);
4077 break;
4078 case 1:
4079 if (fieldFromInstruction32(Insn, 4, 1))
4080 align = 8;
4081 index = fieldFromInstruction32(Insn, 6, 2);
4082 if (fieldFromInstruction32(Insn, 5, 1))
4083 inc = 2;
4084 break;
4085 case 2:
4086 if (fieldFromInstruction32(Insn, 4, 2))
4087 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4088 index = fieldFromInstruction32(Insn, 7, 1);
4089 if (fieldFromInstruction32(Insn, 6, 1))
4090 inc = 2;
4091 break;
4092 }
4093
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4095 return MCDisassembler::Fail;
4096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4097 return MCDisassembler::Fail;
4098 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4099 return MCDisassembler::Fail;
4100 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4101 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4102
4103 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4105 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4106 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4108 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4109 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4110 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4111 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4113 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4114 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4115 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4116 }
4117
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4118 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4119 return MCDisassembler::Fail;
4120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4121 return MCDisassembler::Fail;
4122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4123 return MCDisassembler::Fail;
4124 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4125 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4126 Inst.addOperand(MCOperand::CreateImm(index));
4127
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4128 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4129}
4130
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4131static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4132 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4133 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4134
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4135 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4136 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4137 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4138 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4139 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4140
4141 unsigned align = 0;
4142 unsigned index = 0;
4143 unsigned inc = 1;
4144 switch (size) {
4145 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4146 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4147 case 0:
4148 if (fieldFromInstruction32(Insn, 4, 1))
4149 align = 4;
4150 index = fieldFromInstruction32(Insn, 5, 3);
4151 break;
4152 case 1:
4153 if (fieldFromInstruction32(Insn, 4, 1))
4154 align = 8;
4155 index = fieldFromInstruction32(Insn, 6, 2);
4156 if (fieldFromInstruction32(Insn, 5, 1))
4157 inc = 2;
4158 break;
4159 case 2:
4160 if (fieldFromInstruction32(Insn, 4, 2))
4161 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4162 index = fieldFromInstruction32(Insn, 7, 1);
4163 if (fieldFromInstruction32(Insn, 6, 1))
4164 inc = 2;
4165 break;
4166 }
4167
4168 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4170 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4171 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4173 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4174 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4175 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4176 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4178 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4179 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4180 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4181 }
4182
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4184 return MCDisassembler::Fail;
4185 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4186 return MCDisassembler::Fail;
4187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4188 return MCDisassembler::Fail;
4189 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4190 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4191 Inst.addOperand(MCOperand::CreateImm(index));
4192
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4193 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4194}
4195
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4196static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4197 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4198 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4199 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4200 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4201 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4202 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4203 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4204
4205 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4206 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4207
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4208 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4211 return MCDisassembler::Fail;
4212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4213 return MCDisassembler::Fail;
4214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4215 return MCDisassembler::Fail;
4216 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4217 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4218
4219 return S;
4220}
4221
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4222static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4223 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4224 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4225 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4226 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4227 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4228 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4229 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4230
4231 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4232 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4233
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4235 return MCDisassembler::Fail;
4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4237 return MCDisassembler::Fail;
4238 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4239 return MCDisassembler::Fail;
4240 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4241 return MCDisassembler::Fail;
4242 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4243 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4244
4245 return S;
4246}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4247
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4248static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4249 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4250 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4251 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]4252 unsigned mask = fieldFromInstruction16(Insn, 0, 4);
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4253
4254 if (pred == 0xF) {
4255 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4256 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4257 }
4258
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]4259 if (mask == 0x0) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4260 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4261 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4262 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4263
4264 Inst.addOperand(MCOperand::CreateImm(pred));
4265 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4266 return S;
4267}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4268
4269static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4270DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4271 uint64_t Address, const void *Decoder) {
4272 DecodeStatus S = MCDisassembler::Success;
4273
4274 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4275 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4276 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4277 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4278 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4279 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4280 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4281 bool writeback = (W == 1) | (P == 0);
4282
4283 addr |= (U << 8) | (Rn << 9);
4284
4285 if (writeback && (Rn == Rt || Rn == Rt2))
4286 Check(S, MCDisassembler::SoftFail);
4287 if (Rt == Rt2)
4288 Check(S, MCDisassembler::SoftFail);
4289
4290 // Rt
4291 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4292 return MCDisassembler::Fail;
4293 // Rt2
4294 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4295 return MCDisassembler::Fail;
4296 // Writeback operand
4297 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4298 return MCDisassembler::Fail;
4299 // addr
4300 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4301 return MCDisassembler::Fail;
4302
4303 return S;
4304}
4305
4306static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4307DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4308 uint64_t Address, const void *Decoder) {
4309 DecodeStatus S = MCDisassembler::Success;
4310
4311 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4312 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4313 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4314 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4315 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4316 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4317 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4318 bool writeback = (W == 1) | (P == 0);
4319
4320 addr |= (U << 8) | (Rn << 9);
4321
4322 if (writeback && (Rn == Rt || Rn == Rt2))
4323 Check(S, MCDisassembler::SoftFail);
4324
4325 // Writeback operand
4326 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4327 return MCDisassembler::Fail;
4328 // Rt
4329 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4330 return MCDisassembler::Fail;
4331 // Rt2
4332 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4333 return MCDisassembler::Fail;
4334 // addr
4335 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4336 return MCDisassembler::Fail;
4337
4338 return S;
4339}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4340
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4341static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4342 uint64_t Address, const void *Decoder) {
4343 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4344 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4345 if (sign1 != sign2) return MCDisassembler::Fail;
4346
4347 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4348 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4349 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4350 Val |= sign1 << 12;
4351 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4352
4353 return MCDisassembler::Success;
4354}
4355
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4356static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4357 uint64_t Address,
4358 const void *Decoder) {
4359 DecodeStatus S = MCDisassembler::Success;
4360
4361 // Shift of "asr #32" is not allowed in Thumb2 mode.
4362 if (Val == 0x20) S = MCDisassembler::SoftFail;
4363 Inst.addOperand(MCOperand::CreateImm(Val));
4364 return S;
4365}
4366
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4367static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4368 uint64_t Address, const void *Decoder) {
4369 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4370 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4371 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4372 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4373
4374 if (pred == 0xF)
4375 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4376
4377 DecodeStatus S = MCDisassembler::Success;
Silviu Baranga35ee7d22012-04-18 14:18:57 +0000[diff] [blame]4378
4379 if (Rt == Rn || Rn == Rt2)
4380 S = MCDisassembler::SoftFail;
4381
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4382 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4383 return MCDisassembler::Fail;
4384 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4385 return MCDisassembler::Fail;
4386 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4387 return MCDisassembler::Fail;
4388 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4389 return MCDisassembler::Fail;
4390
4391 return S;
4392}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4393
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4394static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4395 uint64_t Address, const void *Decoder) {
4396 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4397 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4398 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4399 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4400 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4401 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4402
4403 DecodeStatus S = MCDisassembler::Success;
4404
4405 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4406 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4407 Inst.setOpcode(ARM::VMOVv2f32);
4408 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4409 }
4410
4411 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4412
4413 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4414 return MCDisassembler::Fail;
4415 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4416 return MCDisassembler::Fail;
4417 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4418
4419 return S;
4420}
4421
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4422static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4423 uint64_t Address, const void *Decoder) {
4424 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4425 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4426 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4427 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4428 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4429 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4430
4431 DecodeStatus S = MCDisassembler::Success;
4432
4433 // VMOVv4f32 is ambiguous with these decodings.
4434 if (!(imm & 0x38) && cmode == 0xF) {
4435 Inst.setOpcode(ARM::VMOVv4f32);
4436 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4437 }
4438
4439 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4440
4441 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4442 return MCDisassembler::Fail;
4443 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4444 return MCDisassembler::Fail;
4445 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4446
4447 return S;
4448}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4449
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4450static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4451 uint64_t Address, const void *Decoder) {
4452 DecodeStatus S = MCDisassembler::Success;
4453
4454 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4455 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4456 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4457 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4458 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4459
4460 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4461 S = MCDisassembler::SoftFail;
4462
4463 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4464 return MCDisassembler::Fail;
4465 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4466 return MCDisassembler::Fail;
4467 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4468 return MCDisassembler::Fail;
4469 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4470 return MCDisassembler::Fail;
4471 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4472 return MCDisassembler::Fail;
4473
4474 return S;
4475}
4476
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4477static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4478 uint64_t Address, const void *Decoder) {
4479
4480 DecodeStatus S = MCDisassembler::Success;
4481
4482 unsigned CRm = fieldFromInstruction32(Val, 0, 4);
4483 unsigned opc1 = fieldFromInstruction32(Val, 4, 4);
4484 unsigned cop = fieldFromInstruction32(Val, 8, 4);
4485 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4486 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4);
4487
4488 if ((cop & ~0x1) == 0xa)
4489 return MCDisassembler::Fail;
4490
4491 if (Rt == Rt2)
4492 S = MCDisassembler::SoftFail;
4493
4494 Inst.addOperand(MCOperand::CreateImm(cop));
4495 Inst.addOperand(MCOperand::CreateImm(opc1));
4496 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4497 return MCDisassembler::Fail;
4498 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4499 return MCDisassembler::Fail;
4500 Inst.addOperand(MCOperand::CreateImm(CRm));
4501
4502 return S;
4503}
4504