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gerrit-public.fairphone.software / platform / external / llvm / 2dd0353fec61b412e521013049d6a03de29aa8c7 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: ee329dc671ea118e647b359a0aeff33d1c5de018 [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]29#include "llvm/Support/CommandLine.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]30#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]31#include "llvm/Support/MathExtras.h"
Nick Lewycky476b2422010-12-19 20:43:38 +0000[diff] [blame]32#include <cctype>
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]33using namespace llvm;
34
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]35/// We are in the process of implementing a new TypeLegalization action
36/// - the promotion of vector elements. This feature is disabled by default
37/// and only enabled using this flag.
38static cl::opt<bool>
Nadav Rotem8fb06b32011-10-16 20:31:33 +0000[diff] [blame]39AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true),
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]40 cl::desc("Allow promotion of integer vector element types"));
41
Rafael Espindola9a580232009-02-27 13:37:18 +0000[diff] [blame]42namespace llvm {
43TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
44 bool isLocal = GV->hasLocalLinkage();
45 bool isDeclaration = GV->isDeclaration();
46 // FIXME: what should we do for protected and internal visibility?
47 // For variables, is internal different from hidden?
48 bool isHidden = GV->hasHiddenVisibility();
49
50 if (reloc == Reloc::PIC_) {
51 if (isLocal || isHidden)
52 return TLSModel::LocalDynamic;
53 else
54 return TLSModel::GeneralDynamic;
55 } else {
56 if (!isDeclaration || isHidden)
57 return TLSModel::LocalExec;
58 else
59 return TLSModel::InitialExec;
60 }
61}
62}
63
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]64/// InitLibcallNames - Set default libcall names.
65///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]66static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]67 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]68 Names[RTLIB::SHL_I32] = "__ashlsi3";
69 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]70 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]71 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]72 Names[RTLIB::SRL_I32] = "__lshrsi3";
73 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]74 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]75 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]76 Names[RTLIB::SRA_I32] = "__ashrsi3";
77 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]78 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]79 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]80 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]81 Names[RTLIB::MUL_I32] = "__mulsi3";
82 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]83 Names[RTLIB::MUL_I128] = "__multi3";
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]84 Names[RTLIB::MULO_I32] = "__mulosi4";
85 Names[RTLIB::MULO_I64] = "__mulodi4";
86 Names[RTLIB::MULO_I128] = "__muloti4";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]87 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]88 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]89 Names[RTLIB::SDIV_I32] = "__divsi3";
90 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]91 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]92 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]93 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]94 Names[RTLIB::UDIV_I32] = "__udivsi3";
95 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]96 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]97 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]98 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]99 Names[RTLIB::SREM_I32] = "__modsi3";
100 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]101 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]102 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]103 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]104 Names[RTLIB::UREM_I32] = "__umodsi3";
105 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]106 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng8e23e812011-04-01 00:42:02 +0000[diff] [blame]107
108 // These are generally not available.
109 Names[RTLIB::SDIVREM_I8] = 0;
110 Names[RTLIB::SDIVREM_I16] = 0;
111 Names[RTLIB::SDIVREM_I32] = 0;
112 Names[RTLIB::SDIVREM_I64] = 0;
113 Names[RTLIB::SDIVREM_I128] = 0;
114 Names[RTLIB::UDIVREM_I8] = 0;
115 Names[RTLIB::UDIVREM_I16] = 0;
116 Names[RTLIB::UDIVREM_I32] = 0;
117 Names[RTLIB::UDIVREM_I64] = 0;
118 Names[RTLIB::UDIVREM_I128] = 0;
119
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]120 Names[RTLIB::NEG_I32] = "__negsi2";
121 Names[RTLIB::NEG_I64] = "__negdi2";
122 Names[RTLIB::ADD_F32] = "__addsf3";
123 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]124 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]125 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]126 Names[RTLIB::SUB_F32] = "__subsf3";
127 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]128 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]129 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]130 Names[RTLIB::MUL_F32] = "__mulsf3";
131 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]132 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]133 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]134 Names[RTLIB::DIV_F32] = "__divsf3";
135 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]136 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]137 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]138 Names[RTLIB::REM_F32] = "fmodf";
139 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]140 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]141 Names[RTLIB::REM_PPCF128] = "fmodl";
Cameron Zwarich33390842011-07-08 21:39:21 +0000[diff] [blame]142 Names[RTLIB::FMA_F32] = "fmaf";
143 Names[RTLIB::FMA_F64] = "fma";
144 Names[RTLIB::FMA_F80] = "fmal";
145 Names[RTLIB::FMA_PPCF128] = "fmal";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]146 Names[RTLIB::POWI_F32] = "__powisf2";
147 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]148 Names[RTLIB::POWI_F80] = "__powixf2";
149 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]150 Names[RTLIB::SQRT_F32] = "sqrtf";
151 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]152 Names[RTLIB::SQRT_F80] = "sqrtl";
153 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]154 Names[RTLIB::LOG_F32] = "logf";
155 Names[RTLIB::LOG_F64] = "log";
156 Names[RTLIB::LOG_F80] = "logl";
157 Names[RTLIB::LOG_PPCF128] = "logl";
158 Names[RTLIB::LOG2_F32] = "log2f";
159 Names[RTLIB::LOG2_F64] = "log2";
160 Names[RTLIB::LOG2_F80] = "log2l";
161 Names[RTLIB::LOG2_PPCF128] = "log2l";
162 Names[RTLIB::LOG10_F32] = "log10f";
163 Names[RTLIB::LOG10_F64] = "log10";
164 Names[RTLIB::LOG10_F80] = "log10l";
165 Names[RTLIB::LOG10_PPCF128] = "log10l";
166 Names[RTLIB::EXP_F32] = "expf";
167 Names[RTLIB::EXP_F64] = "exp";
168 Names[RTLIB::EXP_F80] = "expl";
169 Names[RTLIB::EXP_PPCF128] = "expl";
170 Names[RTLIB::EXP2_F32] = "exp2f";
171 Names[RTLIB::EXP2_F64] = "exp2";
172 Names[RTLIB::EXP2_F80] = "exp2l";
173 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]174 Names[RTLIB::SIN_F32] = "sinf";
175 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]176 Names[RTLIB::SIN_F80] = "sinl";
177 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]178 Names[RTLIB::COS_F32] = "cosf";
179 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]180 Names[RTLIB::COS_F80] = "cosl";
181 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]182 Names[RTLIB::POW_F32] = "powf";
183 Names[RTLIB::POW_F64] = "pow";
184 Names[RTLIB::POW_F80] = "powl";
185 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]186 Names[RTLIB::CEIL_F32] = "ceilf";
187 Names[RTLIB::CEIL_F64] = "ceil";
188 Names[RTLIB::CEIL_F80] = "ceill";
189 Names[RTLIB::CEIL_PPCF128] = "ceill";
190 Names[RTLIB::TRUNC_F32] = "truncf";
191 Names[RTLIB::TRUNC_F64] = "trunc";
192 Names[RTLIB::TRUNC_F80] = "truncl";
193 Names[RTLIB::TRUNC_PPCF128] = "truncl";
194 Names[RTLIB::RINT_F32] = "rintf";
195 Names[RTLIB::RINT_F64] = "rint";
196 Names[RTLIB::RINT_F80] = "rintl";
197 Names[RTLIB::RINT_PPCF128] = "rintl";
198 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
199 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
200 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
201 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
202 Names[RTLIB::FLOOR_F32] = "floorf";
203 Names[RTLIB::FLOOR_F64] = "floor";
204 Names[RTLIB::FLOOR_F80] = "floorl";
205 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]206 Names[RTLIB::COPYSIGN_F32] = "copysignf";
207 Names[RTLIB::COPYSIGN_F64] = "copysign";
208 Names[RTLIB::COPYSIGN_F80] = "copysignl";
209 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]210 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]211 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
212 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]213 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]214 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
215 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
216 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
217 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]218 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
219 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]220 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
221 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]222 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]223 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
224 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]225 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
226 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]227 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]228 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]229 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]230 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]231 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]232 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]233 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]234 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
235 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]236 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
237 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]238 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]239 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
240 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]241 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
242 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]243 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]244 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
245 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]246 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]247 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]248 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]249 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]250 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
251 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]252 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
253 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]254 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
255 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]256 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
257 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]258 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
259 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
260 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
261 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]262 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
263 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]264 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
265 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]266 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
267 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]268 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
269 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
270 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
271 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
272 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
273 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]274 Names[RTLIB::OEQ_F32] = "__eqsf2";
275 Names[RTLIB::OEQ_F64] = "__eqdf2";
276 Names[RTLIB::UNE_F32] = "__nesf2";
277 Names[RTLIB::UNE_F64] = "__nedf2";
278 Names[RTLIB::OGE_F32] = "__gesf2";
279 Names[RTLIB::OGE_F64] = "__gedf2";
280 Names[RTLIB::OLT_F32] = "__ltsf2";
281 Names[RTLIB::OLT_F64] = "__ltdf2";
282 Names[RTLIB::OLE_F32] = "__lesf2";
283 Names[RTLIB::OLE_F64] = "__ledf2";
284 Names[RTLIB::OGT_F32] = "__gtsf2";
285 Names[RTLIB::OGT_F64] = "__gtdf2";
286 Names[RTLIB::UO_F32] = "__unordsf2";
287 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]288 Names[RTLIB::O_F32] = "__unordsf2";
289 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]290 Names[RTLIB::MEMCPY] = "memcpy";
291 Names[RTLIB::MEMMOVE] = "memmove";
292 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]293 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]294 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
295 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
296 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
297 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]298 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
299 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
300 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
301 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]302 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
303 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
304 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
305 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
306 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
307 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
308 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
309 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
310 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
311 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
312 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
313 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
314 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
315 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
316 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
317 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
318 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
319 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
Jim Grosbach312b7c92011-10-14 15:53:48 +0000[diff] [blame]320 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]321 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
322 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
323 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
324 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
325 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]326}
327
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]328/// InitLibcallCallingConvs - Set default libcall CallingConvs.
329///
330static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
331 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
332 CCs[i] = CallingConv::C;
333 }
334}
335
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]336/// getFPEXT - Return the FPEXT_*_* value for the given types, or
337/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]338RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]339 if (OpVT == MVT::f32) {
340 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]341 return FPEXT_F32_F64;
342 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]343
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]344 return UNKNOWN_LIBCALL;
345}
346
347/// getFPROUND - Return the FPROUND_*_* value for the given types, or
348/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]349RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]350 if (RetVT == MVT::f32) {
351 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]352 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]353 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]354 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]355 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]356 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]357 } else if (RetVT == MVT::f64) {
358 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]359 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]360 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]361 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]362 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]363
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]364 return UNKNOWN_LIBCALL;
365}
366
367/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
368/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]369RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]370 if (OpVT == MVT::f32) {
371 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]372 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]374 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]375 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]377 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]378 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]379 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]380 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]381 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]382 if (RetVT == MVT::i8)
383 return FPTOSINT_F64_I8;
384 if (RetVT == MVT::i16)
385 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]386 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]387 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]388 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]389 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]390 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]391 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]392 } else if (OpVT == MVT::f80) {
393 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]394 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]395 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]396 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]397 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]398 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]399 } else if (OpVT == MVT::ppcf128) {
400 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]401 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]402 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]403 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]404 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]405 return FPTOSINT_PPCF128_I128;
406 }
407 return UNKNOWN_LIBCALL;
408}
409
410/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
411/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]412RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]413 if (OpVT == MVT::f32) {
414 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]415 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]416 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]417 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]418 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]419 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]420 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]421 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]422 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]423 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]424 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]425 if (RetVT == MVT::i8)
426 return FPTOUINT_F64_I8;
427 if (RetVT == MVT::i16)
428 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]429 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]430 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]431 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]432 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]433 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]434 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]435 } else if (OpVT == MVT::f80) {
436 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]437 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]438 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]439 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]440 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]441 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]442 } else if (OpVT == MVT::ppcf128) {
443 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]444 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]445 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]446 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]447 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]448 return FPTOUINT_PPCF128_I128;
449 }
450 return UNKNOWN_LIBCALL;
451}
452
453/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
454/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]455RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]456 if (OpVT == MVT::i32) {
457 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]458 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]459 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]460 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]461 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]462 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]463 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]464 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]465 } else if (OpVT == MVT::i64) {
466 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]467 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]468 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]469 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]470 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]471 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]472 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]473 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]474 } else if (OpVT == MVT::i128) {
475 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]476 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]477 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]478 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]479 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]480 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]481 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]482 return SINTTOFP_I128_PPCF128;
483 }
484 return UNKNOWN_LIBCALL;
485}
486
487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]490 if (OpVT == MVT::i32) {
491 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]492 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]493 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]494 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]495 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]496 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]497 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]498 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]499 } else if (OpVT == MVT::i64) {
500 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]501 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]502 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]503 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]504 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]505 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]506 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]507 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]508 } else if (OpVT == MVT::i128) {
509 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]510 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]511 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]512 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]513 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]514 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]515 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]516 return UINTTOFP_I128_PPCF128;
517 }
518 return UNKNOWN_LIBCALL;
519}
520
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]521/// InitCmpLibcallCCs - Set default comparison libcall CC.
522///
523static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
524 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
525 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
526 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
527 CCs[RTLIB::UNE_F32] = ISD::SETNE;
528 CCs[RTLIB::UNE_F64] = ISD::SETNE;
529 CCs[RTLIB::OGE_F32] = ISD::SETGE;
530 CCs[RTLIB::OGE_F64] = ISD::SETGE;
531 CCs[RTLIB::OLT_F32] = ISD::SETLT;
532 CCs[RTLIB::OLT_F64] = ISD::SETLT;
533 CCs[RTLIB::OLE_F32] = ISD::SETLE;
534 CCs[RTLIB::OLE_F64] = ISD::SETLE;
535 CCs[RTLIB::OGT_F32] = ISD::SETGT;
536 CCs[RTLIB::OGT_F64] = ISD::SETGT;
537 CCs[RTLIB::UO_F32] = ISD::SETNE;
538 CCs[RTLIB::UO_F64] = ISD::SETNE;
539 CCs[RTLIB::O_F32] = ISD::SETEQ;
540 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]541}
542
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]543/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]544TargetLowering::TargetLowering(const TargetMachine &tm,
545 const TargetLoweringObjectFile *tlof)
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]546 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
547 mayPromoteElements(AllowPromoteIntElem) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]548 // All operations default to being supported.
549 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]550 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]551 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]552 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]553 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]554
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]555 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]556 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]557 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]558 for (unsigned IM = (unsigned)ISD::PRE_INC;
559 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]560 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
561 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]562 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]563
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]564 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]565 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]567 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]568
569 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]570 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]571
572 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]573 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]574 // to optimize expansions for certain constants.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]575 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
576 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
577 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]578
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]579 // These library functions default to expand.
Owen Anderson4a4fdf32011-12-08 19:32:14 +0000[diff] [blame]580 setOperationAction(ISD::FLOG , MVT::f64, Expand);
581 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
582 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
583 setOperationAction(ISD::FEXP , MVT::f64, Expand);
584 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
585 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
586 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
587 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
588 setOperationAction(ISD::FRINT, MVT::f64, Expand);
589 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
590 setOperationAction(ISD::FLOG , MVT::f32, Expand);
591 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
592 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
593 setOperationAction(ISD::FEXP , MVT::f32, Expand);
594 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
595 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
596 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
597 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
598 setOperationAction(ISD::FRINT, MVT::f32, Expand);
599 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]600
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]601 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]602 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]603
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]604 IsLittleEndian = TD->isLittleEndian();
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]605 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]606 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]607 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]608 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng05219282011-01-06 06:52:41 +0000[diff] [blame]609 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
610 = maxStoresPerMemmoveOptSize = 4;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]611 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]612 UseUnderscoreSetJmp = false;
613 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]614 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]615 IntDivIsCheap = false;
616 Pow2DivIsCheap = false;
Chris Lattnerde189be2010-11-30 18:12:52 +0000[diff] [blame]617 JumpIsExpensive = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]618 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]619 ExceptionPointerRegister = 0;
620 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]621 BooleanContents = UndefinedBooleanContent;
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]622 BooleanVectorContents = UndefinedBooleanContent;
Dan Gohman8c2d2702011-10-24 17:45:02 +0000[diff] [blame]623 SchedPreferenceInfo = Sched::ILP;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]624 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]625 JumpBufAlignment = 0;
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000[diff] [blame]626 MinFunctionAlignment = 0;
627 PrefFunctionAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]628 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]629 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]630 ShouldFoldAtomicFences = false;
Eli Friedman26689ac2011-08-03 21:06:02 +0000[diff] [blame]631 InsertFencesForAtomic = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]632
633 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]634 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]635 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]636}
637
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]638TargetLowering::~TargetLowering() {
639 delete &TLOF;
640}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]641
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]642MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
643 return MVT::getIntegerVT(8*TD->getPointerSize());
644}
645
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]646/// canOpTrap - Returns true if the operation can trap for the value type.
647/// VT must be a legal type.
648bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
649 assert(isTypeLegal(VT));
650 switch (Op) {
651 default:
652 return false;
653 case ISD::FDIV:
654 case ISD::FREM:
655 case ISD::SDIV:
656 case ISD::UDIV:
657 case ISD::SREM:
658 case ISD::UREM:
659 return true;
660 }
661}
662
663
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]664static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]665 unsigned &NumIntermediates,
666 EVT &RegisterVT,
667 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]668 // Figure out the right, legal destination reg to copy into.
669 unsigned NumElts = VT.getVectorNumElements();
670 MVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]671
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]672 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]673
674 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]675 // could break down into LHS/RHS like LegalizeDAG does.
676 if (!isPowerOf2_32(NumElts)) {
677 NumVectorRegs = NumElts;
678 NumElts = 1;
679 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]680
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]681 // Divide the input until we get to a supported size. This will always
682 // end with a scalar if the target doesn't support vectors.
683 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
684 NumElts >>= 1;
685 NumVectorRegs <<= 1;
686 }
687
688 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]689
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]690 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
691 if (!TLI->isTypeLegal(NewVT))
692 NewVT = EltTy;
693 IntermediateVT = NewVT;
694
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]695 unsigned NewVTSize = NewVT.getSizeInBits();
696
697 // Convert sizes such as i33 to i64.
698 if (!isPowerOf2_32(NewVTSize))
699 NewVTSize = NextPowerOf2(NewVTSize);
700
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]701 EVT DestVT = TLI->getRegisterType(NewVT);
702 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]703 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]704 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]705
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]706 // Otherwise, promotion or legal types use the same number of registers as
707 // the vector decimated to the appropriate level.
708 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]709}
710
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]711/// isLegalRC - Return true if the value types that can be represented by the
712/// specified register class are all legal.
713bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
714 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
715 I != E; ++I) {
716 if (isTypeLegal(*I))
717 return true;
718 }
719 return false;
720}
721
722/// hasLegalSuperRegRegClasses - Return true if the specified register class
723/// has one or more super-reg register classes that are legal.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]724bool
725TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]726 if (*RC->superregclasses_begin() == 0)
727 return false;
728 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
729 E = RC->superregclasses_end(); I != E; ++I) {
730 const TargetRegisterClass *RRC = *I;
731 if (isLegalRC(RRC))
732 return true;
733 }
734 return false;
735}
736
737/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]738/// of the register class for the specified type and its associated "cost".
739std::pair<const TargetRegisterClass*, uint8_t>
740TargetLowering::findRepresentativeClass(EVT VT) const {
741 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
742 if (!RC)
743 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]744 const TargetRegisterClass *BestRC = RC;
745 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
746 E = RC->superregclasses_end(); I != E; ++I) {
747 const TargetRegisterClass *RRC = *I;
748 if (RRC->isASubClass() || !isLegalRC(RRC))
749 continue;
750 if (!hasLegalSuperRegRegClasses(RRC))
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]751 return std::make_pair(RRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]752 BestRC = RRC;
753 }
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]754 return std::make_pair(BestRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]755}
756
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]757
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]758/// computeRegisterProperties - Once all of the register classes are added,
759/// this allows us to compute derived properties we expose.
760void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]761 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]762 "Too many value types for ValueTypeActions to hold!");
763
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]764 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]765 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]766 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]767 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]768 }
769 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]770 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]771
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]772 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]773 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]774 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]775 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]776
777 // Every integer value type larger than this largest register takes twice as
778 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]779 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]780 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
781 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]782 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]783 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]784 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
785 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]786 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]787 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]788
789 // Inspect all of the ValueType's smaller than the largest integer
790 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]791 unsigned LegalIntReg = LargestIntReg;
792 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]793 IntReg >= (unsigned)MVT::i1; --IntReg) {
794 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]795 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]796 LegalIntReg = IntReg;
797 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]798 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]799 (MVT::SimpleValueType)LegalIntReg;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]800 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]801 }
802 }
803
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]804 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]805 if (!isTypeLegal(MVT::ppcf128)) {
806 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
807 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
808 TransformToType[MVT::ppcf128] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]809 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]810 }
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]811
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]812 // Decide how to handle f64. If the target does not have native f64 support,
813 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]814 if (!isTypeLegal(MVT::f64)) {
815 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
816 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
817 TransformToType[MVT::f64] = MVT::i64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]818 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]819 }
820
821 // Decide how to handle f32. If the target does not have native support for
822 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]823 if (!isTypeLegal(MVT::f32)) {
824 if (isTypeLegal(MVT::f64)) {
825 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
826 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
827 TransformToType[MVT::f32] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]828 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]829 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]830 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
831 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
832 TransformToType[MVT::f32] = MVT::i32;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]833 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]834 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]835 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]836
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]837 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]838 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
839 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]840 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]841 if (isTypeLegal(VT)) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]842
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]843 // Determine if there is a legal wider type. If so, we should promote to
844 // that wider vector type.
845 EVT EltVT = VT.getVectorElementType();
846 unsigned NElts = VT.getVectorNumElements();
847 if (NElts != 1) {
848 bool IsLegalWiderType = false;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]849 // If we allow the promotion of vector elements using a flag,
850 // then return TypePromoteInteger on vector elements.
851 // First try to promote the elements of integer vectors. If no legal
852 // promotion was found, fallback to the widen-vector method.
853 if (mayPromoteElements)
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]854 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
855 EVT SVT = (MVT::SimpleValueType)nVT;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]856 // Promote vectors of integers to vectors with the same number
857 // of elements, with a wider element type.
858 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
859 && SVT.getVectorNumElements() == NElts &&
860 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
861 TransformToType[i] = SVT;
862 RegisterTypeForVT[i] = SVT;
863 NumRegistersForVT[i] = 1;
864 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
865 IsLegalWiderType = true;
866 break;
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]867 }
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]868 }
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]869
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]870 if (IsLegalWiderType) continue;
871
872 // Try to widen the vector.
873 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
874 EVT SVT = (MVT::SimpleValueType)nVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]875 if (SVT.getVectorElementType() == EltVT &&
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]876 SVT.getVectorNumElements() > NElts &&
Dale Johannesene93d99c2010-10-20 21:32:10 +0000[diff] [blame]877 isTypeLegal(SVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]878 TransformToType[i] = SVT;
879 RegisterTypeForVT[i] = SVT;
880 NumRegistersForVT[i] = 1;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]881 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]882 IsLegalWiderType = true;
883 break;
884 }
885 }
886 if (IsLegalWiderType) continue;
887 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]888
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]889 MVT IntermediateVT;
890 EVT RegisterVT;
891 unsigned NumIntermediates;
892 NumRegistersForVT[i] =
893 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
894 RegisterVT, this);
895 RegisterTypeForVT[i] = RegisterVT;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]896
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]897 EVT NVT = VT.getPow2VectorType();
898 if (NVT == VT) {
899 // Type is already a power of 2. The default action is to split.
900 TransformToType[i] = MVT::Other;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]901 unsigned NumElts = VT.getVectorNumElements();
902 ValueTypeActions.setTypeAction(VT,
903 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]904 } else {
905 TransformToType[i] = NVT;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]906 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]907 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]908 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]909
910 // Determine the 'representative' register class for each value type.
911 // An representative register class is the largest (meaning one which is
912 // not a sub-register class / subreg register class) legal register class for
913 // a group of value types. For example, on i386, i8, i16, and i32
914 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]915 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]916 const TargetRegisterClass* RRC;
917 uint8_t Cost;
918 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
919 RepRegClassForVT[i] = RRC;
920 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]921 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]922}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]923
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]924const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
925 return NULL;
926}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]927
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]928
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]929EVT TargetLowering::getSetCCResultType(EVT VT) const {
930 assert(!VT.isVector() && "No default SetCC type for vectors!");
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]931 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]932}
933
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]934MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
935 return MVT::i32; // return the default value
936}
937
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]938/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]939/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
940/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
941/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]942///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]943/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]944/// register. It also returns the VT and quantity of the intermediate values
945/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]946///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]947unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]948 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]949 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]950 EVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]951 unsigned NumElts = VT.getVectorNumElements();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]952
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]953 // If there is a wider vector type with the same element type as this one,
954 // we should widen to that legal vector type. This handles things like
955 // <2 x float> -> <4 x float>.
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]956 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]957 RegisterVT = getTypeToTransformTo(Context, VT);
958 if (isTypeLegal(RegisterVT)) {
959 IntermediateVT = RegisterVT;
960 NumIntermediates = 1;
961 return 1;
962 }
963 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]964
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]965 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]966 EVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]967
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]968 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]969
970 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]971 // could break down into LHS/RHS like LegalizeDAG does.
972 if (!isPowerOf2_32(NumElts)) {
973 NumVectorRegs = NumElts;
974 NumElts = 1;
975 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]976
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]977 // Divide the input until we get to a supported size. This will always
978 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]979 while (NumElts > 1 && !isTypeLegal(
980 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]981 NumElts >>= 1;
982 NumVectorRegs <<= 1;
983 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]984
985 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]986
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]987 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]988 if (!isTypeLegal(NewVT))
989 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]990 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]991
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]992 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]993 RegisterVT = DestVT;
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]994 unsigned NewVTSize = NewVT.getSizeInBits();
995
996 // Convert sizes such as i33 to i64.
997 if (!isPowerOf2_32(NewVTSize))
998 NewVTSize = NextPowerOf2(NewVTSize);
999
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]1000 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1001 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1002
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]1003 // Otherwise, promotion or legal types use the same number of registers as
1004 // the vector decimated to the appropriate level.
1005 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1006}
1007
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1008/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1009/// type of the given function. This does not require a DAG or a return value,
1010/// and is suitable for use before any DAGs for the function are constructed.
1011/// TODO: Move this out of TargetLowering.cpp.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1012void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1013 SmallVectorImpl<ISD::OutputArg> &Outs,
1014 const TargetLowering &TLI,
1015 SmallVectorImpl<uint64_t> *Offsets) {
1016 SmallVector<EVT, 4> ValueVTs;
1017 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1018 unsigned NumValues = ValueVTs.size();
1019 if (NumValues == 0) return;
1020 unsigned Offset = 0;
1021
1022 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1023 EVT VT = ValueVTs[j];
1024 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1025
1026 if (attr & Attribute::SExt)
1027 ExtendKind = ISD::SIGN_EXTEND;
1028 else if (attr & Attribute::ZExt)
1029 ExtendKind = ISD::ZERO_EXTEND;
1030
1031 // FIXME: C calling convention requires the return type to be promoted to
1032 // at least 32-bit. But this is not necessary for non-C calling
1033 // conventions. The frontend should mark functions whose return values
1034 // require promoting with signext or zeroext attributes.
1035 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1036 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1037 if (VT.bitsLT(MinVT))
1038 VT = MinVT;
1039 }
1040
1041 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1042 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1043 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1044 PartVT.getTypeForEVT(ReturnType->getContext()));
1045
1046 // 'inreg' on function refers to return value
1047 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1048 if (attr & Attribute::InReg)
1049 Flags.setInReg();
1050
1051 // Propagate extension type if any
1052 if (attr & Attribute::SExt)
1053 Flags.setSExt();
1054 else if (attr & Attribute::ZExt)
1055 Flags.setZExt();
1056
1057 for (unsigned i = 0; i < NumParts; ++i) {
1058 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1059 if (Offsets) {
1060 Offsets->push_back(Offset);
1061 Offset += PartSize;
1062 }
1063 }
1064 }
1065}
1066
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1067/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1068/// function arguments in the caller parameter area. This is the actual
1069/// alignment, not its logarithm.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1070unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1071 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1072}
1073
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1074/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1075/// current function. The returned value is a member of the
1076/// MachineJumpTableInfo::JTEntryKind enum.
1077unsigned TargetLowering::getJumpTableEncoding() const {
1078 // In non-pic modes, just use the address of a block.
1079 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1080 return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1081
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1082 // In PIC mode, if the target supports a GPRel32 directive, use it.
1083 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1084 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1085
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1086 // Otherwise, use a label difference.
1087 return MachineJumpTableInfo::EK_LabelDifference32;
1088}
1089
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1090SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1091 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1092 // If our PIC model is GP relative, use the global offset table as the base.
1093 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]1094 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1095 return Table;
1096}
1097
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1098/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1099/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1100/// MCExpr.
1101const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1102TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1103 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1104 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1105 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1106}
1107
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1108bool
1109TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1110 // Assume that everything is safe in static mode.
1111 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1112 return true;
1113
1114 // In dynamic-no-pic mode, assume that known defined values are safe.
1115 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1116 GA &&
1117 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1118 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1119 return true;
1120
1121 // Otherwise assume nothing is safe.
1122 return false;
1123}
1124
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1125//===----------------------------------------------------------------------===//
1126// Optimization Methods
1127//===----------------------------------------------------------------------===//
1128
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1129/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1130/// specified instruction is a constant integer. If so, check to see if there
1131/// are any bits set in the constant that are not demanded. If so, shrink the
1132/// constant and return true.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1133bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1134 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1135 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1136
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1137 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1138 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1139 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1140 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1141 case ISD::AND:
1142 case ISD::OR: {
1143 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1144 if (!C) return false;
1145
1146 if (Op.getOpcode() == ISD::XOR &&
1147 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1148 return false;
1149
1150 // if we can expand it to have all bits set, do it
1151 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1152 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1153 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1154 DAG.getConstant(Demanded &
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1155 C->getAPIntValue(),
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1156 VT));
1157 return CombineTo(Op, New);
1158 }
1159
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1160 break;
1161 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1162 }
1163
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1164 return false;
1165}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1166
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1167/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1168/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1169/// cast, but it could be generalized for targets with other types of
1170/// implicit widening casts.
1171bool
1172TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1173 unsigned BitWidth,
1174 const APInt &Demanded,
1175 DebugLoc dl) {
1176 assert(Op.getNumOperands() == 2 &&
1177 "ShrinkDemandedOp only supports binary operators!");
1178 assert(Op.getNode()->getNumValues() == 1 &&
1179 "ShrinkDemandedOp only supports nodes with one result!");
1180
1181 // Don't do this if the node has another user, which may require the
1182 // full value.
1183 if (!Op.getNode()->hasOneUse())
1184 return false;
1185
1186 // Search for the smallest integer type with free casts to and from
1187 // Op's type. For expedience, just check power-of-2 integer types.
1188 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1189 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1190 if (!isPowerOf2_32(SmallVTBits))
1191 SmallVTBits = NextPowerOf2(SmallVTBits);
1192 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1193 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1194 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1195 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1196 // We found a type with free casts.
1197 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1198 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1199 Op.getNode()->getOperand(0)),
1200 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1201 Op.getNode()->getOperand(1)));
1202 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1203 return CombineTo(Op, Z);
1204 }
1205 }
1206 return false;
1207}
1208
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1209/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Chad Rosier8c1ec5a2011-06-11 02:27:46 +0000[diff] [blame]1210/// DemandedMask bits of the result of Op are ever used downstream. If we can
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1211/// use this information to simplify Op, create a new simplified DAG node and
1212/// return true, returning the original and new nodes in Old and New. Otherwise,
1213/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1214/// the expression (used to simplify the caller). The KnownZero/One bits may
1215/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1216bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1217 const APInt &DemandedMask,
1218 APInt &KnownZero,
1219 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1220 TargetLoweringOpt &TLO,
1221 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1222 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1223 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1224 "Mask size mismatches value type size!");
1225 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1226 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1227
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1228 // Don't know anything.
1229 KnownZero = KnownOne = APInt(BitWidth, 0);
1230
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1231 // Other users may use these bits.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1232 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1233 if (Depth != 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1234 // If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1235 // simplify things downstream.
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1236 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1237 return false;
1238 }
1239 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1240 // just set the NewMask to all bits.
1241 NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1242 } else if (DemandedMask == 0) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1243 // Not demanding any bits from Op.
1244 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1245 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1246 return false;
1247 } else if (Depth == 6) { // Limit search depth.
1248 return false;
1249 }
1250
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1251 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1252 switch (Op.getOpcode()) {
1253 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1254 // We know all of the bits for a constant!
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1255 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1256 KnownZero = ~KnownOne & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1257 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1258 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1259 // If the RHS is a constant, check to see if the LHS would be zero without
1260 // using the bits from the RHS. Below, we use knowledge about the RHS to
1261 // simplify the LHS, here we're using information from the LHS to simplify
1262 // the RHS.
1263 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1264 APInt LHSZero, LHSOne;
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1265 // Do not increment Depth here; that can cause an infinite loop.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1266 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1267 LHSZero, LHSOne, Depth);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1268 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1269 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1270 return TLO.CombineTo(Op, Op.getOperand(0));
1271 // If any of the set bits in the RHS are known zero on the LHS, shrink
1272 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1273 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1274 return true;
1275 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1276
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1277 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1278 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1279 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1280 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1281 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1282 KnownZero2, KnownOne2, TLO, Depth+1))
1283 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1284 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1285
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1286 // If all of the demanded bits are known one on one side, return the other.
1287 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1288 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1289 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1290 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1291 return TLO.CombineTo(Op, Op.getOperand(1));
1292 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1293 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1294 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1295 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1296 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1297 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1298 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1299 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1300 return true;
1301
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1302 // Output known-1 bits are only known if set in both the LHS & RHS.
1303 KnownOne &= KnownOne2;
1304 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1305 KnownZero |= KnownZero2;
1306 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1307 case ISD::OR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1308 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1309 KnownOne, TLO, Depth+1))
1310 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1311 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1312 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1313 KnownZero2, KnownOne2, TLO, Depth+1))
1314 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1315 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1316
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1317 // If all of the demanded bits are known zero on one side, return the other.
1318 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1319 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1320 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1321 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1322 return TLO.CombineTo(Op, Op.getOperand(1));
1323 // If all of the potentially set bits on one side are known to be set on
1324 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1325 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1326 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1327 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1328 return TLO.CombineTo(Op, Op.getOperand(1));
1329 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1330 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1331 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1332 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1333 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1334 return true;
1335
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1336 // Output known-0 bits are only known if clear in both the LHS & RHS.
1337 KnownZero &= KnownZero2;
1338 // Output known-1 are known to be set if set in either the LHS | RHS.
1339 KnownOne |= KnownOne2;
1340 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1341 case ISD::XOR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1342 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1343 KnownOne, TLO, Depth+1))
1344 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1345 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1346 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1347 KnownOne2, TLO, Depth+1))
1348 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1349 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1350
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1351 // If all of the demanded bits are known zero on one side, return the other.
1352 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1353 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1354 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1355 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1356 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1357 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1358 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1359 return true;
1360
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1361 // If all of the unknown bits are known to be zero on one side or the other
1362 // (but not both) turn this into an *inclusive* or.
1363 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1364 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1365 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1366 Op.getOperand(0),
1367 Op.getOperand(1)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1368
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1369 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1370 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1371 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1372 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1373
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1374 // If all of the demanded bits on one side are known, and all of the set
1375 // bits on that side are also known to be set on the other side, turn this
1376 // into an AND, as we know the bits will be cleared.
1377 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1378 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1379 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1380 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1381 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1382 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1383 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1384 }
1385 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1386
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1387 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1388 // for XOR, we prefer to force bits to 1 if they will make a -1.
1389 // if we can't force bits, try to shrink constant
1390 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1391 APInt Expanded = C->getAPIntValue() | (~NewMask);
1392 // if we can expand it to have all bits set, do it
1393 if (Expanded.isAllOnesValue()) {
1394 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1395 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1396 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1397 TLO.DAG.getConstant(Expanded, VT));
1398 return TLO.CombineTo(Op, New);
1399 }
1400 // if it already has all the bits set, nothing to change
1401 // but don't shrink either!
1402 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1403 return true;
1404 }
1405 }
1406
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1407 KnownZero = KnownZeroOut;
1408 KnownOne = KnownOneOut;
1409 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1410 case ISD::SELECT:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1411 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1412 KnownOne, TLO, Depth+1))
1413 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1414 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1415 KnownOne2, TLO, Depth+1))
1416 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1417 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1418 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1419
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1420 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1421 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1422 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1423
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1424 // Only known if known in both the LHS and RHS.
1425 KnownOne &= KnownOne2;
1426 KnownZero &= KnownZero2;
1427 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1428 case ISD::SELECT_CC:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1429 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1430 KnownOne, TLO, Depth+1))
1431 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1432 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1433 KnownOne2, TLO, Depth+1))
1434 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1435 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1436 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1437
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1438 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1439 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1440 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1441
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1442 // Only known if known in both the LHS and RHS.
1443 KnownOne &= KnownOne2;
1444 KnownZero &= KnownZero2;
1445 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1446 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1447 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1448 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1449 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1450
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1451 // If the shift count is an invalid immediate, don't do anything.
1452 if (ShAmt >= BitWidth)
1453 break;
1454
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1455 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1456 // single shift. We can do this if the bottom bits (which are shifted
1457 // out) are never demanded.
1458 if (InOp.getOpcode() == ISD::SRL &&
1459 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1460 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1461 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1462 unsigned Opc = ISD::SHL;
1463 int Diff = ShAmt-C1;
1464 if (Diff < 0) {
1465 Diff = -Diff;
1466 Opc = ISD::SRL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1467 }
1468
1469 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1470 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1471 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1472 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1473 InOp.getOperand(0), NewSA));
1474 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1475 }
1476
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1477 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1478 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1479 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1480
1481 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1482 // are not demanded. This will likely allow the anyext to be folded away.
1483 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1484 SDValue InnerOp = InOp.getNode()->getOperand(0);
1485 EVT InnerVT = InnerOp.getValueType();
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame^]1486 unsigned InnerBits = InnerVT.getSizeInBits();
1487 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1488 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]1489 EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1490 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1491 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1492 SDValue NarrowShl =
1493 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1494 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1495 return
1496 TLO.CombineTo(Op,
1497 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1498 NarrowShl));
1499 }
1500 }
1501
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1502 KnownZero <<= SA->getZExtValue();
1503 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1504 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1505 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1506 }
1507 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1508 case ISD::SRL:
1509 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1510 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1511 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1512 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1513 SDValue InOp = Op.getOperand(0);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1514
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1515 // If the shift count is an invalid immediate, don't do anything.
1516 if (ShAmt >= BitWidth)
1517 break;
1518
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1519 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1520 // single shift. We can do this if the top bits (which are shifted out)
1521 // are never demanded.
1522 if (InOp.getOpcode() == ISD::SHL &&
1523 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1524 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1525 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1526 unsigned Opc = ISD::SRL;
1527 int Diff = ShAmt-C1;
1528 if (Diff < 0) {
1529 Diff = -Diff;
1530 Opc = ISD::SHL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1531 }
1532
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1533 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1534 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1535 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1536 InOp.getOperand(0), NewSA));
1537 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1538 }
1539
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1540 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1541 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1542 KnownZero, KnownOne, TLO, Depth+1))
1543 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1544 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1545 KnownZero = KnownZero.lshr(ShAmt);
1546 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1547
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1548 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1549 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1550 }
1551 break;
1552 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1553 // If this is an arithmetic shift right and only the low-bit is set, we can
1554 // always convert this into a logical shr, even if the shift amount is
1555 // variable. The low bit of the shift cannot be an input sign bit unless
1556 // the shift amount is >= the size of the datatype, which is undefined.
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame^]1557 if (NewMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1558 return TLO.CombineTo(Op,
1559 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1560 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1561
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1562 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1563 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1564 unsigned ShAmt = SA->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1565
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1566 // If the shift count is an invalid immediate, don't do anything.
1567 if (ShAmt >= BitWidth)
1568 break;
1569
1570 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1571
1572 // If any of the demanded bits are produced by the sign extension, we also
1573 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1574 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1575 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1576 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1577
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1578 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1579 KnownZero, KnownOne, TLO, Depth+1))
1580 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1581 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1582 KnownZero = KnownZero.lshr(ShAmt);
1583 KnownOne = KnownOne.lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1584
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1585 // Handle the sign bit, adjusted to where it is now in the mask.
1586 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1587
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1588 // If the input sign bit is known to be zero, or if none of the top bits
1589 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1590 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1591 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1592 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1593 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1594 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1595 KnownOne |= HighBits;
1596 }
1597 }
1598 break;
1599 case ISD::SIGN_EXTEND_INREG: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1600 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1601
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1602 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1603 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1604 APInt NewBits =
1605 APInt::getHighBitsSet(BitWidth,
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1606 BitWidth - EVT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1607
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1608 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1609 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1610 return TLO.CombineTo(Op, Op.getOperand(0));
1611
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1612 APInt InSignBit =
1613 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1614 APInt InputDemandedBits =
1615 APInt::getLowBitsSet(BitWidth,
1616 EVT.getScalarType().getSizeInBits()) &
1617 NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1618
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1619 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1620 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1621 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1622
1623 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1624 KnownZero, KnownOne, TLO, Depth+1))
1625 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1626 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1627
1628 // If the sign bit of the input is known set or clear, then we know the
1629 // top bits of the result.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1630
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1631 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1632 if (KnownZero.intersects(InSignBit))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1633 return TLO.CombineTo(Op,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1634 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1635
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1636 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1637 KnownOne |= NewBits;
1638 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1639 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1640 KnownZero &= ~NewBits;
1641 KnownOne &= ~NewBits;
1642 }
1643 break;
1644 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1645 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1646 unsigned OperandBitWidth =
1647 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1648 APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1649
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1650 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1651 APInt NewBits =
1652 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1653 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1654 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1655 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1656 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1657
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1658 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1659 KnownZero, KnownOne, TLO, Depth+1))
1660 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1661 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1662 KnownZero = KnownZero.zext(BitWidth);
1663 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1664 KnownZero |= NewBits;
1665 break;
1666 }
1667 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1668 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1669 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1670 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1671 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1672 APInt NewBits = ~InMask & NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1673
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1674 // If none of the top bits are demanded, convert this into an any_extend.
1675 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1676 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1677 Op.getValueType(),
1678 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1679
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1680 // Since some of the sign extended bits are demanded, we know that the sign
1681 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1682 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1683 InDemandedBits |= InSignBit;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1684 InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1685
1686 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1687 KnownOne, TLO, Depth+1))
1688 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1689 KnownZero = KnownZero.zext(BitWidth);
1690 KnownOne = KnownOne.zext(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1691
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1692 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1693 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1694 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1695 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1696 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1697
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1698 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1699 if (KnownOne.intersects(InSignBit)) {
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1700 KnownOne |= NewBits;
1701 KnownZero &= ~NewBits;
1702 } else { // Otherwise, top bits aren't known.
1703 KnownOne &= ~NewBits;
1704 KnownZero &= ~NewBits;
1705 }
1706 break;
1707 }
1708 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1709 unsigned OperandBitWidth =
1710 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1711 APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1712 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1713 KnownZero, KnownOne, TLO, Depth+1))
1714 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1715 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1716 KnownZero = KnownZero.zext(BitWidth);
1717 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1718 break;
1719 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1720 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1721 // Simplify the input, using demanded bit information, and compute the known
1722 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1723 unsigned OperandBitWidth =
1724 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1725 APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1726 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1727 KnownZero, KnownOne, TLO, Depth+1))
1728 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1729 KnownZero = KnownZero.trunc(BitWidth);
1730 KnownOne = KnownOne.trunc(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1731
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1732 // If the input is only used by this truncate, see if we can shrink it based
1733 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1734 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1735 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1736 switch (In.getOpcode()) {
1737 default: break;
1738 case ISD::SRL:
1739 // Shrink SRL by a constant if none of the high bits shifted in are
1740 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1741 if (TLO.LegalTypes() &&
1742 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1743 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1744 // undesirable.
1745 break;
1746 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1747 if (!ShAmt)
1748 break;
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1749 SDValue Shift = In.getOperand(1);
1750 if (TLO.LegalTypes()) {
1751 uint64_t ShVal = ShAmt->getZExtValue();
1752 Shift =
1753 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1754 }
1755
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1756 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1757 OperandBitWidth - BitWidth);
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1758 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1759
1760 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1761 // None of the shifted in bits are needed. Add a truncate of the
1762 // shift input, then shift it.
1763 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1764 Op.getValueType(),
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1765 In.getOperand(0));
1766 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1767 Op.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1768 NewTrunc,
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1769 Shift));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1770 }
1771 break;
1772 }
1773 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1774
1775 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1776 break;
1777 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1778 case ISD::AssertZext: {
Owen Anderson7ab15f62011-09-03 00:26:49 +0000[diff] [blame]1779 // AssertZext demands all of the high bits, plus any of the low bits
1780 // demanded by its users.
1781 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1782 APInt InMask = APInt::getLowBitsSet(BitWidth,
1783 VT.getSizeInBits());
1784 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1785 KnownZero, KnownOne, TLO, Depth+1))
1786 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1787 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1788
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1789 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1790 break;
1791 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1792 case ISD::BITCAST:
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1793 // If this is an FP->Int bitcast and if the sign bit is the only
1794 // thing demanded, turn this into a FGETSIGN.
Eli Friedman0948f0a2011-11-09 22:25:12 +0000[diff] [blame]1795 if (!Op.getValueType().isVector() &&
1796 !Op.getOperand(0).getValueType().isVector() &&
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1797 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1798 Op.getOperand(0).getValueType().isFloatingPoint()) {
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1799 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1800 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1801 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1802 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1803 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1804 // place. We expect the SHL to be eliminated by other optimizations.
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1805 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1806 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1807 if (!OpVTLegal && OpVTSizeInBits > 32)
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1808 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1809 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Stuart Hastingsbdce3722011-06-01 14:04:17 +0000[diff] [blame]1810 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Stuart Hastings3dfc4b122011-05-19 18:48:20 +0000[diff] [blame]1811 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1812 Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1813 Sign, ShAmt));
1814 }
1815 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1816 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1817 case ISD::ADD:
1818 case ISD::MUL:
1819 case ISD::SUB: {
1820 // Add, Sub, and Mul don't demand any bits in positions beyond that
1821 // of the highest bit demanded of them.
1822 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1823 BitWidth - NewMask.countLeadingZeros());
1824 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1825 KnownOne2, TLO, Depth+1))
1826 return true;
1827 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1828 KnownOne2, TLO, Depth+1))
1829 return true;
1830 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1831 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1832 return true;
1833 }
1834 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1835 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1836 // Just use ComputeMaskedBits to compute output bits.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1837 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1838 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1839 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1840
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1841 // If we know the value of all of the demanded bits, return this as a
1842 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1843 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1844 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1845
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1846 return false;
1847}
1848
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1849/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1850/// in Mask are known to be either zero or one and return them in the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1851/// KnownZero/KnownOne bitsets.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1852void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1853 const APInt &Mask,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1854 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1855 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1856 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1857 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1858 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1859 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1860 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1861 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1862 "Should use MaskedValueIsZero if you don't know whether Op"
1863 " is a target node!");
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1864 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1865}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1866
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1867/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1868/// targets that want to expose additional information about sign bits to the
1869/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1870unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1871 unsigned Depth) const {
1872 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1873 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1874 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1875 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1876 "Should use ComputeNumSignBits if you don't know whether Op"
1877 " is a target node!");
1878 return 1;
1879}
1880
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1881/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1882/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1883/// determine which bit is set.
1884///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1885static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1886 // A left-shift of a constant one will have exactly one bit set, because
1887 // shifting the bit off the end is undefined.
1888 if (Val.getOpcode() == ISD::SHL)
1889 if (ConstantSDNode *C =
1890 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1891 if (C->getAPIntValue() == 1)
1892 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1893
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1894 // Similarly, a right-shift of a constant sign-bit will have exactly
1895 // one bit set.
1896 if (Val.getOpcode() == ISD::SRL)
1897 if (ConstantSDNode *C =
1898 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1899 if (C->getAPIntValue().isSignBit())
1900 return true;
1901
1902 // More could be done here, though the above checks are enough
1903 // to handle some common cases.
1904
1905 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1906 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1907 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1908 APInt Mask = APInt::getAllOnesValue(BitWidth);
1909 APInt KnownZero, KnownOne;
1910 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1911 return (KnownZero.countPopulation() == BitWidth - 1) &&
1912 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1913}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1914
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1915/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1916/// and cc. If it is unable to simplify it, return a null SDValue.
1917SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1918TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1919 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1920 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1921 SelectionDAG &DAG = DCI.DAG;
1922
1923 // These setcc operations always fold.
1924 switch (Cond) {
1925 default: break;
1926 case ISD::SETFALSE:
1927 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1928 case ISD::SETTRUE:
1929 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1930 }
1931
Chris Lattner7a2bdde2011-04-15 05:18:47 +0000[diff] [blame]1932 // Ensure that the constant occurs on the RHS, and fold constant
1933 // comparisons.
1934 if (isa<ConstantSDNode>(N0.getNode()))
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1935 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]1936
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1937 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1938 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1939
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1940 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1941 // equality comparison, then we're just comparing whether X itself is
1942 // zero.
1943 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1944 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1945 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1946 const APInt &ShAmt
1947 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1948 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1949 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1950 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1951 // (srl (ctlz x), 5) == 0 -> X != 0
1952 // (srl (ctlz x), 5) != 1 -> X != 0
1953 Cond = ISD::SETNE;
1954 } else {
1955 // (srl (ctlz x), 5) != 0 -> X == 0
1956 // (srl (ctlz x), 5) == 1 -> X == 0
1957 Cond = ISD::SETEQ;
1958 }
1959 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1960 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1961 Zero, Cond);
1962 }
1963 }
1964
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1965 SDValue CTPOP = N0;
1966 // Look through truncs that don't change the value of a ctpop.
1967 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1968 CTPOP = N0.getOperand(0);
1969
1970 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramerc9b6a3e2011-01-17 18:00:28 +0000[diff] [blame]1971 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1972 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1973 EVT CTVT = CTPOP.getValueType();
1974 SDValue CTOp = CTPOP.getOperand(0);
1975
1976 // (ctpop x) u< 2 -> (x & x-1) == 0
1977 // (ctpop x) u> 1 -> (x & x-1) != 0
1978 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1979 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1980 DAG.getConstant(1, CTVT));
1981 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1982 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1983 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1984 }
1985
1986 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1987 }
1988
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]1989 // (zext x) == C --> x == (trunc C)
1990 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1991 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1992 unsigned MinBits = N0.getValueSizeInBits();
1993 SDValue PreZExt;
1994 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1995 // ZExt
1996 MinBits = N0->getOperand(0).getValueSizeInBits();
1997 PreZExt = N0->getOperand(0);
1998 } else if (N0->getOpcode() == ISD::AND) {
1999 // DAGCombine turns costly ZExts into ANDs
2000 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2001 if ((C->getAPIntValue()+1).isPowerOf2()) {
2002 MinBits = C->getAPIntValue().countTrailingOnes();
2003 PreZExt = N0->getOperand(0);
2004 }
2005 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2006 // ZEXTLOAD
2007 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2008 MinBits = LN0->getMemoryVT().getSizeInBits();
2009 PreZExt = N0;
2010 }
2011 }
2012
2013 // Make sure we're not loosing bits from the constant.
2014 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2015 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2016 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2017 // Will get folded away.
2018 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2019 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2020 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2021 }
2022 }
2023 }
2024
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2025 // If the LHS is '(and load, const)', the RHS is 0,
2026 // the test is for equality or unsigned, and all 1 bits of the const are
2027 // in the same partial word, see if we can shorten the load.
2028 if (DCI.isBeforeLegalize() &&
2029 N0.getOpcode() == ISD::AND && C1 == 0 &&
2030 N0.getNode()->hasOneUse() &&
2031 isa<LoadSDNode>(N0.getOperand(0)) &&
2032 N0.getOperand(0).getNode()->hasOneUse() &&
2033 isa<ConstantSDNode>(N0.getOperand(1))) {
2034 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2035 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2036 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2037 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2038 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2039 unsigned maskWidth = origWidth;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2040 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2041 // 8 bits, but have to be careful...
2042 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2043 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2044 const APInt &Mask =
2045 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2046 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2047 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2048 for (unsigned offset=0; offset<origWidth/width; offset++) {
2049 if ((newMask & Mask) == Mask) {
2050 if (!TD->isLittleEndian())
2051 bestOffset = (origWidth/width - offset - 1) * (width/8);
2052 else
2053 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2054 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2055 bestWidth = width;
2056 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2057 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2058 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2059 }
2060 }
2061 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2062 if (bestWidth) {
Chris Lattnerc0c7fca2011-04-14 04:12:47 +0000[diff] [blame]2063 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2064 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2065 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2066 SDValue Ptr = Lod->getBasePtr();
2067 if (bestOffset != 0)
2068 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2069 DAG.getConstant(bestOffset, PtrType));
2070 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2071 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattnerecf42c42010-09-21 16:36:31 +0000[diff] [blame]2072 Lod->getPointerInfo().getWithOffset(bestOffset),
Pete Cooperd752e0f2011-11-08 18:42:53 +0000[diff] [blame]2073 false, false, false, NewAlign);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2074 return DAG.getSetCC(dl, VT,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2075 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2076 DAG.getConstant(bestMask.trunc(bestWidth),
2077 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2078 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2079 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2080 }
2081 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2082
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2083 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2084 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2085 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2086
2087 // If the comparison constant has bits in the upper part, the
2088 // zero-extended value could never match.
2089 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2090 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2091 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2092 case ISD::SETUGT:
2093 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2094 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2095 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2096 case ISD::SETULE:
2097 case ISD::SETNE: return DAG.getConstant(1, VT);
2098 case ISD::SETGT:
2099 case ISD::SETGE:
2100 // True if the sign bit of C1 is set.
2101 return DAG.getConstant(C1.isNegative(), VT);
2102 case ISD::SETLT:
2103 case ISD::SETLE:
2104 // True if the sign bit of C1 isn't set.
2105 return DAG.getConstant(C1.isNonNegative(), VT);
2106 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]2107 break;
2108 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2109 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2110
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2111 // Otherwise, we can perform the comparison with the low bits.
2112 switch (Cond) {
2113 case ISD::SETEQ:
2114 case ISD::SETNE:
2115 case ISD::SETUGT:
2116 case ISD::SETUGE:
2117 case ISD::SETULT:
2118 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2119 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2120 if (DCI.isBeforeLegalizeOps() ||
2121 (isOperationLegal(ISD::SETCC, newVT) &&
2122 getCondCodeAction(Cond, newVT)==Legal))
2123 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]2124 DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2125 Cond);
2126 break;
2127 }
2128 default:
2129 break; // todo, be more careful with signed comparisons
2130 }
2131 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2132 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2133 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2134 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2135 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2136 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2137
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]2138 // If the constant doesn't fit into the number of bits for the source of
2139 // the sign extension, it is impossible for both sides to be equal.
2140 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2141 return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2142
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2143 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2144 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2145 if (Op0Ty == ExtSrcTy) {
2146 ZextOp = N0.getOperand(0);
2147 } else {
2148 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2149 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2150 DAG.getConstant(Imm, Op0Ty));
2151 }
2152 if (!DCI.isCalledByLegalizer())
2153 DCI.AddToWorklist(ZextOp.getNode());
2154 // Otherwise, make this a use of a zext.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2155 return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2156 DAG.getConstant(C1 & APInt::getLowBitsSet(
2157 ExtDstTyBits,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2158 ExtSrcTyBits),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2159 ExtDstTy),
2160 Cond);
2161 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2162 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2163 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2164 if (N0.getOpcode() == ISD::SETCC &&
2165 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2166 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2167 if (TrueWhenTrue)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2168 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2169 // Invert the condition.
2170 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2171 CC = ISD::getSetCCInverse(CC,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2172 N0.getOperand(0).getValueType().isInteger());
2173 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2174 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2175
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2176 if ((N0.getOpcode() == ISD::XOR ||
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2177 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2178 N0.getOperand(0).getOpcode() == ISD::XOR &&
2179 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2180 isa<ConstantSDNode>(N0.getOperand(1)) &&
2181 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2182 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2183 // can only do this if the top bits are known zero.
2184 unsigned BitWidth = N0.getValueSizeInBits();
2185 if (DAG.MaskedValueIsZero(N0,
2186 APInt::getHighBitsSet(BitWidth,
2187 BitWidth-1))) {
2188 // Okay, get the un-inverted input value.
2189 SDValue Val;
2190 if (N0.getOpcode() == ISD::XOR)
2191 Val = N0.getOperand(0);
2192 else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2193 assert(N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2194 N0.getOperand(0).getOpcode() == ISD::XOR);
2195 // ((X^1)&1)^1 -> X & 1
2196 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2197 N0.getOperand(0).getOperand(0),
2198 N0.getOperand(1));
2199 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2200
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2201 return DAG.getSetCC(dl, VT, Val, N1,
2202 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2203 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2204 } else if (N1C->getAPIntValue() == 1 &&
2205 (VT == MVT::i1 ||
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]2206 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2207 SDValue Op0 = N0;
2208 if (Op0.getOpcode() == ISD::TRUNCATE)
2209 Op0 = Op0.getOperand(0);
2210
2211 if ((Op0.getOpcode() == ISD::XOR) &&
2212 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2213 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2214 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2215 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2216 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2217 Cond);
2218 } else if (Op0.getOpcode() == ISD::AND &&
2219 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2220 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2221 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2222 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2223 Op0 = DAG.getNode(ISD::AND, dl, VT,
2224 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2225 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2226 else if (Op0.getValueType().bitsLT(VT))
2227 Op0 = DAG.getNode(ISD::AND, dl, VT,
2228 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2229 DAG.getConstant(1, VT));
2230
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2231 return DAG.getSetCC(dl, VT, Op0,
2232 DAG.getConstant(0, Op0.getValueType()),
2233 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2234 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2235 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2236 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2237
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2238 APInt MinVal, MaxVal;
2239 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2240 if (ISD::isSignedIntSetCC(Cond)) {
2241 MinVal = APInt::getSignedMinValue(OperandBitSize);
2242 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2243 } else {
2244 MinVal = APInt::getMinValue(OperandBitSize);
2245 MaxVal = APInt::getMaxValue(OperandBitSize);
2246 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2247
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2248 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2249 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2250 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2251 // X >= C0 --> X > (C0-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2252 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2253 DAG.getConstant(C1-1, N1.getValueType()),
2254 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2255 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2256
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2257 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2258 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2259 // X <= C0 --> X < (C0+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2260 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2261 DAG.getConstant(C1+1, N1.getValueType()),
2262 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2263 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2264
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2265 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2266 return DAG.getConstant(0, VT); // X < MIN --> false
2267 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2268 return DAG.getConstant(1, VT); // X >= MIN --> true
2269 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2270 return DAG.getConstant(0, VT); // X > MAX --> false
2271 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2272 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2273
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2274 // Canonicalize setgt X, Min --> setne X, Min
2275 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2276 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2277 // Canonicalize setlt X, Max --> setne X, Max
2278 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2279 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2280
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2281 // If we have setult X, 1, turn it into seteq X, 0
2282 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2283 return DAG.getSetCC(dl, VT, N0,
2284 DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2285 ISD::SETEQ);
2286 // If we have setugt X, Max-1, turn it into seteq X, Max
2287 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2288 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2289 DAG.getConstant(MaxVal, N0.getValueType()),
2290 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2291
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2292 // If we have "setcc X, C0", check to see if we can shrink the immediate
2293 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2294
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2295 // SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2296 if (Cond == ISD::SETUGT &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2297 C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2298 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2299 DAG.getConstant(0, N1.getValueType()),
2300 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2301
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2302 // SETULT X, SINTMIN -> SETGT X, -1
2303 if (Cond == ISD::SETULT &&
2304 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2305 SDValue ConstMinusOne =
2306 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2307 N1.getValueType());
2308 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2309 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2310
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2311 // Fold bit comparisons when we can.
2312 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2313 (VT == N0.getValueType() ||
2314 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2315 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2316 if (ConstantSDNode *AndRHS =
2317 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2318 EVT ShiftTy = DCI.isBeforeLegalize() ?
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2319 getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2320 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2321 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2322 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2323 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2324 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2325 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2326 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2327 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2328 // (X & 8) == 8 --> (X & 8) >> 3
2329 // Perform the xform if C1 is a single bit.
2330 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2331 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2332 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2333 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2334 }
2335 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2336 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2337 }
2338
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2339 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2340 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2341 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2342 if (O.getNode()) return O;
2343 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2344 // If the RHS of an FP comparison is a constant, simplify it away in
2345 // some cases.
2346 if (CFP->getValueAPF().isNaN()) {
2347 // If an operand is known to be a nan, we can fold it.
2348 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2349 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2350 case 0: // Known false.
2351 return DAG.getConstant(0, VT);
2352 case 1: // Known true.
2353 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2354 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2355 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2356 }
2357 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2358
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2359 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2360 // constant if knowing that the operand is non-nan is enough. We prefer to
2361 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2362 // materialize 0.0.
2363 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2364 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2365
2366 // If the condition is not legal, see if we can find an equivalent one
2367 // which is legal.
2368 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2369 // If the comparison was an awkward floating-point == or != and one of
2370 // the comparison operands is infinity or negative infinity, convert the
2371 // condition to a less-awkward <= or >=.
2372 if (CFP->getValueAPF().isInfinity()) {
2373 if (CFP->getValueAPF().isNegative()) {
2374 if (Cond == ISD::SETOEQ &&
2375 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2376 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2377 if (Cond == ISD::SETUEQ &&
2378 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2379 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2380 if (Cond == ISD::SETUNE &&
2381 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2382 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2383 if (Cond == ISD::SETONE &&
2384 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2385 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2386 } else {
2387 if (Cond == ISD::SETOEQ &&
2388 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2389 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2390 if (Cond == ISD::SETUEQ &&
2391 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2392 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2393 if (Cond == ISD::SETUNE &&
2394 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2395 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2396 if (Cond == ISD::SETONE &&
2397 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2398 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2399 }
2400 }
2401 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2402 }
2403
2404 if (N0 == N1) {
2405 // We can always fold X == X for integer setcc's.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2406 if (N0.getValueType().isInteger())
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2407 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2408 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2409 if (UOF == 2) // FP operators that are undefined on NaNs.
2410 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2411 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2412 return DAG.getConstant(UOF, VT);
2413 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2414 // if it is not already.
2415 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2416 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2417 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2418 }
2419
2420 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2421 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2422 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2423 N0.getOpcode() == ISD::XOR) {
2424 // Simplify (X+Y) == (X+Z) --> Y == Z
2425 if (N0.getOpcode() == N1.getOpcode()) {
2426 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2427 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2428 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2429 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2430 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2431 // If X op Y == Y op X, try other combinations.
2432 if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2433 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2434 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2435 if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2436 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2437 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2438 }
2439 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2440
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2441 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2442 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2443 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2444 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2445 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2446 DAG.getConstant(RHSC->getAPIntValue()-
2447 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2448 N0.getValueType()), Cond);
2449 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2450
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2451 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2452 if (N0.getOpcode() == ISD::XOR)
2453 // If we know that all of the inverted bits are zero, don't bother
2454 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2455 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2456 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2457 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2458 DAG.getConstant(LHSR->getAPIntValue() ^
2459 RHSC->getAPIntValue(),
2460 N0.getValueType()),
2461 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2462 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2463
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2464 // Turn (C1-X) == C2 --> X == C1-C2
2465 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2466 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2467 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2468 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2469 DAG.getConstant(SUBC->getAPIntValue() -
2470 RHSC->getAPIntValue(),
2471 N0.getValueType()),
2472 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2473 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2474 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2475 }
2476
2477 // Simplify (X+Z) == X --> Z == 0
2478 if (N0.getOperand(0) == N1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2479 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2480 DAG.getConstant(0, N0.getValueType()), Cond);
2481 if (N0.getOperand(1) == N1) {
2482 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2483 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2484 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2485 else if (N0.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2486 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2487 // (Z-X) == X --> Z == X<<1
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2488 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2489 N1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2490 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2491 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2492 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2493 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2494 }
2495 }
2496 }
2497
2498 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2499 N1.getOpcode() == ISD::XOR) {
2500 // Simplify X == (X+Z) --> Z == 0
2501 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2502 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2503 DAG.getConstant(0, N1.getValueType()), Cond);
2504 } else if (N1.getOperand(1) == N0) {
2505 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2506 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2507 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2508 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2509 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2510 // X == (Z-X) --> X<<1 == Z
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2511 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2512 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2513 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2514 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2515 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2516 }
2517 }
2518 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2519
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2520 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2521 // Note that where y is variable and is known to have at most
2522 // one bit set (for example, if it is z&1) we cannot do this;
2523 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2524 if (N0.getOpcode() == ISD::AND)
2525 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2526 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2527 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2528 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2529 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2530 }
2531 }
2532 if (N1.getOpcode() == ISD::AND)
2533 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2534 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2535 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2536 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2537 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2538 }
2539 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2540 }
2541
2542 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2543 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2544 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2545 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2546 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2547 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2548 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2549 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2550 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2551 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2552 break;
2553 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2554 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2555 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2556 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2557 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2558 Temp = DAG.getNOT(dl, N0, MVT::i1);
2559 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2560 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2561 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2562 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2563 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2564 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2565 Temp = DAG.getNOT(dl, N1, MVT::i1);
2566 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2567 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2568 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2569 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2570 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2571 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2572 Temp = DAG.getNOT(dl, N0, MVT::i1);
2573 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2574 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2575 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2576 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2577 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2578 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2579 Temp = DAG.getNOT(dl, N1, MVT::i1);
2580 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2581 break;
2582 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2583 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2584 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2585 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2586 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2587 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2588 }
2589 return N0;
2590 }
2591
2592 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2593 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2594}
2595
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2596/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2597/// node is a GlobalAddress + offset.
Chris Lattner0a9481f2011-02-13 22:25:43 +0000[diff] [blame]2598bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2599 int64_t &Offset) const {
2600 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2601 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2602 GA = GASD->getGlobal();
2603 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2604 return true;
2605 }
2606
2607 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2608 SDValue N1 = N->getOperand(0);
2609 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2610 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2611 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2612 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2613 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2614 return true;
2615 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2616 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2617 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2618 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2619 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2620 return true;
2621 }
2622 }
2623 }
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2624
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2625 return false;
2626}
2627
2628
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2629SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2630PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2631 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2632 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2633}
2634
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2635//===----------------------------------------------------------------------===//
2636// Inline Assembler Implementation Methods
2637//===----------------------------------------------------------------------===//
2638
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2639
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2640TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2641TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2642 if (Constraint.size() == 1) {
2643 switch (Constraint[0]) {
2644 default: break;
2645 case 'r': return C_RegisterClass;
2646 case 'm': // memory
2647 case 'o': // offsetable
2648 case 'V': // not offsetable
2649 return C_Memory;
2650 case 'i': // Simple Integer or Relocatable Constant
2651 case 'n': // Simple Integer
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2652 case 'E': // Floating Point Constant
2653 case 'F': // Floating Point Constant
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2654 case 's': // Relocatable Constant
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2655 case 'p': // Address.
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2656 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2657 case 'I': // Target registers.
2658 case 'J':
2659 case 'K':
2660 case 'L':
2661 case 'M':
2662 case 'N':
2663 case 'O':
2664 case 'P':
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2665 case '<':
2666 case '>':
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2667 return C_Other;
2668 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2669 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2670
2671 if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2672 Constraint[Constraint.size()-1] == '}')
2673 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2674 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2675}
2676
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2677/// LowerXConstraint - try to replace an X constraint, which matches anything,
2678/// with another that has more specific requirements based on the type of the
2679/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2680const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2681 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2682 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2683 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2684 return "f"; // works for many targets
2685 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2686}
2687
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2688/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2689/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2690void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2691 std::string &Constraint,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2692 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2693 SelectionDAG &DAG) const {
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2694
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2695 if (Constraint.length() > 1) return;
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2696
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2697 char ConstraintLetter = Constraint[0];
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2698 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2699 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2700 case 'X': // Allows any operand; labels (basic block) use this.
2701 if (Op.getOpcode() == ISD::BasicBlock) {
2702 Ops.push_back(Op);
2703 return;
2704 }
2705 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2706 case 'i': // Simple Integer or Relocatable Constant
2707 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2708 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2709 // These operands are interested in values of the form (GV+C), where C may
2710 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2711 // is possible and fine if either GV or C are missing.
2712 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2713 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2714
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2715 // If we have "(add GV, C)", pull out GV/C
2716 if (Op.getOpcode() == ISD::ADD) {
2717 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2718 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2719 if (C == 0 || GA == 0) {
2720 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2721 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2722 }
2723 if (C == 0 || GA == 0)
2724 C = 0, GA = 0;
2725 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2726
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2727 // If we find a valid operand, map to the TargetXXX version so that the
2728 // value itself doesn't get selected.
2729 if (GA) { // Either &GV or &GV+C
2730 if (ConstraintLetter != 'n') {
2731 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2732 if (C) Offs += C->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2733 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2734 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2735 Op.getValueType(), Offs));
2736 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2737 }
2738 }
2739 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2740 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2741 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2742 // gcc prints these as sign extended. Sign extend value to 64 bits
2743 // now; without this it would get ZExt'd later in
2744 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2745 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2746 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2747 return;
2748 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2749 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2750 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2751 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2752 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2753}
2754
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2755std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2756getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2757 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2758 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2759 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2760 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2761
2762 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2763 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2764
2765 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2766 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2767 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2768 E = RI->regclass_end(); RCI != E; ++RCI) {
2769 const TargetRegisterClass *RC = *RCI;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2770
2771 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2772 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Jakob Stoklund Olesen22e8a362011-10-12 01:24:51 +0000[diff] [blame]2773 if (!isLegalRC(RC))
2774 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2775
2776 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2777 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2778 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2779 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2780 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2781 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2782
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2783 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2784}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2785
2786//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2787// Constraint Selection.
2788
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2789/// isMatchingInputConstraint - Return true of this is an input operand that is
2790/// a matching constraint like "4".
2791bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2792 assert(!ConstraintCode.empty() && "No known constraint!");
2793 return isdigit(ConstraintCode[0]);
2794}
2795
2796/// getMatchedOperand - If this is an input matching constraint, this method
2797/// returns the output operand it matches.
2798unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2799 assert(!ConstraintCode.empty() && "No known constraint!");
2800 return atoi(ConstraintCode.c_str());
2801}
2802
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2803
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2804/// ParseConstraints - Split up the constraint string from the inline
2805/// assembly value into the specific constraints and their prefixes,
2806/// and also tie in the associated operand values.
2807/// If this returns an empty vector, and if the constraint string itself
2808/// isn't empty, there was an error parsing.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2809TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2810 ImmutableCallSite CS) const {
2811 /// ConstraintOperands - Information about all of the constraints.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2812 AsmOperandInfoVector ConstraintOperands;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2813 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2814 unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2815
2816 // Do a prepass over the constraints, canonicalizing them, and building up the
2817 // ConstraintOperands list.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2818 InlineAsm::ConstraintInfoVector
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2819 ConstraintInfos = IA->ParseConstraints();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2820
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2821 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2822 unsigned ResNo = 0; // ResNo - The result number of the next output.
2823
2824 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2825 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2826 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2827
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2828 // Update multiple alternative constraint count.
2829 if (OpInfo.multipleAlternatives.size() > maCount)
2830 maCount = OpInfo.multipleAlternatives.size();
2831
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2832 OpInfo.ConstraintVT = MVT::Other;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2833
2834 // Compute the value type for each operand.
2835 switch (OpInfo.Type) {
2836 case InlineAsm::isOutput:
2837 // Indirect outputs just consume an argument.
2838 if (OpInfo.isIndirect) {
2839 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2840 break;
2841 }
2842
2843 // The return value of the call is this value. As such, there is no
2844 // corresponding argument.
2845 assert(!CS.getType()->isVoidTy() &&
2846 "Bad inline asm!");
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2847 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2848 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2849 } else {
2850 assert(ResNo == 0 && "Asm only has one result!");
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2851 OpInfo.ConstraintVT = getValueType(CS.getType());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2852 }
2853 ++ResNo;
2854 break;
2855 case InlineAsm::isInput:
2856 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2857 break;
2858 case InlineAsm::isClobber:
2859 // Nothing to do.
2860 break;
2861 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2862
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2863 if (OpInfo.CallOperandVal) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2864 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2865 if (OpInfo.isIndirect) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2866 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2867 if (!PtrTy)
2868 report_fatal_error("Indirect operand for inline asm not a pointer!");
2869 OpTy = PtrTy->getElementType();
2870 }
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2871
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2872 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]2873 if (StructType *STy = dyn_cast<StructType>(OpTy))
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]2874 if (STy->getNumElements() == 1)
2875 OpTy = STy->getElementType(0);
2876
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2877 // If OpTy is not a single value, it may be a struct/union that we
2878 // can tile with integers.
2879 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2880 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2881 switch (BitSize) {
2882 default: break;
2883 case 1:
2884 case 8:
2885 case 16:
2886 case 32:
2887 case 64:
2888 case 128:
Dale Johannesen71365d32010-11-09 01:15:07 +0000[diff] [blame]2889 OpInfo.ConstraintVT =
2890 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2891 break;
2892 }
2893 } else if (dyn_cast<PointerType>(OpTy)) {
2894 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2895 } else {
2896 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2897 }
2898 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2899 }
2900
2901 // If we have multiple alternative constraints, select the best alternative.
2902 if (ConstraintInfos.size()) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2903 if (maCount) {
2904 unsigned bestMAIndex = 0;
2905 int bestWeight = -1;
2906 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2907 int weight = -1;
2908 unsigned maIndex;
2909 // Compute the sums of the weights for each alternative, keeping track
2910 // of the best (highest weight) one so far.
2911 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2912 int weightSum = 0;
2913 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2914 cIndex != eIndex; ++cIndex) {
2915 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2916 if (OpInfo.Type == InlineAsm::isClobber)
2917 continue;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2918
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2919 // If this is an output operand with a matching input operand,
2920 // look up the matching input. If their types mismatch, e.g. one
2921 // is an integer, the other is floating point, or their sizes are
2922 // different, flag it as an maCantMatch.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2923 if (OpInfo.hasMatchingInput()) {
2924 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2925 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2926 if ((OpInfo.ConstraintVT.isInteger() !=
2927 Input.ConstraintVT.isInteger()) ||
2928 (OpInfo.ConstraintVT.getSizeInBits() !=
2929 Input.ConstraintVT.getSizeInBits())) {
2930 weightSum = -1; // Can't match.
2931 break;
2932 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2933 }
2934 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2935 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2936 if (weight == -1) {
2937 weightSum = -1;
2938 break;
2939 }
2940 weightSum += weight;
2941 }
2942 // Update best.
2943 if (weightSum > bestWeight) {
2944 bestWeight = weightSum;
2945 bestMAIndex = maIndex;
2946 }
2947 }
2948
2949 // Now select chosen alternative in each constraint.
2950 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2951 cIndex != eIndex; ++cIndex) {
2952 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2953 if (cInfo.Type == InlineAsm::isClobber)
2954 continue;
2955 cInfo.selectAlternative(bestMAIndex);
2956 }
2957 }
2958 }
2959
2960 // Check and hook up tied operands, choose constraint code to use.
2961 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2962 cIndex != eIndex; ++cIndex) {
2963 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2964
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2965 // If this is an output operand with a matching input operand, look up the
2966 // matching input. If their types mismatch, e.g. one is an integer, the
2967 // other is floating point, or their sizes are different, flag it as an
2968 // error.
2969 if (OpInfo.hasMatchingInput()) {
2970 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2971
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2972 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]2973 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2974 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
2975 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2976 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2977 if ((OpInfo.ConstraintVT.isInteger() !=
2978 Input.ConstraintVT.isInteger()) ||
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]2979 (MatchRC.second != InputRC.second)) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2980 report_fatal_error("Unsupported asm: input constraint"
2981 " with a matching output constraint of"
2982 " incompatible type!");
2983 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2984 }
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2985
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2986 }
2987 }
2988
2989 return ConstraintOperands;
2990}
2991
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2992
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2993/// getConstraintGenerality - Return an integer indicating how general CT
2994/// is.
2995static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2996 switch (CT) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2997 default: llvm_unreachable("Unknown constraint type!");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2998 case TargetLowering::C_Other:
2999 case TargetLowering::C_Unknown:
3000 return 0;
3001 case TargetLowering::C_Register:
3002 return 1;
3003 case TargetLowering::C_RegisterClass:
3004 return 2;
3005 case TargetLowering::C_Memory:
3006 return 3;
3007 }
3008}
3009
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3010/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3011/// This object must already have been set up with the operand type
3012/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3013TargetLowering::ConstraintWeight
3014 TargetLowering::getMultipleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3015 AsmOperandInfo &info, int maIndex) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3016 InlineAsm::ConstraintCodeVector *rCodes;
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3017 if (maIndex >= (int)info.multipleAlternatives.size())
3018 rCodes = &info.Codes;
3019 else
3020 rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3021 ConstraintWeight BestWeight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3022
3023 // Loop over the options, keeping track of the most general one.
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3024 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3025 ConstraintWeight weight =
3026 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3027 if (weight > BestWeight)
3028 BestWeight = weight;
3029 }
3030
3031 return BestWeight;
3032}
3033
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3034/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3035/// This object must already have been set up with the operand type
3036/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3037TargetLowering::ConstraintWeight
3038 TargetLowering::getSingleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3039 AsmOperandInfo &info, const char *constraint) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3040 ConstraintWeight weight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3041 Value *CallOperandVal = info.CallOperandVal;
3042 // If we don't have a value, we can't do a match,
3043 // but allow it at the lowest weight.
3044 if (CallOperandVal == NULL)
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3045 return CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3046 // Look at the constraint type.
3047 switch (*constraint) {
3048 case 'i': // immediate integer.
3049 case 'n': // immediate integer with a known value.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3050 if (isa<ConstantInt>(CallOperandVal))
3051 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3052 break;
3053 case 's': // non-explicit intregal immediate.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3054 if (isa<GlobalValue>(CallOperandVal))
3055 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3056 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3057 case 'E': // immediate float if host format.
3058 case 'F': // immediate float.
3059 if (isa<ConstantFP>(CallOperandVal))
3060 weight = CW_Constant;
3061 break;
3062 case '<': // memory operand with autodecrement.
3063 case '>': // memory operand with autoincrement.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3064 case 'm': // memory operand.
3065 case 'o': // offsettable memory operand
3066 case 'V': // non-offsettable memory operand
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3067 weight = CW_Memory;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3068 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3069 case 'r': // general register.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3070 case 'g': // general register, memory operand or immediate integer.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3071 // note: Clang converts "g" to "imr".
3072 if (CallOperandVal->getType()->isIntegerTy())
3073 weight = CW_Register;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3074 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3075 case 'X': // any operand.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3076 default:
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3077 weight = CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3078 break;
3079 }
3080 return weight;
3081}
3082
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3083/// ChooseConstraint - If there are multiple different constraints that we
3084/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]3085/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3086/// Other -> immediates and magic values
3087/// Register -> one specific register
3088/// RegisterClass -> a group of regs
3089/// Memory -> memory
3090/// Ideally, we would pick the most specific constraint possible: if we have
3091/// something that fits into a register, we would pick it. The problem here
3092/// is that if we have something that could either be in a register or in
3093/// memory that use of the register could cause selection of *other*
3094/// operands to fail: they might only succeed if we pick memory. Because of
3095/// this the heuristic we use is:
3096///
3097/// 1) If there is an 'other' constraint, and if the operand is valid for
3098/// that constraint, use it. This makes us take advantage of 'i'
3099/// constraints when available.
3100/// 2) Otherwise, pick the most general constraint present. This prefers
3101/// 'm' over 'r', for example.
3102///
3103static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3104 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3105 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3106 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3107 unsigned BestIdx = 0;
3108 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3109 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3110
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3111 // Loop over the options, keeping track of the most general one.
3112 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3113 TargetLowering::ConstraintType CType =
3114 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3115
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3116 // If this is an 'other' constraint, see if the operand is valid for it.
3117 // For example, on X86 we might have an 'rI' constraint. If the operand
3118 // is an integer in the range [0..31] we want to use I (saving a load
3119 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3120 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3121 assert(OpInfo.Codes[i].size() == 1 &&
3122 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3123 std::vector<SDValue> ResultOps;
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]3124 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3125 ResultOps, *DAG);
3126 if (!ResultOps.empty()) {
3127 BestType = CType;
3128 BestIdx = i;
3129 break;
3130 }
3131 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3132
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3133 // Things with matching constraints can only be registers, per gcc
3134 // documentation. This mainly affects "g" constraints.
3135 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3136 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3137
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3138 // This constraint letter is more general than the previous one, use it.
3139 int Generality = getConstraintGenerality(CType);
3140 if (Generality > BestGenerality) {
3141 BestType = CType;
3142 BestIdx = i;
3143 BestGenerality = Generality;
3144 }
3145 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3146
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3147 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3148 OpInfo.ConstraintType = BestType;
3149}
3150
3151/// ComputeConstraintToUse - Determines the constraint code and constraint
3152/// type to use for the specific AsmOperandInfo, setting
3153/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3154void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3155 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3156 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3157 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3158
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3159 // Single-letter constraints ('r') are very common.
3160 if (OpInfo.Codes.size() == 1) {
3161 OpInfo.ConstraintCode = OpInfo.Codes[0];
3162 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3163 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3164 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3165 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3166
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3167 // 'X' matches anything.
3168 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3169 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3170 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]3171 // the result, which is not what we want to look at; leave them alone.
3172 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3173 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3174 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3175 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3176 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3177
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3178 // Otherwise, try to resolve it to something we know about by looking at
3179 // the actual operand type.
3180 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3181 OpInfo.ConstraintCode = Repl;
3182 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3183 }
3184 }
3185}
3186
3187//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3188// Loop Strength Reduction hooks
3189//===----------------------------------------------------------------------===//
3190
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3191/// isLegalAddressingMode - Return true if the addressing mode represented
3192/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3193bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3194 Type *Ty) const {
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3195 // The default implementation of this implements a conservative RISCy, r+r and
3196 // r+i addr mode.
3197
3198 // Allows a sign-extended 16-bit immediate field.
3199 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3200 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3201
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3202 // No global is ever allowed as a base.
3203 if (AM.BaseGV)
3204 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3205
3206 // Only support r+r,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3207 switch (AM.Scale) {
3208 case 0: // "r+i" or just "i", depending on HasBaseReg.
3209 break;
3210 case 1:
3211 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3212 return false;
3213 // Otherwise we have r+r or r+i.
3214 break;
3215 case 2:
3216 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3217 return false;
3218 // Allow 2*r as r+r.
3219 break;
3220 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3221
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3222 return true;
3223}
3224
Benjamin Kramer9c640302011-07-08 10:31:30 +0000[diff] [blame]3225/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3226/// with the multiplicative inverse of the constant.
3227SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3228 SelectionDAG &DAG) const {
3229 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3230 APInt d = C->getAPIntValue();
3231 assert(d != 0 && "Division by zero!");
3232
3233 // Shift the value upfront if it is even, so the LSB is one.
3234 unsigned ShAmt = d.countTrailingZeros();
3235 if (ShAmt) {
3236 // TODO: For UDIV use SRL instead of SRA.
3237 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3238 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3239 d = d.ashr(ShAmt);
3240 }
3241
3242 // Calculate the multiplicative inverse, using Newton's method.
3243 APInt t, xn = d;
3244 while ((t = d*xn) != 1)
3245 xn *= APInt(d.getBitWidth(), 2) - t;
3246
3247 Op2 = DAG.getConstant(xn, Op1.getValueType());
3248 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3249}
3250
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3251/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3252/// return a DAG expression to select that will generate the same value by
3253/// multiplying by a magic number. See:
3254/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3255SDValue TargetLowering::
3256BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3257 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3258 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3259 DebugLoc dl= N->getDebugLoc();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3260
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3261 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3262 // FIXME: We should be more aggressive here.
3263 if (!isTypeLegal(VT))
3264 return SDValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3265
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3266 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]3267 APInt::ms magics = d.magic();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3268
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3269 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3270 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3271 SDValue Q;
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3272 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3273 isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3274 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3275 DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3276 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3277 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3278 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3279 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3280 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3281 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3282 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3283 // If d > 0 and m < 0, add the numerator
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3284 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3285 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3286 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3287 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3288 }
3289 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3290 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3291 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3292 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3293 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3294 }
3295 // Shift right algebraic if shift value is nonzero
3296 if (magics.s > 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3297 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3298 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3299 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3300 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3301 }
3302 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3303 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3304 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3305 getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3306 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3307 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3308 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3309}
3310
3311/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3312/// return a DAG expression to select that will generate the same value by
3313/// multiplying by a magic number. See:
3314/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3315SDValue TargetLowering::
3316BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3317 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3318 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3319 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3320
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3321 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3322 // FIXME: We should be more aggressive here.
3323 if (!isTypeLegal(VT))
3324 return SDValue();
3325
3326 // FIXME: We should use a narrower constant when the upper
3327 // bits are known to be zero.
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3328 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3329 APInt::mu magics = N1C.magicu();
3330
3331 SDValue Q = N->getOperand(0);
3332
3333 // If the divisor is even, we can avoid using the expensive fixup by shifting
3334 // the divided value upfront.
3335 if (magics.a != 0 && !N1C[0]) {
3336 unsigned Shift = N1C.countTrailingZeros();
3337 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3338 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3339 if (Created)
3340 Created->push_back(Q.getNode());
3341
3342 // Get magic number for the shifted divisor.
3343 magics = N1C.lshr(Shift).magicu(Shift);
3344 assert(magics.a == 0 && "Should use cheap fixup now");
3345 }
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3346
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3347 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3348 // FIXME: We should support doing a MUL in a wider type
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3349 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3350 isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3351 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3352 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3353 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3354 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3355 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3356 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3357 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3358 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3359 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3360
3361 if (magics.a == 0) {
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3362 assert(magics.s < N1C.getBitWidth() &&
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3363 "We shouldn't generate an undefined shift!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3364 return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3365 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3366 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3367 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3368 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3369 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3370 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3371 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3372 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3373 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3374 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3375 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3376 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3377 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3378 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3379 }
3380}