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gerrit-public.fairphone.software / platform / external / llvm / 64944f48a1164c02c15ca423a53919682a89074c / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 9d4449a4aa1f82fc227e309251de0669a3f0f463 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
50 raw_ostream &vStream) const;
51
52 /// getEDInfo - See MCDisassembler.
53 EDInstInfo *getEDInfo() const;
54private:
55};
56
57/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
58class ThumbDisassembler : public MCDisassembler {
59public:
60 /// Constructor - Initializes the disassembler.
61 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]62 ThumbDisassembler(const MCSubtargetInfo &STI) :
63 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]64 }
65
66 ~ThumbDisassembler() {
67 }
68
69 /// getInstruction - See MCDisassembler.
70 DecodeStatus getInstruction(MCInst &instr,
71 uint64_t &size,
72 const MemoryObject &region,
73 uint64_t address,
74 raw_ostream &vStream) const;
75
76 /// getEDInfo - See MCDisassembler.
77 EDInstInfo *getEDInfo() const;
78private:
79 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]80 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]81 void UpdateThumbVFPPredicate(MCInst&) const;
82};
83}
84
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]85static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]86 switch (In) {
87 case MCDisassembler::Success:
88 // Out stays the same.
89 return true;
90 case MCDisassembler::SoftFail:
91 Out = In;
92 return true;
93 case MCDisassembler::Fail:
94 Out = In;
95 return false;
96 }
97 return false;
98}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]99
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]100
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]101// Forward declare these because the autogenerated code will reference them.
102// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]103static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]106 unsigned RegNo, uint64_t Address,
107 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]109 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]121 unsigned RegNo,
122 uint64_t Address,
123 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]124static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]125 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]126
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]139
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]145 unsigned Insn,
146 uint64_t Address,
147 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]148static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]149 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
156
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 unsigned Insn,
159 uint64_t Adddress,
160 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]161static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
273 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]274static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]290static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]298static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
299 uint64_t Address, const void *Decoder);
300static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
301 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]302static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
303 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]304static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
306
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]307
308#include "ARMGenDisassemblerTables.inc"
309#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]310#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]311
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]312static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
313 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]314}
315
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]316static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
317 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]318}
319
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]320EDInstInfo *ARMDisassembler::getEDInfo() const {
321 return instInfoARM;
322}
323
324EDInstInfo *ThumbDisassembler::getEDInfo() const {
325 return instInfoARM;
326}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]328DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]329 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]330 uint64_t Address,
331 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]332 uint8_t bytes[4];
333
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]334 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
335 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
336
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]338 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
339 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]340 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]341 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]342
343 // Encoded as a small-endian 32-bit word in the stream.
344 uint32_t insn = (bytes[3] << 24) |
345 (bytes[2] << 16) |
346 (bytes[1] << 8) |
347 (bytes[0] << 0);
348
349 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]350 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]351 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]352 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]353 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]354 }
355
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]356 // VFP and NEON instructions, similarly, are shared between ARM
357 // and Thumb modes.
358 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]359 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]360 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]361 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]362 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]363 }
364
365 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]366 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]367 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]368 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 // Add a fake predicate operand, because we share these instruction
370 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]371 if (!DecodePredicateOperand(MI, 0xE, Address, this))
372 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]373 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]374 }
375
376 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]377 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]378 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]379 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]380 // Add a fake predicate operand, because we share these instruction
381 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]382 if (!DecodePredicateOperand(MI, 0xE, Address, this))
383 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]384 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]385 }
386
387 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]388 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]389 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]390 Size = 4;
391 // Add a fake predicate operand, because we share these instruction
392 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]393 if (!DecodePredicateOperand(MI, 0xE, Address, this))
394 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]395 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]396 }
397
398 MI.clear();
399
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]400 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]401 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]402}
403
404namespace llvm {
405extern MCInstrDesc ARMInsts[];
406}
407
408// Thumb1 instructions don't have explicit S bits. Rather, they
409// implicitly set CPSR. Since it's not represented in the encoding, the
410// auto-generated decoder won't inject the CPSR operand. We need to fix
411// that as a post-pass.
412static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
413 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]414 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]416 for (unsigned i = 0; i < NumOps; ++i, ++I) {
417 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]418 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]419 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]420 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
421 return;
422 }
423 }
424
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]425 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]426}
427
428// Most Thumb instructions don't have explicit predicates in the
429// encoding, but rather get their predicates from IT context. We need
430// to fix up the predicate operands using this context information as a
431// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]432MCDisassembler::DecodeStatus
433ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]434 MCDisassembler::DecodeStatus S = Success;
435
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]436 // A few instructions actually have predicates encoded in them. Don't
437 // try to overwrite it if we're seeing one of those.
438 switch (MI.getOpcode()) {
439 case ARM::tBcc:
440 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]441 case ARM::tCBZ:
442 case ARM::tCBNZ:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]443 // Some instructions (mostly conditional branches) are not
444 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]445 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]446 S = SoftFail;
447 else
448 return Success;
449 break;
450 case ARM::tB:
451 case ARM::t2B:
452 // Some instructions (mostly unconditional branches) can
453 // only appears at the end of, or outside of, an IT.
454 if (ITBlock.size() > 1)
455 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]456 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]457 default:
458 break;
459 }
460
461 // If we're in an IT block, base the predicate on that. Otherwise,
462 // assume a predicate of AL.
463 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]464 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]465 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]466 if (CC == 0xF)
467 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]468 ITBlock.pop_back();
469 } else
470 CC = ARMCC::AL;
471
472 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]473 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]474 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]475 for (unsigned i = 0; i < NumOps; ++i, ++I) {
476 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]477 if (OpInfo[i].isPredicate()) {
478 I = MI.insert(I, MCOperand::CreateImm(CC));
479 ++I;
480 if (CC == ARMCC::AL)
481 MI.insert(I, MCOperand::CreateReg(0));
482 else
483 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]484 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]485 }
486 }
487
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]488 I = MI.insert(I, MCOperand::CreateImm(CC));
489 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]490 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]491 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]492 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]493 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]494
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]495 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]496}
497
498// Thumb VFP instructions are a special case. Because we share their
499// encodings between ARM and Thumb modes, and they are predicable in ARM
500// mode, the auto-generated decoder will give them an (incorrect)
501// predicate operand. We need to rewrite these operands based on the IT
502// context as a post-pass.
503void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
504 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]505 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]506 CC = ITBlock.back();
507 ITBlock.pop_back();
508 } else
509 CC = ARMCC::AL;
510
511 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
512 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]513 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
514 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]515 if (OpInfo[i].isPredicate() ) {
516 I->setImm(CC);
517 ++I;
518 if (CC == ARMCC::AL)
519 I->setReg(0);
520 else
521 I->setReg(ARM::CPSR);
522 return;
523 }
524 }
525}
526
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]527DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]528 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]529 uint64_t Address,
530 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]531 uint8_t bytes[4];
532
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]533 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
534 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
535
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]536 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]537 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
538 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]539 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]540 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]541
542 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]543 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]544 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]545 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]546 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]547 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]548 }
549
550 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]551 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]552 if (result) {
553 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]554 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]555 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]556 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]557 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]558 }
559
560 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]561 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]562 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]563 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]564 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]565
566 // If we find an IT instruction, we need to parse its condition
567 // code and mask operands so that we can apply them correctly
568 // to the subsequent instructions.
569 if (MI.getOpcode() == ARM::t2IT) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]570 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]571 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]572 unsigned Mask = MI.getOperand(1).getImm();
573 unsigned CondBit0 = Mask >> 4 & 1;
574 unsigned NumTZ = CountTrailingZeros_32(Mask);
575 assert(NumTZ <= 3 && "Invalid IT mask!");
576 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
577 bool T = ((Mask >> Pos) & 1) == CondBit0;
578 if (T)
579 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]580 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]581 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]582 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]583
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]584 ITBlock.push_back(firstcond);
585 }
586
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]587 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]588 }
589
590 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]591 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
592 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]593 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]594 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]595
596 uint32_t insn32 = (bytes[3] << 8) |
597 (bytes[2] << 0) |
598 (bytes[1] << 24) |
599 (bytes[0] << 16);
600 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]601 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]602 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]603 Size = 4;
604 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]605 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]606 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]607 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]608 }
609
610 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]611 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]612 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]613 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]614 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]615 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]616 }
617
618 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]619 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]620 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]621 Size = 4;
622 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]623 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]624 }
625
626 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]627 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]628 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]629 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]630 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]631 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]632 }
633
634 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
635 MI.clear();
636 uint32_t NEONLdStInsn = insn32;
637 NEONLdStInsn &= 0xF0FFFFFF;
638 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]639 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]640 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]641 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]642 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]643 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]644 }
645 }
646
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]647 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]648 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]649 uint32_t NEONDataInsn = insn32;
650 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
651 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
652 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]653 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]654 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]655 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]656 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]657 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]658 }
659 }
660
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]661 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]662 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]663}
664
665
666extern "C" void LLVMInitializeARMDisassembler() {
667 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
668 createARMDisassembler);
669 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
670 createThumbDisassembler);
671}
672
673static const unsigned GPRDecoderTable[] = {
674 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
675 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
676 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
677 ARM::R12, ARM::SP, ARM::LR, ARM::PC
678};
679
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]680static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]681 uint64_t Address, const void *Decoder) {
682 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]683 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]684
685 unsigned Register = GPRDecoderTable[RegNo];
686 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]687 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]688}
689
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]690static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]691DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
692 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]693 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]694 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
695}
696
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]697static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]698 uint64_t Address, const void *Decoder) {
699 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]700 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]701 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
702}
703
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]704static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]705 uint64_t Address, const void *Decoder) {
706 unsigned Register = 0;
707 switch (RegNo) {
708 case 0:
709 Register = ARM::R0;
710 break;
711 case 1:
712 Register = ARM::R1;
713 break;
714 case 2:
715 Register = ARM::R2;
716 break;
717 case 3:
718 Register = ARM::R3;
719 break;
720 case 9:
721 Register = ARM::R9;
722 break;
723 case 12:
724 Register = ARM::R12;
725 break;
726 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]727 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]728 }
729
730 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]731 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]732}
733
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]734static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]735 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]736 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]737 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
738}
739
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]740static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]741 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
742 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
743 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
744 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
745 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
746 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
747 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
748 ARM::S28, ARM::S29, ARM::S30, ARM::S31
749};
750
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]751static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]752 uint64_t Address, const void *Decoder) {
753 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]754 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]755
756 unsigned Register = SPRDecoderTable[RegNo];
757 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]758 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]759}
760
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]761static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]762 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
763 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
764 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
765 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
766 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
767 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
768 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
769 ARM::D28, ARM::D29, ARM::D30, ARM::D31
770};
771
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]772static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]773 uint64_t Address, const void *Decoder) {
774 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]775 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]776
777 unsigned Register = DPRDecoderTable[RegNo];
778 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]779 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]780}
781
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]782static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 uint64_t Address, const void *Decoder) {
784 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]785 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
787}
788
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]789static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]790DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
791 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]792 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]793 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
795}
796
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]797static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]798 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
799 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
800 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
801 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
802};
803
804
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]805static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]806 uint64_t Address, const void *Decoder) {
807 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]808 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]809 RegNo >>= 1;
810
811 unsigned Register = QPRDecoderTable[RegNo];
812 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]813 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]814}
815
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]816static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]817 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]818 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]819 // AL predicate is not allowed on Thumb1 branches.
820 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]821 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]822 Inst.addOperand(MCOperand::CreateImm(Val));
823 if (Val == ARMCC::AL) {
824 Inst.addOperand(MCOperand::CreateReg(0));
825 } else
826 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]827 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]828}
829
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]830static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]831 uint64_t Address, const void *Decoder) {
832 if (Val)
833 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
834 else
835 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]836 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]837}
838
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]839static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]840 uint64_t Address, const void *Decoder) {
841 uint32_t imm = Val & 0xFF;
842 uint32_t rot = (Val & 0xF00) >> 7;
843 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
844 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]845 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]846}
847
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]848static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]849 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]850 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]851
852 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
853 unsigned type = fieldFromInstruction32(Val, 5, 2);
854 unsigned imm = fieldFromInstruction32(Val, 7, 5);
855
856 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
858 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]859
860 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
861 switch (type) {
862 case 0:
863 Shift = ARM_AM::lsl;
864 break;
865 case 1:
866 Shift = ARM_AM::lsr;
867 break;
868 case 2:
869 Shift = ARM_AM::asr;
870 break;
871 case 3:
872 Shift = ARM_AM::ror;
873 break;
874 }
875
876 if (Shift == ARM_AM::ror && imm == 0)
877 Shift = ARM_AM::rrx;
878
879 unsigned Op = Shift | (imm << 3);
880 Inst.addOperand(MCOperand::CreateImm(Op));
881
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]882 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]883}
884
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]885static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]886 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]887 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]888
889 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
890 unsigned type = fieldFromInstruction32(Val, 5, 2);
891 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
892
893 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
895 return MCDisassembler::Fail;
896 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
897 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]898
899 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
900 switch (type) {
901 case 0:
902 Shift = ARM_AM::lsl;
903 break;
904 case 1:
905 Shift = ARM_AM::lsr;
906 break;
907 case 2:
908 Shift = ARM_AM::asr;
909 break;
910 case 3:
911 Shift = ARM_AM::ror;
912 break;
913 }
914
915 Inst.addOperand(MCOperand::CreateImm(Shift));
916
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]917 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]918}
919
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]920static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]921 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]922 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]923
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]924 bool writebackLoad = false;
925 unsigned writebackReg = 0;
926 switch (Inst.getOpcode()) {
927 default:
928 break;
929 case ARM::LDMIA_UPD:
930 case ARM::LDMDB_UPD:
931 case ARM::LDMIB_UPD:
932 case ARM::LDMDA_UPD:
933 case ARM::t2LDMIA_UPD:
934 case ARM::t2LDMDB_UPD:
935 writebackLoad = true;
936 writebackReg = Inst.getOperand(0).getReg();
937 break;
938 }
939
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]940 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]941 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]942 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]943 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]944 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
945 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]946 // Writeback not allowed if Rn is in the target list.
947 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
948 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]949 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]950 }
951
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]952 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]953}
954
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]955static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]956 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]957 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]958
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]959 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
960 unsigned regs = Val & 0xFF;
961
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]962 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
963 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]964 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]965 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
966 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]967 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]969 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]970}
971
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]972static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]973 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]974 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]975
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]976 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
977 unsigned regs = (Val & 0xFF) / 2;
978
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]979 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
980 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]981 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]982 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
983 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]984 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]985
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]986 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]987}
988
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]989static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]990 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]991 // This operand encodes a mask of contiguous zeros between a specified MSB
992 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
993 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]994 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]995 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]996 unsigned msb = fieldFromInstruction32(Val, 5, 5);
997 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
998 uint32_t msb_mask = (1 << (msb+1)) - 1;
999 uint32_t lsb_mask = (1 << lsb) - 1;
1000 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1001 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002}
1003
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1004static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1005 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1006 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1007
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1008 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1009 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1010 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1011 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1012 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1013 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1014
1015 switch (Inst.getOpcode()) {
1016 case ARM::LDC_OFFSET:
1017 case ARM::LDC_PRE:
1018 case ARM::LDC_POST:
1019 case ARM::LDC_OPTION:
1020 case ARM::LDCL_OFFSET:
1021 case ARM::LDCL_PRE:
1022 case ARM::LDCL_POST:
1023 case ARM::LDCL_OPTION:
1024 case ARM::STC_OFFSET:
1025 case ARM::STC_PRE:
1026 case ARM::STC_POST:
1027 case ARM::STC_OPTION:
1028 case ARM::STCL_OFFSET:
1029 case ARM::STCL_PRE:
1030 case ARM::STCL_POST:
1031 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1032 case ARM::t2LDC_OFFSET:
1033 case ARM::t2LDC_PRE:
1034 case ARM::t2LDC_POST:
1035 case ARM::t2LDC_OPTION:
1036 case ARM::t2LDCL_OFFSET:
1037 case ARM::t2LDCL_PRE:
1038 case ARM::t2LDCL_POST:
1039 case ARM::t2LDCL_OPTION:
1040 case ARM::t2STC_OFFSET:
1041 case ARM::t2STC_PRE:
1042 case ARM::t2STC_POST:
1043 case ARM::t2STC_OPTION:
1044 case ARM::t2STCL_OFFSET:
1045 case ARM::t2STCL_PRE:
1046 case ARM::t2STCL_POST:
1047 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1048 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1049 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1050 break;
1051 default:
1052 break;
1053 }
1054
1055 Inst.addOperand(MCOperand::CreateImm(coproc));
1056 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1058 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1059 switch (Inst.getOpcode()) {
1060 case ARM::LDC_OPTION:
1061 case ARM::LDCL_OPTION:
1062 case ARM::LDC2_OPTION:
1063 case ARM::LDC2L_OPTION:
1064 case ARM::STC_OPTION:
1065 case ARM::STCL_OPTION:
1066 case ARM::STC2_OPTION:
1067 case ARM::STC2L_OPTION:
1068 case ARM::LDCL_POST:
1069 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1070 case ARM::LDC2L_POST:
1071 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1072 case ARM::t2LDC_OPTION:
1073 case ARM::t2LDCL_OPTION:
1074 case ARM::t2STC_OPTION:
1075 case ARM::t2STCL_OPTION:
1076 case ARM::t2LDCL_POST:
1077 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1078 break;
1079 default:
1080 Inst.addOperand(MCOperand::CreateReg(0));
1081 break;
1082 }
1083
1084 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1085 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1086
1087 bool writeback = (P == 0) || (W == 1);
1088 unsigned idx_mode = 0;
1089 if (P && writeback)
1090 idx_mode = ARMII::IndexModePre;
1091 else if (!P && writeback)
1092 idx_mode = ARMII::IndexModePost;
1093
1094 switch (Inst.getOpcode()) {
1095 case ARM::LDCL_POST:
1096 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1097 case ARM::t2LDCL_POST:
1098 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1099 case ARM::LDC2L_POST:
1100 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1101 imm |= U << 8;
1102 case ARM::LDC_OPTION:
1103 case ARM::LDCL_OPTION:
1104 case ARM::LDC2_OPTION:
1105 case ARM::LDC2L_OPTION:
1106 case ARM::STC_OPTION:
1107 case ARM::STCL_OPTION:
1108 case ARM::STC2_OPTION:
1109 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1110 case ARM::t2LDC_OPTION:
1111 case ARM::t2LDCL_OPTION:
1112 case ARM::t2STC_OPTION:
1113 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1114 Inst.addOperand(MCOperand::CreateImm(imm));
1115 break;
1116 default:
1117 if (U)
1118 Inst.addOperand(MCOperand::CreateImm(
1119 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1120 else
1121 Inst.addOperand(MCOperand::CreateImm(
1122 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1123 break;
1124 }
1125
1126 switch (Inst.getOpcode()) {
1127 case ARM::LDC_OFFSET:
1128 case ARM::LDC_PRE:
1129 case ARM::LDC_POST:
1130 case ARM::LDC_OPTION:
1131 case ARM::LDCL_OFFSET:
1132 case ARM::LDCL_PRE:
1133 case ARM::LDCL_POST:
1134 case ARM::LDCL_OPTION:
1135 case ARM::STC_OFFSET:
1136 case ARM::STC_PRE:
1137 case ARM::STC_POST:
1138 case ARM::STC_OPTION:
1139 case ARM::STCL_OFFSET:
1140 case ARM::STCL_PRE:
1141 case ARM::STCL_POST:
1142 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1143 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1144 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1145 break;
1146 default:
1147 break;
1148 }
1149
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1150 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1151}
1152
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1153static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1154DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1155 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1156 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1157
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1158 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1159 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1160 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1161 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1162 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1163 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1164 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1165 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1166
1167 // On stores, the writeback operand precedes Rt.
1168 switch (Inst.getOpcode()) {
1169 case ARM::STR_POST_IMM:
1170 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1171 case ARM::STRB_POST_IMM:
1172 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1173 case ARM::STRT_POST_REG:
1174 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1175 case ARM::STRBT_POST_REG:
1176 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1178 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1179 break;
1180 default:
1181 break;
1182 }
1183
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1185 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1186
1187 // On loads, the writeback operand comes after Rt.
1188 switch (Inst.getOpcode()) {
1189 case ARM::LDR_POST_IMM:
1190 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1191 case ARM::LDRB_POST_IMM:
1192 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1193 case ARM::LDRBT_POST_REG:
1194 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1195 case ARM::LDRT_POST_REG:
1196 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1198 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1199 break;
1200 default:
1201 break;
1202 }
1203
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1205 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1206
1207 ARM_AM::AddrOpc Op = ARM_AM::add;
1208 if (!fieldFromInstruction32(Insn, 23, 1))
1209 Op = ARM_AM::sub;
1210
1211 bool writeback = (P == 0) || (W == 1);
1212 unsigned idx_mode = 0;
1213 if (P && writeback)
1214 idx_mode = ARMII::IndexModePre;
1215 else if (!P && writeback)
1216 idx_mode = ARMII::IndexModePost;
1217
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1218 if (writeback && (Rn == 15 || Rn == Rt))
1219 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1220
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1221 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1222 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1223 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1225 switch( fieldFromInstruction32(Insn, 5, 2)) {
1226 case 0:
1227 Opc = ARM_AM::lsl;
1228 break;
1229 case 1:
1230 Opc = ARM_AM::lsr;
1231 break;
1232 case 2:
1233 Opc = ARM_AM::asr;
1234 break;
1235 case 3:
1236 Opc = ARM_AM::ror;
1237 break;
1238 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1239 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1240 }
1241 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1242 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1243
1244 Inst.addOperand(MCOperand::CreateImm(imm));
1245 } else {
1246 Inst.addOperand(MCOperand::CreateReg(0));
1247 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1248 Inst.addOperand(MCOperand::CreateImm(tmp));
1249 }
1250
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1251 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1252 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1253
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1254 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255}
1256
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1257static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1258 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1259 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1260
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1261 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1262 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1263 unsigned type = fieldFromInstruction32(Val, 5, 2);
1264 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1265 unsigned U = fieldFromInstruction32(Val, 12, 1);
1266
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1267 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1268 switch (type) {
1269 case 0:
1270 ShOp = ARM_AM::lsl;
1271 break;
1272 case 1:
1273 ShOp = ARM_AM::lsr;
1274 break;
1275 case 2:
1276 ShOp = ARM_AM::asr;
1277 break;
1278 case 3:
1279 ShOp = ARM_AM::ror;
1280 break;
1281 }
1282
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1284 return MCDisassembler::Fail;
1285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1286 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1287 unsigned shift;
1288 if (U)
1289 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1290 else
1291 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1292 Inst.addOperand(MCOperand::CreateImm(shift));
1293
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1294 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1295}
1296
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1297static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1298DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1299 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1300 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1301
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1302 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1303 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1304 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1305 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1306 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1307 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1308 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1309 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1310 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1311
1312 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1313
1314 // For {LD,ST}RD, Rt must be even, else undefined.
1315 switch (Inst.getOpcode()) {
1316 case ARM::STRD:
1317 case ARM::STRD_PRE:
1318 case ARM::STRD_POST:
1319 case ARM::LDRD:
1320 case ARM::LDRD_PRE:
1321 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1322 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1323 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1324 default:
1325 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1326 }
1327
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1328 if (writeback) { // Writeback
1329 if (P)
1330 U |= ARMII::IndexModePre << 9;
1331 else
1332 U |= ARMII::IndexModePost << 9;
1333
1334 // On stores, the writeback operand precedes Rt.
1335 switch (Inst.getOpcode()) {
1336 case ARM::STRD:
1337 case ARM::STRD_PRE:
1338 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1339 case ARM::STRH:
1340 case ARM::STRH_PRE:
1341 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1343 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1344 break;
1345 default:
1346 break;
1347 }
1348 }
1349
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1351 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1352 switch (Inst.getOpcode()) {
1353 case ARM::STRD:
1354 case ARM::STRD_PRE:
1355 case ARM::STRD_POST:
1356 case ARM::LDRD:
1357 case ARM::LDRD_PRE:
1358 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1360 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1361 break;
1362 default:
1363 break;
1364 }
1365
1366 if (writeback) {
1367 // On loads, the writeback operand comes after Rt.
1368 switch (Inst.getOpcode()) {
1369 case ARM::LDRD:
1370 case ARM::LDRD_PRE:
1371 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1372 case ARM::LDRH:
1373 case ARM::LDRH_PRE:
1374 case ARM::LDRH_POST:
1375 case ARM::LDRSH:
1376 case ARM::LDRSH_PRE:
1377 case ARM::LDRSH_POST:
1378 case ARM::LDRSB:
1379 case ARM::LDRSB_PRE:
1380 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1381 case ARM::LDRHTr:
1382 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1384 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1385 break;
1386 default:
1387 break;
1388 }
1389 }
1390
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1392 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1393
1394 if (type) {
1395 Inst.addOperand(MCOperand::CreateReg(0));
1396 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1397 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1399 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1400 Inst.addOperand(MCOperand::CreateImm(U));
1401 }
1402
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1403 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1404 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1405
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1406 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1407}
1408
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1409static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1410 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1411 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1412
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1413 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1414 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1415
1416 switch (mode) {
1417 case 0:
1418 mode = ARM_AM::da;
1419 break;
1420 case 1:
1421 mode = ARM_AM::ia;
1422 break;
1423 case 2:
1424 mode = ARM_AM::db;
1425 break;
1426 case 3:
1427 mode = ARM_AM::ib;
1428 break;
1429 }
1430
1431 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1433 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1434
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1435 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1436}
1437
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1438static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1439 unsigned Insn,
1440 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1441 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1442
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1443 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1444 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1445 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1446
1447 if (pred == 0xF) {
1448 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1449 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1450 Inst.setOpcode(ARM::RFEDA);
1451 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1452 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1453 Inst.setOpcode(ARM::RFEDA_UPD);
1454 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1455 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1456 Inst.setOpcode(ARM::RFEDB);
1457 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1458 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1459 Inst.setOpcode(ARM::RFEDB_UPD);
1460 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1461 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1462 Inst.setOpcode(ARM::RFEIA);
1463 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1464 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1465 Inst.setOpcode(ARM::RFEIA_UPD);
1466 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1467 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1468 Inst.setOpcode(ARM::RFEIB);
1469 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1470 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1471 Inst.setOpcode(ARM::RFEIB_UPD);
1472 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1473 case ARM::STMDA:
1474 Inst.setOpcode(ARM::SRSDA);
1475 break;
1476 case ARM::STMDA_UPD:
1477 Inst.setOpcode(ARM::SRSDA_UPD);
1478 break;
1479 case ARM::STMDB:
1480 Inst.setOpcode(ARM::SRSDB);
1481 break;
1482 case ARM::STMDB_UPD:
1483 Inst.setOpcode(ARM::SRSDB_UPD);
1484 break;
1485 case ARM::STMIA:
1486 Inst.setOpcode(ARM::SRSIA);
1487 break;
1488 case ARM::STMIA_UPD:
1489 Inst.setOpcode(ARM::SRSIA_UPD);
1490 break;
1491 case ARM::STMIB:
1492 Inst.setOpcode(ARM::SRSIB);
1493 break;
1494 case ARM::STMIB_UPD:
1495 Inst.setOpcode(ARM::SRSIB_UPD);
1496 break;
1497 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1498 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1499 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1500
1501 // For stores (which become SRS's, the only operand is the mode.
1502 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1503 Inst.addOperand(
1504 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1505 return S;
1506 }
1507
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1508 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1509 }
1510
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1512 return MCDisassembler::Fail;
1513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1514 return MCDisassembler::Fail; // Tied
1515 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1516 return MCDisassembler::Fail;
1517 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1518 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1519
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1520 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1521}
1522
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1523static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1524 uint64_t Address, const void *Decoder) {
1525 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1526 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1527 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1528 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1530 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1531
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1532 // imod == '01' --> UNPREDICTABLE
1533 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1534 // return failure here. The '01' imod value is unprintable, so there's
1535 // nothing useful we could do even if we returned UNPREDICTABLE.
1536
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1537 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1538
1539 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1540 Inst.setOpcode(ARM::CPS3p);
1541 Inst.addOperand(MCOperand::CreateImm(imod));
1542 Inst.addOperand(MCOperand::CreateImm(iflags));
1543 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1544 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1545 Inst.setOpcode(ARM::CPS2p);
1546 Inst.addOperand(MCOperand::CreateImm(imod));
1547 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1548 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1549 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1550 Inst.setOpcode(ARM::CPS1p);
1551 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1552 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1553 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1554 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1555 Inst.setOpcode(ARM::CPS1p);
1556 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1557 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1558 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1559
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1560 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1561}
1562
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1563static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1564 uint64_t Address, const void *Decoder) {
1565 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1566 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1567 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1568 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1569
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1570 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1571
1572 // imod == '01' --> UNPREDICTABLE
1573 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1574 // return failure here. The '01' imod value is unprintable, so there's
1575 // nothing useful we could do even if we returned UNPREDICTABLE.
1576
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1577 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1578
1579 if (imod && M) {
1580 Inst.setOpcode(ARM::t2CPS3p);
1581 Inst.addOperand(MCOperand::CreateImm(imod));
1582 Inst.addOperand(MCOperand::CreateImm(iflags));
1583 Inst.addOperand(MCOperand::CreateImm(mode));
1584 } else if (imod && !M) {
1585 Inst.setOpcode(ARM::t2CPS2p);
1586 Inst.addOperand(MCOperand::CreateImm(imod));
1587 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1588 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1589 } else if (!imod && M) {
1590 Inst.setOpcode(ARM::t2CPS1p);
1591 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1592 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1593 } else {
1594 // imod == '00' && M == '0' --> UNPREDICTABLE
1595 Inst.setOpcode(ARM::t2CPS1p);
1596 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1597 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1598 }
1599
1600 return S;
1601}
1602
1603
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1604static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1605 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1606 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1607
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1608 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1609 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1610 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1611 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1612 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1613
1614 if (pred == 0xF)
1615 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1616
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1617 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1618 return MCDisassembler::Fail;
1619 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1620 return MCDisassembler::Fail;
1621 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1622 return MCDisassembler::Fail;
1623 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1624 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1625
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1626 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1627 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1628
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1629 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1630}
1631
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1632static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1633 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1634 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1635
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1636 unsigned add = fieldFromInstruction32(Val, 12, 1);
1637 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1638 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1639
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1641 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1642
1643 if (!add) imm *= -1;
1644 if (imm == 0 && !add) imm = INT32_MIN;
1645 Inst.addOperand(MCOperand::CreateImm(imm));
1646
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1647 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1648}
1649
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1650static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1651 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1652 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1653
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1654 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1655 unsigned U = fieldFromInstruction32(Val, 8, 1);
1656 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1657
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1659 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1660
1661 if (U)
1662 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1663 else
1664 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1665
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1666 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1667}
1668
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1669static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1670 uint64_t Address, const void *Decoder) {
1671 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1672}
1673
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1674static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1675DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1676 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1677 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1678
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1679 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1680 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1681
1682 if (pred == 0xF) {
1683 Inst.setOpcode(ARM::BLXi);
1684 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1685 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1686 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1687 }
1688
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1689 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1690 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1691 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1692
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1693 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1694}
1695
1696
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1697static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1698 uint64_t Address, const void *Decoder) {
1699 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1700 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1701}
1702
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1703static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1704 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1705 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1706
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1707 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1708 unsigned align = fieldFromInstruction32(Val, 4, 2);
1709
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1711 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1712 if (!align)
1713 Inst.addOperand(MCOperand::CreateImm(0));
1714 else
1715 Inst.addOperand(MCOperand::CreateImm(4 << align));
1716
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1717 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1718}
1719
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1720static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1721 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1722 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1723
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1724 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1725 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1726 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1727 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1728 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1729 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1730
1731 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1732 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1733 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1734
1735 // Second output register
1736 switch (Inst.getOpcode()) {
1737 case ARM::VLD1q8:
1738 case ARM::VLD1q16:
1739 case ARM::VLD1q32:
1740 case ARM::VLD1q64:
1741 case ARM::VLD1q8_UPD:
1742 case ARM::VLD1q16_UPD:
1743 case ARM::VLD1q32_UPD:
1744 case ARM::VLD1q64_UPD:
1745 case ARM::VLD1d8T:
1746 case ARM::VLD1d16T:
1747 case ARM::VLD1d32T:
1748 case ARM::VLD1d64T:
1749 case ARM::VLD1d8T_UPD:
1750 case ARM::VLD1d16T_UPD:
1751 case ARM::VLD1d32T_UPD:
1752 case ARM::VLD1d64T_UPD:
1753 case ARM::VLD1d8Q:
1754 case ARM::VLD1d16Q:
1755 case ARM::VLD1d32Q:
1756 case ARM::VLD1d64Q:
1757 case ARM::VLD1d8Q_UPD:
1758 case ARM::VLD1d16Q_UPD:
1759 case ARM::VLD1d32Q_UPD:
1760 case ARM::VLD1d64Q_UPD:
1761 case ARM::VLD2d8:
1762 case ARM::VLD2d16:
1763 case ARM::VLD2d32:
1764 case ARM::VLD2d8_UPD:
1765 case ARM::VLD2d16_UPD:
1766 case ARM::VLD2d32_UPD:
1767 case ARM::VLD2q8:
1768 case ARM::VLD2q16:
1769 case ARM::VLD2q32:
1770 case ARM::VLD2q8_UPD:
1771 case ARM::VLD2q16_UPD:
1772 case ARM::VLD2q32_UPD:
1773 case ARM::VLD3d8:
1774 case ARM::VLD3d16:
1775 case ARM::VLD3d32:
1776 case ARM::VLD3d8_UPD:
1777 case ARM::VLD3d16_UPD:
1778 case ARM::VLD3d32_UPD:
1779 case ARM::VLD4d8:
1780 case ARM::VLD4d16:
1781 case ARM::VLD4d32:
1782 case ARM::VLD4d8_UPD:
1783 case ARM::VLD4d16_UPD:
1784 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1786 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1787 break;
1788 case ARM::VLD2b8:
1789 case ARM::VLD2b16:
1790 case ARM::VLD2b32:
1791 case ARM::VLD2b8_UPD:
1792 case ARM::VLD2b16_UPD:
1793 case ARM::VLD2b32_UPD:
1794 case ARM::VLD3q8:
1795 case ARM::VLD3q16:
1796 case ARM::VLD3q32:
1797 case ARM::VLD3q8_UPD:
1798 case ARM::VLD3q16_UPD:
1799 case ARM::VLD3q32_UPD:
1800 case ARM::VLD4q8:
1801 case ARM::VLD4q16:
1802 case ARM::VLD4q32:
1803 case ARM::VLD4q8_UPD:
1804 case ARM::VLD4q16_UPD:
1805 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1806 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1807 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1808 default:
1809 break;
1810 }
1811
1812 // Third output register
1813 switch(Inst.getOpcode()) {
1814 case ARM::VLD1d8T:
1815 case ARM::VLD1d16T:
1816 case ARM::VLD1d32T:
1817 case ARM::VLD1d64T:
1818 case ARM::VLD1d8T_UPD:
1819 case ARM::VLD1d16T_UPD:
1820 case ARM::VLD1d32T_UPD:
1821 case ARM::VLD1d64T_UPD:
1822 case ARM::VLD1d8Q:
1823 case ARM::VLD1d16Q:
1824 case ARM::VLD1d32Q:
1825 case ARM::VLD1d64Q:
1826 case ARM::VLD1d8Q_UPD:
1827 case ARM::VLD1d16Q_UPD:
1828 case ARM::VLD1d32Q_UPD:
1829 case ARM::VLD1d64Q_UPD:
1830 case ARM::VLD2q8:
1831 case ARM::VLD2q16:
1832 case ARM::VLD2q32:
1833 case ARM::VLD2q8_UPD:
1834 case ARM::VLD2q16_UPD:
1835 case ARM::VLD2q32_UPD:
1836 case ARM::VLD3d8:
1837 case ARM::VLD3d16:
1838 case ARM::VLD3d32:
1839 case ARM::VLD3d8_UPD:
1840 case ARM::VLD3d16_UPD:
1841 case ARM::VLD3d32_UPD:
1842 case ARM::VLD4d8:
1843 case ARM::VLD4d16:
1844 case ARM::VLD4d32:
1845 case ARM::VLD4d8_UPD:
1846 case ARM::VLD4d16_UPD:
1847 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1848 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1849 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1850 break;
1851 case ARM::VLD3q8:
1852 case ARM::VLD3q16:
1853 case ARM::VLD3q32:
1854 case ARM::VLD3q8_UPD:
1855 case ARM::VLD3q16_UPD:
1856 case ARM::VLD3q32_UPD:
1857 case ARM::VLD4q8:
1858 case ARM::VLD4q16:
1859 case ARM::VLD4q32:
1860 case ARM::VLD4q8_UPD:
1861 case ARM::VLD4q16_UPD:
1862 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1863 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1864 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1865 break;
1866 default:
1867 break;
1868 }
1869
1870 // Fourth output register
1871 switch (Inst.getOpcode()) {
1872 case ARM::VLD1d8Q:
1873 case ARM::VLD1d16Q:
1874 case ARM::VLD1d32Q:
1875 case ARM::VLD1d64Q:
1876 case ARM::VLD1d8Q_UPD:
1877 case ARM::VLD1d16Q_UPD:
1878 case ARM::VLD1d32Q_UPD:
1879 case ARM::VLD1d64Q_UPD:
1880 case ARM::VLD2q8:
1881 case ARM::VLD2q16:
1882 case ARM::VLD2q32:
1883 case ARM::VLD2q8_UPD:
1884 case ARM::VLD2q16_UPD:
1885 case ARM::VLD2q32_UPD:
1886 case ARM::VLD4d8:
1887 case ARM::VLD4d16:
1888 case ARM::VLD4d32:
1889 case ARM::VLD4d8_UPD:
1890 case ARM::VLD4d16_UPD:
1891 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1892 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1893 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1894 break;
1895 case ARM::VLD4q8:
1896 case ARM::VLD4q16:
1897 case ARM::VLD4q32:
1898 case ARM::VLD4q8_UPD:
1899 case ARM::VLD4q16_UPD:
1900 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1901 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1902 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1903 break;
1904 default:
1905 break;
1906 }
1907
1908 // Writeback operand
1909 switch (Inst.getOpcode()) {
1910 case ARM::VLD1d8_UPD:
1911 case ARM::VLD1d16_UPD:
1912 case ARM::VLD1d32_UPD:
1913 case ARM::VLD1d64_UPD:
1914 case ARM::VLD1q8_UPD:
1915 case ARM::VLD1q16_UPD:
1916 case ARM::VLD1q32_UPD:
1917 case ARM::VLD1q64_UPD:
1918 case ARM::VLD1d8T_UPD:
1919 case ARM::VLD1d16T_UPD:
1920 case ARM::VLD1d32T_UPD:
1921 case ARM::VLD1d64T_UPD:
1922 case ARM::VLD1d8Q_UPD:
1923 case ARM::VLD1d16Q_UPD:
1924 case ARM::VLD1d32Q_UPD:
1925 case ARM::VLD1d64Q_UPD:
1926 case ARM::VLD2d8_UPD:
1927 case ARM::VLD2d16_UPD:
1928 case ARM::VLD2d32_UPD:
1929 case ARM::VLD2q8_UPD:
1930 case ARM::VLD2q16_UPD:
1931 case ARM::VLD2q32_UPD:
1932 case ARM::VLD2b8_UPD:
1933 case ARM::VLD2b16_UPD:
1934 case ARM::VLD2b32_UPD:
1935 case ARM::VLD3d8_UPD:
1936 case ARM::VLD3d16_UPD:
1937 case ARM::VLD3d32_UPD:
1938 case ARM::VLD3q8_UPD:
1939 case ARM::VLD3q16_UPD:
1940 case ARM::VLD3q32_UPD:
1941 case ARM::VLD4d8_UPD:
1942 case ARM::VLD4d16_UPD:
1943 case ARM::VLD4d32_UPD:
1944 case ARM::VLD4q8_UPD:
1945 case ARM::VLD4q16_UPD:
1946 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1947 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1948 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1949 break;
1950 default:
1951 break;
1952 }
1953
1954 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1955 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1956 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1957
1958 // AddrMode6 Offset (register)
1959 if (Rm == 0xD)
1960 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1961 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1963 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1964 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1965
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1966 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1967}
1968
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1969static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1970 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1971 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1972
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1973 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1974 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1975 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1976 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1977 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1978 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1979
1980 // Writeback Operand
1981 switch (Inst.getOpcode()) {
1982 case ARM::VST1d8_UPD:
1983 case ARM::VST1d16_UPD:
1984 case ARM::VST1d32_UPD:
1985 case ARM::VST1d64_UPD:
1986 case ARM::VST1q8_UPD:
1987 case ARM::VST1q16_UPD:
1988 case ARM::VST1q32_UPD:
1989 case ARM::VST1q64_UPD:
1990 case ARM::VST1d8T_UPD:
1991 case ARM::VST1d16T_UPD:
1992 case ARM::VST1d32T_UPD:
1993 case ARM::VST1d64T_UPD:
1994 case ARM::VST1d8Q_UPD:
1995 case ARM::VST1d16Q_UPD:
1996 case ARM::VST1d32Q_UPD:
1997 case ARM::VST1d64Q_UPD:
1998 case ARM::VST2d8_UPD:
1999 case ARM::VST2d16_UPD:
2000 case ARM::VST2d32_UPD:
2001 case ARM::VST2q8_UPD:
2002 case ARM::VST2q16_UPD:
2003 case ARM::VST2q32_UPD:
2004 case ARM::VST2b8_UPD:
2005 case ARM::VST2b16_UPD:
2006 case ARM::VST2b32_UPD:
2007 case ARM::VST3d8_UPD:
2008 case ARM::VST3d16_UPD:
2009 case ARM::VST3d32_UPD:
2010 case ARM::VST3q8_UPD:
2011 case ARM::VST3q16_UPD:
2012 case ARM::VST3q32_UPD:
2013 case ARM::VST4d8_UPD:
2014 case ARM::VST4d16_UPD:
2015 case ARM::VST4d32_UPD:
2016 case ARM::VST4q8_UPD:
2017 case ARM::VST4q16_UPD:
2018 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2019 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2020 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2021 break;
2022 default:
2023 break;
2024 }
2025
2026 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2027 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2028 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2029
2030 // AddrMode6 Offset (register)
2031 if (Rm == 0xD)
2032 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2033 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2035 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2036 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2037
2038 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2039 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2040 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2041
2042 // Second input register
2043 switch (Inst.getOpcode()) {
2044 case ARM::VST1q8:
2045 case ARM::VST1q16:
2046 case ARM::VST1q32:
2047 case ARM::VST1q64:
2048 case ARM::VST1q8_UPD:
2049 case ARM::VST1q16_UPD:
2050 case ARM::VST1q32_UPD:
2051 case ARM::VST1q64_UPD:
2052 case ARM::VST1d8T:
2053 case ARM::VST1d16T:
2054 case ARM::VST1d32T:
2055 case ARM::VST1d64T:
2056 case ARM::VST1d8T_UPD:
2057 case ARM::VST1d16T_UPD:
2058 case ARM::VST1d32T_UPD:
2059 case ARM::VST1d64T_UPD:
2060 case ARM::VST1d8Q:
2061 case ARM::VST1d16Q:
2062 case ARM::VST1d32Q:
2063 case ARM::VST1d64Q:
2064 case ARM::VST1d8Q_UPD:
2065 case ARM::VST1d16Q_UPD:
2066 case ARM::VST1d32Q_UPD:
2067 case ARM::VST1d64Q_UPD:
2068 case ARM::VST2d8:
2069 case ARM::VST2d16:
2070 case ARM::VST2d32:
2071 case ARM::VST2d8_UPD:
2072 case ARM::VST2d16_UPD:
2073 case ARM::VST2d32_UPD:
2074 case ARM::VST2q8:
2075 case ARM::VST2q16:
2076 case ARM::VST2q32:
2077 case ARM::VST2q8_UPD:
2078 case ARM::VST2q16_UPD:
2079 case ARM::VST2q32_UPD:
2080 case ARM::VST3d8:
2081 case ARM::VST3d16:
2082 case ARM::VST3d32:
2083 case ARM::VST3d8_UPD:
2084 case ARM::VST3d16_UPD:
2085 case ARM::VST3d32_UPD:
2086 case ARM::VST4d8:
2087 case ARM::VST4d16:
2088 case ARM::VST4d32:
2089 case ARM::VST4d8_UPD:
2090 case ARM::VST4d16_UPD:
2091 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2092 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2093 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2094 break;
2095 case ARM::VST2b8:
2096 case ARM::VST2b16:
2097 case ARM::VST2b32:
2098 case ARM::VST2b8_UPD:
2099 case ARM::VST2b16_UPD:
2100 case ARM::VST2b32_UPD:
2101 case ARM::VST3q8:
2102 case ARM::VST3q16:
2103 case ARM::VST3q32:
2104 case ARM::VST3q8_UPD:
2105 case ARM::VST3q16_UPD:
2106 case ARM::VST3q32_UPD:
2107 case ARM::VST4q8:
2108 case ARM::VST4q16:
2109 case ARM::VST4q32:
2110 case ARM::VST4q8_UPD:
2111 case ARM::VST4q16_UPD:
2112 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2113 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2114 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2115 break;
2116 default:
2117 break;
2118 }
2119
2120 // Third input register
2121 switch (Inst.getOpcode()) {
2122 case ARM::VST1d8T:
2123 case ARM::VST1d16T:
2124 case ARM::VST1d32T:
2125 case ARM::VST1d64T:
2126 case ARM::VST1d8T_UPD:
2127 case ARM::VST1d16T_UPD:
2128 case ARM::VST1d32T_UPD:
2129 case ARM::VST1d64T_UPD:
2130 case ARM::VST1d8Q:
2131 case ARM::VST1d16Q:
2132 case ARM::VST1d32Q:
2133 case ARM::VST1d64Q:
2134 case ARM::VST1d8Q_UPD:
2135 case ARM::VST1d16Q_UPD:
2136 case ARM::VST1d32Q_UPD:
2137 case ARM::VST1d64Q_UPD:
2138 case ARM::VST2q8:
2139 case ARM::VST2q16:
2140 case ARM::VST2q32:
2141 case ARM::VST2q8_UPD:
2142 case ARM::VST2q16_UPD:
2143 case ARM::VST2q32_UPD:
2144 case ARM::VST3d8:
2145 case ARM::VST3d16:
2146 case ARM::VST3d32:
2147 case ARM::VST3d8_UPD:
2148 case ARM::VST3d16_UPD:
2149 case ARM::VST3d32_UPD:
2150 case ARM::VST4d8:
2151 case ARM::VST4d16:
2152 case ARM::VST4d32:
2153 case ARM::VST4d8_UPD:
2154 case ARM::VST4d16_UPD:
2155 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2156 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2157 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2158 break;
2159 case ARM::VST3q8:
2160 case ARM::VST3q16:
2161 case ARM::VST3q32:
2162 case ARM::VST3q8_UPD:
2163 case ARM::VST3q16_UPD:
2164 case ARM::VST3q32_UPD:
2165 case ARM::VST4q8:
2166 case ARM::VST4q16:
2167 case ARM::VST4q32:
2168 case ARM::VST4q8_UPD:
2169 case ARM::VST4q16_UPD:
2170 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2171 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2172 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2173 break;
2174 default:
2175 break;
2176 }
2177
2178 // Fourth input register
2179 switch (Inst.getOpcode()) {
2180 case ARM::VST1d8Q:
2181 case ARM::VST1d16Q:
2182 case ARM::VST1d32Q:
2183 case ARM::VST1d64Q:
2184 case ARM::VST1d8Q_UPD:
2185 case ARM::VST1d16Q_UPD:
2186 case ARM::VST1d32Q_UPD:
2187 case ARM::VST1d64Q_UPD:
2188 case ARM::VST2q8:
2189 case ARM::VST2q16:
2190 case ARM::VST2q32:
2191 case ARM::VST2q8_UPD:
2192 case ARM::VST2q16_UPD:
2193 case ARM::VST2q32_UPD:
2194 case ARM::VST4d8:
2195 case ARM::VST4d16:
2196 case ARM::VST4d32:
2197 case ARM::VST4d8_UPD:
2198 case ARM::VST4d16_UPD:
2199 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2200 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2201 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2202 break;
2203 case ARM::VST4q8:
2204 case ARM::VST4q16:
2205 case ARM::VST4q32:
2206 case ARM::VST4q8_UPD:
2207 case ARM::VST4q16_UPD:
2208 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2209 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2210 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2211 break;
2212 default:
2213 break;
2214 }
2215
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2216 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2217}
2218
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2219static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2220 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2221 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2222
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2223 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2224 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2225 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2226 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2227 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2228 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2229 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2230
2231 align *= (1 << size);
2232
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2233 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2234 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2235 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2236 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2237 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2238 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2239 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2241 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2242 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2243
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2245 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2246 Inst.addOperand(MCOperand::CreateImm(align));
2247
2248 if (Rm == 0xD)
2249 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2250 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2252 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2253 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2254
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2255 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2256}
2257
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2258static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2259 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2260 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2261
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2262 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2263 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2264 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2265 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2266 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2267 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2268 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2269 align *= 2*size;
2270
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2271 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2272 return MCDisassembler::Fail;
2273 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2274 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2275 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2276 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2277 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2278 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2279
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2281 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2282 Inst.addOperand(MCOperand::CreateImm(align));
2283
2284 if (Rm == 0xD)
2285 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2286 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2288 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2289 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2290
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2291 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2292}
2293
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2294static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2295 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2296 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2297
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2298 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2299 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2300 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2301 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2302 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2303
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2305 return MCDisassembler::Fail;
2306 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2307 return MCDisassembler::Fail;
2308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2309 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2310 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2312 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2313 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2314
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2316 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2317 Inst.addOperand(MCOperand::CreateImm(0));
2318
2319 if (Rm == 0xD)
2320 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2321 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2323 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2324 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2325
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2326 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2327}
2328
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2329static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2330 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2331 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2332
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2333 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2334 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2335 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2336 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2337 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2338 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2339 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2340
2341 if (size == 0x3) {
2342 size = 4;
2343 align = 16;
2344 } else {
2345 if (size == 2) {
2346 size = 1 << size;
2347 align *= 8;
2348 } else {
2349 size = 1 << size;
2350 align *= 4*size;
2351 }
2352 }
2353
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2355 return MCDisassembler::Fail;
2356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2357 return MCDisassembler::Fail;
2358 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2359 return MCDisassembler::Fail;
2360 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2361 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2362 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2364 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2365 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2366
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2368 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2369 Inst.addOperand(MCOperand::CreateImm(align));
2370
2371 if (Rm == 0xD)
2372 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2373 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2375 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2376 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2377
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2378 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2379}
2380
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2381static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2382DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2383 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2384 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2385
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2386 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2387 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2388 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2389 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2390 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2391 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2392 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2393 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2394
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2395 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2396 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2397 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2398 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2399 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2400 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2401 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2402
2403 Inst.addOperand(MCOperand::CreateImm(imm));
2404
2405 switch (Inst.getOpcode()) {
2406 case ARM::VORRiv4i16:
2407 case ARM::VORRiv2i32:
2408 case ARM::VBICiv4i16:
2409 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2410 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2411 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2412 break;
2413 case ARM::VORRiv8i16:
2414 case ARM::VORRiv4i32:
2415 case ARM::VBICiv8i16:
2416 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2417 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2418 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2419 break;
2420 default:
2421 break;
2422 }
2423
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2424 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2425}
2426
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2427static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2428 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2429 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2430
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2431 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2432 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2433 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2434 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2435 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2436
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2437 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2438 return MCDisassembler::Fail;
2439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2440 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2441 Inst.addOperand(MCOperand::CreateImm(8 << size));
2442
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2443 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2444}
2445
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2446static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2447 uint64_t Address, const void *Decoder) {
2448 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2449 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2450}
2451
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2452static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2453 uint64_t Address, const void *Decoder) {
2454 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2455 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2456}
2457
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2458static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2459 uint64_t Address, const void *Decoder) {
2460 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2461 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2462}
2463
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2464static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2465 uint64_t Address, const void *Decoder) {
2466 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2467 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2468}
2469
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2470static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2471 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2472 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2473
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2474 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2475 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2476 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2477 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2478 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2479 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2480 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2481 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2482
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2484 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2485 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2486 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2487 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2488 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2489
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2490 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2491 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2492 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2493 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2494
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2496 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2497
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2498 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2499}
2500
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2501static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2502 uint64_t Address, const void *Decoder) {
2503 // The immediate needs to be a fully instantiated float. However, the
2504 // auto-generated decoder is only able to fill in some of the bits
2505 // necessary. For instance, the 'b' bit is replicated multiple times,
2506 // and is even present in inverted form in one bit. We do a little
2507 // binary parsing here to fill in those missing bits, and then
2508 // reinterpret it all as a float.
2509 union {
2510 uint32_t integer;
2511 float fp;
2512 } fp_conv;
2513
2514 fp_conv.integer = Val;
2515 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2516 fp_conv.integer |= b << 26;
2517 fp_conv.integer |= b << 27;
2518 fp_conv.integer |= b << 28;
2519 fp_conv.integer |= b << 29;
2520 fp_conv.integer |= (~b & 0x1) << 30;
2521
2522 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2523 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524}
2525
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2526static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2527 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2528 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2529
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2530 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2531 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2532
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2533 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2534 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2535
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2536 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2537 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2538 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2539 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2540 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2541 case ARM::tADDrSPi:
2542 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2543 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2544 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2545
2546 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2547 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2548}
2549
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2550static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2551 uint64_t Address, const void *Decoder) {
2552 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2553 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2554}
2555
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2556static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2557 uint64_t Address, const void *Decoder) {
2558 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2559 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2560}
2561
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2562static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2563 uint64_t Address, const void *Decoder) {
2564 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2565 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2566}
2567
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2568static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2569 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2570 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2571
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2572 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2573 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2574
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2575 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2576 return MCDisassembler::Fail;
2577 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2578 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2579
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2580 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2581}
2582
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2583static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2584 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2585 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2586
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2587 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2588 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2589
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2590 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2591 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2592 Inst.addOperand(MCOperand::CreateImm(imm));
2593
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2594 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2595}
2596
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2597static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2598 uint64_t Address, const void *Decoder) {
2599 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2600
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2601 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2602}
2603
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2604static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2605 uint64_t Address, const void *Decoder) {
2606 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2607 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2608
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2609 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2610}
2611
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2612static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2613 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2614 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2615
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2616 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2617 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2618 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2619
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2621 return MCDisassembler::Fail;
2622 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2623 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2624 Inst.addOperand(MCOperand::CreateImm(imm));
2625
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2626 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2627}
2628
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2629static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2630 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2631 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2632
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2633 switch (Inst.getOpcode()) {
2634 case ARM::t2PLDs:
2635 case ARM::t2PLDWs:
2636 case ARM::t2PLIs:
2637 break;
2638 default: {
2639 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2641 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2642 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2643 }
2644
2645 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2646 if (Rn == 0xF) {
2647 switch (Inst.getOpcode()) {
2648 case ARM::t2LDRBs:
2649 Inst.setOpcode(ARM::t2LDRBpci);
2650 break;
2651 case ARM::t2LDRHs:
2652 Inst.setOpcode(ARM::t2LDRHpci);
2653 break;
2654 case ARM::t2LDRSHs:
2655 Inst.setOpcode(ARM::t2LDRSHpci);
2656 break;
2657 case ARM::t2LDRSBs:
2658 Inst.setOpcode(ARM::t2LDRSBpci);
2659 break;
2660 case ARM::t2PLDs:
2661 Inst.setOpcode(ARM::t2PLDi12);
2662 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2663 break;
2664 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2665 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2666 }
2667
2668 int imm = fieldFromInstruction32(Insn, 0, 12);
2669 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2670 Inst.addOperand(MCOperand::CreateImm(imm));
2671
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2672 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2673 }
2674
2675 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2676 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2677 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2678 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2679 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2680
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2681 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682}
2683
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2684static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2685 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2686 int imm = Val & 0xFF;
2687 if (!(Val & 0x100)) imm *= -1;
2688 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2689
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2690 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2691}
2692
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2693static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2695 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2696
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2697 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2698 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2699
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2701 return MCDisassembler::Fail;
2702 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2703 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2704
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2705 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2706}
2707
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2708static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2709 uint64_t Address, const void *Decoder) {
2710 DecodeStatus S = MCDisassembler::Success;
2711
2712 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2713 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2714
2715 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2716 return MCDisassembler::Fail;
2717
2718 Inst.addOperand(MCOperand::CreateImm(imm));
2719
2720 return S;
2721}
2722
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2723static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2724 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2725 int imm = Val & 0xFF;
2726 if (!(Val & 0x100)) imm *= -1;
2727 Inst.addOperand(MCOperand::CreateImm(imm));
2728
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2729 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2730}
2731
2732
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2733static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2734 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2735 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2736
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2737 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2738 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2739
2740 // Some instructions always use an additive offset.
2741 switch (Inst.getOpcode()) {
2742 case ARM::t2LDRT:
2743 case ARM::t2LDRBT:
2744 case ARM::t2LDRHT:
2745 case ARM::t2LDRSBT:
2746 case ARM::t2LDRSHT:
2747 imm |= 0x100;
2748 break;
2749 default:
2750 break;
2751 }
2752
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2754 return MCDisassembler::Fail;
2755 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2756 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2758 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2759}
2760
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2761static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2762 uint64_t Address, const void *Decoder) {
2763 DecodeStatus S = MCDisassembler::Success;
2764
2765 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2766 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2767 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2768 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2769 addr |= Rn << 9;
2770 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2771
2772 if (!load) {
2773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2774 return MCDisassembler::Fail;
2775 }
2776
2777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2778 return MCDisassembler::Fail;
2779
2780 if (load) {
2781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2782 return MCDisassembler::Fail;
2783 }
2784
2785 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2786 return MCDisassembler::Fail;
2787
2788 return S;
2789}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2790
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2791static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2792 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2793 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2794
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2795 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2796 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2797
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2799 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2800 Inst.addOperand(MCOperand::CreateImm(imm));
2801
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2802 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2803}
2804
2805
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2806static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2807 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2809
2810 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2811 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2812 Inst.addOperand(MCOperand::CreateImm(imm));
2813
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2814 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2815}
2816
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2817static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2818 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2819 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2820
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2821 if (Inst.getOpcode() == ARM::tADDrSP) {
2822 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2823 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2824
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2826 return MCDisassembler::Fail;
2827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2828 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2829 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2830 } else if (Inst.getOpcode() == ARM::tADDspr) {
2831 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2832
2833 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2834 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2836 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2837 }
2838
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2839 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2840}
2841
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2842static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2843 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2844 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2845 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2846
2847 Inst.addOperand(MCOperand::CreateImm(imod));
2848 Inst.addOperand(MCOperand::CreateImm(flags));
2849
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2850 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2851}
2852
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2853static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2854 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2855 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2856 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2857 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2858
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2860 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2861 Inst.addOperand(MCOperand::CreateImm(add));
2862
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2863 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2864}
2865
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2866static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2867 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2868 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2869 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2870}
2871
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2872static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2873 uint64_t Address, const void *Decoder) {
2874 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2875 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2876
2877 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2878 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2879}
2880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2881static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2882DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2883 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2884 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2885
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2886 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2887 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2888 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2889 switch (opc) {
2890 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2891 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2892 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893 Inst.setOpcode(ARM::t2DSB);
2894 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2895 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2896 Inst.setOpcode(ARM::t2DMB);
2897 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2898 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2899 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2900 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2901 }
2902
2903 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2904 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2905 }
2906
2907 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2908 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2909 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2910 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2911 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2912
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2913 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2914 return MCDisassembler::Fail;
2915 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2916 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2917
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2918 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2919}
2920
2921// Decode a shifted immediate operand. These basically consist
2922// of an 8-bit value, and a 4-bit directive that specifies either
2923// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2924static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2925 uint64_t Address, const void *Decoder) {
2926 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2927 if (ctrl == 0) {
2928 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2929 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2930 switch (byte) {
2931 case 0:
2932 Inst.addOperand(MCOperand::CreateImm(imm));
2933 break;
2934 case 1:
2935 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2936 break;
2937 case 2:
2938 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2939 break;
2940 case 3:
2941 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2942 (imm << 8) | imm));
2943 break;
2944 }
2945 } else {
2946 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2947 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2948 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2949 Inst.addOperand(MCOperand::CreateImm(imm));
2950 }
2951
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2952 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2953}
2954
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2955static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2956DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2957 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2958 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2959 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2960}
2961
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2962static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2963 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2964 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2965 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2966}
2967
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2968static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2969 uint64_t Address, const void *Decoder) {
2970 switch (Val) {
2971 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2972 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2973 case 0xF: // SY
2974 case 0xE: // ST
2975 case 0xB: // ISH
2976 case 0xA: // ISHST
2977 case 0x7: // NSH
2978 case 0x6: // NSHST
2979 case 0x3: // OSH
2980 case 0x2: // OSHST
2981 break;
2982 }
2983
2984 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2985 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2986}
2987
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2988static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2989 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2990 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2991 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2992 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2993}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2994
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2995static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2996 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2997 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2998
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2999 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3000 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3001 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3002
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3003 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3004
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3006 return MCDisassembler::Fail;
3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3008 return MCDisassembler::Fail;
3009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3010 return MCDisassembler::Fail;
3011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3012 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3013
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3014 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3015}
3016
3017
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3018static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3019 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3020 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3021
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3022 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3023 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3024 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3025 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3026
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3027 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3028 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3029
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3030 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3031 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3032
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3034 return MCDisassembler::Fail;
3035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3036 return MCDisassembler::Fail;
3037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3038 return MCDisassembler::Fail;
3039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3040 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3041
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3042 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3043}
3044
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3045static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3046 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3047 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3048
3049 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3050 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3051 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3052 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3053 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3054 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3055
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3056 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3057
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3059 return MCDisassembler::Fail;
3060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3061 return MCDisassembler::Fail;
3062 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3063 return MCDisassembler::Fail;
3064 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3065 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3066
3067 return S;
3068}
3069
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3070static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3071 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3072 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3073
3074 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3075 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3076 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3077 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3078 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3079 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3080 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3081
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3082 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3083 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3084
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3086 return MCDisassembler::Fail;
3087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3088 return MCDisassembler::Fail;
3089 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3090 return MCDisassembler::Fail;
3091 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3092 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3093
3094 return S;
3095}
3096
3097
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3098static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3099 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3100 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3101
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3102 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3103 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3104 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3105 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3106 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3107 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3108
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3109 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3110
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3112 return MCDisassembler::Fail;
3113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3114 return MCDisassembler::Fail;
3115 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3116 return MCDisassembler::Fail;
3117 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3118 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3119
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3120 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3121}
3122
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3123static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3124 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3125 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3126
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3127 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3128 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3129 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3130 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3131 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3132 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3133
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3134 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3135
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3136 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3137 return MCDisassembler::Fail;
3138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3139 return MCDisassembler::Fail;
3140 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3141 return MCDisassembler::Fail;
3142 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3143 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3144
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3145 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3146}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3147
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3148static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3149 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3150 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3151
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3152 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3153 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3154 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3155 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3156 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3157
3158 unsigned align = 0;
3159 unsigned index = 0;
3160 switch (size) {
3161 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3162 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3163 case 0:
3164 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3165 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3166 index = fieldFromInstruction32(Insn, 5, 3);
3167 break;
3168 case 1:
3169 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3170 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3171 index = fieldFromInstruction32(Insn, 6, 2);
3172 if (fieldFromInstruction32(Insn, 4, 1))
3173 align = 2;
3174 break;
3175 case 2:
3176 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3177 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3178 index = fieldFromInstruction32(Insn, 7, 1);
3179 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3180 align = 4;
3181 }
3182
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3184 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3185 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3187 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3188 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3190 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3191 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3192 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3193 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3194 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3195 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3196 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3197 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3198 }
3199
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3200 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3201 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3202 Inst.addOperand(MCOperand::CreateImm(index));
3203
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3204 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3205}
3206
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3207static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3208 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3209 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3210
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3211 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3212 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3213 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3214 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3215 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3216
3217 unsigned align = 0;
3218 unsigned index = 0;
3219 switch (size) {
3220 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3221 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3222 case 0:
3223 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3224 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3225 index = fieldFromInstruction32(Insn, 5, 3);
3226 break;
3227 case 1:
3228 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3229 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3230 index = fieldFromInstruction32(Insn, 6, 2);
3231 if (fieldFromInstruction32(Insn, 4, 1))
3232 align = 2;
3233 break;
3234 case 2:
3235 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3236 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3237 index = fieldFromInstruction32(Insn, 7, 1);
3238 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3239 align = 4;
3240 }
3241
3242 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3244 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3245 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3247 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3248 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3249 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3250 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3252 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3253 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3254 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3255 }
3256
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3257 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3258 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3259 Inst.addOperand(MCOperand::CreateImm(index));
3260
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3261 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3262}
3263
3264
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3265static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3266 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3267 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3268
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3269 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3270 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3271 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3272 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3273 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3274
3275 unsigned align = 0;
3276 unsigned index = 0;
3277 unsigned inc = 1;
3278 switch (size) {
3279 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3280 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3281 case 0:
3282 index = fieldFromInstruction32(Insn, 5, 3);
3283 if (fieldFromInstruction32(Insn, 4, 1))
3284 align = 2;
3285 break;
3286 case 1:
3287 index = fieldFromInstruction32(Insn, 6, 2);
3288 if (fieldFromInstruction32(Insn, 4, 1))
3289 align = 4;
3290 if (fieldFromInstruction32(Insn, 5, 1))
3291 inc = 2;
3292 break;
3293 case 2:
3294 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3295 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3296 index = fieldFromInstruction32(Insn, 7, 1);
3297 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3298 align = 8;
3299 if (fieldFromInstruction32(Insn, 6, 1))
3300 inc = 2;
3301 break;
3302 }
3303
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3305 return MCDisassembler::Fail;
3306 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3307 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3308 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3310 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3311 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3313 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3314 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3315 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3316 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3318 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3319 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3320 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3321 }
3322
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3323 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3324 return MCDisassembler::Fail;
3325 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3326 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3327 Inst.addOperand(MCOperand::CreateImm(index));
3328
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3329 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3330}
3331
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3332static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3333 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3334 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3335
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3336 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3337 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3338 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3339 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3340 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3341
3342 unsigned align = 0;
3343 unsigned index = 0;
3344 unsigned inc = 1;
3345 switch (size) {
3346 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3347 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3348 case 0:
3349 index = fieldFromInstruction32(Insn, 5, 3);
3350 if (fieldFromInstruction32(Insn, 4, 1))
3351 align = 2;
3352 break;
3353 case 1:
3354 index = fieldFromInstruction32(Insn, 6, 2);
3355 if (fieldFromInstruction32(Insn, 4, 1))
3356 align = 4;
3357 if (fieldFromInstruction32(Insn, 5, 1))
3358 inc = 2;
3359 break;
3360 case 2:
3361 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3362 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3363 index = fieldFromInstruction32(Insn, 7, 1);
3364 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3365 align = 8;
3366 if (fieldFromInstruction32(Insn, 6, 1))
3367 inc = 2;
3368 break;
3369 }
3370
3371 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3373 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3374 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3376 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3377 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3378 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3379 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3381 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3382 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3383 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3384 }
3385
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3386 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3387 return MCDisassembler::Fail;
3388 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3389 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3390 Inst.addOperand(MCOperand::CreateImm(index));
3391
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3392 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3393}
3394
3395
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3396static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3397 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3398 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3399
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3400 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3401 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3402 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3403 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3404 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3405
3406 unsigned align = 0;
3407 unsigned index = 0;
3408 unsigned inc = 1;
3409 switch (size) {
3410 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3411 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3412 case 0:
3413 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3414 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3415 index = fieldFromInstruction32(Insn, 5, 3);
3416 break;
3417 case 1:
3418 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3419 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3420 index = fieldFromInstruction32(Insn, 6, 2);
3421 if (fieldFromInstruction32(Insn, 5, 1))
3422 inc = 2;
3423 break;
3424 case 2:
3425 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3426 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3427 index = fieldFromInstruction32(Insn, 7, 1);
3428 if (fieldFromInstruction32(Insn, 6, 1))
3429 inc = 2;
3430 break;
3431 }
3432
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3434 return MCDisassembler::Fail;
3435 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3436 return MCDisassembler::Fail;
3437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3438 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3439
3440 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3442 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3443 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3445 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3446 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3447 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3448 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3450 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3451 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3452 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3453 }
3454
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3456 return MCDisassembler::Fail;
3457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3458 return MCDisassembler::Fail;
3459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3460 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3461 Inst.addOperand(MCOperand::CreateImm(index));
3462
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3463 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3464}
3465
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3466static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3467 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3468 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3469
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3470 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3471 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3472 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3473 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3474 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3475
3476 unsigned align = 0;
3477 unsigned index = 0;
3478 unsigned inc = 1;
3479 switch (size) {
3480 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3481 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3482 case 0:
3483 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3484 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3485 index = fieldFromInstruction32(Insn, 5, 3);
3486 break;
3487 case 1:
3488 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3489 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3490 index = fieldFromInstruction32(Insn, 6, 2);
3491 if (fieldFromInstruction32(Insn, 5, 1))
3492 inc = 2;
3493 break;
3494 case 2:
3495 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3496 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3497 index = fieldFromInstruction32(Insn, 7, 1);
3498 if (fieldFromInstruction32(Insn, 6, 1))
3499 inc = 2;
3500 break;
3501 }
3502
3503 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3505 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3506 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3508 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3509 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3510 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3511 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3513 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3514 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3515 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3516 }
3517
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3518 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3519 return MCDisassembler::Fail;
3520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3521 return MCDisassembler::Fail;
3522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3523 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3524 Inst.addOperand(MCOperand::CreateImm(index));
3525
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3526 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3527}
3528
3529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3530static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3531 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3532 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3533
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3534 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3535 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3536 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3537 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3538 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3539
3540 unsigned align = 0;
3541 unsigned index = 0;
3542 unsigned inc = 1;
3543 switch (size) {
3544 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3545 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3546 case 0:
3547 if (fieldFromInstruction32(Insn, 4, 1))
3548 align = 4;
3549 index = fieldFromInstruction32(Insn, 5, 3);
3550 break;
3551 case 1:
3552 if (fieldFromInstruction32(Insn, 4, 1))
3553 align = 8;
3554 index = fieldFromInstruction32(Insn, 6, 2);
3555 if (fieldFromInstruction32(Insn, 5, 1))
3556 inc = 2;
3557 break;
3558 case 2:
3559 if (fieldFromInstruction32(Insn, 4, 2))
3560 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3561 index = fieldFromInstruction32(Insn, 7, 1);
3562 if (fieldFromInstruction32(Insn, 6, 1))
3563 inc = 2;
3564 break;
3565 }
3566
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3568 return MCDisassembler::Fail;
3569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3570 return MCDisassembler::Fail;
3571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3572 return MCDisassembler::Fail;
3573 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3574 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3575
3576 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3578 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3579 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3581 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3582 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3583 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3584 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3586 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3587 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3588 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3589 }
3590
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3591 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3592 return MCDisassembler::Fail;
3593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3598 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3599 Inst.addOperand(MCOperand::CreateImm(index));
3600
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3601 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3602}
3603
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3604static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3605 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3606 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3607
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3608 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3609 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3610 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3611 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3612 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3613
3614 unsigned align = 0;
3615 unsigned index = 0;
3616 unsigned inc = 1;
3617 switch (size) {
3618 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3619 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3620 case 0:
3621 if (fieldFromInstruction32(Insn, 4, 1))
3622 align = 4;
3623 index = fieldFromInstruction32(Insn, 5, 3);
3624 break;
3625 case 1:
3626 if (fieldFromInstruction32(Insn, 4, 1))
3627 align = 8;
3628 index = fieldFromInstruction32(Insn, 6, 2);
3629 if (fieldFromInstruction32(Insn, 5, 1))
3630 inc = 2;
3631 break;
3632 case 2:
3633 if (fieldFromInstruction32(Insn, 4, 2))
3634 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3635 index = fieldFromInstruction32(Insn, 7, 1);
3636 if (fieldFromInstruction32(Insn, 6, 1))
3637 inc = 2;
3638 break;
3639 }
3640
3641 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3643 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3644 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3646 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3647 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3648 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3649 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3651 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3652 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3653 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3654 }
3655
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3656 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3657 return MCDisassembler::Fail;
3658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3659 return MCDisassembler::Fail;
3660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3661 return MCDisassembler::Fail;
3662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3663 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3664 Inst.addOperand(MCOperand::CreateImm(index));
3665
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3666 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3667}
3668
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3669static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3670 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3671 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3672 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3673 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3674 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3675 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3676 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3677
3678 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3679 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3680
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3681 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3682 return MCDisassembler::Fail;
3683 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3684 return MCDisassembler::Fail;
3685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3686 return MCDisassembler::Fail;
3687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3688 return MCDisassembler::Fail;
3689 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3690 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3691
3692 return S;
3693}
3694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3695static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3696 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3697 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3698 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3699 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3700 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3701 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3702 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3703
3704 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3705 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3706
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3708 return MCDisassembler::Fail;
3709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3710 return MCDisassembler::Fail;
3711 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3712 return MCDisassembler::Fail;
3713 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3714 return MCDisassembler::Fail;
3715 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3716 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3717
3718 return S;
3719}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3720
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3721static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3722 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3723 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3724 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3725 // The InstPrinter needs to have the low bit of the predicate in
3726 // the mask operand to be able to print it properly.
3727 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3728
3729 if (pred == 0xF) {
3730 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3731 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3732 }
3733
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3734 if ((mask & 0xF) == 0) {
3735 // Preserve the high bit of the mask, which is the low bit of
3736 // the predicate.
3737 mask &= 0x10;
3738 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3739 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3740 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3741
3742 Inst.addOperand(MCOperand::CreateImm(pred));
3743 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3744 return S;
3745}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3746
3747static DecodeStatus
3748DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3749 uint64_t Address, const void *Decoder) {
3750 DecodeStatus S = MCDisassembler::Success;
3751
3752 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3753 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3754 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3755 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3756 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3757 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3758 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3759 bool writeback = (W == 1) | (P == 0);
3760
3761 addr |= (U << 8) | (Rn << 9);
3762
3763 if (writeback && (Rn == Rt || Rn == Rt2))
3764 Check(S, MCDisassembler::SoftFail);
3765 if (Rt == Rt2)
3766 Check(S, MCDisassembler::SoftFail);
3767
3768 // Rt
3769 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3770 return MCDisassembler::Fail;
3771 // Rt2
3772 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3773 return MCDisassembler::Fail;
3774 // Writeback operand
3775 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3776 return MCDisassembler::Fail;
3777 // addr
3778 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3779 return MCDisassembler::Fail;
3780
3781 return S;
3782}
3783
3784static DecodeStatus
3785DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3786 uint64_t Address, const void *Decoder) {
3787 DecodeStatus S = MCDisassembler::Success;
3788
3789 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3790 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3791 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3792 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3793 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3794 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3795 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3796 bool writeback = (W == 1) | (P == 0);
3797
3798 addr |= (U << 8) | (Rn << 9);
3799
3800 if (writeback && (Rn == Rt || Rn == Rt2))
3801 Check(S, MCDisassembler::SoftFail);
3802
3803 // Writeback operand
3804 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3805 return MCDisassembler::Fail;
3806 // Rt
3807 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3808 return MCDisassembler::Fail;
3809 // Rt2
3810 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3811 return MCDisassembler::Fail;
3812 // addr
3813 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3814 return MCDisassembler::Fail;
3815
3816 return S;
3817}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]3818
3819static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3820 uint64_t Address, const void *Decoder) {
3821 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3822 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3823 if (sign1 != sign2) return MCDisassembler::Fail;
3824
3825 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3826 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3827 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3828 Val |= sign1 << 12;
3829 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3830
3831 return MCDisassembler::Success;
3832}
3833