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gerrit-public.fairphone.software / platform / external / llvm / c1ed096b6b34c5f9af1a856aef5978144b20f31e / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: d2b1cc37f212d77b79521f490deec2041dabf734 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]13#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]14#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]15#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]16#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]17#include "llvm/MC/MCInstrDesc.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]20#include "llvm/MC/MCDisassembler.h"
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]22#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]26#include "llvm/Support/LEB128.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]27#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]28#include "llvm/Support/raw_ostream.h"
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]29#include <vector>
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]30
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]31using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]32
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]33typedef MCDisassembler::DecodeStatus DecodeStatus;
34
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]35namespace {
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]36 // Handles the condition code status of instructions in IT blocks
37 class ITStatus
38 {
39 public:
40 // Returns the condition code for instruction in IT block
41 unsigned getITCC() {
42 unsigned CC = ARMCC::AL;
43 if (instrInITBlock())
44 CC = ITStates.back();
45 return CC;
46 }
47
48 // Advances the IT block state to the next T or E
49 void advanceITState() {
50 ITStates.pop_back();
51 }
52
53 // Returns true if the current instruction is in an IT block
54 bool instrInITBlock() {
55 return !ITStates.empty();
56 }
57
58 // Returns true if current instruction is the last instruction in an IT block
59 bool instrLastInITBlock() {
60 return ITStates.size() == 1;
61 }
62
63 // Called when decoding an IT instruction. Sets the IT state for the following
64 // instructions that for the IT block. Firstcond and Mask correspond to the
65 // fields in the IT instruction encoding.
66 void setITState(char Firstcond, char Mask) {
67 // (3 - the number of trailing zeros) is the number of then / else.
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]68 unsigned CondBit0 = Firstcond & 1;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]69 unsigned NumTZ = CountTrailingZeros_32(Mask);
70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
71 assert(NumTZ <= 3 && "Invalid IT mask!");
72 // push condition codes onto the stack the correct order for the pops
73 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
74 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 if (T)
76 ITStates.push_back(CCBits);
77 else
78 ITStates.push_back(CCBits ^ 1);
79 }
80 ITStates.push_back(CCBits);
81 }
82
83 private:
84 std::vector<unsigned char> ITStates;
85 };
86}
87
88namespace {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]89/// ARMDisassembler - ARM disassembler for all ARM platforms.
90class ARMDisassembler : public MCDisassembler {
91public:
92 /// Constructor - Initializes the disassembler.
93 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]94 ARMDisassembler(const MCSubtargetInfo &STI) :
95 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]96 }
97
98 ~ARMDisassembler() {
99 }
100
101 /// getInstruction - See MCDisassembler.
102 DecodeStatus getInstruction(MCInst &instr,
103 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]104 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]105 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]106 raw_ostream &vStream,
107 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]108
109 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]110 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]111private:
112};
113
114/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
115class ThumbDisassembler : public MCDisassembler {
116public:
117 /// Constructor - Initializes the disassembler.
118 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]119 ThumbDisassembler(const MCSubtargetInfo &STI) :
120 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]121 }
122
123 ~ThumbDisassembler() {
124 }
125
126 /// getInstruction - See MCDisassembler.
127 DecodeStatus getInstruction(MCInst &instr,
128 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]129 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]130 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]131 raw_ostream &vStream,
132 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]133
134 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]135 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]136private:
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]137 mutable ITStatus ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]138 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]139 void UpdateThumbVFPPredicate(MCInst&) const;
140};
141}
142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]144 switch (In) {
145 case MCDisassembler::Success:
146 // Out stays the same.
147 return true;
148 case MCDisassembler::SoftFail:
149 Out = In;
150 return true;
151 case MCDisassembler::Fail:
152 Out = In;
153 return false;
154 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]155 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]156}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]157
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]158
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]159// Forward declare these because the autogenerated code will reference them.
160// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]161static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]163static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]164 unsigned RegNo, uint64_t Address,
165 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]166static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]167 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]168static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]170static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]172static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]174static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]176static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]178static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]179 unsigned RegNo,
180 uint64_t Address,
181 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]182static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]184static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]186static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]187 unsigned RegNo, uint64_t Address,
188 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]189
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]190static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]192static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]194static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]198static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]200static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]202
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]203static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]205static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]207static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]208 unsigned Insn,
209 uint64_t Address,
210 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]211static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]213static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]215static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]217static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
219
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]220static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]221 unsigned Insn,
222 uint64_t Adddress,
223 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]224static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]226static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]228static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]230static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]232static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]234static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]236static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]238static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]240static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]242static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]244static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]246static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]248static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]250static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]252static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]254static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]256static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]258static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]260static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]262static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]264static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]266static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]268static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]270static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]272static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]274static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]276static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]278static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]280static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]282static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]284static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]286static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]288static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]290static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]292static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]294static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]296static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]298static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]300static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]302static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]303 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]304static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]305 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]306static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]307 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]308static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]309 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]310static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]311 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]312static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]313 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]314static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]315 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]316static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]317 uint64_t Address, const void *Decoder);
318
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]319
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]320static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]321 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]322static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]323 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]324static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]325 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]326static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]328static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]330static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]332static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]333 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]334static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]335 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]336static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]338static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]340static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]341 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]342static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]343 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]344static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]345 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]346static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]348static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]349 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]350static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]351 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]352static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]353 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]354static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]356static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]358static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]359 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]360static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]361 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]362static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]363 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]364static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]366static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]368static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]370static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]371 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]372static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]373 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]374static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]375 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]376static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]377 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]378static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]379 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]380static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]381 uint64_t Address, const void *Decoder);
382
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]383static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]384 uint64_t Address, const void *Decoder);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]385static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
386 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]387#include "ARMGenDisassemblerTables.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]388#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]389
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]390static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
391 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]392}
393
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]394static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
395 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]396}
397
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]398const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]399 return instInfoARM;
400}
401
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]402const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]403 return instInfoARM;
404}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]405
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]406DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]407 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]408 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]409 raw_ostream &os,
410 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]411 CommentStream = &cs;
412
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]413 uint8_t bytes[4];
414
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]415 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
416 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
417
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]418 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]419 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
420 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]421 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]422 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]423
424 // Encoded as a small-endian 32-bit word in the stream.
425 uint32_t insn = (bytes[3] << 24) |
426 (bytes[2] << 16) |
427 (bytes[1] << 8) |
428 (bytes[0] << 0);
429
430 // Calling the auto-generated decoder function.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]431 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
432 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]433 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]434 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]435 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]436 }
437
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]438 // VFP and NEON instructions, similarly, are shared between ARM
439 // and Thumb modes.
440 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]441 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]442 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]443 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]444 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]445 }
446
447 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]448 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
449 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]450 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]451 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]452 // Add a fake predicate operand, because we share these instruction
453 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]454 if (!DecodePredicateOperand(MI, 0xE, Address, this))
455 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]456 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]457 }
458
459 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]460 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
461 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]462 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]463 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]464 // Add a fake predicate operand, because we share these instruction
465 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]466 if (!DecodePredicateOperand(MI, 0xE, Address, this))
467 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]468 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]469 }
470
471 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]472 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
473 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]474 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]475 Size = 4;
476 // Add a fake predicate operand, because we share these instruction
477 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]478 if (!DecodePredicateOperand(MI, 0xE, Address, this))
479 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]480 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]481 }
482
483 MI.clear();
484
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]485 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]486 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]487}
488
489namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]490extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]491}
492
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]493/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
494/// immediate Value in the MCInst. The immediate Value has had any PC
495/// adjustment made by the caller. If the instruction is a branch instruction
496/// then isBranch is true, else false. If the getOpInfo() function was set as
497/// part of the setupForSymbolicDisassembly() call then that function is called
498/// to get any symbolic information at the Address for this instruction. If
499/// that returns non-zero then the symbolic information it returns is used to
500/// create an MCExpr and that is added as an operand to the MCInst. If
501/// getOpInfo() returns zero and isBranch is true then a symbol look up for
502/// Value is done and if a symbol is found an MCExpr is created with that, else
503/// an MCExpr with Value is created. This function returns true if it adds an
504/// operand to the MCInst and false otherwise.
505static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
506 bool isBranch, uint64_t InstSize,
507 MCInst &MI, const void *Decoder) {
508 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
509 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]510 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]511 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]512 SymbolicOp.Value = Value;
513 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]514
515 if (!getOpInfo ||
516 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
517 // Clear SymbolicOp.Value from above and also all other fields.
518 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
519 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
520 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]521 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]522 uint64_t ReferenceType;
523 if (isBranch)
524 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
525 else
526 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
527 const char *ReferenceName;
Kevin Enderby88d12662012-10-18 21:49:18 +0000[diff] [blame]528 uint64_t SymbolValue = 0x00000000ffffffffULL & Value;
529 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType,
530 Address, &ReferenceName);
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]531 if (Name) {
532 SymbolicOp.AddSymbol.Name = Name;
533 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]534 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]535 // For branches always create an MCExpr so it gets printed as hex address.
536 else if (isBranch) {
537 SymbolicOp.Value = Value;
538 }
539 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
540 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
541 if (!Name && !isBranch)
542 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]543 }
544
545 MCContext *Ctx = Dis->getMCContext();
546 const MCExpr *Add = NULL;
547 if (SymbolicOp.AddSymbol.Present) {
548 if (SymbolicOp.AddSymbol.Name) {
549 StringRef Name(SymbolicOp.AddSymbol.Name);
550 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
551 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
552 } else {
553 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
554 }
555 }
556
557 const MCExpr *Sub = NULL;
558 if (SymbolicOp.SubtractSymbol.Present) {
559 if (SymbolicOp.SubtractSymbol.Name) {
560 StringRef Name(SymbolicOp.SubtractSymbol.Name);
561 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
562 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
563 } else {
564 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
565 }
566 }
567
568 const MCExpr *Off = NULL;
569 if (SymbolicOp.Value != 0)
570 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
571
572 const MCExpr *Expr;
573 if (Sub) {
574 const MCExpr *LHS;
575 if (Add)
576 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
577 else
578 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
579 if (Off != 0)
580 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
581 else
582 Expr = LHS;
583 } else if (Add) {
584 if (Off != 0)
585 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
586 else
587 Expr = Add;
588 } else {
589 if (Off != 0)
590 Expr = Off;
591 else
592 Expr = MCConstantExpr::Create(0, *Ctx);
593 }
594
595 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
596 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
597 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
598 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
599 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
600 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]601 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]602 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]603
604 return true;
605}
606
607/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
608/// referenced by a load instruction with the base register that is the Pc.
609/// These can often be values in a literal pool near the Address of the
610/// instruction. The Address of the instruction and its immediate Value are
611/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledruc8e41c52012-07-23 08:51:15 +0000[diff] [blame]612/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]613/// the referenced address is that of a symbol. Or it will return a pointer to
614/// a literal 'C' string if the referenced address of the literal pool's entry
615/// is an address into a section with 'C' string literals.
616static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]617 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]618 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
619 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
620 if (SymbolLookUp) {
621 void *DisInfo = Dis->getDisInfoBlock();
622 uint64_t ReferenceType;
623 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
624 const char *ReferenceName;
625 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
626 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
627 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
628 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
629 }
630}
631
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]632// Thumb1 instructions don't have explicit S bits. Rather, they
633// implicitly set CPSR. Since it's not represented in the encoding, the
634// auto-generated decoder won't inject the CPSR operand. We need to fix
635// that as a post-pass.
636static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
637 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]638 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]639 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]640 for (unsigned i = 0; i < NumOps; ++i, ++I) {
641 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]642 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]643 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]644 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
645 return;
646 }
647 }
648
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]649 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]650}
651
652// Most Thumb instructions don't have explicit predicates in the
653// encoding, but rather get their predicates from IT context. We need
654// to fix up the predicate operands using this context information as a
655// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]656MCDisassembler::DecodeStatus
657ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]658 MCDisassembler::DecodeStatus S = Success;
659
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]660 // A few instructions actually have predicates encoded in them. Don't
661 // try to overwrite it if we're seeing one of those.
662 switch (MI.getOpcode()) {
663 case ARM::tBcc:
664 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]665 case ARM::tCBZ:
666 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]667 case ARM::tCPS:
668 case ARM::t2CPS3p:
669 case ARM::t2CPS2p:
670 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]671 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]672 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]673 // Some instructions (mostly conditional branches) are not
674 // allowed in IT blocks.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]675 if (ITBlock.instrInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]676 S = SoftFail;
677 else
678 return Success;
679 break;
680 case ARM::tB:
681 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]682 case ARM::t2TBB:
683 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]684 // Some instructions (mostly unconditional branches) can
685 // only appears at the end of, or outside of, an IT.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]686 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]687 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]688 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]689 default:
690 break;
691 }
692
693 // If we're in an IT block, base the predicate on that. Otherwise,
694 // assume a predicate of AL.
695 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]696 CC = ITBlock.getITCC();
697 if (CC == 0xF)
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]698 CC = ARMCC::AL;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]699 if (ITBlock.instrInITBlock())
700 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]701
702 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]703 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]705 for (unsigned i = 0; i < NumOps; ++i, ++I) {
706 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]707 if (OpInfo[i].isPredicate()) {
708 I = MI.insert(I, MCOperand::CreateImm(CC));
709 ++I;
710 if (CC == ARMCC::AL)
711 MI.insert(I, MCOperand::CreateReg(0));
712 else
713 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]714 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]715 }
716 }
717
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]718 I = MI.insert(I, MCOperand::CreateImm(CC));
719 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]720 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]721 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]722 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]723 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]724
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]725 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]726}
727
728// Thumb VFP instructions are a special case. Because we share their
729// encodings between ARM and Thumb modes, and they are predicable in ARM
730// mode, the auto-generated decoder will give them an (incorrect)
731// predicate operand. We need to rewrite these operands based on the IT
732// context as a post-pass.
733void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
734 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]735 CC = ITBlock.getITCC();
736 if (ITBlock.instrInITBlock())
737 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]738
739 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
740 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]741 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
742 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]743 if (OpInfo[i].isPredicate() ) {
744 I->setImm(CC);
745 ++I;
746 if (CC == ARMCC::AL)
747 I->setReg(0);
748 else
749 I->setReg(ARM::CPSR);
750 return;
751 }
752 }
753}
754
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]755DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]756 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]757 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]758 raw_ostream &os,
759 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]760 CommentStream = &cs;
761
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]762 uint8_t bytes[4];
763
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]764 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
765 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
766
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]767 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]768 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
769 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]770 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]771 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]772
773 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]774 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
775 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]776 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]778 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]779 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]780 }
781
782 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]783 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
784 Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]785 if (result) {
786 Size = 2;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]787 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]788 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]789 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]790 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 }
792
793 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]794 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
795 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]796 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]797 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]798
799 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
800 // the Thumb predicate.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]801 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]802 result = MCDisassembler::SoftFail;
803
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]804 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]805
806 // If we find an IT instruction, we need to parse its condition
807 // code and mask operands so that we can apply them correctly
808 // to the subsequent instructions.
809 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]810
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]811 unsigned Firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]812 unsigned Mask = MI.getOperand(1).getImm();
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]813 ITBlock.setITState(Firstcond, Mask);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]814 }
815
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]816 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]817 }
818
819 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]820 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
821 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]822 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]823 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]824
825 uint32_t insn32 = (bytes[3] << 8) |
826 (bytes[2] << 0) |
827 (bytes[1] << 24) |
828 (bytes[0] << 16);
829 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]830 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
831 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]832 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833 Size = 4;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]834 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]835 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]837 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]838 }
839
840 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]841 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
842 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]843 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]844 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]845 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]846 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]847 }
848
849 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]850 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]851 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]852 Size = 4;
853 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]854 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]855 }
856
857 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]858 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
859 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]860 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]861 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]862 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]863 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]864 }
865
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]866 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]867 MI.clear();
868 uint32_t NEONLdStInsn = insn32;
869 NEONLdStInsn &= 0xF0FFFFFF;
870 NEONLdStInsn |= 0x04000000;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]871 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
872 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]873 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]874 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]875 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]876 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]877 }
878 }
879
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]880 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]881 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]882 uint32_t NEONDataInsn = insn32;
883 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
884 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
885 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]886 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
887 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]888 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]889 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]890 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]891 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]892 }
893 }
894
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]895 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]896 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]897}
898
899
900extern "C" void LLVMInitializeARMDisassembler() {
901 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
902 createARMDisassembler);
903 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
904 createThumbDisassembler);
905}
906
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]907static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
909 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
910 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
911 ARM::R12, ARM::SP, ARM::LR, ARM::PC
912};
913
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]914static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]915 uint64_t Address, const void *Decoder) {
916 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]917 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]918
919 unsigned Register = GPRDecoderTable[RegNo];
920 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]921 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]922}
923
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]924static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]925DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]926 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]927 DecodeStatus S = MCDisassembler::Success;
928
929 if (RegNo == 15)
930 S = MCDisassembler::SoftFail;
931
932 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
933
934 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]935}
936
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]937static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]938 uint64_t Address, const void *Decoder) {
939 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]940 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]941 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
942}
943
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]944static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]945 uint64_t Address, const void *Decoder) {
946 unsigned Register = 0;
947 switch (RegNo) {
948 case 0:
949 Register = ARM::R0;
950 break;
951 case 1:
952 Register = ARM::R1;
953 break;
954 case 2:
955 Register = ARM::R2;
956 break;
957 case 3:
958 Register = ARM::R3;
959 break;
960 case 9:
961 Register = ARM::R9;
962 break;
963 case 12:
964 Register = ARM::R12;
965 break;
966 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]967 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968 }
969
970 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]971 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]972}
973
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]974static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]975 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]976 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]977 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
978}
979
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]980static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]981 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
982 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
983 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
984 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
985 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
986 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
987 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
988 ARM::S28, ARM::S29, ARM::S30, ARM::S31
989};
990
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]991static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]992 uint64_t Address, const void *Decoder) {
993 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]994 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995
996 unsigned Register = SPRDecoderTable[RegNo];
997 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]998 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999}
1000
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1001static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1010};
1011
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1012static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1013 uint64_t Address, const void *Decoder) {
1014 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1015 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1016
1017 unsigned Register = DPRDecoderTable[RegNo];
1018 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1019 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1020}
1021
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1022static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1023 uint64_t Address, const void *Decoder) {
1024 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1025 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1027}
1028
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1029static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1030DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1031 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1032 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1033 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1035}
1036
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1037static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1042};
1043
1044
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1045static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1046 uint64_t Address, const void *Decoder) {
1047 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1048 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1049 RegNo >>= 1;
1050
1051 unsigned Register = QPRDecoderTable[RegNo];
1052 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1053 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1054}
1055
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1056static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1062 ARM::Q15
1063};
1064
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1065static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1066 uint64_t Address, const void *Decoder) {
1067 if (RegNo > 30)
1068 return MCDisassembler::Fail;
1069
1070 unsigned Register = DPairDecoderTable[RegNo];
1071 Inst.addOperand(MCOperand::CreateReg(Register));
1072 return MCDisassembler::Success;
1073}
1074
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1075static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1083 ARM::D28_D30, ARM::D29_D31
1084};
1085
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1086static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1087 unsigned RegNo,
1088 uint64_t Address,
1089 const void *Decoder) {
1090 if (RegNo > 29)
1091 return MCDisassembler::Fail;
1092
1093 unsigned Register = DPairSpacedDecoderTable[RegNo];
1094 Inst.addOperand(MCOperand::CreateReg(Register));
1095 return MCDisassembler::Success;
1096}
1097
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1098static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1099 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1100 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1101 // AL predicate is not allowed on Thumb1 branches.
1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1103 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1104 Inst.addOperand(MCOperand::CreateImm(Val));
1105 if (Val == ARMCC::AL) {
1106 Inst.addOperand(MCOperand::CreateReg(0));
1107 } else
1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1109 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1110}
1111
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1112static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1113 uint64_t Address, const void *Decoder) {
1114 if (Val)
1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1116 else
1117 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1118 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1119}
1120
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1121static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1122 uint64_t Address, const void *Decoder) {
1123 uint32_t imm = Val & 0xFF;
1124 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1126 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1127 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1128}
1129
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1130static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1131 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1132 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1133
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1134 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1135 unsigned type = fieldFromInstruction(Val, 5, 2);
1136 unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1137
1138 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1140 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1141
1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1143 switch (type) {
1144 case 0:
1145 Shift = ARM_AM::lsl;
1146 break;
1147 case 1:
1148 Shift = ARM_AM::lsr;
1149 break;
1150 case 2:
1151 Shift = ARM_AM::asr;
1152 break;
1153 case 3:
1154 Shift = ARM_AM::ror;
1155 break;
1156 }
1157
1158 if (Shift == ARM_AM::ror && imm == 0)
1159 Shift = ARM_AM::rrx;
1160
1161 unsigned Op = Shift | (imm << 3);
1162 Inst.addOperand(MCOperand::CreateImm(Op));
1163
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1164 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1165}
1166
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1167static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1168 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1169 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1170
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1171 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1172 unsigned type = fieldFromInstruction(Val, 5, 2);
1173 unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1174
1175 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1177 return MCDisassembler::Fail;
1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1179 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1180
1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1182 switch (type) {
1183 case 0:
1184 Shift = ARM_AM::lsl;
1185 break;
1186 case 1:
1187 Shift = ARM_AM::lsr;
1188 break;
1189 case 2:
1190 Shift = ARM_AM::asr;
1191 break;
1192 case 3:
1193 Shift = ARM_AM::ror;
1194 break;
1195 }
1196
1197 Inst.addOperand(MCOperand::CreateImm(Shift));
1198
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1199 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1200}
1201
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1202static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1203 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1204 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1205
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1206 bool writebackLoad = false;
1207 unsigned writebackReg = 0;
1208 switch (Inst.getOpcode()) {
1209 default:
1210 break;
1211 case ARM::LDMIA_UPD:
1212 case ARM::LDMDB_UPD:
1213 case ARM::LDMIB_UPD:
1214 case ARM::LDMDA_UPD:
1215 case ARM::t2LDMIA_UPD:
1216 case ARM::t2LDMDB_UPD:
1217 writebackLoad = true;
1218 writebackReg = Inst.getOperand(0).getReg();
1219 break;
1220 }
1221
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1222 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1223 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1225 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1226 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1227 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1228 // Writeback not allowed if Rn is in the target list.
1229 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1230 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1231 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1232 }
1233
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1234 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235}
1236
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1237static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1239 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1240
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1241 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1242 unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1243
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1244 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1245 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1246 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1247 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1248 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1249 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1250
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1251 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1252}
1253
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1254static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1256 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1257
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1258 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1259 unsigned regs = fieldFromInstruction(Val, 0, 8);
Silviu Barangab422d0b2012-05-03 16:38:40 +0000[diff] [blame]1260
1261 regs = regs >> 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1262
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1263 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1264 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1265 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1266 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1267 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1268 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1269
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1270 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1271}
1272
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1273static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1274 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1275 // This operand encodes a mask of contiguous zeros between a specified MSB
1276 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1277 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1278 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1279 // create the final mask.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1280 unsigned msb = fieldFromInstruction(Val, 5, 5);
1281 unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1282
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1283 DecodeStatus S = MCDisassembler::Success;
1284 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1285
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1286 uint32_t msb_mask = 0xFFFFFFFF;
1287 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1288 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1289
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1290 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1291 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1292}
1293
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1294static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1295 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1296 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1297
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1298 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1299 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1300 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1301 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1302 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1303 unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1304
1305 switch (Inst.getOpcode()) {
1306 case ARM::LDC_OFFSET:
1307 case ARM::LDC_PRE:
1308 case ARM::LDC_POST:
1309 case ARM::LDC_OPTION:
1310 case ARM::LDCL_OFFSET:
1311 case ARM::LDCL_PRE:
1312 case ARM::LDCL_POST:
1313 case ARM::LDCL_OPTION:
1314 case ARM::STC_OFFSET:
1315 case ARM::STC_PRE:
1316 case ARM::STC_POST:
1317 case ARM::STC_OPTION:
1318 case ARM::STCL_OFFSET:
1319 case ARM::STCL_PRE:
1320 case ARM::STCL_POST:
1321 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1322 case ARM::t2LDC_OFFSET:
1323 case ARM::t2LDC_PRE:
1324 case ARM::t2LDC_POST:
1325 case ARM::t2LDC_OPTION:
1326 case ARM::t2LDCL_OFFSET:
1327 case ARM::t2LDCL_PRE:
1328 case ARM::t2LDCL_POST:
1329 case ARM::t2LDCL_OPTION:
1330 case ARM::t2STC_OFFSET:
1331 case ARM::t2STC_PRE:
1332 case ARM::t2STC_POST:
1333 case ARM::t2STC_OPTION:
1334 case ARM::t2STCL_OFFSET:
1335 case ARM::t2STCL_PRE:
1336 case ARM::t2STCL_POST:
1337 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1338 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1339 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1340 break;
1341 default:
1342 break;
1343 }
1344
1345 Inst.addOperand(MCOperand::CreateImm(coproc));
1346 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1348 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1349
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1350 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1351 case ARM::t2LDC2_OFFSET:
1352 case ARM::t2LDC2L_OFFSET:
1353 case ARM::t2LDC2_PRE:
1354 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1355 case ARM::t2STC2_OFFSET:
1356 case ARM::t2STC2L_OFFSET:
1357 case ARM::t2STC2_PRE:
1358 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1359 case ARM::LDC2_OFFSET:
1360 case ARM::LDC2L_OFFSET:
1361 case ARM::LDC2_PRE:
1362 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1363 case ARM::STC2_OFFSET:
1364 case ARM::STC2L_OFFSET:
1365 case ARM::STC2_PRE:
1366 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1367 case ARM::t2LDC_OFFSET:
1368 case ARM::t2LDCL_OFFSET:
1369 case ARM::t2LDC_PRE:
1370 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1371 case ARM::t2STC_OFFSET:
1372 case ARM::t2STCL_OFFSET:
1373 case ARM::t2STC_PRE:
1374 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1375 case ARM::LDC_OFFSET:
1376 case ARM::LDCL_OFFSET:
1377 case ARM::LDC_PRE:
1378 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1379 case ARM::STC_OFFSET:
1380 case ARM::STCL_OFFSET:
1381 case ARM::STC_PRE:
1382 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1383 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1384 Inst.addOperand(MCOperand::CreateImm(imm));
1385 break;
1386 case ARM::t2LDC2_POST:
1387 case ARM::t2LDC2L_POST:
1388 case ARM::t2STC2_POST:
1389 case ARM::t2STC2L_POST:
1390 case ARM::LDC2_POST:
1391 case ARM::LDC2L_POST:
1392 case ARM::STC2_POST:
1393 case ARM::STC2L_POST:
1394 case ARM::t2LDC_POST:
1395 case ARM::t2LDCL_POST:
1396 case ARM::t2STC_POST:
1397 case ARM::t2STCL_POST:
1398 case ARM::LDC_POST:
1399 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1400 case ARM::STC_POST:
1401 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1402 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1403 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1404 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1405 // The 'option' variant doesn't encode 'U' in the immediate since
1406 // the immediate is unsigned [0,255].
1407 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1408 break;
1409 }
1410
1411 switch (Inst.getOpcode()) {
1412 case ARM::LDC_OFFSET:
1413 case ARM::LDC_PRE:
1414 case ARM::LDC_POST:
1415 case ARM::LDC_OPTION:
1416 case ARM::LDCL_OFFSET:
1417 case ARM::LDCL_PRE:
1418 case ARM::LDCL_POST:
1419 case ARM::LDCL_OPTION:
1420 case ARM::STC_OFFSET:
1421 case ARM::STC_PRE:
1422 case ARM::STC_POST:
1423 case ARM::STC_OPTION:
1424 case ARM::STCL_OFFSET:
1425 case ARM::STCL_PRE:
1426 case ARM::STCL_POST:
1427 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1428 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1429 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1430 break;
1431 default:
1432 break;
1433 }
1434
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1435 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1436}
1437
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1438static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1439DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1440 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1441 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1442
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1443 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1444 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1445 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1446 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1447 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1448 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1449 unsigned P = fieldFromInstruction(Insn, 24, 1);
1450 unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1451
1452 // On stores, the writeback operand precedes Rt.
1453 switch (Inst.getOpcode()) {
1454 case ARM::STR_POST_IMM:
1455 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1456 case ARM::STRB_POST_IMM:
1457 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1458 case ARM::STRT_POST_REG:
1459 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1460 case ARM::STRBT_POST_REG:
1461 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1463 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1464 break;
1465 default:
1466 break;
1467 }
1468
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1470 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1471
1472 // On loads, the writeback operand comes after Rt.
1473 switch (Inst.getOpcode()) {
1474 case ARM::LDR_POST_IMM:
1475 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1476 case ARM::LDRB_POST_IMM:
1477 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1478 case ARM::LDRBT_POST_REG:
1479 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1480 case ARM::LDRT_POST_REG:
1481 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1483 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1484 break;
1485 default:
1486 break;
1487 }
1488
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1490 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1491
1492 ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1493 if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1494 Op = ARM_AM::sub;
1495
1496 bool writeback = (P == 0) || (W == 1);
1497 unsigned idx_mode = 0;
1498 if (P && writeback)
1499 idx_mode = ARMII::IndexModePre;
1500 else if (!P && writeback)
1501 idx_mode = ARMII::IndexModePost;
1502
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1503 if (writeback && (Rn == 15 || Rn == Rt))
1504 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1505
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1506 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1508 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1509 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1510 switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1511 case 0:
1512 Opc = ARM_AM::lsl;
1513 break;
1514 case 1:
1515 Opc = ARM_AM::lsr;
1516 break;
1517 case 2:
1518 Opc = ARM_AM::asr;
1519 break;
1520 case 3:
1521 Opc = ARM_AM::ror;
1522 break;
1523 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1524 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1525 }
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1526 unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover93c7c442012-09-22 11:18:12 +0000[diff] [blame]1527 if (Opc == ARM_AM::ror && amt == 0)
1528 Opc = ARM_AM::rrx;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1529 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1530
1531 Inst.addOperand(MCOperand::CreateImm(imm));
1532 } else {
1533 Inst.addOperand(MCOperand::CreateReg(0));
1534 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1535 Inst.addOperand(MCOperand::CreateImm(tmp));
1536 }
1537
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1538 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1539 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1540
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1541 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1542}
1543
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1544static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1545 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1546 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1547
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1548 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1549 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1550 unsigned type = fieldFromInstruction(Val, 5, 2);
1551 unsigned imm = fieldFromInstruction(Val, 7, 5);
1552 unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1553
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1554 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1555 switch (type) {
1556 case 0:
1557 ShOp = ARM_AM::lsl;
1558 break;
1559 case 1:
1560 ShOp = ARM_AM::lsr;
1561 break;
1562 case 2:
1563 ShOp = ARM_AM::asr;
1564 break;
1565 case 3:
1566 ShOp = ARM_AM::ror;
1567 break;
1568 }
1569
Tim Northover93c7c442012-09-22 11:18:12 +0000[diff] [blame]1570 if (ShOp == ARM_AM::ror && imm == 0)
1571 ShOp = ARM_AM::rrx;
1572
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1574 return MCDisassembler::Fail;
1575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1576 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1577 unsigned shift;
1578 if (U)
1579 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1580 else
1581 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1582 Inst.addOperand(MCOperand::CreateImm(shift));
1583
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1584 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1585}
1586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1587static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1588DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1589 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1590 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1591
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1592 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1593 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1594 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1595 unsigned type = fieldFromInstruction(Insn, 22, 1);
1596 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1597 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1598 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1599 unsigned W = fieldFromInstruction(Insn, 21, 1);
1600 unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1601 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1602
1603 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1604
1605 // For {LD,ST}RD, Rt must be even, else undefined.
1606 switch (Inst.getOpcode()) {
1607 case ARM::STRD:
1608 case ARM::STRD_PRE:
1609 case ARM::STRD_POST:
1610 case ARM::LDRD:
1611 case ARM::LDRD_PRE:
1612 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1613 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1614 break;
1615 default:
1616 break;
1617 }
1618 switch (Inst.getOpcode()) {
1619 case ARM::STRD:
1620 case ARM::STRD_PRE:
1621 case ARM::STRD_POST:
1622 if (P == 0 && W == 1)
1623 S = MCDisassembler::SoftFail;
1624
1625 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1626 S = MCDisassembler::SoftFail;
1627 if (type && Rm == 15)
1628 S = MCDisassembler::SoftFail;
1629 if (Rt2 == 15)
1630 S = MCDisassembler::SoftFail;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1631 if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1632 S = MCDisassembler::SoftFail;
1633 break;
1634 case ARM::STRH:
1635 case ARM::STRH_PRE:
1636 case ARM::STRH_POST:
1637 if (Rt == 15)
1638 S = MCDisassembler::SoftFail;
1639 if (writeback && (Rn == 15 || Rn == Rt))
1640 S = MCDisassembler::SoftFail;
1641 if (!type && Rm == 15)
1642 S = MCDisassembler::SoftFail;
1643 break;
1644 case ARM::LDRD:
1645 case ARM::LDRD_PRE:
1646 case ARM::LDRD_POST:
1647 if (type && Rn == 15){
1648 if (Rt2 == 15)
1649 S = MCDisassembler::SoftFail;
1650 break;
1651 }
1652 if (P == 0 && W == 1)
1653 S = MCDisassembler::SoftFail;
1654 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1655 S = MCDisassembler::SoftFail;
1656 if (!type && writeback && Rn == 15)
1657 S = MCDisassembler::SoftFail;
1658 if (writeback && (Rn == Rt || Rn == Rt2))
1659 S = MCDisassembler::SoftFail;
1660 break;
1661 case ARM::LDRH:
1662 case ARM::LDRH_PRE:
1663 case ARM::LDRH_POST:
1664 if (type && Rn == 15){
1665 if (Rt == 15)
1666 S = MCDisassembler::SoftFail;
1667 break;
1668 }
1669 if (Rt == 15)
1670 S = MCDisassembler::SoftFail;
1671 if (!type && Rm == 15)
1672 S = MCDisassembler::SoftFail;
1673 if (!type && writeback && (Rn == 15 || Rn == Rt))
1674 S = MCDisassembler::SoftFail;
1675 break;
1676 case ARM::LDRSH:
1677 case ARM::LDRSH_PRE:
1678 case ARM::LDRSH_POST:
1679 case ARM::LDRSB:
1680 case ARM::LDRSB_PRE:
1681 case ARM::LDRSB_POST:
1682 if (type && Rn == 15){
1683 if (Rt == 15)
1684 S = MCDisassembler::SoftFail;
1685 break;
1686 }
1687 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1688 S = MCDisassembler::SoftFail;
1689 if (!type && (Rt == 15 || Rm == 15))
1690 S = MCDisassembler::SoftFail;
1691 if (!type && writeback && (Rn == 15 || Rn == Rt))
1692 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1693 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1694 default:
1695 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1696 }
1697
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1698 if (writeback) { // Writeback
1699 if (P)
1700 U |= ARMII::IndexModePre << 9;
1701 else
1702 U |= ARMII::IndexModePost << 9;
1703
1704 // On stores, the writeback operand precedes Rt.
1705 switch (Inst.getOpcode()) {
1706 case ARM::STRD:
1707 case ARM::STRD_PRE:
1708 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1709 case ARM::STRH:
1710 case ARM::STRH_PRE:
1711 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1713 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1714 break;
1715 default:
1716 break;
1717 }
1718 }
1719
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1721 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1722 switch (Inst.getOpcode()) {
1723 case ARM::STRD:
1724 case ARM::STRD_PRE:
1725 case ARM::STRD_POST:
1726 case ARM::LDRD:
1727 case ARM::LDRD_PRE:
1728 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1730 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1731 break;
1732 default:
1733 break;
1734 }
1735
1736 if (writeback) {
1737 // On loads, the writeback operand comes after Rt.
1738 switch (Inst.getOpcode()) {
1739 case ARM::LDRD:
1740 case ARM::LDRD_PRE:
1741 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1742 case ARM::LDRH:
1743 case ARM::LDRH_PRE:
1744 case ARM::LDRH_POST:
1745 case ARM::LDRSH:
1746 case ARM::LDRSH_PRE:
1747 case ARM::LDRSH_POST:
1748 case ARM::LDRSB:
1749 case ARM::LDRSB_PRE:
1750 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1751 case ARM::LDRHTr:
1752 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1754 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1755 break;
1756 default:
1757 break;
1758 }
1759 }
1760
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1762 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1763
1764 if (type) {
1765 Inst.addOperand(MCOperand::CreateReg(0));
1766 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1767 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1769 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1770 Inst.addOperand(MCOperand::CreateImm(U));
1771 }
1772
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1773 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1774 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1775
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1776 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1777}
1778
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1779static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1780 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1781 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1782
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1783 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1784 unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1785
1786 switch (mode) {
1787 case 0:
1788 mode = ARM_AM::da;
1789 break;
1790 case 1:
1791 mode = ARM_AM::ia;
1792 break;
1793 case 2:
1794 mode = ARM_AM::db;
1795 break;
1796 case 3:
1797 mode = ARM_AM::ib;
1798 break;
1799 }
1800
1801 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1803 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1804
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1805 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1806}
1807
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1808static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1809 unsigned Insn,
1810 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1811 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1812
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1813 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1814 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1815 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1816
1817 if (pred == 0xF) {
1818 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1819 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1820 Inst.setOpcode(ARM::RFEDA);
1821 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1822 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1823 Inst.setOpcode(ARM::RFEDA_UPD);
1824 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1825 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1826 Inst.setOpcode(ARM::RFEDB);
1827 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1828 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1829 Inst.setOpcode(ARM::RFEDB_UPD);
1830 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1831 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1832 Inst.setOpcode(ARM::RFEIA);
1833 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1834 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1835 Inst.setOpcode(ARM::RFEIA_UPD);
1836 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1837 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1838 Inst.setOpcode(ARM::RFEIB);
1839 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1840 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1841 Inst.setOpcode(ARM::RFEIB_UPD);
1842 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1843 case ARM::STMDA:
1844 Inst.setOpcode(ARM::SRSDA);
1845 break;
1846 case ARM::STMDA_UPD:
1847 Inst.setOpcode(ARM::SRSDA_UPD);
1848 break;
1849 case ARM::STMDB:
1850 Inst.setOpcode(ARM::SRSDB);
1851 break;
1852 case ARM::STMDB_UPD:
1853 Inst.setOpcode(ARM::SRSDB_UPD);
1854 break;
1855 case ARM::STMIA:
1856 Inst.setOpcode(ARM::SRSIA);
1857 break;
1858 case ARM::STMIA_UPD:
1859 Inst.setOpcode(ARM::SRSIA_UPD);
1860 break;
1861 case ARM::STMIB:
1862 Inst.setOpcode(ARM::SRSIB);
1863 break;
1864 case ARM::STMIB_UPD:
1865 Inst.setOpcode(ARM::SRSIB_UPD);
1866 break;
1867 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1868 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1869 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1870
1871 // For stores (which become SRS's, the only operand is the mode.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1872 if (fieldFromInstruction(Insn, 20, 1) == 0) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1873 Inst.addOperand(
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1874 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1875 return S;
1876 }
1877
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1878 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1879 }
1880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1882 return MCDisassembler::Fail;
1883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1884 return MCDisassembler::Fail; // Tied
1885 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1886 return MCDisassembler::Fail;
1887 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1889
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1890 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1891}
1892
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1893static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1894 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1895 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1896 unsigned M = fieldFromInstruction(Insn, 17, 1);
1897 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1898 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1899
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1900 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1901
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1902 // imod == '01' --> UNPREDICTABLE
1903 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1904 // return failure here. The '01' imod value is unprintable, so there's
1905 // nothing useful we could do even if we returned UNPREDICTABLE.
1906
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1907 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1908
1909 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1910 Inst.setOpcode(ARM::CPS3p);
1911 Inst.addOperand(MCOperand::CreateImm(imod));
1912 Inst.addOperand(MCOperand::CreateImm(iflags));
1913 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1914 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1915 Inst.setOpcode(ARM::CPS2p);
1916 Inst.addOperand(MCOperand::CreateImm(imod));
1917 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1918 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1919 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1920 Inst.setOpcode(ARM::CPS1p);
1921 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1922 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1923 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1924 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1925 Inst.setOpcode(ARM::CPS1p);
1926 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1927 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1928 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1929
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1930 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1931}
1932
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1933static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1934 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1935 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1936 unsigned M = fieldFromInstruction(Insn, 8, 1);
1937 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1938 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1939
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1940 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1941
1942 // imod == '01' --> UNPREDICTABLE
1943 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1944 // return failure here. The '01' imod value is unprintable, so there's
1945 // nothing useful we could do even if we returned UNPREDICTABLE.
1946
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1947 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1948
1949 if (imod && M) {
1950 Inst.setOpcode(ARM::t2CPS3p);
1951 Inst.addOperand(MCOperand::CreateImm(imod));
1952 Inst.addOperand(MCOperand::CreateImm(iflags));
1953 Inst.addOperand(MCOperand::CreateImm(mode));
1954 } else if (imod && !M) {
1955 Inst.setOpcode(ARM::t2CPS2p);
1956 Inst.addOperand(MCOperand::CreateImm(imod));
1957 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1958 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1959 } else if (!imod && M) {
1960 Inst.setOpcode(ARM::t2CPS1p);
1961 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1962 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1963 } else {
1964 // imod == '00' && M == '0' --> UNPREDICTABLE
1965 Inst.setOpcode(ARM::t2CPS1p);
1966 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1967 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1968 }
1969
1970 return S;
1971}
1972
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1973static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1974 uint64_t Address, const void *Decoder) {
1975 DecodeStatus S = MCDisassembler::Success;
1976
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1977 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1978 unsigned imm = 0;
1979
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1980 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1981 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1982 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1983 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1984
1985 if (Inst.getOpcode() == ARM::t2MOVTi16)
1986 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1987 return MCDisassembler::Fail;
1988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1989 return MCDisassembler::Fail;
1990
1991 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1992 Inst.addOperand(MCOperand::CreateImm(imm));
1993
1994 return S;
1995}
1996
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1997static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1998 uint64_t Address, const void *Decoder) {
1999 DecodeStatus S = MCDisassembler::Success;
2000
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2001 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2002 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2003 unsigned imm = 0;
2004
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2005 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2006 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2007
2008 if (Inst.getOpcode() == ARM::MOVTi16)
2009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2010 return MCDisassembler::Fail;
2011 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2012 return MCDisassembler::Fail;
2013
2014 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2015 Inst.addOperand(MCOperand::CreateImm(imm));
2016
2017 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2018 return MCDisassembler::Fail;
2019
2020 return S;
2021}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]2022
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2023static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2024 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2025 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2026
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2027 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2028 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2029 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2030 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2031 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2032
2033 if (pred == 0xF)
2034 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2035
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2036 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2037 return MCDisassembler::Fail;
2038 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2039 return MCDisassembler::Fail;
2040 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2041 return MCDisassembler::Fail;
2042 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2043 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2044
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2045 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2046 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]2047
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2048 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2049}
2050
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2051static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2052 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2053 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2054
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2055 unsigned add = fieldFromInstruction(Val, 12, 1);
2056 unsigned imm = fieldFromInstruction(Val, 0, 12);
2057 unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2058
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2059 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2060 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2061
2062 if (!add) imm *= -1;
2063 if (imm == 0 && !add) imm = INT32_MIN;
2064 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2065 if (Rn == 15)
2066 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2067
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2068 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2069}
2070
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2071static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2072 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2073 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2074
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2075 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2076 unsigned U = fieldFromInstruction(Val, 8, 1);
2077 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2078
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2080 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2081
2082 if (U)
2083 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2084 else
2085 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2086
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2087 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2088}
2089
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2090static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2091 uint64_t Address, const void *Decoder) {
2092 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2093}
2094
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2095static DecodeStatus
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2096DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2097 uint64_t Address, const void *Decoder) {
2098 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2099 unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) |
2100 (fieldFromInstruction(Insn, 11, 1) << 18) |
2101 (fieldFromInstruction(Insn, 13, 1) << 17) |
2102 (fieldFromInstruction(Insn, 16, 6) << 11) |
2103 (fieldFromInstruction(Insn, 26, 1) << 19);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2104 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2105 true, 4, Inst, Decoder))
2106 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2107 return S;
2108}
2109
2110static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2111DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2112 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2113 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2114
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2115 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2116 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2117
2118 if (pred == 0xF) {
2119 Inst.setOpcode(ARM::BLXi);
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2120 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2121 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2122 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2123 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2124 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2125 }
2126
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2127 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2128 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2129 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2130 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2131 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2132
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2133 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2134}
2135
2136
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2137static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2138 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2139 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2140
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2141 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2142 unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2143
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2145 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2146 if (!align)
2147 Inst.addOperand(MCOperand::CreateImm(0));
2148 else
2149 Inst.addOperand(MCOperand::CreateImm(4 << align));
2150
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2151 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2152}
2153
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2154static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2155 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2156 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2157
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2158 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2159 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2160 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2161 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2162 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2163 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2164
2165 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2166 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2167 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2168 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2169 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2170 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2171 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2172 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2173 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2174 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2175 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2176 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2177 return MCDisassembler::Fail;
2178 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2179 case ARM::VLD2b16:
2180 case ARM::VLD2b32:
2181 case ARM::VLD2b8:
2182 case ARM::VLD2b16wb_fixed:
2183 case ARM::VLD2b16wb_register:
2184 case ARM::VLD2b32wb_fixed:
2185 case ARM::VLD2b32wb_register:
2186 case ARM::VLD2b8wb_fixed:
2187 case ARM::VLD2b8wb_register:
2188 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2189 return MCDisassembler::Fail;
2190 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2191 default:
2192 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2193 return MCDisassembler::Fail;
2194 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2195
2196 // Second output register
2197 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2198 case ARM::VLD3d8:
2199 case ARM::VLD3d16:
2200 case ARM::VLD3d32:
2201 case ARM::VLD3d8_UPD:
2202 case ARM::VLD3d16_UPD:
2203 case ARM::VLD3d32_UPD:
2204 case ARM::VLD4d8:
2205 case ARM::VLD4d16:
2206 case ARM::VLD4d32:
2207 case ARM::VLD4d8_UPD:
2208 case ARM::VLD4d16_UPD:
2209 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2210 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2211 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2212 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2213 case ARM::VLD3q8:
2214 case ARM::VLD3q16:
2215 case ARM::VLD3q32:
2216 case ARM::VLD3q8_UPD:
2217 case ARM::VLD3q16_UPD:
2218 case ARM::VLD3q32_UPD:
2219 case ARM::VLD4q8:
2220 case ARM::VLD4q16:
2221 case ARM::VLD4q32:
2222 case ARM::VLD4q8_UPD:
2223 case ARM::VLD4q16_UPD:
2224 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2225 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2226 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2227 default:
2228 break;
2229 }
2230
2231 // Third output register
2232 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2233 case ARM::VLD3d8:
2234 case ARM::VLD3d16:
2235 case ARM::VLD3d32:
2236 case ARM::VLD3d8_UPD:
2237 case ARM::VLD3d16_UPD:
2238 case ARM::VLD3d32_UPD:
2239 case ARM::VLD4d8:
2240 case ARM::VLD4d16:
2241 case ARM::VLD4d32:
2242 case ARM::VLD4d8_UPD:
2243 case ARM::VLD4d16_UPD:
2244 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2245 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2246 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2247 break;
2248 case ARM::VLD3q8:
2249 case ARM::VLD3q16:
2250 case ARM::VLD3q32:
2251 case ARM::VLD3q8_UPD:
2252 case ARM::VLD3q16_UPD:
2253 case ARM::VLD3q32_UPD:
2254 case ARM::VLD4q8:
2255 case ARM::VLD4q16:
2256 case ARM::VLD4q32:
2257 case ARM::VLD4q8_UPD:
2258 case ARM::VLD4q16_UPD:
2259 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2260 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2261 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2262 break;
2263 default:
2264 break;
2265 }
2266
2267 // Fourth output register
2268 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2269 case ARM::VLD4d8:
2270 case ARM::VLD4d16:
2271 case ARM::VLD4d32:
2272 case ARM::VLD4d8_UPD:
2273 case ARM::VLD4d16_UPD:
2274 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2275 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2276 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2277 break;
2278 case ARM::VLD4q8:
2279 case ARM::VLD4q16:
2280 case ARM::VLD4q32:
2281 case ARM::VLD4q8_UPD:
2282 case ARM::VLD4q16_UPD:
2283 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2284 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2285 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2286 break;
2287 default:
2288 break;
2289 }
2290
2291 // Writeback operand
2292 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2293 case ARM::VLD1d8wb_fixed:
2294 case ARM::VLD1d16wb_fixed:
2295 case ARM::VLD1d32wb_fixed:
2296 case ARM::VLD1d64wb_fixed:
2297 case ARM::VLD1d8wb_register:
2298 case ARM::VLD1d16wb_register:
2299 case ARM::VLD1d32wb_register:
2300 case ARM::VLD1d64wb_register:
2301 case ARM::VLD1q8wb_fixed:
2302 case ARM::VLD1q16wb_fixed:
2303 case ARM::VLD1q32wb_fixed:
2304 case ARM::VLD1q64wb_fixed:
2305 case ARM::VLD1q8wb_register:
2306 case ARM::VLD1q16wb_register:
2307 case ARM::VLD1q32wb_register:
2308 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2309 case ARM::VLD1d8Twb_fixed:
2310 case ARM::VLD1d8Twb_register:
2311 case ARM::VLD1d16Twb_fixed:
2312 case ARM::VLD1d16Twb_register:
2313 case ARM::VLD1d32Twb_fixed:
2314 case ARM::VLD1d32Twb_register:
2315 case ARM::VLD1d64Twb_fixed:
2316 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2317 case ARM::VLD1d8Qwb_fixed:
2318 case ARM::VLD1d8Qwb_register:
2319 case ARM::VLD1d16Qwb_fixed:
2320 case ARM::VLD1d16Qwb_register:
2321 case ARM::VLD1d32Qwb_fixed:
2322 case ARM::VLD1d32Qwb_register:
2323 case ARM::VLD1d64Qwb_fixed:
2324 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2325 case ARM::VLD2d8wb_fixed:
2326 case ARM::VLD2d16wb_fixed:
2327 case ARM::VLD2d32wb_fixed:
2328 case ARM::VLD2q8wb_fixed:
2329 case ARM::VLD2q16wb_fixed:
2330 case ARM::VLD2q32wb_fixed:
2331 case ARM::VLD2d8wb_register:
2332 case ARM::VLD2d16wb_register:
2333 case ARM::VLD2d32wb_register:
2334 case ARM::VLD2q8wb_register:
2335 case ARM::VLD2q16wb_register:
2336 case ARM::VLD2q32wb_register:
2337 case ARM::VLD2b8wb_fixed:
2338 case ARM::VLD2b16wb_fixed:
2339 case ARM::VLD2b32wb_fixed:
2340 case ARM::VLD2b8wb_register:
2341 case ARM::VLD2b16wb_register:
2342 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2343 Inst.addOperand(MCOperand::CreateImm(0));
2344 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2345 case ARM::VLD3d8_UPD:
2346 case ARM::VLD3d16_UPD:
2347 case ARM::VLD3d32_UPD:
2348 case ARM::VLD3q8_UPD:
2349 case ARM::VLD3q16_UPD:
2350 case ARM::VLD3q32_UPD:
2351 case ARM::VLD4d8_UPD:
2352 case ARM::VLD4d16_UPD:
2353 case ARM::VLD4d32_UPD:
2354 case ARM::VLD4q8_UPD:
2355 case ARM::VLD4q16_UPD:
2356 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2357 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2358 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2359 break;
2360 default:
2361 break;
2362 }
2363
2364 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2365 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2366 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2367
2368 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2369 switch (Inst.getOpcode()) {
2370 default:
2371 // The below have been updated to have explicit am6offset split
2372 // between fixed and register offset. For those instructions not
2373 // yet updated, we need to add an additional reg0 operand for the
2374 // fixed variant.
2375 //
2376 // The fixed offset encodes as Rm == 0xd, so we check for that.
2377 if (Rm == 0xd) {
2378 Inst.addOperand(MCOperand::CreateReg(0));
2379 break;
2380 }
2381 // Fall through to handle the register offset variant.
2382 case ARM::VLD1d8wb_fixed:
2383 case ARM::VLD1d16wb_fixed:
2384 case ARM::VLD1d32wb_fixed:
2385 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2386 case ARM::VLD1d8Twb_fixed:
2387 case ARM::VLD1d16Twb_fixed:
2388 case ARM::VLD1d32Twb_fixed:
2389 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2390 case ARM::VLD1d8Qwb_fixed:
2391 case ARM::VLD1d16Qwb_fixed:
2392 case ARM::VLD1d32Qwb_fixed:
2393 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2394 case ARM::VLD1d8wb_register:
2395 case ARM::VLD1d16wb_register:
2396 case ARM::VLD1d32wb_register:
2397 case ARM::VLD1d64wb_register:
2398 case ARM::VLD1q8wb_fixed:
2399 case ARM::VLD1q16wb_fixed:
2400 case ARM::VLD1q32wb_fixed:
2401 case ARM::VLD1q64wb_fixed:
2402 case ARM::VLD1q8wb_register:
2403 case ARM::VLD1q16wb_register:
2404 case ARM::VLD1q32wb_register:
2405 case ARM::VLD1q64wb_register:
2406 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2407 // variant encodes Rm == 0xf. Anything else is a register offset post-
2408 // increment and we need to add the register operand to the instruction.
2409 if (Rm != 0xD && Rm != 0xF &&
2410 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2411 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2412 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2413 case ARM::VLD2d8wb_fixed:
2414 case ARM::VLD2d16wb_fixed:
2415 case ARM::VLD2d32wb_fixed:
2416 case ARM::VLD2b8wb_fixed:
2417 case ARM::VLD2b16wb_fixed:
2418 case ARM::VLD2b32wb_fixed:
2419 case ARM::VLD2q8wb_fixed:
2420 case ARM::VLD2q16wb_fixed:
2421 case ARM::VLD2q32wb_fixed:
2422 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2423 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2424
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2425 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2426}
2427
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2428static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2429 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2430 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2431
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2432 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2433 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2434 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2435 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2436 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2437 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2438
2439 // Writeback Operand
2440 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2441 case ARM::VST1d8wb_fixed:
2442 case ARM::VST1d16wb_fixed:
2443 case ARM::VST1d32wb_fixed:
2444 case ARM::VST1d64wb_fixed:
2445 case ARM::VST1d8wb_register:
2446 case ARM::VST1d16wb_register:
2447 case ARM::VST1d32wb_register:
2448 case ARM::VST1d64wb_register:
2449 case ARM::VST1q8wb_fixed:
2450 case ARM::VST1q16wb_fixed:
2451 case ARM::VST1q32wb_fixed:
2452 case ARM::VST1q64wb_fixed:
2453 case ARM::VST1q8wb_register:
2454 case ARM::VST1q16wb_register:
2455 case ARM::VST1q32wb_register:
2456 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2457 case ARM::VST1d8Twb_fixed:
2458 case ARM::VST1d16Twb_fixed:
2459 case ARM::VST1d32Twb_fixed:
2460 case ARM::VST1d64Twb_fixed:
2461 case ARM::VST1d8Twb_register:
2462 case ARM::VST1d16Twb_register:
2463 case ARM::VST1d32Twb_register:
2464 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2465 case ARM::VST1d8Qwb_fixed:
2466 case ARM::VST1d16Qwb_fixed:
2467 case ARM::VST1d32Qwb_fixed:
2468 case ARM::VST1d64Qwb_fixed:
2469 case ARM::VST1d8Qwb_register:
2470 case ARM::VST1d16Qwb_register:
2471 case ARM::VST1d32Qwb_register:
2472 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2473 case ARM::VST2d8wb_fixed:
2474 case ARM::VST2d16wb_fixed:
2475 case ARM::VST2d32wb_fixed:
2476 case ARM::VST2d8wb_register:
2477 case ARM::VST2d16wb_register:
2478 case ARM::VST2d32wb_register:
2479 case ARM::VST2q8wb_fixed:
2480 case ARM::VST2q16wb_fixed:
2481 case ARM::VST2q32wb_fixed:
2482 case ARM::VST2q8wb_register:
2483 case ARM::VST2q16wb_register:
2484 case ARM::VST2q32wb_register:
2485 case ARM::VST2b8wb_fixed:
2486 case ARM::VST2b16wb_fixed:
2487 case ARM::VST2b32wb_fixed:
2488 case ARM::VST2b8wb_register:
2489 case ARM::VST2b16wb_register:
2490 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame]2491 if (Rm == 0xF)
2492 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2493 Inst.addOperand(MCOperand::CreateImm(0));
2494 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2495 case ARM::VST3d8_UPD:
2496 case ARM::VST3d16_UPD:
2497 case ARM::VST3d32_UPD:
2498 case ARM::VST3q8_UPD:
2499 case ARM::VST3q16_UPD:
2500 case ARM::VST3q32_UPD:
2501 case ARM::VST4d8_UPD:
2502 case ARM::VST4d16_UPD:
2503 case ARM::VST4d32_UPD:
2504 case ARM::VST4q8_UPD:
2505 case ARM::VST4q16_UPD:
2506 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2507 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2508 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2509 break;
2510 default:
2511 break;
2512 }
2513
2514 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2515 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2516 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2517
2518 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2519 switch (Inst.getOpcode()) {
2520 default:
2521 if (Rm == 0xD)
2522 Inst.addOperand(MCOperand::CreateReg(0));
2523 else if (Rm != 0xF) {
2524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2525 return MCDisassembler::Fail;
2526 }
2527 break;
2528 case ARM::VST1d8wb_fixed:
2529 case ARM::VST1d16wb_fixed:
2530 case ARM::VST1d32wb_fixed:
2531 case ARM::VST1d64wb_fixed:
2532 case ARM::VST1q8wb_fixed:
2533 case ARM::VST1q16wb_fixed:
2534 case ARM::VST1q32wb_fixed:
2535 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2536 case ARM::VST1d8Twb_fixed:
2537 case ARM::VST1d16Twb_fixed:
2538 case ARM::VST1d32Twb_fixed:
2539 case ARM::VST1d64Twb_fixed:
2540 case ARM::VST1d8Qwb_fixed:
2541 case ARM::VST1d16Qwb_fixed:
2542 case ARM::VST1d32Qwb_fixed:
2543 case ARM::VST1d64Qwb_fixed:
2544 case ARM::VST2d8wb_fixed:
2545 case ARM::VST2d16wb_fixed:
2546 case ARM::VST2d32wb_fixed:
2547 case ARM::VST2q8wb_fixed:
2548 case ARM::VST2q16wb_fixed:
2549 case ARM::VST2q32wb_fixed:
2550 case ARM::VST2b8wb_fixed:
2551 case ARM::VST2b16wb_fixed:
2552 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2553 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2554 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2555
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2556
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2557 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2558 switch (Inst.getOpcode()) {
2559 case ARM::VST1q16:
2560 case ARM::VST1q32:
2561 case ARM::VST1q64:
2562 case ARM::VST1q8:
2563 case ARM::VST1q16wb_fixed:
2564 case ARM::VST1q16wb_register:
2565 case ARM::VST1q32wb_fixed:
2566 case ARM::VST1q32wb_register:
2567 case ARM::VST1q64wb_fixed:
2568 case ARM::VST1q64wb_register:
2569 case ARM::VST1q8wb_fixed:
2570 case ARM::VST1q8wb_register:
2571 case ARM::VST2d16:
2572 case ARM::VST2d32:
2573 case ARM::VST2d8:
2574 case ARM::VST2d16wb_fixed:
2575 case ARM::VST2d16wb_register:
2576 case ARM::VST2d32wb_fixed:
2577 case ARM::VST2d32wb_register:
2578 case ARM::VST2d8wb_fixed:
2579 case ARM::VST2d8wb_register:
2580 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2581 return MCDisassembler::Fail;
2582 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2583 case ARM::VST2b16:
2584 case ARM::VST2b32:
2585 case ARM::VST2b8:
2586 case ARM::VST2b16wb_fixed:
2587 case ARM::VST2b16wb_register:
2588 case ARM::VST2b32wb_fixed:
2589 case ARM::VST2b32wb_register:
2590 case ARM::VST2b8wb_fixed:
2591 case ARM::VST2b8wb_register:
2592 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2593 return MCDisassembler::Fail;
2594 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2595 default:
2596 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2597 return MCDisassembler::Fail;
2598 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2599
2600 // Second input register
2601 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2602 case ARM::VST3d8:
2603 case ARM::VST3d16:
2604 case ARM::VST3d32:
2605 case ARM::VST3d8_UPD:
2606 case ARM::VST3d16_UPD:
2607 case ARM::VST3d32_UPD:
2608 case ARM::VST4d8:
2609 case ARM::VST4d16:
2610 case ARM::VST4d32:
2611 case ARM::VST4d8_UPD:
2612 case ARM::VST4d16_UPD:
2613 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2614 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2615 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2616 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2617 case ARM::VST3q8:
2618 case ARM::VST3q16:
2619 case ARM::VST3q32:
2620 case ARM::VST3q8_UPD:
2621 case ARM::VST3q16_UPD:
2622 case ARM::VST3q32_UPD:
2623 case ARM::VST4q8:
2624 case ARM::VST4q16:
2625 case ARM::VST4q32:
2626 case ARM::VST4q8_UPD:
2627 case ARM::VST4q16_UPD:
2628 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2629 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2630 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2631 break;
2632 default:
2633 break;
2634 }
2635
2636 // Third input register
2637 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2638 case ARM::VST3d8:
2639 case ARM::VST3d16:
2640 case ARM::VST3d32:
2641 case ARM::VST3d8_UPD:
2642 case ARM::VST3d16_UPD:
2643 case ARM::VST3d32_UPD:
2644 case ARM::VST4d8:
2645 case ARM::VST4d16:
2646 case ARM::VST4d32:
2647 case ARM::VST4d8_UPD:
2648 case ARM::VST4d16_UPD:
2649 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2650 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2651 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2652 break;
2653 case ARM::VST3q8:
2654 case ARM::VST3q16:
2655 case ARM::VST3q32:
2656 case ARM::VST3q8_UPD:
2657 case ARM::VST3q16_UPD:
2658 case ARM::VST3q32_UPD:
2659 case ARM::VST4q8:
2660 case ARM::VST4q16:
2661 case ARM::VST4q32:
2662 case ARM::VST4q8_UPD:
2663 case ARM::VST4q16_UPD:
2664 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2665 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2666 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2667 break;
2668 default:
2669 break;
2670 }
2671
2672 // Fourth input register
2673 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2674 case ARM::VST4d8:
2675 case ARM::VST4d16:
2676 case ARM::VST4d32:
2677 case ARM::VST4d8_UPD:
2678 case ARM::VST4d16_UPD:
2679 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2680 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2681 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682 break;
2683 case ARM::VST4q8:
2684 case ARM::VST4q16:
2685 case ARM::VST4q32:
2686 case ARM::VST4q8_UPD:
2687 case ARM::VST4q16_UPD:
2688 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2689 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2690 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2691 break;
2692 default:
2693 break;
2694 }
2695
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2696 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2697}
2698
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2699static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2700 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2701 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2702
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2703 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2704 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2705 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2706 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2707 unsigned align = fieldFromInstruction(Insn, 4, 1);
2708 unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2709
Tim Northover24b9f252012-09-06 15:27:12 +0000[diff] [blame]2710 if (size == 0 && align == 1)
2711 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2712 align *= (1 << size);
2713
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2714 switch (Inst.getOpcode()) {
2715 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2716 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2717 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2718 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2719 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2720 return MCDisassembler::Fail;
2721 break;
2722 default:
2723 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2724 return MCDisassembler::Fail;
2725 break;
2726 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2727 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2729 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2730 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2731
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2733 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2734 Inst.addOperand(MCOperand::CreateImm(align));
2735
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2736 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2737 // variant encodes Rm == 0xf. Anything else is a register offset post-
2738 // increment and we need to add the register operand to the instruction.
2739 if (Rm != 0xD && Rm != 0xF &&
2740 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2741 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2742
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2743 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2744}
2745
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2746static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2747 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2748 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2749
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2750 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2751 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2752 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2753 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2754 unsigned align = fieldFromInstruction(Insn, 4, 1);
2755 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2756 align *= 2*size;
2757
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2758 switch (Inst.getOpcode()) {
2759 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2760 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2761 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2762 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2763 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2764 return MCDisassembler::Fail;
2765 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2766 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2767 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2768 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2769 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2770 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2771 return MCDisassembler::Fail;
2772 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2773 default:
2774 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2775 return MCDisassembler::Fail;
2776 break;
2777 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2778
2779 if (Rm != 0xF)
2780 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2781
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2783 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2784 Inst.addOperand(MCOperand::CreateImm(align));
2785
Kevin Enderbyc5a2a332012-04-17 00:49:27 +0000[diff] [blame]2786 if (Rm != 0xD && Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2788 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2789 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2790
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2791 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2792}
2793
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2794static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2795 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2796 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2797
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2798 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2799 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2800 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2801 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2802 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2803
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2804 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2805 return MCDisassembler::Fail;
2806 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2807 return MCDisassembler::Fail;
2808 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2809 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2810 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2812 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2813 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2814
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2816 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817 Inst.addOperand(MCOperand::CreateImm(0));
2818
2819 if (Rm == 0xD)
2820 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2821 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2823 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2824 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2825
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2826 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2827}
2828
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2829static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2830 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2831 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2832
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2833 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2834 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2835 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2836 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2837 unsigned size = fieldFromInstruction(Insn, 6, 2);
2838 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2839 unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2840
2841 if (size == 0x3) {
Tim Northover24b9f252012-09-06 15:27:12 +0000[diff] [blame]2842 if (align == 0)
2843 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2844 size = 4;
2845 align = 16;
2846 } else {
2847 if (size == 2) {
2848 size = 1 << size;
2849 align *= 8;
2850 } else {
2851 size = 1 << size;
2852 align *= 4*size;
2853 }
2854 }
2855
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2856 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2857 return MCDisassembler::Fail;
2858 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2859 return MCDisassembler::Fail;
2860 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2861 return MCDisassembler::Fail;
2862 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2863 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2864 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2866 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2867 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2868
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2870 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2871 Inst.addOperand(MCOperand::CreateImm(align));
2872
2873 if (Rm == 0xD)
2874 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2875 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2877 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2878 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2879
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2880 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2881}
2882
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2883static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2884DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2885 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2886 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2887
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2888 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2889 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2890 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2891 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2892 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2893 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2894 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2895 unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2896
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2897 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2898 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2899 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2900 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2901 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2902 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2903 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2904
2905 Inst.addOperand(MCOperand::CreateImm(imm));
2906
2907 switch (Inst.getOpcode()) {
2908 case ARM::VORRiv4i16:
2909 case ARM::VORRiv2i32:
2910 case ARM::VBICiv4i16:
2911 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2913 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2914 break;
2915 case ARM::VORRiv8i16:
2916 case ARM::VORRiv4i32:
2917 case ARM::VBICiv8i16:
2918 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2919 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2920 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2921 break;
2922 default:
2923 break;
2924 }
2925
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2926 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2927}
2928
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2929static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2930 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2931 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2932
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2933 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2934 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2935 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2936 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2937 unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2938
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2939 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2940 return MCDisassembler::Fail;
2941 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2942 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2943 Inst.addOperand(MCOperand::CreateImm(8 << size));
2944
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2945 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2946}
2947
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2948static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2949 uint64_t Address, const void *Decoder) {
2950 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2951 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2952}
2953
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2954static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2955 uint64_t Address, const void *Decoder) {
2956 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2957 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2958}
2959
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2960static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2961 uint64_t Address, const void *Decoder) {
2962 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2963 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2964}
2965
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2966static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2967 uint64_t Address, const void *Decoder) {
2968 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2969 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2970}
2971
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2972static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2973 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2974 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2975
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2976 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2977 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2978 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2979 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2980 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2981 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2982 unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2983
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2984 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2985 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2986 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2987 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2988 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2989 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2990
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2991 switch (Inst.getOpcode()) {
2992 case ARM::VTBL2:
2993 case ARM::VTBX2:
2994 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996 break;
2997 default:
2998 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2999 return MCDisassembler::Fail;
3000 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3001
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3003 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3004
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3005 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3006}
3007
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3008static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3009 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3010 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3011
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3012 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3013 unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3015 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3016 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3017
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3018 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]3019 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3020 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3021 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]3022 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3023 case ARM::tADDrSPi:
3024 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3025 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3026 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3027
3028 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3029 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3030}
3031
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3032static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3033 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3034 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3035 true, 2, Inst, Decoder))
3036 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3037 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3038}
3039
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3040static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3041 uint64_t Address, const void *Decoder) {
Kevin Enderby3610a152012-05-04 22:09:52 +0000[diff] [blame]3042 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3043 true, 4, Inst, Decoder))
3044 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3045 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3046}
3047
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3048static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3049 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3050 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
3051 true, 2, Inst, Decoder))
3052 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3053 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3054}
3055
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3056static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3057 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3058 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3059
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3060 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3061 unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3062
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3063 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3064 return MCDisassembler::Fail;
3065 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3066 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3067
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3068 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3069}
3070
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3071static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3072 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3073 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3074
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3075 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3076 unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3077
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3078 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3079 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3080 Inst.addOperand(MCOperand::CreateImm(imm));
3081
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3082 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3083}
3084
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3085static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3086 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3087 unsigned imm = Val << 2;
3088
3089 Inst.addOperand(MCOperand::CreateImm(imm));
3090 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3091
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3092 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3093}
3094
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3095static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3096 uint64_t Address, const void *Decoder) {
3097 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3098 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3099
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3100 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3101}
3102
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3103static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3104 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3105 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3106
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3107 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3108 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3109 unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3110
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3112 return MCDisassembler::Fail;
3113 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3114 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3115 Inst.addOperand(MCOperand::CreateImm(imm));
3116
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3117 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3118}
3119
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3120static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3121 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3122 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3123
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3124 switch (Inst.getOpcode()) {
3125 case ARM::t2PLDs:
3126 case ARM::t2PLDWs:
3127 case ARM::t2PLIs:
3128 break;
3129 default: {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3130 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3131 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3132 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3133 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3134 }
3135
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3136 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3137 if (Rn == 0xF) {
3138 switch (Inst.getOpcode()) {
3139 case ARM::t2LDRBs:
3140 Inst.setOpcode(ARM::t2LDRBpci);
3141 break;
3142 case ARM::t2LDRHs:
3143 Inst.setOpcode(ARM::t2LDRHpci);
3144 break;
3145 case ARM::t2LDRSHs:
3146 Inst.setOpcode(ARM::t2LDRSHpci);
3147 break;
3148 case ARM::t2LDRSBs:
3149 Inst.setOpcode(ARM::t2LDRSBpci);
3150 break;
3151 case ARM::t2PLDs:
3152 Inst.setOpcode(ARM::t2PLDi12);
3153 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3154 break;
3155 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3156 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3157 }
3158
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3159 int imm = fieldFromInstruction(Insn, 0, 12);
3160 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3161 Inst.addOperand(MCOperand::CreateImm(imm));
3162
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3163 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3164 }
3165
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3166 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3167 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3168 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3169 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3170 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3171
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3172 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3173}
3174
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3175static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3176 uint64_t Address, const void *Decoder) {
Jiangning Liufd652df2012-08-02 08:29:50 +0000[diff] [blame]3177 if (Val == 0)
3178 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3179 else {
3180 int imm = Val & 0xFF;
3181
3182 if (!(Val & 0x100)) imm *= -1;
Richard Smith1144af32012-08-24 23:29:28 +0000[diff] [blame]3183 Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liufd652df2012-08-02 08:29:50 +0000[diff] [blame]3184 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3185
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3186 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3187}
3188
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3189static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3190 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3191 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3192
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3193 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3194 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3195
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3197 return MCDisassembler::Fail;
3198 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3199 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3200
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3201 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3202}
3203
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3204static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3205 uint64_t Address, const void *Decoder) {
3206 DecodeStatus S = MCDisassembler::Success;
3207
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3208 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3209 unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3210
3211 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3212 return MCDisassembler::Fail;
3213
3214 Inst.addOperand(MCOperand::CreateImm(imm));
3215
3216 return S;
3217}
3218
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3219static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3220 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3221 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3222 if (Val == 0)
3223 imm = INT32_MIN;
3224 else if (!(Val & 0x100))
3225 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3226 Inst.addOperand(MCOperand::CreateImm(imm));
3227
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3228 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3229}
3230
3231
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3232static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3233 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3234 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3235
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3236 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3237 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3238
3239 // Some instructions always use an additive offset.
3240 switch (Inst.getOpcode()) {
3241 case ARM::t2LDRT:
3242 case ARM::t2LDRBT:
3243 case ARM::t2LDRHT:
3244 case ARM::t2LDRSBT:
3245 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3246 case ARM::t2STRT:
3247 case ARM::t2STRBT:
3248 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3249 imm |= 0x100;
3250 break;
3251 default:
3252 break;
3253 }
3254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3256 return MCDisassembler::Fail;
3257 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3258 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3259
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3260 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3261}
3262
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3263static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3264 uint64_t Address, const void *Decoder) {
3265 DecodeStatus S = MCDisassembler::Success;
3266
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3267 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3268 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3269 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3270 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3271 addr |= Rn << 9;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3272 unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3273
3274 if (!load) {
3275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3276 return MCDisassembler::Fail;
3277 }
3278
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]3279 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3280 return MCDisassembler::Fail;
3281
3282 if (load) {
3283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3284 return MCDisassembler::Fail;
3285 }
3286
3287 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3288 return MCDisassembler::Fail;
3289
3290 return S;
3291}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3292
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3293static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3294 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3295 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3296
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3297 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3298 unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3299
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3301 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3302 Inst.addOperand(MCOperand::CreateImm(imm));
3303
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3304 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3305}
3306
3307
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3308static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3309 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3310 unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3311
3312 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3313 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3314 Inst.addOperand(MCOperand::CreateImm(imm));
3315
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3316 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3317}
3318
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3319static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3320 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3321 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3322
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3323 if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3324 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3325 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3326
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3328 return MCDisassembler::Fail;
Jim Grosbachbb32f1d2012-04-27 23:51:33 +0000[diff] [blame]3329 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3331 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3332 } else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3333 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3334
3335 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3336 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3338 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3339 }
3340
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3341 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3342}
3343
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3344static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3345 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3346 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3347 unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3348
3349 Inst.addOperand(MCOperand::CreateImm(imod));
3350 Inst.addOperand(MCOperand::CreateImm(flags));
3351
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3352 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3353}
3354
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3355static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3356 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3357 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3358 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3359 unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3360
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3361 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3362 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3363 Inst.addOperand(MCOperand::CreateImm(add));
3364
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3365 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3366}
3367
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3368static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3369 uint64_t Address, const void *Decoder) {
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3370 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3371 // Note only one trailing zero not two. Also the J1 and J2 values are from
3372 // the encoded instruction. So here change to I1 and I2 values via:
3373 // I1 = NOT(J1 EOR S);
3374 // I2 = NOT(J2 EOR S);
3375 // and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3376 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3377 unsigned S = (Val >> 23) & 1;
3378 unsigned J1 = (Val >> 22) & 1;
3379 unsigned J2 = (Val >> 21) & 1;
3380 unsigned I1 = !(J1 ^ S);
3381 unsigned I2 = !(J2 ^ S);
3382 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3383 int imm32 = SignExtend32<25>(tmp << 1);
3384
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3385 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3386 (Address & ~2u) + imm32 + 4,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3387 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3388 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3389 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3390}
3391
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3392static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3393 uint64_t Address, const void *Decoder) {
3394 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3395 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3396
3397 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3398 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3399}
3400
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3401static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3402DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3403 uint64_t Address, const void *Decoder) {
3404 DecodeStatus S = MCDisassembler::Success;
3405
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3406 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3407 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3408
3409 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3411 return MCDisassembler::Fail;
3412 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3413 return MCDisassembler::Fail;
3414 return S;
3415}
3416
3417static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3418DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3419 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3420 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3421
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3422 unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3423 if (pred == 0xE || pred == 0xF) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3424 unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3425 switch (opc) {
3426 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3427 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3428 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3429 Inst.setOpcode(ARM::t2DSB);
3430 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3431 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3432 Inst.setOpcode(ARM::t2DMB);
3433 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3434 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3435 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3436 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3437 }
3438
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3439 unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3440 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3441 }
3442
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3443 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3444 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3445 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3446 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3447 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3448
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3449 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3450 return MCDisassembler::Fail;
3451 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3452 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3453
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3454 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3455}
3456
3457// Decode a shifted immediate operand. These basically consist
3458// of an 8-bit value, and a 4-bit directive that specifies either
3459// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3460static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3461 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3462 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3463 if (ctrl == 0) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3464 unsigned byte = fieldFromInstruction(Val, 8, 2);
3465 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3466 switch (byte) {
3467 case 0:
3468 Inst.addOperand(MCOperand::CreateImm(imm));
3469 break;
3470 case 1:
3471 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3472 break;
3473 case 2:
3474 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3475 break;
3476 case 3:
3477 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3478 (imm << 8) | imm));
3479 break;
3480 }
3481 } else {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3482 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3483 unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3484 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3485 Inst.addOperand(MCOperand::CreateImm(imm));
3486 }
3487
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3488 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3489}
3490
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3491static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3492DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3493 uint64_t Address, const void *Decoder){
Richard Bartonc8f2fcc2012-06-06 09:12:53 +0000[diff] [blame]3494 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3495 true, 2, Inst, Decoder))
Richard Bartonc8f2fcc2012-06-06 09:12:53 +0000[diff] [blame]3496 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3497 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3498}
3499
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3500static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3501 uint64_t Address, const void *Decoder){
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3502 // Val is passed in as S:J1:J2:imm10:imm11
3503 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3504 // the encoded instruction. So here change to I1 and I2 values via:
3505 // I1 = NOT(J1 EOR S);
3506 // I2 = NOT(J2 EOR S);
3507 // and build the imm32 with one trailing zero as documented:
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3508 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3509 unsigned S = (Val >> 23) & 1;
3510 unsigned J1 = (Val >> 22) & 1;
3511 unsigned J2 = (Val >> 21) & 1;
3512 unsigned I1 = !(J1 ^ S);
3513 unsigned I2 = !(J2 ^ S);
3514 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3515 int imm32 = SignExtend32<25>(tmp << 1);
3516
3517 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3518 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3519 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3520 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3521}
3522
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3523static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3524 uint64_t Address, const void *Decoder) {
Jiangning Liuc1b7ca52012-08-02 08:21:27 +0000[diff] [blame]3525 if (Val & ~0xf)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3526 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3527
3528 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3529 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3530}
3531
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3532static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3533 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3534 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3535 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3536 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3537}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3538
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3539static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3540 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3541 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3542
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3543 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3544 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3545 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3546
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3547 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3548
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3550 return MCDisassembler::Fail;
3551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3552 return MCDisassembler::Fail;
3553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3554 return MCDisassembler::Fail;
3555 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3556 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3557
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3558 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3559}
3560
3561
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3562static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3563 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3564 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3565
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3566 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3567 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3568 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3569 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3570
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3571 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3572 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3573
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3574 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3575 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3576
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3578 return MCDisassembler::Fail;
3579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3580 return MCDisassembler::Fail;
3581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3582 return MCDisassembler::Fail;
3583 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3584 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3585
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3586 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3587}
3588
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3589static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3590 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3591 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3592
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3593 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3594 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3595 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3596 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3597 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3598 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3599
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3600 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3601
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3603 return MCDisassembler::Fail;
3604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3605 return MCDisassembler::Fail;
3606 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3607 return MCDisassembler::Fail;
3608 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3609 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3610
3611 return S;
3612}
3613
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3614static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3615 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3616 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3617
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3618 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3619 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3620 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3621 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3622 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3623 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3624 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3625
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3626 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3627 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3628
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3630 return MCDisassembler::Fail;
3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3632 return MCDisassembler::Fail;
3633 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3634 return MCDisassembler::Fail;
3635 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3636 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3637
3638 return S;
3639}
3640
3641
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3642static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3643 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3644 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3645
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3646 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3647 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3648 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3649 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3650 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3651 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3652
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3653 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3654
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3656 return MCDisassembler::Fail;
3657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3658 return MCDisassembler::Fail;
3659 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3660 return MCDisassembler::Fail;
3661 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3662 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3663
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3664 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3665}
3666
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3667static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3668 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3669 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3670
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3671 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3672 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3673 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3674 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3675 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3676 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3677
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3678 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3679
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3681 return MCDisassembler::Fail;
3682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3683 return MCDisassembler::Fail;
3684 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3685 return MCDisassembler::Fail;
3686 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3687 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3688
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3689 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3690}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3691
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3692static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3693 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3694 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3695
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3696 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3697 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3698 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3699 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3700 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3701
3702 unsigned align = 0;
3703 unsigned index = 0;
3704 switch (size) {
3705 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3706 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3707 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3708 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3709 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3710 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3711 break;
3712 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3713 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3714 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3715 index = fieldFromInstruction(Insn, 6, 2);
3716 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3717 align = 2;
3718 break;
3719 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3720 if (fieldFromInstruction(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3721 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3722 index = fieldFromInstruction(Insn, 7, 1);
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]3723
3724 switch (fieldFromInstruction(Insn, 4, 2)) {
3725 case 0 :
3726 align = 0; break;
3727 case 3:
3728 align = 4; break;
3729 default:
3730 return MCDisassembler::Fail;
3731 }
3732 break;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3733 }
3734
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3735 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3736 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3737 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3739 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3740 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3743 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3744 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3745 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3747 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3748 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3749 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3750 }
3751
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3753 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3754 Inst.addOperand(MCOperand::CreateImm(index));
3755
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3756 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3757}
3758
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3759static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3760 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3761 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3762
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3763 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3764 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3765 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3766 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3767 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3768
3769 unsigned align = 0;
3770 unsigned index = 0;
3771 switch (size) {
3772 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3773 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3774 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3775 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3776 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3777 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3778 break;
3779 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3780 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3781 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3782 index = fieldFromInstruction(Insn, 6, 2);
3783 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3784 align = 2;
3785 break;
3786 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3787 if (fieldFromInstruction(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3788 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3789 index = fieldFromInstruction(Insn, 7, 1);
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]3790
3791 switch (fieldFromInstruction(Insn, 4, 2)) {
3792 case 0:
3793 align = 0; break;
3794 case 3:
3795 align = 4; break;
3796 default:
3797 return MCDisassembler::Fail;
3798 }
3799 break;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3800 }
3801
3802 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3804 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3805 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3807 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3808 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3809 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3810 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3812 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3813 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3814 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3815 }
3816
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3817 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3818 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3819 Inst.addOperand(MCOperand::CreateImm(index));
3820
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3821 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3822}
3823
3824
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3825static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3826 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3827 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3828
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3829 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3830 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3831 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3832 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3833 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3834
3835 unsigned align = 0;
3836 unsigned index = 0;
3837 unsigned inc = 1;
3838 switch (size) {
3839 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3840 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3841 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3842 index = fieldFromInstruction(Insn, 5, 3);
3843 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3844 align = 2;
3845 break;
3846 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3847 index = fieldFromInstruction(Insn, 6, 2);
3848 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3849 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3850 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3851 inc = 2;
3852 break;
3853 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3854 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3855 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3856 index = fieldFromInstruction(Insn, 7, 1);
3857 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3858 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3859 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3860 inc = 2;
3861 break;
3862 }
3863
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3864 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3865 return MCDisassembler::Fail;
3866 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3867 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3868 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3870 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3871 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3873 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3874 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3875 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3876 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3878 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3879 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3880 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3881 }
3882
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3884 return MCDisassembler::Fail;
3885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3886 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3887 Inst.addOperand(MCOperand::CreateImm(index));
3888
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3889 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3890}
3891
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3892static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3893 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3894 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3895
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3896 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3897 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3898 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3899 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3900 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3901
3902 unsigned align = 0;
3903 unsigned index = 0;
3904 unsigned inc = 1;
3905 switch (size) {
3906 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3907 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3908 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3909 index = fieldFromInstruction(Insn, 5, 3);
3910 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3911 align = 2;
3912 break;
3913 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3914 index = fieldFromInstruction(Insn, 6, 2);
3915 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3916 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3917 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3918 inc = 2;
3919 break;
3920 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3921 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3922 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3923 index = fieldFromInstruction(Insn, 7, 1);
3924 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3925 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3926 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3927 inc = 2;
3928 break;
3929 }
3930
3931 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3933 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3934 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3936 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3937 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3938 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3939 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3941 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3942 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3943 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3944 }
3945
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3946 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3947 return MCDisassembler::Fail;
3948 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3949 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3950 Inst.addOperand(MCOperand::CreateImm(index));
3951
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3952 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3953}
3954
3955
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3956static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3957 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3958 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3959
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3960 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3961 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3962 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3963 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3964 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3965
3966 unsigned align = 0;
3967 unsigned index = 0;
3968 unsigned inc = 1;
3969 switch (size) {
3970 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3971 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3972 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3973 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3974 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3975 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3976 break;
3977 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3978 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3979 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3980 index = fieldFromInstruction(Insn, 6, 2);
3981 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3982 inc = 2;
3983 break;
3984 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3985 if (fieldFromInstruction(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3986 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3987 index = fieldFromInstruction(Insn, 7, 1);
3988 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3989 inc = 2;
3990 break;
3991 }
3992
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3993 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3994 return MCDisassembler::Fail;
3995 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3996 return MCDisassembler::Fail;
3997 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3998 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3999
4000 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4002 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4003 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4005 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4006 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4007 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4008 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4010 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4011 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4012 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4013 }
4014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4016 return MCDisassembler::Fail;
4017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4018 return MCDisassembler::Fail;
4019 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4020 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4021 Inst.addOperand(MCOperand::CreateImm(index));
4022
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4023 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4024}
4025
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4026static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4027 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4028 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4029
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4030 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4031 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4032 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4033 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4034 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4035
4036 unsigned align = 0;
4037 unsigned index = 0;
4038 unsigned inc = 1;
4039 switch (size) {
4040 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4041 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4042 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4043 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4044 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4045 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4046 break;
4047 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4048 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4049 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4050 index = fieldFromInstruction(Insn, 6, 2);
4051 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4052 inc = 2;
4053 break;
4054 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4055 if (fieldFromInstruction(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4056 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4057 index = fieldFromInstruction(Insn, 7, 1);
4058 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4059 inc = 2;
4060 break;
4061 }
4062
4063 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4065 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4066 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4068 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4069 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4070 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4071 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4073 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4074 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4075 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4076 }
4077
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4078 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4079 return MCDisassembler::Fail;
4080 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4081 return MCDisassembler::Fail;
4082 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4083 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4084 Inst.addOperand(MCOperand::CreateImm(index));
4085
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4086 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4087}
4088
4089
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4090static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4091 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4092 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4093
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4094 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4095 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4096 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4097 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4098 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4099
4100 unsigned align = 0;
4101 unsigned index = 0;
4102 unsigned inc = 1;
4103 switch (size) {
4104 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4105 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4106 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4107 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4108 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4109 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4110 break;
4111 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4112 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4113 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4114 index = fieldFromInstruction(Insn, 6, 2);
4115 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4116 inc = 2;
4117 break;
4118 case 2:
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]4119 switch (fieldFromInstruction(Insn, 4, 2)) {
4120 case 0:
4121 align = 0; break;
4122 case 3:
4123 return MCDisassembler::Fail;
4124 default:
4125 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4126 }
4127
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4128 index = fieldFromInstruction(Insn, 7, 1);
4129 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4130 inc = 2;
4131 break;
4132 }
4133
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4134 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4135 return MCDisassembler::Fail;
4136 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4137 return MCDisassembler::Fail;
4138 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4139 return MCDisassembler::Fail;
4140 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4141 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4142
4143 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4145 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4146 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4147 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4148 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4149 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4150 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4151 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4153 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4154 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4155 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4156 }
4157
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4159 return MCDisassembler::Fail;
4160 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4161 return MCDisassembler::Fail;
4162 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4163 return MCDisassembler::Fail;
4164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4165 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4166 Inst.addOperand(MCOperand::CreateImm(index));
4167
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4168 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4169}
4170
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4171static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4172 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4173 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4174
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4175 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4176 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4177 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4178 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4179 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4180
4181 unsigned align = 0;
4182 unsigned index = 0;
4183 unsigned inc = 1;
4184 switch (size) {
4185 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4186 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4187 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4188 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4189 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4190 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4191 break;
4192 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4193 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4194 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4195 index = fieldFromInstruction(Insn, 6, 2);
4196 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4197 inc = 2;
4198 break;
4199 case 2:
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]4200 switch (fieldFromInstruction(Insn, 4, 2)) {
4201 case 0:
4202 align = 0; break;
4203 case 3:
4204 return MCDisassembler::Fail;
4205 default:
4206 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4207 }
4208
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4209 index = fieldFromInstruction(Insn, 7, 1);
4210 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4211 inc = 2;
4212 break;
4213 }
4214
4215 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4217 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4218 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4220 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4221 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4222 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4223 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4225 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4226 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4227 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4228 }
4229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4230 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4233 return MCDisassembler::Fail;
4234 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4235 return MCDisassembler::Fail;
4236 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4237 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4238 Inst.addOperand(MCOperand::CreateImm(index));
4239
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4240 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4241}
4242
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4243static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4244 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4245 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4246 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4247 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4248 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4249 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4250 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4251
4252 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4253 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4255 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4256 return MCDisassembler::Fail;
4257 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4258 return MCDisassembler::Fail;
4259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4260 return MCDisassembler::Fail;
4261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4262 return MCDisassembler::Fail;
4263 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4264 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4265
4266 return S;
4267}
4268
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4269static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4270 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4271 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4272 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4273 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4274 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4275 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4276 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4277
4278 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4279 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4280
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4282 return MCDisassembler::Fail;
4283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4284 return MCDisassembler::Fail;
4285 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4286 return MCDisassembler::Fail;
4287 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4288 return MCDisassembler::Fail;
4289 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4290 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4291
4292 return S;
4293}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4294
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4295static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4296 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4297 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4298 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4299 unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4300
4301 if (pred == 0xF) {
4302 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4303 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4304 }
4305
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]4306 if (mask == 0x0) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4307 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4308 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4309 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4310
4311 Inst.addOperand(MCOperand::CreateImm(pred));
4312 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4313 return S;
4314}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4315
4316static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4317DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4318 uint64_t Address, const void *Decoder) {
4319 DecodeStatus S = MCDisassembler::Success;
4320
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4321 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4322 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4323 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4324 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4325 unsigned W = fieldFromInstruction(Insn, 21, 1);
4326 unsigned U = fieldFromInstruction(Insn, 23, 1);
4327 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4328 bool writeback = (W == 1) | (P == 0);
4329
4330 addr |= (U << 8) | (Rn << 9);
4331
4332 if (writeback && (Rn == Rt || Rn == Rt2))
4333 Check(S, MCDisassembler::SoftFail);
4334 if (Rt == Rt2)
4335 Check(S, MCDisassembler::SoftFail);
4336
4337 // Rt
4338 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4339 return MCDisassembler::Fail;
4340 // Rt2
4341 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4342 return MCDisassembler::Fail;
4343 // Writeback operand
4344 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4345 return MCDisassembler::Fail;
4346 // addr
4347 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4348 return MCDisassembler::Fail;
4349
4350 return S;
4351}
4352
4353static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4354DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4355 uint64_t Address, const void *Decoder) {
4356 DecodeStatus S = MCDisassembler::Success;
4357
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4358 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4359 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4360 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4361 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4362 unsigned W = fieldFromInstruction(Insn, 21, 1);
4363 unsigned U = fieldFromInstruction(Insn, 23, 1);
4364 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4365 bool writeback = (W == 1) | (P == 0);
4366
4367 addr |= (U << 8) | (Rn << 9);
4368
4369 if (writeback && (Rn == Rt || Rn == Rt2))
4370 Check(S, MCDisassembler::SoftFail);
4371
4372 // Writeback operand
4373 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4374 return MCDisassembler::Fail;
4375 // Rt
4376 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4377 return MCDisassembler::Fail;
4378 // Rt2
4379 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4380 return MCDisassembler::Fail;
4381 // addr
4382 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4383 return MCDisassembler::Fail;
4384
4385 return S;
4386}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4387
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4388static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4389 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4390 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4391 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4392 if (sign1 != sign2) return MCDisassembler::Fail;
4393
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4394 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4395 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4396 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4397 Val |= sign1 << 12;
4398 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4399
4400 return MCDisassembler::Success;
4401}
4402
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4403static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4404 uint64_t Address,
4405 const void *Decoder) {
4406 DecodeStatus S = MCDisassembler::Success;
4407
4408 // Shift of "asr #32" is not allowed in Thumb2 mode.
4409 if (Val == 0x20) S = MCDisassembler::SoftFail;
4410 Inst.addOperand(MCOperand::CreateImm(Val));
4411 return S;
4412}
4413
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4414static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4415 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4416 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4417 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4418 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4419 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4420
4421 if (pred == 0xF)
4422 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4423
4424 DecodeStatus S = MCDisassembler::Success;
Silviu Baranga35ee7d22012-04-18 14:18:57 +0000[diff] [blame]4425
4426 if (Rt == Rn || Rn == Rt2)
4427 S = MCDisassembler::SoftFail;
4428
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4429 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4430 return MCDisassembler::Fail;
4431 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4432 return MCDisassembler::Fail;
4433 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4434 return MCDisassembler::Fail;
4435 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4436 return MCDisassembler::Fail;
4437
4438 return S;
4439}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4440
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4441static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4442 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4443 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4444 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4445 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4446 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4447 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4448 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4449
4450 DecodeStatus S = MCDisassembler::Success;
4451
4452 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4453 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4454 Inst.setOpcode(ARM::VMOVv2f32);
4455 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4456 }
4457
4458 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4459
4460 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4461 return MCDisassembler::Fail;
4462 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4463 return MCDisassembler::Fail;
4464 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4465
4466 return S;
4467}
4468
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4469static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4470 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4471 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4472 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4473 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4474 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4475 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4476 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4477
4478 DecodeStatus S = MCDisassembler::Success;
4479
4480 // VMOVv4f32 is ambiguous with these decodings.
4481 if (!(imm & 0x38) && cmode == 0xF) {
4482 Inst.setOpcode(ARM::VMOVv4f32);
4483 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4484 }
4485
4486 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4487
4488 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4489 return MCDisassembler::Fail;
4490 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4491 return MCDisassembler::Fail;
4492 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4493
4494 return S;
4495}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4496
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4497static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4498 uint64_t Address, const void *Decoder) {
4499 DecodeStatus S = MCDisassembler::Success;
4500
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4501 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4502 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4503 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4504 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4505 unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4506
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4507 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4508 S = MCDisassembler::SoftFail;
4509
4510 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4511 return MCDisassembler::Fail;
4512 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4513 return MCDisassembler::Fail;
4514 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4515 return MCDisassembler::Fail;
4516 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4517 return MCDisassembler::Fail;
4518 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4519 return MCDisassembler::Fail;
4520
4521 return S;
4522}
4523
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4524static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4525 uint64_t Address, const void *Decoder) {
4526
4527 DecodeStatus S = MCDisassembler::Success;
4528
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4529 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4530 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4531 unsigned cop = fieldFromInstruction(Val, 8, 4);
4532 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4533 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4534
4535 if ((cop & ~0x1) == 0xa)
4536 return MCDisassembler::Fail;
4537
4538 if (Rt == Rt2)
4539 S = MCDisassembler::SoftFail;
4540
4541 Inst.addOperand(MCOperand::CreateImm(cop));
4542 Inst.addOperand(MCOperand::CreateImm(opc1));
4543 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4544 return MCDisassembler::Fail;
4545 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4546 return MCDisassembler::Fail;
4547 Inst.addOperand(MCOperand::CreateImm(CRm));
4548
4549 return S;
4550}
4551