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gerrit-public.fairphone.software / platform / external / llvm / 445ba85b8d7bc8fb4689ca22131cadc80a034705 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: f00142de50dc2dbffe13ac2a8e514eae73ff32a1 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]13#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]14#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]15#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]16#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]17#include "llvm/MC/MCInstrDesc.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]20#include "llvm/MC/MCDisassembler.h"
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]22#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]26#include "llvm/Support/LEB128.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]27#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]28#include "llvm/Support/raw_ostream.h"
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]29#include <vector>
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]30
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]31using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]32
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]33typedef MCDisassembler::DecodeStatus DecodeStatus;
34
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]35namespace {
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]36 // Handles the condition code status of instructions in IT blocks
37 class ITStatus
38 {
39 public:
40 // Returns the condition code for instruction in IT block
41 unsigned getITCC() {
42 unsigned CC = ARMCC::AL;
43 if (instrInITBlock())
44 CC = ITStates.back();
45 return CC;
46 }
47
48 // Advances the IT block state to the next T or E
49 void advanceITState() {
50 ITStates.pop_back();
51 }
52
53 // Returns true if the current instruction is in an IT block
54 bool instrInITBlock() {
55 return !ITStates.empty();
56 }
57
58 // Returns true if current instruction is the last instruction in an IT block
59 bool instrLastInITBlock() {
60 return ITStates.size() == 1;
61 }
62
63 // Called when decoding an IT instruction. Sets the IT state for the following
64 // instructions that for the IT block. Firstcond and Mask correspond to the
65 // fields in the IT instruction encoding.
66 void setITState(char Firstcond, char Mask) {
67 // (3 - the number of trailing zeros) is the number of then / else.
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]68 unsigned CondBit0 = Firstcond & 1;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]69 unsigned NumTZ = CountTrailingZeros_32(Mask);
70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
71 assert(NumTZ <= 3 && "Invalid IT mask!");
72 // push condition codes onto the stack the correct order for the pops
73 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
74 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 if (T)
76 ITStates.push_back(CCBits);
77 else
78 ITStates.push_back(CCBits ^ 1);
79 }
80 ITStates.push_back(CCBits);
81 }
82
83 private:
84 std::vector<unsigned char> ITStates;
85 };
86}
87
88namespace {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]89/// ARMDisassembler - ARM disassembler for all ARM platforms.
90class ARMDisassembler : public MCDisassembler {
91public:
92 /// Constructor - Initializes the disassembler.
93 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]94 ARMDisassembler(const MCSubtargetInfo &STI) :
95 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]96 }
97
98 ~ARMDisassembler() {
99 }
100
101 /// getInstruction - See MCDisassembler.
102 DecodeStatus getInstruction(MCInst &instr,
103 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]104 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]105 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]106 raw_ostream &vStream,
107 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]108
109 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]110 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]111private:
112};
113
114/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
115class ThumbDisassembler : public MCDisassembler {
116public:
117 /// Constructor - Initializes the disassembler.
118 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]119 ThumbDisassembler(const MCSubtargetInfo &STI) :
120 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]121 }
122
123 ~ThumbDisassembler() {
124 }
125
126 /// getInstruction - See MCDisassembler.
127 DecodeStatus getInstruction(MCInst &instr,
128 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]129 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]130 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]131 raw_ostream &vStream,
132 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]133
134 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]135 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]136private:
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]137 mutable ITStatus ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]138 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]139 void UpdateThumbVFPPredicate(MCInst&) const;
140};
141}
142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]144 switch (In) {
145 case MCDisassembler::Success:
146 // Out stays the same.
147 return true;
148 case MCDisassembler::SoftFail:
149 Out = In;
150 return true;
151 case MCDisassembler::Fail:
152 Out = In;
153 return false;
154 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]155 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]156}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]157
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]158
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]159// Forward declare these because the autogenerated code will reference them.
160// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]161static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]163static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]164 unsigned RegNo, uint64_t Address,
165 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]166static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]167 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]168static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]170static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]172static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]174static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]176static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]178static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]179 unsigned RegNo,
180 uint64_t Address,
181 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]182static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]184static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]186static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]187 unsigned RegNo, uint64_t Address,
188 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]189
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]190static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]192static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]194static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]198static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]200static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]202
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]203static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]205static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]207static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]208 unsigned Insn,
209 uint64_t Address,
210 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]211static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]213static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]215static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]217static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
219
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]220static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]221 unsigned Insn,
222 uint64_t Adddress,
223 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]224static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]226static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]228static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]230static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]232static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]234static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]236static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]238static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]240static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]242static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]244static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]246static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]248static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]250static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]252static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]254static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]256static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]258static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]260static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]262static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]264static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]266static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]268static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]270static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]272static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]274static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]276static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]278static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]280static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]282static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]284static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]286static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]288static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]290static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]292static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]294static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]296static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]298static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]300static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]302static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]303 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]304static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]305 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]306static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]307 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]308static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]309 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]310static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]311 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]312static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]313 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]314static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]315 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]316static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]317 uint64_t Address, const void *Decoder);
318
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]319
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]320static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]321 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]322static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]323 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]324static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]325 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]326static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]328static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]330static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]332static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]333 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]334static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]335 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]336static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]338static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]340static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]341 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]342static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]343 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]344static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]345 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]346static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]348static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]349 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]350static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]351 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]352static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]353 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]354static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]356static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]358static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]359 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]360static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]361 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]362static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]363 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]364static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]366static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]368static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]370static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]371 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]372static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]373 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]374static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]375 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]376static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]377 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]378static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]379 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]380static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]381 uint64_t Address, const void *Decoder);
382
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]383static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]384 uint64_t Address, const void *Decoder);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]385static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
386 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]387#include "ARMGenDisassemblerTables.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]388#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]389
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]390static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
391 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]392}
393
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]394static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
395 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]396}
397
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]398const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]399 return instInfoARM;
400}
401
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]402const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]403 return instInfoARM;
404}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]405
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]406DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]407 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]408 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]409 raw_ostream &os,
410 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]411 CommentStream = &cs;
412
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]413 uint8_t bytes[4];
414
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]415 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
416 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
417
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]418 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]419 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
420 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]421 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]422 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]423
424 // Encoded as a small-endian 32-bit word in the stream.
425 uint32_t insn = (bytes[3] << 24) |
426 (bytes[2] << 16) |
427 (bytes[1] << 8) |
428 (bytes[0] << 0);
429
430 // Calling the auto-generated decoder function.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]431 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
432 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]433 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]434 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]435 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]436 }
437
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]438 // VFP and NEON instructions, similarly, are shared between ARM
439 // and Thumb modes.
440 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]441 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]442 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]443 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]444 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]445 }
446
447 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]448 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
449 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]450 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]451 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]452 // Add a fake predicate operand, because we share these instruction
453 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]454 if (!DecodePredicateOperand(MI, 0xE, Address, this))
455 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]456 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]457 }
458
459 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]460 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
461 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]462 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]463 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]464 // Add a fake predicate operand, because we share these instruction
465 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]466 if (!DecodePredicateOperand(MI, 0xE, Address, this))
467 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]468 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]469 }
470
471 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]472 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
473 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]474 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]475 Size = 4;
476 // Add a fake predicate operand, because we share these instruction
477 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]478 if (!DecodePredicateOperand(MI, 0xE, Address, this))
479 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]480 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]481 }
482
483 MI.clear();
484
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]485 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]486 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]487}
488
489namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]490extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]491}
492
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]493/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
494/// immediate Value in the MCInst. The immediate Value has had any PC
495/// adjustment made by the caller. If the instruction is a branch instruction
496/// then isBranch is true, else false. If the getOpInfo() function was set as
497/// part of the setupForSymbolicDisassembly() call then that function is called
498/// to get any symbolic information at the Address for this instruction. If
499/// that returns non-zero then the symbolic information it returns is used to
500/// create an MCExpr and that is added as an operand to the MCInst. If
501/// getOpInfo() returns zero and isBranch is true then a symbol look up for
502/// Value is done and if a symbol is found an MCExpr is created with that, else
503/// an MCExpr with Value is created. This function returns true if it adds an
504/// operand to the MCInst and false otherwise.
505static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
506 bool isBranch, uint64_t InstSize,
507 MCInst &MI, const void *Decoder) {
508 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
509 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]510 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]511 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]512 SymbolicOp.Value = Value;
513 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]514
515 if (!getOpInfo ||
516 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
517 // Clear SymbolicOp.Value from above and also all other fields.
518 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
519 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
520 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]521 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]522 uint64_t ReferenceType;
523 if (isBranch)
524 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
525 else
526 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
527 const char *ReferenceName;
Kevin Enderby88d12662012-10-18 21:49:18 +0000[diff] [blame]528 uint64_t SymbolValue = 0x00000000ffffffffULL & Value;
529 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType,
530 Address, &ReferenceName);
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]531 if (Name) {
532 SymbolicOp.AddSymbol.Name = Name;
533 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]534 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]535 // For branches always create an MCExpr so it gets printed as hex address.
536 else if (isBranch) {
537 SymbolicOp.Value = Value;
538 }
539 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
540 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
541 if (!Name && !isBranch)
542 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]543 }
544
545 MCContext *Ctx = Dis->getMCContext();
546 const MCExpr *Add = NULL;
547 if (SymbolicOp.AddSymbol.Present) {
548 if (SymbolicOp.AddSymbol.Name) {
549 StringRef Name(SymbolicOp.AddSymbol.Name);
550 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
551 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
552 } else {
553 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
554 }
555 }
556
557 const MCExpr *Sub = NULL;
558 if (SymbolicOp.SubtractSymbol.Present) {
559 if (SymbolicOp.SubtractSymbol.Name) {
560 StringRef Name(SymbolicOp.SubtractSymbol.Name);
561 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
562 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
563 } else {
564 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
565 }
566 }
567
568 const MCExpr *Off = NULL;
569 if (SymbolicOp.Value != 0)
570 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
571
572 const MCExpr *Expr;
573 if (Sub) {
574 const MCExpr *LHS;
575 if (Add)
576 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
577 else
578 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
579 if (Off != 0)
580 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
581 else
582 Expr = LHS;
583 } else if (Add) {
584 if (Off != 0)
585 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
586 else
587 Expr = Add;
588 } else {
589 if (Off != 0)
590 Expr = Off;
591 else
592 Expr = MCConstantExpr::Create(0, *Ctx);
593 }
594
595 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
596 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
597 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
598 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
599 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
600 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]601 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]602 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]603
604 return true;
605}
606
607/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
608/// referenced by a load instruction with the base register that is the Pc.
609/// These can often be values in a literal pool near the Address of the
610/// instruction. The Address of the instruction and its immediate Value are
611/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledruc8e41c52012-07-23 08:51:15 +0000[diff] [blame]612/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]613/// the referenced address is that of a symbol. Or it will return a pointer to
614/// a literal 'C' string if the referenced address of the literal pool's entry
615/// is an address into a section with 'C' string literals.
616static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]617 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]618 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
619 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
620 if (SymbolLookUp) {
621 void *DisInfo = Dis->getDisInfoBlock();
622 uint64_t ReferenceType;
623 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
624 const char *ReferenceName;
625 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
626 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
627 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
628 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
629 }
630}
631
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]632// Thumb1 instructions don't have explicit S bits. Rather, they
633// implicitly set CPSR. Since it's not represented in the encoding, the
634// auto-generated decoder won't inject the CPSR operand. We need to fix
635// that as a post-pass.
636static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
637 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]638 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]639 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]640 for (unsigned i = 0; i < NumOps; ++i, ++I) {
641 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]642 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]643 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]644 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
645 return;
646 }
647 }
648
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]649 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]650}
651
652// Most Thumb instructions don't have explicit predicates in the
653// encoding, but rather get their predicates from IT context. We need
654// to fix up the predicate operands using this context information as a
655// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]656MCDisassembler::DecodeStatus
657ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]658 MCDisassembler::DecodeStatus S = Success;
659
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]660 // A few instructions actually have predicates encoded in them. Don't
661 // try to overwrite it if we're seeing one of those.
662 switch (MI.getOpcode()) {
663 case ARM::tBcc:
664 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]665 case ARM::tCBZ:
666 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]667 case ARM::tCPS:
668 case ARM::t2CPS3p:
669 case ARM::t2CPS2p:
670 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]671 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]672 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]673 // Some instructions (mostly conditional branches) are not
674 // allowed in IT blocks.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]675 if (ITBlock.instrInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]676 S = SoftFail;
677 else
678 return Success;
679 break;
680 case ARM::tB:
681 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]682 case ARM::t2TBB:
683 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]684 // Some instructions (mostly unconditional branches) can
685 // only appears at the end of, or outside of, an IT.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]686 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]687 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]688 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]689 default:
690 break;
691 }
692
693 // If we're in an IT block, base the predicate on that. Otherwise,
694 // assume a predicate of AL.
695 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]696 CC = ITBlock.getITCC();
697 if (CC == 0xF)
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]698 CC = ARMCC::AL;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]699 if (ITBlock.instrInITBlock())
700 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]701
702 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]703 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]705 for (unsigned i = 0; i < NumOps; ++i, ++I) {
706 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]707 if (OpInfo[i].isPredicate()) {
708 I = MI.insert(I, MCOperand::CreateImm(CC));
709 ++I;
710 if (CC == ARMCC::AL)
711 MI.insert(I, MCOperand::CreateReg(0));
712 else
713 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]714 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]715 }
716 }
717
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]718 I = MI.insert(I, MCOperand::CreateImm(CC));
719 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]720 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]721 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]722 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]723 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]724
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]725 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]726}
727
728// Thumb VFP instructions are a special case. Because we share their
729// encodings between ARM and Thumb modes, and they are predicable in ARM
730// mode, the auto-generated decoder will give them an (incorrect)
731// predicate operand. We need to rewrite these operands based on the IT
732// context as a post-pass.
733void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
734 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]735 CC = ITBlock.getITCC();
736 if (ITBlock.instrInITBlock())
737 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]738
739 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
740 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]741 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
742 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]743 if (OpInfo[i].isPredicate() ) {
744 I->setImm(CC);
745 ++I;
746 if (CC == ARMCC::AL)
747 I->setReg(0);
748 else
749 I->setReg(ARM::CPSR);
750 return;
751 }
752 }
753}
754
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]755DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]756 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]757 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]758 raw_ostream &os,
759 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]760 CommentStream = &cs;
761
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]762 uint8_t bytes[4];
763
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]764 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
765 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
766
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]767 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]768 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
769 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]770 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]771 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]772
773 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]774 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
775 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]776 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]778 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]779 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]780 }
781
782 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]783 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
784 Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]785 if (result) {
786 Size = 2;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]787 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]788 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]789 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]790 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 }
792
793 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]794 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
795 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]796 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]797 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]798
799 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
800 // the Thumb predicate.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]801 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]802 result = MCDisassembler::SoftFail;
803
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]804 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]805
806 // If we find an IT instruction, we need to parse its condition
807 // code and mask operands so that we can apply them correctly
808 // to the subsequent instructions.
809 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]810
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]811 unsigned Firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]812 unsigned Mask = MI.getOperand(1).getImm();
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]813 ITBlock.setITState(Firstcond, Mask);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]814 }
815
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]816 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]817 }
818
819 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]820 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
821 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]822 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]823 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]824
825 uint32_t insn32 = (bytes[3] << 8) |
826 (bytes[2] << 0) |
827 (bytes[1] << 24) |
828 (bytes[0] << 16);
829 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]830 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
831 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]832 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833 Size = 4;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]834 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]835 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]837 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]838 }
839
840 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]841 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
842 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]843 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]844 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]845 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]846 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]847 }
848
849 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]850 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]851 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]852 Size = 4;
853 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]854 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]855 }
856
857 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]858 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
859 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]860 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]861 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]862 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]863 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]864 }
865
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]866 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]867 MI.clear();
868 uint32_t NEONLdStInsn = insn32;
869 NEONLdStInsn &= 0xF0FFFFFF;
870 NEONLdStInsn |= 0x04000000;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]871 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
872 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]873 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]874 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]875 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]876 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]877 }
878 }
879
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]880 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]881 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]882 uint32_t NEONDataInsn = insn32;
883 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
884 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
885 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]886 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
887 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]888 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]889 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]890 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]891 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]892 }
893 }
894
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]895 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]896 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]897}
898
899
900extern "C" void LLVMInitializeARMDisassembler() {
901 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
902 createARMDisassembler);
903 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
904 createThumbDisassembler);
905}
906
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]907static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
909 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
910 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
911 ARM::R12, ARM::SP, ARM::LR, ARM::PC
912};
913
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]914static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]915 uint64_t Address, const void *Decoder) {
916 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]917 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]918
919 unsigned Register = GPRDecoderTable[RegNo];
920 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]921 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]922}
923
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]924static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]925DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]926 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]927 DecodeStatus S = MCDisassembler::Success;
928
929 if (RegNo == 15)
930 S = MCDisassembler::SoftFail;
931
932 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
933
934 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]935}
936
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]937static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]938 uint64_t Address, const void *Decoder) {
939 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]940 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]941 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
942}
943
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]944static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]945 uint64_t Address, const void *Decoder) {
946 unsigned Register = 0;
947 switch (RegNo) {
948 case 0:
949 Register = ARM::R0;
950 break;
951 case 1:
952 Register = ARM::R1;
953 break;
954 case 2:
955 Register = ARM::R2;
956 break;
957 case 3:
958 Register = ARM::R3;
959 break;
960 case 9:
961 Register = ARM::R9;
962 break;
963 case 12:
964 Register = ARM::R12;
965 break;
966 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]967 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968 }
969
970 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]971 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]972}
973
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]974static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]975 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]976 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]977 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
978}
979
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]980static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]981 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
982 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
983 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
984 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
985 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
986 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
987 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
988 ARM::S28, ARM::S29, ARM::S30, ARM::S31
989};
990
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]991static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]992 uint64_t Address, const void *Decoder) {
993 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]994 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995
996 unsigned Register = SPRDecoderTable[RegNo];
997 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]998 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999}
1000
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1001static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1010};
1011
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1012static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1013 uint64_t Address, const void *Decoder) {
1014 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1015 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1016
1017 unsigned Register = DPRDecoderTable[RegNo];
1018 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1019 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1020}
1021
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1022static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1023 uint64_t Address, const void *Decoder) {
1024 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1025 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1027}
1028
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1029static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1030DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1031 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1032 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1033 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1035}
1036
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1037static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1042};
1043
1044
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1045static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1046 uint64_t Address, const void *Decoder) {
1047 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1048 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1049 RegNo >>= 1;
1050
1051 unsigned Register = QPRDecoderTable[RegNo];
1052 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1053 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1054}
1055
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1056static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1062 ARM::Q15
1063};
1064
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1065static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1066 uint64_t Address, const void *Decoder) {
1067 if (RegNo > 30)
1068 return MCDisassembler::Fail;
1069
1070 unsigned Register = DPairDecoderTable[RegNo];
1071 Inst.addOperand(MCOperand::CreateReg(Register));
1072 return MCDisassembler::Success;
1073}
1074
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1075static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1083 ARM::D28_D30, ARM::D29_D31
1084};
1085
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1086static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1087 unsigned RegNo,
1088 uint64_t Address,
1089 const void *Decoder) {
1090 if (RegNo > 29)
1091 return MCDisassembler::Fail;
1092
1093 unsigned Register = DPairSpacedDecoderTable[RegNo];
1094 Inst.addOperand(MCOperand::CreateReg(Register));
1095 return MCDisassembler::Success;
1096}
1097
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1098static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1099 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1100 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1101 // AL predicate is not allowed on Thumb1 branches.
1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1103 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1104 Inst.addOperand(MCOperand::CreateImm(Val));
1105 if (Val == ARMCC::AL) {
1106 Inst.addOperand(MCOperand::CreateReg(0));
1107 } else
1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1109 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1110}
1111
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1112static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1113 uint64_t Address, const void *Decoder) {
1114 if (Val)
1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1116 else
1117 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1118 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1119}
1120
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1121static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1122 uint64_t Address, const void *Decoder) {
1123 uint32_t imm = Val & 0xFF;
1124 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1126 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1127 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1128}
1129
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1130static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1131 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1132 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1133
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1134 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1135 unsigned type = fieldFromInstruction(Val, 5, 2);
1136 unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1137
1138 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1140 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1141
1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1143 switch (type) {
1144 case 0:
1145 Shift = ARM_AM::lsl;
1146 break;
1147 case 1:
1148 Shift = ARM_AM::lsr;
1149 break;
1150 case 2:
1151 Shift = ARM_AM::asr;
1152 break;
1153 case 3:
1154 Shift = ARM_AM::ror;
1155 break;
1156 }
1157
1158 if (Shift == ARM_AM::ror && imm == 0)
1159 Shift = ARM_AM::rrx;
1160
1161 unsigned Op = Shift | (imm << 3);
1162 Inst.addOperand(MCOperand::CreateImm(Op));
1163
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1164 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1165}
1166
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1167static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1168 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1169 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1170
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1171 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1172 unsigned type = fieldFromInstruction(Val, 5, 2);
1173 unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1174
1175 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1177 return MCDisassembler::Fail;
1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1179 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1180
1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1182 switch (type) {
1183 case 0:
1184 Shift = ARM_AM::lsl;
1185 break;
1186 case 1:
1187 Shift = ARM_AM::lsr;
1188 break;
1189 case 2:
1190 Shift = ARM_AM::asr;
1191 break;
1192 case 3:
1193 Shift = ARM_AM::ror;
1194 break;
1195 }
1196
1197 Inst.addOperand(MCOperand::CreateImm(Shift));
1198
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1199 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1200}
1201
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1202static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1203 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1204 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1205
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1206 bool writebackLoad = false;
1207 unsigned writebackReg = 0;
1208 switch (Inst.getOpcode()) {
1209 default:
1210 break;
1211 case ARM::LDMIA_UPD:
1212 case ARM::LDMDB_UPD:
1213 case ARM::LDMIB_UPD:
1214 case ARM::LDMDA_UPD:
1215 case ARM::t2LDMIA_UPD:
1216 case ARM::t2LDMDB_UPD:
1217 writebackLoad = true;
1218 writebackReg = Inst.getOperand(0).getReg();
1219 break;
1220 }
1221
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1222 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1223 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1225 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1226 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1227 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1228 // Writeback not allowed if Rn is in the target list.
1229 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1230 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1231 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1232 }
1233
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1234 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235}
1236
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1237static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1239 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1240
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1241 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1242 unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1243
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1244 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1245 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1246 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1247 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1248 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1249 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1250
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1251 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1252}
1253
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1254static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1256 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1257
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1258 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1259 unsigned regs = fieldFromInstruction(Val, 0, 8);
Silviu Barangab422d0b2012-05-03 16:38:40 +0000[diff] [blame]1260
1261 regs = regs >> 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1262
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1263 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1264 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1265 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1266 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1267 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1268 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1269
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1270 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1271}
1272
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1273static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1274 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1275 // This operand encodes a mask of contiguous zeros between a specified MSB
1276 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1277 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1278 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1279 // create the final mask.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1280 unsigned msb = fieldFromInstruction(Val, 5, 5);
1281 unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1282
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1283 DecodeStatus S = MCDisassembler::Success;
1284 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1285
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1286 uint32_t msb_mask = 0xFFFFFFFF;
1287 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1288 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1289
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1290 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1291 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1292}
1293
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1294static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1295 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1296 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1297
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1298 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1299 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1300 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1301 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1302 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1303 unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1304
1305 switch (Inst.getOpcode()) {
1306 case ARM::LDC_OFFSET:
1307 case ARM::LDC_PRE:
1308 case ARM::LDC_POST:
1309 case ARM::LDC_OPTION:
1310 case ARM::LDCL_OFFSET:
1311 case ARM::LDCL_PRE:
1312 case ARM::LDCL_POST:
1313 case ARM::LDCL_OPTION:
1314 case ARM::STC_OFFSET:
1315 case ARM::STC_PRE:
1316 case ARM::STC_POST:
1317 case ARM::STC_OPTION:
1318 case ARM::STCL_OFFSET:
1319 case ARM::STCL_PRE:
1320 case ARM::STCL_POST:
1321 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1322 case ARM::t2LDC_OFFSET:
1323 case ARM::t2LDC_PRE:
1324 case ARM::t2LDC_POST:
1325 case ARM::t2LDC_OPTION:
1326 case ARM::t2LDCL_OFFSET:
1327 case ARM::t2LDCL_PRE:
1328 case ARM::t2LDCL_POST:
1329 case ARM::t2LDCL_OPTION:
1330 case ARM::t2STC_OFFSET:
1331 case ARM::t2STC_PRE:
1332 case ARM::t2STC_POST:
1333 case ARM::t2STC_OPTION:
1334 case ARM::t2STCL_OFFSET:
1335 case ARM::t2STCL_PRE:
1336 case ARM::t2STCL_POST:
1337 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1338 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1339 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1340 break;
1341 default:
1342 break;
1343 }
1344
1345 Inst.addOperand(MCOperand::CreateImm(coproc));
1346 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1348 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1349
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1350 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1351 case ARM::t2LDC2_OFFSET:
1352 case ARM::t2LDC2L_OFFSET:
1353 case ARM::t2LDC2_PRE:
1354 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1355 case ARM::t2STC2_OFFSET:
1356 case ARM::t2STC2L_OFFSET:
1357 case ARM::t2STC2_PRE:
1358 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1359 case ARM::LDC2_OFFSET:
1360 case ARM::LDC2L_OFFSET:
1361 case ARM::LDC2_PRE:
1362 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1363 case ARM::STC2_OFFSET:
1364 case ARM::STC2L_OFFSET:
1365 case ARM::STC2_PRE:
1366 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1367 case ARM::t2LDC_OFFSET:
1368 case ARM::t2LDCL_OFFSET:
1369 case ARM::t2LDC_PRE:
1370 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1371 case ARM::t2STC_OFFSET:
1372 case ARM::t2STCL_OFFSET:
1373 case ARM::t2STC_PRE:
1374 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1375 case ARM::LDC_OFFSET:
1376 case ARM::LDCL_OFFSET:
1377 case ARM::LDC_PRE:
1378 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1379 case ARM::STC_OFFSET:
1380 case ARM::STCL_OFFSET:
1381 case ARM::STC_PRE:
1382 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1383 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1384 Inst.addOperand(MCOperand::CreateImm(imm));
1385 break;
1386 case ARM::t2LDC2_POST:
1387 case ARM::t2LDC2L_POST:
1388 case ARM::t2STC2_POST:
1389 case ARM::t2STC2L_POST:
1390 case ARM::LDC2_POST:
1391 case ARM::LDC2L_POST:
1392 case ARM::STC2_POST:
1393 case ARM::STC2L_POST:
1394 case ARM::t2LDC_POST:
1395 case ARM::t2LDCL_POST:
1396 case ARM::t2STC_POST:
1397 case ARM::t2STCL_POST:
1398 case ARM::LDC_POST:
1399 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1400 case ARM::STC_POST:
1401 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1402 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1403 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1404 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1405 // The 'option' variant doesn't encode 'U' in the immediate since
1406 // the immediate is unsigned [0,255].
1407 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1408 break;
1409 }
1410
1411 switch (Inst.getOpcode()) {
1412 case ARM::LDC_OFFSET:
1413 case ARM::LDC_PRE:
1414 case ARM::LDC_POST:
1415 case ARM::LDC_OPTION:
1416 case ARM::LDCL_OFFSET:
1417 case ARM::LDCL_PRE:
1418 case ARM::LDCL_POST:
1419 case ARM::LDCL_OPTION:
1420 case ARM::STC_OFFSET:
1421 case ARM::STC_PRE:
1422 case ARM::STC_POST:
1423 case ARM::STC_OPTION:
1424 case ARM::STCL_OFFSET:
1425 case ARM::STCL_PRE:
1426 case ARM::STCL_POST:
1427 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1428 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1429 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1430 break;
1431 default:
1432 break;
1433 }
1434
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1435 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1436}
1437
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1438static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1439DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1440 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1441 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1442
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1443 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1444 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1445 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1446 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1447 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1448 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1449 unsigned P = fieldFromInstruction(Insn, 24, 1);
1450 unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1451
1452 // On stores, the writeback operand precedes Rt.
1453 switch (Inst.getOpcode()) {
1454 case ARM::STR_POST_IMM:
1455 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1456 case ARM::STRB_POST_IMM:
1457 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1458 case ARM::STRT_POST_REG:
1459 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1460 case ARM::STRBT_POST_REG:
1461 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1463 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1464 break;
1465 default:
1466 break;
1467 }
1468
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1470 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1471
1472 // On loads, the writeback operand comes after Rt.
1473 switch (Inst.getOpcode()) {
1474 case ARM::LDR_POST_IMM:
1475 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1476 case ARM::LDRB_POST_IMM:
1477 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1478 case ARM::LDRBT_POST_REG:
1479 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1480 case ARM::LDRT_POST_REG:
1481 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1483 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1484 break;
1485 default:
1486 break;
1487 }
1488
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1490 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1491
1492 ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1493 if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1494 Op = ARM_AM::sub;
1495
1496 bool writeback = (P == 0) || (W == 1);
1497 unsigned idx_mode = 0;
1498 if (P && writeback)
1499 idx_mode = ARMII::IndexModePre;
1500 else if (!P && writeback)
1501 idx_mode = ARMII::IndexModePost;
1502
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1503 if (writeback && (Rn == 15 || Rn == Rt))
1504 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1505
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1506 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1508 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1509 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1510 switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1511 case 0:
1512 Opc = ARM_AM::lsl;
1513 break;
1514 case 1:
1515 Opc = ARM_AM::lsr;
1516 break;
1517 case 2:
1518 Opc = ARM_AM::asr;
1519 break;
1520 case 3:
1521 Opc = ARM_AM::ror;
1522 break;
1523 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1524 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1525 }
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1526 unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover93c7c442012-09-22 11:18:12 +0000[diff] [blame]1527 if (Opc == ARM_AM::ror && amt == 0)
1528 Opc = ARM_AM::rrx;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1529 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1530
1531 Inst.addOperand(MCOperand::CreateImm(imm));
1532 } else {
1533 Inst.addOperand(MCOperand::CreateReg(0));
1534 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1535 Inst.addOperand(MCOperand::CreateImm(tmp));
1536 }
1537
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1538 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1539 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1540
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1541 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1542}
1543
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1544static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1545 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1546 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1547
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1548 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1549 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1550 unsigned type = fieldFromInstruction(Val, 5, 2);
1551 unsigned imm = fieldFromInstruction(Val, 7, 5);
1552 unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1553
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1554 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1555 switch (type) {
1556 case 0:
1557 ShOp = ARM_AM::lsl;
1558 break;
1559 case 1:
1560 ShOp = ARM_AM::lsr;
1561 break;
1562 case 2:
1563 ShOp = ARM_AM::asr;
1564 break;
1565 case 3:
1566 ShOp = ARM_AM::ror;
1567 break;
1568 }
1569
Tim Northover93c7c442012-09-22 11:18:12 +0000[diff] [blame]1570 if (ShOp == ARM_AM::ror && imm == 0)
1571 ShOp = ARM_AM::rrx;
1572
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1574 return MCDisassembler::Fail;
1575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1576 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1577 unsigned shift;
1578 if (U)
1579 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1580 else
1581 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1582 Inst.addOperand(MCOperand::CreateImm(shift));
1583
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1584 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1585}
1586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1587static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1588DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1589 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1590 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1591
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1592 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1593 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1594 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1595 unsigned type = fieldFromInstruction(Insn, 22, 1);
1596 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1597 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1598 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1599 unsigned W = fieldFromInstruction(Insn, 21, 1);
1600 unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1601 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1602
1603 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1604
1605 // For {LD,ST}RD, Rt must be even, else undefined.
1606 switch (Inst.getOpcode()) {
1607 case ARM::STRD:
1608 case ARM::STRD_PRE:
1609 case ARM::STRD_POST:
1610 case ARM::LDRD:
1611 case ARM::LDRD_PRE:
1612 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1613 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1614 break;
1615 default:
1616 break;
1617 }
1618 switch (Inst.getOpcode()) {
1619 case ARM::STRD:
1620 case ARM::STRD_PRE:
1621 case ARM::STRD_POST:
1622 if (P == 0 && W == 1)
1623 S = MCDisassembler::SoftFail;
1624
1625 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1626 S = MCDisassembler::SoftFail;
1627 if (type && Rm == 15)
1628 S = MCDisassembler::SoftFail;
1629 if (Rt2 == 15)
1630 S = MCDisassembler::SoftFail;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1631 if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1632 S = MCDisassembler::SoftFail;
1633 break;
1634 case ARM::STRH:
1635 case ARM::STRH_PRE:
1636 case ARM::STRH_POST:
1637 if (Rt == 15)
1638 S = MCDisassembler::SoftFail;
1639 if (writeback && (Rn == 15 || Rn == Rt))
1640 S = MCDisassembler::SoftFail;
1641 if (!type && Rm == 15)
1642 S = MCDisassembler::SoftFail;
1643 break;
1644 case ARM::LDRD:
1645 case ARM::LDRD_PRE:
1646 case ARM::LDRD_POST:
1647 if (type && Rn == 15){
1648 if (Rt2 == 15)
1649 S = MCDisassembler::SoftFail;
1650 break;
1651 }
1652 if (P == 0 && W == 1)
1653 S = MCDisassembler::SoftFail;
1654 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1655 S = MCDisassembler::SoftFail;
1656 if (!type && writeback && Rn == 15)
1657 S = MCDisassembler::SoftFail;
1658 if (writeback && (Rn == Rt || Rn == Rt2))
1659 S = MCDisassembler::SoftFail;
1660 break;
1661 case ARM::LDRH:
1662 case ARM::LDRH_PRE:
1663 case ARM::LDRH_POST:
1664 if (type && Rn == 15){
1665 if (Rt == 15)
1666 S = MCDisassembler::SoftFail;
1667 break;
1668 }
1669 if (Rt == 15)
1670 S = MCDisassembler::SoftFail;
1671 if (!type && Rm == 15)
1672 S = MCDisassembler::SoftFail;
1673 if (!type && writeback && (Rn == 15 || Rn == Rt))
1674 S = MCDisassembler::SoftFail;
1675 break;
1676 case ARM::LDRSH:
1677 case ARM::LDRSH_PRE:
1678 case ARM::LDRSH_POST:
1679 case ARM::LDRSB:
1680 case ARM::LDRSB_PRE:
1681 case ARM::LDRSB_POST:
1682 if (type && Rn == 15){
1683 if (Rt == 15)
1684 S = MCDisassembler::SoftFail;
1685 break;
1686 }
1687 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1688 S = MCDisassembler::SoftFail;
1689 if (!type && (Rt == 15 || Rm == 15))
1690 S = MCDisassembler::SoftFail;
1691 if (!type && writeback && (Rn == 15 || Rn == Rt))
1692 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1693 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1694 default:
1695 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1696 }
1697
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1698 if (writeback) { // Writeback
1699 if (P)
1700 U |= ARMII::IndexModePre << 9;
1701 else
1702 U |= ARMII::IndexModePost << 9;
1703
1704 // On stores, the writeback operand precedes Rt.
1705 switch (Inst.getOpcode()) {
1706 case ARM::STRD:
1707 case ARM::STRD_PRE:
1708 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1709 case ARM::STRH:
1710 case ARM::STRH_PRE:
1711 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1713 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1714 break;
1715 default:
1716 break;
1717 }
1718 }
1719
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1721 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1722 switch (Inst.getOpcode()) {
1723 case ARM::STRD:
1724 case ARM::STRD_PRE:
1725 case ARM::STRD_POST:
1726 case ARM::LDRD:
1727 case ARM::LDRD_PRE:
1728 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1730 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1731 break;
1732 default:
1733 break;
1734 }
1735
1736 if (writeback) {
1737 // On loads, the writeback operand comes after Rt.
1738 switch (Inst.getOpcode()) {
1739 case ARM::LDRD:
1740 case ARM::LDRD_PRE:
1741 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1742 case ARM::LDRH:
1743 case ARM::LDRH_PRE:
1744 case ARM::LDRH_POST:
1745 case ARM::LDRSH:
1746 case ARM::LDRSH_PRE:
1747 case ARM::LDRSH_POST:
1748 case ARM::LDRSB:
1749 case ARM::LDRSB_PRE:
1750 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1751 case ARM::LDRHTr:
1752 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1754 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1755 break;
1756 default:
1757 break;
1758 }
1759 }
1760
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1762 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1763
1764 if (type) {
1765 Inst.addOperand(MCOperand::CreateReg(0));
1766 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1767 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1769 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1770 Inst.addOperand(MCOperand::CreateImm(U));
1771 }
1772
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1773 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1774 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1775
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1776 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1777}
1778
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1779static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1780 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1781 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1782
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1783 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1784 unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1785
1786 switch (mode) {
1787 case 0:
1788 mode = ARM_AM::da;
1789 break;
1790 case 1:
1791 mode = ARM_AM::ia;
1792 break;
1793 case 2:
1794 mode = ARM_AM::db;
1795 break;
1796 case 3:
1797 mode = ARM_AM::ib;
1798 break;
1799 }
1800
1801 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1803 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1804
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1805 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1806}
1807
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1808static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1809 unsigned Insn,
1810 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1811 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1812
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1813 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1814 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1815 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1816
1817 if (pred == 0xF) {
1818 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1819 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1820 Inst.setOpcode(ARM::RFEDA);
1821 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1822 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1823 Inst.setOpcode(ARM::RFEDA_UPD);
1824 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1825 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1826 Inst.setOpcode(ARM::RFEDB);
1827 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1828 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1829 Inst.setOpcode(ARM::RFEDB_UPD);
1830 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1831 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1832 Inst.setOpcode(ARM::RFEIA);
1833 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1834 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1835 Inst.setOpcode(ARM::RFEIA_UPD);
1836 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1837 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1838 Inst.setOpcode(ARM::RFEIB);
1839 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1840 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1841 Inst.setOpcode(ARM::RFEIB_UPD);
1842 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1843 case ARM::STMDA:
1844 Inst.setOpcode(ARM::SRSDA);
1845 break;
1846 case ARM::STMDA_UPD:
1847 Inst.setOpcode(ARM::SRSDA_UPD);
1848 break;
1849 case ARM::STMDB:
1850 Inst.setOpcode(ARM::SRSDB);
1851 break;
1852 case ARM::STMDB_UPD:
1853 Inst.setOpcode(ARM::SRSDB_UPD);
1854 break;
1855 case ARM::STMIA:
1856 Inst.setOpcode(ARM::SRSIA);
1857 break;
1858 case ARM::STMIA_UPD:
1859 Inst.setOpcode(ARM::SRSIA_UPD);
1860 break;
1861 case ARM::STMIB:
1862 Inst.setOpcode(ARM::SRSIB);
1863 break;
1864 case ARM::STMIB_UPD:
1865 Inst.setOpcode(ARM::SRSIB_UPD);
1866 break;
1867 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1868 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1869 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1870
1871 // For stores (which become SRS's, the only operand is the mode.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1872 if (fieldFromInstruction(Insn, 20, 1) == 0) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1873 Inst.addOperand(
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1874 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1875 return S;
1876 }
1877
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1878 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1879 }
1880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1882 return MCDisassembler::Fail;
1883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1884 return MCDisassembler::Fail; // Tied
1885 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1886 return MCDisassembler::Fail;
1887 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1889
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1890 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1891}
1892
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1893static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1894 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1895 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1896 unsigned M = fieldFromInstruction(Insn, 17, 1);
1897 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1898 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1899
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1900 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1901
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1902 // imod == '01' --> UNPREDICTABLE
1903 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1904 // return failure here. The '01' imod value is unprintable, so there's
1905 // nothing useful we could do even if we returned UNPREDICTABLE.
1906
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1907 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1908
1909 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1910 Inst.setOpcode(ARM::CPS3p);
1911 Inst.addOperand(MCOperand::CreateImm(imod));
1912 Inst.addOperand(MCOperand::CreateImm(iflags));
1913 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1914 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1915 Inst.setOpcode(ARM::CPS2p);
1916 Inst.addOperand(MCOperand::CreateImm(imod));
1917 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1918 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1919 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1920 Inst.setOpcode(ARM::CPS1p);
1921 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1922 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1923 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1924 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1925 Inst.setOpcode(ARM::CPS1p);
1926 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1927 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1928 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1929
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1930 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1931}
1932
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1933static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1934 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1935 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1936 unsigned M = fieldFromInstruction(Insn, 8, 1);
1937 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1938 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1939
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1940 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1941
1942 // imod == '01' --> UNPREDICTABLE
1943 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1944 // return failure here. The '01' imod value is unprintable, so there's
1945 // nothing useful we could do even if we returned UNPREDICTABLE.
1946
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1947 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1948
1949 if (imod && M) {
1950 Inst.setOpcode(ARM::t2CPS3p);
1951 Inst.addOperand(MCOperand::CreateImm(imod));
1952 Inst.addOperand(MCOperand::CreateImm(iflags));
1953 Inst.addOperand(MCOperand::CreateImm(mode));
1954 } else if (imod && !M) {
1955 Inst.setOpcode(ARM::t2CPS2p);
1956 Inst.addOperand(MCOperand::CreateImm(imod));
1957 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1958 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1959 } else if (!imod && M) {
1960 Inst.setOpcode(ARM::t2CPS1p);
1961 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1962 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1963 } else {
1964 // imod == '00' && M == '0' --> UNPREDICTABLE
1965 Inst.setOpcode(ARM::t2CPS1p);
1966 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1967 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1968 }
1969
1970 return S;
1971}
1972
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1973static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1974 uint64_t Address, const void *Decoder) {
1975 DecodeStatus S = MCDisassembler::Success;
1976
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1977 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1978 unsigned imm = 0;
1979
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1980 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1981 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1982 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1983 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1984
1985 if (Inst.getOpcode() == ARM::t2MOVTi16)
1986 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1987 return MCDisassembler::Fail;
1988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1989 return MCDisassembler::Fail;
1990
1991 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1992 Inst.addOperand(MCOperand::CreateImm(imm));
1993
1994 return S;
1995}
1996
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1997static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1998 uint64_t Address, const void *Decoder) {
1999 DecodeStatus S = MCDisassembler::Success;
2000
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2001 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2002 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2003 unsigned imm = 0;
2004
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2005 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2006 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2007
2008 if (Inst.getOpcode() == ARM::MOVTi16)
2009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2010 return MCDisassembler::Fail;
2011 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2012 return MCDisassembler::Fail;
2013
2014 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2015 Inst.addOperand(MCOperand::CreateImm(imm));
2016
2017 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2018 return MCDisassembler::Fail;
2019
2020 return S;
2021}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]2022
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2023static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2024 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2025 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2026
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2027 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2028 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2029 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2030 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2031 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2032
2033 if (pred == 0xF)
2034 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2035
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2036 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2037 return MCDisassembler::Fail;
2038 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2039 return MCDisassembler::Fail;
2040 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2041 return MCDisassembler::Fail;
2042 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2043 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2044
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2045 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2046 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]2047
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2048 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2049}
2050
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2051static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2052 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2053 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2054
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2055 unsigned add = fieldFromInstruction(Val, 12, 1);
2056 unsigned imm = fieldFromInstruction(Val, 0, 12);
2057 unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2058
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2059 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2060 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2061
2062 if (!add) imm *= -1;
2063 if (imm == 0 && !add) imm = INT32_MIN;
2064 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2065 if (Rn == 15)
2066 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2067
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2068 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2069}
2070
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2071static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2072 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2073 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2074
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2075 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2076 unsigned U = fieldFromInstruction(Val, 8, 1);
2077 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2078
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2080 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2081
2082 if (U)
2083 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2084 else
2085 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2086
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2087 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2088}
2089
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2090static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2091 uint64_t Address, const void *Decoder) {
2092 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2093}
2094
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2095static DecodeStatus
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2096DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2097 uint64_t Address, const void *Decoder) {
Kevin Enderby445ba852012-10-29 23:27:20 +0000[diff] [blame^]2098 DecodeStatus Status = MCDisassembler::Success;
2099
2100 // Note the J1 and J2 values are from the encoded instruction. So here
2101 // change them to I1 and I2 values via as documented:
2102 // I1 = NOT(J1 EOR S);
2103 // I2 = NOT(J2 EOR S);
2104 // and build the imm32 with one trailing zero as documented:
2105 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2106 unsigned S = fieldFromInstruction(Insn, 26, 1);
2107 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2108 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2109 unsigned I1 = !(J1 ^ S);
2110 unsigned I2 = !(J2 ^ S);
2111 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2112 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2113 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2114 int imm32 = SignExtend32<24>(tmp << 1);
2115 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2116 true, 4, Inst, Decoder))
Kevin Enderby445ba852012-10-29 23:27:20 +0000[diff] [blame^]2117 Inst.addOperand(MCOperand::CreateImm(imm32));
2118
2119 return Status;
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2120}
2121
2122static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2123DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2124 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2125 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2126
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2127 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2128 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2129
2130 if (pred == 0xF) {
2131 Inst.setOpcode(ARM::BLXi);
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2132 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2133 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2134 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2135 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2136 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2137 }
2138
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2139 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2140 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2141 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2142 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2143 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2144
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2145 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2146}
2147
2148
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2149static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2150 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2151 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2152
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2153 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2154 unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2155
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2157 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2158 if (!align)
2159 Inst.addOperand(MCOperand::CreateImm(0));
2160 else
2161 Inst.addOperand(MCOperand::CreateImm(4 << align));
2162
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2163 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2164}
2165
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2166static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2167 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2168 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2169
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2170 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2171 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2172 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2173 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2174 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2175 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2176
2177 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2178 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2179 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2180 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2181 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2182 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2183 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2184 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2185 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2186 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2187 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2188 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2189 return MCDisassembler::Fail;
2190 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2191 case ARM::VLD2b16:
2192 case ARM::VLD2b32:
2193 case ARM::VLD2b8:
2194 case ARM::VLD2b16wb_fixed:
2195 case ARM::VLD2b16wb_register:
2196 case ARM::VLD2b32wb_fixed:
2197 case ARM::VLD2b32wb_register:
2198 case ARM::VLD2b8wb_fixed:
2199 case ARM::VLD2b8wb_register:
2200 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2201 return MCDisassembler::Fail;
2202 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2203 default:
2204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2205 return MCDisassembler::Fail;
2206 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2207
2208 // Second output register
2209 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2210 case ARM::VLD3d8:
2211 case ARM::VLD3d16:
2212 case ARM::VLD3d32:
2213 case ARM::VLD3d8_UPD:
2214 case ARM::VLD3d16_UPD:
2215 case ARM::VLD3d32_UPD:
2216 case ARM::VLD4d8:
2217 case ARM::VLD4d16:
2218 case ARM::VLD4d32:
2219 case ARM::VLD4d8_UPD:
2220 case ARM::VLD4d16_UPD:
2221 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2222 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2223 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2224 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2225 case ARM::VLD3q8:
2226 case ARM::VLD3q16:
2227 case ARM::VLD3q32:
2228 case ARM::VLD3q8_UPD:
2229 case ARM::VLD3q16_UPD:
2230 case ARM::VLD3q32_UPD:
2231 case ARM::VLD4q8:
2232 case ARM::VLD4q16:
2233 case ARM::VLD4q32:
2234 case ARM::VLD4q8_UPD:
2235 case ARM::VLD4q16_UPD:
2236 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2237 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2238 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2239 default:
2240 break;
2241 }
2242
2243 // Third output register
2244 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2245 case ARM::VLD3d8:
2246 case ARM::VLD3d16:
2247 case ARM::VLD3d32:
2248 case ARM::VLD3d8_UPD:
2249 case ARM::VLD3d16_UPD:
2250 case ARM::VLD3d32_UPD:
2251 case ARM::VLD4d8:
2252 case ARM::VLD4d16:
2253 case ARM::VLD4d32:
2254 case ARM::VLD4d8_UPD:
2255 case ARM::VLD4d16_UPD:
2256 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2257 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2258 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2259 break;
2260 case ARM::VLD3q8:
2261 case ARM::VLD3q16:
2262 case ARM::VLD3q32:
2263 case ARM::VLD3q8_UPD:
2264 case ARM::VLD3q16_UPD:
2265 case ARM::VLD3q32_UPD:
2266 case ARM::VLD4q8:
2267 case ARM::VLD4q16:
2268 case ARM::VLD4q32:
2269 case ARM::VLD4q8_UPD:
2270 case ARM::VLD4q16_UPD:
2271 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2272 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2273 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2274 break;
2275 default:
2276 break;
2277 }
2278
2279 // Fourth output register
2280 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2281 case ARM::VLD4d8:
2282 case ARM::VLD4d16:
2283 case ARM::VLD4d32:
2284 case ARM::VLD4d8_UPD:
2285 case ARM::VLD4d16_UPD:
2286 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2287 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2288 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2289 break;
2290 case ARM::VLD4q8:
2291 case ARM::VLD4q16:
2292 case ARM::VLD4q32:
2293 case ARM::VLD4q8_UPD:
2294 case ARM::VLD4q16_UPD:
2295 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2296 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2297 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2298 break;
2299 default:
2300 break;
2301 }
2302
2303 // Writeback operand
2304 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2305 case ARM::VLD1d8wb_fixed:
2306 case ARM::VLD1d16wb_fixed:
2307 case ARM::VLD1d32wb_fixed:
2308 case ARM::VLD1d64wb_fixed:
2309 case ARM::VLD1d8wb_register:
2310 case ARM::VLD1d16wb_register:
2311 case ARM::VLD1d32wb_register:
2312 case ARM::VLD1d64wb_register:
2313 case ARM::VLD1q8wb_fixed:
2314 case ARM::VLD1q16wb_fixed:
2315 case ARM::VLD1q32wb_fixed:
2316 case ARM::VLD1q64wb_fixed:
2317 case ARM::VLD1q8wb_register:
2318 case ARM::VLD1q16wb_register:
2319 case ARM::VLD1q32wb_register:
2320 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2321 case ARM::VLD1d8Twb_fixed:
2322 case ARM::VLD1d8Twb_register:
2323 case ARM::VLD1d16Twb_fixed:
2324 case ARM::VLD1d16Twb_register:
2325 case ARM::VLD1d32Twb_fixed:
2326 case ARM::VLD1d32Twb_register:
2327 case ARM::VLD1d64Twb_fixed:
2328 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2329 case ARM::VLD1d8Qwb_fixed:
2330 case ARM::VLD1d8Qwb_register:
2331 case ARM::VLD1d16Qwb_fixed:
2332 case ARM::VLD1d16Qwb_register:
2333 case ARM::VLD1d32Qwb_fixed:
2334 case ARM::VLD1d32Qwb_register:
2335 case ARM::VLD1d64Qwb_fixed:
2336 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2337 case ARM::VLD2d8wb_fixed:
2338 case ARM::VLD2d16wb_fixed:
2339 case ARM::VLD2d32wb_fixed:
2340 case ARM::VLD2q8wb_fixed:
2341 case ARM::VLD2q16wb_fixed:
2342 case ARM::VLD2q32wb_fixed:
2343 case ARM::VLD2d8wb_register:
2344 case ARM::VLD2d16wb_register:
2345 case ARM::VLD2d32wb_register:
2346 case ARM::VLD2q8wb_register:
2347 case ARM::VLD2q16wb_register:
2348 case ARM::VLD2q32wb_register:
2349 case ARM::VLD2b8wb_fixed:
2350 case ARM::VLD2b16wb_fixed:
2351 case ARM::VLD2b32wb_fixed:
2352 case ARM::VLD2b8wb_register:
2353 case ARM::VLD2b16wb_register:
2354 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2355 Inst.addOperand(MCOperand::CreateImm(0));
2356 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2357 case ARM::VLD3d8_UPD:
2358 case ARM::VLD3d16_UPD:
2359 case ARM::VLD3d32_UPD:
2360 case ARM::VLD3q8_UPD:
2361 case ARM::VLD3q16_UPD:
2362 case ARM::VLD3q32_UPD:
2363 case ARM::VLD4d8_UPD:
2364 case ARM::VLD4d16_UPD:
2365 case ARM::VLD4d32_UPD:
2366 case ARM::VLD4q8_UPD:
2367 case ARM::VLD4q16_UPD:
2368 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2369 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2370 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2371 break;
2372 default:
2373 break;
2374 }
2375
2376 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2377 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2378 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2379
2380 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2381 switch (Inst.getOpcode()) {
2382 default:
2383 // The below have been updated to have explicit am6offset split
2384 // between fixed and register offset. For those instructions not
2385 // yet updated, we need to add an additional reg0 operand for the
2386 // fixed variant.
2387 //
2388 // The fixed offset encodes as Rm == 0xd, so we check for that.
2389 if (Rm == 0xd) {
2390 Inst.addOperand(MCOperand::CreateReg(0));
2391 break;
2392 }
2393 // Fall through to handle the register offset variant.
2394 case ARM::VLD1d8wb_fixed:
2395 case ARM::VLD1d16wb_fixed:
2396 case ARM::VLD1d32wb_fixed:
2397 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2398 case ARM::VLD1d8Twb_fixed:
2399 case ARM::VLD1d16Twb_fixed:
2400 case ARM::VLD1d32Twb_fixed:
2401 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2402 case ARM::VLD1d8Qwb_fixed:
2403 case ARM::VLD1d16Qwb_fixed:
2404 case ARM::VLD1d32Qwb_fixed:
2405 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2406 case ARM::VLD1d8wb_register:
2407 case ARM::VLD1d16wb_register:
2408 case ARM::VLD1d32wb_register:
2409 case ARM::VLD1d64wb_register:
2410 case ARM::VLD1q8wb_fixed:
2411 case ARM::VLD1q16wb_fixed:
2412 case ARM::VLD1q32wb_fixed:
2413 case ARM::VLD1q64wb_fixed:
2414 case ARM::VLD1q8wb_register:
2415 case ARM::VLD1q16wb_register:
2416 case ARM::VLD1q32wb_register:
2417 case ARM::VLD1q64wb_register:
2418 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2419 // variant encodes Rm == 0xf. Anything else is a register offset post-
2420 // increment and we need to add the register operand to the instruction.
2421 if (Rm != 0xD && Rm != 0xF &&
2422 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2423 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2424 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2425 case ARM::VLD2d8wb_fixed:
2426 case ARM::VLD2d16wb_fixed:
2427 case ARM::VLD2d32wb_fixed:
2428 case ARM::VLD2b8wb_fixed:
2429 case ARM::VLD2b16wb_fixed:
2430 case ARM::VLD2b32wb_fixed:
2431 case ARM::VLD2q8wb_fixed:
2432 case ARM::VLD2q16wb_fixed:
2433 case ARM::VLD2q32wb_fixed:
2434 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2435 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2436
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2437 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2438}
2439
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2440static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2441 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2442 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2443
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2444 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2445 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2446 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2447 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2448 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2449 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2450
2451 // Writeback Operand
2452 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2453 case ARM::VST1d8wb_fixed:
2454 case ARM::VST1d16wb_fixed:
2455 case ARM::VST1d32wb_fixed:
2456 case ARM::VST1d64wb_fixed:
2457 case ARM::VST1d8wb_register:
2458 case ARM::VST1d16wb_register:
2459 case ARM::VST1d32wb_register:
2460 case ARM::VST1d64wb_register:
2461 case ARM::VST1q8wb_fixed:
2462 case ARM::VST1q16wb_fixed:
2463 case ARM::VST1q32wb_fixed:
2464 case ARM::VST1q64wb_fixed:
2465 case ARM::VST1q8wb_register:
2466 case ARM::VST1q16wb_register:
2467 case ARM::VST1q32wb_register:
2468 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2469 case ARM::VST1d8Twb_fixed:
2470 case ARM::VST1d16Twb_fixed:
2471 case ARM::VST1d32Twb_fixed:
2472 case ARM::VST1d64Twb_fixed:
2473 case ARM::VST1d8Twb_register:
2474 case ARM::VST1d16Twb_register:
2475 case ARM::VST1d32Twb_register:
2476 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2477 case ARM::VST1d8Qwb_fixed:
2478 case ARM::VST1d16Qwb_fixed:
2479 case ARM::VST1d32Qwb_fixed:
2480 case ARM::VST1d64Qwb_fixed:
2481 case ARM::VST1d8Qwb_register:
2482 case ARM::VST1d16Qwb_register:
2483 case ARM::VST1d32Qwb_register:
2484 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2485 case ARM::VST2d8wb_fixed:
2486 case ARM::VST2d16wb_fixed:
2487 case ARM::VST2d32wb_fixed:
2488 case ARM::VST2d8wb_register:
2489 case ARM::VST2d16wb_register:
2490 case ARM::VST2d32wb_register:
2491 case ARM::VST2q8wb_fixed:
2492 case ARM::VST2q16wb_fixed:
2493 case ARM::VST2q32wb_fixed:
2494 case ARM::VST2q8wb_register:
2495 case ARM::VST2q16wb_register:
2496 case ARM::VST2q32wb_register:
2497 case ARM::VST2b8wb_fixed:
2498 case ARM::VST2b16wb_fixed:
2499 case ARM::VST2b32wb_fixed:
2500 case ARM::VST2b8wb_register:
2501 case ARM::VST2b16wb_register:
2502 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame]2503 if (Rm == 0xF)
2504 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2505 Inst.addOperand(MCOperand::CreateImm(0));
2506 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2507 case ARM::VST3d8_UPD:
2508 case ARM::VST3d16_UPD:
2509 case ARM::VST3d32_UPD:
2510 case ARM::VST3q8_UPD:
2511 case ARM::VST3q16_UPD:
2512 case ARM::VST3q32_UPD:
2513 case ARM::VST4d8_UPD:
2514 case ARM::VST4d16_UPD:
2515 case ARM::VST4d32_UPD:
2516 case ARM::VST4q8_UPD:
2517 case ARM::VST4q16_UPD:
2518 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2519 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2520 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521 break;
2522 default:
2523 break;
2524 }
2525
2526 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2527 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2528 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2529
2530 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2531 switch (Inst.getOpcode()) {
2532 default:
2533 if (Rm == 0xD)
2534 Inst.addOperand(MCOperand::CreateReg(0));
2535 else if (Rm != 0xF) {
2536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2537 return MCDisassembler::Fail;
2538 }
2539 break;
2540 case ARM::VST1d8wb_fixed:
2541 case ARM::VST1d16wb_fixed:
2542 case ARM::VST1d32wb_fixed:
2543 case ARM::VST1d64wb_fixed:
2544 case ARM::VST1q8wb_fixed:
2545 case ARM::VST1q16wb_fixed:
2546 case ARM::VST1q32wb_fixed:
2547 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2548 case ARM::VST1d8Twb_fixed:
2549 case ARM::VST1d16Twb_fixed:
2550 case ARM::VST1d32Twb_fixed:
2551 case ARM::VST1d64Twb_fixed:
2552 case ARM::VST1d8Qwb_fixed:
2553 case ARM::VST1d16Qwb_fixed:
2554 case ARM::VST1d32Qwb_fixed:
2555 case ARM::VST1d64Qwb_fixed:
2556 case ARM::VST2d8wb_fixed:
2557 case ARM::VST2d16wb_fixed:
2558 case ARM::VST2d32wb_fixed:
2559 case ARM::VST2q8wb_fixed:
2560 case ARM::VST2q16wb_fixed:
2561 case ARM::VST2q32wb_fixed:
2562 case ARM::VST2b8wb_fixed:
2563 case ARM::VST2b16wb_fixed:
2564 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2565 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2566 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2567
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2568
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2569 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2570 switch (Inst.getOpcode()) {
2571 case ARM::VST1q16:
2572 case ARM::VST1q32:
2573 case ARM::VST1q64:
2574 case ARM::VST1q8:
2575 case ARM::VST1q16wb_fixed:
2576 case ARM::VST1q16wb_register:
2577 case ARM::VST1q32wb_fixed:
2578 case ARM::VST1q32wb_register:
2579 case ARM::VST1q64wb_fixed:
2580 case ARM::VST1q64wb_register:
2581 case ARM::VST1q8wb_fixed:
2582 case ARM::VST1q8wb_register:
2583 case ARM::VST2d16:
2584 case ARM::VST2d32:
2585 case ARM::VST2d8:
2586 case ARM::VST2d16wb_fixed:
2587 case ARM::VST2d16wb_register:
2588 case ARM::VST2d32wb_fixed:
2589 case ARM::VST2d32wb_register:
2590 case ARM::VST2d8wb_fixed:
2591 case ARM::VST2d8wb_register:
2592 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2593 return MCDisassembler::Fail;
2594 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2595 case ARM::VST2b16:
2596 case ARM::VST2b32:
2597 case ARM::VST2b8:
2598 case ARM::VST2b16wb_fixed:
2599 case ARM::VST2b16wb_register:
2600 case ARM::VST2b32wb_fixed:
2601 case ARM::VST2b32wb_register:
2602 case ARM::VST2b8wb_fixed:
2603 case ARM::VST2b8wb_register:
2604 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2605 return MCDisassembler::Fail;
2606 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2607 default:
2608 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2609 return MCDisassembler::Fail;
2610 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2611
2612 // Second input register
2613 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2614 case ARM::VST3d8:
2615 case ARM::VST3d16:
2616 case ARM::VST3d32:
2617 case ARM::VST3d8_UPD:
2618 case ARM::VST3d16_UPD:
2619 case ARM::VST3d32_UPD:
2620 case ARM::VST4d8:
2621 case ARM::VST4d16:
2622 case ARM::VST4d32:
2623 case ARM::VST4d8_UPD:
2624 case ARM::VST4d16_UPD:
2625 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2626 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2627 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2628 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2629 case ARM::VST3q8:
2630 case ARM::VST3q16:
2631 case ARM::VST3q32:
2632 case ARM::VST3q8_UPD:
2633 case ARM::VST3q16_UPD:
2634 case ARM::VST3q32_UPD:
2635 case ARM::VST4q8:
2636 case ARM::VST4q16:
2637 case ARM::VST4q32:
2638 case ARM::VST4q8_UPD:
2639 case ARM::VST4q16_UPD:
2640 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2641 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2642 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2643 break;
2644 default:
2645 break;
2646 }
2647
2648 // Third input register
2649 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2650 case ARM::VST3d8:
2651 case ARM::VST3d16:
2652 case ARM::VST3d32:
2653 case ARM::VST3d8_UPD:
2654 case ARM::VST3d16_UPD:
2655 case ARM::VST3d32_UPD:
2656 case ARM::VST4d8:
2657 case ARM::VST4d16:
2658 case ARM::VST4d32:
2659 case ARM::VST4d8_UPD:
2660 case ARM::VST4d16_UPD:
2661 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2662 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2663 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2664 break;
2665 case ARM::VST3q8:
2666 case ARM::VST3q16:
2667 case ARM::VST3q32:
2668 case ARM::VST3q8_UPD:
2669 case ARM::VST3q16_UPD:
2670 case ARM::VST3q32_UPD:
2671 case ARM::VST4q8:
2672 case ARM::VST4q16:
2673 case ARM::VST4q32:
2674 case ARM::VST4q8_UPD:
2675 case ARM::VST4q16_UPD:
2676 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2677 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2678 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2679 break;
2680 default:
2681 break;
2682 }
2683
2684 // Fourth input register
2685 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2686 case ARM::VST4d8:
2687 case ARM::VST4d16:
2688 case ARM::VST4d32:
2689 case ARM::VST4d8_UPD:
2690 case ARM::VST4d16_UPD:
2691 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2692 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2693 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694 break;
2695 case ARM::VST4q8:
2696 case ARM::VST4q16:
2697 case ARM::VST4q32:
2698 case ARM::VST4q8_UPD:
2699 case ARM::VST4q16_UPD:
2700 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2701 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2702 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2703 break;
2704 default:
2705 break;
2706 }
2707
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2708 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2709}
2710
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2711static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2712 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2713 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2714
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2715 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2716 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2717 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2718 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2719 unsigned align = fieldFromInstruction(Insn, 4, 1);
2720 unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2721
Tim Northover24b9f252012-09-06 15:27:12 +0000[diff] [blame]2722 if (size == 0 && align == 1)
2723 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2724 align *= (1 << size);
2725
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2726 switch (Inst.getOpcode()) {
2727 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2728 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2729 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2730 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2731 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2732 return MCDisassembler::Fail;
2733 break;
2734 default:
2735 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2736 return MCDisassembler::Fail;
2737 break;
2738 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2739 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2741 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2742 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2743
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2745 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2746 Inst.addOperand(MCOperand::CreateImm(align));
2747
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2748 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2749 // variant encodes Rm == 0xf. Anything else is a register offset post-
2750 // increment and we need to add the register operand to the instruction.
2751 if (Rm != 0xD && Rm != 0xF &&
2752 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2753 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2754
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2755 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2756}
2757
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2758static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2759 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2760 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2761
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2762 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2763 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2764 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2765 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2766 unsigned align = fieldFromInstruction(Insn, 4, 1);
2767 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2768 align *= 2*size;
2769
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2770 switch (Inst.getOpcode()) {
2771 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2772 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2773 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2774 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2775 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2776 return MCDisassembler::Fail;
2777 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2778 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2779 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2780 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2781 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2782 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2783 return MCDisassembler::Fail;
2784 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2785 default:
2786 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2787 return MCDisassembler::Fail;
2788 break;
2789 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2790
2791 if (Rm != 0xF)
2792 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2793
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2795 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2796 Inst.addOperand(MCOperand::CreateImm(align));
2797
Kevin Enderbyc5a2a332012-04-17 00:49:27 +0000[diff] [blame]2798 if (Rm != 0xD && Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2800 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2801 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2802
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2803 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804}
2805
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2806static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2807 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2808 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2809
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2810 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2811 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2812 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2813 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2814 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2815
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2816 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2817 return MCDisassembler::Fail;
2818 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2819 return MCDisassembler::Fail;
2820 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2821 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2822 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2824 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2825 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2826
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2828 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2829 Inst.addOperand(MCOperand::CreateImm(0));
2830
2831 if (Rm == 0xD)
2832 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2833 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2835 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2836 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2837
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2838 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2839}
2840
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2841static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2842 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2843 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2844
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2845 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2846 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2847 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2848 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2849 unsigned size = fieldFromInstruction(Insn, 6, 2);
2850 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2851 unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2852
2853 if (size == 0x3) {
Tim Northover24b9f252012-09-06 15:27:12 +0000[diff] [blame]2854 if (align == 0)
2855 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2856 size = 4;
2857 align = 16;
2858 } else {
2859 if (size == 2) {
2860 size = 1 << size;
2861 align *= 8;
2862 } else {
2863 size = 1 << size;
2864 align *= 4*size;
2865 }
2866 }
2867
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2869 return MCDisassembler::Fail;
2870 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2871 return MCDisassembler::Fail;
2872 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2873 return MCDisassembler::Fail;
2874 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2875 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2876 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2878 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2879 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2882 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2883 Inst.addOperand(MCOperand::CreateImm(align));
2884
2885 if (Rm == 0xD)
2886 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2887 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2889 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2890 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2891
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2892 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893}
2894
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2895static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2896DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2897 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2898 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2899
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2900 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2901 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2902 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2903 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2904 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2905 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2906 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2907 unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2908
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2909 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2910 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2911 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2912 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2913 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2914 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2915 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2916
2917 Inst.addOperand(MCOperand::CreateImm(imm));
2918
2919 switch (Inst.getOpcode()) {
2920 case ARM::VORRiv4i16:
2921 case ARM::VORRiv2i32:
2922 case ARM::VBICiv4i16:
2923 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2924 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2925 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2926 break;
2927 case ARM::VORRiv8i16:
2928 case ARM::VORRiv4i32:
2929 case ARM::VBICiv8i16:
2930 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2931 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2932 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2933 break;
2934 default:
2935 break;
2936 }
2937
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2938 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2939}
2940
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2941static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2942 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2943 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2944
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2945 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2946 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2947 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2948 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2949 unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2950
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2951 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2952 return MCDisassembler::Fail;
2953 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2954 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2955 Inst.addOperand(MCOperand::CreateImm(8 << size));
2956
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2957 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2958}
2959
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2960static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2961 uint64_t Address, const void *Decoder) {
2962 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2963 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2964}
2965
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2966static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2967 uint64_t Address, const void *Decoder) {
2968 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2969 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2970}
2971
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2972static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2973 uint64_t Address, const void *Decoder) {
2974 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2975 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2976}
2977
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2978static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2979 uint64_t Address, const void *Decoder) {
2980 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2981 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2982}
2983
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2984static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2985 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2986 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2987
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2988 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2989 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2990 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2991 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2992 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2993 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2994 unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2995
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2996 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2997 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2998 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3000 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]3001 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3002
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]3003 switch (Inst.getOpcode()) {
3004 case ARM::VTBL2:
3005 case ARM::VTBX2:
3006 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3007 return MCDisassembler::Fail;
3008 break;
3009 default:
3010 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3011 return MCDisassembler::Fail;
3012 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3013
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3014 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3015 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3016
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3017 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3018}
3019
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3020static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3021 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3022 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3023
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3024 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3025 unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3026
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3027 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3028 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3029
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3030 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]3031 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3032 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3033 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]3034 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3035 case ARM::tADDrSPi:
3036 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3037 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3038 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3039
3040 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3041 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3042}
3043
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3044static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3045 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3046 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3047 true, 2, Inst, Decoder))
3048 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3049 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3050}
3051
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3052static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3053 uint64_t Address, const void *Decoder) {
Kevin Enderby3610a152012-05-04 22:09:52 +0000[diff] [blame]3054 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3055 true, 4, Inst, Decoder))
3056 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3057 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3058}
3059
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3060static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3061 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3062 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
3063 true, 2, Inst, Decoder))
3064 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3065 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3066}
3067
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3068static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3069 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3070 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3071
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3072 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3073 unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3074
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3075 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3076 return MCDisassembler::Fail;
3077 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3078 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3079
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3080 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3081}
3082
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3083static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3084 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3085 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3086
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3087 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3088 unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3089
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3090 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3091 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3092 Inst.addOperand(MCOperand::CreateImm(imm));
3093
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3094 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3095}
3096
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3097static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3098 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3099 unsigned imm = Val << 2;
3100
3101 Inst.addOperand(MCOperand::CreateImm(imm));
3102 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3103
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3104 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3105}
3106
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3107static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3108 uint64_t Address, const void *Decoder) {
3109 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3110 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3111
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3112 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3113}
3114
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3115static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3116 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3117 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3118
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3119 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3120 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3121 unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3122
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3124 return MCDisassembler::Fail;
3125 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3126 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3127 Inst.addOperand(MCOperand::CreateImm(imm));
3128
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3129 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3130}
3131
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3132static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3133 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3134 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3135
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3136 switch (Inst.getOpcode()) {
3137 case ARM::t2PLDs:
3138 case ARM::t2PLDWs:
3139 case ARM::t2PLIs:
3140 break;
3141 default: {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3142 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3143 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3144 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3145 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3146 }
3147
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3148 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3149 if (Rn == 0xF) {
3150 switch (Inst.getOpcode()) {
3151 case ARM::t2LDRBs:
3152 Inst.setOpcode(ARM::t2LDRBpci);
3153 break;
3154 case ARM::t2LDRHs:
3155 Inst.setOpcode(ARM::t2LDRHpci);
3156 break;
3157 case ARM::t2LDRSHs:
3158 Inst.setOpcode(ARM::t2LDRSHpci);
3159 break;
3160 case ARM::t2LDRSBs:
3161 Inst.setOpcode(ARM::t2LDRSBpci);
3162 break;
3163 case ARM::t2PLDs:
3164 Inst.setOpcode(ARM::t2PLDi12);
3165 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3166 break;
3167 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3168 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3169 }
3170
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3171 int imm = fieldFromInstruction(Insn, 0, 12);
3172 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3173 Inst.addOperand(MCOperand::CreateImm(imm));
3174
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3175 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3176 }
3177
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3178 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3179 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3180 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3181 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3182 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3183
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3184 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3185}
3186
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3187static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3188 uint64_t Address, const void *Decoder) {
Jiangning Liufd652df2012-08-02 08:29:50 +0000[diff] [blame]3189 if (Val == 0)
3190 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3191 else {
3192 int imm = Val & 0xFF;
3193
3194 if (!(Val & 0x100)) imm *= -1;
Richard Smith1144af32012-08-24 23:29:28 +0000[diff] [blame]3195 Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liufd652df2012-08-02 08:29:50 +0000[diff] [blame]3196 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3197
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3198 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3199}
3200
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3201static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3202 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3203 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3204
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3205 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3206 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3207
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3209 return MCDisassembler::Fail;
3210 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3211 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3212
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3213 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3214}
3215
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3216static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3217 uint64_t Address, const void *Decoder) {
3218 DecodeStatus S = MCDisassembler::Success;
3219
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3220 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3221 unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3222
3223 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3224 return MCDisassembler::Fail;
3225
3226 Inst.addOperand(MCOperand::CreateImm(imm));
3227
3228 return S;
3229}
3230
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3231static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3232 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3233 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3234 if (Val == 0)
3235 imm = INT32_MIN;
3236 else if (!(Val & 0x100))
3237 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3238 Inst.addOperand(MCOperand::CreateImm(imm));
3239
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3240 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3241}
3242
3243
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3244static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3245 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3246 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3247
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3248 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3249 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3250
3251 // Some instructions always use an additive offset.
3252 switch (Inst.getOpcode()) {
3253 case ARM::t2LDRT:
3254 case ARM::t2LDRBT:
3255 case ARM::t2LDRHT:
3256 case ARM::t2LDRSBT:
3257 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3258 case ARM::t2STRT:
3259 case ARM::t2STRBT:
3260 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3261 imm |= 0x100;
3262 break;
3263 default:
3264 break;
3265 }
3266
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3268 return MCDisassembler::Fail;
3269 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3270 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3271
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3272 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3273}
3274
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3275static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3276 uint64_t Address, const void *Decoder) {
3277 DecodeStatus S = MCDisassembler::Success;
3278
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3279 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3280 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3281 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3282 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3283 addr |= Rn << 9;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3284 unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3285
3286 if (!load) {
3287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3288 return MCDisassembler::Fail;
3289 }
3290
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]3291 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3292 return MCDisassembler::Fail;
3293
3294 if (load) {
3295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3296 return MCDisassembler::Fail;
3297 }
3298
3299 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3300 return MCDisassembler::Fail;
3301
3302 return S;
3303}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3304
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3305static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3306 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3307 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3308
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3309 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3310 unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3311
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3313 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3314 Inst.addOperand(MCOperand::CreateImm(imm));
3315
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3316 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3317}
3318
3319
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3320static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3321 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3322 unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3323
3324 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3325 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3326 Inst.addOperand(MCOperand::CreateImm(imm));
3327
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3328 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3329}
3330
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3331static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3332 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3333 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3334
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3335 if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3336 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3337 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3338
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3340 return MCDisassembler::Fail;
Jim Grosbachbb32f1d2012-04-27 23:51:33 +0000[diff] [blame]3341 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3343 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3344 } else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3345 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3346
3347 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3348 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3350 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3351 }
3352
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3353 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3354}
3355
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3356static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3357 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3358 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3359 unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3360
3361 Inst.addOperand(MCOperand::CreateImm(imod));
3362 Inst.addOperand(MCOperand::CreateImm(flags));
3363
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3364 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3365}
3366
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3367static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3368 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3369 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3370 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3371 unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3372
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3373 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3374 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3375 Inst.addOperand(MCOperand::CreateImm(add));
3376
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3377 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3378}
3379
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3380static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3381 uint64_t Address, const void *Decoder) {
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3382 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3383 // Note only one trailing zero not two. Also the J1 and J2 values are from
3384 // the encoded instruction. So here change to I1 and I2 values via:
3385 // I1 = NOT(J1 EOR S);
3386 // I2 = NOT(J2 EOR S);
3387 // and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3388 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3389 unsigned S = (Val >> 23) & 1;
3390 unsigned J1 = (Val >> 22) & 1;
3391 unsigned J2 = (Val >> 21) & 1;
3392 unsigned I1 = !(J1 ^ S);
3393 unsigned I2 = !(J2 ^ S);
3394 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3395 int imm32 = SignExtend32<25>(tmp << 1);
3396
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3397 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3398 (Address & ~2u) + imm32 + 4,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3399 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3400 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3401 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3402}
3403
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3404static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3405 uint64_t Address, const void *Decoder) {
3406 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3407 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3408
3409 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3410 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3411}
3412
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3413static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3414DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3415 uint64_t Address, const void *Decoder) {
3416 DecodeStatus S = MCDisassembler::Success;
3417
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3418 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3419 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3420
3421 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3423 return MCDisassembler::Fail;
3424 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3425 return MCDisassembler::Fail;
3426 return S;
3427}
3428
3429static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3430DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3431 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3432 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3433
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3434 unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3435 if (pred == 0xE || pred == 0xF) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3436 unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3437 switch (opc) {
3438 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3439 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3440 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3441 Inst.setOpcode(ARM::t2DSB);
3442 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3443 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3444 Inst.setOpcode(ARM::t2DMB);
3445 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3446 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3447 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3448 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3449 }
3450
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3451 unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3452 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3453 }
3454
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3455 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3456 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3457 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3458 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3459 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3460
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3461 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3462 return MCDisassembler::Fail;
3463 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3464 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3465
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3466 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3467}
3468
3469// Decode a shifted immediate operand. These basically consist
3470// of an 8-bit value, and a 4-bit directive that specifies either
3471// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3472static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3473 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3474 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3475 if (ctrl == 0) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3476 unsigned byte = fieldFromInstruction(Val, 8, 2);
3477 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3478 switch (byte) {
3479 case 0:
3480 Inst.addOperand(MCOperand::CreateImm(imm));
3481 break;
3482 case 1:
3483 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3484 break;
3485 case 2:
3486 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3487 break;
3488 case 3:
3489 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3490 (imm << 8) | imm));
3491 break;
3492 }
3493 } else {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3494 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3495 unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3496 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3497 Inst.addOperand(MCOperand::CreateImm(imm));
3498 }
3499
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3500 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3501}
3502
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3503static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3504DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3505 uint64_t Address, const void *Decoder){
Richard Bartonc8f2fcc2012-06-06 09:12:53 +0000[diff] [blame]3506 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3507 true, 2, Inst, Decoder))
Richard Bartonc8f2fcc2012-06-06 09:12:53 +0000[diff] [blame]3508 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3509 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3510}
3511
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3512static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3513 uint64_t Address, const void *Decoder){
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3514 // Val is passed in as S:J1:J2:imm10:imm11
3515 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3516 // the encoded instruction. So here change to I1 and I2 values via:
3517 // I1 = NOT(J1 EOR S);
3518 // I2 = NOT(J2 EOR S);
3519 // and build the imm32 with one trailing zero as documented:
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3520 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3521 unsigned S = (Val >> 23) & 1;
3522 unsigned J1 = (Val >> 22) & 1;
3523 unsigned J2 = (Val >> 21) & 1;
3524 unsigned I1 = !(J1 ^ S);
3525 unsigned I2 = !(J2 ^ S);
3526 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3527 int imm32 = SignExtend32<25>(tmp << 1);
3528
3529 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3530 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3531 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3532 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3533}
3534
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3535static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3536 uint64_t Address, const void *Decoder) {
Jiangning Liuc1b7ca52012-08-02 08:21:27 +0000[diff] [blame]3537 if (Val & ~0xf)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3538 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3539
3540 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3541 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3542}
3543
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3544static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3545 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3546 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3547 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3548 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3549}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3550
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3551static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3552 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3553 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3554
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3555 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3556 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3557 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3558
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3559 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3560
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3562 return MCDisassembler::Fail;
3563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3564 return MCDisassembler::Fail;
3565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3566 return MCDisassembler::Fail;
3567 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3568 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3569
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3570 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3571}
3572
3573
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3574static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3575 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3576 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3577
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3578 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3579 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3580 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3581 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3582
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3583 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3584 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3585
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3586 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3587 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3588
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3589 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3590 return MCDisassembler::Fail;
3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3592 return MCDisassembler::Fail;
3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3596 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3597
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3598 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3599}
3600
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3601static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3602 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3603 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3604
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3605 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3606 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3607 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3608 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3609 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3610 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3611
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3612 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3613
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3615 return MCDisassembler::Fail;
3616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3617 return MCDisassembler::Fail;
3618 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3619 return MCDisassembler::Fail;
3620 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3621 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3622
3623 return S;
3624}
3625
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3626static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3627 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3628 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3629
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3630 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3631 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3632 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3633 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3634 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3635 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3636 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3637
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3638 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3639 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3640
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3642 return MCDisassembler::Fail;
3643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3644 return MCDisassembler::Fail;
3645 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3646 return MCDisassembler::Fail;
3647 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3648 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3649
3650 return S;
3651}
3652
3653
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3654static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3655 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3656 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3657
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3658 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3659 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3660 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3661 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3662 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3663 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3664
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3665 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3666
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3668 return MCDisassembler::Fail;
3669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3670 return MCDisassembler::Fail;
3671 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3672 return MCDisassembler::Fail;
3673 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3674 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3675
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3676 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3677}
3678
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3679static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3680 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3681 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3682
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3683 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3684 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3685 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3686 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3687 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3688 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3689
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3690 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3691
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3693 return MCDisassembler::Fail;
3694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3695 return MCDisassembler::Fail;
3696 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3697 return MCDisassembler::Fail;
3698 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3699 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3700
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3701 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3702}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3703
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3704static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3705 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3706 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3707
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3708 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3709 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3710 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3711 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3712 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3713
3714 unsigned align = 0;
3715 unsigned index = 0;
3716 switch (size) {
3717 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3718 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3719 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3720 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3721 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3722 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3723 break;
3724 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3725 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3726 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3727 index = fieldFromInstruction(Insn, 6, 2);
3728 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3729 align = 2;
3730 break;
3731 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3732 if (fieldFromInstruction(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3733 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3734 index = fieldFromInstruction(Insn, 7, 1);
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]3735
3736 switch (fieldFromInstruction(Insn, 4, 2)) {
3737 case 0 :
3738 align = 0; break;
3739 case 3:
3740 align = 4; break;
3741 default:
3742 return MCDisassembler::Fail;
3743 }
3744 break;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3745 }
3746
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3748 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3749 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3751 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3752 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3754 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3755 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3756 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3757 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3759 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3760 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3761 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3762 }
3763
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3764 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3765 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3766 Inst.addOperand(MCOperand::CreateImm(index));
3767
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3768 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3769}
3770
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3771static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3772 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3773 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3774
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3775 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3776 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3777 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3778 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3779 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3780
3781 unsigned align = 0;
3782 unsigned index = 0;
3783 switch (size) {
3784 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3785 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3786 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3787 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3788 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3789 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3790 break;
3791 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3792 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3793 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3794 index = fieldFromInstruction(Insn, 6, 2);
3795 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3796 align = 2;
3797 break;
3798 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3799 if (fieldFromInstruction(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3800 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3801 index = fieldFromInstruction(Insn, 7, 1);
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]3802
3803 switch (fieldFromInstruction(Insn, 4, 2)) {
3804 case 0:
3805 align = 0; break;
3806 case 3:
3807 align = 4; break;
3808 default:
3809 return MCDisassembler::Fail;
3810 }
3811 break;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3812 }
3813
3814 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3816 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3817 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3819 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3820 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3821 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3822 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3824 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3825 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3826 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3827 }
3828
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3830 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3831 Inst.addOperand(MCOperand::CreateImm(index));
3832
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3833 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3834}
3835
3836
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3837static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3838 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3839 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3840
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3841 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3842 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3843 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3844 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3845 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3846
3847 unsigned align = 0;
3848 unsigned index = 0;
3849 unsigned inc = 1;
3850 switch (size) {
3851 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3852 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3853 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3854 index = fieldFromInstruction(Insn, 5, 3);
3855 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3856 align = 2;
3857 break;
3858 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3859 index = fieldFromInstruction(Insn, 6, 2);
3860 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3861 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3862 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3863 inc = 2;
3864 break;
3865 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3866 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3867 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3868 index = fieldFromInstruction(Insn, 7, 1);
3869 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3870 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3871 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3872 inc = 2;
3873 break;
3874 }
3875
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3877 return MCDisassembler::Fail;
3878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3879 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3880 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3882 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3883 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3885 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3886 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3887 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3888 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3890 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3891 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3892 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3893 }
3894
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3896 return MCDisassembler::Fail;
3897 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3898 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3899 Inst.addOperand(MCOperand::CreateImm(index));
3900
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3901 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3902}
3903
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3904static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3905 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3906 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3907
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3908 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3909 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3910 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3911 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3912 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3913
3914 unsigned align = 0;
3915 unsigned index = 0;
3916 unsigned inc = 1;
3917 switch (size) {
3918 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3919 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3920 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3921 index = fieldFromInstruction(Insn, 5, 3);
3922 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3923 align = 2;
3924 break;
3925 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3926 index = fieldFromInstruction(Insn, 6, 2);
3927 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3928 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3929 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3930 inc = 2;
3931 break;
3932 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3933 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3934 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3935 index = fieldFromInstruction(Insn, 7, 1);
3936 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3937 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3938 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3939 inc = 2;
3940 break;
3941 }
3942
3943 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3945 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3946 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3948 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3949 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3950 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3951 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3953 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3954 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3955 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3956 }
3957
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3958 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3959 return MCDisassembler::Fail;
3960 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3961 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3962 Inst.addOperand(MCOperand::CreateImm(index));
3963
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3964 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3965}
3966
3967
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3968static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3969 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3970 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3971
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3972 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3973 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3974 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3975 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3976 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3977
3978 unsigned align = 0;
3979 unsigned index = 0;
3980 unsigned inc = 1;
3981 switch (size) {
3982 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3983 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3984 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3985 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3986 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3987 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3988 break;
3989 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3990 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3991 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3992 index = fieldFromInstruction(Insn, 6, 2);
3993 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3994 inc = 2;
3995 break;
3996 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3997 if (fieldFromInstruction(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3998 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3999 index = fieldFromInstruction(Insn, 7, 1);
4000 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4001 inc = 2;
4002 break;
4003 }
4004
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4006 return MCDisassembler::Fail;
4007 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4008 return MCDisassembler::Fail;
4009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4010 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4011
4012 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4014 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4015 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4017 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4018 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4019 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4020 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4022 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4023 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4024 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4025 }
4026
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4027 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4028 return MCDisassembler::Fail;
4029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4030 return MCDisassembler::Fail;
4031 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4032 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4033 Inst.addOperand(MCOperand::CreateImm(index));
4034
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4035 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4036}
4037
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4038static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4039 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4040 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4041
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4042 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4043 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4044 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4045 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4046 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4047
4048 unsigned align = 0;
4049 unsigned index = 0;
4050 unsigned inc = 1;
4051 switch (size) {
4052 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4053 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4054 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4055 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4056 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4057 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4058 break;
4059 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4060 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4061 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4062 index = fieldFromInstruction(Insn, 6, 2);
4063 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4064 inc = 2;
4065 break;
4066 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4067 if (fieldFromInstruction(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4068 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4069 index = fieldFromInstruction(Insn, 7, 1);
4070 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4071 inc = 2;
4072 break;
4073 }
4074
4075 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4077 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4078 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4080 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4081 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4082 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4083 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4085 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4086 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4087 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4088 }
4089
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4091 return MCDisassembler::Fail;
4092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4093 return MCDisassembler::Fail;
4094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4095 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4096 Inst.addOperand(MCOperand::CreateImm(index));
4097
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4098 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4099}
4100
4101
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4102static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4103 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4104 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4105
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4106 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4107 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4108 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4109 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4110 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4111
4112 unsigned align = 0;
4113 unsigned index = 0;
4114 unsigned inc = 1;
4115 switch (size) {
4116 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4117 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4118 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4119 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4120 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4121 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4122 break;
4123 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4124 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4125 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4126 index = fieldFromInstruction(Insn, 6, 2);
4127 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4128 inc = 2;
4129 break;
4130 case 2:
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]4131 switch (fieldFromInstruction(Insn, 4, 2)) {
4132 case 0:
4133 align = 0; break;
4134 case 3:
4135 return MCDisassembler::Fail;
4136 default:
4137 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4138 }
4139
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4140 index = fieldFromInstruction(Insn, 7, 1);
4141 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4142 inc = 2;
4143 break;
4144 }
4145
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4146 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4147 return MCDisassembler::Fail;
4148 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4149 return MCDisassembler::Fail;
4150 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4151 return MCDisassembler::Fail;
4152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4153 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4154
4155 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4157 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4158 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4160 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4161 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4162 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4163 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4165 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4166 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4167 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4168 }
4169
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4170 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4171 return MCDisassembler::Fail;
4172 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4173 return MCDisassembler::Fail;
4174 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4175 return MCDisassembler::Fail;
4176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4177 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4178 Inst.addOperand(MCOperand::CreateImm(index));
4179
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4180 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4181}
4182
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4183static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4184 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4185 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4186
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4187 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4188 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4189 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4190 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4191 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4192
4193 unsigned align = 0;
4194 unsigned index = 0;
4195 unsigned inc = 1;
4196 switch (size) {
4197 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4198 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4199 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4200 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4201 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4202 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4203 break;
4204 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4205 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4206 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4207 index = fieldFromInstruction(Insn, 6, 2);
4208 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4209 inc = 2;
4210 break;
4211 case 2:
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]4212 switch (fieldFromInstruction(Insn, 4, 2)) {
4213 case 0:
4214 align = 0; break;
4215 case 3:
4216 return MCDisassembler::Fail;
4217 default:
4218 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4219 }
4220
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4221 index = fieldFromInstruction(Insn, 7, 1);
4222 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4223 inc = 2;
4224 break;
4225 }
4226
4227 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4229 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4230 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4232 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4233 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4234 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4235 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4237 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4238 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4239 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4240 }
4241
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4242 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4243 return MCDisassembler::Fail;
4244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4245 return MCDisassembler::Fail;
4246 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4247 return MCDisassembler::Fail;
4248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4249 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4250 Inst.addOperand(MCOperand::CreateImm(index));
4251
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4252 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4253}
4254
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4255static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4256 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4257 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4258 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4259 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4260 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4261 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4262 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4263
4264 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4265 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4266
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4267 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4268 return MCDisassembler::Fail;
4269 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4270 return MCDisassembler::Fail;
4271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4272 return MCDisassembler::Fail;
4273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4274 return MCDisassembler::Fail;
4275 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4276 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4277
4278 return S;
4279}
4280
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4281static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4282 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4283 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4284 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4285 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4286 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4287 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4288 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4289
4290 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4291 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4292
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4294 return MCDisassembler::Fail;
4295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4296 return MCDisassembler::Fail;
4297 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4298 return MCDisassembler::Fail;
4299 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4300 return MCDisassembler::Fail;
4301 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4302 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4303
4304 return S;
4305}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4306
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4307static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4308 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4309 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4310 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4311 unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4312
4313 if (pred == 0xF) {
4314 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4315 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4316 }
4317
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]4318 if (mask == 0x0) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4319 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4320 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4321 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4322
4323 Inst.addOperand(MCOperand::CreateImm(pred));
4324 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4325 return S;
4326}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4327
4328static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4329DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4330 uint64_t Address, const void *Decoder) {
4331 DecodeStatus S = MCDisassembler::Success;
4332
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4333 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4334 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4335 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4336 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4337 unsigned W = fieldFromInstruction(Insn, 21, 1);
4338 unsigned U = fieldFromInstruction(Insn, 23, 1);
4339 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4340 bool writeback = (W == 1) | (P == 0);
4341
4342 addr |= (U << 8) | (Rn << 9);
4343
4344 if (writeback && (Rn == Rt || Rn == Rt2))
4345 Check(S, MCDisassembler::SoftFail);
4346 if (Rt == Rt2)
4347 Check(S, MCDisassembler::SoftFail);
4348
4349 // Rt
4350 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4351 return MCDisassembler::Fail;
4352 // Rt2
4353 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4354 return MCDisassembler::Fail;
4355 // Writeback operand
4356 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4357 return MCDisassembler::Fail;
4358 // addr
4359 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4360 return MCDisassembler::Fail;
4361
4362 return S;
4363}
4364
4365static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4366DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4367 uint64_t Address, const void *Decoder) {
4368 DecodeStatus S = MCDisassembler::Success;
4369
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4370 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4371 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4372 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4373 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4374 unsigned W = fieldFromInstruction(Insn, 21, 1);
4375 unsigned U = fieldFromInstruction(Insn, 23, 1);
4376 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4377 bool writeback = (W == 1) | (P == 0);
4378
4379 addr |= (U << 8) | (Rn << 9);
4380
4381 if (writeback && (Rn == Rt || Rn == Rt2))
4382 Check(S, MCDisassembler::SoftFail);
4383
4384 // Writeback operand
4385 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4386 return MCDisassembler::Fail;
4387 // Rt
4388 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4389 return MCDisassembler::Fail;
4390 // Rt2
4391 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4392 return MCDisassembler::Fail;
4393 // addr
4394 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4395 return MCDisassembler::Fail;
4396
4397 return S;
4398}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4399
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4400static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4401 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4402 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4403 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4404 if (sign1 != sign2) return MCDisassembler::Fail;
4405
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4406 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4407 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4408 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4409 Val |= sign1 << 12;
4410 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4411
4412 return MCDisassembler::Success;
4413}
4414
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4415static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4416 uint64_t Address,
4417 const void *Decoder) {
4418 DecodeStatus S = MCDisassembler::Success;
4419
4420 // Shift of "asr #32" is not allowed in Thumb2 mode.
4421 if (Val == 0x20) S = MCDisassembler::SoftFail;
4422 Inst.addOperand(MCOperand::CreateImm(Val));
4423 return S;
4424}
4425
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4426static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4427 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4428 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4429 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4430 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4431 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4432
4433 if (pred == 0xF)
4434 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4435
4436 DecodeStatus S = MCDisassembler::Success;
Silviu Baranga35ee7d22012-04-18 14:18:57 +0000[diff] [blame]4437
4438 if (Rt == Rn || Rn == Rt2)
4439 S = MCDisassembler::SoftFail;
4440
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4441 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4442 return MCDisassembler::Fail;
4443 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4444 return MCDisassembler::Fail;
4445 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4446 return MCDisassembler::Fail;
4447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4448 return MCDisassembler::Fail;
4449
4450 return S;
4451}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4452
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4453static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4454 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4455 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4456 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4457 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4458 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4459 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4460 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4461
4462 DecodeStatus S = MCDisassembler::Success;
4463
4464 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4465 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4466 Inst.setOpcode(ARM::VMOVv2f32);
4467 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4468 }
4469
4470 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4471
4472 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4473 return MCDisassembler::Fail;
4474 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4475 return MCDisassembler::Fail;
4476 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4477
4478 return S;
4479}
4480
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4481static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4482 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4483 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4484 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4485 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4486 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4487 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4488 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4489
4490 DecodeStatus S = MCDisassembler::Success;
4491
4492 // VMOVv4f32 is ambiguous with these decodings.
4493 if (!(imm & 0x38) && cmode == 0xF) {
4494 Inst.setOpcode(ARM::VMOVv4f32);
4495 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4496 }
4497
4498 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4499
4500 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4501 return MCDisassembler::Fail;
4502 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4503 return MCDisassembler::Fail;
4504 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4505
4506 return S;
4507}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4508
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4509static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4510 uint64_t Address, const void *Decoder) {
4511 DecodeStatus S = MCDisassembler::Success;
4512
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4513 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4514 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4515 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4516 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4517 unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4518
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4519 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4520 S = MCDisassembler::SoftFail;
4521
4522 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4523 return MCDisassembler::Fail;
4524 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4525 return MCDisassembler::Fail;
4526 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4527 return MCDisassembler::Fail;
4528 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4529 return MCDisassembler::Fail;
4530 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4531 return MCDisassembler::Fail;
4532
4533 return S;
4534}
4535
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4536static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4537 uint64_t Address, const void *Decoder) {
4538
4539 DecodeStatus S = MCDisassembler::Success;
4540
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4541 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4542 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4543 unsigned cop = fieldFromInstruction(Val, 8, 4);
4544 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4545 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4546
4547 if ((cop & ~0x1) == 0xa)
4548 return MCDisassembler::Fail;
4549
4550 if (Rt == Rt2)
4551 S = MCDisassembler::SoftFail;
4552
4553 Inst.addOperand(MCOperand::CreateImm(cop));
4554 Inst.addOperand(MCOperand::CreateImm(opc1));
4555 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4556 return MCDisassembler::Fail;
4557 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4558 return MCDisassembler::Fail;
4559 Inst.addOperand(MCOperand::CreateImm(CRm));
4560
4561 return S;
4562}
4563