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Kevin Enderbyca9c42c2009-09-15 00:27:25 +00001//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Evan Cheng94b95502011-07-26 00:24:13 +000010#include "MCTargetDesc/ARMBaseInfo.h"
Evan Chengee04a6d2011-07-20 23:34:39 +000011#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
Chris Lattnerc6ef2772010-01-22 01:44:57 +000013#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
Rafael Espindola64695402011-05-16 16:17:21 +000016#include "llvm/MC/MCAsmInfo.h"
Jim Grosbach642fc9c2010-11-05 22:33:53 +000017#include "llvm/MC/MCContext.h"
Kevin Enderbyca9c42c2009-09-15 00:27:25 +000018#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
Evan Cheng78011362011-08-23 20:15:21 +000021#include "llvm/MC/MCInstrDesc.h"
Evan Cheng94b95502011-07-26 00:24:13 +000022#include "llvm/MC/MCRegisterInfo.h"
Evan Chengebdeeab2011-07-08 01:53:10 +000023#include "llvm/MC/MCSubtargetInfo.h"
Evan Cheng94b95502011-07-26 00:24:13 +000024#include "llvm/MC/MCTargetAsmParser.h"
Jim Grosbach89df9962011-08-26 21:43:41 +000025#include "llvm/Support/MathExtras.h"
Chris Lattnerc6ef2772010-01-22 01:44:57 +000026#include "llvm/Support/SourceMgr.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +000027#include "llvm/Support/TargetRegistry.h"
Daniel Dunbarfa315de2010-08-11 06:37:12 +000028#include "llvm/Support/raw_ostream.h"
Jim Grosbach11e03e72011-08-22 18:50:36 +000029#include "llvm/ADT/BitVector.h"
Benjamin Kramer75ca4b92011-07-08 21:06:23 +000030#include "llvm/ADT/OwningPtr.h"
Evan Cheng94b95502011-07-26 00:24:13 +000031#include "llvm/ADT/STLExtras.h"
Chris Lattnerc6ef2772010-01-22 01:44:57 +000032#include "llvm/ADT/SmallVector.h"
Daniel Dunbar345a9a62010-08-11 06:37:20 +000033#include "llvm/ADT/StringSwitch.h"
Chris Lattnerc6ef2772010-01-22 01:44:57 +000034#include "llvm/ADT/Twine.h"
Evan Chengebdeeab2011-07-08 01:53:10 +000035
Kevin Enderbyca9c42c2009-09-15 00:27:25 +000036using namespace llvm;
37
Chris Lattner3a697562010-10-28 17:20:03 +000038namespace {
Bill Wendling146018f2010-11-06 21:42:12 +000039
40class ARMOperand;
Jim Grosbach16c74252010-10-29 14:46:02 +000041
Jim Grosbach7636bf62011-12-02 00:35:16 +000042enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
Jim Grosbach98b05a52011-11-30 01:09:44 +000043
Evan Cheng94b95502011-07-26 00:24:13 +000044class ARMAsmParser : public MCTargetAsmParser {
Evan Chengffc0e732011-07-09 05:47:46 +000045 MCSubtargetInfo &STI;
Kevin Enderbyca9c42c2009-09-15 00:27:25 +000046 MCAsmParser &Parser;
47
Jim Grosbacha39cda72011-12-14 02:16:11 +000048 // Map of register aliases registers via the .req directive.
49 StringMap<unsigned> RegisterReqs;
50
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +000051 struct {
52 ARMCC::CondCodes Cond; // Condition for IT block.
53 unsigned Mask:4; // Condition mask for instructions.
54 // Starting at first 1 (from lsb).
55 // '1' condition as indicated in IT.
56 // '0' inverse of condition (else).
57 // Count of instructions in IT block is
58 // 4 - trailingzeroes(mask)
59
60 bool FirstCond; // Explicit flag for when we're parsing the
61 // First instruction in the IT block. It's
62 // implied in the mask, so needs special
63 // handling.
64
65 unsigned CurPosition; // Current position in parsing of IT
66 // block. In range [0,3]. Initialized
67 // according to count of instructions in block.
68 // ~0U if no active IT block.
69 } ITState;
70 bool inITBlock() { return ITState.CurPosition != ~0U;}
Jim Grosbacha1109882011-09-02 23:22:08 +000071 void forwardITPosition() {
72 if (!inITBlock()) return;
73 // Move to the next instruction in the IT block, if there is one. If not,
74 // mark the block as done.
75 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
76 if (++ITState.CurPosition == 5 - TZ)
77 ITState.CurPosition = ~0U; // Done with the IT block after this.
78 }
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +000079
80
Kevin Enderbyca9c42c2009-09-15 00:27:25 +000081 MCAsmParser &getParser() const { return Parser; }
Kevin Enderbyca9c42c2009-09-15 00:27:25 +000082 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
83
84 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
Kevin Enderbyca9c42c2009-09-15 00:27:25 +000085 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
86
Jim Grosbach1355cf12011-07-26 17:10:22 +000087 int tryParseRegister();
88 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach0d87ec22011-07-26 20:41:24 +000089 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach1355cf12011-07-26 17:10:22 +000090 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach7ce05792011-08-03 23:50:40 +000091 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach1355cf12011-07-26 17:10:22 +000092 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
93 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
Jim Grosbach7ce05792011-08-03 23:50:40 +000094 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
95 unsigned &ShiftAmount);
Jim Grosbach1355cf12011-07-26 17:10:22 +000096 bool parseDirectiveWord(unsigned Size, SMLoc L);
97 bool parseDirectiveThumb(SMLoc L);
Jim Grosbach9a70df92011-12-07 18:04:19 +000098 bool parseDirectiveARM(SMLoc L);
Jim Grosbach1355cf12011-07-26 17:10:22 +000099 bool parseDirectiveThumbFunc(SMLoc L);
100 bool parseDirectiveCode(SMLoc L);
101 bool parseDirectiveSyntax(SMLoc L);
Jim Grosbacha39cda72011-12-14 02:16:11 +0000102 bool parseDirectiveReq(StringRef Name, SMLoc L);
103 bool parseDirectiveUnreq(SMLoc L);
Jason W Kimd7c9e082011-12-20 17:38:12 +0000104 bool parseDirectiveArch(SMLoc L);
105 bool parseDirectiveEabiAttr(SMLoc L);
Kevin Enderby515d5092009-10-15 20:48:48 +0000106
Jim Grosbach1355cf12011-07-26 17:10:22 +0000107 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
Jim Grosbach89df9962011-08-26 21:43:41 +0000108 bool &CarrySetting, unsigned &ProcessorIMod,
109 StringRef &ITMask);
Jim Grosbach1355cf12011-07-26 17:10:22 +0000110 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
Bruno Cardoso Lopesfdcee772011-01-18 20:55:11 +0000111 bool &CanAcceptPredicationCode);
Jim Grosbach16c74252010-10-29 14:46:02 +0000112
Evan Chengebdeeab2011-07-08 01:53:10 +0000113 bool isThumb() const {
114 // FIXME: Can tablegen auto-generate this?
Evan Chengffc0e732011-07-09 05:47:46 +0000115 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
Evan Chengebdeeab2011-07-08 01:53:10 +0000116 }
Evan Chengebdeeab2011-07-08 01:53:10 +0000117 bool isThumbOne() const {
Evan Chengffc0e732011-07-09 05:47:46 +0000118 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
Evan Chengebdeeab2011-07-08 01:53:10 +0000119 }
Jim Grosbach47a0d522011-08-16 20:45:50 +0000120 bool isThumbTwo() const {
121 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
122 }
Jim Grosbach194bd892011-08-16 22:20:01 +0000123 bool hasV6Ops() const {
124 return STI.getFeatureBits() & ARM::HasV6Ops;
125 }
James Molloyacad68d2011-09-28 14:21:38 +0000126 bool hasV7Ops() const {
127 return STI.getFeatureBits() & ARM::HasV7Ops;
128 }
Evan Cheng32869202011-07-08 22:36:29 +0000129 void SwitchMode() {
Evan Chengffc0e732011-07-09 05:47:46 +0000130 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
131 setAvailableFeatures(FB);
Evan Cheng32869202011-07-08 22:36:29 +0000132 }
James Molloyacad68d2011-09-28 14:21:38 +0000133 bool isMClass() const {
134 return STI.getFeatureBits() & ARM::FeatureMClass;
135 }
Evan Chengebdeeab2011-07-08 01:53:10 +0000136
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000137 /// @name Auto-generated Match Functions
138 /// {
Daniel Dunbar3483aca2010-08-11 05:24:50 +0000139
Chris Lattner0692ee62010-09-06 19:11:01 +0000140#define GET_ASSEMBLER_HEADER
141#include "ARMGenAsmMatcher.inc"
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000142
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000143 /// }
144
Jim Grosbach89df9962011-08-26 21:43:41 +0000145 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach43904292011-07-25 20:14:50 +0000146 OperandMatchResultTy parseCoprocNumOperand(
Jim Grosbachf922c472011-02-12 01:34:40 +0000147 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach43904292011-07-25 20:14:50 +0000148 OperandMatchResultTy parseCoprocRegOperand(
Jim Grosbachf922c472011-02-12 01:34:40 +0000149 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach9b8f2a02011-10-12 17:34:41 +0000150 OperandMatchResultTy parseCoprocOptionOperand(
151 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach43904292011-07-25 20:14:50 +0000152 OperandMatchResultTy parseMemBarrierOptOperand(
Bruno Cardoso Lopes8bba1a52011-02-18 19:49:06 +0000153 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach43904292011-07-25 20:14:50 +0000154 OperandMatchResultTy parseProcIFlagsOperand(
Bruno Cardoso Lopes8bba1a52011-02-18 19:49:06 +0000155 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach43904292011-07-25 20:14:50 +0000156 OperandMatchResultTy parseMSRMaskOperand(
Bruno Cardoso Lopes8bba1a52011-02-18 19:49:06 +0000157 SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbachf6c05252011-07-21 17:23:04 +0000158 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
159 StringRef Op, int Low, int High);
160 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
161 return parsePKHImm(O, "lsl", 0, 31);
162 }
163 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
164 return parsePKHImm(O, "asr", 1, 32);
165 }
Jim Grosbachc27d4f92011-07-22 17:44:50 +0000166 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach580f4a92011-07-25 22:20:28 +0000167 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach7e1547e2011-07-27 20:15:40 +0000168 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach293a2ee2011-07-28 21:34:26 +0000169 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach7ce05792011-08-03 23:50:40 +0000170 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach251bf252011-08-10 21:56:18 +0000171 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach9d390362011-10-03 23:38:36 +0000172 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach862019c2011-10-18 23:02:30 +0000173 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
Jim Grosbach7636bf62011-12-02 00:35:16 +0000174 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +0000175
176 // Asm Match Converter Methods
Jim Grosbacha77295d2011-09-08 22:07:06 +0000177 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbacheeec0252011-09-08 00:39:19 +0000181 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbachee2c2a42011-09-16 21:55:56 +0000183 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach1355cf12011-07-26 17:10:22 +0000185 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +0000186 const SmallVectorImpl<MCParsedAsmOperand*> &);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000187 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach548340c2011-08-11 19:22:40 +0000189 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach1355cf12011-07-26 17:10:22 +0000191 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +0000192 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach7b8f46c2011-08-11 21:17:22 +0000193 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
194 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach7ce05792011-08-03 23:50:40 +0000195 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
196 const SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
198 const SmallVectorImpl<MCParsedAsmOperand*> &);
199 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
200 const SmallVectorImpl<MCParsedAsmOperand*> &);
201 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
202 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000203 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
204 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach14605d12011-08-11 20:28:23 +0000205 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
206 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach623a4542011-08-10 22:42:16 +0000207 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
208 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach88ae2bc2011-08-19 22:07:46 +0000209 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
210 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach12431322011-10-24 22:16:58 +0000211 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
212 const SmallVectorImpl<MCParsedAsmOperand*> &);
213 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
214 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach4334e032011-10-31 21:50:31 +0000215 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
216 const SmallVectorImpl<MCParsedAsmOperand*> &);
217 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
218 const SmallVectorImpl<MCParsedAsmOperand*> &);
Jim Grosbach189610f2011-07-26 18:25:39 +0000219
220 bool validateInstruction(MCInst &Inst,
221 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
Jim Grosbach83ec8772011-11-10 23:42:14 +0000222 bool processInstruction(MCInst &Inst,
Jim Grosbachf8fce712011-08-11 17:35:48 +0000223 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
Jim Grosbachd54b4e62011-08-16 21:12:37 +0000224 bool shouldOmitCCOutOperand(StringRef Mnemonic,
225 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
Jim Grosbach189610f2011-07-26 18:25:39 +0000226
Kevin Enderbyca9c42c2009-09-15 00:27:25 +0000227public:
Jim Grosbach47a0d522011-08-16 20:45:50 +0000228 enum ARMMatchResultTy {
Jim Grosbach194bd892011-08-16 22:20:01 +0000229 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +0000230 Match_RequiresNotITBlock,
Jim Grosbach194bd892011-08-16 22:20:01 +0000231 Match_RequiresV6,
232 Match_RequiresThumb2
Jim Grosbach47a0d522011-08-16 20:45:50 +0000233 };
234
Evan Chengffc0e732011-07-09 05:47:46 +0000235 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
Evan Cheng94b95502011-07-26 00:24:13 +0000236 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
Evan Chengebdeeab2011-07-08 01:53:10 +0000237 MCAsmParserExtension::Initialize(_Parser);
Evan Cheng32869202011-07-08 22:36:29 +0000238
Evan Chengebdeeab2011-07-08 01:53:10 +0000239 // Initialize the set of available features.
Evan Chengffc0e732011-07-09 05:47:46 +0000240 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +0000241
242 // Not in an ITBlock to start with.
243 ITState.CurPosition = ~0U;
Evan Chengebdeeab2011-07-08 01:53:10 +0000244 }
Kevin Enderbyca9c42c2009-09-15 00:27:25 +0000245
Jim Grosbach1355cf12011-07-26 17:10:22 +0000246 // Implementation of the MCTargetAsmParser interface:
247 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
248 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
Jim Grosbach189610f2011-07-26 18:25:39 +0000249 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
Jim Grosbach1355cf12011-07-26 17:10:22 +0000250 bool ParseDirective(AsmToken DirectiveID);
251
Jim Grosbach47a0d522011-08-16 20:45:50 +0000252 unsigned checkTargetMatchPredicate(MCInst &Inst);
253
Jim Grosbach1355cf12011-07-26 17:10:22 +0000254 bool MatchAndEmitInstruction(SMLoc IDLoc,
255 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
256 MCStreamer &Out);
Kevin Enderbyca9c42c2009-09-15 00:27:25 +0000257};
Jim Grosbach16c74252010-10-29 14:46:02 +0000258} // end anonymous namespace
259
Chris Lattner3a697562010-10-28 17:20:03 +0000260namespace {
261
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000262/// ARMOperand - Instances of this class represent a parsed ARM machine
263/// instruction.
Bill Wendling146018f2010-11-06 21:42:12 +0000264class ARMOperand : public MCParsedAsmOperand {
Sean Callanan76264762010-04-02 22:27:05 +0000265 enum KindTy {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000266 k_CondCode,
267 k_CCOut,
268 k_ITCondMask,
269 k_CoprocNum,
270 k_CoprocReg,
Jim Grosbach9b8f2a02011-10-12 17:34:41 +0000271 k_CoprocOption,
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000272 k_Immediate,
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000273 k_MemBarrierOpt,
274 k_Memory,
275 k_PostIndexRegister,
276 k_MSRMask,
277 k_ProcIFlags,
Jim Grosbach460a9052011-10-07 23:56:00 +0000278 k_VectorIndex,
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000279 k_Register,
280 k_RegisterList,
281 k_DPRRegisterList,
282 k_SPRRegisterList,
Jim Grosbach862019c2011-10-18 23:02:30 +0000283 k_VectorList,
Jim Grosbach98b05a52011-11-30 01:09:44 +0000284 k_VectorListAllLanes,
Jim Grosbach7636bf62011-12-02 00:35:16 +0000285 k_VectorListIndexed,
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000286 k_ShiftedRegister,
287 k_ShiftedImmediate,
288 k_ShifterImmediate,
289 k_RotateImmediate,
290 k_BitfieldDescriptor,
291 k_Token
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000292 } Kind;
293
Sean Callanan76264762010-04-02 22:27:05 +0000294 SMLoc StartLoc, EndLoc;
Bill Wendling24d22d22010-11-18 21:50:54 +0000295 SmallVector<unsigned, 8> Registers;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000296
297 union {
298 struct {
Daniel Dunbar8462b302010-08-11 06:36:53 +0000299 ARMCC::CondCodes Val;
300 } CC;
301
302 struct {
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +0000303 unsigned Val;
304 } Cop;
305
306 struct {
Jim Grosbach9b8f2a02011-10-12 17:34:41 +0000307 unsigned Val;
308 } CoprocOption;
309
310 struct {
Jim Grosbach89df9962011-08-26 21:43:41 +0000311 unsigned Mask:4;
312 } ITMask;
313
314 struct {
315 ARM_MB::MemBOpt Val;
316 } MBOpt;
317
318 struct {
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +0000319 ARM_PROC::IFlags Val;
320 } IFlags;
321
322 struct {
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +0000323 unsigned Val;
324 } MMask;
325
326 struct {
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000327 const char *Data;
328 unsigned Length;
329 } Tok;
330
331 struct {
332 unsigned RegNum;
333 } Reg;
334
Jim Grosbach862019c2011-10-18 23:02:30 +0000335 // A vector register list is a sequential list of 1 to 4 registers.
336 struct {
337 unsigned RegNum;
338 unsigned Count;
Jim Grosbach7636bf62011-12-02 00:35:16 +0000339 unsigned LaneIndex;
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +0000340 bool isDoubleSpaced;
Jim Grosbach862019c2011-10-18 23:02:30 +0000341 } VectorList;
342
Bill Wendling8155e5b2010-11-06 22:19:43 +0000343 struct {
Jim Grosbach460a9052011-10-07 23:56:00 +0000344 unsigned Val;
345 } VectorIndex;
346
347 struct {
Kevin Enderbycfe07242009-10-13 22:19:02 +0000348 const MCExpr *Val;
349 } Imm;
Jim Grosbach16c74252010-10-29 14:46:02 +0000350
Daniel Dunbar6a5c22e2011-01-10 15:26:21 +0000351 /// Combined record for all forms of ARM address expressions.
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000352 struct {
353 unsigned BaseRegNum;
Jim Grosbach7ce05792011-08-03 23:50:40 +0000354 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
355 // was specified.
356 const MCConstantExpr *OffsetImm; // Offset immediate value
357 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
358 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
Jim Grosbach57dcb852011-10-11 17:29:55 +0000359 unsigned ShiftImm; // shift for OffsetReg.
360 unsigned Alignment; // 0 = no alignment specified
Jim Grosbacheeaf1c12011-12-19 18:31:43 +0000361 // n = alignment in bytes (2, 4, 8, 16, or 32)
Jim Grosbach7ce05792011-08-03 23:50:40 +0000362 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
Jim Grosbache53c87b2011-10-11 15:59:20 +0000363 } Memory;
Owen Anderson00828302011-03-18 22:50:18 +0000364
365 struct {
Jim Grosbach7ce05792011-08-03 23:50:40 +0000366 unsigned RegNum;
Jim Grosbachf4fa3d62011-08-05 21:28:30 +0000367 bool isAdd;
368 ARM_AM::ShiftOpc ShiftTy;
369 unsigned ShiftImm;
Jim Grosbach7ce05792011-08-03 23:50:40 +0000370 } PostIdxReg;
371
372 struct {
Jim Grosbach580f4a92011-07-25 22:20:28 +0000373 bool isASR;
Jim Grosbache8606dc2011-07-13 17:50:29 +0000374 unsigned Imm;
Jim Grosbach580f4a92011-07-25 22:20:28 +0000375 } ShifterImm;
Jim Grosbache8606dc2011-07-13 17:50:29 +0000376 struct {
377 ARM_AM::ShiftOpc ShiftTy;
378 unsigned SrcReg;
379 unsigned ShiftReg;
380 unsigned ShiftImm;
Jim Grosbachaf6981f2011-07-25 20:49:51 +0000381 } RegShiftedReg;
Owen Anderson92a20222011-07-21 18:54:16 +0000382 struct {
383 ARM_AM::ShiftOpc ShiftTy;
384 unsigned SrcReg;
385 unsigned ShiftImm;
Jim Grosbachaf6981f2011-07-25 20:49:51 +0000386 } RegShiftedImm;
Jim Grosbach7e1547e2011-07-27 20:15:40 +0000387 struct {
388 unsigned Imm;
389 } RotImm;
Jim Grosbach293a2ee2011-07-28 21:34:26 +0000390 struct {
391 unsigned LSB;
392 unsigned Width;
393 } Bitfield;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000394 };
Jim Grosbach16c74252010-10-29 14:46:02 +0000395
Bill Wendling146018f2010-11-06 21:42:12 +0000396 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
397public:
Sean Callanan76264762010-04-02 22:27:05 +0000398 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
399 Kind = o.Kind;
400 StartLoc = o.StartLoc;
401 EndLoc = o.EndLoc;
402 switch (Kind) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000403 case k_CondCode:
Daniel Dunbar8462b302010-08-11 06:36:53 +0000404 CC = o.CC;
405 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000406 case k_ITCondMask:
Jim Grosbach89df9962011-08-26 21:43:41 +0000407 ITMask = o.ITMask;
408 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000409 case k_Token:
Daniel Dunbar8462b302010-08-11 06:36:53 +0000410 Tok = o.Tok;
Sean Callanan76264762010-04-02 22:27:05 +0000411 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000412 case k_CCOut:
413 case k_Register:
Sean Callanan76264762010-04-02 22:27:05 +0000414 Reg = o.Reg;
415 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000416 case k_RegisterList:
417 case k_DPRRegisterList:
418 case k_SPRRegisterList:
Bill Wendling24d22d22010-11-18 21:50:54 +0000419 Registers = o.Registers;
Bill Wendling8d5acb72010-11-06 19:56:04 +0000420 break;
Jim Grosbach862019c2011-10-18 23:02:30 +0000421 case k_VectorList:
Jim Grosbach98b05a52011-11-30 01:09:44 +0000422 case k_VectorListAllLanes:
Jim Grosbach7636bf62011-12-02 00:35:16 +0000423 case k_VectorListIndexed:
Jim Grosbach862019c2011-10-18 23:02:30 +0000424 VectorList = o.VectorList;
425 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000426 case k_CoprocNum:
427 case k_CoprocReg:
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +0000428 Cop = o.Cop;
429 break;
Jim Grosbach9b8f2a02011-10-12 17:34:41 +0000430 case k_CoprocOption:
431 CoprocOption = o.CoprocOption;
432 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000433 case k_Immediate:
Sean Callanan76264762010-04-02 22:27:05 +0000434 Imm = o.Imm;
435 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000436 case k_MemBarrierOpt:
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +0000437 MBOpt = o.MBOpt;
438 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000439 case k_Memory:
Jim Grosbache53c87b2011-10-11 15:59:20 +0000440 Memory = o.Memory;
Sean Callanan76264762010-04-02 22:27:05 +0000441 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000442 case k_PostIndexRegister:
Jim Grosbach7ce05792011-08-03 23:50:40 +0000443 PostIdxReg = o.PostIdxReg;
444 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000445 case k_MSRMask:
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +0000446 MMask = o.MMask;
447 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000448 case k_ProcIFlags:
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +0000449 IFlags = o.IFlags;
Owen Anderson00828302011-03-18 22:50:18 +0000450 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000451 case k_ShifterImmediate:
Jim Grosbach580f4a92011-07-25 22:20:28 +0000452 ShifterImm = o.ShifterImm;
Owen Anderson00828302011-03-18 22:50:18 +0000453 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000454 case k_ShiftedRegister:
Jim Grosbachaf6981f2011-07-25 20:49:51 +0000455 RegShiftedReg = o.RegShiftedReg;
Jim Grosbache8606dc2011-07-13 17:50:29 +0000456 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000457 case k_ShiftedImmediate:
Jim Grosbachaf6981f2011-07-25 20:49:51 +0000458 RegShiftedImm = o.RegShiftedImm;
Owen Anderson92a20222011-07-21 18:54:16 +0000459 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000460 case k_RotateImmediate:
Jim Grosbach7e1547e2011-07-27 20:15:40 +0000461 RotImm = o.RotImm;
462 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000463 case k_BitfieldDescriptor:
Jim Grosbach293a2ee2011-07-28 21:34:26 +0000464 Bitfield = o.Bitfield;
465 break;
Jim Grosbach460a9052011-10-07 23:56:00 +0000466 case k_VectorIndex:
467 VectorIndex = o.VectorIndex;
468 break;
Sean Callanan76264762010-04-02 22:27:05 +0000469 }
470 }
Jim Grosbach16c74252010-10-29 14:46:02 +0000471
Sean Callanan76264762010-04-02 22:27:05 +0000472 /// getStartLoc - Get the location of the first token of this operand.
473 SMLoc getStartLoc() const { return StartLoc; }
474 /// getEndLoc - Get the location of the last token of this operand.
475 SMLoc getEndLoc() const { return EndLoc; }
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000476
Daniel Dunbar8462b302010-08-11 06:36:53 +0000477 ARMCC::CondCodes getCondCode() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000478 assert(Kind == k_CondCode && "Invalid access!");
Daniel Dunbar8462b302010-08-11 06:36:53 +0000479 return CC.Val;
480 }
481
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +0000482 unsigned getCoproc() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000483 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +0000484 return Cop.Val;
485 }
486
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000487 StringRef getToken() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000488 assert(Kind == k_Token && "Invalid access!");
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000489 return StringRef(Tok.Data, Tok.Length);
490 }
491
492 unsigned getReg() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000493 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
Bill Wendling7729e062010-11-09 22:44:22 +0000494 return Reg.RegNum;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +0000495 }
496
Bill Wendling5fa22a12010-11-09 23:28:44 +0000497 const SmallVectorImpl<unsigned> &getRegList() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000498 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
499 Kind == k_SPRRegisterList) && "Invalid access!");
Bill Wendling24d22d22010-11-18 21:50:54 +0000500 return Registers;
Bill Wendling8d5acb72010-11-06 19:56:04 +0000501 }
502
Kevin Enderbycfe07242009-10-13 22:19:02 +0000503 const MCExpr *getImm() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000504 assert(isImm() && "Invalid access!");
Kevin Enderbycfe07242009-10-13 22:19:02 +0000505 return Imm.Val;
506 }
507
Jim Grosbach460a9052011-10-07 23:56:00 +0000508 unsigned getVectorIndex() const {
509 assert(Kind == k_VectorIndex && "Invalid access!");
510 return VectorIndex.Val;
511 }
512
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +0000513 ARM_MB::MemBOpt getMemBarrierOpt() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000514 assert(Kind == k_MemBarrierOpt && "Invalid access!");
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +0000515 return MBOpt.Val;
516 }
517
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +0000518 ARM_PROC::IFlags getProcIFlags() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000519 assert(Kind == k_ProcIFlags && "Invalid access!");
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +0000520 return IFlags.Val;
521 }
522
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +0000523 unsigned getMSRMask() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000524 assert(Kind == k_MSRMask && "Invalid access!");
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +0000525 return MMask.Val;
526 }
527
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000528 bool isCoprocNum() const { return Kind == k_CoprocNum; }
529 bool isCoprocReg() const { return Kind == k_CoprocReg; }
Jim Grosbach9b8f2a02011-10-12 17:34:41 +0000530 bool isCoprocOption() const { return Kind == k_CoprocOption; }
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000531 bool isCondCode() const { return Kind == k_CondCode; }
532 bool isCCOut() const { return Kind == k_CCOut; }
533 bool isITMask() const { return Kind == k_ITCondMask; }
534 bool isITCondCode() const { return Kind == k_CondCode; }
535 bool isImm() const { return Kind == k_Immediate; }
Jim Grosbach51222d12012-01-20 18:09:51 +0000536 bool isFPImm() const {
537 if (!isImm()) return false;
538 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
539 if (!CE) return false;
540 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
541 return Val != -1;
542 }
Jim Grosbach4050bc42011-12-22 22:19:05 +0000543 bool isFBits16() const {
544 if (!isImm()) return false;
545 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
546 if (!CE) return false;
547 int64_t Value = CE->getValue();
548 return Value >= 0 && Value <= 16;
549 }
550 bool isFBits32() const {
551 if (!isImm()) return false;
552 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
553 if (!CE) return false;
554 int64_t Value = CE->getValue();
555 return Value >= 1 && Value <= 32;
556 }
Jim Grosbacha77295d2011-09-08 22:07:06 +0000557 bool isImm8s4() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000558 if (!isImm()) return false;
Jim Grosbacha77295d2011-09-08 22:07:06 +0000559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
560 if (!CE) return false;
561 int64_t Value = CE->getValue();
562 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
563 }
Jim Grosbach72f39f82011-08-24 21:22:15 +0000564 bool isImm0_1020s4() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000565 if (!isImm()) return false;
Jim Grosbach72f39f82011-08-24 21:22:15 +0000566 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
567 if (!CE) return false;
568 int64_t Value = CE->getValue();
569 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
570 }
571 bool isImm0_508s4() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000572 if (!isImm()) return false;
Jim Grosbach72f39f82011-08-24 21:22:15 +0000573 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
574 if (!CE) return false;
575 int64_t Value = CE->getValue();
576 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
577 }
Jim Grosbach6b8f1e32011-06-27 23:54:06 +0000578 bool isImm0_255() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000579 if (!isImm()) return false;
Jim Grosbach6b8f1e32011-06-27 23:54:06 +0000580 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
581 if (!CE) return false;
582 int64_t Value = CE->getValue();
583 return Value >= 0 && Value < 256;
584 }
Jim Grosbach587f5062011-12-02 23:34:39 +0000585 bool isImm0_1() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000586 if (!isImm()) return false;
Jim Grosbach587f5062011-12-02 23:34:39 +0000587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
588 if (!CE) return false;
589 int64_t Value = CE->getValue();
590 return Value >= 0 && Value < 2;
591 }
592 bool isImm0_3() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000593 if (!isImm()) return false;
Jim Grosbach587f5062011-12-02 23:34:39 +0000594 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
595 if (!CE) return false;
596 int64_t Value = CE->getValue();
597 return Value >= 0 && Value < 4;
598 }
Jim Grosbach83ab0702011-07-13 22:01:08 +0000599 bool isImm0_7() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000600 if (!isImm()) return false;
Jim Grosbach83ab0702011-07-13 22:01:08 +0000601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602 if (!CE) return false;
603 int64_t Value = CE->getValue();
604 return Value >= 0 && Value < 8;
605 }
606 bool isImm0_15() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000607 if (!isImm()) return false;
Jim Grosbach83ab0702011-07-13 22:01:08 +0000608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609 if (!CE) return false;
610 int64_t Value = CE->getValue();
611 return Value >= 0 && Value < 16;
612 }
Jim Grosbach7c6e42e2011-07-21 23:26:25 +0000613 bool isImm0_31() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000614 if (!isImm()) return false;
Jim Grosbach7c6e42e2011-07-21 23:26:25 +0000615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
616 if (!CE) return false;
617 int64_t Value = CE->getValue();
618 return Value >= 0 && Value < 32;
619 }
Jim Grosbach730fe6c2011-12-08 01:30:04 +0000620 bool isImm0_63() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000621 if (!isImm()) return false;
Jim Grosbach730fe6c2011-12-08 01:30:04 +0000622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
623 if (!CE) return false;
624 int64_t Value = CE->getValue();
625 return Value >= 0 && Value < 64;
626 }
Jim Grosbach3b8991c2011-12-07 01:07:24 +0000627 bool isImm8() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000628 if (!isImm()) return false;
Jim Grosbach3b8991c2011-12-07 01:07:24 +0000629 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
630 if (!CE) return false;
631 int64_t Value = CE->getValue();
632 return Value == 8;
633 }
634 bool isImm16() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000635 if (!isImm()) return false;
Jim Grosbach3b8991c2011-12-07 01:07:24 +0000636 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
637 if (!CE) return false;
638 int64_t Value = CE->getValue();
639 return Value == 16;
640 }
641 bool isImm32() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000642 if (!isImm()) return false;
Jim Grosbach3b8991c2011-12-07 01:07:24 +0000643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
644 if (!CE) return false;
645 int64_t Value = CE->getValue();
646 return Value == 32;
647 }
Jim Grosbach6b044c22011-12-08 22:06:06 +0000648 bool isShrImm8() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000649 if (!isImm()) return false;
Jim Grosbach6b044c22011-12-08 22:06:06 +0000650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
651 if (!CE) return false;
652 int64_t Value = CE->getValue();
653 return Value > 0 && Value <= 8;
654 }
655 bool isShrImm16() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000656 if (!isImm()) return false;
Jim Grosbach6b044c22011-12-08 22:06:06 +0000657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
658 if (!CE) return false;
659 int64_t Value = CE->getValue();
660 return Value > 0 && Value <= 16;
661 }
662 bool isShrImm32() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000663 if (!isImm()) return false;
Jim Grosbach6b044c22011-12-08 22:06:06 +0000664 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
665 if (!CE) return false;
666 int64_t Value = CE->getValue();
667 return Value > 0 && Value <= 32;
668 }
669 bool isShrImm64() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000670 if (!isImm()) return false;
Jim Grosbach6b044c22011-12-08 22:06:06 +0000671 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
672 if (!CE) return false;
673 int64_t Value = CE->getValue();
674 return Value > 0 && Value <= 64;
675 }
Jim Grosbach3b8991c2011-12-07 01:07:24 +0000676 bool isImm1_7() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000677 if (!isImm()) return false;
Jim Grosbach3b8991c2011-12-07 01:07:24 +0000678 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
679 if (!CE) return false;
680 int64_t Value = CE->getValue();
681 return Value > 0 && Value < 8;
682 }
683 bool isImm1_15() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000684 if (!isImm()) return false;
Jim Grosbach3b8991c2011-12-07 01:07:24 +0000685 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
686 if (!CE) return false;
687 int64_t Value = CE->getValue();
688 return Value > 0 && Value < 16;
689 }
690 bool isImm1_31() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000691 if (!isImm()) return false;
Jim Grosbach3b8991c2011-12-07 01:07:24 +0000692 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
693 if (!CE) return false;
694 int64_t Value = CE->getValue();
695 return Value > 0 && Value < 32;
696 }
Jim Grosbachf4943352011-07-25 23:09:14 +0000697 bool isImm1_16() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000698 if (!isImm()) return false;
Jim Grosbachf4943352011-07-25 23:09:14 +0000699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
700 if (!CE) return false;
701 int64_t Value = CE->getValue();
702 return Value > 0 && Value < 17;
703 }
Jim Grosbach4a5ffb32011-07-22 23:16:18 +0000704 bool isImm1_32() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000705 if (!isImm()) return false;
Jim Grosbach4a5ffb32011-07-22 23:16:18 +0000706 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
707 if (!CE) return false;
708 int64_t Value = CE->getValue();
709 return Value > 0 && Value < 33;
710 }
Jim Grosbachee10ff82011-11-10 19:18:01 +0000711 bool isImm0_32() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000712 if (!isImm()) return false;
Jim Grosbachee10ff82011-11-10 19:18:01 +0000713 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
714 if (!CE) return false;
715 int64_t Value = CE->getValue();
716 return Value >= 0 && Value < 33;
717 }
Jim Grosbachfff76ee2011-07-13 20:10:10 +0000718 bool isImm0_65535() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000719 if (!isImm()) return false;
Jim Grosbachfff76ee2011-07-13 20:10:10 +0000720 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
721 if (!CE) return false;
722 int64_t Value = CE->getValue();
723 return Value >= 0 && Value < 65536;
724 }
Jim Grosbachffa32252011-07-19 19:13:28 +0000725 bool isImm0_65535Expr() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000726 if (!isImm()) return false;
Jim Grosbachffa32252011-07-19 19:13:28 +0000727 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
728 // If it's not a constant expression, it'll generate a fixup and be
729 // handled later.
730 if (!CE) return true;
731 int64_t Value = CE->getValue();
732 return Value >= 0 && Value < 65536;
733 }
Jim Grosbached838482011-07-26 16:24:27 +0000734 bool isImm24bit() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000735 if (!isImm()) return false;
Jim Grosbached838482011-07-26 16:24:27 +0000736 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
737 if (!CE) return false;
738 int64_t Value = CE->getValue();
739 return Value >= 0 && Value <= 0xffffff;
740 }
Jim Grosbach70939ee2011-08-17 21:51:27 +0000741 bool isImmThumbSR() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000742 if (!isImm()) return false;
Jim Grosbach70939ee2011-08-17 21:51:27 +0000743 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
744 if (!CE) return false;
745 int64_t Value = CE->getValue();
746 return Value > 0 && Value < 33;
747 }
Jim Grosbachf6c05252011-07-21 17:23:04 +0000748 bool isPKHLSLImm() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000749 if (!isImm()) return false;
Jim Grosbachf6c05252011-07-21 17:23:04 +0000750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
751 if (!CE) return false;
752 int64_t Value = CE->getValue();
753 return Value >= 0 && Value < 32;
754 }
755 bool isPKHASRImm() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000756 if (!isImm()) return false;
Jim Grosbachf6c05252011-07-21 17:23:04 +0000757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758 if (!CE) return false;
759 int64_t Value = CE->getValue();
760 return Value > 0 && Value <= 32;
761 }
Jim Grosbach6bc1dbc2011-07-19 16:50:30 +0000762 bool isARMSOImm() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000763 if (!isImm()) return false;
Jim Grosbach6bc1dbc2011-07-19 16:50:30 +0000764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765 if (!CE) return false;
766 int64_t Value = CE->getValue();
767 return ARM_AM::getSOImmVal(Value) != -1;
768 }
Jim Grosbache70ec842011-10-28 22:50:54 +0000769 bool isARMSOImmNot() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000770 if (!isImm()) return false;
Jim Grosbache70ec842011-10-28 22:50:54 +0000771 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
772 if (!CE) return false;
773 int64_t Value = CE->getValue();
774 return ARM_AM::getSOImmVal(~Value) != -1;
775 }
Jim Grosbach3bc8a3d2011-12-08 00:31:07 +0000776 bool isARMSOImmNeg() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000777 if (!isImm()) return false;
Jim Grosbach3bc8a3d2011-12-08 00:31:07 +0000778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779 if (!CE) return false;
780 int64_t Value = CE->getValue();
781 return ARM_AM::getSOImmVal(-Value) != -1;
782 }
Jim Grosbach6b8f1e32011-06-27 23:54:06 +0000783 bool isT2SOImm() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000784 if (!isImm()) return false;
Jim Grosbach6b8f1e32011-06-27 23:54:06 +0000785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
786 if (!CE) return false;
787 int64_t Value = CE->getValue();
788 return ARM_AM::getT2SOImmVal(Value) != -1;
789 }
Jim Grosbach89a63372011-10-28 22:36:30 +0000790 bool isT2SOImmNot() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000791 if (!isImm()) return false;
Jim Grosbach89a63372011-10-28 22:36:30 +0000792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793 if (!CE) return false;
794 int64_t Value = CE->getValue();
795 return ARM_AM::getT2SOImmVal(~Value) != -1;
796 }
Jim Grosbach3bc8a3d2011-12-08 00:31:07 +0000797 bool isT2SOImmNeg() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000798 if (!isImm()) return false;
Jim Grosbach3bc8a3d2011-12-08 00:31:07 +0000799 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800 if (!CE) return false;
801 int64_t Value = CE->getValue();
802 return ARM_AM::getT2SOImmVal(-Value) != -1;
803 }
Jim Grosbachc27d4f92011-07-22 17:44:50 +0000804 bool isSetEndImm() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000805 if (!isImm()) return false;
Jim Grosbachc27d4f92011-07-22 17:44:50 +0000806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807 if (!CE) return false;
808 int64_t Value = CE->getValue();
809 return Value == 1 || Value == 0;
810 }
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000811 bool isReg() const { return Kind == k_Register; }
812 bool isRegList() const { return Kind == k_RegisterList; }
813 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
814 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
815 bool isToken() const { return Kind == k_Token; }
816 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
817 bool isMemory() const { return Kind == k_Memory; }
818 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
819 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
820 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
821 bool isRotImm() const { return Kind == k_RotateImmediate; }
822 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
823 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
Jim Grosbachf4fa3d62011-08-05 21:28:30 +0000824 bool isPostIdxReg() const {
Jim Grosbach430052b2011-11-14 17:52:47 +0000825 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
Jim Grosbachf4fa3d62011-08-05 21:28:30 +0000826 }
Jim Grosbach57dcb852011-10-11 17:29:55 +0000827 bool isMemNoOffset(bool alignOK = false) const {
Jim Grosbachf6c35c52011-10-10 23:06:42 +0000828 if (!isMemory())
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +0000829 return false;
Jim Grosbach7ce05792011-08-03 23:50:40 +0000830 // No offset of any kind.
Jim Grosbach57dcb852011-10-11 17:29:55 +0000831 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
832 (alignOK || Memory.Alignment == 0);
833 }
Jim Grosbach0b4c6732012-01-18 22:46:46 +0000834 bool isMemPCRelImm12() const {
835 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
836 return false;
837 // Base register must be PC.
838 if (Memory.BaseRegNum != ARM::PC)
839 return false;
840 // Immediate offset in range [-4095, 4095].
841 if (!Memory.OffsetImm) return true;
842 int64_t Val = Memory.OffsetImm->getValue();
843 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
844 }
Jim Grosbach57dcb852011-10-11 17:29:55 +0000845 bool isAlignedMemory() const {
846 return isMemNoOffset(true);
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +0000847 }
Jim Grosbach7ce05792011-08-03 23:50:40 +0000848 bool isAddrMode2() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +0000849 if (!isMemory() || Memory.Alignment != 0) return false;
Jim Grosbach7ce05792011-08-03 23:50:40 +0000850 // Check for register offset.
Jim Grosbache53c87b2011-10-11 15:59:20 +0000851 if (Memory.OffsetRegNum) return true;
Jim Grosbach7ce05792011-08-03 23:50:40 +0000852 // Immediate offset in range [-4095, 4095].
Jim Grosbache53c87b2011-10-11 15:59:20 +0000853 if (!Memory.OffsetImm) return true;
854 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach7ce05792011-08-03 23:50:40 +0000855 return Val > -4096 && Val < 4096;
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +0000856 }
Jim Grosbach039c2e12011-08-04 23:01:30 +0000857 bool isAM2OffsetImm() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +0000858 if (!isImm()) return false;
Jim Grosbach039c2e12011-08-04 23:01:30 +0000859 // Immediate offset in range [-4095, 4095].
860 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
861 if (!CE) return false;
862 int64_t Val = CE->getValue();
863 return Val > -4096 && Val < 4096;
864 }
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000865 bool isAddrMode3() const {
Jim Grosbach2f196742011-12-19 23:06:24 +0000866 // If we have an immediate that's not a constant, treat it as a label
867 // reference needing a fixup. If it is a constant, it's something else
868 // and we reject it.
Jim Grosbach21bcca82011-12-22 22:02:35 +0000869 if (isImm() && !isa<MCConstantExpr>(getImm()))
Jim Grosbach2f196742011-12-19 23:06:24 +0000870 return true;
Jim Grosbach57dcb852011-10-11 17:29:55 +0000871 if (!isMemory() || Memory.Alignment != 0) return false;
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000872 // No shifts are legal for AM3.
Jim Grosbache53c87b2011-10-11 15:59:20 +0000873 if (Memory.ShiftType != ARM_AM::no_shift) return false;
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000874 // Check for register offset.
Jim Grosbache53c87b2011-10-11 15:59:20 +0000875 if (Memory.OffsetRegNum) return true;
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000876 // Immediate offset in range [-255, 255].
Jim Grosbache53c87b2011-10-11 15:59:20 +0000877 if (!Memory.OffsetImm) return true;
878 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000879 return Val > -256 && Val < 256;
880 }
881 bool isAM3Offset() const {
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000882 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000883 return false;
Jim Grosbach21ff17c2011-10-07 23:24:09 +0000884 if (Kind == k_PostIndexRegister)
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000885 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
886 // Immediate offset in range [-255, 255].
887 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
888 if (!CE) return false;
889 int64_t Val = CE->getValue();
Jim Grosbach251bf252011-08-10 21:56:18 +0000890 // Special case, #-0 is INT32_MIN.
891 return (Val > -256 && Val < 256) || Val == INT32_MIN;
Jim Grosbach2fd2b872011-08-10 20:29:19 +0000892 }
Jim Grosbach7ce05792011-08-03 23:50:40 +0000893 bool isAddrMode5() const {
Jim Grosbach681460f2011-11-01 01:24:45 +0000894 // If we have an immediate that's not a constant, treat it as a label
895 // reference needing a fixup. If it is a constant, it's something else
896 // and we reject it.
Jim Grosbach21bcca82011-12-22 22:02:35 +0000897 if (isImm() && !isa<MCConstantExpr>(getImm()))
Jim Grosbach681460f2011-11-01 01:24:45 +0000898 return true;
Jim Grosbach57dcb852011-10-11 17:29:55 +0000899 if (!isMemory() || Memory.Alignment != 0) return false;
Jim Grosbach7ce05792011-08-03 23:50:40 +0000900 // Check for register offset.
Jim Grosbache53c87b2011-10-11 15:59:20 +0000901 if (Memory.OffsetRegNum) return false;
Jim Grosbach7ce05792011-08-03 23:50:40 +0000902 // Immediate offset in range [-1020, 1020] and a multiple of 4.
Jim Grosbache53c87b2011-10-11 15:59:20 +0000903 if (!Memory.OffsetImm) return true;
904 int64_t Val = Memory.OffsetImm->getValue();
Owen Anderson0da10cf2011-08-29 19:36:44 +0000905 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
Jim Grosbach681460f2011-11-01 01:24:45 +0000906 Val == INT32_MIN;
Bill Wendling87f4f9a2010-11-08 23:49:57 +0000907 }
Jim Grosbach7f739be2011-09-19 22:21:13 +0000908 bool isMemTBB() const {
Jim Grosbache53c87b2011-10-11 15:59:20 +0000909 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
Jim Grosbach57dcb852011-10-11 17:29:55 +0000910 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
Jim Grosbach7f739be2011-09-19 22:21:13 +0000911 return false;
912 return true;
913 }
914 bool isMemTBH() const {
Jim Grosbache53c87b2011-10-11 15:59:20 +0000915 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
Jim Grosbach57dcb852011-10-11 17:29:55 +0000916 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
917 Memory.Alignment != 0 )
Jim Grosbach7f739be2011-09-19 22:21:13 +0000918 return false;
919 return true;
920 }
Jim Grosbach7ce05792011-08-03 23:50:40 +0000921 bool isMemRegOffset() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +0000922 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
Bill Wendlingf4caf692010-12-14 03:36:38 +0000923 return false;
Daniel Dunbard3df5f32011-01-18 05:34:11 +0000924 return true;
Bill Wendlingf4caf692010-12-14 03:36:38 +0000925 }
Jim Grosbachab899c12011-09-07 23:10:15 +0000926 bool isT2MemRegOffset() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +0000927 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
928 Memory.Alignment != 0)
Jim Grosbachab899c12011-09-07 23:10:15 +0000929 return false;
930 // Only lsl #{0, 1, 2, 3} allowed.
Jim Grosbache53c87b2011-10-11 15:59:20 +0000931 if (Memory.ShiftType == ARM_AM::no_shift)
Jim Grosbachab899c12011-09-07 23:10:15 +0000932 return true;
Jim Grosbache53c87b2011-10-11 15:59:20 +0000933 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
Jim Grosbachab899c12011-09-07 23:10:15 +0000934 return false;
935 return true;
936 }
Jim Grosbach7ce05792011-08-03 23:50:40 +0000937 bool isMemThumbRR() const {
938 // Thumb reg+reg addressing is simple. Just two registers, a base and
939 // an offset. No shifts, negations or any other complicating factors.
Jim Grosbache53c87b2011-10-11 15:59:20 +0000940 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
Jim Grosbach57dcb852011-10-11 17:29:55 +0000941 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
Bill Wendlingef4a68b2010-11-30 07:44:32 +0000942 return false;
Jim Grosbache53c87b2011-10-11 15:59:20 +0000943 return isARMLowRegister(Memory.BaseRegNum) &&
944 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
Jim Grosbach60f91a32011-08-19 17:55:24 +0000945 }
946 bool isMemThumbRIs4() const {
Jim Grosbache53c87b2011-10-11 15:59:20 +0000947 if (!isMemory() || Memory.OffsetRegNum != 0 ||
Jim Grosbach57dcb852011-10-11 17:29:55 +0000948 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
Jim Grosbach60f91a32011-08-19 17:55:24 +0000949 return false;
950 // Immediate offset, multiple of 4 in range [0, 124].
Jim Grosbache53c87b2011-10-11 15:59:20 +0000951 if (!Memory.OffsetImm) return true;
952 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbachecd85892011-08-19 18:13:48 +0000953 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
954 }
Jim Grosbach38466302011-08-19 18:55:51 +0000955 bool isMemThumbRIs2() const {
Jim Grosbache53c87b2011-10-11 15:59:20 +0000956 if (!isMemory() || Memory.OffsetRegNum != 0 ||
Jim Grosbach57dcb852011-10-11 17:29:55 +0000957 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
Jim Grosbach38466302011-08-19 18:55:51 +0000958 return false;
959 // Immediate offset, multiple of 4 in range [0, 62].
Jim Grosbache53c87b2011-10-11 15:59:20 +0000960 if (!Memory.OffsetImm) return true;
961 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach38466302011-08-19 18:55:51 +0000962 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
963 }
Jim Grosbach48ff5ff2011-08-19 18:49:59 +0000964 bool isMemThumbRIs1() const {
Jim Grosbache53c87b2011-10-11 15:59:20 +0000965 if (!isMemory() || Memory.OffsetRegNum != 0 ||
Jim Grosbach57dcb852011-10-11 17:29:55 +0000966 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
Jim Grosbach48ff5ff2011-08-19 18:49:59 +0000967 return false;
968 // Immediate offset in range [0, 31].
Jim Grosbache53c87b2011-10-11 15:59:20 +0000969 if (!Memory.OffsetImm) return true;
970 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbach48ff5ff2011-08-19 18:49:59 +0000971 return Val >= 0 && Val <= 31;
972 }
Jim Grosbachecd85892011-08-19 18:13:48 +0000973 bool isMemThumbSPI() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +0000974 if (!isMemory() || Memory.OffsetRegNum != 0 ||
975 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
Jim Grosbachecd85892011-08-19 18:13:48 +0000976 return false;
977 // Immediate offset, multiple of 4 in range [0, 1020].
Jim Grosbache53c87b2011-10-11 15:59:20 +0000978 if (!Memory.OffsetImm) return true;
979 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbachecd85892011-08-19 18:13:48 +0000980 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
Bill Wendlingef4a68b2010-11-30 07:44:32 +0000981 }
Jim Grosbacha77295d2011-09-08 22:07:06 +0000982 bool isMemImm8s4Offset() const {
Jim Grosbach2f196742011-12-19 23:06:24 +0000983 // If we have an immediate that's not a constant, treat it as a label
984 // reference needing a fixup. If it is a constant, it's something else
985 // and we reject it.
Jim Grosbach21bcca82011-12-22 22:02:35 +0000986 if (isImm() && !isa<MCConstantExpr>(getImm()))
Jim Grosbach2f196742011-12-19 23:06:24 +0000987 return true;
Jim Grosbach57dcb852011-10-11 17:29:55 +0000988 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbacha77295d2011-09-08 22:07:06 +0000989 return false;
990 // Immediate offset a multiple of 4 in range [-1020, 1020].
Jim Grosbache53c87b2011-10-11 15:59:20 +0000991 if (!Memory.OffsetImm) return true;
992 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbacha77295d2011-09-08 22:07:06 +0000993 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
994 }
Jim Grosbachb6aed502011-09-09 18:37:27 +0000995 bool isMemImm0_1020s4Offset() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +0000996 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbachb6aed502011-09-09 18:37:27 +0000997 return false;
998 // Immediate offset a multiple of 4 in range [0, 1020].
Jim Grosbache53c87b2011-10-11 15:59:20 +0000999 if (!Memory.OffsetImm) return true;
1000 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbachb6aed502011-09-09 18:37:27 +00001001 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1002 }
Jim Grosbach7ce05792011-08-03 23:50:40 +00001003 bool isMemImm8Offset() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +00001004 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbach7ce05792011-08-03 23:50:40 +00001005 return false;
Jim Grosbach0b4c6732012-01-18 22:46:46 +00001006 // Base reg of PC isn't allowed for these encodings.
1007 if (Memory.BaseRegNum == ARM::PC) return false;
Jim Grosbach7ce05792011-08-03 23:50:40 +00001008 // Immediate offset in range [-255, 255].
Jim Grosbache53c87b2011-10-11 15:59:20 +00001009 if (!Memory.OffsetImm) return true;
1010 int64_t Val = Memory.OffsetImm->getValue();
Owen Anderson4d2a0012011-09-23 22:25:02 +00001011 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
Jim Grosbach7ce05792011-08-03 23:50:40 +00001012 }
Jim Grosbachf0eee6e2011-09-07 23:39:14 +00001013 bool isMemPosImm8Offset() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +00001014 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbachf0eee6e2011-09-07 23:39:14 +00001015 return false;
1016 // Immediate offset in range [0, 255].
Jim Grosbache53c87b2011-10-11 15:59:20 +00001017 if (!Memory.OffsetImm) return true;
1018 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbachf0eee6e2011-09-07 23:39:14 +00001019 return Val >= 0 && Val < 256;
1020 }
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001021 bool isMemNegImm8Offset() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +00001022 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001023 return false;
Jim Grosbach0b4c6732012-01-18 22:46:46 +00001024 // Base reg of PC isn't allowed for these encodings.
1025 if (Memory.BaseRegNum == ARM::PC) return false;
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001026 // Immediate offset in range [-255, -1].
Jim Grosbachdf33e0d2011-12-06 04:49:29 +00001027 if (!Memory.OffsetImm) return false;
Jim Grosbache53c87b2011-10-11 15:59:20 +00001028 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbachdf33e0d2011-12-06 04:49:29 +00001029 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001030 }
1031 bool isMemUImm12Offset() const {
Jim Grosbach57dcb852011-10-11 17:29:55 +00001032 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001033 return false;
1034 // Immediate offset in range [0, 4095].
Jim Grosbache53c87b2011-10-11 15:59:20 +00001035 if (!Memory.OffsetImm) return true;
1036 int64_t Val = Memory.OffsetImm->getValue();
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001037 return (Val >= 0 && Val < 4096);
1038 }
Jim Grosbach7ce05792011-08-03 23:50:40 +00001039 bool isMemImm12Offset() const {
Jim Grosbach09176e12011-08-08 20:59:31 +00001040 // If we have an immediate that's not a constant, treat it as a label
1041 // reference needing a fixup. If it is a constant, it's something else
1042 // and we reject it.
Jim Grosbach21bcca82011-12-22 22:02:35 +00001043 if (isImm() && !isa<MCConstantExpr>(getImm()))
Jim Grosbach09176e12011-08-08 20:59:31 +00001044 return true;
1045
Jim Grosbach57dcb852011-10-11 17:29:55 +00001046 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
Jim Grosbach7ce05792011-08-03 23:50:40 +00001047 return false;
1048 // Immediate offset in range [-4095, 4095].
Jim Grosbache53c87b2011-10-11 15:59:20 +00001049 if (!Memory.OffsetImm) return true;
1050 int64_t Val = Memory.OffsetImm->getValue();
Owen Anderson0da10cf2011-08-29 19:36:44 +00001051 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
Jim Grosbach7ce05792011-08-03 23:50:40 +00001052 }
1053 bool isPostIdxImm8() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +00001054 if (!isImm()) return false;
Jim Grosbach7ce05792011-08-03 23:50:40 +00001055 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1056 if (!CE) return false;
1057 int64_t Val = CE->getValue();
Owen Anderson63553c72011-08-29 17:17:09 +00001058 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
Jim Grosbach7ce05792011-08-03 23:50:40 +00001059 }
Jim Grosbach2bd01182011-10-11 21:55:36 +00001060 bool isPostIdxImm8s4() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +00001061 if (!isImm()) return false;
Jim Grosbach2bd01182011-10-11 21:55:36 +00001062 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1063 if (!CE) return false;
1064 int64_t Val = CE->getValue();
1065 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1066 (Val == INT32_MIN);
1067 }
Jim Grosbach7ce05792011-08-03 23:50:40 +00001068
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001069 bool isMSRMask() const { return Kind == k_MSRMask; }
1070 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
Daniel Dunbar3483aca2010-08-11 05:24:50 +00001071
Jim Grosbach0e387b22011-10-17 22:26:03 +00001072 // NEON operands.
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00001073 bool isSingleSpacedVectorList() const {
1074 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1075 }
1076 bool isDoubleSpacedVectorList() const {
1077 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1078 }
Jim Grosbach862019c2011-10-18 23:02:30 +00001079 bool isVecListOneD() const {
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00001080 if (!isSingleSpacedVectorList()) return false;
Jim Grosbach862019c2011-10-18 23:02:30 +00001081 return VectorList.Count == 1;
1082 }
1083
Jim Grosbach280dfad2011-10-21 18:54:25 +00001084 bool isVecListTwoD() const {
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00001085 if (!isSingleSpacedVectorList()) return false;
Jim Grosbach280dfad2011-10-21 18:54:25 +00001086 return VectorList.Count == 2;
1087 }
1088
Jim Grosbachcdcfa282011-10-21 20:02:19 +00001089 bool isVecListThreeD() const {
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00001090 if (!isSingleSpacedVectorList()) return false;
Jim Grosbachcdcfa282011-10-21 20:02:19 +00001091 return VectorList.Count == 3;
1092 }
1093
Jim Grosbachb6310312011-10-21 20:35:01 +00001094 bool isVecListFourD() const {
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00001095 if (!isSingleSpacedVectorList()) return false;
Jim Grosbachb6310312011-10-21 20:35:01 +00001096 return VectorList.Count == 4;
1097 }
1098
Jim Grosbach4661d4c2011-10-21 22:21:10 +00001099 bool isVecListTwoQ() const {
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00001100 if (!isDoubleSpacedVectorList()) return false;
1101 return VectorList.Count == 2;
Jim Grosbach4661d4c2011-10-21 22:21:10 +00001102 }
1103
Jim Grosbach3471d4f2011-12-21 00:38:54 +00001104 bool isSingleSpacedVectorAllLanes() const {
1105 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1106 }
1107 bool isDoubleSpacedVectorAllLanes() const {
1108 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1109 }
Jim Grosbach98b05a52011-11-30 01:09:44 +00001110 bool isVecListOneDAllLanes() const {
Jim Grosbach3471d4f2011-12-21 00:38:54 +00001111 if (!isSingleSpacedVectorAllLanes()) return false;
Jim Grosbach98b05a52011-11-30 01:09:44 +00001112 return VectorList.Count == 1;
1113 }
1114
Jim Grosbach13af2222011-11-30 18:21:25 +00001115 bool isVecListTwoDAllLanes() const {
Jim Grosbach3471d4f2011-12-21 00:38:54 +00001116 if (!isSingleSpacedVectorAllLanes()) return false;
1117 return VectorList.Count == 2;
1118 }
1119
1120 bool isVecListTwoQAllLanes() const {
1121 if (!isDoubleSpacedVectorAllLanes()) return false;
Jim Grosbach13af2222011-11-30 18:21:25 +00001122 return VectorList.Count == 2;
1123 }
1124
Jim Grosbach95fad1c2011-12-20 19:21:26 +00001125 bool isSingleSpacedVectorIndexed() const {
1126 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1127 }
1128 bool isDoubleSpacedVectorIndexed() const {
1129 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1130 }
Jim Grosbach7636bf62011-12-02 00:35:16 +00001131 bool isVecListOneDByteIndexed() const {
Jim Grosbach95fad1c2011-12-20 19:21:26 +00001132 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbach7636bf62011-12-02 00:35:16 +00001133 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1134 }
1135
Jim Grosbach799ca9d2011-12-14 23:35:06 +00001136 bool isVecListOneDHWordIndexed() const {
Jim Grosbach95fad1c2011-12-20 19:21:26 +00001137 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbach799ca9d2011-12-14 23:35:06 +00001138 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1139 }
1140
1141 bool isVecListOneDWordIndexed() const {
Jim Grosbach95fad1c2011-12-20 19:21:26 +00001142 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbach799ca9d2011-12-14 23:35:06 +00001143 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1144 }
1145
Jim Grosbach9b1b3902011-12-14 23:25:46 +00001146 bool isVecListTwoDByteIndexed() const {
Jim Grosbach95fad1c2011-12-20 19:21:26 +00001147 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00001148 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1149 }
1150
Jim Grosbach799ca9d2011-12-14 23:35:06 +00001151 bool isVecListTwoDHWordIndexed() const {
Jim Grosbach95fad1c2011-12-20 19:21:26 +00001152 if (!isSingleSpacedVectorIndexed()) return false;
1153 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1154 }
1155
1156 bool isVecListTwoQWordIndexed() const {
1157 if (!isDoubleSpacedVectorIndexed()) return false;
1158 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1159 }
1160
1161 bool isVecListTwoQHWordIndexed() const {
1162 if (!isDoubleSpacedVectorIndexed()) return false;
Jim Grosbach799ca9d2011-12-14 23:35:06 +00001163 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1164 }
1165
1166 bool isVecListTwoDWordIndexed() const {
Jim Grosbach95fad1c2011-12-20 19:21:26 +00001167 if (!isSingleSpacedVectorIndexed()) return false;
Jim Grosbach799ca9d2011-12-14 23:35:06 +00001168 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1169 }
1170
Jim Grosbach460a9052011-10-07 23:56:00 +00001171 bool isVectorIndex8() const {
1172 if (Kind != k_VectorIndex) return false;
1173 return VectorIndex.Val < 8;
1174 }
1175 bool isVectorIndex16() const {
1176 if (Kind != k_VectorIndex) return false;
1177 return VectorIndex.Val < 4;
1178 }
1179 bool isVectorIndex32() const {
1180 if (Kind != k_VectorIndex) return false;
1181 return VectorIndex.Val < 2;
1182 }
1183
Jim Grosbach0e387b22011-10-17 22:26:03 +00001184 bool isNEONi8splat() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +00001185 if (!isImm()) return false;
Jim Grosbach0e387b22011-10-17 22:26:03 +00001186 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1187 // Must be a constant.
1188 if (!CE) return false;
1189 int64_t Value = CE->getValue();
1190 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1191 // value.
Jim Grosbach0e387b22011-10-17 22:26:03 +00001192 return Value >= 0 && Value < 256;
1193 }
Jim Grosbach460a9052011-10-07 23:56:00 +00001194
Jim Grosbachea461102011-10-17 23:09:09 +00001195 bool isNEONi16splat() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +00001196 if (!isImm()) return false;
Jim Grosbachea461102011-10-17 23:09:09 +00001197 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1198 // Must be a constant.
1199 if (!CE) return false;
1200 int64_t Value = CE->getValue();
1201 // i16 value in the range [0,255] or [0x0100, 0xff00]
1202 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1203 }
1204
Jim Grosbach6248a542011-10-18 00:22:00 +00001205 bool isNEONi32splat() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +00001206 if (!isImm()) return false;
Jim Grosbach6248a542011-10-18 00:22:00 +00001207 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1208 // Must be a constant.
1209 if (!CE) return false;
1210 int64_t Value = CE->getValue();
1211 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1212 return (Value >= 0 && Value < 256) ||
1213 (Value >= 0x0100 && Value <= 0xff00) ||
1214 (Value >= 0x010000 && Value <= 0xff0000) ||
1215 (Value >= 0x01000000 && Value <= 0xff000000);
1216 }
1217
1218 bool isNEONi32vmov() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +00001219 if (!isImm()) return false;
Jim Grosbach6248a542011-10-18 00:22:00 +00001220 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1221 // Must be a constant.
1222 if (!CE) return false;
1223 int64_t Value = CE->getValue();
1224 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1225 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1226 return (Value >= 0 && Value < 256) ||
1227 (Value >= 0x0100 && Value <= 0xff00) ||
1228 (Value >= 0x010000 && Value <= 0xff0000) ||
1229 (Value >= 0x01000000 && Value <= 0xff000000) ||
1230 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1231 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1232 }
Jim Grosbach9b087852011-12-19 23:51:07 +00001233 bool isNEONi32vmovNeg() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +00001234 if (!isImm()) return false;
Jim Grosbach9b087852011-12-19 23:51:07 +00001235 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1236 // Must be a constant.
1237 if (!CE) return false;
1238 int64_t Value = ~CE->getValue();
1239 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1240 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1241 return (Value >= 0 && Value < 256) ||
1242 (Value >= 0x0100 && Value <= 0xff00) ||
1243 (Value >= 0x010000 && Value <= 0xff0000) ||
1244 (Value >= 0x01000000 && Value <= 0xff000000) ||
1245 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1246 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1247 }
Jim Grosbach6248a542011-10-18 00:22:00 +00001248
Jim Grosbachf2f5bc62011-10-18 16:18:11 +00001249 bool isNEONi64splat() const {
Jim Grosbach21bcca82011-12-22 22:02:35 +00001250 if (!isImm()) return false;
Jim Grosbachf2f5bc62011-10-18 16:18:11 +00001251 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1252 // Must be a constant.
1253 if (!CE) return false;
1254 uint64_t Value = CE->getValue();
1255 // i64 value with each byte being either 0 or 0xff.
1256 for (unsigned i = 0; i < 8; ++i)
1257 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1258 return true;
1259 }
1260
Daniel Dunbar3483aca2010-08-11 05:24:50 +00001261 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
Chris Lattner14b93852010-10-29 00:27:31 +00001262 // Add as immediates when possible. Null MCExpr = 0.
1263 if (Expr == 0)
1264 Inst.addOperand(MCOperand::CreateImm(0));
1265 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
Daniel Dunbar3483aca2010-08-11 05:24:50 +00001266 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1267 else
1268 Inst.addOperand(MCOperand::CreateExpr(Expr));
1269 }
1270
Daniel Dunbar8462b302010-08-11 06:36:53 +00001271 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
Daniel Dunbar345a9a62010-08-11 06:37:20 +00001272 assert(N == 2 && "Invalid number of operands!");
Daniel Dunbar8462b302010-08-11 06:36:53 +00001273 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
Jim Grosbach04f74942010-12-06 18:30:57 +00001274 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1275 Inst.addOperand(MCOperand::CreateReg(RegNum));
Daniel Dunbar8462b302010-08-11 06:36:53 +00001276 }
1277
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00001278 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1279 assert(N == 1 && "Invalid number of operands!");
1280 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1281 }
1282
Jim Grosbach9b8f2a02011-10-12 17:34:41 +00001283 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1284 assert(N == 1 && "Invalid number of operands!");
1285 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1286 }
1287
1288 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1289 assert(N == 1 && "Invalid number of operands!");
1290 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1291 }
1292
Jim Grosbach89df9962011-08-26 21:43:41 +00001293 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1294 assert(N == 1 && "Invalid number of operands!");
1295 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1296 }
1297
1298 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1299 assert(N == 1 && "Invalid number of operands!");
1300 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1301 }
1302
Jim Grosbachd67641b2010-12-06 18:21:12 +00001303 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1304 assert(N == 1 && "Invalid number of operands!");
1305 Inst.addOperand(MCOperand::CreateReg(getReg()));
1306 }
1307
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00001308 void addRegOperands(MCInst &Inst, unsigned N) const {
1309 assert(N == 1 && "Invalid number of operands!");
1310 Inst.addOperand(MCOperand::CreateReg(getReg()));
1311 }
1312
Jim Grosbachaf6981f2011-07-25 20:49:51 +00001313 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
Jim Grosbache8606dc2011-07-13 17:50:29 +00001314 assert(N == 3 && "Invalid number of operands!");
Jim Grosbach430052b2011-11-14 17:52:47 +00001315 assert(isRegShiftedReg() &&
1316 "addRegShiftedRegOperands() on non RegShiftedReg!");
Jim Grosbachaf6981f2011-07-25 20:49:51 +00001317 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1318 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
Jim Grosbache8606dc2011-07-13 17:50:29 +00001319 Inst.addOperand(MCOperand::CreateImm(
Jim Grosbachaf6981f2011-07-25 20:49:51 +00001320 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
Jim Grosbache8606dc2011-07-13 17:50:29 +00001321 }
1322
Jim Grosbachaf6981f2011-07-25 20:49:51 +00001323 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
Owen Anderson152d4a42011-07-21 23:38:37 +00001324 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach430052b2011-11-14 17:52:47 +00001325 assert(isRegShiftedImm() &&
1326 "addRegShiftedImmOperands() on non RegShiftedImm!");
Jim Grosbachaf6981f2011-07-25 20:49:51 +00001327 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
Owen Anderson92a20222011-07-21 18:54:16 +00001328 Inst.addOperand(MCOperand::CreateImm(
Jim Grosbachaf6981f2011-07-25 20:49:51 +00001329 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
Owen Anderson92a20222011-07-21 18:54:16 +00001330 }
1331
Jim Grosbach580f4a92011-07-25 22:20:28 +00001332 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
Owen Anderson00828302011-03-18 22:50:18 +00001333 assert(N == 1 && "Invalid number of operands!");
Jim Grosbach580f4a92011-07-25 22:20:28 +00001334 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1335 ShifterImm.Imm));
Owen Anderson00828302011-03-18 22:50:18 +00001336 }
1337
Bill Wendling87f4f9a2010-11-08 23:49:57 +00001338 void addRegListOperands(MCInst &Inst, unsigned N) const {
Bill Wendling7729e062010-11-09 22:44:22 +00001339 assert(N == 1 && "Invalid number of operands!");
Bill Wendling5fa22a12010-11-09 23:28:44 +00001340 const SmallVectorImpl<unsigned> &RegList = getRegList();
1341 for (SmallVectorImpl<unsigned>::const_iterator
Bill Wendling7729e062010-11-09 22:44:22 +00001342 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1343 Inst.addOperand(MCOperand::CreateReg(*I));
Bill Wendling87f4f9a2010-11-08 23:49:57 +00001344 }
1345
Bill Wendling0f630752010-11-17 04:32:08 +00001346 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1347 addRegListOperands(Inst, N);
1348 }
1349
1350 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1351 addRegListOperands(Inst, N);
1352 }
1353
Jim Grosbach7e1547e2011-07-27 20:15:40 +00001354 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1355 assert(N == 1 && "Invalid number of operands!");
1356 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1357 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1358 }
1359
Jim Grosbach293a2ee2011-07-28 21:34:26 +00001360 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1361 assert(N == 1 && "Invalid number of operands!");
1362 // Munge the lsb/width into a bitfield mask.
1363 unsigned lsb = Bitfield.LSB;
1364 unsigned width = Bitfield.Width;
1365 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1366 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1367 (32 - (lsb + width)));
1368 Inst.addOperand(MCOperand::CreateImm(Mask));
1369 }
1370
Daniel Dunbar3483aca2010-08-11 05:24:50 +00001371 void addImmOperands(MCInst &Inst, unsigned N) const {
1372 assert(N == 1 && "Invalid number of operands!");
1373 addExpr(Inst, getImm());
1374 }
Jim Grosbach16c74252010-10-29 14:46:02 +00001375
Jim Grosbach4050bc42011-12-22 22:19:05 +00001376 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1377 assert(N == 1 && "Invalid number of operands!");
1378 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1379 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1380 }
1381
1382 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1383 assert(N == 1 && "Invalid number of operands!");
1384 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1385 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1386 }
1387
Jim Grosbach9d390362011-10-03 23:38:36 +00001388 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1389 assert(N == 1 && "Invalid number of operands!");
Jim Grosbach51222d12012-01-20 18:09:51 +00001390 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1391 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1392 Inst.addOperand(MCOperand::CreateImm(Val));
Jim Grosbach9d390362011-10-03 23:38:36 +00001393 }
1394
Jim Grosbacha77295d2011-09-08 22:07:06 +00001395 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1396 assert(N == 1 && "Invalid number of operands!");
1397 // FIXME: We really want to scale the value here, but the LDRD/STRD
1398 // instruction don't encode operands that way yet.
1399 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1400 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1401 }
1402
Jim Grosbach72f39f82011-08-24 21:22:15 +00001403 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1404 assert(N == 1 && "Invalid number of operands!");
1405 // The immediate is scaled by four in the encoding and is stored
1406 // in the MCInst as such. Lop off the low two bits here.
1407 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1408 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1409 }
1410
1411 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1412 assert(N == 1 && "Invalid number of operands!");
1413 // The immediate is scaled by four in the encoding and is stored
1414 // in the MCInst as such. Lop off the low two bits here.
1415 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1416 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1417 }
1418
Jim Grosbachf4943352011-07-25 23:09:14 +00001419 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1420 assert(N == 1 && "Invalid number of operands!");
1421 // The constant encodes as the immediate-1, and we store in the instruction
1422 // the bits as encoded, so subtract off one here.
1423 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1424 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1425 }
1426
Jim Grosbach4a5ffb32011-07-22 23:16:18 +00001427 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1428 assert(N == 1 && "Invalid number of operands!");
1429 // The constant encodes as the immediate-1, and we store in the instruction
1430 // the bits as encoded, so subtract off one here.
1431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1432 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1433 }
1434
Jim Grosbach70939ee2011-08-17 21:51:27 +00001435 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1436 assert(N == 1 && "Invalid number of operands!");
1437 // The constant encodes as the immediate, except for 32, which encodes as
1438 // zero.
1439 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1440 unsigned Imm = CE->getValue();
1441 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1442 }
1443
Jim Grosbachf6c05252011-07-21 17:23:04 +00001444 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1445 assert(N == 1 && "Invalid number of operands!");
1446 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1447 // the instruction as well.
1448 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1449 int Val = CE->getValue();
1450 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1451 }
1452
Jim Grosbach89a63372011-10-28 22:36:30 +00001453 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1454 assert(N == 1 && "Invalid number of operands!");
1455 // The operand is actually a t2_so_imm, but we have its bitwise
1456 // negation in the assembly source, so twiddle it here.
1457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1458 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1459 }
1460
Jim Grosbach3bc8a3d2011-12-08 00:31:07 +00001461 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1462 assert(N == 1 && "Invalid number of operands!");
1463 // The operand is actually a t2_so_imm, but we have its
1464 // negation in the assembly source, so twiddle it here.
1465 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1466 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1467 }
1468
Jim Grosbache70ec842011-10-28 22:50:54 +00001469 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1470 assert(N == 1 && "Invalid number of operands!");
1471 // The operand is actually a so_imm, but we have its bitwise
1472 // negation in the assembly source, so twiddle it here.
1473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1474 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1475 }
1476
Jim Grosbach3bc8a3d2011-12-08 00:31:07 +00001477 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1478 assert(N == 1 && "Invalid number of operands!");
1479 // The operand is actually a so_imm, but we have its
1480 // negation in the assembly source, so twiddle it here.
1481 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1482 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1483 }
1484
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00001485 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1486 assert(N == 1 && "Invalid number of operands!");
1487 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1488 }
1489
Jim Grosbach7ce05792011-08-03 23:50:40 +00001490 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1491 assert(N == 1 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001492 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Bruno Cardoso Lopes505f3cd2011-03-24 21:04:58 +00001493 }
1494
Jim Grosbach0b4c6732012-01-18 22:46:46 +00001495 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1496 assert(N == 1 && "Invalid number of operands!");
1497 int32_t Imm = Memory.OffsetImm->getValue();
1498 // FIXME: Handle #-0
1499 if (Imm == INT32_MIN) Imm = 0;
1500 Inst.addOperand(MCOperand::CreateImm(Imm));
1501 }
1502
Jim Grosbach57dcb852011-10-11 17:29:55 +00001503 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1504 assert(N == 2 && "Invalid number of operands!");
1505 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1506 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1507 }
1508
Jim Grosbach7ce05792011-08-03 23:50:40 +00001509 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1510 assert(N == 3 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001511 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1512 if (!Memory.OffsetRegNum) {
Jim Grosbach7ce05792011-08-03 23:50:40 +00001513 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1514 // Special case for #-0
1515 if (Val == INT32_MIN) Val = 0;
1516 if (Val < 0) Val = -Val;
1517 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1518 } else {
1519 // For register offset, we encode the shift type and negation flag
1520 // here.
Jim Grosbache53c87b2011-10-11 15:59:20 +00001521 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1522 Memory.ShiftImm, Memory.ShiftType);
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00001523 }
Jim Grosbache53c87b2011-10-11 15:59:20 +00001524 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1525 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach7ce05792011-08-03 23:50:40 +00001526 Inst.addOperand(MCOperand::CreateImm(Val));
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00001527 }
1528
Jim Grosbach039c2e12011-08-04 23:01:30 +00001529 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1530 assert(N == 2 && "Invalid number of operands!");
1531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1532 assert(CE && "non-constant AM2OffsetImm operand!");
1533 int32_t Val = CE->getValue();
1534 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1535 // Special case for #-0
1536 if (Val == INT32_MIN) Val = 0;
1537 if (Val < 0) Val = -Val;
1538 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1539 Inst.addOperand(MCOperand::CreateReg(0));
1540 Inst.addOperand(MCOperand::CreateImm(Val));
1541 }
1542
Jim Grosbach2fd2b872011-08-10 20:29:19 +00001543 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1544 assert(N == 3 && "Invalid number of operands!");
Jim Grosbach2f196742011-12-19 23:06:24 +00001545 // If we have an immediate that's not a constant, treat it as a label
1546 // reference needing a fixup. If it is a constant, it's something else
1547 // and we reject it.
1548 if (isImm()) {
1549 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1550 Inst.addOperand(MCOperand::CreateReg(0));
1551 Inst.addOperand(MCOperand::CreateImm(0));
1552 return;
1553 }
1554
Jim Grosbache53c87b2011-10-11 15:59:20 +00001555 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1556 if (!Memory.OffsetRegNum) {
Jim Grosbach2fd2b872011-08-10 20:29:19 +00001557 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1558 // Special case for #-0
1559 if (Val == INT32_MIN) Val = 0;
1560 if (Val < 0) Val = -Val;
1561 Val = ARM_AM::getAM3Opc(AddSub, Val);
1562 } else {
1563 // For register offset, we encode the shift type and negation flag
1564 // here.
Jim Grosbache53c87b2011-10-11 15:59:20 +00001565 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
Jim Grosbach2fd2b872011-08-10 20:29:19 +00001566 }
Jim Grosbache53c87b2011-10-11 15:59:20 +00001567 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1568 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach2fd2b872011-08-10 20:29:19 +00001569 Inst.addOperand(MCOperand::CreateImm(Val));
1570 }
1571
1572 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1573 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001574 if (Kind == k_PostIndexRegister) {
Jim Grosbach2fd2b872011-08-10 20:29:19 +00001575 int32_t Val =
1576 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1577 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1578 Inst.addOperand(MCOperand::CreateImm(Val));
Jim Grosbach251bf252011-08-10 21:56:18 +00001579 return;
Jim Grosbach2fd2b872011-08-10 20:29:19 +00001580 }
1581
1582 // Constant offset.
1583 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1584 int32_t Val = CE->getValue();
1585 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1586 // Special case for #-0
1587 if (Val == INT32_MIN) Val = 0;
1588 if (Val < 0) Val = -Val;
Jim Grosbach251bf252011-08-10 21:56:18 +00001589 Val = ARM_AM::getAM3Opc(AddSub, Val);
Jim Grosbach2fd2b872011-08-10 20:29:19 +00001590 Inst.addOperand(MCOperand::CreateReg(0));
1591 Inst.addOperand(MCOperand::CreateImm(Val));
1592 }
1593
Jim Grosbach7ce05792011-08-03 23:50:40 +00001594 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1595 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach681460f2011-11-01 01:24:45 +00001596 // If we have an immediate that's not a constant, treat it as a label
1597 // reference needing a fixup. If it is a constant, it's something else
1598 // and we reject it.
1599 if (isImm()) {
1600 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1601 Inst.addOperand(MCOperand::CreateImm(0));
1602 return;
1603 }
1604
Jim Grosbach7ce05792011-08-03 23:50:40 +00001605 // The lower two bits are always zero and as such are not encoded.
Jim Grosbache53c87b2011-10-11 15:59:20 +00001606 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
Jim Grosbach7ce05792011-08-03 23:50:40 +00001607 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1608 // Special case for #-0
1609 if (Val == INT32_MIN) Val = 0;
1610 if (Val < 0) Val = -Val;
1611 Val = ARM_AM::getAM5Opc(AddSub, Val);
Jim Grosbache53c87b2011-10-11 15:59:20 +00001612 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach7ce05792011-08-03 23:50:40 +00001613 Inst.addOperand(MCOperand::CreateImm(Val));
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +00001614 }
1615
Jim Grosbacha77295d2011-09-08 22:07:06 +00001616 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1617 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach2f196742011-12-19 23:06:24 +00001618 // If we have an immediate that's not a constant, treat it as a label
1619 // reference needing a fixup. If it is a constant, it's something else
1620 // and we reject it.
1621 if (isImm()) {
1622 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1623 Inst.addOperand(MCOperand::CreateImm(0));
1624 return;
1625 }
1626
Jim Grosbache53c87b2011-10-11 15:59:20 +00001627 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1628 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbacha77295d2011-09-08 22:07:06 +00001629 Inst.addOperand(MCOperand::CreateImm(Val));
1630 }
1631
Jim Grosbachb6aed502011-09-09 18:37:27 +00001632 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1633 assert(N == 2 && "Invalid number of operands!");
1634 // The lower two bits are always zero and as such are not encoded.
Jim Grosbache53c87b2011-10-11 15:59:20 +00001635 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1636 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbachb6aed502011-09-09 18:37:27 +00001637 Inst.addOperand(MCOperand::CreateImm(Val));
1638 }
1639
Jim Grosbach7ce05792011-08-03 23:50:40 +00001640 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1641 assert(N == 2 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001642 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1643 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach7ce05792011-08-03 23:50:40 +00001644 Inst.addOperand(MCOperand::CreateImm(Val));
Chris Lattner14b93852010-10-29 00:27:31 +00001645 }
Daniel Dunbar3483aca2010-08-11 05:24:50 +00001646
Jim Grosbachf0eee6e2011-09-07 23:39:14 +00001647 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1648 addMemImm8OffsetOperands(Inst, N);
1649 }
1650
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001651 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
Jim Grosbachf0eee6e2011-09-07 23:39:14 +00001652 addMemImm8OffsetOperands(Inst, N);
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001653 }
1654
1655 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1656 assert(N == 2 && "Invalid number of operands!");
1657 // If this is an immediate, it's a label reference.
Jim Grosbach21bcca82011-12-22 22:02:35 +00001658 if (isImm()) {
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001659 addExpr(Inst, getImm());
1660 Inst.addOperand(MCOperand::CreateImm(0));
1661 return;
1662 }
1663
1664 // Otherwise, it's a normal memory reg+offset.
Jim Grosbache53c87b2011-10-11 15:59:20 +00001665 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1666 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbacha8307dd2011-09-07 20:58:57 +00001667 Inst.addOperand(MCOperand::CreateImm(Val));
1668 }
1669
Jim Grosbach7ce05792011-08-03 23:50:40 +00001670 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1671 assert(N == 2 && "Invalid number of operands!");
Jim Grosbach09176e12011-08-08 20:59:31 +00001672 // If this is an immediate, it's a label reference.
Jim Grosbach21bcca82011-12-22 22:02:35 +00001673 if (isImm()) {
Jim Grosbach09176e12011-08-08 20:59:31 +00001674 addExpr(Inst, getImm());
1675 Inst.addOperand(MCOperand::CreateImm(0));
1676 return;
1677 }
1678
1679 // Otherwise, it's a normal memory reg+offset.
Jim Grosbache53c87b2011-10-11 15:59:20 +00001680 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1681 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach7ce05792011-08-03 23:50:40 +00001682 Inst.addOperand(MCOperand::CreateImm(Val));
Bill Wendlingf4caf692010-12-14 03:36:38 +00001683 }
Bill Wendlingef4a68b2010-11-30 07:44:32 +00001684
Jim Grosbach7f739be2011-09-19 22:21:13 +00001685 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1686 assert(N == 2 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001687 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1688 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach7f739be2011-09-19 22:21:13 +00001689 }
1690
1691 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1692 assert(N == 2 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001693 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1694 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach7f739be2011-09-19 22:21:13 +00001695 }
1696
Jim Grosbach7ce05792011-08-03 23:50:40 +00001697 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1698 assert(N == 3 && "Invalid number of operands!");
Jim Grosbach430052b2011-11-14 17:52:47 +00001699 unsigned Val =
1700 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1701 Memory.ShiftImm, Memory.ShiftType);
Jim Grosbache53c87b2011-10-11 15:59:20 +00001702 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1703 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach7ce05792011-08-03 23:50:40 +00001704 Inst.addOperand(MCOperand::CreateImm(Val));
1705 }
1706
Jim Grosbachab899c12011-09-07 23:10:15 +00001707 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1708 assert(N == 3 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001709 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1710 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1711 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
Jim Grosbachab899c12011-09-07 23:10:15 +00001712 }
1713
Jim Grosbach7ce05792011-08-03 23:50:40 +00001714 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1715 assert(N == 2 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001716 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1717 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
Jim Grosbach7ce05792011-08-03 23:50:40 +00001718 }
1719
Jim Grosbach60f91a32011-08-19 17:55:24 +00001720 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1721 assert(N == 2 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001722 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1723 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach60f91a32011-08-19 17:55:24 +00001724 Inst.addOperand(MCOperand::CreateImm(Val));
1725 }
1726
Jim Grosbach38466302011-08-19 18:55:51 +00001727 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1728 assert(N == 2 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001729 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1730 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach38466302011-08-19 18:55:51 +00001731 Inst.addOperand(MCOperand::CreateImm(Val));
1732 }
1733
Jim Grosbach48ff5ff2011-08-19 18:49:59 +00001734 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1735 assert(N == 2 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001736 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1737 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbach48ff5ff2011-08-19 18:49:59 +00001738 Inst.addOperand(MCOperand::CreateImm(Val));
1739 }
1740
Jim Grosbachecd85892011-08-19 18:13:48 +00001741 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1742 assert(N == 2 && "Invalid number of operands!");
Jim Grosbache53c87b2011-10-11 15:59:20 +00001743 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1744 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
Jim Grosbachecd85892011-08-19 18:13:48 +00001745 Inst.addOperand(MCOperand::CreateImm(Val));
1746 }
1747
Jim Grosbach7ce05792011-08-03 23:50:40 +00001748 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1749 assert(N == 1 && "Invalid number of operands!");
1750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1751 assert(CE && "non-constant post-idx-imm8 operand!");
1752 int Imm = CE->getValue();
1753 bool isAdd = Imm >= 0;
Owen Anderson63553c72011-08-29 17:17:09 +00001754 if (Imm == INT32_MIN) Imm = 0;
Jim Grosbach7ce05792011-08-03 23:50:40 +00001755 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1756 Inst.addOperand(MCOperand::CreateImm(Imm));
1757 }
1758
Jim Grosbach2bd01182011-10-11 21:55:36 +00001759 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1760 assert(N == 1 && "Invalid number of operands!");
1761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1762 assert(CE && "non-constant post-idx-imm8s4 operand!");
1763 int Imm = CE->getValue();
1764 bool isAdd = Imm >= 0;
1765 if (Imm == INT32_MIN) Imm = 0;
1766 // Immediate is scaled by 4.
1767 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1768 Inst.addOperand(MCOperand::CreateImm(Imm));
1769 }
1770
Jim Grosbach7ce05792011-08-03 23:50:40 +00001771 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1772 assert(N == 2 && "Invalid number of operands!");
1773 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
Jim Grosbachf4fa3d62011-08-05 21:28:30 +00001774 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1775 }
1776
1777 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1778 assert(N == 2 && "Invalid number of operands!");
1779 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1780 // The sign, shift type, and shift amount are encoded in a single operand
1781 // using the AM2 encoding helpers.
1782 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1783 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1784 PostIdxReg.ShiftTy);
1785 Inst.addOperand(MCOperand::CreateImm(Imm));
Bill Wendlingef4a68b2010-11-30 07:44:32 +00001786 }
1787
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00001788 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1789 assert(N == 1 && "Invalid number of operands!");
1790 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1791 }
1792
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00001793 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1794 assert(N == 1 && "Invalid number of operands!");
1795 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1796 }
1797
Jim Grosbach6029b6d2011-11-29 23:51:09 +00001798 void addVecListOperands(MCInst &Inst, unsigned N) const {
Jim Grosbach862019c2011-10-18 23:02:30 +00001799 assert(N == 1 && "Invalid number of operands!");
1800 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1801 }
1802
Jim Grosbach7636bf62011-12-02 00:35:16 +00001803 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1804 assert(N == 2 && "Invalid number of operands!");
1805 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1806 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1807 }
1808
Jim Grosbach460a9052011-10-07 23:56:00 +00001809 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1810 assert(N == 1 && "Invalid number of operands!");
1811 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1812 }
1813
1814 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1815 assert(N == 1 && "Invalid number of operands!");
1816 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1817 }
1818
1819 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1820 assert(N == 1 && "Invalid number of operands!");
1821 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1822 }
1823
Jim Grosbach0e387b22011-10-17 22:26:03 +00001824 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1825 assert(N == 1 && "Invalid number of operands!");
1826 // The immediate encodes the type of constant as well as the value.
1827 // Mask in that this is an i8 splat.
1828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1829 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1830 }
1831
Jim Grosbachea461102011-10-17 23:09:09 +00001832 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1833 assert(N == 1 && "Invalid number of operands!");
1834 // The immediate encodes the type of constant as well as the value.
1835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1836 unsigned Value = CE->getValue();
1837 if (Value >= 256)
1838 Value = (Value >> 8) | 0xa00;
1839 else
1840 Value |= 0x800;
1841 Inst.addOperand(MCOperand::CreateImm(Value));
1842 }
1843
Jim Grosbach6248a542011-10-18 00:22:00 +00001844 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1845 assert(N == 1 && "Invalid number of operands!");
1846 // The immediate encodes the type of constant as well as the value.
1847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1848 unsigned Value = CE->getValue();
1849 if (Value >= 256 && Value <= 0xff00)
1850 Value = (Value >> 8) | 0x200;
1851 else if (Value > 0xffff && Value <= 0xff0000)
1852 Value = (Value >> 16) | 0x400;
1853 else if (Value > 0xffffff)
1854 Value = (Value >> 24) | 0x600;
1855 Inst.addOperand(MCOperand::CreateImm(Value));
1856 }
1857
1858 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1859 assert(N == 1 && "Invalid number of operands!");
1860 // The immediate encodes the type of constant as well as the value.
1861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1862 unsigned Value = CE->getValue();
1863 if (Value >= 256 && Value <= 0xffff)
1864 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1865 else if (Value > 0xffff && Value <= 0xffffff)
1866 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1867 else if (Value > 0xffffff)
1868 Value = (Value >> 24) | 0x600;
1869 Inst.addOperand(MCOperand::CreateImm(Value));
1870 }
1871
Jim Grosbach9b087852011-12-19 23:51:07 +00001872 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
1873 assert(N == 1 && "Invalid number of operands!");
1874 // The immediate encodes the type of constant as well as the value.
1875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1876 unsigned Value = ~CE->getValue();
1877 if (Value >= 256 && Value <= 0xffff)
1878 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1879 else if (Value > 0xffff && Value <= 0xffffff)
1880 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1881 else if (Value > 0xffffff)
1882 Value = (Value >> 24) | 0x600;
1883 Inst.addOperand(MCOperand::CreateImm(Value));
1884 }
1885
Jim Grosbachf2f5bc62011-10-18 16:18:11 +00001886 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1887 assert(N == 1 && "Invalid number of operands!");
1888 // The immediate encodes the type of constant as well as the value.
1889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1890 uint64_t Value = CE->getValue();
1891 unsigned Imm = 0;
1892 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1893 Imm |= (Value & 1) << i;
1894 }
1895 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1896 }
1897
Jim Grosbachb7f689b2011-07-13 15:34:57 +00001898 virtual void print(raw_ostream &OS) const;
Daniel Dunbarb3cb6962010-08-11 06:37:04 +00001899
Jim Grosbach89df9962011-08-26 21:43:41 +00001900 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001901 ARMOperand *Op = new ARMOperand(k_ITCondMask);
Jim Grosbach89df9962011-08-26 21:43:41 +00001902 Op->ITMask.Mask = Mask;
1903 Op->StartLoc = S;
1904 Op->EndLoc = S;
1905 return Op;
1906 }
1907
Chris Lattner3a697562010-10-28 17:20:03 +00001908 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001909 ARMOperand *Op = new ARMOperand(k_CondCode);
Daniel Dunbar345a9a62010-08-11 06:37:20 +00001910 Op->CC.Val = CC;
1911 Op->StartLoc = S;
1912 Op->EndLoc = S;
Chris Lattner3a697562010-10-28 17:20:03 +00001913 return Op;
Daniel Dunbar345a9a62010-08-11 06:37:20 +00001914 }
1915
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00001916 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001917 ARMOperand *Op = new ARMOperand(k_CoprocNum);
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00001918 Op->Cop.Val = CopVal;
1919 Op->StartLoc = S;
1920 Op->EndLoc = S;
1921 return Op;
1922 }
1923
1924 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001925 ARMOperand *Op = new ARMOperand(k_CoprocReg);
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00001926 Op->Cop.Val = CopVal;
1927 Op->StartLoc = S;
1928 Op->EndLoc = S;
1929 return Op;
1930 }
1931
Jim Grosbach9b8f2a02011-10-12 17:34:41 +00001932 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1933 ARMOperand *Op = new ARMOperand(k_CoprocOption);
1934 Op->Cop.Val = Val;
1935 Op->StartLoc = S;
1936 Op->EndLoc = E;
1937 return Op;
1938 }
1939
Jim Grosbachd67641b2010-12-06 18:21:12 +00001940 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001941 ARMOperand *Op = new ARMOperand(k_CCOut);
Jim Grosbachd67641b2010-12-06 18:21:12 +00001942 Op->Reg.RegNum = RegNum;
1943 Op->StartLoc = S;
1944 Op->EndLoc = S;
1945 return Op;
1946 }
1947
Chris Lattner3a697562010-10-28 17:20:03 +00001948 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001949 ARMOperand *Op = new ARMOperand(k_Token);
Sean Callanan76264762010-04-02 22:27:05 +00001950 Op->Tok.Data = Str.data();
1951 Op->Tok.Length = Str.size();
1952 Op->StartLoc = S;
1953 Op->EndLoc = S;
Chris Lattner3a697562010-10-28 17:20:03 +00001954 return Op;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00001955 }
1956
Bill Wendling50d0f582010-11-18 23:43:05 +00001957 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001958 ARMOperand *Op = new ARMOperand(k_Register);
Sean Callanan76264762010-04-02 22:27:05 +00001959 Op->Reg.RegNum = RegNum;
Sean Callanan76264762010-04-02 22:27:05 +00001960 Op->StartLoc = S;
1961 Op->EndLoc = E;
Chris Lattner3a697562010-10-28 17:20:03 +00001962 return Op;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00001963 }
1964
Jim Grosbache8606dc2011-07-13 17:50:29 +00001965 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1966 unsigned SrcReg,
1967 unsigned ShiftReg,
1968 unsigned ShiftImm,
1969 SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001970 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
Jim Grosbachaf6981f2011-07-25 20:49:51 +00001971 Op->RegShiftedReg.ShiftTy = ShTy;
1972 Op->RegShiftedReg.SrcReg = SrcReg;
1973 Op->RegShiftedReg.ShiftReg = ShiftReg;
1974 Op->RegShiftedReg.ShiftImm = ShiftImm;
Jim Grosbache8606dc2011-07-13 17:50:29 +00001975 Op->StartLoc = S;
1976 Op->EndLoc = E;
1977 return Op;
1978 }
1979
Owen Anderson92a20222011-07-21 18:54:16 +00001980 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1981 unsigned SrcReg,
1982 unsigned ShiftImm,
1983 SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001984 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
Jim Grosbachaf6981f2011-07-25 20:49:51 +00001985 Op->RegShiftedImm.ShiftTy = ShTy;
1986 Op->RegShiftedImm.SrcReg = SrcReg;
1987 Op->RegShiftedImm.ShiftImm = ShiftImm;
Owen Anderson92a20222011-07-21 18:54:16 +00001988 Op->StartLoc = S;
1989 Op->EndLoc = E;
1990 return Op;
1991 }
1992
Jim Grosbach580f4a92011-07-25 22:20:28 +00001993 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
Owen Anderson00828302011-03-18 22:50:18 +00001994 SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00001995 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
Jim Grosbach580f4a92011-07-25 22:20:28 +00001996 Op->ShifterImm.isASR = isASR;
1997 Op->ShifterImm.Imm = Imm;
Owen Anderson00828302011-03-18 22:50:18 +00001998 Op->StartLoc = S;
1999 Op->EndLoc = E;
2000 return Op;
2001 }
2002
Jim Grosbach7e1547e2011-07-27 20:15:40 +00002003 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002004 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
Jim Grosbach7e1547e2011-07-27 20:15:40 +00002005 Op->RotImm.Imm = Imm;
2006 Op->StartLoc = S;
2007 Op->EndLoc = E;
2008 return Op;
2009 }
2010
Jim Grosbach293a2ee2011-07-28 21:34:26 +00002011 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2012 SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002013 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
Jim Grosbach293a2ee2011-07-28 21:34:26 +00002014 Op->Bitfield.LSB = LSB;
2015 Op->Bitfield.Width = Width;
2016 Op->StartLoc = S;
2017 Op->EndLoc = E;
2018 return Op;
2019 }
2020
Bill Wendling7729e062010-11-09 22:44:22 +00002021 static ARMOperand *
Bill Wendling5fa22a12010-11-09 23:28:44 +00002022 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
Matt Beaumont-Gaycc8d10e2010-11-10 00:08:58 +00002023 SMLoc StartLoc, SMLoc EndLoc) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002024 KindTy Kind = k_RegisterList;
Bill Wendling0f630752010-11-17 04:32:08 +00002025
Jim Grosbachd300b942011-09-13 22:56:44 +00002026 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002027 Kind = k_DPRRegisterList;
Jim Grosbachd300b942011-09-13 22:56:44 +00002028 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
Evan Cheng275944a2011-07-25 21:32:49 +00002029 contains(Regs.front().first))
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002030 Kind = k_SPRRegisterList;
Bill Wendling0f630752010-11-17 04:32:08 +00002031
2032 ARMOperand *Op = new ARMOperand(Kind);
Bill Wendling5fa22a12010-11-09 23:28:44 +00002033 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
Bill Wendling7729e062010-11-09 22:44:22 +00002034 I = Regs.begin(), E = Regs.end(); I != E; ++I)
Bill Wendling24d22d22010-11-18 21:50:54 +00002035 Op->Registers.push_back(I->first);
Bill Wendlingcb21d1c2010-11-19 00:38:19 +00002036 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
Matt Beaumont-Gaycc8d10e2010-11-10 00:08:58 +00002037 Op->StartLoc = StartLoc;
2038 Op->EndLoc = EndLoc;
Bill Wendling8d5acb72010-11-06 19:56:04 +00002039 return Op;
2040 }
2041
Jim Grosbach862019c2011-10-18 23:02:30 +00002042 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00002043 bool isDoubleSpaced, SMLoc S, SMLoc E) {
Jim Grosbach862019c2011-10-18 23:02:30 +00002044 ARMOperand *Op = new ARMOperand(k_VectorList);
2045 Op->VectorList.RegNum = RegNum;
2046 Op->VectorList.Count = Count;
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00002047 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Jim Grosbach862019c2011-10-18 23:02:30 +00002048 Op->StartLoc = S;
2049 Op->EndLoc = E;
2050 return Op;
2051 }
2052
Jim Grosbach98b05a52011-11-30 01:09:44 +00002053 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
Jim Grosbach3471d4f2011-12-21 00:38:54 +00002054 bool isDoubleSpaced,
Jim Grosbach98b05a52011-11-30 01:09:44 +00002055 SMLoc S, SMLoc E) {
2056 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2057 Op->VectorList.RegNum = RegNum;
2058 Op->VectorList.Count = Count;
Jim Grosbach3471d4f2011-12-21 00:38:54 +00002059 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Jim Grosbach98b05a52011-11-30 01:09:44 +00002060 Op->StartLoc = S;
2061 Op->EndLoc = E;
2062 return Op;
2063 }
2064
Jim Grosbach7636bf62011-12-02 00:35:16 +00002065 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
Jim Grosbach95fad1c2011-12-20 19:21:26 +00002066 unsigned Index,
2067 bool isDoubleSpaced,
2068 SMLoc S, SMLoc E) {
Jim Grosbach7636bf62011-12-02 00:35:16 +00002069 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2070 Op->VectorList.RegNum = RegNum;
2071 Op->VectorList.Count = Count;
2072 Op->VectorList.LaneIndex = Index;
Jim Grosbach95fad1c2011-12-20 19:21:26 +00002073 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
Jim Grosbach7636bf62011-12-02 00:35:16 +00002074 Op->StartLoc = S;
2075 Op->EndLoc = E;
2076 return Op;
2077 }
2078
Jim Grosbach460a9052011-10-07 23:56:00 +00002079 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2080 MCContext &Ctx) {
2081 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2082 Op->VectorIndex.Val = Idx;
2083 Op->StartLoc = S;
2084 Op->EndLoc = E;
2085 return Op;
2086 }
2087
Chris Lattner3a697562010-10-28 17:20:03 +00002088 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002089 ARMOperand *Op = new ARMOperand(k_Immediate);
Sean Callanan76264762010-04-02 22:27:05 +00002090 Op->Imm.Val = Val;
Sean Callanan76264762010-04-02 22:27:05 +00002091 Op->StartLoc = S;
2092 Op->EndLoc = E;
Chris Lattner3a697562010-10-28 17:20:03 +00002093 return Op;
Kevin Enderbycfe07242009-10-13 22:19:02 +00002094 }
2095
Jim Grosbach7ce05792011-08-03 23:50:40 +00002096 static ARMOperand *CreateMem(unsigned BaseRegNum,
2097 const MCConstantExpr *OffsetImm,
2098 unsigned OffsetRegNum,
2099 ARM_AM::ShiftOpc ShiftType,
Jim Grosbach0d6fac32011-08-05 22:03:36 +00002100 unsigned ShiftImm,
Jim Grosbach57dcb852011-10-11 17:29:55 +00002101 unsigned Alignment,
Jim Grosbach7ce05792011-08-03 23:50:40 +00002102 bool isNegative,
Chris Lattner3a697562010-10-28 17:20:03 +00002103 SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002104 ARMOperand *Op = new ARMOperand(k_Memory);
Jim Grosbache53c87b2011-10-11 15:59:20 +00002105 Op->Memory.BaseRegNum = BaseRegNum;
2106 Op->Memory.OffsetImm = OffsetImm;
2107 Op->Memory.OffsetRegNum = OffsetRegNum;
2108 Op->Memory.ShiftType = ShiftType;
2109 Op->Memory.ShiftImm = ShiftImm;
Jim Grosbach57dcb852011-10-11 17:29:55 +00002110 Op->Memory.Alignment = Alignment;
Jim Grosbache53c87b2011-10-11 15:59:20 +00002111 Op->Memory.isNegative = isNegative;
Jim Grosbach7ce05792011-08-03 23:50:40 +00002112 Op->StartLoc = S;
2113 Op->EndLoc = E;
2114 return Op;
2115 }
Jim Grosbach16c74252010-10-29 14:46:02 +00002116
Jim Grosbachf4fa3d62011-08-05 21:28:30 +00002117 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2118 ARM_AM::ShiftOpc ShiftTy,
2119 unsigned ShiftImm,
Jim Grosbach7ce05792011-08-03 23:50:40 +00002120 SMLoc S, SMLoc E) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002121 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
Jim Grosbach7ce05792011-08-03 23:50:40 +00002122 Op->PostIdxReg.RegNum = RegNum;
Jim Grosbachf4fa3d62011-08-05 21:28:30 +00002123 Op->PostIdxReg.isAdd = isAdd;
2124 Op->PostIdxReg.ShiftTy = ShiftTy;
2125 Op->PostIdxReg.ShiftImm = ShiftImm;
Sean Callanan76264762010-04-02 22:27:05 +00002126 Op->StartLoc = S;
2127 Op->EndLoc = E;
Chris Lattner3a697562010-10-28 17:20:03 +00002128 return Op;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00002129 }
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00002130
2131 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002132 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00002133 Op->MBOpt.Val = Opt;
2134 Op->StartLoc = S;
2135 Op->EndLoc = S;
2136 return Op;
2137 }
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00002138
2139 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002140 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00002141 Op->IFlags.Val = IFlags;
2142 Op->StartLoc = S;
2143 Op->EndLoc = S;
2144 return Op;
2145 }
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00002146
2147 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002148 ARMOperand *Op = new ARMOperand(k_MSRMask);
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00002149 Op->MMask.Val = MMask;
2150 Op->StartLoc = S;
2151 Op->EndLoc = S;
2152 return Op;
2153 }
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00002154};
2155
2156} // end anonymous namespace.
2157
Jim Grosbachb7f689b2011-07-13 15:34:57 +00002158void ARMOperand::print(raw_ostream &OS) const {
Daniel Dunbarfa315de2010-08-11 06:37:12 +00002159 switch (Kind) {
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002160 case k_CondCode:
Daniel Dunbar6a5c22e2011-01-10 15:26:21 +00002161 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
Daniel Dunbarfa315de2010-08-11 06:37:12 +00002162 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002163 case k_CCOut:
Jim Grosbachd67641b2010-12-06 18:21:12 +00002164 OS << "<ccout " << getReg() << ">";
2165 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002166 case k_ITCondMask: {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +00002167 static const char *MaskStr[] = {
2168 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2169 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2170 };
Jim Grosbach89df9962011-08-26 21:43:41 +00002171 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2172 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2173 break;
2174 }
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002175 case k_CoprocNum:
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002176 OS << "<coprocessor number: " << getCoproc() << ">";
2177 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002178 case k_CoprocReg:
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002179 OS << "<coprocessor register: " << getCoproc() << ">";
2180 break;
Jim Grosbach9b8f2a02011-10-12 17:34:41 +00002181 case k_CoprocOption:
2182 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2183 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002184 case k_MSRMask:
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00002185 OS << "<mask: " << getMSRMask() << ">";
2186 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002187 case k_Immediate:
Daniel Dunbarfa315de2010-08-11 06:37:12 +00002188 getImm()->print(OS);
2189 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002190 case k_MemBarrierOpt:
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00002191 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2192 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002193 case k_Memory:
Daniel Dunbar6ec56202011-01-18 05:55:21 +00002194 OS << "<memory "
Jim Grosbache53c87b2011-10-11 15:59:20 +00002195 << " base:" << Memory.BaseRegNum;
Daniel Dunbar6ec56202011-01-18 05:55:21 +00002196 OS << ">";
Daniel Dunbarfa315de2010-08-11 06:37:12 +00002197 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002198 case k_PostIndexRegister:
Jim Grosbachf4fa3d62011-08-05 21:28:30 +00002199 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2200 << PostIdxReg.RegNum;
2201 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2202 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2203 << PostIdxReg.ShiftImm;
2204 OS << ">";
Jim Grosbach7ce05792011-08-03 23:50:40 +00002205 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002206 case k_ProcIFlags: {
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00002207 OS << "<ARM_PROC::";
2208 unsigned IFlags = getProcIFlags();
2209 for (int i=2; i >= 0; --i)
2210 if (IFlags & (1 << i))
2211 OS << ARM_PROC::IFlagsToString(1 << i);
2212 OS << ">";
2213 break;
2214 }
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002215 case k_Register:
Bill Wendling50d0f582010-11-18 23:43:05 +00002216 OS << "<register " << getReg() << ">";
Daniel Dunbarfa315de2010-08-11 06:37:12 +00002217 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002218 case k_ShifterImmediate:
Jim Grosbach580f4a92011-07-25 22:20:28 +00002219 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2220 << " #" << ShifterImm.Imm << ">";
Jim Grosbache8606dc2011-07-13 17:50:29 +00002221 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002222 case k_ShiftedRegister:
Owen Anderson92a20222011-07-21 18:54:16 +00002223 OS << "<so_reg_reg "
Jim Grosbachefed3d12011-11-16 21:46:50 +00002224 << RegShiftedReg.SrcReg << " "
2225 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2226 << " " << RegShiftedReg.ShiftReg << ">";
Owen Anderson00828302011-03-18 22:50:18 +00002227 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002228 case k_ShiftedImmediate:
Owen Anderson92a20222011-07-21 18:54:16 +00002229 OS << "<so_reg_imm "
Jim Grosbachefed3d12011-11-16 21:46:50 +00002230 << RegShiftedImm.SrcReg << " "
2231 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2232 << " #" << RegShiftedImm.ShiftImm << ">";
Owen Anderson92a20222011-07-21 18:54:16 +00002233 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002234 case k_RotateImmediate:
Jim Grosbach7e1547e2011-07-27 20:15:40 +00002235 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2236 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002237 case k_BitfieldDescriptor:
Jim Grosbach293a2ee2011-07-28 21:34:26 +00002238 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2239 << ", width: " << Bitfield.Width << ">";
2240 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002241 case k_RegisterList:
2242 case k_DPRRegisterList:
2243 case k_SPRRegisterList: {
Bill Wendling8d5acb72010-11-06 19:56:04 +00002244 OS << "<register_list ";
Bill Wendling8d5acb72010-11-06 19:56:04 +00002245
Bill Wendling5fa22a12010-11-09 23:28:44 +00002246 const SmallVectorImpl<unsigned> &RegList = getRegList();
2247 for (SmallVectorImpl<unsigned>::const_iterator
Bill Wendling7729e062010-11-09 22:44:22 +00002248 I = RegList.begin(), E = RegList.end(); I != E; ) {
2249 OS << *I;
2250 if (++I < E) OS << ", ";
Bill Wendling8d5acb72010-11-06 19:56:04 +00002251 }
2252
2253 OS << ">";
2254 break;
2255 }
Jim Grosbach862019c2011-10-18 23:02:30 +00002256 case k_VectorList:
2257 OS << "<vector_list " << VectorList.Count << " * "
2258 << VectorList.RegNum << ">";
2259 break;
Jim Grosbach98b05a52011-11-30 01:09:44 +00002260 case k_VectorListAllLanes:
2261 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2262 << VectorList.RegNum << ">";
2263 break;
Jim Grosbach7636bf62011-12-02 00:35:16 +00002264 case k_VectorListIndexed:
2265 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2266 << VectorList.Count << " * " << VectorList.RegNum << ">";
2267 break;
Jim Grosbach21ff17c2011-10-07 23:24:09 +00002268 case k_Token:
Daniel Dunbarfa315de2010-08-11 06:37:12 +00002269 OS << "'" << getToken() << "'";
2270 break;
Jim Grosbach460a9052011-10-07 23:56:00 +00002271 case k_VectorIndex:
2272 OS << "<vectorindex " << getVectorIndex() << ">";
2273 break;
Daniel Dunbarfa315de2010-08-11 06:37:12 +00002274 }
2275}
Daniel Dunbar3483aca2010-08-11 05:24:50 +00002276
2277/// @name Auto-generated Match Functions
2278/// {
2279
2280static unsigned MatchRegisterName(StringRef Name);
2281
2282/// }
2283
Bob Wilson69df7232011-02-03 21:46:10 +00002284bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2285 SMLoc &StartLoc, SMLoc &EndLoc) {
Jim Grosbacha39cda72011-12-14 02:16:11 +00002286 StartLoc = Parser.getTok().getLoc();
Jim Grosbach1355cf12011-07-26 17:10:22 +00002287 RegNo = tryParseRegister();
Jim Grosbacha39cda72011-12-14 02:16:11 +00002288 EndLoc = Parser.getTok().getLoc();
Roman Divackybf755322011-01-27 17:14:22 +00002289
2290 return (RegNo == (unsigned)-1);
2291}
2292
Kevin Enderby9c41fa82009-10-30 22:55:57 +00002293/// Try to parse a register name. The token must be an Identifier when called,
Chris Lattnere5658fa2010-10-30 04:09:10 +00002294/// and if it is a register name the token is eaten and the register number is
2295/// returned. Otherwise return -1.
2296///
Jim Grosbach1355cf12011-07-26 17:10:22 +00002297int ARMAsmParser::tryParseRegister() {
Chris Lattnere5658fa2010-10-30 04:09:10 +00002298 const AsmToken &Tok = Parser.getTok();
Jim Grosbach7ce05792011-08-03 23:50:40 +00002299 if (Tok.isNot(AsmToken::Identifier)) return -1;
Jim Grosbachd4462a52010-11-01 16:44:21 +00002300
Benjamin Kramer59085362011-11-06 20:37:06 +00002301 std::string lowerCase = Tok.getString().lower();
Owen Anderson0c9f2502011-01-13 22:50:36 +00002302 unsigned RegNum = MatchRegisterName(lowerCase);
2303 if (!RegNum) {
2304 RegNum = StringSwitch<unsigned>(lowerCase)
2305 .Case("r13", ARM::SP)
2306 .Case("r14", ARM::LR)
2307 .Case("r15", ARM::PC)
2308 .Case("ip", ARM::R12)
Jim Grosbach40e28552011-12-08 19:27:38 +00002309 // Additional register name aliases for 'gas' compatibility.
2310 .Case("a1", ARM::R0)
2311 .Case("a2", ARM::R1)
2312 .Case("a3", ARM::R2)
2313 .Case("a4", ARM::R3)
2314 .Case("v1", ARM::R4)
2315 .Case("v2", ARM::R5)
2316 .Case("v3", ARM::R6)
2317 .Case("v4", ARM::R7)
2318 .Case("v5", ARM::R8)
2319 .Case("v6", ARM::R9)
2320 .Case("v7", ARM::R10)
2321 .Case("v8", ARM::R11)
2322 .Case("sb", ARM::R9)
2323 .Case("sl", ARM::R10)
2324 .Case("fp", ARM::R11)
Owen Anderson0c9f2502011-01-13 22:50:36 +00002325 .Default(0);
2326 }
Jim Grosbacha39cda72011-12-14 02:16:11 +00002327 if (!RegNum) {
Jim Grosbachaee718b2011-12-20 23:11:00 +00002328 // Check for aliases registered via .req. Canonicalize to lower case.
2329 // That's more consistent since register names are case insensitive, and
2330 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2331 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
Jim Grosbacha39cda72011-12-14 02:16:11 +00002332 // If no match, return failure.
2333 if (Entry == RegisterReqs.end())
2334 return -1;
2335 Parser.Lex(); // Eat identifier token.
2336 return Entry->getValue();
2337 }
Bob Wilson69df7232011-02-03 21:46:10 +00002338
Chris Lattnere5658fa2010-10-30 04:09:10 +00002339 Parser.Lex(); // Eat identifier token.
Jim Grosbach460a9052011-10-07 23:56:00 +00002340
Chris Lattnere5658fa2010-10-30 04:09:10 +00002341 return RegNum;
2342}
Jim Grosbachd4462a52010-11-01 16:44:21 +00002343
Jim Grosbach19906722011-07-13 18:49:30 +00002344// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2345// If a recoverable error occurs, return 1. If an irrecoverable error
2346// occurs, return -1. An irrecoverable error is one where tokens have been
2347// consumed in the process of trying to parse the shifter (i.e., when it is
2348// indeed a shifter operand, but malformed).
Jim Grosbach0d87ec22011-07-26 20:41:24 +00002349int ARMAsmParser::tryParseShiftRegister(
Owen Anderson00828302011-03-18 22:50:18 +00002350 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2351 SMLoc S = Parser.getTok().getLoc();
2352 const AsmToken &Tok = Parser.getTok();
2353 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2354
Benjamin Kramer59085362011-11-06 20:37:06 +00002355 std::string lowerCase = Tok.getString().lower();
Owen Anderson00828302011-03-18 22:50:18 +00002356 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
Jim Grosbachaf4edea2011-12-07 23:40:58 +00002357 .Case("asl", ARM_AM::lsl)
Owen Anderson00828302011-03-18 22:50:18 +00002358 .Case("lsl", ARM_AM::lsl)
2359 .Case("lsr", ARM_AM::lsr)
2360 .Case("asr", ARM_AM::asr)
2361 .Case("ror", ARM_AM::ror)
2362 .Case("rrx", ARM_AM::rrx)
2363 .Default(ARM_AM::no_shift);
2364
2365 if (ShiftTy == ARM_AM::no_shift)
Jim Grosbach19906722011-07-13 18:49:30 +00002366 return 1;
Owen Anderson00828302011-03-18 22:50:18 +00002367
Jim Grosbache8606dc2011-07-13 17:50:29 +00002368 Parser.Lex(); // Eat the operator.
Owen Anderson00828302011-03-18 22:50:18 +00002369
Jim Grosbache8606dc2011-07-13 17:50:29 +00002370 // The source register for the shift has already been added to the
2371 // operand list, so we need to pop it off and combine it into the shifted
2372 // register operand instead.
Benjamin Kramereac07962011-07-14 18:41:22 +00002373 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
Jim Grosbache8606dc2011-07-13 17:50:29 +00002374 if (!PrevOp->isReg())
2375 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2376 int SrcReg = PrevOp->getReg();
2377 int64_t Imm = 0;
2378 int ShiftReg = 0;
2379 if (ShiftTy == ARM_AM::rrx) {
2380 // RRX Doesn't have an explicit shift amount. The encoder expects
2381 // the shift register to be the same as the source register. Seems odd,
2382 // but OK.
2383 ShiftReg = SrcReg;
2384 } else {
2385 // Figure out if this is shifted by a constant or a register (for non-RRX).
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00002386 if (Parser.getTok().is(AsmToken::Hash) ||
2387 Parser.getTok().is(AsmToken::Dollar)) {
Jim Grosbache8606dc2011-07-13 17:50:29 +00002388 Parser.Lex(); // Eat hash.
2389 SMLoc ImmLoc = Parser.getTok().getLoc();
2390 const MCExpr *ShiftExpr = 0;
Jim Grosbach19906722011-07-13 18:49:30 +00002391 if (getParser().ParseExpression(ShiftExpr)) {
2392 Error(ImmLoc, "invalid immediate shift value");
2393 return -1;
2394 }
Jim Grosbache8606dc2011-07-13 17:50:29 +00002395 // The expression must be evaluatable as an immediate.
2396 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
Jim Grosbach19906722011-07-13 18:49:30 +00002397 if (!CE) {
2398 Error(ImmLoc, "invalid immediate shift value");
2399 return -1;
2400 }
Jim Grosbache8606dc2011-07-13 17:50:29 +00002401 // Range check the immediate.
2402 // lsl, ror: 0 <= imm <= 31
2403 // lsr, asr: 0 <= imm <= 32
2404 Imm = CE->getValue();
2405 if (Imm < 0 ||
2406 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2407 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
Jim Grosbach19906722011-07-13 18:49:30 +00002408 Error(ImmLoc, "immediate shift value out of range");
2409 return -1;
Jim Grosbache8606dc2011-07-13 17:50:29 +00002410 }
Jim Grosbachde626ad2011-12-22 17:37:00 +00002411 // shift by zero is a nop. Always send it through as lsl.
2412 // ('as' compatibility)
2413 if (Imm == 0)
2414 ShiftTy = ARM_AM::lsl;
Jim Grosbache8606dc2011-07-13 17:50:29 +00002415 } else if (Parser.getTok().is(AsmToken::Identifier)) {
Jim Grosbach1355cf12011-07-26 17:10:22 +00002416 ShiftReg = tryParseRegister();
Jim Grosbache8606dc2011-07-13 17:50:29 +00002417 SMLoc L = Parser.getTok().getLoc();
Jim Grosbach19906722011-07-13 18:49:30 +00002418 if (ShiftReg == -1) {
2419 Error (L, "expected immediate or register in shift operand");
2420 return -1;
2421 }
2422 } else {
2423 Error (Parser.getTok().getLoc(),
Jim Grosbache8606dc2011-07-13 17:50:29 +00002424 "expected immediate or register in shift operand");
Jim Grosbach19906722011-07-13 18:49:30 +00002425 return -1;
2426 }
Jim Grosbache8606dc2011-07-13 17:50:29 +00002427 }
2428
Owen Anderson92a20222011-07-21 18:54:16 +00002429 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2430 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
Jim Grosbachaf6981f2011-07-25 20:49:51 +00002431 ShiftReg, Imm,
Owen Anderson00828302011-03-18 22:50:18 +00002432 S, Parser.getTok().getLoc()));
Owen Anderson92a20222011-07-21 18:54:16 +00002433 else
2434 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2435 S, Parser.getTok().getLoc()));
Owen Anderson00828302011-03-18 22:50:18 +00002436
Jim Grosbach19906722011-07-13 18:49:30 +00002437 return 0;
Owen Anderson00828302011-03-18 22:50:18 +00002438}
2439
2440
Bill Wendling50d0f582010-11-18 23:43:05 +00002441/// Try to parse a register name. The token must be an Identifier when called.
2442/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2443/// if there is a "writeback". 'true' if it's not a register.
Chris Lattner3a697562010-10-28 17:20:03 +00002444///
Kevin Enderby9c41fa82009-10-30 22:55:57 +00002445/// TODO this is likely to change to allow different register types and or to
2446/// parse for a specific register type.
Bill Wendling50d0f582010-11-18 23:43:05 +00002447bool ARMAsmParser::
Jim Grosbach1355cf12011-07-26 17:10:22 +00002448tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Chris Lattnere5658fa2010-10-30 04:09:10 +00002449 SMLoc S = Parser.getTok().getLoc();
Jim Grosbach1355cf12011-07-26 17:10:22 +00002450 int RegNo = tryParseRegister();
Bill Wendlinge7176102010-11-06 22:36:58 +00002451 if (RegNo == -1)
Bill Wendling50d0f582010-11-18 23:43:05 +00002452 return true;
Jim Grosbachd4462a52010-11-01 16:44:21 +00002453
Bill Wendling50d0f582010-11-18 23:43:05 +00002454 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00002455
Chris Lattnere5658fa2010-10-30 04:09:10 +00002456 const AsmToken &ExclaimTok = Parser.getTok();
2457 if (ExclaimTok.is(AsmToken::Exclaim)) {
Bill Wendling50d0f582010-11-18 23:43:05 +00002458 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2459 ExclaimTok.getLoc()));
Chris Lattnere5658fa2010-10-30 04:09:10 +00002460 Parser.Lex(); // Eat exclaim token
Jim Grosbach460a9052011-10-07 23:56:00 +00002461 return false;
2462 }
2463
2464 // Also check for an index operand. This is only legal for vector registers,
2465 // but that'll get caught OK in operand matching, so we don't need to
2466 // explicitly filter everything else out here.
2467 if (Parser.getTok().is(AsmToken::LBrac)) {
2468 SMLoc SIdx = Parser.getTok().getLoc();
2469 Parser.Lex(); // Eat left bracket token.
2470
2471 const MCExpr *ImmVal;
Jim Grosbach460a9052011-10-07 23:56:00 +00002472 if (getParser().ParseExpression(ImmVal))
2473 return MatchOperand_ParseFail;
2474 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2475 if (!MCE) {
2476 TokError("immediate value expected for vector index");
2477 return MatchOperand_ParseFail;
2478 }
2479
2480 SMLoc E = Parser.getTok().getLoc();
2481 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2482 Error(E, "']' expected");
2483 return MatchOperand_ParseFail;
2484 }
2485
2486 Parser.Lex(); // Eat right bracket token.
2487
2488 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2489 SIdx, E,
2490 getContext()));
Kevin Enderby99e6d4e2009-10-07 18:01:35 +00002491 }
2492
Bill Wendling50d0f582010-11-18 23:43:05 +00002493 return false;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00002494}
2495
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002496/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2497/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2498/// "c5", ...
2499static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002500 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2501 // but efficient.
2502 switch (Name.size()) {
David Blaikie4d6ccb52012-01-20 21:51:11 +00002503 default: return -1;
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002504 case 2:
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002505 if (Name[0] != CoprocOp)
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002506 return -1;
2507 switch (Name[1]) {
2508 default: return -1;
2509 case '0': return 0;
2510 case '1': return 1;
2511 case '2': return 2;
2512 case '3': return 3;
2513 case '4': return 4;
2514 case '5': return 5;
2515 case '6': return 6;
2516 case '7': return 7;
2517 case '8': return 8;
2518 case '9': return 9;
2519 }
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002520 case 3:
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002521 if (Name[0] != CoprocOp || Name[1] != '1')
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002522 return -1;
2523 switch (Name[2]) {
2524 default: return -1;
2525 case '0': return 10;
2526 case '1': return 11;
2527 case '2': return 12;
2528 case '3': return 13;
2529 case '4': return 14;
2530 case '5': return 15;
2531 }
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002532 }
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002533}
2534
Jim Grosbach89df9962011-08-26 21:43:41 +00002535/// parseITCondCode - Try to parse a condition code for an IT instruction.
2536ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2537parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2538 SMLoc S = Parser.getTok().getLoc();
2539 const AsmToken &Tok = Parser.getTok();
2540 if (!Tok.is(AsmToken::Identifier))
2541 return MatchOperand_NoMatch;
2542 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2543 .Case("eq", ARMCC::EQ)
2544 .Case("ne", ARMCC::NE)
2545 .Case("hs", ARMCC::HS)
2546 .Case("cs", ARMCC::HS)
2547 .Case("lo", ARMCC::LO)
2548 .Case("cc", ARMCC::LO)
2549 .Case("mi", ARMCC::MI)
2550 .Case("pl", ARMCC::PL)
2551 .Case("vs", ARMCC::VS)
2552 .Case("vc", ARMCC::VC)
2553 .Case("hi", ARMCC::HI)
2554 .Case("ls", ARMCC::LS)
2555 .Case("ge", ARMCC::GE)
2556 .Case("lt", ARMCC::LT)
2557 .Case("gt", ARMCC::GT)
2558 .Case("le", ARMCC::LE)
2559 .Case("al", ARMCC::AL)
2560 .Default(~0U);
2561 if (CC == ~0U)
2562 return MatchOperand_NoMatch;
2563 Parser.Lex(); // Eat the token.
2564
2565 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2566
2567 return MatchOperand_Success;
2568}
2569
Jim Grosbach43904292011-07-25 20:14:50 +00002570/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002571/// token must be an Identifier when called, and if it is a coprocessor
2572/// number, the token is eaten and the operand is added to the operand list.
Jim Grosbachf922c472011-02-12 01:34:40 +00002573ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach43904292011-07-25 20:14:50 +00002574parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002575 SMLoc S = Parser.getTok().getLoc();
2576 const AsmToken &Tok = Parser.getTok();
Jim Grosbachc66e7af2011-10-12 20:54:17 +00002577 if (Tok.isNot(AsmToken::Identifier))
2578 return MatchOperand_NoMatch;
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002579
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002580 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002581 if (Num == -1)
Jim Grosbachf922c472011-02-12 01:34:40 +00002582 return MatchOperand_NoMatch;
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002583
2584 Parser.Lex(); // Eat identifier token.
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002585 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
Jim Grosbachf922c472011-02-12 01:34:40 +00002586 return MatchOperand_Success;
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002587}
2588
Jim Grosbach43904292011-07-25 20:14:50 +00002589/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002590/// token must be an Identifier when called, and if it is a coprocessor
2591/// number, the token is eaten and the operand is added to the operand list.
Jim Grosbachf922c472011-02-12 01:34:40 +00002592ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach43904292011-07-25 20:14:50 +00002593parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002594 SMLoc S = Parser.getTok().getLoc();
2595 const AsmToken &Tok = Parser.getTok();
Jim Grosbachc66e7af2011-10-12 20:54:17 +00002596 if (Tok.isNot(AsmToken::Identifier))
2597 return MatchOperand_NoMatch;
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002598
2599 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2600 if (Reg == -1)
Jim Grosbachf922c472011-02-12 01:34:40 +00002601 return MatchOperand_NoMatch;
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00002602
2603 Parser.Lex(); // Eat identifier token.
2604 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
Jim Grosbachf922c472011-02-12 01:34:40 +00002605 return MatchOperand_Success;
Owen Andersone4e5e2a2011-01-13 21:46:02 +00002606}
2607
Jim Grosbach9b8f2a02011-10-12 17:34:41 +00002608/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2609/// coproc_option : '{' imm0_255 '}'
2610ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2611parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2612 SMLoc S = Parser.getTok().getLoc();
2613
2614 // If this isn't a '{', this isn't a coprocessor immediate operand.
2615 if (Parser.getTok().isNot(AsmToken::LCurly))
2616 return MatchOperand_NoMatch;
2617 Parser.Lex(); // Eat the '{'
2618
2619 const MCExpr *Expr;
2620 SMLoc Loc = Parser.getTok().getLoc();
2621 if (getParser().ParseExpression(Expr)) {
2622 Error(Loc, "illegal expression");
2623 return MatchOperand_ParseFail;
2624 }
2625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2626 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2627 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2628 return MatchOperand_ParseFail;
2629 }
2630 int Val = CE->getValue();
2631
2632 // Check for and consume the closing '}'
2633 if (Parser.getTok().isNot(AsmToken::RCurly))
2634 return MatchOperand_ParseFail;
2635 SMLoc E = Parser.getTok().getLoc();
2636 Parser.Lex(); // Eat the '}'
2637
2638 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2639 return MatchOperand_Success;
2640}
2641
Jim Grosbachd0588e22011-09-14 18:08:35 +00002642// For register list parsing, we need to map from raw GPR register numbering
2643// to the enumeration values. The enumeration values aren't sorted by
2644// register number due to our using "sp", "lr" and "pc" as canonical names.
2645static unsigned getNextRegister(unsigned Reg) {
2646 // If this is a GPR, we need to do it manually, otherwise we can rely
2647 // on the sort ordering of the enumeration since the other reg-classes
2648 // are sane.
2649 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2650 return Reg + 1;
2651 switch(Reg) {
2652 default: assert(0 && "Invalid GPR number!");
2653 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2654 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2655 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2656 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2657 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2658 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2659 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2660 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2661 }
2662}
2663
Jim Grosbachce485e72011-11-11 21:27:40 +00002664// Return the low-subreg of a given Q register.
2665static unsigned getDRegFromQReg(unsigned QReg) {
2666 switch (QReg) {
2667 default: llvm_unreachable("expected a Q register!");
2668 case ARM::Q0: return ARM::D0;
2669 case ARM::Q1: return ARM::D2;
2670 case ARM::Q2: return ARM::D4;
2671 case ARM::Q3: return ARM::D6;
2672 case ARM::Q4: return ARM::D8;
2673 case ARM::Q5: return ARM::D10;
2674 case ARM::Q6: return ARM::D12;
2675 case ARM::Q7: return ARM::D14;
2676 case ARM::Q8: return ARM::D16;
Jim Grosbach25e0a872011-11-15 21:01:30 +00002677 case ARM::Q9: return ARM::D18;
Jim Grosbachce485e72011-11-11 21:27:40 +00002678 case ARM::Q10: return ARM::D20;
2679 case ARM::Q11: return ARM::D22;
2680 case ARM::Q12: return ARM::D24;
2681 case ARM::Q13: return ARM::D26;
2682 case ARM::Q14: return ARM::D28;
2683 case ARM::Q15: return ARM::D30;
2684 }
2685}
2686
Jim Grosbachd0588e22011-09-14 18:08:35 +00002687/// Parse a register list.
Bill Wendling50d0f582010-11-18 23:43:05 +00002688bool ARMAsmParser::
Jim Grosbach1355cf12011-07-26 17:10:22 +00002689parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Sean Callanan18b83232010-01-19 21:44:56 +00002690 assert(Parser.getTok().is(AsmToken::LCurly) &&
Bill Wendlinga60f1572010-11-06 10:48:18 +00002691 "Token is not a Left Curly Brace");
Bill Wendlinge7176102010-11-06 22:36:58 +00002692 SMLoc S = Parser.getTok().getLoc();
Jim Grosbachd0588e22011-09-14 18:08:35 +00002693 Parser.Lex(); // Eat '{' token.
2694 SMLoc RegLoc = Parser.getTok().getLoc();
Kevin Enderbyd7894f12009-10-09 21:12:28 +00002695
Jim Grosbachd0588e22011-09-14 18:08:35 +00002696 // Check the first register in the list to see what register class
2697 // this is a list of.
2698 int Reg = tryParseRegister();
2699 if (Reg == -1)
2700 return Error(RegLoc, "register expected");
2701
Jim Grosbachce485e72011-11-11 21:27:40 +00002702 // The reglist instructions have at most 16 registers, so reserve
2703 // space for that many.
2704 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2705
2706 // Allow Q regs and just interpret them as the two D sub-registers.
2707 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2708 Reg = getDRegFromQReg(Reg);
2709 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2710 ++Reg;
2711 }
Benjamin Kramer1a2f9882011-10-22 16:50:00 +00002712 const MCRegisterClass *RC;
Jim Grosbachd0588e22011-09-14 18:08:35 +00002713 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2714 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2715 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2716 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2717 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2718 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2719 else
2720 return Error(RegLoc, "invalid register in register list");
2721
Jim Grosbachce485e72011-11-11 21:27:40 +00002722 // Store the register.
Jim Grosbachd0588e22011-09-14 18:08:35 +00002723 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
Kevin Enderbyd7894f12009-10-09 21:12:28 +00002724
Jim Grosbachd0588e22011-09-14 18:08:35 +00002725 // This starts immediately after the first register token in the list,
2726 // so we can see either a comma or a minus (range separator) as a legal
2727 // next token.
2728 while (Parser.getTok().is(AsmToken::Comma) ||
2729 Parser.getTok().is(AsmToken::Minus)) {
2730 if (Parser.getTok().is(AsmToken::Minus)) {
Jim Grosbache43862b2011-11-15 23:19:15 +00002731 Parser.Lex(); // Eat the minus.
Jim Grosbachd0588e22011-09-14 18:08:35 +00002732 SMLoc EndLoc = Parser.getTok().getLoc();
2733 int EndReg = tryParseRegister();
2734 if (EndReg == -1)
2735 return Error(EndLoc, "register expected");
Jim Grosbachce485e72011-11-11 21:27:40 +00002736 // Allow Q regs and just interpret them as the two D sub-registers.
2737 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2738 EndReg = getDRegFromQReg(EndReg) + 1;
Jim Grosbachd0588e22011-09-14 18:08:35 +00002739 // If the register is the same as the start reg, there's nothing
2740 // more to do.
2741 if (Reg == EndReg)
2742 continue;
2743 // The register must be in the same register class as the first.
2744 if (!RC->contains(EndReg))
2745 return Error(EndLoc, "invalid register in register list");
2746 // Ranges must go from low to high.
2747 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2748 return Error(EndLoc, "bad range in register list");
Kevin Enderbyd7894f12009-10-09 21:12:28 +00002749
Jim Grosbachd0588e22011-09-14 18:08:35 +00002750 // Add all the registers in the range to the register list.
2751 while (Reg != EndReg) {
2752 Reg = getNextRegister(Reg);
2753 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2754 }
2755 continue;
2756 }
2757 Parser.Lex(); // Eat the comma.
2758 RegLoc = Parser.getTok().getLoc();
2759 int OldReg = Reg;
Jim Grosbacha62d11e2011-12-08 21:34:20 +00002760 const AsmToken RegTok = Parser.getTok();
Jim Grosbachd0588e22011-09-14 18:08:35 +00002761 Reg = tryParseRegister();
2762 if (Reg == -1)
Jim Grosbach2d539692011-09-12 23:36:42 +00002763 return Error(RegLoc, "register expected");
Jim Grosbachce485e72011-11-11 21:27:40 +00002764 // Allow Q regs and just interpret them as the two D sub-registers.
2765 bool isQReg = false;
2766 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2767 Reg = getDRegFromQReg(Reg);
2768 isQReg = true;
2769 }
Jim Grosbachd0588e22011-09-14 18:08:35 +00002770 // The register must be in the same register class as the first.
2771 if (!RC->contains(Reg))
2772 return Error(RegLoc, "invalid register in register list");
2773 // List must be monotonically increasing.
Jim Grosbacha62d11e2011-12-08 21:34:20 +00002774 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg))
Jim Grosbachd0588e22011-09-14 18:08:35 +00002775 return Error(RegLoc, "register list not in ascending order");
Jim Grosbacha62d11e2011-12-08 21:34:20 +00002776 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
2777 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2778 ") in register list");
2779 continue;
2780 }
Jim Grosbachd0588e22011-09-14 18:08:35 +00002781 // VFP register lists must also be contiguous.
2782 // It's OK to use the enumeration values directly here rather, as the
2783 // VFP register classes have the enum sorted properly.
2784 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2785 Reg != OldReg + 1)
2786 return Error(RegLoc, "non-contiguous register range");
2787 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
Jim Grosbachce485e72011-11-11 21:27:40 +00002788 if (isQReg)
2789 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
Bill Wendlinge7176102010-11-06 22:36:58 +00002790 }
2791
Jim Grosbachd0588e22011-09-14 18:08:35 +00002792 SMLoc E = Parser.getTok().getLoc();
2793 if (Parser.getTok().isNot(AsmToken::RCurly))
2794 return Error(E, "'}' expected");
2795 Parser.Lex(); // Eat '}' token.
2796
Jim Grosbach27debd62011-12-13 21:48:29 +00002797 // Push the register list operand.
Bill Wendling50d0f582010-11-18 23:43:05 +00002798 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
Jim Grosbach27debd62011-12-13 21:48:29 +00002799
2800 // The ARM system instruction variants for LDM/STM have a '^' token here.
2801 if (Parser.getTok().is(AsmToken::Caret)) {
2802 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2803 Parser.Lex(); // Eat '^' token.
2804 }
2805
Bill Wendling50d0f582010-11-18 23:43:05 +00002806 return false;
Kevin Enderbyd7894f12009-10-09 21:12:28 +00002807}
2808
Jim Grosbach98b05a52011-11-30 01:09:44 +00002809// Helper function to parse the lane index for vector lists.
2810ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach7636bf62011-12-02 00:35:16 +00002811parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2812 Index = 0; // Always return a defined index value.
Jim Grosbach98b05a52011-11-30 01:09:44 +00002813 if (Parser.getTok().is(AsmToken::LBrac)) {
2814 Parser.Lex(); // Eat the '['.
2815 if (Parser.getTok().is(AsmToken::RBrac)) {
2816 // "Dn[]" is the 'all lanes' syntax.
2817 LaneKind = AllLanes;
2818 Parser.Lex(); // Eat the ']'.
2819 return MatchOperand_Success;
2820 }
Jim Grosbachc9313252011-12-21 01:19:23 +00002821 const MCExpr *LaneIndex;
2822 SMLoc Loc = Parser.getTok().getLoc();
2823 if (getParser().ParseExpression(LaneIndex)) {
2824 Error(Loc, "illegal expression");
2825 return MatchOperand_ParseFail;
Jim Grosbach7636bf62011-12-02 00:35:16 +00002826 }
Jim Grosbachc9313252011-12-21 01:19:23 +00002827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
2828 if (!CE) {
2829 Error(Loc, "lane index must be empty or an integer");
2830 return MatchOperand_ParseFail;
2831 }
2832 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2833 Error(Parser.getTok().getLoc(), "']' expected");
2834 return MatchOperand_ParseFail;
2835 }
2836 Parser.Lex(); // Eat the ']'.
2837 int64_t Val = CE->getValue();
2838
2839 // FIXME: Make this range check context sensitive for .8, .16, .32.
2840 if (Val < 0 || Val > 7) {
2841 Error(Parser.getTok().getLoc(), "lane index out of range");
2842 return MatchOperand_ParseFail;
2843 }
2844 Index = Val;
2845 LaneKind = IndexedLane;
2846 return MatchOperand_Success;
Jim Grosbach98b05a52011-11-30 01:09:44 +00002847 }
2848 LaneKind = NoLanes;
2849 return MatchOperand_Success;
2850}
2851
Jim Grosbach862019c2011-10-18 23:02:30 +00002852// parse a vector register list
2853ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2854parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbach98b05a52011-11-30 01:09:44 +00002855 VectorLaneTy LaneKind;
Jim Grosbach7636bf62011-12-02 00:35:16 +00002856 unsigned LaneIndex;
Jim Grosbach5c984e42011-11-15 21:45:55 +00002857 SMLoc S = Parser.getTok().getLoc();
2858 // As an extension (to match gas), support a plain D register or Q register
2859 // (without encosing curly braces) as a single or double entry list,
2860 // respectively.
2861 if (Parser.getTok().is(AsmToken::Identifier)) {
2862 int Reg = tryParseRegister();
2863 if (Reg == -1)
2864 return MatchOperand_NoMatch;
2865 SMLoc E = Parser.getTok().getLoc();
2866 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
Jim Grosbach7636bf62011-12-02 00:35:16 +00002867 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
Jim Grosbach98b05a52011-11-30 01:09:44 +00002868 if (Res != MatchOperand_Success)
2869 return Res;
2870 switch (LaneKind) {
Jim Grosbach98b05a52011-11-30 01:09:44 +00002871 case NoLanes:
2872 E = Parser.getTok().getLoc();
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00002873 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
Jim Grosbach98b05a52011-11-30 01:09:44 +00002874 break;
2875 case AllLanes:
2876 E = Parser.getTok().getLoc();
Jim Grosbach3471d4f2011-12-21 00:38:54 +00002877 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
2878 S, E));
Jim Grosbach98b05a52011-11-30 01:09:44 +00002879 break;
Jim Grosbach7636bf62011-12-02 00:35:16 +00002880 case IndexedLane:
2881 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
Jim Grosbach95fad1c2011-12-20 19:21:26 +00002882 LaneIndex,
2883 false, S, E));
Jim Grosbach7636bf62011-12-02 00:35:16 +00002884 break;
Jim Grosbach98b05a52011-11-30 01:09:44 +00002885 }
Jim Grosbach5c984e42011-11-15 21:45:55 +00002886 return MatchOperand_Success;
2887 }
2888 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2889 Reg = getDRegFromQReg(Reg);
Jim Grosbach7636bf62011-12-02 00:35:16 +00002890 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
Jim Grosbach98b05a52011-11-30 01:09:44 +00002891 if (Res != MatchOperand_Success)
2892 return Res;
2893 switch (LaneKind) {
Jim Grosbach98b05a52011-11-30 01:09:44 +00002894 case NoLanes:
2895 E = Parser.getTok().getLoc();
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00002896 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
Jim Grosbach98b05a52011-11-30 01:09:44 +00002897 break;
2898 case AllLanes:
2899 E = Parser.getTok().getLoc();
Jim Grosbach3471d4f2011-12-21 00:38:54 +00002900 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
2901 S, E));
Jim Grosbach98b05a52011-11-30 01:09:44 +00002902 break;
Jim Grosbach7636bf62011-12-02 00:35:16 +00002903 case IndexedLane:
2904 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
Jim Grosbach95fad1c2011-12-20 19:21:26 +00002905 LaneIndex,
2906 false, S, E));
Jim Grosbach7636bf62011-12-02 00:35:16 +00002907 break;
Jim Grosbach98b05a52011-11-30 01:09:44 +00002908 }
Jim Grosbach5c984e42011-11-15 21:45:55 +00002909 return MatchOperand_Success;
2910 }
2911 Error(S, "vector register expected");
2912 return MatchOperand_ParseFail;
2913 }
2914
2915 if (Parser.getTok().isNot(AsmToken::LCurly))
Jim Grosbach862019c2011-10-18 23:02:30 +00002916 return MatchOperand_NoMatch;
2917
Jim Grosbach862019c2011-10-18 23:02:30 +00002918 Parser.Lex(); // Eat '{' token.
2919 SMLoc RegLoc = Parser.getTok().getLoc();
2920
2921 int Reg = tryParseRegister();
2922 if (Reg == -1) {
2923 Error(RegLoc, "register expected");
2924 return MatchOperand_ParseFail;
2925 }
Jim Grosbach862019c2011-10-18 23:02:30 +00002926 unsigned Count = 1;
Jim Grosbach276ed032011-12-15 21:54:55 +00002927 int Spacing = 0;
Jim Grosbachc73d73e2011-10-28 00:06:50 +00002928 unsigned FirstReg = Reg;
2929 // The list is of D registers, but we also allow Q regs and just interpret
2930 // them as the two D sub-registers.
2931 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2932 FirstReg = Reg = getDRegFromQReg(Reg);
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00002933 Spacing = 1; // double-spacing requires explicit D registers, otherwise
2934 // it's ambiguous with four-register single spaced.
Jim Grosbachc73d73e2011-10-28 00:06:50 +00002935 ++Reg;
2936 ++Count;
2937 }
Jim Grosbach7636bf62011-12-02 00:35:16 +00002938 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
Jim Grosbach98b05a52011-11-30 01:09:44 +00002939 return MatchOperand_ParseFail;
Jim Grosbachc73d73e2011-10-28 00:06:50 +00002940
Jim Grosbache43862b2011-11-15 23:19:15 +00002941 while (Parser.getTok().is(AsmToken::Comma) ||
2942 Parser.getTok().is(AsmToken::Minus)) {
2943 if (Parser.getTok().is(AsmToken::Minus)) {
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00002944 if (!Spacing)
2945 Spacing = 1; // Register range implies a single spaced list.
2946 else if (Spacing == 2) {
2947 Error(Parser.getTok().getLoc(),
2948 "sequential registers in double spaced list");
2949 return MatchOperand_ParseFail;
2950 }
Jim Grosbache43862b2011-11-15 23:19:15 +00002951 Parser.Lex(); // Eat the minus.
2952 SMLoc EndLoc = Parser.getTok().getLoc();
2953 int EndReg = tryParseRegister();
2954 if (EndReg == -1) {
2955 Error(EndLoc, "register expected");
2956 return MatchOperand_ParseFail;
2957 }
2958 // Allow Q regs and just interpret them as the two D sub-registers.
2959 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2960 EndReg = getDRegFromQReg(EndReg) + 1;
2961 // If the register is the same as the start reg, there's nothing
2962 // more to do.
2963 if (Reg == EndReg)
2964 continue;
2965 // The register must be in the same register class as the first.
2966 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
2967 Error(EndLoc, "invalid register in register list");
2968 return MatchOperand_ParseFail;
2969 }
2970 // Ranges must go from low to high.
2971 if (Reg > EndReg) {
2972 Error(EndLoc, "bad range in register list");
2973 return MatchOperand_ParseFail;
2974 }
Jim Grosbach98b05a52011-11-30 01:09:44 +00002975 // Parse the lane specifier if present.
2976 VectorLaneTy NextLaneKind;
Jim Grosbach7636bf62011-12-02 00:35:16 +00002977 unsigned NextLaneIndex;
2978 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
Jim Grosbach98b05a52011-11-30 01:09:44 +00002979 return MatchOperand_ParseFail;
Jim Grosbach7636bf62011-12-02 00:35:16 +00002980 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Jim Grosbach98b05a52011-11-30 01:09:44 +00002981 Error(EndLoc, "mismatched lane index in register list");
2982 return MatchOperand_ParseFail;
2983 }
2984 EndLoc = Parser.getTok().getLoc();
Jim Grosbache43862b2011-11-15 23:19:15 +00002985
2986 // Add all the registers in the range to the register list.
2987 Count += EndReg - Reg;
2988 Reg = EndReg;
2989 continue;
2990 }
Jim Grosbach862019c2011-10-18 23:02:30 +00002991 Parser.Lex(); // Eat the comma.
2992 RegLoc = Parser.getTok().getLoc();
2993 int OldReg = Reg;
2994 Reg = tryParseRegister();
2995 if (Reg == -1) {
2996 Error(RegLoc, "register expected");
2997 return MatchOperand_ParseFail;
2998 }
Jim Grosbachc73d73e2011-10-28 00:06:50 +00002999 // vector register lists must be contiguous.
Jim Grosbach862019c2011-10-18 23:02:30 +00003000 // It's OK to use the enumeration values directly here rather, as the
3001 // VFP register classes have the enum sorted properly.
Jim Grosbachc73d73e2011-10-28 00:06:50 +00003002 //
3003 // The list is of D registers, but we also allow Q regs and just interpret
3004 // them as the two D sub-registers.
3005 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00003006 if (!Spacing)
3007 Spacing = 1; // Register range implies a single spaced list.
3008 else if (Spacing == 2) {
3009 Error(RegLoc,
3010 "invalid register in double-spaced list (must be 'D' register')");
3011 return MatchOperand_ParseFail;
3012 }
Jim Grosbachc73d73e2011-10-28 00:06:50 +00003013 Reg = getDRegFromQReg(Reg);
3014 if (Reg != OldReg + 1) {
3015 Error(RegLoc, "non-contiguous register range");
3016 return MatchOperand_ParseFail;
3017 }
3018 ++Reg;
3019 Count += 2;
Jim Grosbach98b05a52011-11-30 01:09:44 +00003020 // Parse the lane specifier if present.
3021 VectorLaneTy NextLaneKind;
Jim Grosbach7636bf62011-12-02 00:35:16 +00003022 unsigned NextLaneIndex;
Jim Grosbach98b05a52011-11-30 01:09:44 +00003023 SMLoc EndLoc = Parser.getTok().getLoc();
Jim Grosbach7636bf62011-12-02 00:35:16 +00003024 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
Jim Grosbach98b05a52011-11-30 01:09:44 +00003025 return MatchOperand_ParseFail;
Jim Grosbach7636bf62011-12-02 00:35:16 +00003026 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Jim Grosbach98b05a52011-11-30 01:09:44 +00003027 Error(EndLoc, "mismatched lane index in register list");
3028 return MatchOperand_ParseFail;
3029 }
Jim Grosbachc73d73e2011-10-28 00:06:50 +00003030 continue;
3031 }
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00003032 // Normal D register.
3033 // Figure out the register spacing (single or double) of the list if
3034 // we don't know it already.
3035 if (!Spacing)
3036 Spacing = 1 + (Reg == OldReg + 2);
3037
3038 // Just check that it's contiguous and keep going.
3039 if (Reg != OldReg + Spacing) {
Jim Grosbach862019c2011-10-18 23:02:30 +00003040 Error(RegLoc, "non-contiguous register range");
3041 return MatchOperand_ParseFail;
3042 }
Jim Grosbach862019c2011-10-18 23:02:30 +00003043 ++Count;
Jim Grosbach98b05a52011-11-30 01:09:44 +00003044 // Parse the lane specifier if present.
3045 VectorLaneTy NextLaneKind;
Jim Grosbach7636bf62011-12-02 00:35:16 +00003046 unsigned NextLaneIndex;
Jim Grosbach98b05a52011-11-30 01:09:44 +00003047 SMLoc EndLoc = Parser.getTok().getLoc();
Jim Grosbach7636bf62011-12-02 00:35:16 +00003048 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
Jim Grosbach98b05a52011-11-30 01:09:44 +00003049 return MatchOperand_ParseFail;
Jim Grosbach7636bf62011-12-02 00:35:16 +00003050 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Jim Grosbach98b05a52011-11-30 01:09:44 +00003051 Error(EndLoc, "mismatched lane index in register list");
3052 return MatchOperand_ParseFail;
3053 }
Jim Grosbach862019c2011-10-18 23:02:30 +00003054 }
3055
3056 SMLoc E = Parser.getTok().getLoc();
3057 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3058 Error(E, "'}' expected");
3059 return MatchOperand_ParseFail;
3060 }
3061 Parser.Lex(); // Eat '}' token.
3062
Jim Grosbach98b05a52011-11-30 01:09:44 +00003063 switch (LaneKind) {
Jim Grosbach98b05a52011-11-30 01:09:44 +00003064 case NoLanes:
Jim Grosbach0aaf4cd2011-12-15 21:44:33 +00003065 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3066 (Spacing == 2), S, E));
Jim Grosbach98b05a52011-11-30 01:09:44 +00003067 break;
3068 case AllLanes:
3069 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
Jim Grosbach3471d4f2011-12-21 00:38:54 +00003070 (Spacing == 2),
Jim Grosbach98b05a52011-11-30 01:09:44 +00003071 S, E));
3072 break;
Jim Grosbach7636bf62011-12-02 00:35:16 +00003073 case IndexedLane:
3074 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
Jim Grosbach95fad1c2011-12-20 19:21:26 +00003075 LaneIndex,
3076 (Spacing == 2),
3077 S, E));
Jim Grosbach7636bf62011-12-02 00:35:16 +00003078 break;
Jim Grosbach98b05a52011-11-30 01:09:44 +00003079 }
Jim Grosbach862019c2011-10-18 23:02:30 +00003080 return MatchOperand_Success;
3081}
3082
Jim Grosbach43904292011-07-25 20:14:50 +00003083/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
Jim Grosbachf922c472011-02-12 01:34:40 +00003084ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach43904292011-07-25 20:14:50 +00003085parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00003086 SMLoc S = Parser.getTok().getLoc();
3087 const AsmToken &Tok = Parser.getTok();
3088 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3089 StringRef OptStr = Tok.getString();
3090
3091 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
3092 .Case("sy", ARM_MB::SY)
3093 .Case("st", ARM_MB::ST)
Jim Grosbach032434d2011-07-13 23:40:38 +00003094 .Case("sh", ARM_MB::ISH)
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00003095 .Case("ish", ARM_MB::ISH)
Jim Grosbach032434d2011-07-13 23:40:38 +00003096 .Case("shst", ARM_MB::ISHST)
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00003097 .Case("ishst", ARM_MB::ISHST)
3098 .Case("nsh", ARM_MB::NSH)
Jim Grosbach032434d2011-07-13 23:40:38 +00003099 .Case("un", ARM_MB::NSH)
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00003100 .Case("nshst", ARM_MB::NSHST)
Jim Grosbach032434d2011-07-13 23:40:38 +00003101 .Case("unst", ARM_MB::NSHST)
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00003102 .Case("osh", ARM_MB::OSH)
3103 .Case("oshst", ARM_MB::OSHST)
3104 .Default(~0U);
3105
3106 if (Opt == ~0U)
Jim Grosbachf922c472011-02-12 01:34:40 +00003107 return MatchOperand_NoMatch;
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00003108
3109 Parser.Lex(); // Eat identifier token.
3110 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
Jim Grosbachf922c472011-02-12 01:34:40 +00003111 return MatchOperand_Success;
Bruno Cardoso Lopes706d9462011-02-07 22:09:15 +00003112}
3113
Jim Grosbach43904292011-07-25 20:14:50 +00003114/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00003115ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach43904292011-07-25 20:14:50 +00003116parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00003117 SMLoc S = Parser.getTok().getLoc();
3118 const AsmToken &Tok = Parser.getTok();
3119 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3120 StringRef IFlagsStr = Tok.getString();
3121
Owen Anderson2dbb46a2011-10-05 17:16:40 +00003122 // An iflags string of "none" is interpreted to mean that none of the AIF
3123 // bits are set. Not a terribly useful instruction, but a valid encoding.
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00003124 unsigned IFlags = 0;
Owen Anderson2dbb46a2011-10-05 17:16:40 +00003125 if (IFlagsStr != "none") {
3126 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3127 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3128 .Case("a", ARM_PROC::A)
3129 .Case("i", ARM_PROC::I)
3130 .Case("f", ARM_PROC::F)
3131 .Default(~0U);
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00003132
Owen Anderson2dbb46a2011-10-05 17:16:40 +00003133 // If some specific iflag is already set, it means that some letter is
3134 // present more than once, this is not acceptable.
3135 if (Flag == ~0U || (IFlags & Flag))
3136 return MatchOperand_NoMatch;
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00003137
Owen Anderson2dbb46a2011-10-05 17:16:40 +00003138 IFlags |= Flag;
3139 }
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00003140 }
3141
3142 Parser.Lex(); // Eat identifier token.
3143 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3144 return MatchOperand_Success;
3145}
3146
Jim Grosbach43904292011-07-25 20:14:50 +00003147/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003148ARMAsmParser::OperandMatchResultTy ARMAsmParser::
Jim Grosbach43904292011-07-25 20:14:50 +00003149parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003150 SMLoc S = Parser.getTok().getLoc();
3151 const AsmToken &Tok = Parser.getTok();
3152 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3153 StringRef Mask = Tok.getString();
3154
James Molloyacad68d2011-09-28 14:21:38 +00003155 if (isMClass()) {
3156 // See ARMv6-M 10.1.1
3157 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
3158 .Case("apsr", 0)
3159 .Case("iapsr", 1)
3160 .Case("eapsr", 2)
3161 .Case("xpsr", 3)
3162 .Case("ipsr", 5)
3163 .Case("epsr", 6)
3164 .Case("iepsr", 7)
3165 .Case("msp", 8)
3166 .Case("psp", 9)
3167 .Case("primask", 16)
3168 .Case("basepri", 17)
3169 .Case("basepri_max", 18)
3170 .Case("faultmask", 19)
3171 .Case("control", 20)
3172 .Default(~0U);
Jim Grosbach18c8d122011-12-22 17:17:10 +00003173
James Molloyacad68d2011-09-28 14:21:38 +00003174 if (FlagsVal == ~0U)
3175 return MatchOperand_NoMatch;
3176
3177 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
3178 // basepri, basepri_max and faultmask only valid for V7m.
3179 return MatchOperand_NoMatch;
Jim Grosbach18c8d122011-12-22 17:17:10 +00003180
James Molloyacad68d2011-09-28 14:21:38 +00003181 Parser.Lex(); // Eat identifier token.
3182 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3183 return MatchOperand_Success;
3184 }
3185
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003186 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3187 size_t Start = 0, Next = Mask.find('_');
3188 StringRef Flags = "";
Benjamin Kramer59085362011-11-06 20:37:06 +00003189 std::string SpecReg = Mask.slice(Start, Next).lower();
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003190 if (Next != StringRef::npos)
3191 Flags = Mask.slice(Next+1, Mask.size());
3192
3193 // FlagsVal contains the complete mask:
3194 // 3-0: Mask
3195 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3196 unsigned FlagsVal = 0;
3197
3198 if (SpecReg == "apsr") {
3199 FlagsVal = StringSwitch<unsigned>(Flags)
Jim Grosbachb29b4dd2011-07-19 22:45:10 +00003200 .Case("nzcvq", 0x8) // same as CPSR_f
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003201 .Case("g", 0x4) // same as CPSR_s
3202 .Case("nzcvqg", 0xc) // same as CPSR_fs
3203 .Default(~0U);
3204
Joerg Sonnenberger4b19c982011-02-19 00:43:45 +00003205 if (FlagsVal == ~0U) {
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003206 if (!Flags.empty())
3207 return MatchOperand_NoMatch;
3208 else
Jim Grosbachbf841cf2011-09-14 20:03:46 +00003209 FlagsVal = 8; // No flag
Joerg Sonnenberger4b19c982011-02-19 00:43:45 +00003210 }
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003211 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
Bruno Cardoso Lopes56926a32011-05-25 00:35:03 +00003212 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
3213 Flags = "fc";
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003214 for (int i = 0, e = Flags.size(); i != e; ++i) {
3215 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3216 .Case("c", 1)
3217 .Case("x", 2)
3218 .Case("s", 4)
3219 .Case("f", 8)
3220 .Default(~0U);
3221
3222 // If some specific flag is already set, it means that some letter is
3223 // present more than once, this is not acceptable.
3224 if (FlagsVal == ~0U || (FlagsVal & Flag))
3225 return MatchOperand_NoMatch;
3226 FlagsVal |= Flag;
3227 }
3228 } else // No match for special register.
3229 return MatchOperand_NoMatch;
3230
Owen Anderson7784f1d2011-10-21 18:43:28 +00003231 // Special register without flags is NOT equivalent to "fc" flags.
3232 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3233 // two lines would enable gas compatibility at the expense of breaking
3234 // round-tripping.
3235 //
3236 // if (!FlagsVal)
3237 // FlagsVal = 0x9;
Bruno Cardoso Lopes584bf7b2011-02-18 19:45:59 +00003238
3239 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3240 if (SpecReg == "spsr")
3241 FlagsVal |= 16;
3242
3243 Parser.Lex(); // Eat identifier token.
3244 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3245 return MatchOperand_Success;
3246}
3247
Jim Grosbachf6c05252011-07-21 17:23:04 +00003248ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3249parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3250 int Low, int High) {
3251 const AsmToken &Tok = Parser.getTok();
3252 if (Tok.isNot(AsmToken::Identifier)) {
3253 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3254 return MatchOperand_ParseFail;
3255 }
3256 StringRef ShiftName = Tok.getString();
Benjamin Kramer59085362011-11-06 20:37:06 +00003257 std::string LowerOp = Op.lower();
3258 std::string UpperOp = Op.upper();
Jim Grosbachf6c05252011-07-21 17:23:04 +00003259 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3260 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3261 return MatchOperand_ParseFail;
3262 }
3263 Parser.Lex(); // Eat shift type token.
3264
3265 // There must be a '#' and a shift amount.
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00003266 if (Parser.getTok().isNot(AsmToken::Hash) &&
3267 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbachf6c05252011-07-21 17:23:04 +00003268 Error(Parser.getTok().getLoc(), "'#' expected");
3269 return MatchOperand_ParseFail;
3270 }
3271 Parser.Lex(); // Eat hash token.
3272
3273 const MCExpr *ShiftAmount;
3274 SMLoc Loc = Parser.getTok().getLoc();
3275 if (getParser().ParseExpression(ShiftAmount)) {
3276 Error(Loc, "illegal expression");
3277 return MatchOperand_ParseFail;
3278 }
3279 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3280 if (!CE) {
3281 Error(Loc, "constant expression expected");
3282 return MatchOperand_ParseFail;
3283 }
3284 int Val = CE->getValue();
3285 if (Val < Low || Val > High) {
3286 Error(Loc, "immediate value out of range");
3287 return MatchOperand_ParseFail;
3288 }
3289
3290 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3291
3292 return MatchOperand_Success;
3293}
3294
Jim Grosbachc27d4f92011-07-22 17:44:50 +00003295ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3296parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3297 const AsmToken &Tok = Parser.getTok();
3298 SMLoc S = Tok.getLoc();
3299 if (Tok.isNot(AsmToken::Identifier)) {
3300 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3301 return MatchOperand_ParseFail;
3302 }
3303 int Val = StringSwitch<int>(Tok.getString())
3304 .Case("be", 1)
3305 .Case("le", 0)
3306 .Default(-1);
3307 Parser.Lex(); // Eat the token.
3308
3309 if (Val == -1) {
3310 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3311 return MatchOperand_ParseFail;
3312 }
3313 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3314 getContext()),
3315 S, Parser.getTok().getLoc()));
3316 return MatchOperand_Success;
3317}
3318
Jim Grosbach580f4a92011-07-25 22:20:28 +00003319/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3320/// instructions. Legal values are:
3321/// lsl #n 'n' in [0,31]
3322/// asr #n 'n' in [1,32]
3323/// n == 32 encoded as n == 0.
3324ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3325parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3326 const AsmToken &Tok = Parser.getTok();
3327 SMLoc S = Tok.getLoc();
3328 if (Tok.isNot(AsmToken::Identifier)) {
3329 Error(S, "shift operator 'asr' or 'lsl' expected");
3330 return MatchOperand_ParseFail;
3331 }
3332 StringRef ShiftName = Tok.getString();
3333 bool isASR;
3334 if (ShiftName == "lsl" || ShiftName == "LSL")
3335 isASR = false;
3336 else if (ShiftName == "asr" || ShiftName == "ASR")
3337 isASR = true;
3338 else {
3339 Error(S, "shift operator 'asr' or 'lsl' expected");
3340 return MatchOperand_ParseFail;
3341 }
3342 Parser.Lex(); // Eat the operator.
3343
3344 // A '#' and a shift amount.
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00003345 if (Parser.getTok().isNot(AsmToken::Hash) &&
3346 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach580f4a92011-07-25 22:20:28 +00003347 Error(Parser.getTok().getLoc(), "'#' expected");
3348 return MatchOperand_ParseFail;
3349 }
3350 Parser.Lex(); // Eat hash token.
3351
3352 const MCExpr *ShiftAmount;
3353 SMLoc E = Parser.getTok().getLoc();
3354 if (getParser().ParseExpression(ShiftAmount)) {
3355 Error(E, "malformed shift expression");
3356 return MatchOperand_ParseFail;
3357 }
3358 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3359 if (!CE) {
3360 Error(E, "shift amount must be an immediate");
3361 return MatchOperand_ParseFail;
3362 }
3363
3364 int64_t Val = CE->getValue();
3365 if (isASR) {
3366 // Shift amount must be in [1,32]
3367 if (Val < 1 || Val > 32) {
3368 Error(E, "'asr' shift amount must be in range [1,32]");
3369 return MatchOperand_ParseFail;
3370 }
Owen Anderson0afa0092011-09-26 21:06:22 +00003371 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3372 if (isThumb() && Val == 32) {
3373 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3374 return MatchOperand_ParseFail;
3375 }
Jim Grosbach580f4a92011-07-25 22:20:28 +00003376 if (Val == 32) Val = 0;
3377 } else {
3378 // Shift amount must be in [1,32]
3379 if (Val < 0 || Val > 31) {
3380 Error(E, "'lsr' shift amount must be in range [0,31]");
3381 return MatchOperand_ParseFail;
3382 }
3383 }
3384
3385 E = Parser.getTok().getLoc();
3386 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3387
3388 return MatchOperand_Success;
3389}
3390
Jim Grosbach7e1547e2011-07-27 20:15:40 +00003391/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3392/// of instructions. Legal values are:
3393/// ror #n 'n' in {0, 8, 16, 24}
3394ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3395parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3396 const AsmToken &Tok = Parser.getTok();
3397 SMLoc S = Tok.getLoc();
Jim Grosbach326efe52011-09-19 20:29:33 +00003398 if (Tok.isNot(AsmToken::Identifier))
3399 return MatchOperand_NoMatch;
Jim Grosbach7e1547e2011-07-27 20:15:40 +00003400 StringRef ShiftName = Tok.getString();
Jim Grosbach326efe52011-09-19 20:29:33 +00003401 if (ShiftName != "ror" && ShiftName != "ROR")
3402 return MatchOperand_NoMatch;
Jim Grosbach7e1547e2011-07-27 20:15:40 +00003403 Parser.Lex(); // Eat the operator.
3404
3405 // A '#' and a rotate amount.
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00003406 if (Parser.getTok().isNot(AsmToken::Hash) &&
3407 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach7e1547e2011-07-27 20:15:40 +00003408 Error(Parser.getTok().getLoc(), "'#' expected");
3409 return MatchOperand_ParseFail;
3410 }
3411 Parser.Lex(); // Eat hash token.
3412
3413 const MCExpr *ShiftAmount;
3414 SMLoc E = Parser.getTok().getLoc();
3415 if (getParser().ParseExpression(ShiftAmount)) {
3416 Error(E, "malformed rotate expression");
3417 return MatchOperand_ParseFail;
3418 }
3419 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3420 if (!CE) {
3421 Error(E, "rotate amount must be an immediate");
3422 return MatchOperand_ParseFail;
3423 }
3424
3425 int64_t Val = CE->getValue();
3426 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3427 // normally, zero is represented in asm by omitting the rotate operand
3428 // entirely.
3429 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3430 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3431 return MatchOperand_ParseFail;
3432 }
3433
3434 E = Parser.getTok().getLoc();
3435 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3436
3437 return MatchOperand_Success;
3438}
3439
Jim Grosbach293a2ee2011-07-28 21:34:26 +00003440ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3441parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3442 SMLoc S = Parser.getTok().getLoc();
3443 // The bitfield descriptor is really two operands, the LSB and the width.
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00003444 if (Parser.getTok().isNot(AsmToken::Hash) &&
3445 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach293a2ee2011-07-28 21:34:26 +00003446 Error(Parser.getTok().getLoc(), "'#' expected");
3447 return MatchOperand_ParseFail;
3448 }
3449 Parser.Lex(); // Eat hash token.
3450
3451 const MCExpr *LSBExpr;
3452 SMLoc E = Parser.getTok().getLoc();
3453 if (getParser().ParseExpression(LSBExpr)) {
3454 Error(E, "malformed immediate expression");
3455 return MatchOperand_ParseFail;
3456 }
3457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3458 if (!CE) {
3459 Error(E, "'lsb' operand must be an immediate");
3460 return MatchOperand_ParseFail;
3461 }
3462
3463 int64_t LSB = CE->getValue();
3464 // The LSB must be in the range [0,31]
3465 if (LSB < 0 || LSB > 31) {
3466 Error(E, "'lsb' operand must be in the range [0,31]");
3467 return MatchOperand_ParseFail;
3468 }
3469 E = Parser.getTok().getLoc();
3470
3471 // Expect another immediate operand.
3472 if (Parser.getTok().isNot(AsmToken::Comma)) {
3473 Error(Parser.getTok().getLoc(), "too few operands");
3474 return MatchOperand_ParseFail;
3475 }
3476 Parser.Lex(); // Eat hash token.
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00003477 if (Parser.getTok().isNot(AsmToken::Hash) &&
3478 Parser.getTok().isNot(AsmToken::Dollar)) {
Jim Grosbach293a2ee2011-07-28 21:34:26 +00003479 Error(Parser.getTok().getLoc(), "'#' expected");
3480 return MatchOperand_ParseFail;
3481 }
3482 Parser.Lex(); // Eat hash token.
3483
3484 const MCExpr *WidthExpr;
3485 if (getParser().ParseExpression(WidthExpr)) {
3486 Error(E, "malformed immediate expression");
3487 return MatchOperand_ParseFail;
3488 }
3489 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3490 if (!CE) {
3491 Error(E, "'width' operand must be an immediate");
3492 return MatchOperand_ParseFail;
3493 }
3494
3495 int64_t Width = CE->getValue();
3496 // The LSB must be in the range [1,32-lsb]
3497 if (Width < 1 || Width > 32 - LSB) {
3498 Error(E, "'width' operand must be in the range [1,32-lsb]");
3499 return MatchOperand_ParseFail;
3500 }
3501 E = Parser.getTok().getLoc();
3502
3503 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3504
3505 return MatchOperand_Success;
3506}
3507
Jim Grosbach7ce05792011-08-03 23:50:40 +00003508ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3509parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3510 // Check for a post-index addressing register operand. Specifically:
Jim Grosbachf4fa3d62011-08-05 21:28:30 +00003511 // postidx_reg := '+' register {, shift}
3512 // | '-' register {, shift}
3513 // | register {, shift}
Jim Grosbach7ce05792011-08-03 23:50:40 +00003514
3515 // This method must return MatchOperand_NoMatch without consuming any tokens
3516 // in the case where there is no match, as other alternatives take other
3517 // parse methods.
3518 AsmToken Tok = Parser.getTok();
3519 SMLoc S = Tok.getLoc();
3520 bool haveEaten = false;
Jim Grosbach16578b52011-08-05 16:11:38 +00003521 bool isAdd = true;
Jim Grosbach7ce05792011-08-03 23:50:40 +00003522 int Reg = -1;
3523 if (Tok.is(AsmToken::Plus)) {
3524 Parser.Lex(); // Eat the '+' token.
3525 haveEaten = true;
3526 } else if (Tok.is(AsmToken::Minus)) {
3527 Parser.Lex(); // Eat the '-' token.
Jim Grosbach16578b52011-08-05 16:11:38 +00003528 isAdd = false;
Jim Grosbach7ce05792011-08-03 23:50:40 +00003529 haveEaten = true;
3530 }
3531 if (Parser.getTok().is(AsmToken::Identifier))
3532 Reg = tryParseRegister();
3533 if (Reg == -1) {
3534 if (!haveEaten)
3535 return MatchOperand_NoMatch;
3536 Error(Parser.getTok().getLoc(), "register expected");
3537 return MatchOperand_ParseFail;
3538 }
3539 SMLoc E = Parser.getTok().getLoc();
3540
Jim Grosbachf4fa3d62011-08-05 21:28:30 +00003541 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3542 unsigned ShiftImm = 0;
Jim Grosbach0d6fac32011-08-05 22:03:36 +00003543 if (Parser.getTok().is(AsmToken::Comma)) {
3544 Parser.Lex(); // Eat the ','.
3545 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3546 return MatchOperand_ParseFail;
3547 }
Jim Grosbachf4fa3d62011-08-05 21:28:30 +00003548
3549 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3550 ShiftImm, S, E));
Jim Grosbach7ce05792011-08-03 23:50:40 +00003551
3552 return MatchOperand_Success;
3553}
3554
Jim Grosbach251bf252011-08-10 21:56:18 +00003555ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3556parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3557 // Check for a post-index addressing register operand. Specifically:
3558 // am3offset := '+' register
3559 // | '-' register
3560 // | register
3561 // | # imm
3562 // | # + imm
3563 // | # - imm
3564
3565 // This method must return MatchOperand_NoMatch without consuming any tokens
3566 // in the case where there is no match, as other alternatives take other
3567 // parse methods.
3568 AsmToken Tok = Parser.getTok();
3569 SMLoc S = Tok.getLoc();
3570
3571 // Do immediates first, as we always parse those if we have a '#'.
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00003572 if (Parser.getTok().is(AsmToken::Hash) ||
3573 Parser.getTok().is(AsmToken::Dollar)) {
Jim Grosbach251bf252011-08-10 21:56:18 +00003574 Parser.Lex(); // Eat the '#'.
3575 // Explicitly look for a '-', as we need to encode negative zero
3576 // differently.
3577 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3578 const MCExpr *Offset;
3579 if (getParser().ParseExpression(Offset))
3580 return MatchOperand_ParseFail;
3581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3582 if (!CE) {
3583 Error(S, "constant expression expected");
3584 return MatchOperand_ParseFail;
3585 }
3586 SMLoc E = Tok.getLoc();
3587 // Negative zero is encoded as the flag value INT32_MIN.
3588 int32_t Val = CE->getValue();
3589 if (isNegative && Val == 0)
3590 Val = INT32_MIN;
3591
3592 Operands.push_back(
3593 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3594
3595 return MatchOperand_Success;
3596 }
3597
3598
3599 bool haveEaten = false;
3600 bool isAdd = true;
3601 int Reg = -1;
3602 if (Tok.is(AsmToken::Plus)) {
3603 Parser.Lex(); // Eat the '+' token.
3604 haveEaten = true;
3605 } else if (Tok.is(AsmToken::Minus)) {
3606 Parser.Lex(); // Eat the '-' token.
3607 isAdd = false;
3608 haveEaten = true;
3609 }
3610 if (Parser.getTok().is(AsmToken::Identifier))
3611 Reg = tryParseRegister();
3612 if (Reg == -1) {
3613 if (!haveEaten)
3614 return MatchOperand_NoMatch;
3615 Error(Parser.getTok().getLoc(), "register expected");
3616 return MatchOperand_ParseFail;
3617 }
3618 SMLoc E = Parser.getTok().getLoc();
3619
3620 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3621 0, S, E));
3622
3623 return MatchOperand_Success;
3624}
3625
Jim Grosbacha77295d2011-09-08 22:07:06 +00003626/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3627/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3628/// when they refer multiple MIOperands inside a single one.
3629bool ARMAsmParser::
3630cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3631 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3632 // Rt, Rt2
3633 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3634 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3635 // Create a writeback register dummy placeholder.
3636 Inst.addOperand(MCOperand::CreateReg(0));
3637 // addr
3638 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3639 // pred
3640 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3641 return true;
3642}
3643
3644/// cvtT2StrdPre - Convert parsed operands to MCInst.
3645/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3646/// when they refer multiple MIOperands inside a single one.
3647bool ARMAsmParser::
3648cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3649 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3650 // Create a writeback register dummy placeholder.
3651 Inst.addOperand(MCOperand::CreateReg(0));
3652 // Rt, Rt2
3653 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3654 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3655 // addr
3656 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3657 // pred
3658 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3659 return true;
3660}
3661
Jim Grosbacheeec0252011-09-08 00:39:19 +00003662/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3663/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3664/// when they refer multiple MIOperands inside a single one.
3665bool ARMAsmParser::
3666cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3667 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3668 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3669
3670 // Create a writeback register dummy placeholder.
3671 Inst.addOperand(MCOperand::CreateImm(0));
3672
3673 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3674 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3675 return true;
3676}
3677
Jim Grosbachee2c2a42011-09-16 21:55:56 +00003678/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3679/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3680/// when they refer multiple MIOperands inside a single one.
3681bool ARMAsmParser::
3682cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3683 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3684 // Create a writeback register dummy placeholder.
3685 Inst.addOperand(MCOperand::CreateImm(0));
3686 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3687 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3688 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3689 return true;
3690}
3691
Jim Grosbach1355cf12011-07-26 17:10:22 +00003692/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00003693/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3694/// when they refer multiple MIOperands inside a single one.
3695bool ARMAsmParser::
Jim Grosbach1355cf12011-07-26 17:10:22 +00003696cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00003697 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3698 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3699
3700 // Create a writeback register dummy placeholder.
3701 Inst.addOperand(MCOperand::CreateImm(0));
3702
Jim Grosbach7ce05792011-08-03 23:50:40 +00003703 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00003704 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3705 return true;
3706}
3707
Owen Anderson9ab0f252011-08-26 20:43:14 +00003708/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3709/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3710/// when they refer multiple MIOperands inside a single one.
3711bool ARMAsmParser::
3712cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3713 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3714 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3715
3716 // Create a writeback register dummy placeholder.
3717 Inst.addOperand(MCOperand::CreateImm(0));
3718
3719 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3720 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3721 return true;
3722}
3723
3724
Jim Grosbach548340c2011-08-11 19:22:40 +00003725/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3726/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3727/// when they refer multiple MIOperands inside a single one.
3728bool ARMAsmParser::
3729cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3730 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3731 // Create a writeback register dummy placeholder.
3732 Inst.addOperand(MCOperand::CreateImm(0));
3733 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3734 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3735 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3736 return true;
3737}
3738
Jim Grosbach1355cf12011-07-26 17:10:22 +00003739/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00003740/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3741/// when they refer multiple MIOperands inside a single one.
3742bool ARMAsmParser::
Jim Grosbach1355cf12011-07-26 17:10:22 +00003743cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00003744 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3745 // Create a writeback register dummy placeholder.
3746 Inst.addOperand(MCOperand::CreateImm(0));
Jim Grosbach548340c2011-08-11 19:22:40 +00003747 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3748 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3749 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
Jim Grosbach7ce05792011-08-03 23:50:40 +00003750 return true;
3751}
3752
Jim Grosbach7b8f46c2011-08-11 21:17:22 +00003753/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3754/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3755/// when they refer multiple MIOperands inside a single one.
3756bool ARMAsmParser::
3757cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3758 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3759 // Create a writeback register dummy placeholder.
3760 Inst.addOperand(MCOperand::CreateImm(0));
3761 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3762 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3763 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3764 return true;
3765}
3766
Jim Grosbach7ce05792011-08-03 23:50:40 +00003767/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3768/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3769/// when they refer multiple MIOperands inside a single one.
3770bool ARMAsmParser::
3771cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3772 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3773 // Rt
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00003774 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
Jim Grosbach7ce05792011-08-03 23:50:40 +00003775 // Create a writeback register dummy placeholder.
3776 Inst.addOperand(MCOperand::CreateImm(0));
3777 // addr
3778 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3779 // offset
3780 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3781 // pred
Bruno Cardoso Lopesae085542011-03-31 23:26:08 +00003782 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3783 return true;
3784}
3785
Jim Grosbach7ce05792011-08-03 23:50:40 +00003786/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +00003787/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3788/// when they refer multiple MIOperands inside a single one.
3789bool ARMAsmParser::
Jim Grosbach7ce05792011-08-03 23:50:40 +00003790cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3791 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3792 // Rt
Owen Andersonaa3402e2011-07-28 17:18:57 +00003793 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +00003794 // Create a writeback register dummy placeholder.
3795 Inst.addOperand(MCOperand::CreateImm(0));
Jim Grosbach7ce05792011-08-03 23:50:40 +00003796 // addr
3797 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3798 // offset
3799 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3800 // pred
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +00003801 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3802 return true;
3803}
3804
Jim Grosbach7ce05792011-08-03 23:50:40 +00003805/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +00003806/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3807/// when they refer multiple MIOperands inside a single one.
3808bool ARMAsmParser::
Jim Grosbach7ce05792011-08-03 23:50:40 +00003809cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3810 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +00003811 // Create a writeback register dummy placeholder.
3812 Inst.addOperand(MCOperand::CreateImm(0));
Jim Grosbach7ce05792011-08-03 23:50:40 +00003813 // Rt
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +00003814 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
Jim Grosbach7ce05792011-08-03 23:50:40 +00003815 // addr
3816 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3817 // offset
3818 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3819 // pred
3820 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3821 return true;
3822}
3823
3824/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3825/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3826/// when they refer multiple MIOperands inside a single one.
3827bool ARMAsmParser::
3828cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3829 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3830 // Create a writeback register dummy placeholder.
3831 Inst.addOperand(MCOperand::CreateImm(0));
3832 // Rt
3833 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3834 // addr
3835 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3836 // offset
3837 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3838 // pred
Bruno Cardoso Lopesac79e4c2011-04-04 17:18:19 +00003839 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3840 return true;
3841}
3842
Jim Grosbach2fd2b872011-08-10 20:29:19 +00003843/// cvtLdrdPre - Convert parsed operands to MCInst.
3844/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3845/// when they refer multiple MIOperands inside a single one.
3846bool ARMAsmParser::
3847cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3848 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3849 // Rt, Rt2
3850 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3851 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3852 // Create a writeback register dummy placeholder.
3853 Inst.addOperand(MCOperand::CreateImm(0));
3854 // addr
3855 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3856 // pred
3857 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3858 return true;
3859}
3860
Jim Grosbach14605d12011-08-11 20:28:23 +00003861/// cvtStrdPre - Convert parsed operands to MCInst.
3862/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3863/// when they refer multiple MIOperands inside a single one.
3864bool ARMAsmParser::
3865cvtStrdPre(MCInst &Inst, unsigned Opcode,
3866 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3867 // Create a writeback register dummy placeholder.
3868 Inst.addOperand(MCOperand::CreateImm(0));
3869 // Rt, Rt2
3870 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3871 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3872 // addr
3873 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3874 // pred
3875 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3876 return true;
3877}
3878
Jim Grosbach623a4542011-08-10 22:42:16 +00003879/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3880/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3881/// when they refer multiple MIOperands inside a single one.
3882bool ARMAsmParser::
3883cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3884 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3885 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3886 // Create a writeback register dummy placeholder.
3887 Inst.addOperand(MCOperand::CreateImm(0));
3888 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3889 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3890 return true;
3891}
3892
Jim Grosbach88ae2bc2011-08-19 22:07:46 +00003893/// cvtThumbMultiple- Convert parsed operands to MCInst.
3894/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3895/// when they refer multiple MIOperands inside a single one.
3896bool ARMAsmParser::
3897cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3898 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3899 // The second source operand must be the same register as the destination
3900 // operand.
3901 if (Operands.size() == 6 &&
Jim Grosbach7a010692011-08-19 22:30:46 +00003902 (((ARMOperand*)Operands[3])->getReg() !=
3903 ((ARMOperand*)Operands[5])->getReg()) &&
3904 (((ARMOperand*)Operands[3])->getReg() !=
3905 ((ARMOperand*)Operands[4])->getReg())) {
Jim Grosbach88ae2bc2011-08-19 22:07:46 +00003906 Error(Operands[3]->getStartLoc(),
Jim Grosbach7a010692011-08-19 22:30:46 +00003907 "destination register must match source register");
Jim Grosbach88ae2bc2011-08-19 22:07:46 +00003908 return false;
3909 }
3910 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3911 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
Jim Grosbach1b332862011-11-10 22:10:12 +00003912 // If we have a three-operand form, make sure to set Rn to be the operand
3913 // that isn't the same as Rd.
3914 unsigned RegOp = 4;
3915 if (Operands.size() == 6 &&
3916 ((ARMOperand*)Operands[4])->getReg() ==
3917 ((ARMOperand*)Operands[3])->getReg())
3918 RegOp = 5;
3919 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
3920 Inst.addOperand(Inst.getOperand(0));
Jim Grosbach88ae2bc2011-08-19 22:07:46 +00003921 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3922
3923 return true;
3924}
Jim Grosbach623a4542011-08-10 22:42:16 +00003925
Jim Grosbach12431322011-10-24 22:16:58 +00003926bool ARMAsmParser::
3927cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3928 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3929 // Vd
Jim Grosbach6029b6d2011-11-29 23:51:09 +00003930 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
Jim Grosbach12431322011-10-24 22:16:58 +00003931 // Create a writeback register dummy placeholder.
3932 Inst.addOperand(MCOperand::CreateImm(0));
3933 // Vn
3934 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3935 // pred
3936 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3937 return true;
3938}
3939
3940bool ARMAsmParser::
3941cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3942 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3943 // Vd
Jim Grosbach6029b6d2011-11-29 23:51:09 +00003944 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
Jim Grosbach12431322011-10-24 22:16:58 +00003945 // Create a writeback register dummy placeholder.
3946 Inst.addOperand(MCOperand::CreateImm(0));
3947 // Vn
3948 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3949 // Vm
3950 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3951 // pred
3952 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3953 return true;
3954}
3955
Jim Grosbach4334e032011-10-31 21:50:31 +00003956bool ARMAsmParser::
3957cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3958 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3959 // Create a writeback register dummy placeholder.
3960 Inst.addOperand(MCOperand::CreateImm(0));
3961 // Vn
3962 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3963 // Vt
Jim Grosbach6029b6d2011-11-29 23:51:09 +00003964 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
Jim Grosbach4334e032011-10-31 21:50:31 +00003965 // pred
3966 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3967 return true;
3968}
3969
3970bool ARMAsmParser::
3971cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3972 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3973 // Create a writeback register dummy placeholder.
3974 Inst.addOperand(MCOperand::CreateImm(0));
3975 // Vn
3976 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3977 // Vm
3978 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3979 // Vt
Jim Grosbach6029b6d2011-11-29 23:51:09 +00003980 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
Jim Grosbach4334e032011-10-31 21:50:31 +00003981 // pred
3982 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3983 return true;
3984}
3985
Bill Wendlinge7176102010-11-06 22:36:58 +00003986/// Parse an ARM memory expression, return false if successful else return true
Kevin Enderby9c41fa82009-10-30 22:55:57 +00003987/// or an error. The first token must be a '[' when called.
Bill Wendling50d0f582010-11-18 23:43:05 +00003988bool ARMAsmParser::
Jim Grosbach7ce05792011-08-03 23:50:40 +00003989parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Sean Callanan76264762010-04-02 22:27:05 +00003990 SMLoc S, E;
Sean Callanan18b83232010-01-19 21:44:56 +00003991 assert(Parser.getTok().is(AsmToken::LBrac) &&
Bill Wendlinga60f1572010-11-06 10:48:18 +00003992 "Token is not a Left Bracket");
Sean Callanan76264762010-04-02 22:27:05 +00003993 S = Parser.getTok().getLoc();
Sean Callananb9a25b72010-01-19 20:27:46 +00003994 Parser.Lex(); // Eat left bracket token.
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00003995
Sean Callanan18b83232010-01-19 21:44:56 +00003996 const AsmToken &BaseRegTok = Parser.getTok();
Jim Grosbach1355cf12011-07-26 17:10:22 +00003997 int BaseRegNum = tryParseRegister();
Jim Grosbach7ce05792011-08-03 23:50:40 +00003998 if (BaseRegNum == -1)
3999 return Error(BaseRegTok.getLoc(), "register expected");
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004000
Daniel Dunbar05710932011-01-18 05:34:17 +00004001 // The next token must either be a comma or a closing bracket.
4002 const AsmToken &Tok = Parser.getTok();
4003 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
Jim Grosbach7ce05792011-08-03 23:50:40 +00004004 return Error(Tok.getLoc(), "malformed memory operand");
Daniel Dunbar05710932011-01-18 05:34:17 +00004005
Jim Grosbach7ce05792011-08-03 23:50:40 +00004006 if (Tok.is(AsmToken::RBrac)) {
Sean Callanan76264762010-04-02 22:27:05 +00004007 E = Tok.getLoc();
Sean Callananb9a25b72010-01-19 20:27:46 +00004008 Parser.Lex(); // Eat right bracket token.
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004009
Jim Grosbach7ce05792011-08-03 23:50:40 +00004010 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
Jim Grosbach57dcb852011-10-11 17:29:55 +00004011 0, 0, false, S, E));
Jim Grosbach03f44a02010-11-29 23:18:01 +00004012
Jim Grosbachfb12f352011-09-19 18:42:21 +00004013 // If there's a pre-indexing writeback marker, '!', just add it as a token
4014 // operand. It's rather odd, but syntactically valid.
4015 if (Parser.getTok().is(AsmToken::Exclaim)) {
4016 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4017 Parser.Lex(); // Eat the '!'.
4018 }
4019
Jim Grosbach7ce05792011-08-03 23:50:40 +00004020 return false;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004021 }
Daniel Dunbar05d8b712011-01-18 05:34:24 +00004022
Jim Grosbach7ce05792011-08-03 23:50:40 +00004023 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4024 Parser.Lex(); // Eat the comma.
Daniel Dunbar05d8b712011-01-18 05:34:24 +00004025
Jim Grosbach57dcb852011-10-11 17:29:55 +00004026 // If we have a ':', it's an alignment specifier.
4027 if (Parser.getTok().is(AsmToken::Colon)) {
4028 Parser.Lex(); // Eat the ':'.
4029 E = Parser.getTok().getLoc();
4030
4031 const MCExpr *Expr;
4032 if (getParser().ParseExpression(Expr))
4033 return true;
4034
4035 // The expression has to be a constant. Memory references with relocations
4036 // don't come through here, as they use the <label> forms of the relevant
4037 // instructions.
4038 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4039 if (!CE)
4040 return Error (E, "constant expression expected");
4041
4042 unsigned Align = 0;
4043 switch (CE->getValue()) {
4044 default:
Jim Grosbacheeaf1c12011-12-19 18:31:43 +00004045 return Error(E,
4046 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4047 case 16: Align = 2; break;
4048 case 32: Align = 4; break;
Jim Grosbach57dcb852011-10-11 17:29:55 +00004049 case 64: Align = 8; break;
4050 case 128: Align = 16; break;
4051 case 256: Align = 32; break;
4052 }
4053
4054 // Now we should have the closing ']'
4055 E = Parser.getTok().getLoc();
4056 if (Parser.getTok().isNot(AsmToken::RBrac))
4057 return Error(E, "']' expected");
4058 Parser.Lex(); // Eat right bracket token.
4059
4060 // Don't worry about range checking the value here. That's handled by
4061 // the is*() predicates.
4062 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4063 ARM_AM::no_shift, 0, Align,
4064 false, S, E));
4065
4066 // If there's a pre-indexing writeback marker, '!', just add it as a token
4067 // operand.
4068 if (Parser.getTok().is(AsmToken::Exclaim)) {
4069 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4070 Parser.Lex(); // Eat the '!'.
4071 }
4072
4073 return false;
4074 }
4075
4076 // If we have a '#', it's an immediate offset, else assume it's a register
Jim Grosbach6cb4b082011-11-15 22:14:41 +00004077 // offset. Be friendly and also accept a plain integer (without a leading
4078 // hash) for gas compatibility.
4079 if (Parser.getTok().is(AsmToken::Hash) ||
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00004080 Parser.getTok().is(AsmToken::Dollar) ||
Jim Grosbach6cb4b082011-11-15 22:14:41 +00004081 Parser.getTok().is(AsmToken::Integer)) {
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00004082 if (Parser.getTok().isNot(AsmToken::Integer))
Jim Grosbach6cb4b082011-11-15 22:14:41 +00004083 Parser.Lex(); // Eat the '#'.
Jim Grosbach7ce05792011-08-03 23:50:40 +00004084 E = Parser.getTok().getLoc();
Daniel Dunbar05d8b712011-01-18 05:34:24 +00004085
Owen Anderson0da10cf2011-08-29 19:36:44 +00004086 bool isNegative = getParser().getTok().is(AsmToken::Minus);
Jim Grosbach7ce05792011-08-03 23:50:40 +00004087 const MCExpr *Offset;
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004088 if (getParser().ParseExpression(Offset))
4089 return true;
Jim Grosbach7ce05792011-08-03 23:50:40 +00004090
4091 // The expression has to be a constant. Memory references with relocations
4092 // don't come through here, as they use the <label> forms of the relevant
4093 // instructions.
4094 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4095 if (!CE)
4096 return Error (E, "constant expression expected");
4097
Owen Anderson0da10cf2011-08-29 19:36:44 +00004098 // If the constant was #-0, represent it as INT32_MIN.
4099 int32_t Val = CE->getValue();
4100 if (isNegative && Val == 0)
4101 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4102
Jim Grosbach7ce05792011-08-03 23:50:40 +00004103 // Now we should have the closing ']'
4104 E = Parser.getTok().getLoc();
4105 if (Parser.getTok().isNot(AsmToken::RBrac))
4106 return Error(E, "']' expected");
4107 Parser.Lex(); // Eat right bracket token.
4108
4109 // Don't worry about range checking the value here. That's handled by
4110 // the is*() predicates.
4111 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
Jim Grosbach57dcb852011-10-11 17:29:55 +00004112 ARM_AM::no_shift, 0, 0,
4113 false, S, E));
Jim Grosbach7ce05792011-08-03 23:50:40 +00004114
4115 // If there's a pre-indexing writeback marker, '!', just add it as a token
4116 // operand.
4117 if (Parser.getTok().is(AsmToken::Exclaim)) {
4118 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4119 Parser.Lex(); // Eat the '!'.
4120 }
4121
4122 return false;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004123 }
Jim Grosbach7ce05792011-08-03 23:50:40 +00004124
4125 // The register offset is optionally preceded by a '+' or '-'
4126 bool isNegative = false;
4127 if (Parser.getTok().is(AsmToken::Minus)) {
4128 isNegative = true;
4129 Parser.Lex(); // Eat the '-'.
4130 } else if (Parser.getTok().is(AsmToken::Plus)) {
4131 // Nothing to do.
4132 Parser.Lex(); // Eat the '+'.
4133 }
4134
4135 E = Parser.getTok().getLoc();
4136 int OffsetRegNum = tryParseRegister();
4137 if (OffsetRegNum == -1)
4138 return Error(E, "register expected");
4139
4140 // If there's a shift operator, handle it.
4141 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
Jim Grosbach0d6fac32011-08-05 22:03:36 +00004142 unsigned ShiftImm = 0;
Jim Grosbach7ce05792011-08-03 23:50:40 +00004143 if (Parser.getTok().is(AsmToken::Comma)) {
4144 Parser.Lex(); // Eat the ','.
Jim Grosbach0d6fac32011-08-05 22:03:36 +00004145 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
Jim Grosbach7ce05792011-08-03 23:50:40 +00004146 return true;
4147 }
4148
4149 // Now we should have the closing ']'
4150 E = Parser.getTok().getLoc();
4151 if (Parser.getTok().isNot(AsmToken::RBrac))
4152 return Error(E, "']' expected");
4153 Parser.Lex(); // Eat right bracket token.
4154
4155 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
Jim Grosbach57dcb852011-10-11 17:29:55 +00004156 ShiftType, ShiftImm, 0, isNegative,
Jim Grosbach7ce05792011-08-03 23:50:40 +00004157 S, E));
4158
Jim Grosbachf4fa3d62011-08-05 21:28:30 +00004159 // If there's a pre-indexing writeback marker, '!', just add it as a token
4160 // operand.
4161 if (Parser.getTok().is(AsmToken::Exclaim)) {
4162 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4163 Parser.Lex(); // Eat the '!'.
4164 }
Jim Grosbach7ce05792011-08-03 23:50:40 +00004165
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004166 return false;
4167}
4168
Jim Grosbach7ce05792011-08-03 23:50:40 +00004169/// parseMemRegOffsetShift - one of these two:
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004170/// ( lsl | lsr | asr | ror ) , # shift_amount
4171/// rrx
Jim Grosbach7ce05792011-08-03 23:50:40 +00004172/// return true if it parses a shift otherwise it returns false.
4173bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4174 unsigned &Amount) {
4175 SMLoc Loc = Parser.getTok().getLoc();
Sean Callanan18b83232010-01-19 21:44:56 +00004176 const AsmToken &Tok = Parser.getTok();
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004177 if (Tok.isNot(AsmToken::Identifier))
4178 return true;
Benjamin Kramer38e59892010-07-14 22:38:02 +00004179 StringRef ShiftName = Tok.getString();
Jim Grosbachaf4edea2011-12-07 23:40:58 +00004180 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4181 ShiftName == "asl" || ShiftName == "ASL")
Owen Anderson00828302011-03-18 22:50:18 +00004182 St = ARM_AM::lsl;
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004183 else if (ShiftName == "lsr" || ShiftName == "LSR")
Owen Anderson00828302011-03-18 22:50:18 +00004184 St = ARM_AM::lsr;
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004185 else if (ShiftName == "asr" || ShiftName == "ASR")
Owen Anderson00828302011-03-18 22:50:18 +00004186 St = ARM_AM::asr;
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004187 else if (ShiftName == "ror" || ShiftName == "ROR")
Owen Anderson00828302011-03-18 22:50:18 +00004188 St = ARM_AM::ror;
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004189 else if (ShiftName == "rrx" || ShiftName == "RRX")
Owen Anderson00828302011-03-18 22:50:18 +00004190 St = ARM_AM::rrx;
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004191 else
Jim Grosbach7ce05792011-08-03 23:50:40 +00004192 return Error(Loc, "illegal shift operator");
Sean Callananb9a25b72010-01-19 20:27:46 +00004193 Parser.Lex(); // Eat shift type token.
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004194
Jim Grosbach7ce05792011-08-03 23:50:40 +00004195 // rrx stands alone.
4196 Amount = 0;
4197 if (St != ARM_AM::rrx) {
4198 Loc = Parser.getTok().getLoc();
4199 // A '#' and a shift amount.
4200 const AsmToken &HashTok = Parser.getTok();
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00004201 if (HashTok.isNot(AsmToken::Hash) &&
4202 HashTok.isNot(AsmToken::Dollar))
Jim Grosbach7ce05792011-08-03 23:50:40 +00004203 return Error(HashTok.getLoc(), "'#' expected");
4204 Parser.Lex(); // Eat hash token.
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004205
Jim Grosbach7ce05792011-08-03 23:50:40 +00004206 const MCExpr *Expr;
4207 if (getParser().ParseExpression(Expr))
4208 return true;
4209 // Range check the immediate.
4210 // lsl, ror: 0 <= imm <= 31
4211 // lsr, asr: 0 <= imm <= 32
4212 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4213 if (!CE)
4214 return Error(Loc, "shift amount must be an immediate");
4215 int64_t Imm = CE->getValue();
4216 if (Imm < 0 ||
4217 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4218 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4219 return Error(Loc, "immediate shift value out of range");
4220 Amount = Imm;
4221 }
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004222
4223 return false;
4224}
4225
Jim Grosbach9d390362011-10-03 23:38:36 +00004226/// parseFPImm - A floating point immediate expression operand.
4227ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4228parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbach51222d12012-01-20 18:09:51 +00004229 // Anything that can accept a floating point constant as an operand
4230 // needs to go through here, as the regular ParseExpression is
4231 // integer only.
4232 //
4233 // This routine still creates a generic Immediate operand, containing
4234 // a bitcast of the 64-bit floating point value. The various operands
4235 // that accept floats can check whether the value is valid for them
4236 // via the standard is*() predicates.
4237
Jim Grosbach9d390362011-10-03 23:38:36 +00004238 SMLoc S = Parser.getTok().getLoc();
4239
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00004240 if (Parser.getTok().isNot(AsmToken::Hash) &&
4241 Parser.getTok().isNot(AsmToken::Dollar))
Jim Grosbach9d390362011-10-03 23:38:36 +00004242 return MatchOperand_NoMatch;
Jim Grosbach0e387b22011-10-17 22:26:03 +00004243
4244 // Disambiguate the VMOV forms that can accept an FP immediate.
4245 // vmov.f32 <sreg>, #imm
4246 // vmov.f64 <dreg>, #imm
4247 // vmov.f32 <dreg>, #imm @ vector f32x2
4248 // vmov.f32 <qreg>, #imm @ vector f32x4
4249 //
4250 // There are also the NEON VMOV instructions which expect an
4251 // integer constant. Make sure we don't try to parse an FPImm
4252 // for these:
4253 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4254 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4255 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4256 TyOp->getToken() != ".f64"))
4257 return MatchOperand_NoMatch;
4258
Jim Grosbach9d390362011-10-03 23:38:36 +00004259 Parser.Lex(); // Eat the '#'.
4260
4261 // Handle negation, as that still comes through as a separate token.
4262 bool isNegative = false;
4263 if (Parser.getTok().is(AsmToken::Minus)) {
4264 isNegative = true;
4265 Parser.Lex();
4266 }
4267 const AsmToken &Tok = Parser.getTok();
Jim Grosbachae69f702012-01-19 02:47:30 +00004268 SMLoc Loc = Tok.getLoc();
Jim Grosbach9d390362011-10-03 23:38:36 +00004269 if (Tok.is(AsmToken::Real)) {
Jim Grosbach51222d12012-01-20 18:09:51 +00004270 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
Jim Grosbach9d390362011-10-03 23:38:36 +00004271 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4272 // If we had a '-' in front, toggle the sign bit.
Jim Grosbach51222d12012-01-20 18:09:51 +00004273 IntVal ^= (uint64_t)isNegative << 31;
Jim Grosbach9d390362011-10-03 23:38:36 +00004274 Parser.Lex(); // Eat the token.
Jim Grosbach51222d12012-01-20 18:09:51 +00004275 Operands.push_back(ARMOperand::CreateImm(
4276 MCConstantExpr::Create(IntVal, getContext()),
4277 S, Parser.getTok().getLoc()));
Jim Grosbach9d390362011-10-03 23:38:36 +00004278 return MatchOperand_Success;
4279 }
Jim Grosbach51222d12012-01-20 18:09:51 +00004280 // Also handle plain integers. Instructions which allow floating point
4281 // immediates also allow a raw encoded 8-bit value.
Jim Grosbach9d390362011-10-03 23:38:36 +00004282 if (Tok.is(AsmToken::Integer)) {
4283 int64_t Val = Tok.getIntVal();
4284 Parser.Lex(); // Eat the token.
4285 if (Val > 255 || Val < 0) {
Jim Grosbachae69f702012-01-19 02:47:30 +00004286 Error(Loc, "encoded floating point value out of range");
Jim Grosbach9d390362011-10-03 23:38:36 +00004287 return MatchOperand_ParseFail;
4288 }
Jim Grosbach51222d12012-01-20 18:09:51 +00004289 double RealVal = ARM_AM::getFPImmFloat(Val);
4290 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4291 Operands.push_back(ARMOperand::CreateImm(
4292 MCConstantExpr::Create(Val, getContext()), S,
4293 Parser.getTok().getLoc()));
Jim Grosbach9d390362011-10-03 23:38:36 +00004294 return MatchOperand_Success;
4295 }
4296
Jim Grosbachae69f702012-01-19 02:47:30 +00004297 Error(Loc, "invalid floating point immediate");
Jim Grosbach9d390362011-10-03 23:38:36 +00004298 return MatchOperand_ParseFail;
4299}
Jim Grosbach51222d12012-01-20 18:09:51 +00004300
Kevin Enderby9c41fa82009-10-30 22:55:57 +00004301/// Parse a arm instruction operand. For now this parses the operand regardless
4302/// of the mnemonic.
Jim Grosbach1355cf12011-07-26 17:10:22 +00004303bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00004304 StringRef Mnemonic) {
Sean Callanan76264762010-04-02 22:27:05 +00004305 SMLoc S, E;
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00004306
4307 // Check if the current operand has a custom associated parser, if so, try to
4308 // custom parse the operand, or fallback to the general approach.
Jim Grosbachf922c472011-02-12 01:34:40 +00004309 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4310 if (ResTy == MatchOperand_Success)
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00004311 return false;
Jim Grosbachf922c472011-02-12 01:34:40 +00004312 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4313 // there was a match, but an error occurred, in which case, just return that
4314 // the operand parsing failed.
4315 if (ResTy == MatchOperand_ParseFail)
4316 return true;
Bruno Cardoso Lopesfafde7f2011-02-07 21:41:25 +00004317
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004318 switch (getLexer().getKind()) {
Bill Wendling146018f2010-11-06 21:42:12 +00004319 default:
4320 Error(Parser.getTok().getLoc(), "unexpected token in operand");
Bill Wendling50d0f582010-11-18 23:43:05 +00004321 return true;
Jim Grosbach19906722011-07-13 18:49:30 +00004322 case AsmToken::Identifier: {
Jim Grosbach1355cf12011-07-26 17:10:22 +00004323 if (!tryParseRegisterWithWriteBack(Operands))
Bill Wendling50d0f582010-11-18 23:43:05 +00004324 return false;
Jim Grosbach0d87ec22011-07-26 20:41:24 +00004325 int Res = tryParseShiftRegister(Operands);
Jim Grosbach19906722011-07-13 18:49:30 +00004326 if (Res == 0) // success
Owen Anderson00828302011-03-18 22:50:18 +00004327 return false;
Jim Grosbach19906722011-07-13 18:49:30 +00004328 else if (Res == -1) // irrecoverable error
4329 return true;
Jim Grosbach3cbe43f2011-12-20 22:26:38 +00004330 // If this is VMRS, check for the apsr_nzcv operand.
Jim Grosbach5cd5ac62011-10-03 21:12:43 +00004331 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
4332 S = Parser.getTok().getLoc();
4333 Parser.Lex();
4334 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
4335 return false;
4336 }
Owen Andersone4e5e2a2011-01-13 21:46:02 +00004337
4338 // Fall though for the Identifier case that is not a register or a
4339 // special name.
Jim Grosbach19906722011-07-13 18:49:30 +00004340 }
Jim Grosbach758a5192011-10-26 21:14:08 +00004341 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
Kevin Enderby67b212e2011-01-13 20:32:36 +00004342 case AsmToken::Integer: // things like 1f and 2b as a branch targets
Jim Grosbach6284afc2011-11-01 22:38:31 +00004343 case AsmToken::String: // quoted label names.
Kevin Enderby67b212e2011-01-13 20:32:36 +00004344 case AsmToken::Dot: { // . as a branch target
Kevin Enderby515d5092009-10-15 20:48:48 +00004345 // This was not a register so parse other operands that start with an
4346 // identifier (like labels) as expressions and create them as immediates.
4347 const MCExpr *IdVal;
Sean Callanan76264762010-04-02 22:27:05 +00004348 S = Parser.getTok().getLoc();
Kevin Enderby515d5092009-10-15 20:48:48 +00004349 if (getParser().ParseExpression(IdVal))
Bill Wendling50d0f582010-11-18 23:43:05 +00004350 return true;
Sean Callanan76264762010-04-02 22:27:05 +00004351 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Bill Wendling50d0f582010-11-18 23:43:05 +00004352 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4353 return false;
4354 }
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004355 case AsmToken::LBrac:
Jim Grosbach1355cf12011-07-26 17:10:22 +00004356 return parseMemory(Operands);
Kevin Enderbyd7894f12009-10-09 21:12:28 +00004357 case AsmToken::LCurly:
Jim Grosbach1355cf12011-07-26 17:10:22 +00004358 return parseRegisterList(Operands);
Jim Grosbach8a12e3b2011-12-09 22:25:03 +00004359 case AsmToken::Dollar:
Owen Anderson63553c72011-08-29 17:17:09 +00004360 case AsmToken::Hash: {
Kevin Enderby079469f2009-10-13 23:33:38 +00004361 // #42 -> immediate.
4362 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
Sean Callanan76264762010-04-02 22:27:05 +00004363 S = Parser.getTok().getLoc();
Sean Callananb9a25b72010-01-19 20:27:46 +00004364 Parser.Lex();
Owen Anderson63553c72011-08-29 17:17:09 +00004365 bool isNegative = Parser.getTok().is(AsmToken::Minus);
Kevin Enderby515d5092009-10-15 20:48:48 +00004366 const MCExpr *ImmVal;
4367 if (getParser().ParseExpression(ImmVal))
Bill Wendling50d0f582010-11-18 23:43:05 +00004368 return true;
Owen Anderson63553c72011-08-29 17:17:09 +00004369 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
Jim Grosbached6a0c52011-11-01 22:37:37 +00004370 if (CE) {
4371 int32_t Val = CE->getValue();
4372 if (isNegative && Val == 0)
4373 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
Owen Anderson63553c72011-08-29 17:17:09 +00004374 }
Sean Callanan76264762010-04-02 22:27:05 +00004375 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Bill Wendling50d0f582010-11-18 23:43:05 +00004376 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4377 return false;
Owen Anderson63553c72011-08-29 17:17:09 +00004378 }
Jason W Kim9081b4b2011-01-11 23:53:41 +00004379 case AsmToken::Colon: {
4380 // ":lower16:" and ":upper16:" expression prefixes
Evan Cheng75972122011-01-13 07:58:56 +00004381 // FIXME: Check it's an expression prefix,
4382 // e.g. (FOO - :lower16:BAR) isn't legal.
4383 ARMMCExpr::VariantKind RefKind;
Jim Grosbach1355cf12011-07-26 17:10:22 +00004384 if (parsePrefix(RefKind))
Jason W Kim9081b4b2011-01-11 23:53:41 +00004385 return true;
4386
Evan Cheng75972122011-01-13 07:58:56 +00004387 const MCExpr *SubExprVal;
4388 if (getParser().ParseExpression(SubExprVal))
Jason W Kim9081b4b2011-01-11 23:53:41 +00004389 return true;
4390
Evan Cheng75972122011-01-13 07:58:56 +00004391 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4392 getContext());
Jason W Kim9081b4b2011-01-11 23:53:41 +00004393 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Evan Cheng75972122011-01-13 07:58:56 +00004394 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
Jason W Kim9081b4b2011-01-11 23:53:41 +00004395 return false;
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004396 }
Jason W Kim9081b4b2011-01-11 23:53:41 +00004397 }
4398}
4399
Jim Grosbach1355cf12011-07-26 17:10:22 +00004400// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
Evan Cheng75972122011-01-13 07:58:56 +00004401// :lower16: and :upper16:.
Jim Grosbach1355cf12011-07-26 17:10:22 +00004402bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
Evan Cheng75972122011-01-13 07:58:56 +00004403 RefKind = ARMMCExpr::VK_ARM_None;
Jason W Kim9081b4b2011-01-11 23:53:41 +00004404
4405 // :lower16: and :upper16: modifiers
Jason W Kim8a8696d2011-01-13 00:27:00 +00004406 assert(getLexer().is(AsmToken::Colon) && "expected a :");
Jason W Kim9081b4b2011-01-11 23:53:41 +00004407 Parser.Lex(); // Eat ':'
4408
4409 if (getLexer().isNot(AsmToken::Identifier)) {
4410 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4411 return true;
4412 }
4413
4414 StringRef IDVal = Parser.getTok().getIdentifier();
4415 if (IDVal == "lower16") {
Evan Cheng75972122011-01-13 07:58:56 +00004416 RefKind = ARMMCExpr::VK_ARM_LO16;
Jason W Kim9081b4b2011-01-11 23:53:41 +00004417 } else if (IDVal == "upper16") {
Evan Cheng75972122011-01-13 07:58:56 +00004418 RefKind = ARMMCExpr::VK_ARM_HI16;
Jason W Kim9081b4b2011-01-11 23:53:41 +00004419 } else {
4420 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4421 return true;
4422 }
4423 Parser.Lex();
4424
4425 if (getLexer().isNot(AsmToken::Colon)) {
4426 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4427 return true;
4428 }
4429 Parser.Lex(); // Eat the last ':'
4430 return false;
4431}
4432
Daniel Dunbar352e1482011-01-11 15:59:50 +00004433/// \brief Given a mnemonic, split out possible predication code and carry
4434/// setting letters to form a canonical mnemonic and flags.
4435//
Daniel Dunbarbadbd2f2011-01-10 12:24:52 +00004436// FIXME: Would be nice to autogen this.
Jim Grosbach89df9962011-08-26 21:43:41 +00004437// FIXME: This is a bit of a maze of special cases.
Jim Grosbach1355cf12011-07-26 17:10:22 +00004438StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
Jim Grosbach5f160572011-07-19 20:10:31 +00004439 unsigned &PredicationCode,
4440 bool &CarrySetting,
Jim Grosbach89df9962011-08-26 21:43:41 +00004441 unsigned &ProcessorIMod,
4442 StringRef &ITMask) {
Daniel Dunbar352e1482011-01-11 15:59:50 +00004443 PredicationCode = ARMCC::AL;
4444 CarrySetting = false;
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00004445 ProcessorIMod = 0;
Daniel Dunbar352e1482011-01-11 15:59:50 +00004446
Daniel Dunbarbadbd2f2011-01-10 12:24:52 +00004447 // Ignore some mnemonics we know aren't predicated forms.
Daniel Dunbar352e1482011-01-11 15:59:50 +00004448 //
4449 // FIXME: Would be nice to autogen this.
Jim Grosbach5f160572011-07-19 20:10:31 +00004450 if ((Mnemonic == "movs" && isThumb()) ||
4451 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4452 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4453 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4454 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4455 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4456 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
Jim Grosbach68490192011-12-19 19:43:50 +00004457 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4458 Mnemonic == "fmuls")
Daniel Dunbar352e1482011-01-11 15:59:50 +00004459 return Mnemonic;
Daniel Dunbar5747b132010-08-11 06:37:16 +00004460
Jim Grosbach3f00e312011-07-11 17:09:57 +00004461 // First, split out any predication code. Ignore mnemonics we know aren't
4462 // predicated but do have a carry-set and so weren't caught above.
Jim Grosbachab40f4b2011-07-20 18:20:31 +00004463 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
Jim Grosbach71725a02011-07-27 21:58:11 +00004464 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
Jim Grosbach04d55f12011-08-22 23:55:58 +00004465 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
Jim Grosbach2f25d9b2011-09-01 18:22:13 +00004466 Mnemonic != "sbcs" && Mnemonic != "rscs") {
Jim Grosbach3f00e312011-07-11 17:09:57 +00004467 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4468 .Case("eq", ARMCC::EQ)
4469 .Case("ne", ARMCC::NE)
4470 .Case("hs", ARMCC::HS)
4471 .Case("cs", ARMCC::HS)
4472 .Case("lo", ARMCC::LO)
4473 .Case("cc", ARMCC::LO)
4474 .Case("mi", ARMCC::MI)
4475 .Case("pl", ARMCC::PL)
4476 .Case("vs", ARMCC::VS)
4477 .Case("vc", ARMCC::VC)
4478 .Case("hi", ARMCC::HI)
4479 .Case("ls", ARMCC::LS)
4480 .Case("ge", ARMCC::GE)
4481 .Case("lt", ARMCC::LT)
4482 .Case("gt", ARMCC::GT)
4483 .Case("le", ARMCC::LE)
4484 .Case("al", ARMCC::AL)
4485 .Default(~0U);
4486 if (CC != ~0U) {
4487 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4488 PredicationCode = CC;
4489 }
Bill Wendling52925b62010-10-29 23:50:21 +00004490 }
Daniel Dunbar345a9a62010-08-11 06:37:20 +00004491
Daniel Dunbar352e1482011-01-11 15:59:50 +00004492 // Next, determine if we have a carry setting bit. We explicitly ignore all
4493 // the instructions we know end in 's'.
4494 if (Mnemonic.endswith("s") &&
Jim Grosbach00f5d982011-08-17 22:49:09 +00004495 !(Mnemonic == "cps" || Mnemonic == "mls" ||
Jim Grosbach5f160572011-07-19 20:10:31 +00004496 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4497 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4498 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
Jim Grosbach67ca1ad2011-12-08 00:49:29 +00004499 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
Jim Grosbach48171e72011-12-10 00:01:02 +00004500 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
Jim Grosbach9c397892011-12-19 19:02:41 +00004501 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
Jim Grosbach1aa149f2011-12-22 19:20:45 +00004502 Mnemonic == "fmuls" || Mnemonic == "fcmps" ||
Jim Grosbache1cf5902011-07-29 20:26:09 +00004503 (Mnemonic == "movs" && isThumb()))) {
Daniel Dunbar352e1482011-01-11 15:59:50 +00004504 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4505 CarrySetting = true;
4506 }
4507
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00004508 // The "cps" instruction can have a interrupt mode operand which is glued into
4509 // the mnemonic. Check if this is the case, split it and parse the imod op
4510 if (Mnemonic.startswith("cps")) {
4511 // Split out any imod code.
4512 unsigned IMod =
4513 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4514 .Case("ie", ARM_PROC::IE)
4515 .Case("id", ARM_PROC::ID)
4516 .Default(~0U);
4517 if (IMod != ~0U) {
4518 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4519 ProcessorIMod = IMod;
4520 }
4521 }
4522
Jim Grosbach89df9962011-08-26 21:43:41 +00004523 // The "it" instruction has the condition mask on the end of the mnemonic.
4524 if (Mnemonic.startswith("it")) {
4525 ITMask = Mnemonic.slice(2, Mnemonic.size());
4526 Mnemonic = Mnemonic.slice(0, 2);
4527 }
4528
Daniel Dunbar352e1482011-01-11 15:59:50 +00004529 return Mnemonic;
4530}
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004531
4532/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4533/// inclusion of carry set or predication code operands.
4534//
4535// FIXME: It would be nice to autogen this.
Bruno Cardoso Lopesfdcee772011-01-18 20:55:11 +00004536void ARMAsmParser::
Jim Grosbach1355cf12011-07-26 17:10:22 +00004537getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
Bruno Cardoso Lopesfdcee772011-01-18 20:55:11 +00004538 bool &CanAcceptPredicationCode) {
Daniel Dunbareb9f3f92011-01-11 19:06:29 +00004539 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4540 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
Jim Grosbach3443ed52011-09-16 18:05:48 +00004541 Mnemonic == "add" || Mnemonic == "adc" ||
Daniel Dunbareb9f3f92011-01-11 19:06:29 +00004542 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
Jim Grosbachd5d0e812011-09-19 23:31:02 +00004543 Mnemonic == "orr" || Mnemonic == "mvn" ||
Daniel Dunbareb9f3f92011-01-11 19:06:29 +00004544 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
Jim Grosbachd5d0e812011-09-19 23:31:02 +00004545 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
Jim Grosbach3443ed52011-09-16 18:05:48 +00004546 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
Jim Grosbachd5d0e812011-09-19 23:31:02 +00004547 Mnemonic == "mla" || Mnemonic == "smlal" ||
4548 Mnemonic == "umlal" || Mnemonic == "umull"))) {
Daniel Dunbareb9f3f92011-01-11 19:06:29 +00004549 CanAcceptCarrySet = true;
Jim Grosbachfb9cffe2011-09-16 16:39:25 +00004550 } else
Daniel Dunbareb9f3f92011-01-11 19:06:29 +00004551 CanAcceptCarrySet = false;
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004552
Daniel Dunbareb9f3f92011-01-11 19:06:29 +00004553 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4554 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4555 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4556 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
Jim Grosbachad2dad92011-09-06 20:27:04 +00004557 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4558 (Mnemonic == "clrex" && !isThumb()) ||
Jim Grosbach0780b632011-08-19 23:24:36 +00004559 (Mnemonic == "nop" && isThumbOne()) ||
Jim Grosbach2bd01182011-10-11 21:55:36 +00004560 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4561 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4562 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
Jim Grosbach4af54a42011-08-26 22:21:51 +00004563 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4564 !isThumb()) ||
Jim Grosbach1ad60c22011-09-10 00:15:36 +00004565 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004566 CanAcceptPredicationCode = false;
Jim Grosbachfb9cffe2011-09-16 16:39:25 +00004567 } else
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004568 CanAcceptPredicationCode = true;
Bruno Cardoso Lopesfa5bd272011-01-20 16:35:57 +00004569
Jim Grosbachfb9cffe2011-09-16 16:39:25 +00004570 if (isThumb()) {
Bruno Cardoso Lopesfa5bd272011-01-20 16:35:57 +00004571 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
Jim Grosbach63b46fa2011-06-30 22:10:46 +00004572 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
Bruno Cardoso Lopesfa5bd272011-01-20 16:35:57 +00004573 CanAcceptPredicationCode = false;
Jim Grosbachfb9cffe2011-09-16 16:39:25 +00004574 }
Daniel Dunbarbadbd2f2011-01-10 12:24:52 +00004575}
4576
Jim Grosbachd54b4e62011-08-16 21:12:37 +00004577bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4578 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbach20ed2e72011-09-01 00:28:52 +00004579 // FIXME: This is all horribly hacky. We really need a better way to deal
4580 // with optional operands like this in the matcher table.
Jim Grosbachd54b4e62011-08-16 21:12:37 +00004581
4582 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4583 // another does not. Specifically, the MOVW instruction does not. So we
4584 // special case it here and remove the defaulted (non-setting) cc_out
4585 // operand if that's the instruction we're trying to match.
4586 //
4587 // We do this as post-processing of the explicit operands rather than just
4588 // conditionally adding the cc_out in the first place because we need
4589 // to check the type of the parsed immediate operand.
Owen Anderson8adf6202011-09-14 22:46:14 +00004590 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
Jim Grosbachd54b4e62011-08-16 21:12:37 +00004591 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4592 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4593 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4594 return true;
Jim Grosbach3912b732011-08-16 21:34:08 +00004595
4596 // Register-register 'add' for thumb does not have a cc_out operand
4597 // when there are only two register operands.
4598 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4599 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4600 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4601 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4602 return true;
Jim Grosbach72f39f82011-08-24 21:22:15 +00004603 // Register-register 'add' for thumb does not have a cc_out operand
Jim Grosbach20ed2e72011-09-01 00:28:52 +00004604 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4605 // have to check the immediate range here since Thumb2 has a variant
4606 // that can handle a different range and has a cc_out operand.
Jim Grosbachf67e8552011-09-16 22:58:42 +00004607 if (((isThumb() && Mnemonic == "add") ||
4608 (isThumbTwo() && Mnemonic == "sub")) &&
4609 Operands.size() == 6 &&
Jim Grosbach72f39f82011-08-24 21:22:15 +00004610 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4611 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4612 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
Jim Grosbach20ed2e72011-09-01 00:28:52 +00004613 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4614 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4615 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
Jim Grosbach72f39f82011-08-24 21:22:15 +00004616 return true;
Jim Grosbachf67e8552011-09-16 22:58:42 +00004617 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4618 // imm0_4095 variant. That's the least-preferred variant when
Jim Grosbach20ed2e72011-09-01 00:28:52 +00004619 // selecting via the generic "add" mnemonic, so to know that we
4620 // should remove the cc_out operand, we have to explicitly check that
4621 // it's not one of the other variants. Ugh.
Jim Grosbachf67e8552011-09-16 22:58:42 +00004622 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4623 Operands.size() == 6 &&
Jim Grosbach20ed2e72011-09-01 00:28:52 +00004624 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4625 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4626 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4627 // Nest conditions rather than one big 'if' statement for readability.
4628 //
4629 // If either register is a high reg, it's either one of the SP
4630 // variants (handled above) or a 32-bit encoding, so we just
4631 // check against T3.
4632 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4633 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4634 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4635 return false;
4636 // If both registers are low, we're in an IT block, and the immediate is
4637 // in range, we should use encoding T1 instead, which has a cc_out.
4638 if (inITBlock() &&
Jim Grosbach64944f42011-09-14 21:00:40 +00004639 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
Jim Grosbach20ed2e72011-09-01 00:28:52 +00004640 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4641 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4642 return false;
4643
4644 // Otherwise, we use encoding T4, which does not have a cc_out
4645 // operand.
4646 return true;
4647 }
4648
Jim Grosbach64944f42011-09-14 21:00:40 +00004649 // The thumb2 multiply instruction doesn't have a CCOut register, so
4650 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4651 // use the 16-bit encoding or not.
4652 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4653 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4654 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4655 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4656 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4657 // If the registers aren't low regs, the destination reg isn't the
4658 // same as one of the source regs, or the cc_out operand is zero
4659 // outside of an IT block, we have to use the 32-bit encoding, so
4660 // remove the cc_out operand.
4661 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4662 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
Jim Grosbach1de0bd12011-11-15 19:29:45 +00004663 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
Jim Grosbach64944f42011-09-14 21:00:40 +00004664 !inITBlock() ||
4665 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4666 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4667 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4668 static_cast<ARMOperand*>(Operands[4])->getReg())))
4669 return true;
4670
Jim Grosbach7f1ec952011-11-15 19:55:16 +00004671 // Also check the 'mul' syntax variant that doesn't specify an explicit
4672 // destination register.
4673 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4674 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4675 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4676 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4677 // If the registers aren't low regs or the cc_out operand is zero
4678 // outside of an IT block, we have to use the 32-bit encoding, so
4679 // remove the cc_out operand.
4680 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4681 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4682 !inITBlock()))
4683 return true;
4684
Jim Grosbach64944f42011-09-14 21:00:40 +00004685
Jim Grosbach20ed2e72011-09-01 00:28:52 +00004686
Jim Grosbachf69c8042011-08-24 21:42:27 +00004687 // Register-register 'add/sub' for thumb does not have a cc_out operand
4688 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4689 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4690 // right, this will result in better diagnostics (which operand is off)
4691 // anyway.
4692 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4693 (Operands.size() == 5 || Operands.size() == 6) &&
Jim Grosbach72f39f82011-08-24 21:22:15 +00004694 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4695 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4696 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4697 return true;
Jim Grosbach3912b732011-08-16 21:34:08 +00004698
Jim Grosbachd54b4e62011-08-16 21:12:37 +00004699 return false;
4700}
4701
Jim Grosbach7aef99b2011-11-11 23:08:10 +00004702static bool isDataTypeToken(StringRef Tok) {
4703 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4704 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4705 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4706 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4707 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4708 Tok == ".f" || Tok == ".d";
4709}
4710
4711// FIXME: This bit should probably be handled via an explicit match class
4712// in the .td files that matches the suffix instead of having it be
4713// a literal string token the way it is now.
4714static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4715 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4716}
4717
Jim Grosbach21d7fb82011-12-09 23:34:09 +00004718static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
Daniel Dunbarbadbd2f2011-01-10 12:24:52 +00004719/// Parse an arm instruction mnemonic followed by its operands.
4720bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4721 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Jim Grosbach21d7fb82011-12-09 23:34:09 +00004722 // Apply mnemonic aliases before doing anything else, as the destination
4723 // mnemnonic may include suffices and we want to handle them normally.
4724 // The generic tblgen'erated code does this later, at the start of
4725 // MatchInstructionImpl(), but that's too late for aliases that include
4726 // any sort of suffix.
4727 unsigned AvailableFeatures = getAvailableFeatures();
4728 applyMnemonicAliases(Name, AvailableFeatures);
4729
Jim Grosbacha39cda72011-12-14 02:16:11 +00004730 // First check for the ARM-specific .req directive.
4731 if (Parser.getTok().is(AsmToken::Identifier) &&
4732 Parser.getTok().getIdentifier() == ".req") {
4733 parseDirectiveReq(Name, NameLoc);
4734 // We always return 'error' for this, as we're done with this
4735 // statement and don't need to match the 'instruction."
4736 return true;
4737 }
4738
Daniel Dunbarbadbd2f2011-01-10 12:24:52 +00004739 // Create the leading tokens for the mnemonic, split by '.' characters.
4740 size_t Start = 0, Next = Name.find('.');
Jim Grosbachffa32252011-07-19 19:13:28 +00004741 StringRef Mnemonic = Name.slice(Start, Next);
Daniel Dunbarbadbd2f2011-01-10 12:24:52 +00004742
Daniel Dunbar352e1482011-01-11 15:59:50 +00004743 // Split out the predication code and carry setting flag from the mnemonic.
4744 unsigned PredicationCode;
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00004745 unsigned ProcessorIMod;
Daniel Dunbar352e1482011-01-11 15:59:50 +00004746 bool CarrySetting;
Jim Grosbach89df9962011-08-26 21:43:41 +00004747 StringRef ITMask;
Jim Grosbach1355cf12011-07-26 17:10:22 +00004748 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
Jim Grosbach89df9962011-08-26 21:43:41 +00004749 ProcessorIMod, ITMask);
Daniel Dunbarbadbd2f2011-01-10 12:24:52 +00004750
Jim Grosbach0c49ac02011-08-25 17:23:55 +00004751 // In Thumb1, only the branch (B) instruction can be predicated.
4752 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4753 Parser.EatToEndOfStatement();
4754 return Error(NameLoc, "conditional execution not supported in Thumb1");
4755 }
4756
Jim Grosbachffa32252011-07-19 19:13:28 +00004757 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4758
Jim Grosbach89df9962011-08-26 21:43:41 +00004759 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4760 // is the mask as it will be for the IT encoding if the conditional
4761 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4762 // where the conditional bit0 is zero, the instruction post-processing
4763 // will adjust the mask accordingly.
4764 if (Mnemonic == "it") {
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004765 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4766 if (ITMask.size() > 3) {
4767 Parser.EatToEndOfStatement();
4768 return Error(Loc, "too many conditions on IT instruction");
4769 }
Jim Grosbach89df9962011-08-26 21:43:41 +00004770 unsigned Mask = 8;
4771 for (unsigned i = ITMask.size(); i != 0; --i) {
4772 char pos = ITMask[i - 1];
4773 if (pos != 't' && pos != 'e') {
4774 Parser.EatToEndOfStatement();
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004775 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
Jim Grosbach89df9962011-08-26 21:43:41 +00004776 }
4777 Mask >>= 1;
4778 if (ITMask[i - 1] == 't')
4779 Mask |= 8;
4780 }
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004781 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
Jim Grosbach89df9962011-08-26 21:43:41 +00004782 }
4783
Jim Grosbachffa32252011-07-19 19:13:28 +00004784 // FIXME: This is all a pretty gross hack. We should automatically handle
4785 // optional operands like this via tblgen.
Bill Wendling9717fa92010-11-21 10:56:05 +00004786
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004787 // Next, add the CCOut and ConditionCode operands, if needed.
4788 //
4789 // For mnemonics which can ever incorporate a carry setting bit or predication
4790 // code, our matching model involves us always generating CCOut and
4791 // ConditionCode operands to match the mnemonic "as written" and then we let
4792 // the matcher deal with finding the right instruction or generating an
4793 // appropriate error.
4794 bool CanAcceptCarrySet, CanAcceptPredicationCode;
Jim Grosbach1355cf12011-07-26 17:10:22 +00004795 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004796
Jim Grosbach33c16a22011-07-14 22:04:21 +00004797 // If we had a carry-set on an instruction that can't do that, issue an
4798 // error.
4799 if (!CanAcceptCarrySet && CarrySetting) {
4800 Parser.EatToEndOfStatement();
Jim Grosbachffa32252011-07-19 19:13:28 +00004801 return Error(NameLoc, "instruction '" + Mnemonic +
Jim Grosbach33c16a22011-07-14 22:04:21 +00004802 "' can not set flags, but 's' suffix specified");
4803 }
Jim Grosbachc27d4f92011-07-22 17:44:50 +00004804 // If we had a predication code on an instruction that can't do that, issue an
4805 // error.
4806 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4807 Parser.EatToEndOfStatement();
4808 return Error(NameLoc, "instruction '" + Mnemonic +
4809 "' is not predicable, but condition code specified");
4810 }
Jim Grosbach33c16a22011-07-14 22:04:21 +00004811
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004812 // Add the carry setting operand, if necessary.
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004813 if (CanAcceptCarrySet) {
4814 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004815 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004816 Loc));
4817 }
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004818
4819 // Add the predication code operand, if necessary.
4820 if (CanAcceptPredicationCode) {
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004821 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4822 CarrySetting);
Daniel Dunbar3771dd02011-01-11 15:59:53 +00004823 Operands.push_back(ARMOperand::CreateCondCode(
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004824 ARMCC::CondCodes(PredicationCode), Loc));
Daniel Dunbarbadbd2f2011-01-10 12:24:52 +00004825 }
Daniel Dunbar345a9a62010-08-11 06:37:20 +00004826
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00004827 // Add the processor imod operand, if necessary.
4828 if (ProcessorIMod) {
4829 Operands.push_back(ARMOperand::CreateImm(
4830 MCConstantExpr::Create(ProcessorIMod, getContext()),
4831 NameLoc, NameLoc));
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00004832 }
4833
Daniel Dunbar345a9a62010-08-11 06:37:20 +00004834 // Add the remaining tokens in the mnemonic.
Daniel Dunbar5747b132010-08-11 06:37:16 +00004835 while (Next != StringRef::npos) {
4836 Start = Next;
4837 Next = Name.find('.', Start + 1);
Bruno Cardoso Lopesa2b6e412011-02-14 13:09:44 +00004838 StringRef ExtraToken = Name.slice(Start, Next);
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004839
Jim Grosbach7aef99b2011-11-11 23:08:10 +00004840 // Some NEON instructions have an optional datatype suffix that is
4841 // completely ignored. Check for that.
4842 if (isDataTypeToken(ExtraToken) &&
4843 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4844 continue;
4845
Jim Grosbach81d2e392011-09-07 16:06:04 +00004846 if (ExtraToken != ".n") {
4847 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4848 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4849 }
Daniel Dunbar5747b132010-08-11 06:37:16 +00004850 }
4851
4852 // Read the remaining operands.
4853 if (getLexer().isNot(AsmToken::EndOfStatement)) {
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004854 // Read the first operand.
Jim Grosbach1355cf12011-07-26 17:10:22 +00004855 if (parseOperand(Operands, Mnemonic)) {
Chris Lattnercbf8a982010-09-11 16:18:25 +00004856 Parser.EatToEndOfStatement();
4857 return true;
4858 }
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004859
4860 while (getLexer().is(AsmToken::Comma)) {
Sean Callananb9a25b72010-01-19 20:27:46 +00004861 Parser.Lex(); // Eat the comma.
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004862
4863 // Parse and remember the operand.
Jim Grosbach1355cf12011-07-26 17:10:22 +00004864 if (parseOperand(Operands, Mnemonic)) {
Chris Lattnercbf8a982010-09-11 16:18:25 +00004865 Parser.EatToEndOfStatement();
4866 return true;
4867 }
Kevin Enderbya7ba3a82009-10-06 22:26:42 +00004868 }
4869 }
Jim Grosbach16c74252010-10-29 14:46:02 +00004870
Chris Lattnercbf8a982010-09-11 16:18:25 +00004871 if (getLexer().isNot(AsmToken::EndOfStatement)) {
Jim Grosbach186ffac2011-10-07 18:27:04 +00004872 SMLoc Loc = getLexer().getLoc();
Chris Lattnercbf8a982010-09-11 16:18:25 +00004873 Parser.EatToEndOfStatement();
Jim Grosbach186ffac2011-10-07 18:27:04 +00004874 return Error(Loc, "unexpected token in argument list");
Chris Lattnercbf8a982010-09-11 16:18:25 +00004875 }
Bill Wendling146018f2010-11-06 21:42:12 +00004876
Chris Lattner34e53142010-09-08 05:10:46 +00004877 Parser.Lex(); // Consume the EndOfStatement
Jim Grosbachffa32252011-07-19 19:13:28 +00004878
Jim Grosbachd54b4e62011-08-16 21:12:37 +00004879 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4880 // do and don't have a cc_out optional-def operand. With some spot-checks
4881 // of the operand list, we can figure out which variant we're trying to
Jim Grosbach20ed2e72011-09-01 00:28:52 +00004882 // parse and adjust accordingly before actually matching. We shouldn't ever
4883 // try to remove a cc_out operand that was explicitly set on the the
4884 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4885 // table driven matcher doesn't fit well with the ARM instruction set.
4886 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
Jim Grosbachffa32252011-07-19 19:13:28 +00004887 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4888 Operands.erase(Operands.begin() + 1);
4889 delete Op;
4890 }
4891
Jim Grosbachcf121c32011-07-28 21:57:55 +00004892 // ARM mode 'blx' need special handling, as the register operand version
4893 // is predicable, but the label operand version is not. So, we can't rely
4894 // on the Mnemonic based checking to correctly figure out when to put
Jim Grosbach21ff17c2011-10-07 23:24:09 +00004895 // a k_CondCode operand in the list. If we're trying to match the label
4896 // version, remove the k_CondCode operand here.
Jim Grosbachcf121c32011-07-28 21:57:55 +00004897 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4898 static_cast<ARMOperand*>(Operands[2])->isImm()) {
4899 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4900 Operands.erase(Operands.begin() + 1);
4901 delete Op;
4902 }
Jim Grosbach857e1a72011-08-11 23:51:13 +00004903
4904 // The vector-compare-to-zero instructions have a literal token "#0" at
4905 // the end that comes to here as an immediate operand. Convert it to a
4906 // token to play nicely with the matcher.
4907 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4908 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4909 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4910 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4912 if (CE && CE->getValue() == 0) {
4913 Operands.erase(Operands.begin() + 5);
4914 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4915 delete Op;
4916 }
4917 }
Jim Grosbach68259142011-10-03 22:30:24 +00004918 // VCMP{E} does the same thing, but with a different operand count.
4919 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4920 static_cast<ARMOperand*>(Operands[4])->isImm()) {
4921 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4922 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4923 if (CE && CE->getValue() == 0) {
4924 Operands.erase(Operands.begin() + 4);
4925 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4926 delete Op;
4927 }
4928 }
Jim Grosbach934755a2011-08-22 23:47:13 +00004929 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
Jim Grosbach55b02f22011-12-13 20:50:38 +00004930 // end. Convert it to a token here. Take care not to convert those
4931 // that should hit the Thumb2 encoding.
Jim Grosbach934755a2011-08-22 23:47:13 +00004932 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
Jim Grosbach55b02f22011-12-13 20:50:38 +00004933 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4934 static_cast<ARMOperand*>(Operands[4])->isReg() &&
Jim Grosbach934755a2011-08-22 23:47:13 +00004935 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4936 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
Jim Grosbach55b02f22011-12-13 20:50:38 +00004938 if (CE && CE->getValue() == 0 &&
4939 (isThumbOne() ||
Jim Grosbachd7ea73a2011-12-13 21:06:41 +00004940 // The cc_out operand matches the IT block.
4941 ((inITBlock() != CarrySetting) &&
4942 // Neither register operand is a high register.
Jim Grosbach55b02f22011-12-13 20:50:38 +00004943 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
Jim Grosbachd7ea73a2011-12-13 21:06:41 +00004944 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
Jim Grosbach934755a2011-08-22 23:47:13 +00004945 Operands.erase(Operands.begin() + 5);
4946 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4947 delete Op;
4948 }
4949 }
4950
Chris Lattner98986712010-01-14 22:21:20 +00004951 return false;
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00004952}
4953
Jim Grosbach189610f2011-07-26 18:25:39 +00004954// Validate context-sensitive operand constraints.
Jim Grosbachaa875f82011-08-23 18:13:04 +00004955
4956// return 'true' if register list contains non-low GPR registers,
4957// 'false' otherwise. If Reg is in the register list or is HiReg, set
4958// 'containsReg' to true.
4959static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4960 unsigned HiReg, bool &containsReg) {
4961 containsReg = false;
4962 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4963 unsigned OpReg = Inst.getOperand(i).getReg();
4964 if (OpReg == Reg)
4965 containsReg = true;
4966 // Anything other than a low register isn't legal here.
4967 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4968 return true;
4969 }
4970 return false;
4971}
4972
Jim Grosbach76ecc3d2011-09-07 18:05:34 +00004973// Check if the specified regisgter is in the register list of the inst,
4974// starting at the indicated operand number.
4975static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4976 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4977 unsigned OpReg = Inst.getOperand(i).getReg();
4978 if (OpReg == Reg)
4979 return true;
4980 }
4981 return false;
4982}
4983
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004984// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4985// the ARMInsts array) instead. Getting that here requires awkward
4986// API changes, though. Better way?
4987namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +00004988extern const MCInstrDesc ARMInsts[];
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004989}
Benjamin Kramer1a2f9882011-10-22 16:50:00 +00004990static const MCInstrDesc &getInstDesc(unsigned Opcode) {
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004991 return ARMInsts[Opcode];
4992}
4993
Jim Grosbach189610f2011-07-26 18:25:39 +00004994// FIXME: We would really like to be able to tablegen'erate this.
4995bool ARMAsmParser::
4996validateInstruction(MCInst &Inst,
4997 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +00004998 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00004999 SMLoc Loc = Operands[0]->getStartLoc();
5000 // Check the IT block state first.
Owen Andersonb6b7f512011-09-13 17:59:19 +00005001 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
5002 // being allowed in IT blocks, but not being predicable. It just always
5003 // executes.
5004 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00005005 unsigned bit = 1;
5006 if (ITState.FirstCond)
5007 ITState.FirstCond = false;
5008 else
Jim Grosbacha1109882011-09-02 23:22:08 +00005009 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00005010 // The instruction must be predicable.
5011 if (!MCID.isPredicable())
5012 return Error(Loc, "instructions in IT block must be predicable");
5013 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5014 unsigned ITCond = bit ? ITState.Cond :
5015 ARMCC::getOppositeCondition(ITState.Cond);
5016 if (Cond != ITCond) {
5017 // Find the condition code Operand to get its SMLoc information.
5018 SMLoc CondLoc;
5019 for (unsigned i = 1; i < Operands.size(); ++i)
5020 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5021 CondLoc = Operands[i]->getStartLoc();
5022 return Error(CondLoc, "incorrect condition in IT block; got '" +
5023 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5024 "', but expected '" +
5025 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5026 }
Jim Grosbachc9a9b442011-08-31 18:29:05 +00005027 // Check for non-'al' condition codes outside of the IT block.
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00005028 } else if (isThumbTwo() && MCID.isPredicable() &&
5029 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
Owen Anderson51f6a7a2011-09-09 21:48:23 +00005030 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5031 Inst.getOpcode() != ARM::t2B)
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00005032 return Error(Loc, "predicated instructions must be in IT block");
5033
Jim Grosbach189610f2011-07-26 18:25:39 +00005034 switch (Inst.getOpcode()) {
Jim Grosbach2fd2b872011-08-10 20:29:19 +00005035 case ARM::LDRD:
5036 case ARM::LDRD_PRE:
5037 case ARM::LDRD_POST:
Jim Grosbach189610f2011-07-26 18:25:39 +00005038 case ARM::LDREXD: {
5039 // Rt2 must be Rt + 1.
5040 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5041 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5042 if (Rt2 != Rt + 1)
5043 return Error(Operands[3]->getStartLoc(),
5044 "destination operands must be sequential");
5045 return false;
5046 }
Jim Grosbach14605d12011-08-11 20:28:23 +00005047 case ARM::STRD: {
5048 // Rt2 must be Rt + 1.
5049 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5050 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5051 if (Rt2 != Rt + 1)
5052 return Error(Operands[3]->getStartLoc(),
5053 "source operands must be sequential");
5054 return false;
5055 }
Jim Grosbach53642c52011-08-10 20:49:18 +00005056 case ARM::STRD_PRE:
5057 case ARM::STRD_POST:
Jim Grosbach189610f2011-07-26 18:25:39 +00005058 case ARM::STREXD: {
5059 // Rt2 must be Rt + 1.
5060 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5061 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
5062 if (Rt2 != Rt + 1)
Jim Grosbach14605d12011-08-11 20:28:23 +00005063 return Error(Operands[3]->getStartLoc(),
Jim Grosbach189610f2011-07-26 18:25:39 +00005064 "source operands must be sequential");
5065 return false;
5066 }
Jim Grosbachfb8989e2011-07-27 21:09:25 +00005067 case ARM::SBFX:
5068 case ARM::UBFX: {
5069 // width must be in range [1, 32-lsb]
5070 unsigned lsb = Inst.getOperand(2).getImm();
5071 unsigned widthm1 = Inst.getOperand(3).getImm();
5072 if (widthm1 >= 32 - lsb)
5073 return Error(Operands[5]->getStartLoc(),
5074 "bitfield width must be in range [1,32-lsb]");
Jim Grosbach00c9a512011-08-16 21:42:31 +00005075 return false;
Jim Grosbachfb8989e2011-07-27 21:09:25 +00005076 }
Jim Grosbach93b3eff2011-08-18 21:50:53 +00005077 case ARM::tLDMIA: {
Jim Grosbach76ecc3d2011-09-07 18:05:34 +00005078 // If we're parsing Thumb2, the .w variant is available and handles
5079 // most cases that are normally illegal for a Thumb1 LDM
5080 // instruction. We'll make the transformation in processInstruction()
5081 // if necessary.
5082 //
Jim Grosbach93b3eff2011-08-18 21:50:53 +00005083 // Thumb LDM instructions are writeback iff the base register is not
5084 // in the register list.
5085 unsigned Rn = Inst.getOperand(0).getReg();
Jim Grosbach7260c6a2011-08-22 23:01:07 +00005086 bool hasWritebackToken =
5087 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5088 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
Jim Grosbachaa875f82011-08-23 18:13:04 +00005089 bool listContainsBase;
Jim Grosbach76ecc3d2011-09-07 18:05:34 +00005090 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
Jim Grosbachaa875f82011-08-23 18:13:04 +00005091 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5092 "registers must be in range r0-r7");
Jim Grosbach93b3eff2011-08-18 21:50:53 +00005093 // If we should have writeback, then there should be a '!' token.
Jim Grosbach76ecc3d2011-09-07 18:05:34 +00005094 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
Jim Grosbach93b3eff2011-08-18 21:50:53 +00005095 return Error(Operands[2]->getStartLoc(),
5096 "writeback operator '!' expected");
Jim Grosbach76ecc3d2011-09-07 18:05:34 +00005097 // If we should not have writeback, there must not be a '!'. This is
5098 // true even for the 32-bit wide encodings.
Jim Grosbachaa875f82011-08-23 18:13:04 +00005099 if (listContainsBase && hasWritebackToken)
Jim Grosbach7260c6a2011-08-22 23:01:07 +00005100 return Error(Operands[3]->getStartLoc(),
5101 "writeback operator '!' not allowed when base register "
5102 "in register list");
Jim Grosbach93b3eff2011-08-18 21:50:53 +00005103
5104 break;
5105 }
Jim Grosbach76ecc3d2011-09-07 18:05:34 +00005106 case ARM::t2LDMIA_UPD: {
5107 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5108 return Error(Operands[4]->getStartLoc(),
5109 "writeback operator '!' not allowed when base register "
5110 "in register list");
5111 break;
5112 }
Jim Grosbach54026372011-11-10 23:17:11 +00005113 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5114 // so only issue a diagnostic for thumb1. The instructions will be
5115 // switched to the t2 encodings in processInstruction() if necessary.
Jim Grosbach6dcafc02011-08-22 23:17:34 +00005116 case ARM::tPOP: {
Jim Grosbachaa875f82011-08-23 18:13:04 +00005117 bool listContainsBase;
Jim Grosbach54026372011-11-10 23:17:11 +00005118 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5119 !isThumbTwo())
Jim Grosbachaa875f82011-08-23 18:13:04 +00005120 return Error(Operands[2]->getStartLoc(),
5121 "registers must be in range r0-r7 or pc");
Jim Grosbach6dcafc02011-08-22 23:17:34 +00005122 break;
5123 }
5124 case ARM::tPUSH: {
Jim Grosbachaa875f82011-08-23 18:13:04 +00005125 bool listContainsBase;
Jim Grosbach54026372011-11-10 23:17:11 +00005126 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5127 !isThumbTwo())
Jim Grosbachaa875f82011-08-23 18:13:04 +00005128 return Error(Operands[2]->getStartLoc(),
5129 "registers must be in range r0-r7 or lr");
Jim Grosbach6dcafc02011-08-22 23:17:34 +00005130 break;
5131 }
Jim Grosbach1e84f192011-08-23 18:15:37 +00005132 case ARM::tSTMIA_UPD: {
5133 bool listContainsBase;
Jim Grosbach8213c962011-09-16 20:50:13 +00005134 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
Jim Grosbach1e84f192011-08-23 18:15:37 +00005135 return Error(Operands[4]->getStartLoc(),
5136 "registers must be in range r0-r7");
5137 break;
5138 }
Jim Grosbach189610f2011-07-26 18:25:39 +00005139 }
5140
5141 return false;
5142}
5143
Jim Grosbach5b484312011-12-20 20:46:29 +00005144static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) {
Jim Grosbach84defb52011-12-02 22:34:51 +00005145 switch(Opc) {
5146 default: assert(0 && "unexpected opcode!");
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005147 // VST1LN
5148 case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8:
5149 case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8:
5150 case ARM::VST1LNdWB_fixed_Asm_U8:
Jim Grosbach5b484312011-12-20 20:46:29 +00005151 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005152 return ARM::VST1LNd8_UPD;
5153 case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16:
5154 case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16:
5155 case ARM::VST1LNdWB_fixed_Asm_U16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005156 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005157 return ARM::VST1LNd16_UPD;
5158 case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F:
5159 case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32:
5160 case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005161 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005162 return ARM::VST1LNd32_UPD;
5163 case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8:
5164 case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8:
5165 case ARM::VST1LNdWB_register_Asm_U8:
Jim Grosbach5b484312011-12-20 20:46:29 +00005166 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005167 return ARM::VST1LNd8_UPD;
5168 case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16:
5169 case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16:
5170 case ARM::VST1LNdWB_register_Asm_U16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005171 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005172 return ARM::VST1LNd16_UPD;
5173 case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F:
5174 case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32:
5175 case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005176 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005177 return ARM::VST1LNd32_UPD;
5178 case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8:
5179 case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8:
5180 case ARM::VST1LNdAsm_U8:
Jim Grosbach5b484312011-12-20 20:46:29 +00005181 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005182 return ARM::VST1LNd8;
5183 case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16:
5184 case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16:
5185 case ARM::VST1LNdAsm_U16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005186 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005187 return ARM::VST1LNd16;
5188 case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F:
5189 case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32:
5190 case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005191 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005192 return ARM::VST1LNd32;
5193
5194 // VST2LN
5195 case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
5196 case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
5197 case ARM::VST2LNdWB_fixed_Asm_U8:
Jim Grosbach5b484312011-12-20 20:46:29 +00005198 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005199 return ARM::VST2LNd8_UPD;
5200 case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16:
5201 case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16:
5202 case ARM::VST2LNdWB_fixed_Asm_U16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005203 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005204 return ARM::VST2LNd16_UPD;
5205 case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
5206 case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
5207 case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005208 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005209 return ARM::VST2LNd32_UPD;
Jim Grosbach5b484312011-12-20 20:46:29 +00005210 case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
5211 case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
5212 case ARM::VST2LNqWB_fixed_Asm_U16:
5213 Spacing = 2;
5214 return ARM::VST2LNq16_UPD;
5215 case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F:
5216 case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32:
5217 case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32:
5218 Spacing = 2;
5219 return ARM::VST2LNq32_UPD;
5220
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005221 case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
5222 case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
5223 case ARM::VST2LNdWB_register_Asm_U8:
Jim Grosbach5b484312011-12-20 20:46:29 +00005224 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005225 return ARM::VST2LNd8_UPD;
5226 case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16:
5227 case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16:
5228 case ARM::VST2LNdWB_register_Asm_U16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005229 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005230 return ARM::VST2LNd16_UPD;
5231 case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
5232 case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
5233 case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005234 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005235 return ARM::VST2LNd32_UPD;
Jim Grosbach5b484312011-12-20 20:46:29 +00005236 case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
5237 case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
5238 case ARM::VST2LNqWB_register_Asm_U16:
5239 Spacing = 2;
5240 return ARM::VST2LNq16_UPD;
5241 case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F:
5242 case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32:
5243 case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32:
5244 Spacing = 2;
5245 return ARM::VST2LNq32_UPD;
5246
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005247 case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8:
5248 case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8:
5249 case ARM::VST2LNdAsm_U8:
Jim Grosbach5b484312011-12-20 20:46:29 +00005250 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005251 return ARM::VST2LNd8;
5252 case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16:
5253 case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
5254 case ARM::VST2LNdAsm_U16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005255 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005256 return ARM::VST2LNd16;
5257 case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
5258 case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32:
5259 case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005260 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005261 return ARM::VST2LNd32;
Jim Grosbach5b484312011-12-20 20:46:29 +00005262 case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
5263 case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16:
5264 case ARM::VST2LNqAsm_U16:
5265 Spacing = 2;
5266 return ARM::VST2LNq16;
5267 case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F:
5268 case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32:
5269 case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:
5270 Spacing = 2;
5271 return ARM::VST2LNq32;
Jim Grosbach84defb52011-12-02 22:34:51 +00005272 }
5273}
5274
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005275static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) {
Jim Grosbach7636bf62011-12-02 00:35:16 +00005276 switch(Opc) {
5277 default: assert(0 && "unexpected opcode!");
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005278 // VLD1LN
5279 case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8:
5280 case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8:
5281 case ARM::VLD1LNdWB_fixed_Asm_U8:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005282 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005283 return ARM::VLD1LNd8_UPD;
5284 case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16:
5285 case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16:
5286 case ARM::VLD1LNdWB_fixed_Asm_U16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005287 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005288 return ARM::VLD1LNd16_UPD;
5289 case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F:
5290 case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32:
5291 case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005292 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005293 return ARM::VLD1LNd32_UPD;
5294 case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8:
5295 case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8:
5296 case ARM::VLD1LNdWB_register_Asm_U8:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005297 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005298 return ARM::VLD1LNd8_UPD;
5299 case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16:
5300 case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16:
5301 case ARM::VLD1LNdWB_register_Asm_U16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005302 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005303 return ARM::VLD1LNd16_UPD;
5304 case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F:
5305 case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32:
5306 case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005307 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005308 return ARM::VLD1LNd32_UPD;
5309 case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8:
5310 case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8:
5311 case ARM::VLD1LNdAsm_U8:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005312 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005313 return ARM::VLD1LNd8;
5314 case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16:
5315 case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
5316 case ARM::VLD1LNdAsm_U16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005317 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005318 return ARM::VLD1LNd16;
5319 case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
5320 case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32:
5321 case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005322 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005323 return ARM::VLD1LNd32;
5324
5325 // VLD2LN
5326 case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
5327 case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
5328 case ARM::VLD2LNdWB_fixed_Asm_U8:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005329 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005330 return ARM::VLD2LNd8_UPD;
5331 case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16:
5332 case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16:
5333 case ARM::VLD2LNdWB_fixed_Asm_U16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005334 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005335 return ARM::VLD2LNd16_UPD;
5336 case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
5337 case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
5338 case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005339 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005340 return ARM::VLD2LNd32_UPD;
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005341 case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
5342 case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
5343 case ARM::VLD2LNqWB_fixed_Asm_U16:
5344 Spacing = 1;
5345 return ARM::VLD2LNq16_UPD;
5346 case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
5347 case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
5348 case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32:
5349 Spacing = 2;
5350 return ARM::VLD2LNq32_UPD;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005351 case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
5352 case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
5353 case ARM::VLD2LNdWB_register_Asm_U8:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005354 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005355 return ARM::VLD2LNd8_UPD;
5356 case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16:
5357 case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16:
5358 case ARM::VLD2LNdWB_register_Asm_U16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005359 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005360 return ARM::VLD2LNd16_UPD;
5361 case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
5362 case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
5363 case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005364 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005365 return ARM::VLD2LNd32_UPD;
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005366 case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
5367 case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
5368 case ARM::VLD2LNqWB_register_Asm_U16:
5369 Spacing = 2;
5370 return ARM::VLD2LNq16_UPD;
5371 case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
5372 case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
5373 case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32:
5374 Spacing = 2;
5375 return ARM::VLD2LNq32_UPD;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005376 case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8:
5377 case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8:
5378 case ARM::VLD2LNdAsm_U8:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005379 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005380 return ARM::VLD2LNd8;
5381 case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16:
5382 case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
5383 case ARM::VLD2LNdAsm_U16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005384 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005385 return ARM::VLD2LNd16;
5386 case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
5387 case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32:
5388 case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005389 Spacing = 1;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005390 return ARM::VLD2LNd32;
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005391 case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
5392 case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16:
5393 case ARM::VLD2LNqAsm_U16:
5394 Spacing = 2;
5395 return ARM::VLD2LNq16;
5396 case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F:
5397 case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32:
5398 case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32:
5399 Spacing = 2;
5400 return ARM::VLD2LNq32;
Jim Grosbach7636bf62011-12-02 00:35:16 +00005401 }
5402}
5403
Jim Grosbach83ec8772011-11-10 23:42:14 +00005404bool ARMAsmParser::
Jim Grosbachf8fce712011-08-11 17:35:48 +00005405processInstruction(MCInst &Inst,
5406 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5407 switch (Inst.getOpcode()) {
Jim Grosbach0b4c6732012-01-18 22:46:46 +00005408 // Aliases for alternate PC+imm syntax of LDR instructions.
5409 case ARM::t2LDRpcrel:
5410 Inst.setOpcode(ARM::t2LDRpci);
5411 return true;
5412 case ARM::t2LDRBpcrel:
5413 Inst.setOpcode(ARM::t2LDRBpci);
5414 return true;
5415 case ARM::t2LDRHpcrel:
5416 Inst.setOpcode(ARM::t2LDRHpci);
5417 return true;
5418 case ARM::t2LDRSBpcrel:
5419 Inst.setOpcode(ARM::t2LDRSBpci);
5420 return true;
5421 case ARM::t2LDRSHpcrel:
5422 Inst.setOpcode(ARM::t2LDRSHpci);
5423 return true;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005424 // Handle NEON VST complex aliases.
5425 case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8:
5426 case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8:
5427 case ARM::VST1LNdWB_register_Asm_U8: case ARM::VST1LNdWB_register_Asm_16:
5428 case ARM::VST1LNdWB_register_Asm_P16: case ARM::VST1LNdWB_register_Asm_I16:
5429 case ARM::VST1LNdWB_register_Asm_S16: case ARM::VST1LNdWB_register_Asm_U16:
5430 case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F:
5431 case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32:
5432 case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: {
Jim Grosbach84defb52011-12-02 22:34:51 +00005433 MCInst TmpInst;
5434 // Shuffle the operands around so the lane index operand is in the
5435 // right place.
Jim Grosbach5b484312011-12-20 20:46:29 +00005436 unsigned Spacing;
5437 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach84defb52011-12-02 22:34:51 +00005438 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5439 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5440 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5441 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5442 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5443 TmpInst.addOperand(Inst.getOperand(1)); // lane
5444 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5445 TmpInst.addOperand(Inst.getOperand(6));
5446 Inst = TmpInst;
5447 return true;
5448 }
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005449
Jim Grosbach5b484312011-12-20 20:46:29 +00005450 case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
5451 case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
5452 case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005453 case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16:
5454 case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005455 case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005456 case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005457 case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
5458 case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
5459 case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
5460 case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32:
5461 case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32:
5462 case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32:
5463 case ARM::VST2LNqWB_register_Asm_U32: {
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005464 MCInst TmpInst;
5465 // Shuffle the operands around so the lane index operand is in the
5466 // right place.
Jim Grosbach5b484312011-12-20 20:46:29 +00005467 unsigned Spacing;
5468 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005469 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5470 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5471 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5472 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5473 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach5b484312011-12-20 20:46:29 +00005474 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5475 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005476 TmpInst.addOperand(Inst.getOperand(1)); // lane
5477 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5478 TmpInst.addOperand(Inst.getOperand(6));
5479 Inst = TmpInst;
5480 return true;
5481 }
5482 case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8:
5483 case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8:
5484 case ARM::VST1LNdWB_fixed_Asm_U8: case ARM::VST1LNdWB_fixed_Asm_16:
5485 case ARM::VST1LNdWB_fixed_Asm_P16: case ARM::VST1LNdWB_fixed_Asm_I16:
5486 case ARM::VST1LNdWB_fixed_Asm_S16: case ARM::VST1LNdWB_fixed_Asm_U16:
5487 case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F:
5488 case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32:
5489 case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: {
Jim Grosbach84defb52011-12-02 22:34:51 +00005490 MCInst TmpInst;
5491 // Shuffle the operands around so the lane index operand is in the
5492 // right place.
Jim Grosbach5b484312011-12-20 20:46:29 +00005493 unsigned Spacing;
5494 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach84defb52011-12-02 22:34:51 +00005495 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5496 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5497 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5498 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5499 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5500 TmpInst.addOperand(Inst.getOperand(1)); // lane
5501 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5502 TmpInst.addOperand(Inst.getOperand(5));
5503 Inst = TmpInst;
5504 return true;
5505 }
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005506
Jim Grosbach5b484312011-12-20 20:46:29 +00005507 case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
5508 case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
5509 case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005510 case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16:
5511 case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005512 case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005513 case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005514 case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
5515 case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
5516 case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
5517 case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32:
5518 case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32:
5519 case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32:
5520 case ARM::VST2LNqWB_fixed_Asm_U32: {
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005521 MCInst TmpInst;
5522 // Shuffle the operands around so the lane index operand is in the
5523 // right place.
Jim Grosbach5b484312011-12-20 20:46:29 +00005524 unsigned Spacing;
5525 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005526 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5527 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5528 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5529 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5530 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach5b484312011-12-20 20:46:29 +00005531 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5532 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005533 TmpInst.addOperand(Inst.getOperand(1)); // lane
5534 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5535 TmpInst.addOperand(Inst.getOperand(5));
5536 Inst = TmpInst;
5537 return true;
5538 }
5539 case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: case ARM::VST1LNdAsm_I8:
5540 case ARM::VST1LNdAsm_S8: case ARM::VST1LNdAsm_U8: case ARM::VST1LNdAsm_16:
5541 case ARM::VST1LNdAsm_P16: case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16:
5542 case ARM::VST1LNdAsm_U16: case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F:
5543 case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: case ARM::VST1LNdAsm_S32:
Jim Grosbach84defb52011-12-02 22:34:51 +00005544 case ARM::VST1LNdAsm_U32: {
5545 MCInst TmpInst;
5546 // Shuffle the operands around so the lane index operand is in the
5547 // right place.
Jim Grosbach5b484312011-12-20 20:46:29 +00005548 unsigned Spacing;
5549 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach84defb52011-12-02 22:34:51 +00005550 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5551 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5552 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5553 TmpInst.addOperand(Inst.getOperand(1)); // lane
5554 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5555 TmpInst.addOperand(Inst.getOperand(5));
5556 Inst = TmpInst;
5557 return true;
5558 }
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005559
Jim Grosbach5b484312011-12-20 20:46:29 +00005560 case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8:
5561 case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005562 case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005563 case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005564 case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005565 case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
5566 case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16:
5567 case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32:
5568 case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005569 MCInst TmpInst;
5570 // Shuffle the operands around so the lane index operand is in the
5571 // right place.
Jim Grosbach5b484312011-12-20 20:46:29 +00005572 unsigned Spacing;
5573 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005574 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5575 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5576 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach5b484312011-12-20 20:46:29 +00005577 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5578 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005579 TmpInst.addOperand(Inst.getOperand(1)); // lane
5580 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5581 TmpInst.addOperand(Inst.getOperand(5));
5582 Inst = TmpInst;
5583 return true;
5584 }
5585 // Handle NEON VLD complex aliases.
5586 case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8:
5587 case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8:
5588 case ARM::VLD1LNdWB_register_Asm_U8: case ARM::VLD1LNdWB_register_Asm_16:
5589 case ARM::VLD1LNdWB_register_Asm_P16: case ARM::VLD1LNdWB_register_Asm_I16:
5590 case ARM::VLD1LNdWB_register_Asm_S16: case ARM::VLD1LNdWB_register_Asm_U16:
5591 case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F:
5592 case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32:
5593 case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: {
Jim Grosbach872eedb2011-12-02 22:01:52 +00005594 MCInst TmpInst;
5595 // Shuffle the operands around so the lane index operand is in the
5596 // right place.
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005597 unsigned Spacing;
5598 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach872eedb2011-12-02 22:01:52 +00005599 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5600 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5601 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5602 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5603 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5604 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5605 TmpInst.addOperand(Inst.getOperand(1)); // lane
5606 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5607 TmpInst.addOperand(Inst.getOperand(6));
5608 Inst = TmpInst;
5609 return true;
5610 }
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005611
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005612 case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
5613 case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
5614 case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005615 case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16:
5616 case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005617 case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005618 case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005619 case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005620 case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
5621 case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
5622 case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32:
5623 case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32:
5624 case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32:
5625 case ARM::VLD2LNqWB_register_Asm_U32: {
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005626 MCInst TmpInst;
5627 // Shuffle the operands around so the lane index operand is in the
5628 // right place.
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005629 unsigned Spacing;
5630 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005631 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005632 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5633 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005634 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5635 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5636 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5637 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5638 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005639 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5640 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005641 TmpInst.addOperand(Inst.getOperand(1)); // lane
5642 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5643 TmpInst.addOperand(Inst.getOperand(6));
5644 Inst = TmpInst;
5645 return true;
5646 }
5647
5648 case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8:
5649 case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8:
5650 case ARM::VLD1LNdWB_fixed_Asm_U8: case ARM::VLD1LNdWB_fixed_Asm_16:
5651 case ARM::VLD1LNdWB_fixed_Asm_P16: case ARM::VLD1LNdWB_fixed_Asm_I16:
5652 case ARM::VLD1LNdWB_fixed_Asm_S16: case ARM::VLD1LNdWB_fixed_Asm_U16:
5653 case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F:
5654 case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32:
5655 case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: {
Jim Grosbach872eedb2011-12-02 22:01:52 +00005656 MCInst TmpInst;
5657 // Shuffle the operands around so the lane index operand is in the
5658 // right place.
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005659 unsigned Spacing;
5660 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach872eedb2011-12-02 22:01:52 +00005661 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5662 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5663 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5664 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5665 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5666 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5667 TmpInst.addOperand(Inst.getOperand(1)); // lane
5668 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5669 TmpInst.addOperand(Inst.getOperand(5));
5670 Inst = TmpInst;
5671 return true;
5672 }
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005673
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005674 case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
5675 case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
5676 case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005677 case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16:
5678 case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005679 case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005680 case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005681 case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
Jim Grosbach5b484312011-12-20 20:46:29 +00005682 case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
5683 case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
5684 case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32:
5685 case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32:
5686 case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32:
5687 case ARM::VLD2LNqWB_fixed_Asm_U32: {
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005688 MCInst TmpInst;
5689 // Shuffle the operands around so the lane index operand is in the
5690 // right place.
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005691 unsigned Spacing;
5692 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005693 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5695 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005696 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5697 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5698 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5699 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5700 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005701 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5702 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005703 TmpInst.addOperand(Inst.getOperand(1)); // lane
5704 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5705 TmpInst.addOperand(Inst.getOperand(5));
5706 Inst = TmpInst;
5707 return true;
5708 }
5709
Jim Grosbach5b484312011-12-20 20:46:29 +00005710 case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8:
5711 case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005712 case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
Jim Grosbach5b484312011-12-20 20:46:29 +00005713 case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005714 case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32:
Jim Grosbachdad2f8e2011-12-02 18:52:30 +00005715 case ARM::VLD1LNdAsm_U32: {
Jim Grosbach7636bf62011-12-02 00:35:16 +00005716 MCInst TmpInst;
5717 // Shuffle the operands around so the lane index operand is in the
5718 // right place.
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005719 unsigned Spacing;
5720 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach7636bf62011-12-02 00:35:16 +00005721 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5722 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5723 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5724 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5725 TmpInst.addOperand(Inst.getOperand(1)); // lane
5726 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5727 TmpInst.addOperand(Inst.getOperand(5));
5728 Inst = TmpInst;
5729 return true;
5730 }
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005731
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005732 case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8:
5733 case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005734 case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005735 case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005736 case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32:
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005737 case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
5738 case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16:
5739 case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32:
5740 case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32:
5741 case ARM::VLD2LNqAsm_U32: {
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005742 MCInst TmpInst;
5743 // Shuffle the operands around so the lane index operand is in the
5744 // right place.
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005745 unsigned Spacing;
5746 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005747 TmpInst.addOperand(Inst.getOperand(0)); // Vd
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005748 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5749 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005750 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5751 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5752 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005753 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5754 Spacing));
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005755 TmpInst.addOperand(Inst.getOperand(1)); // lane
5756 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5757 TmpInst.addOperand(Inst.getOperand(5));
5758 Inst = TmpInst;
5759 return true;
5760 }
Jim Grosbach863d2af2011-12-13 22:45:11 +00005761 // Handle the Thumb2 mode MOV complex aliases.
Jim Grosbach2cc5cda2011-12-21 20:54:00 +00005762 case ARM::t2MOVsr:
5763 case ARM::t2MOVSsr: {
5764 // Which instruction to expand to depends on the CCOut operand and
5765 // whether we're in an IT block if the register operands are low
5766 // registers.
5767 bool isNarrow = false;
5768 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5769 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5770 isARMLowRegister(Inst.getOperand(2).getReg()) &&
5771 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
5772 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
5773 isNarrow = true;
5774 MCInst TmpInst;
5775 unsigned newOpc;
5776 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
5777 default: llvm_unreachable("unexpected opcode!");
5778 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
5779 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
5780 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
5781 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
5782 }
5783 TmpInst.setOpcode(newOpc);
5784 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5785 if (isNarrow)
5786 TmpInst.addOperand(MCOperand::CreateReg(
5787 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
5788 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5789 TmpInst.addOperand(Inst.getOperand(2)); // Rm
5790 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5791 TmpInst.addOperand(Inst.getOperand(5));
5792 if (!isNarrow)
5793 TmpInst.addOperand(MCOperand::CreateReg(
5794 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
5795 Inst = TmpInst;
5796 return true;
5797 }
Jim Grosbach863d2af2011-12-13 22:45:11 +00005798 case ARM::t2MOVsi:
5799 case ARM::t2MOVSsi: {
5800 // Which instruction to expand to depends on the CCOut operand and
5801 // whether we're in an IT block if the register operands are low
5802 // registers.
5803 bool isNarrow = false;
5804 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5805 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5806 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
5807 isNarrow = true;
5808 MCInst TmpInst;
5809 unsigned newOpc;
5810 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
5811 default: llvm_unreachable("unexpected opcode!");
5812 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
5813 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
5814 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
5815 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
Jim Grosbach520dc782011-12-21 21:04:19 +00005816 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
Jim Grosbach863d2af2011-12-13 22:45:11 +00005817 }
5818 unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
5819 if (Ammount == 32) Ammount = 0;
5820 TmpInst.setOpcode(newOpc);
5821 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5822 if (isNarrow)
5823 TmpInst.addOperand(MCOperand::CreateReg(
5824 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
5825 TmpInst.addOperand(Inst.getOperand(1)); // Rn
Jim Grosbach520dc782011-12-21 21:04:19 +00005826 if (newOpc != ARM::t2RRX)
5827 TmpInst.addOperand(MCOperand::CreateImm(Ammount));
Jim Grosbach863d2af2011-12-13 22:45:11 +00005828 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5829 TmpInst.addOperand(Inst.getOperand(4));
5830 if (!isNarrow)
5831 TmpInst.addOperand(MCOperand::CreateReg(
5832 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
5833 Inst = TmpInst;
5834 return true;
5835 }
5836 // Handle the ARM mode MOV complex aliases.
Jim Grosbach23f22072011-11-16 18:31:45 +00005837 case ARM::ASRr:
5838 case ARM::LSRr:
5839 case ARM::LSLr:
5840 case ARM::RORr: {
5841 ARM_AM::ShiftOpc ShiftTy;
5842 switch(Inst.getOpcode()) {
5843 default: llvm_unreachable("unexpected opcode!");
5844 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
5845 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
5846 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
5847 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
5848 }
Jim Grosbach23f22072011-11-16 18:31:45 +00005849 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
5850 MCInst TmpInst;
5851 TmpInst.setOpcode(ARM::MOVsr);
5852 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5853 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5854 TmpInst.addOperand(Inst.getOperand(2)); // Rm
5855 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5856 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5857 TmpInst.addOperand(Inst.getOperand(4));
5858 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
5859 Inst = TmpInst;
5860 return true;
5861 }
Jim Grosbachee10ff82011-11-10 19:18:01 +00005862 case ARM::ASRi:
5863 case ARM::LSRi:
5864 case ARM::LSLi:
5865 case ARM::RORi: {
5866 ARM_AM::ShiftOpc ShiftTy;
Jim Grosbachee10ff82011-11-10 19:18:01 +00005867 switch(Inst.getOpcode()) {
5868 default: llvm_unreachable("unexpected opcode!");
5869 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
5870 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
5871 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
5872 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
5873 }
5874 // A shift by zero is a plain MOVr, not a MOVsi.
Jim Grosbach48b368b2011-11-16 19:05:59 +00005875 unsigned Amt = Inst.getOperand(2).getImm();
Jim Grosbachee10ff82011-11-10 19:18:01 +00005876 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
5877 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
Jim Grosbach71810ab2011-11-10 16:44:55 +00005878 MCInst TmpInst;
Jim Grosbachee10ff82011-11-10 19:18:01 +00005879 TmpInst.setOpcode(Opc);
Jim Grosbach71810ab2011-11-10 16:44:55 +00005880 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5881 TmpInst.addOperand(Inst.getOperand(1)); // Rn
Jim Grosbachee10ff82011-11-10 19:18:01 +00005882 if (Opc == ARM::MOVsi)
5883 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
Jim Grosbach71810ab2011-11-10 16:44:55 +00005884 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5885 TmpInst.addOperand(Inst.getOperand(4));
5886 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
5887 Inst = TmpInst;
Jim Grosbach83ec8772011-11-10 23:42:14 +00005888 return true;
Jim Grosbach71810ab2011-11-10 16:44:55 +00005889 }
Jim Grosbach48b368b2011-11-16 19:05:59 +00005890 case ARM::RRXi: {
5891 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
5892 MCInst TmpInst;
5893 TmpInst.setOpcode(ARM::MOVsi);
5894 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5895 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5896 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5897 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5898 TmpInst.addOperand(Inst.getOperand(3));
5899 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
5900 Inst = TmpInst;
5901 return true;
5902 }
Jim Grosbach0352b462011-11-10 23:58:34 +00005903 case ARM::t2LDMIA_UPD: {
5904 // If this is a load of a single register, then we should use
5905 // a post-indexed LDR instruction instead, per the ARM ARM.
5906 if (Inst.getNumOperands() != 5)
5907 return false;
5908 MCInst TmpInst;
5909 TmpInst.setOpcode(ARM::t2LDR_POST);
5910 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5911 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5912 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5913 TmpInst.addOperand(MCOperand::CreateImm(4));
5914 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5915 TmpInst.addOperand(Inst.getOperand(3));
5916 Inst = TmpInst;
5917 return true;
5918 }
5919 case ARM::t2STMDB_UPD: {
5920 // If this is a store of a single register, then we should use
5921 // a pre-indexed STR instruction instead, per the ARM ARM.
5922 if (Inst.getNumOperands() != 5)
5923 return false;
5924 MCInst TmpInst;
5925 TmpInst.setOpcode(ARM::t2STR_PRE);
5926 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5927 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5928 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5929 TmpInst.addOperand(MCOperand::CreateImm(-4));
5930 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5931 TmpInst.addOperand(Inst.getOperand(3));
5932 Inst = TmpInst;
5933 return true;
5934 }
Jim Grosbachf8fce712011-08-11 17:35:48 +00005935 case ARM::LDMIA_UPD:
5936 // If this is a load of a single register via a 'pop', then we should use
5937 // a post-indexed LDR instruction instead, per the ARM ARM.
5938 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
5939 Inst.getNumOperands() == 5) {
5940 MCInst TmpInst;
5941 TmpInst.setOpcode(ARM::LDR_POST_IMM);
5942 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5943 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5944 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5945 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
5946 TmpInst.addOperand(MCOperand::CreateImm(4));
5947 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5948 TmpInst.addOperand(Inst.getOperand(3));
5949 Inst = TmpInst;
Jim Grosbach83ec8772011-11-10 23:42:14 +00005950 return true;
Jim Grosbachf8fce712011-08-11 17:35:48 +00005951 }
5952 break;
Jim Grosbachf6713912011-08-11 18:07:11 +00005953 case ARM::STMDB_UPD:
5954 // If this is a store of a single register via a 'push', then we should use
5955 // a pre-indexed STR instruction instead, per the ARM ARM.
5956 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
5957 Inst.getNumOperands() == 5) {
5958 MCInst TmpInst;
5959 TmpInst.setOpcode(ARM::STR_PRE_IMM);
5960 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5961 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5962 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
5963 TmpInst.addOperand(MCOperand::CreateImm(-4));
5964 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5965 TmpInst.addOperand(Inst.getOperand(3));
5966 Inst = TmpInst;
5967 }
5968 break;
Jim Grosbachda847862011-12-05 21:06:26 +00005969 case ARM::t2ADDri12:
5970 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
5971 // mnemonic was used (not "addw"), encoding T3 is preferred.
5972 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
5973 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
5974 break;
5975 Inst.setOpcode(ARM::t2ADDri);
5976 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
5977 break;
5978 case ARM::t2SUBri12:
5979 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
5980 // mnemonic was used (not "subw"), encoding T3 is preferred.
5981 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
5982 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
5983 break;
5984 Inst.setOpcode(ARM::t2SUBri);
5985 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
5986 break;
Jim Grosbach89e2aa62011-08-16 23:57:34 +00005987 case ARM::tADDi8:
Jim Grosbach0f3abd82011-08-31 17:07:33 +00005988 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
5989 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
5990 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
5991 // to encoding T1 if <Rd> is omitted."
Jim Grosbach83ec8772011-11-10 23:42:14 +00005992 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
Jim Grosbach89e2aa62011-08-16 23:57:34 +00005993 Inst.setOpcode(ARM::tADDi3);
Jim Grosbach83ec8772011-11-10 23:42:14 +00005994 return true;
5995 }
Jim Grosbach89e2aa62011-08-16 23:57:34 +00005996 break;
Jim Grosbachf67e8552011-09-16 22:58:42 +00005997 case ARM::tSUBi8:
5998 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
5999 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6000 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6001 // to encoding T1 if <Rd> is omitted."
Jim Grosbach83ec8772011-11-10 23:42:14 +00006002 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
Jim Grosbachf67e8552011-09-16 22:58:42 +00006003 Inst.setOpcode(ARM::tSUBi3);
Jim Grosbach83ec8772011-11-10 23:42:14 +00006004 return true;
6005 }
Jim Grosbachf67e8552011-09-16 22:58:42 +00006006 break;
Jim Grosbach927b9df2011-12-05 22:16:39 +00006007 case ARM::t2ADDrr: {
6008 // If the destination and first source operand are the same, and
6009 // there's no setting of the flags, use encoding T2 instead of T3.
6010 // Note that this is only for ADD, not SUB. This mirrors the system
6011 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
6012 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
6013 Inst.getOperand(5).getReg() != 0 ||
Jim Grosbach713c7022011-12-05 22:27:04 +00006014 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6015 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
Jim Grosbach927b9df2011-12-05 22:16:39 +00006016 break;
6017 MCInst TmpInst;
6018 TmpInst.setOpcode(ARM::tADDhirr);
6019 TmpInst.addOperand(Inst.getOperand(0));
6020 TmpInst.addOperand(Inst.getOperand(0));
6021 TmpInst.addOperand(Inst.getOperand(2));
6022 TmpInst.addOperand(Inst.getOperand(3));
6023 TmpInst.addOperand(Inst.getOperand(4));
6024 Inst = TmpInst;
6025 return true;
6026 }
Owen Anderson51f6a7a2011-09-09 21:48:23 +00006027 case ARM::tB:
6028 // A Thumb conditional branch outside of an IT block is a tBcc.
Jim Grosbach83ec8772011-11-10 23:42:14 +00006029 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
Owen Anderson51f6a7a2011-09-09 21:48:23 +00006030 Inst.setOpcode(ARM::tBcc);
Jim Grosbach83ec8772011-11-10 23:42:14 +00006031 return true;
6032 }
Owen Anderson51f6a7a2011-09-09 21:48:23 +00006033 break;
6034 case ARM::t2B:
6035 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
Jim Grosbach83ec8772011-11-10 23:42:14 +00006036 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
Owen Anderson51f6a7a2011-09-09 21:48:23 +00006037 Inst.setOpcode(ARM::t2Bcc);
Jim Grosbach83ec8772011-11-10 23:42:14 +00006038 return true;
6039 }
Owen Anderson51f6a7a2011-09-09 21:48:23 +00006040 break;
Jim Grosbachc0755102011-08-31 21:17:31 +00006041 case ARM::t2Bcc:
Jim Grosbacha1109882011-09-02 23:22:08 +00006042 // If the conditional is AL or we're in an IT block, we really want t2B.
Jim Grosbach83ec8772011-11-10 23:42:14 +00006043 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
Jim Grosbachc0755102011-08-31 21:17:31 +00006044 Inst.setOpcode(ARM::t2B);
Jim Grosbach83ec8772011-11-10 23:42:14 +00006045 return true;
6046 }
Jim Grosbachc0755102011-08-31 21:17:31 +00006047 break;
Jim Grosbach395b4532011-08-17 22:57:40 +00006048 case ARM::tBcc:
6049 // If the conditional is AL, we really want tB.
Jim Grosbach83ec8772011-11-10 23:42:14 +00006050 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
Jim Grosbach395b4532011-08-17 22:57:40 +00006051 Inst.setOpcode(ARM::tB);
Jim Grosbach83ec8772011-11-10 23:42:14 +00006052 return true;
6053 }
Jim Grosbach3ce23d32011-08-18 16:08:39 +00006054 break;
Jim Grosbach76ecc3d2011-09-07 18:05:34 +00006055 case ARM::tLDMIA: {
6056 // If the register list contains any high registers, or if the writeback
6057 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
6058 // instead if we're in Thumb2. Otherwise, this should have generated
6059 // an error in validateInstruction().
6060 unsigned Rn = Inst.getOperand(0).getReg();
6061 bool hasWritebackToken =
6062 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6063 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
6064 bool listContainsBase;
6065 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
6066 (!listContainsBase && !hasWritebackToken) ||
6067 (listContainsBase && hasWritebackToken)) {
6068 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
6069 assert (isThumbTwo());
6070 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
6071 // If we're switching to the updating version, we need to insert
6072 // the writeback tied operand.
6073 if (hasWritebackToken)
6074 Inst.insert(Inst.begin(),
6075 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
Jim Grosbach83ec8772011-11-10 23:42:14 +00006076 return true;
Jim Grosbach76ecc3d2011-09-07 18:05:34 +00006077 }
6078 break;
6079 }
Jim Grosbach8213c962011-09-16 20:50:13 +00006080 case ARM::tSTMIA_UPD: {
6081 // If the register list contains any high registers, we need to use
6082 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
6083 // should have generated an error in validateInstruction().
6084 unsigned Rn = Inst.getOperand(0).getReg();
6085 bool listContainsBase;
6086 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
6087 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
6088 assert (isThumbTwo());
6089 Inst.setOpcode(ARM::t2STMIA_UPD);
Jim Grosbach83ec8772011-11-10 23:42:14 +00006090 return true;
Jim Grosbach8213c962011-09-16 20:50:13 +00006091 }
6092 break;
6093 }
Jim Grosbach54026372011-11-10 23:17:11 +00006094 case ARM::tPOP: {
6095 bool listContainsBase;
6096 // If the register list contains any high registers, we need to use
6097 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
6098 // should have generated an error in validateInstruction().
6099 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
Jim Grosbach83ec8772011-11-10 23:42:14 +00006100 return false;
Jim Grosbach54026372011-11-10 23:17:11 +00006101 assert (isThumbTwo());
6102 Inst.setOpcode(ARM::t2LDMIA_UPD);
6103 // Add the base register and writeback operands.
6104 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6105 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
Jim Grosbach83ec8772011-11-10 23:42:14 +00006106 return true;
Jim Grosbach54026372011-11-10 23:17:11 +00006107 }
6108 case ARM::tPUSH: {
6109 bool listContainsBase;
6110 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
Jim Grosbach83ec8772011-11-10 23:42:14 +00006111 return false;
Jim Grosbach54026372011-11-10 23:17:11 +00006112 assert (isThumbTwo());
6113 Inst.setOpcode(ARM::t2STMDB_UPD);
6114 // Add the base register and writeback operands.
6115 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6116 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
Jim Grosbach83ec8772011-11-10 23:42:14 +00006117 return true;
Jim Grosbach54026372011-11-10 23:17:11 +00006118 }
Jim Grosbach1ad60c22011-09-10 00:15:36 +00006119 case ARM::t2MOVi: {
6120 // If we can use the 16-bit encoding and the user didn't explicitly
6121 // request the 32-bit variant, transform it here.
6122 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6123 Inst.getOperand(1).getImm() <= 255 &&
Jim Grosbachc2d31642011-09-14 19:12:11 +00006124 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
6125 Inst.getOperand(4).getReg() == ARM::CPSR) ||
6126 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
Jim Grosbach1ad60c22011-09-10 00:15:36 +00006127 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
6128 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
6129 // The operands aren't in the same order for tMOVi8...
6130 MCInst TmpInst;
6131 TmpInst.setOpcode(ARM::tMOVi8);
6132 TmpInst.addOperand(Inst.getOperand(0));
6133 TmpInst.addOperand(Inst.getOperand(4));
6134 TmpInst.addOperand(Inst.getOperand(1));
6135 TmpInst.addOperand(Inst.getOperand(2));
6136 TmpInst.addOperand(Inst.getOperand(3));
6137 Inst = TmpInst;
Jim Grosbach83ec8772011-11-10 23:42:14 +00006138 return true;
Jim Grosbach1ad60c22011-09-10 00:15:36 +00006139 }
6140 break;
6141 }
6142 case ARM::t2MOVr: {
6143 // If we can use the 16-bit encoding and the user didn't explicitly
6144 // request the 32-bit variant, transform it here.
6145 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6146 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6147 Inst.getOperand(2).getImm() == ARMCC::AL &&
6148 Inst.getOperand(4).getReg() == ARM::CPSR &&
6149 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
6150 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
6151 // The operands aren't the same for tMOV[S]r... (no cc_out)
6152 MCInst TmpInst;
6153 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
6154 TmpInst.addOperand(Inst.getOperand(0));
6155 TmpInst.addOperand(Inst.getOperand(1));
6156 TmpInst.addOperand(Inst.getOperand(2));
6157 TmpInst.addOperand(Inst.getOperand(3));
6158 Inst = TmpInst;
Jim Grosbach83ec8772011-11-10 23:42:14 +00006159 return true;
Jim Grosbach1ad60c22011-09-10 00:15:36 +00006160 }
6161 break;
6162 }
Jim Grosbach326efe52011-09-19 20:29:33 +00006163 case ARM::t2SXTH:
Jim Grosbach50f1c372011-09-20 00:46:54 +00006164 case ARM::t2SXTB:
6165 case ARM::t2UXTH:
6166 case ARM::t2UXTB: {
Jim Grosbach326efe52011-09-19 20:29:33 +00006167 // If we can use the 16-bit encoding and the user didn't explicitly
6168 // request the 32-bit variant, transform it here.
6169 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6170 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6171 Inst.getOperand(2).getImm() == 0 &&
6172 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
6173 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
Jim Grosbach50f1c372011-09-20 00:46:54 +00006174 unsigned NewOpc;
6175 switch (Inst.getOpcode()) {
6176 default: llvm_unreachable("Illegal opcode!");
6177 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
6178 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
6179 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
6180 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
6181 }
Jim Grosbach326efe52011-09-19 20:29:33 +00006182 // The operands aren't the same for thumb1 (no rotate operand).
6183 MCInst TmpInst;
6184 TmpInst.setOpcode(NewOpc);
6185 TmpInst.addOperand(Inst.getOperand(0));
6186 TmpInst.addOperand(Inst.getOperand(1));
6187 TmpInst.addOperand(Inst.getOperand(3));
6188 TmpInst.addOperand(Inst.getOperand(4));
6189 Inst = TmpInst;
Jim Grosbach83ec8772011-11-10 23:42:14 +00006190 return true;
Jim Grosbach326efe52011-09-19 20:29:33 +00006191 }
6192 break;
6193 }
Jim Grosbach04b5d932011-12-20 00:59:38 +00006194 case ARM::MOVsi: {
6195 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
6196 if (SOpc == ARM_AM::rrx) return false;
6197 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
6198 // Shifting by zero is accepted as a vanilla 'MOVr'
6199 MCInst TmpInst;
6200 TmpInst.setOpcode(ARM::MOVr);
6201 TmpInst.addOperand(Inst.getOperand(0));
6202 TmpInst.addOperand(Inst.getOperand(1));
6203 TmpInst.addOperand(Inst.getOperand(3));
6204 TmpInst.addOperand(Inst.getOperand(4));
6205 TmpInst.addOperand(Inst.getOperand(5));
6206 Inst = TmpInst;
6207 return true;
6208 }
6209 return false;
6210 }
Jim Grosbach8d9550b2011-12-22 18:04:04 +00006211 case ARM::ANDrsi:
6212 case ARM::ORRrsi:
6213 case ARM::EORrsi:
6214 case ARM::BICrsi:
6215 case ARM::SUBrsi:
6216 case ARM::ADDrsi: {
6217 unsigned newOpc;
6218 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
6219 if (SOpc == ARM_AM::rrx) return false;
6220 switch (Inst.getOpcode()) {
Matt Beaumont-Gay19055cc2012-01-03 19:03:59 +00006221 default: assert(0 && "unexpected opcode!");
Jim Grosbach8d9550b2011-12-22 18:04:04 +00006222 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
6223 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
6224 case ARM::EORrsi: newOpc = ARM::EORrr; break;
6225 case ARM::BICrsi: newOpc = ARM::BICrr; break;
6226 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
6227 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
6228 }
6229 // If the shift is by zero, use the non-shifted instruction definition.
6230 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) {
6231 MCInst TmpInst;
6232 TmpInst.setOpcode(newOpc);
6233 TmpInst.addOperand(Inst.getOperand(0));
6234 TmpInst.addOperand(Inst.getOperand(1));
6235 TmpInst.addOperand(Inst.getOperand(2));
6236 TmpInst.addOperand(Inst.getOperand(4));
6237 TmpInst.addOperand(Inst.getOperand(5));
6238 TmpInst.addOperand(Inst.getOperand(6));
6239 Inst = TmpInst;
6240 return true;
6241 }
6242 return false;
6243 }
Jim Grosbach89df9962011-08-26 21:43:41 +00006244 case ARM::t2IT: {
6245 // The mask bits for all but the first condition are represented as
6246 // the low bit of the condition code value implies 't'. We currently
6247 // always have 1 implies 't', so XOR toggle the bits if the low bit
6248 // of the condition code is zero. The encoding also expects the low
6249 // bit of the condition to be encoded as bit 4 of the mask operand,
6250 // so mask that in if needed
6251 MCOperand &MO = Inst.getOperand(1);
6252 unsigned Mask = MO.getImm();
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00006253 unsigned OrigMask = Mask;
6254 unsigned TZ = CountTrailingZeros_32(Mask);
Jim Grosbach89df9962011-08-26 21:43:41 +00006255 if ((Inst.getOperand(0).getImm() & 1) == 0) {
Jim Grosbach89df9962011-08-26 21:43:41 +00006256 assert(Mask && TZ <= 3 && "illegal IT mask value!");
6257 for (unsigned i = 3; i != TZ; --i)
6258 Mask ^= 1 << i;
6259 } else
6260 Mask |= 0x10;
6261 MO.setImm(Mask);
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00006262
6263 // Set up the IT block state according to the IT instruction we just
6264 // matched.
6265 assert(!inITBlock() && "nested IT blocks?!");
6266 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
6267 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
6268 ITState.CurPosition = 0;
6269 ITState.FirstCond = true;
Jim Grosbach89df9962011-08-26 21:43:41 +00006270 break;
6271 }
Jim Grosbachf8fce712011-08-11 17:35:48 +00006272 }
Jim Grosbach83ec8772011-11-10 23:42:14 +00006273 return false;
Jim Grosbachf8fce712011-08-11 17:35:48 +00006274}
6275
Jim Grosbach47a0d522011-08-16 20:45:50 +00006276unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
6277 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
6278 // suffix depending on whether they're in an IT block or not.
Jim Grosbach194bd892011-08-16 22:20:01 +00006279 unsigned Opc = Inst.getOpcode();
Benjamin Kramer1a2f9882011-10-22 16:50:00 +00006280 const MCInstrDesc &MCID = getInstDesc(Opc);
Jim Grosbach47a0d522011-08-16 20:45:50 +00006281 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
6282 assert(MCID.hasOptionalDef() &&
6283 "optionally flag setting instruction missing optional def operand");
6284 assert(MCID.NumOperands == Inst.getNumOperands() &&
6285 "operand count mismatch!");
6286 // Find the optional-def operand (cc_out).
6287 unsigned OpNo;
6288 for (OpNo = 0;
6289 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
6290 ++OpNo)
6291 ;
6292 // If we're parsing Thumb1, reject it completely.
6293 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
6294 return Match_MnemonicFail;
6295 // If we're parsing Thumb2, which form is legal depends on whether we're
6296 // in an IT block.
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00006297 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
6298 !inITBlock())
Jim Grosbach47a0d522011-08-16 20:45:50 +00006299 return Match_RequiresITBlock;
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00006300 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
6301 inITBlock())
6302 return Match_RequiresNotITBlock;
Jim Grosbach47a0d522011-08-16 20:45:50 +00006303 }
Jim Grosbach194bd892011-08-16 22:20:01 +00006304 // Some high-register supporting Thumb1 encodings only allow both registers
6305 // to be from r0-r7 when in Thumb2.
6306 else if (Opc == ARM::tADDhirr && isThumbOne() &&
6307 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6308 isARMLowRegister(Inst.getOperand(2).getReg()))
6309 return Match_RequiresThumb2;
6310 // Others only require ARMv6 or later.
Jim Grosbach4ec6e882011-08-19 20:46:54 +00006311 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
Jim Grosbach194bd892011-08-16 22:20:01 +00006312 isARMLowRegister(Inst.getOperand(0).getReg()) &&
6313 isARMLowRegister(Inst.getOperand(1).getReg()))
6314 return Match_RequiresV6;
Jim Grosbach47a0d522011-08-16 20:45:50 +00006315 return Match_Success;
6316}
6317
Chris Lattnerfa42fad2010-10-28 21:28:01 +00006318bool ARMAsmParser::
6319MatchAndEmitInstruction(SMLoc IDLoc,
6320 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
6321 MCStreamer &Out) {
6322 MCInst Inst;
6323 unsigned ErrorInfo;
Jim Grosbach19cb7f42011-08-15 23:03:29 +00006324 unsigned MatchResult;
Kevin Enderby193c3ac2010-12-09 19:19:43 +00006325 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
Kevin Enderby193c3ac2010-12-09 19:19:43 +00006326 switch (MatchResult) {
Jim Grosbach19cb7f42011-08-15 23:03:29 +00006327 default: break;
Chris Lattnere73d4f82010-10-28 21:41:58 +00006328 case Match_Success:
Jim Grosbach189610f2011-07-26 18:25:39 +00006329 // Context sensitive operand constraints aren't handled by the matcher,
6330 // so check them here.
Jim Grosbacha1109882011-09-02 23:22:08 +00006331 if (validateInstruction(Inst, Operands)) {
6332 // Still progress the IT block, otherwise one wrong condition causes
6333 // nasty cascading errors.
6334 forwardITPosition();
Jim Grosbach189610f2011-07-26 18:25:39 +00006335 return true;
Jim Grosbacha1109882011-09-02 23:22:08 +00006336 }
Jim Grosbach189610f2011-07-26 18:25:39 +00006337
Jim Grosbachf8fce712011-08-11 17:35:48 +00006338 // Some instructions need post-processing to, for example, tweak which
Jim Grosbach83ec8772011-11-10 23:42:14 +00006339 // encoding is selected. Loop on it while changes happen so the
6340 // individual transformations can chain off each other. E.g.,
6341 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
6342 while (processInstruction(Inst, Operands))
6343 ;
Jim Grosbachf8fce712011-08-11 17:35:48 +00006344
Jim Grosbacha1109882011-09-02 23:22:08 +00006345 // Only move forward at the very end so that everything in validate
6346 // and process gets a consistent answer about whether we're in an IT
6347 // block.
6348 forwardITPosition();
6349
Chris Lattnerfa42fad2010-10-28 21:28:01 +00006350 Out.EmitInstruction(Inst);
6351 return false;
Chris Lattnere73d4f82010-10-28 21:41:58 +00006352 case Match_MissingFeature:
6353 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
6354 return true;
6355 case Match_InvalidOperand: {
6356 SMLoc ErrorLoc = IDLoc;
6357 if (ErrorInfo != ~0U) {
6358 if (ErrorInfo >= Operands.size())
6359 return Error(IDLoc, "too few operands for instruction");
Jim Grosbach16c74252010-10-29 14:46:02 +00006360
Chris Lattnere73d4f82010-10-28 21:41:58 +00006361 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
6362 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
6363 }
Jim Grosbach16c74252010-10-29 14:46:02 +00006364
Chris Lattnere73d4f82010-10-28 21:41:58 +00006365 return Error(ErrorLoc, "invalid operand for instruction");
Chris Lattnerfa42fad2010-10-28 21:28:01 +00006366 }
Chris Lattnere73d4f82010-10-28 21:41:58 +00006367 case Match_MnemonicFail:
Jim Grosbach47a0d522011-08-16 20:45:50 +00006368 return Error(IDLoc, "invalid instruction");
Daniel Dunbarb4129152011-02-04 17:12:23 +00006369 case Match_ConversionFail:
Jim Grosbach88ae2bc2011-08-19 22:07:46 +00006370 // The converter function will have already emited a diagnostic.
6371 return true;
Jim Grosbachf8e1e3e2011-08-29 22:24:09 +00006372 case Match_RequiresNotITBlock:
6373 return Error(IDLoc, "flag setting instruction only valid outside IT block");
Jim Grosbach47a0d522011-08-16 20:45:50 +00006374 case Match_RequiresITBlock:
6375 return Error(IDLoc, "instruction only valid inside IT block");
Jim Grosbach194bd892011-08-16 22:20:01 +00006376 case Match_RequiresV6:
6377 return Error(IDLoc, "instruction variant requires ARMv6 or later");
6378 case Match_RequiresThumb2:
6379 return Error(IDLoc, "instruction variant requires Thumb2");
Chris Lattnere73d4f82010-10-28 21:41:58 +00006380 }
Jim Grosbach16c74252010-10-29 14:46:02 +00006381
Eric Christopherc223e2b2010-10-29 09:26:59 +00006382 llvm_unreachable("Implement any new match types added!");
Chris Lattnerfa42fad2010-10-28 21:28:01 +00006383}
6384
Jim Grosbach1355cf12011-07-26 17:10:22 +00006385/// parseDirective parses the arm specific directives
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006386bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
6387 StringRef IDVal = DirectiveID.getIdentifier();
6388 if (IDVal == ".word")
Jim Grosbach1355cf12011-07-26 17:10:22 +00006389 return parseDirectiveWord(4, DirectiveID.getLoc());
Kevin Enderby515d5092009-10-15 20:48:48 +00006390 else if (IDVal == ".thumb")
Jim Grosbach1355cf12011-07-26 17:10:22 +00006391 return parseDirectiveThumb(DirectiveID.getLoc());
Jim Grosbach9a70df92011-12-07 18:04:19 +00006392 else if (IDVal == ".arm")
6393 return parseDirectiveARM(DirectiveID.getLoc());
Kevin Enderby515d5092009-10-15 20:48:48 +00006394 else if (IDVal == ".thumb_func")
Jim Grosbach1355cf12011-07-26 17:10:22 +00006395 return parseDirectiveThumbFunc(DirectiveID.getLoc());
Kevin Enderby515d5092009-10-15 20:48:48 +00006396 else if (IDVal == ".code")
Jim Grosbach1355cf12011-07-26 17:10:22 +00006397 return parseDirectiveCode(DirectiveID.getLoc());
Kevin Enderby515d5092009-10-15 20:48:48 +00006398 else if (IDVal == ".syntax")
Jim Grosbach1355cf12011-07-26 17:10:22 +00006399 return parseDirectiveSyntax(DirectiveID.getLoc());
Jim Grosbacha39cda72011-12-14 02:16:11 +00006400 else if (IDVal == ".unreq")
6401 return parseDirectiveUnreq(DirectiveID.getLoc());
Jason W Kimd7c9e082011-12-20 17:38:12 +00006402 else if (IDVal == ".arch")
6403 return parseDirectiveArch(DirectiveID.getLoc());
6404 else if (IDVal == ".eabi_attribute")
6405 return parseDirectiveEabiAttr(DirectiveID.getLoc());
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006406 return true;
6407}
6408
Jim Grosbach1355cf12011-07-26 17:10:22 +00006409/// parseDirectiveWord
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006410/// ::= .word [ expression (, expression)* ]
Jim Grosbach1355cf12011-07-26 17:10:22 +00006411bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006412 if (getLexer().isNot(AsmToken::EndOfStatement)) {
6413 for (;;) {
6414 const MCExpr *Value;
6415 if (getParser().ParseExpression(Value))
6416 return true;
6417
Chris Lattneraaec2052010-01-19 19:46:13 +00006418 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006419
6420 if (getLexer().is(AsmToken::EndOfStatement))
6421 break;
Jim Grosbach16c74252010-10-29 14:46:02 +00006422
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006423 // FIXME: Improve diagnostic.
6424 if (getLexer().isNot(AsmToken::Comma))
6425 return Error(L, "unexpected token in directive");
Sean Callananb9a25b72010-01-19 20:27:46 +00006426 Parser.Lex();
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006427 }
6428 }
6429
Sean Callananb9a25b72010-01-19 20:27:46 +00006430 Parser.Lex();
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006431 return false;
6432}
6433
Jim Grosbach1355cf12011-07-26 17:10:22 +00006434/// parseDirectiveThumb
Kevin Enderby515d5092009-10-15 20:48:48 +00006435/// ::= .thumb
Jim Grosbach1355cf12011-07-26 17:10:22 +00006436bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
Kevin Enderby515d5092009-10-15 20:48:48 +00006437 if (getLexer().isNot(AsmToken::EndOfStatement))
6438 return Error(L, "unexpected token in directive");
Sean Callananb9a25b72010-01-19 20:27:46 +00006439 Parser.Lex();
Kevin Enderby515d5092009-10-15 20:48:48 +00006440
Jim Grosbach9a70df92011-12-07 18:04:19 +00006441 if (!isThumb())
6442 SwitchMode();
6443 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
6444 return false;
6445}
6446
6447/// parseDirectiveARM
6448/// ::= .arm
6449bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
6450 if (getLexer().isNot(AsmToken::EndOfStatement))
6451 return Error(L, "unexpected token in directive");
6452 Parser.Lex();
6453
6454 if (isThumb())
6455 SwitchMode();
6456 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
Kevin Enderby515d5092009-10-15 20:48:48 +00006457 return false;
6458}
6459
Jim Grosbach1355cf12011-07-26 17:10:22 +00006460/// parseDirectiveThumbFunc
Kevin Enderby515d5092009-10-15 20:48:48 +00006461/// ::= .thumbfunc symbol_name
Jim Grosbach1355cf12011-07-26 17:10:22 +00006462bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
Rafael Espindola64695402011-05-16 16:17:21 +00006463 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
6464 bool isMachO = MAI.hasSubsectionsViaSymbols();
6465 StringRef Name;
Jim Grosbachde4d8392011-12-21 22:30:16 +00006466 bool needFuncName = true;
Rafael Espindola64695402011-05-16 16:17:21 +00006467
Jim Grosbachde4d8392011-12-21 22:30:16 +00006468 // Darwin asm has (optionally) function name after .thumb_func direction
Rafael Espindola64695402011-05-16 16:17:21 +00006469 // ELF doesn't
6470 if (isMachO) {
6471 const AsmToken &Tok = Parser.getTok();
Jim Grosbachde4d8392011-12-21 22:30:16 +00006472 if (Tok.isNot(AsmToken::EndOfStatement)) {
6473 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
6474 return Error(L, "unexpected token in .thumb_func directive");
6475 Name = Tok.getIdentifier();
6476 Parser.Lex(); // Consume the identifier token.
6477 needFuncName = false;
6478 }
Rafael Espindola64695402011-05-16 16:17:21 +00006479 }
6480
Jim Grosbachde4d8392011-12-21 22:30:16 +00006481 if (getLexer().isNot(AsmToken::EndOfStatement))
Kevin Enderby515d5092009-10-15 20:48:48 +00006482 return Error(L, "unexpected token in directive");
Jim Grosbachde4d8392011-12-21 22:30:16 +00006483
6484 // Eat the end of statement and any blank lines that follow.
6485 while (getLexer().is(AsmToken::EndOfStatement))
6486 Parser.Lex();
Kevin Enderby515d5092009-10-15 20:48:48 +00006487
Rafael Espindola64695402011-05-16 16:17:21 +00006488 // FIXME: assuming function name will be the line following .thumb_func
Jim Grosbachde4d8392011-12-21 22:30:16 +00006489 // We really should be checking the next symbol definition even if there's
6490 // stuff in between.
6491 if (needFuncName) {
Jim Grosbachd475f862011-11-10 20:48:53 +00006492 Name = Parser.getTok().getIdentifier();
Rafael Espindola64695402011-05-16 16:17:21 +00006493 }
6494
Jim Grosbach642fc9c2010-11-05 22:33:53 +00006495 // Mark symbol as a thumb symbol.
6496 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
6497 getParser().getStreamer().EmitThumbFunc(Func);
Kevin Enderby515d5092009-10-15 20:48:48 +00006498 return false;
6499}
6500
Jim Grosbach1355cf12011-07-26 17:10:22 +00006501/// parseDirectiveSyntax
Kevin Enderby515d5092009-10-15 20:48:48 +00006502/// ::= .syntax unified | divided
Jim Grosbach1355cf12011-07-26 17:10:22 +00006503bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
Sean Callanan18b83232010-01-19 21:44:56 +00006504 const AsmToken &Tok = Parser.getTok();
Kevin Enderby515d5092009-10-15 20:48:48 +00006505 if (Tok.isNot(AsmToken::Identifier))
6506 return Error(L, "unexpected token in .syntax directive");
Benjamin Kramer38e59892010-07-14 22:38:02 +00006507 StringRef Mode = Tok.getString();
Duncan Sands58c86912010-06-29 13:04:35 +00006508 if (Mode == "unified" || Mode == "UNIFIED")
Sean Callananb9a25b72010-01-19 20:27:46 +00006509 Parser.Lex();
Duncan Sands58c86912010-06-29 13:04:35 +00006510 else if (Mode == "divided" || Mode == "DIVIDED")
Kevin Enderby9e56fb12011-01-27 23:22:36 +00006511 return Error(L, "'.syntax divided' arm asssembly not supported");
Kevin Enderby515d5092009-10-15 20:48:48 +00006512 else
6513 return Error(L, "unrecognized syntax mode in .syntax directive");
6514
6515 if (getLexer().isNot(AsmToken::EndOfStatement))
Sean Callanan18b83232010-01-19 21:44:56 +00006516 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
Sean Callananb9a25b72010-01-19 20:27:46 +00006517 Parser.Lex();
Kevin Enderby515d5092009-10-15 20:48:48 +00006518
6519 // TODO tell the MC streamer the mode
6520 // getParser().getStreamer().Emit???();
6521 return false;
6522}
6523
Jim Grosbach1355cf12011-07-26 17:10:22 +00006524/// parseDirectiveCode
Kevin Enderby515d5092009-10-15 20:48:48 +00006525/// ::= .code 16 | 32
Jim Grosbach1355cf12011-07-26 17:10:22 +00006526bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
Sean Callanan18b83232010-01-19 21:44:56 +00006527 const AsmToken &Tok = Parser.getTok();
Kevin Enderby515d5092009-10-15 20:48:48 +00006528 if (Tok.isNot(AsmToken::Integer))
6529 return Error(L, "unexpected token in .code directive");
Sean Callanan18b83232010-01-19 21:44:56 +00006530 int64_t Val = Parser.getTok().getIntVal();
Duncan Sands58c86912010-06-29 13:04:35 +00006531 if (Val == 16)
Sean Callananb9a25b72010-01-19 20:27:46 +00006532 Parser.Lex();
Duncan Sands58c86912010-06-29 13:04:35 +00006533 else if (Val == 32)
Sean Callananb9a25b72010-01-19 20:27:46 +00006534 Parser.Lex();
Kevin Enderby515d5092009-10-15 20:48:48 +00006535 else
6536 return Error(L, "invalid operand to .code directive");
6537
6538 if (getLexer().isNot(AsmToken::EndOfStatement))
Sean Callanan18b83232010-01-19 21:44:56 +00006539 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
Sean Callananb9a25b72010-01-19 20:27:46 +00006540 Parser.Lex();
Kevin Enderby515d5092009-10-15 20:48:48 +00006541
Evan Cheng32869202011-07-08 22:36:29 +00006542 if (Val == 16) {
Jim Grosbach98447da2011-09-06 18:46:23 +00006543 if (!isThumb())
Evan Chengffc0e732011-07-09 05:47:46 +00006544 SwitchMode();
Jim Grosbach98447da2011-09-06 18:46:23 +00006545 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
Evan Cheng32869202011-07-08 22:36:29 +00006546 } else {
Jim Grosbach98447da2011-09-06 18:46:23 +00006547 if (isThumb())
Evan Chengffc0e732011-07-09 05:47:46 +00006548 SwitchMode();
Jim Grosbach98447da2011-09-06 18:46:23 +00006549 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
Evan Chengeb0caa12011-07-08 22:49:55 +00006550 }
Jim Grosbach2a301702010-11-05 22:40:53 +00006551
Kevin Enderby515d5092009-10-15 20:48:48 +00006552 return false;
6553}
6554
Jim Grosbacha39cda72011-12-14 02:16:11 +00006555/// parseDirectiveReq
6556/// ::= name .req registername
6557bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
6558 Parser.Lex(); // Eat the '.req' token.
6559 unsigned Reg;
6560 SMLoc SRegLoc, ERegLoc;
6561 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
6562 Parser.EatToEndOfStatement();
6563 return Error(SRegLoc, "register name expected");
6564 }
6565
6566 // Shouldn't be anything else.
6567 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
6568 Parser.EatToEndOfStatement();
6569 return Error(Parser.getTok().getLoc(),
6570 "unexpected input in .req directive.");
6571 }
6572
6573 Parser.Lex(); // Consume the EndOfStatement
6574
6575 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
6576 return Error(SRegLoc, "redefinition of '" + Name +
6577 "' does not match original.");
6578
6579 return false;
6580}
6581
6582/// parseDirectiveUneq
6583/// ::= .unreq registername
6584bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
6585 if (Parser.getTok().isNot(AsmToken::Identifier)) {
6586 Parser.EatToEndOfStatement();
6587 return Error(L, "unexpected input in .unreq directive.");
6588 }
6589 RegisterReqs.erase(Parser.getTok().getIdentifier());
6590 Parser.Lex(); // Eat the identifier.
6591 return false;
6592}
6593
Jason W Kimd7c9e082011-12-20 17:38:12 +00006594/// parseDirectiveArch
6595/// ::= .arch token
6596bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
6597 return true;
6598}
6599
6600/// parseDirectiveEabiAttr
6601/// ::= .eabi_attribute int, int
6602bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
6603 return true;
6604}
6605
Sean Callanan90b70972010-04-07 20:29:34 +00006606extern "C" void LLVMInitializeARMAsmLexer();
6607
Kevin Enderby9c41fa82009-10-30 22:55:57 +00006608/// Force static initialization.
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006609extern "C" void LLVMInitializeARMAsmParser() {
Evan Cheng94b95502011-07-26 00:24:13 +00006610 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
6611 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
Sean Callanan90b70972010-04-07 20:29:34 +00006612 LLVMInitializeARMAsmLexer();
Kevin Enderbyca9c42c2009-09-15 00:27:25 +00006613}
Daniel Dunbar3483aca2010-08-11 05:24:50 +00006614
Chris Lattner0692ee62010-09-06 19:11:01 +00006615#define GET_REGISTER_MATCHER
6616#define GET_MATCHER_IMPLEMENTATION
Daniel Dunbar3483aca2010-08-11 05:24:50 +00006617#include "ARMGenAsmMatcher.inc"