Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1 | //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 10 | // This file contains the PowerPC implementation of the MRegisterInfo class. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #define DEBUG_TYPE "reginfo" |
Chris Lattner | 2668959 | 2005-10-14 23:51:18 +0000 | [diff] [blame] | 15 | #include "PPC.h" |
Chris Lattner | 26bd0d4 | 2005-10-14 23:45:43 +0000 | [diff] [blame] | 16 | #include "PPCInstrBuilder.h" |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 17 | #include "PPCRegisterInfo.h" |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 18 | #include "PPCSubtarget.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 19 | #include "llvm/Constants.h" |
| 20 | #include "llvm/Type.h" |
| 21 | #include "llvm/CodeGen/ValueTypes.h" |
| 22 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineDebugInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/MachineFunction.h" |
| 25 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineLocation.h" |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 27 | #include "llvm/CodeGen/SelectionDAGNodes.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 28 | #include "llvm/Target/TargetFrameInfo.h" |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 29 | #include "llvm/Target/TargetInstrInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 30 | #include "llvm/Target/TargetMachine.h" |
| 31 | #include "llvm/Target/TargetOptions.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 32 | #include "llvm/Support/CommandLine.h" |
| 33 | #include "llvm/Support/Debug.h" |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 34 | #include "llvm/Support/MathExtras.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 35 | #include "llvm/ADT/STLExtras.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 36 | #include <cstdlib> |
| 37 | #include <iostream> |
| 38 | using namespace llvm; |
| 39 | |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 40 | /// getRegisterNumbering - Given the enum value for some register, e.g. |
| 41 | /// PPC::F14, return the number that it corresponds to (e.g. 14). |
| 42 | unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 43 | using namespace PPC; |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 44 | switch (RegEnum) { |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 45 | case R0 : case X0 : case F0 : case V0 : case CR0: return 0; |
| 46 | case R1 : case X1 : case F1 : case V1 : case CR1: return 1; |
| 47 | case R2 : case X2 : case F2 : case V2 : case CR2: return 2; |
| 48 | case R3 : case X3 : case F3 : case V3 : case CR3: return 3; |
| 49 | case R4 : case X4 : case F4 : case V4 : case CR4: return 4; |
| 50 | case R5 : case X5 : case F5 : case V5 : case CR5: return 5; |
| 51 | case R6 : case X6 : case F6 : case V6 : case CR6: return 6; |
| 52 | case R7 : case X7 : case F7 : case V7 : case CR7: return 7; |
| 53 | case R8 : case X8 : case F8 : case V8 : return 8; |
| 54 | case R9 : case X9 : case F9 : case V9 : return 9; |
| 55 | case R10: case X10: case F10: case V10: return 10; |
| 56 | case R11: case X11: case F11: case V11: return 11; |
| 57 | case R12: case X12: case F12: case V12: return 12; |
| 58 | case R13: case X13: case F13: case V13: return 13; |
| 59 | case R14: case X14: case F14: case V14: return 14; |
| 60 | case R15: case X15: case F15: case V15: return 15; |
| 61 | case R16: case X16: case F16: case V16: return 16; |
| 62 | case R17: case X17: case F17: case V17: return 17; |
| 63 | case R18: case X18: case F18: case V18: return 18; |
| 64 | case R19: case X19: case F19: case V19: return 19; |
| 65 | case R20: case X20: case F20: case V20: return 20; |
| 66 | case R21: case X21: case F21: case V21: return 21; |
| 67 | case R22: case X22: case F22: case V22: return 22; |
| 68 | case R23: case X23: case F23: case V23: return 23; |
| 69 | case R24: case X24: case F24: case V24: return 24; |
| 70 | case R25: case X25: case F25: case V25: return 25; |
| 71 | case R26: case X26: case F26: case V26: return 26; |
| 72 | case R27: case X27: case F27: case V27: return 27; |
| 73 | case R28: case X28: case F28: case V28: return 28; |
| 74 | case R29: case X29: case F29: case V29: return 29; |
| 75 | case R30: case X30: case F30: case V30: return 30; |
| 76 | case R31: case X31: case F31: case V31: return 31; |
| 77 | default: |
| 78 | std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; |
| 79 | abort(); |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 80 | } |
| 81 | } |
| 82 | |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 83 | PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) |
| 84 | : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), |
| 85 | Subtarget(ST) { |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 86 | ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 87 | ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; |
| 88 | ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; |
| 89 | ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; |
| 90 | ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; |
| 91 | ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; |
| 92 | ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 93 | ImmToIdxMap[PPC::ADDI] = PPC::ADD4; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 94 | } |
| 95 | |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 96 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 97 | PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| 98 | MachineBasicBlock::iterator MI, |
| 99 | unsigned SrcReg, int FrameIdx, |
| 100 | const TargetRegisterClass *RC) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 101 | if (SrcReg == PPC::LR) { |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 102 | // FIXME: this spills LR immediately to memory in one step. To do this, we |
| 103 | // use R11, which we know cannot be used in the prolog/epilog. This is a |
| 104 | // hack. |
Chris Lattner | 3f852b4 | 2005-08-18 23:24:50 +0000 | [diff] [blame] | 105 | BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 106 | addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 107 | } else if (RC == PPC::CRRCRegisterClass) { |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 108 | // FIXME: We use R0 here, because it isn't available for RA. |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 109 | // We need to store the CR in the low 4-bits of the saved value. First, |
| 110 | // issue a MFCR to save all of the CRBits. |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 111 | BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 112 | |
| 113 | // If the saved register wasn't CR0, shift the bits left so that they are in |
| 114 | // CR0's slot. |
| 115 | if (SrcReg != PPC::CR0) { |
| 116 | unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 117 | // rlwinm r0, r0, ShiftBits, 0, 31. |
| 118 | BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) |
| 119 | .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 120 | } |
| 121 | |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 122 | addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 123 | } else if (RC == PPC::GPRCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 124 | addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 125 | } else if (RC == PPC::G8RCRegisterClass) { |
| 126 | addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); |
| 127 | } else if (RC == PPC::F8RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 128 | addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 129 | } else if (RC == PPC::F4RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 130 | addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 131 | } else if (RC == PPC::VRRCRegisterClass) { |
| 132 | // We don't have indexed addressing for vector loads. Emit: |
| 133 | // R11 = ADDI FI# |
| 134 | // Dest = LVX R0, R11 |
| 135 | // |
| 136 | // FIXME: We use R0 here, because it isn't available for RA. |
Chris Lattner | e45aa73 | 2006-05-04 16:56:45 +0000 | [diff] [blame] | 137 | addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 138 | BuildMI(MBB, MI, PPC::STVX, 3) |
| 139 | .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 140 | } else { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 141 | assert(0 && "Unknown regclass!"); |
| 142 | abort(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 143 | } |
| 144 | } |
| 145 | |
| 146 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 147 | PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 148 | MachineBasicBlock::iterator MI, |
Chris Lattner | b48d2cf | 2005-09-30 01:31:52 +0000 | [diff] [blame] | 149 | unsigned DestReg, int FrameIdx, |
| 150 | const TargetRegisterClass *RC) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 151 | if (DestReg == PPC::LR) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 152 | addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 153 | BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 154 | } else if (RC == PPC::CRRCRegisterClass) { |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 155 | // FIXME: We use R0 here, because it isn't available for RA. |
| 156 | addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 157 | |
| 158 | // If the reloaded register isn't CR0, shift the bits right so that they are |
| 159 | // in the right CR's slot. |
| 160 | if (DestReg != PPC::CR0) { |
| 161 | unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; |
| 162 | // rlwinm r11, r11, 32-ShiftBits, 0, 31. |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 163 | BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) |
| 164 | .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 165 | } |
| 166 | |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 167 | BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 168 | } else if (RC == PPC::GPRCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 169 | addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 170 | } else if (RC == PPC::G8RCRegisterClass) { |
| 171 | addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); |
| 172 | } else if (RC == PPC::F8RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 173 | addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 174 | } else if (RC == PPC::F4RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 175 | addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 176 | } else if (RC == PPC::VRRCRegisterClass) { |
| 177 | // We don't have indexed addressing for vector loads. Emit: |
| 178 | // R11 = ADDI FI# |
| 179 | // Dest = LVX R0, R11 |
| 180 | // |
| 181 | // FIXME: We use R0 here, because it isn't available for RA. |
Chris Lattner | e45aa73 | 2006-05-04 16:56:45 +0000 | [diff] [blame] | 182 | addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 183 | BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 184 | } else { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 185 | assert(0 && "Unknown regclass!"); |
| 186 | abort(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 187 | } |
| 188 | } |
| 189 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 190 | void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 191 | MachineBasicBlock::iterator MI, |
| 192 | unsigned DestReg, unsigned SrcReg, |
| 193 | const TargetRegisterClass *RC) const { |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 194 | if (RC == PPC::GPRCRegisterClass) { |
Chris Lattner | b410dc9 | 2006-06-20 23:18:58 +0000 | [diff] [blame] | 195 | BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 196 | } else if (RC == PPC::G8RCRegisterClass) { |
| 197 | BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); |
| 198 | } else if (RC == PPC::F4RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 199 | BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 200 | } else if (RC == PPC::F8RCRegisterClass) { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 201 | BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 202 | } else if (RC == PPC::CRRCRegisterClass) { |
Nate Begeman | 7af0248 | 2005-04-12 07:04:16 +0000 | [diff] [blame] | 203 | BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); |
Chris Lattner | 335fd3c | 2006-03-16 20:03:58 +0000 | [diff] [blame] | 204 | } else if (RC == PPC::VRRCRegisterClass) { |
| 205 | BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); |
Nate Begeman | 7af0248 | 2005-04-12 07:04:16 +0000 | [diff] [blame] | 206 | } else { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 207 | std::cerr << "Attempt to copy register that is not GPR or FPR"; |
| 208 | abort(); |
| 209 | } |
| 210 | } |
| 211 | |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 212 | const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const { |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 213 | // 32-bit Darwin calling convention. |
| 214 | static const unsigned Darwin32_CalleeSaveRegs[] = { |
| 215 | PPC::R1 , PPC::R13, PPC::R14, PPC::R15, |
| 216 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 217 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 218 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 219 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 220 | |
| 221 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 222 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 223 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 224 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 225 | PPC::F30, PPC::F31, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 226 | |
| 227 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 228 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 229 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 230 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 231 | |
| 232 | PPC::LR, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 233 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 234 | // 64-bit Darwin calling convention. |
| 235 | static const unsigned Darwin64_CalleeSaveRegs[] = { |
| 236 | PPC::X1 , PPC::X13, PPC::X14, PPC::X15, |
| 237 | PPC::X16, PPC::X17, PPC::X18, PPC::X19, |
| 238 | PPC::X20, PPC::X21, PPC::X22, PPC::X23, |
| 239 | PPC::X24, PPC::X25, PPC::X26, PPC::X27, |
| 240 | PPC::X28, PPC::X29, PPC::X30, PPC::X31, |
| 241 | |
| 242 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 243 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 244 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 245 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 246 | PPC::F30, PPC::F31, |
| 247 | |
| 248 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 249 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 250 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 251 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 252 | |
| 253 | PPC::LR, 0 |
| 254 | }; |
| 255 | |
| 256 | return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs : |
| 257 | Darwin32_CalleeSaveRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | const TargetRegisterClass* const* |
| 261 | PPCRegisterInfo::getCalleeSaveRegClasses() const { |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 262 | // 32-bit Darwin calling convention. |
| 263 | static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = { |
| 264 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 265 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 266 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 267 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 268 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 269 | |
| 270 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 271 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 272 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 273 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 274 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 275 | |
| 276 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 277 | |
| 278 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 279 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 280 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 281 | |
| 282 | &PPC::GPRCRegClass, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 283 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 284 | |
| 285 | // 64-bit Darwin calling convention. |
| 286 | static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = { |
| 287 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 288 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 289 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 290 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 291 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 292 | |
| 293 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 294 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 295 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 296 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 297 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 298 | |
| 299 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 300 | |
| 301 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 302 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 303 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 304 | |
| 305 | &PPC::GPRCRegClass, 0 |
| 306 | }; |
| 307 | |
| 308 | return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses : |
| 309 | Darwin32_CalleeSaveRegClasses; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 310 | } |
| 311 | |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 312 | /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into |
| 313 | /// copy instructions, turning them into load/store instructions. |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 314 | MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, |
| 315 | unsigned OpNum, |
| 316 | int FrameIndex) const { |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 317 | // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because |
| 318 | // it takes more than one instruction to store it. |
| 319 | unsigned Opc = MI->getOpcode(); |
| 320 | |
Chris Lattner | b410dc9 | 2006-06-20 23:18:58 +0000 | [diff] [blame] | 321 | if ((Opc == PPC::OR && |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 322 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { |
| 323 | if (OpNum == 0) { // move -> store |
| 324 | unsigned InReg = MI->getOperand(1).getReg(); |
| 325 | return addFrameReference(BuildMI(PPC::STW, |
| 326 | 3).addReg(InReg), FrameIndex); |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 327 | } else { // move -> load |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 328 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 329 | return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); |
| 330 | } |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 331 | } else if ((Opc == PPC::OR8 && |
| 332 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { |
| 333 | if (OpNum == 0) { // move -> store |
| 334 | unsigned InReg = MI->getOperand(1).getReg(); |
| 335 | return addFrameReference(BuildMI(PPC::STD, |
| 336 | 3).addReg(InReg), FrameIndex); |
| 337 | } else { // move -> load |
| 338 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 339 | return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); |
| 340 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 341 | } else if (Opc == PPC::FMRD) { |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 342 | if (OpNum == 0) { // move -> store |
| 343 | unsigned InReg = MI->getOperand(1).getReg(); |
| 344 | return addFrameReference(BuildMI(PPC::STFD, |
| 345 | 3).addReg(InReg), FrameIndex); |
| 346 | } else { // move -> load |
| 347 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 348 | return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); |
| 349 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 350 | } else if (Opc == PPC::FMRS) { |
| 351 | if (OpNum == 0) { // move -> store |
| 352 | unsigned InReg = MI->getOperand(1).getReg(); |
| 353 | return addFrameReference(BuildMI(PPC::STFS, |
| 354 | 3).addReg(InReg), FrameIndex); |
| 355 | } else { // move -> load |
| 356 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 357 | return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); |
| 358 | } |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 359 | } |
| 360 | return 0; |
| 361 | } |
| 362 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 363 | //===----------------------------------------------------------------------===// |
| 364 | // Stack Frame Processing methods |
| 365 | //===----------------------------------------------------------------------===// |
| 366 | |
| 367 | // hasFP - Return true if the specified function should have a dedicated frame |
| 368 | // pointer register. This is true if the function has variable sized allocas or |
| 369 | // if frame pointer elimination is disabled. |
| 370 | // |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 371 | static bool hasFP(const MachineFunction &MF) { |
| 372 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 373 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 374 | |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 375 | // If frame pointers are forced, or if there are variable sized stack objects, |
| 376 | // use a frame pointer. |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 377 | // |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 378 | return NoFramePointerElim || MFI->hasVarSizedObjects(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 379 | } |
| 380 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 381 | void PPCRegisterInfo:: |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 382 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 383 | MachineBasicBlock::iterator I) const { |
| 384 | if (hasFP(MF)) { |
| 385 | // If we have a frame pointer, convert as follows: |
| 386 | // ADJCALLSTACKDOWN -> addi, r1, r1, -amount |
| 387 | // ADJCALLSTACKUP -> addi, r1, r1, amount |
| 388 | MachineInstr *Old = I; |
| 389 | unsigned Amount = Old->getOperand(0).getImmedValue(); |
| 390 | if (Amount != 0) { |
| 391 | // We need to keep the stack aligned properly. To do this, we round the |
| 392 | // amount of space needed for the outgoing arguments up to the next |
| 393 | // alignment boundary. |
| 394 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 395 | Amount = (Amount+Align-1)/Align*Align; |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 396 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 397 | // Replace the pseudo instruction with a new instruction... |
| 398 | if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 399 | BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 400 | } else { |
| 401 | assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 402 | BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 403 | } |
| 404 | } |
| 405 | } |
| 406 | MBB.erase(I); |
| 407 | } |
| 408 | |
| 409 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 410 | PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 411 | unsigned i = 0; |
| 412 | MachineInstr &MI = *II; |
| 413 | MachineBasicBlock &MBB = *MI.getParent(); |
| 414 | MachineFunction &MF = *MBB.getParent(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 415 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 416 | while (!MI.getOperand(i).isFrameIndex()) { |
| 417 | ++i; |
| 418 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 419 | } |
| 420 | |
| 421 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
| 422 | |
| 423 | // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 424 | MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 425 | |
| 426 | // Take into account whether it's an add or mem instruction |
| 427 | unsigned OffIdx = (i == 2) ? 1 : 2; |
| 428 | |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 429 | // Figure out if the offset in the instruction is shifted right two bits. This |
| 430 | // is true for instructions like "STD", which the machine implicitly adds two |
| 431 | // low zeros to. |
| 432 | bool isIXAddr = false; |
| 433 | switch (MI.getOpcode()) { |
| 434 | case PPC::LWA: |
| 435 | case PPC::LD: |
| 436 | case PPC::STD: |
| 437 | case PPC::STD_32: |
| 438 | isIXAddr = true; |
| 439 | break; |
| 440 | } |
| 441 | |
| 442 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 443 | // Now add the frame object offset to the offset from r1. |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 444 | int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); |
| 445 | |
| 446 | if (!isIXAddr) |
| 447 | Offset += MI.getOperand(OffIdx).getImmedValue(); |
| 448 | else |
| 449 | Offset += MI.getOperand(OffIdx).getImmedValue() << 2; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 450 | |
| 451 | // If we're not using a Frame Pointer that has been set to the value of the |
| 452 | // SP before having the stack size subtracted from it, then add the stack size |
| 453 | // to Offset to get the correct offset. |
| 454 | Offset += MF.getFrameInfo()->getStackSize(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 455 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 456 | if (Offset > 32767 || Offset < -32768) { |
| 457 | // Insert a set of r0 with the full offset value before the ld, st, or add |
| 458 | MachineBasicBlock *MBB = MI.getParent(); |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 459 | BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16); |
Chris Lattner | c6d48d3 | 2006-01-11 23:07:57 +0000 | [diff] [blame] | 460 | BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); |
| 461 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 462 | // convert into indexed form of the instruction |
| 463 | // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 |
| 464 | // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 |
Chris Lattner | 1463019 | 2005-09-09 20:51:08 +0000 | [diff] [blame] | 465 | assert(ImmToIdxMap.count(MI.getOpcode()) && |
| 466 | "No indexed form of load or store available!"); |
| 467 | unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 468 | MI.setOpcode(NewOpcode); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 469 | MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg()); |
| 470 | MI.getOperand(2).ChangeToRegister(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 471 | } else { |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 472 | if (isIXAddr) { |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 473 | assert((Offset & 3) == 0 && "Invalid frame offset!"); |
| 474 | Offset >>= 2; // The actual encoded value has the low two bits zero. |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 475 | } |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 476 | MI.getOperand(OffIdx).ChangeToImmediate(Offset); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 477 | } |
| 478 | } |
| 479 | |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 480 | /// VRRegNo - Map from a numbered VR register to its enum value. |
| 481 | /// |
| 482 | static const unsigned short VRRegNo[] = { |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 483 | PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , |
| 484 | PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 485 | PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 486 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 |
| 487 | }; |
| 488 | |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 489 | /// RemoveVRSaveCode - We have found that this function does not need any code |
| 490 | /// to manipulate the VRSAVE register, even though it uses vector registers. |
| 491 | /// This can happen when the only registers used are known to be live in or out |
| 492 | /// of the function. Remove all of the VRSAVE related code from the function. |
| 493 | static void RemoveVRSaveCode(MachineInstr *MI) { |
| 494 | MachineBasicBlock *Entry = MI->getParent(); |
| 495 | MachineFunction *MF = Entry->getParent(); |
| 496 | |
| 497 | // We know that the MTVRSAVE instruction immediately follows MI. Remove it. |
| 498 | MachineBasicBlock::iterator MBBI = MI; |
| 499 | ++MBBI; |
| 500 | assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); |
| 501 | MBBI->eraseFromParent(); |
| 502 | |
| 503 | bool RemovedAllMTVRSAVEs = true; |
| 504 | // See if we can find and remove the MTVRSAVE instruction from all of the |
| 505 | // epilog blocks. |
| 506 | const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); |
| 507 | for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { |
| 508 | // If last instruction is a return instruction, add an epilogue |
| 509 | if (!I->empty() && TII.isReturn(I->back().getOpcode())) { |
| 510 | bool FoundIt = false; |
| 511 | for (MBBI = I->end(); MBBI != I->begin(); ) { |
| 512 | --MBBI; |
| 513 | if (MBBI->getOpcode() == PPC::MTVRSAVE) { |
| 514 | MBBI->eraseFromParent(); // remove it. |
| 515 | FoundIt = true; |
| 516 | break; |
| 517 | } |
| 518 | } |
| 519 | RemovedAllMTVRSAVEs &= FoundIt; |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | // If we found and removed all MTVRSAVE instructions, remove the read of |
| 524 | // VRSAVE as well. |
| 525 | if (RemovedAllMTVRSAVEs) { |
| 526 | MBBI = MI; |
| 527 | assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); |
| 528 | --MBBI; |
| 529 | assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); |
| 530 | MBBI->eraseFromParent(); |
| 531 | } |
| 532 | |
| 533 | // Finally, nuke the UPDATE_VRSAVE. |
| 534 | MI->eraseFromParent(); |
| 535 | } |
| 536 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 537 | // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the |
| 538 | // instruction selector. Based on the vector registers that have been used, |
| 539 | // transform this into the appropriate ORI instruction. |
| 540 | static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { |
| 541 | unsigned UsedRegMask = 0; |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 542 | for (unsigned i = 0; i != 32; ++i) |
| 543 | if (UsedRegs[VRRegNo[i]]) |
| 544 | UsedRegMask |= 1 << (31-i); |
| 545 | |
Chris Lattner | 402504b | 2006-04-17 21:22:06 +0000 | [diff] [blame] | 546 | // Live in and live out values already must be in the mask, so don't bother |
| 547 | // marking them. |
| 548 | MachineFunction *MF = MI->getParent()->getParent(); |
| 549 | for (MachineFunction::livein_iterator I = |
| 550 | MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { |
| 551 | unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); |
| 552 | if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. |
| 553 | UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. |
| 554 | } |
| 555 | for (MachineFunction::liveout_iterator I = |
| 556 | MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { |
| 557 | unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); |
| 558 | if (VRRegNo[RegNo] == *I) // If this really is a vector reg. |
| 559 | UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. |
| 560 | } |
| 561 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 562 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 563 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 564 | // If no registers are used, turn this into a copy. |
| 565 | if (UsedRegMask == 0) { |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 566 | // Remove all VRSAVE code. |
| 567 | RemoveVRSaveCode(MI); |
| 568 | return; |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 569 | } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { |
| 570 | BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) |
| 571 | .addReg(SrcReg).addImm(UsedRegMask); |
| 572 | } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { |
| 573 | BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) |
| 574 | .addReg(SrcReg).addImm(UsedRegMask >> 16); |
| 575 | } else { |
| 576 | BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) |
| 577 | .addReg(SrcReg).addImm(UsedRegMask >> 16); |
| 578 | BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) |
| 579 | .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); |
| 580 | } |
| 581 | |
| 582 | // Remove the old UPDATE_VRSAVE instruction. |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 583 | MI->eraseFromParent(); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 584 | } |
| 585 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 586 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 587 | void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 588 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
| 589 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 590 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 591 | MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 592 | |
| 593 | // Do we have a frame pointer for this function? |
| 594 | bool HasFP = hasFP(MF); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 595 | |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 596 | // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, |
| 597 | // process it. |
Chris Lattner | 8aa777d | 2006-03-16 21:31:45 +0000 | [diff] [blame] | 598 | for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 599 | if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { |
| 600 | HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); |
| 601 | break; |
| 602 | } |
| 603 | } |
| 604 | |
| 605 | // Move MBBI back to the beginning of the function. |
| 606 | MBBI = MBB.begin(); |
| 607 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 608 | // Get the number of bytes to allocate from the FrameInfo |
| 609 | unsigned NumBytes = MFI->getStackSize(); |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 610 | |
| 611 | // Get the alignments provided by the target, and the maximum alignment |
| 612 | // (if any) of the fixed frame objects. |
| 613 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 614 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 615 | |
| 616 | // If we have calls, we cannot use the red zone to store callee save registers |
| 617 | // and we must set up a stack frame, so calculate the necessary size here. |
| 618 | if (MFI->hasCalls()) { |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 619 | // We reserve argument space for call sites in the function immediately on |
| 620 | // entry to the current function. This eliminates the need for add/sub |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 621 | // brackets around call sites. |
| 622 | NumBytes += MFI->getMaxCallFrameSize(); |
| 623 | } |
| 624 | |
Jeff Cohen | d29b6aa | 2005-07-30 18:33:25 +0000 | [diff] [blame] | 625 | // If we are a leaf function, and use up to 224 bytes of stack space, |
Nate Begeman | 54eed36 | 2005-07-27 06:06:29 +0000 | [diff] [blame] | 626 | // and don't have a frame pointer, then we do not need to adjust the stack |
| 627 | // pointer (we fit in the Red Zone). |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 628 | if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 629 | MaxAlign <= TargetAlign)) { |
Nate Begeman | 54eed36 | 2005-07-27 06:06:29 +0000 | [diff] [blame] | 630 | MFI->setStackSize(0); |
| 631 | return; |
| 632 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 633 | |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 634 | // Add the size of R1 to NumBytes size for the store of R1 to the bottom |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 635 | // of the stack and round the size to a multiple of the alignment. |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 636 | unsigned Align = std::max(TargetAlign, MaxAlign); |
Chris Lattner | 5802be1 | 2005-09-30 17:16:59 +0000 | [diff] [blame] | 637 | unsigned GPRSize = 4; |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 638 | unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 639 | NumBytes = (NumBytes+Size+Align-1)/Align*Align; |
| 640 | |
| 641 | // Update frame info to pretend that this is part of the stack... |
| 642 | MFI->setStackSize(NumBytes); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 643 | int NegNumbytes = -NumBytes; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 644 | |
Nate Begeman | 3dee175 | 2005-07-27 23:11:27 +0000 | [diff] [blame] | 645 | // Adjust stack pointer: r1 -= numbytes. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 646 | // If there is a preferred stack alignment, align R1 now |
| 647 | if (MaxAlign > TargetAlign) { |
| 648 | assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); |
Chris Lattner | 3e6a350 | 2006-05-10 06:38:32 +0000 | [diff] [blame] | 649 | assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!"); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 650 | BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) |
| 651 | .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); |
Nate Begeman | 2186298 | 2006-04-11 19:44:43 +0000 | [diff] [blame] | 652 | BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) |
Chris Lattner | 3e6a350 | 2006-05-10 06:38:32 +0000 | [diff] [blame] | 653 | .addImm(0-NumBytes); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 654 | BuildMI(MBB, MBBI, PPC::STWUX, 3) |
| 655 | .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); |
| 656 | } else if (NumBytes <= 32768) { |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 657 | BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes) |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 658 | .addReg(PPC::R1); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 659 | } else { |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 660 | BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 661 | BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) |
| 662 | .addImm(NegNumbytes & 0xFFFF); |
| 663 | BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) |
| 664 | .addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 665 | } |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 666 | |
Jim Laskey | 52fa244 | 2006-04-11 08:11:53 +0000 | [diff] [blame] | 667 | if (DebugInfo && DebugInfo->hasInfo()) { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 668 | std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves(); |
| 669 | unsigned LabelID = DebugInfo->NextLabelID(); |
| 670 | |
| 671 | // Show update of SP. |
| 672 | MachineLocation Dst(MachineLocation::VirtualFP); |
| 673 | MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); |
| 674 | Moves.push_back(new MachineMove(LabelID, Dst, Src)); |
| 675 | |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame^] | 676 | // Mark effective beginning of when frame pointer becomes valid. |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 677 | BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID); |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame^] | 678 | |
| 679 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 680 | } |
| 681 | |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 682 | // If there is a frame pointer, copy R1 (SP) into R31 (FP) |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 683 | if (HasFP) { |
Chris Lattner | c6d48d3 | 2006-01-11 23:07:57 +0000 | [diff] [blame] | 684 | BuildMI(MBB, MBBI, PPC::STW, 3) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 685 | .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1); |
Chris Lattner | b410dc9 | 2006-06-20 23:18:58 +0000 | [diff] [blame] | 686 | BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 687 | } |
| 688 | } |
| 689 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 690 | void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, |
| 691 | MachineBasicBlock &MBB) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 692 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Evan Cheng | 6da8d99 | 2006-01-09 18:28:21 +0000 | [diff] [blame] | 693 | assert(MBBI->getOpcode() == PPC::BLR && |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 694 | "Can only insert epilog into returning blocks"); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 695 | |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 696 | // Get alignment info so we know how to restore r1 |
| 697 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 698 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 699 | |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 700 | // Get the number of bytes allocated from the FrameInfo. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 701 | unsigned NumBytes = MFI->getStackSize(); |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 702 | unsigned GPRSize = 4; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 703 | |
| 704 | if (NumBytes != 0) { |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 705 | // If this function has a frame pointer, load the saved stack pointer from |
| 706 | // its stack slot. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 707 | if (hasFP(MF)) { |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 708 | BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 709 | .addImm(GPRSize).addReg(PPC::R31); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 710 | } |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 711 | |
| 712 | // The loaded (or persistent) stack pointer value is offseted by the 'stwu' |
| 713 | // on entry to the function. Add this offset back now. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 714 | if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 715 | BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 716 | .addReg(PPC::R1).addImm(NumBytes); |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 717 | } else { |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 718 | BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1); |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 719 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 720 | } |
| 721 | } |
| 722 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 723 | unsigned PPCRegisterInfo::getRARegister() const { |
| 724 | return PPC::LR; |
| 725 | } |
| 726 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 727 | unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 728 | return hasFP(MF) ? PPC::R31 : PPC::R1; |
| 729 | } |
| 730 | |
| 731 | void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) |
| 732 | const { |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame^] | 733 | // Initial state of the frame pointer is R1. |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 734 | MachineLocation Dst(MachineLocation::VirtualFP); |
| 735 | MachineLocation Src(PPC::R1, 0); |
| 736 | Moves.push_back(new MachineMove(0, Dst, Src)); |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 737 | } |
| 738 | |
Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 739 | #include "PPCGenRegisterInfo.inc" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 740 | |