Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1 | //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 10 | // This file contains the PowerPC implementation of the MRegisterInfo class. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #define DEBUG_TYPE "reginfo" |
Chris Lattner | 2668959 | 2005-10-14 23:51:18 +0000 | [diff] [blame] | 15 | #include "PPC.h" |
Chris Lattner | 26bd0d4 | 2005-10-14 23:45:43 +0000 | [diff] [blame] | 16 | #include "PPCInstrBuilder.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 17 | #include "PPCMachineFunctionInfo.h" |
Chris Lattner | 16e71f2 | 2005-10-14 23:59:06 +0000 | [diff] [blame] | 18 | #include "PPCRegisterInfo.h" |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 19 | #include "PPCFrameInfo.h" |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 20 | #include "PPCSubtarget.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 21 | #include "llvm/Constants.h" |
| 22 | #include "llvm/Type.h" |
| 23 | #include "llvm/CodeGen/ValueTypes.h" |
| 24 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineModuleInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineFunction.h" |
| 27 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 28 | #include "llvm/CodeGen/MachineLocation.h" |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/SelectionDAGNodes.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 30 | #include "llvm/Target/TargetFrameInfo.h" |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 31 | #include "llvm/Target/TargetInstrInfo.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 32 | #include "llvm/Target/TargetMachine.h" |
| 33 | #include "llvm/Target/TargetOptions.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 34 | #include "llvm/Support/CommandLine.h" |
| 35 | #include "llvm/Support/Debug.h" |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 36 | #include "llvm/Support/MathExtras.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 37 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 38 | #include "llvm/ADT/STLExtras.h" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 39 | #include <cstdlib> |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 40 | using namespace llvm; |
| 41 | |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 42 | /// getRegisterNumbering - Given the enum value for some register, e.g. |
| 43 | /// PPC::F14, return the number that it corresponds to (e.g. 14). |
| 44 | unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 45 | using namespace PPC; |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 46 | switch (RegEnum) { |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 47 | case R0 : case X0 : case F0 : case V0 : case CR0: return 0; |
| 48 | case R1 : case X1 : case F1 : case V1 : case CR1: return 1; |
| 49 | case R2 : case X2 : case F2 : case V2 : case CR2: return 2; |
| 50 | case R3 : case X3 : case F3 : case V3 : case CR3: return 3; |
| 51 | case R4 : case X4 : case F4 : case V4 : case CR4: return 4; |
| 52 | case R5 : case X5 : case F5 : case V5 : case CR5: return 5; |
| 53 | case R6 : case X6 : case F6 : case V6 : case CR6: return 6; |
| 54 | case R7 : case X7 : case F7 : case V7 : case CR7: return 7; |
| 55 | case R8 : case X8 : case F8 : case V8 : return 8; |
| 56 | case R9 : case X9 : case F9 : case V9 : return 9; |
| 57 | case R10: case X10: case F10: case V10: return 10; |
| 58 | case R11: case X11: case F11: case V11: return 11; |
| 59 | case R12: case X12: case F12: case V12: return 12; |
| 60 | case R13: case X13: case F13: case V13: return 13; |
| 61 | case R14: case X14: case F14: case V14: return 14; |
| 62 | case R15: case X15: case F15: case V15: return 15; |
| 63 | case R16: case X16: case F16: case V16: return 16; |
| 64 | case R17: case X17: case F17: case V17: return 17; |
| 65 | case R18: case X18: case F18: case V18: return 18; |
| 66 | case R19: case X19: case F19: case V19: return 19; |
| 67 | case R20: case X20: case F20: case V20: return 20; |
| 68 | case R21: case X21: case F21: case V21: return 21; |
| 69 | case R22: case X22: case F22: case V22: return 22; |
| 70 | case R23: case X23: case F23: case V23: return 23; |
| 71 | case R24: case X24: case F24: case V24: return 24; |
| 72 | case R25: case X25: case F25: case V25: return 25; |
| 73 | case R26: case X26: case F26: case V26: return 26; |
| 74 | case R27: case X27: case F27: case V27: return 27; |
| 75 | case R28: case X28: case F28: case V28: return 28; |
| 76 | case R29: case X29: case F29: case V29: return 29; |
| 77 | case R30: case X30: case F30: case V30: return 30; |
| 78 | case R31: case X31: case F31: case V31: return 31; |
| 79 | default: |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 80 | cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; |
Chris Lattner | be6a039 | 2006-07-11 20:53:55 +0000 | [diff] [blame] | 81 | abort(); |
Chris Lattner | 369503f | 2006-04-17 21:07:20 +0000 | [diff] [blame] | 82 | } |
| 83 | } |
| 84 | |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 85 | PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, |
| 86 | const TargetInstrInfo &tii) |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 87 | : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 88 | Subtarget(ST), TII(tii) { |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 89 | ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 90 | ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; |
| 91 | ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; |
| 92 | ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; |
| 93 | ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; |
| 94 | ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; |
| 95 | ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 96 | ImmToIdxMap[PPC::ADDI] = PPC::ADD4; |
Bill Wendling | 82d2514 | 2007-09-07 22:01:02 +0000 | [diff] [blame] | 97 | |
| 98 | // 64-bit |
| 99 | ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; |
| 100 | ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; |
| 101 | ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; |
| 102 | ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; |
| 103 | ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 104 | } |
| 105 | |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 106 | static void StoreRegToStackSlot(const TargetInstrInfo &TII, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 107 | unsigned SrcReg, bool isKill, int FrameIdx, |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 108 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 109 | SmallVectorImpl<MachineInstr*> &NewMIs) { |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 110 | if (RC == PPC::GPRCRegisterClass) { |
| 111 | if (SrcReg != PPC::LR) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 112 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 113 | .addReg(SrcReg, false, false, isKill), FrameIdx)); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 114 | } else { |
| 115 | // FIXME: this spills LR immediately to memory in one step. To do this, |
| 116 | // we use R11, which we know cannot be used in the prolog/epilog. This is |
| 117 | // a hack. |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 118 | NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11)); |
| 119 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 120 | .addReg(PPC::R11, false, false, isKill), FrameIdx)); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 121 | } |
| 122 | } else if (RC == PPC::G8RCRegisterClass) { |
| 123 | if (SrcReg != PPC::LR8) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 124 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 125 | .addReg(SrcReg, false, false, isKill), FrameIdx)); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 126 | } else { |
| 127 | // FIXME: this spills LR immediately to memory in one step. To do this, |
| 128 | // we use R11, which we know cannot be used in the prolog/epilog. This is |
| 129 | // a hack. |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 130 | NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11)); |
| 131 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 132 | .addReg(PPC::X11, false, false, isKill), FrameIdx)); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 133 | } |
| 134 | } else if (RC == PPC::F8RCRegisterClass) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 135 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 136 | .addReg(SrcReg, false, false, isKill), FrameIdx)); |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 137 | } else if (RC == PPC::F4RCRegisterClass) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 138 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 139 | .addReg(SrcReg, false, false, isKill), FrameIdx)); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 140 | } else if (RC == PPC::CRRCRegisterClass) { |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 141 | // FIXME: We use R0 here, because it isn't available for RA. |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 142 | // We need to store the CR in the low 4-bits of the saved value. First, |
| 143 | // issue a MFCR to save all of the CRBits. |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 144 | NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 145 | |
| 146 | // If the saved register wasn't CR0, shift the bits left so that they are in |
| 147 | // CR0's slot. |
| 148 | if (SrcReg != PPC::CR0) { |
| 149 | unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; |
Chris Lattner | e67304f | 2006-06-12 23:59:16 +0000 | [diff] [blame] | 150 | // rlwinm r0, r0, ShiftBits, 0, 31. |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 151 | NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) |
| 152 | .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 153 | } |
| 154 | |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 155 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 156 | .addReg(PPC::R0, false, false, isKill), FrameIdx)); |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 157 | } else if (RC == PPC::VRRCRegisterClass) { |
| 158 | // We don't have indexed addressing for vector loads. Emit: |
Evan Cheng | fdd9f00 | 2007-09-14 01:57:02 +0000 | [diff] [blame] | 159 | // R0 = ADDI FI# |
| 160 | // STVX VAL, 0, R0 |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 161 | // |
| 162 | // FIXME: We use R0 here, because it isn't available for RA. |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 163 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0), |
| 164 | FrameIdx, 0, 0)); |
| 165 | NewMIs.push_back(BuildMI(TII.get(PPC::STVX)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 166 | .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 167 | } else { |
| 168 | assert(0 && "Unknown regclass!"); |
| 169 | abort(); |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | void |
| 174 | PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| 175 | MachineBasicBlock::iterator MI, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 176 | unsigned SrcReg, bool isKill, int FrameIdx, |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 177 | const TargetRegisterClass *RC) const { |
| 178 | SmallVector<MachineInstr*, 4> NewMIs; |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 179 | StoreRegToStackSlot(TII, SrcReg, isKill, FrameIdx, RC, NewMIs); |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 180 | for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) |
| 181 | MBB.insert(MI, NewMIs[i]); |
| 182 | } |
| 183 | |
| 184 | void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 185 | bool isKill, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 186 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 187 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 188 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 189 | if (Addr[0].isFrameIndex()) { |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 190 | StoreRegToStackSlot(TII, SrcReg, isKill, Addr[0].getFrameIndex(), RC, |
| 191 | NewMIs); |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 192 | return; |
| 193 | } |
| 194 | |
| 195 | unsigned Opc = 0; |
| 196 | if (RC == PPC::GPRCRegisterClass) { |
| 197 | Opc = PPC::STW; |
| 198 | } else if (RC == PPC::G8RCRegisterClass) { |
| 199 | Opc = PPC::STD; |
| 200 | } else if (RC == PPC::F8RCRegisterClass) { |
| 201 | Opc = PPC::STFD; |
| 202 | } else if (RC == PPC::F4RCRegisterClass) { |
| 203 | Opc = PPC::STFS; |
| 204 | } else if (RC == PPC::VRRCRegisterClass) { |
| 205 | Opc = PPC::STVX; |
| 206 | } else { |
| 207 | assert(0 && "Unknown regclass!"); |
| 208 | abort(); |
| 209 | } |
| 210 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 211 | .addReg(SrcReg, false, false, isKill); |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 212 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) { |
| 213 | MachineOperand &MO = Addr[i]; |
| 214 | if (MO.isRegister()) |
| 215 | MIB.addReg(MO.getReg()); |
| 216 | else if (MO.isImmediate()) |
| 217 | MIB.addImm(MO.getImmedValue()); |
| 218 | else |
| 219 | MIB.addFrameIndex(MO.getFrameIndex()); |
| 220 | } |
| 221 | NewMIs.push_back(MIB); |
| 222 | return; |
| 223 | } |
| 224 | |
| 225 | static void LoadRegFromStackSlot(const TargetInstrInfo &TII, |
| 226 | unsigned DestReg, int FrameIdx, |
| 227 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 228 | SmallVectorImpl<MachineInstr*> &NewMIs) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 229 | if (RC == PPC::GPRCRegisterClass) { |
| 230 | if (DestReg != PPC::LR) { |
| 231 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg), |
| 232 | FrameIdx)); |
| 233 | } else { |
| 234 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11), |
| 235 | FrameIdx)); |
| 236 | NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11)); |
| 237 | } |
| 238 | } else if (RC == PPC::G8RCRegisterClass) { |
| 239 | if (DestReg != PPC::LR8) { |
| 240 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg), |
| 241 | FrameIdx)); |
| 242 | } else { |
| 243 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11), |
| 244 | FrameIdx)); |
| 245 | NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11)); |
| 246 | } |
| 247 | } else if (RC == PPC::F8RCRegisterClass) { |
| 248 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg), |
| 249 | FrameIdx)); |
| 250 | } else if (RC == PPC::F4RCRegisterClass) { |
| 251 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg), |
| 252 | FrameIdx)); |
| 253 | } else if (RC == PPC::CRRCRegisterClass) { |
| 254 | // FIXME: We use R0 here, because it isn't available for RA. |
| 255 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0), |
| 256 | FrameIdx)); |
| 257 | |
| 258 | // If the reloaded register isn't CR0, shift the bits right so that they are |
| 259 | // in the right CR's slot. |
| 260 | if (DestReg != PPC::CR0) { |
| 261 | unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; |
| 262 | // rlwinm r11, r11, 32-ShiftBits, 0, 31. |
| 263 | NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) |
| 264 | .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31)); |
| 265 | } |
| 266 | |
| 267 | NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0)); |
| 268 | } else if (RC == PPC::VRRCRegisterClass) { |
| 269 | // We don't have indexed addressing for vector loads. Emit: |
| 270 | // R0 = ADDI FI# |
| 271 | // Dest = LVX 0, R0 |
| 272 | // |
| 273 | // FIXME: We use R0 here, because it isn't available for RA. |
| 274 | NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0), |
| 275 | FrameIdx, 0, 0)); |
| 276 | NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0) |
| 277 | .addReg(PPC::R0)); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 278 | } else { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 279 | assert(0 && "Unknown regclass!"); |
| 280 | abort(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 281 | } |
| 282 | } |
| 283 | |
| 284 | void |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 285 | PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 286 | MachineBasicBlock::iterator MI, |
| 287 | unsigned DestReg, int FrameIdx, |
| 288 | const TargetRegisterClass *RC) const { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 289 | SmallVector<MachineInstr*, 4> NewMIs; |
| 290 | LoadRegFromStackSlot(TII, DestReg, FrameIdx, RC, NewMIs); |
| 291 | for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) |
| 292 | MBB.insert(MI, NewMIs[i]); |
| 293 | } |
| 294 | |
| 295 | void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 296 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 297 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 298 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 299 | if (Addr[0].isFrameIndex()) { |
| 300 | LoadRegFromStackSlot(TII, DestReg, Addr[0].getFrameIndex(), RC, NewMIs); |
| 301 | return; |
| 302 | } |
| 303 | |
| 304 | unsigned Opc = 0; |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 305 | if (RC == PPC::GPRCRegisterClass) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 306 | assert(DestReg != PPC::LR && "Can't handle this yet!"); |
| 307 | Opc = PPC::LWZ; |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 308 | } else if (RC == PPC::G8RCRegisterClass) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 309 | assert(DestReg != PPC::LR8 && "Can't handle this yet!"); |
| 310 | Opc = PPC::LD; |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 311 | } else if (RC == PPC::F8RCRegisterClass) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 312 | Opc = PPC::LFD; |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 313 | } else if (RC == PPC::F4RCRegisterClass) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 314 | Opc = PPC::LFS; |
Chris Lattner | 9c09c9e | 2006-03-16 22:24:02 +0000 | [diff] [blame] | 315 | } else if (RC == PPC::VRRCRegisterClass) { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 316 | Opc = PPC::LVX; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 317 | } else { |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 318 | assert(0 && "Unknown regclass!"); |
| 319 | abort(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 320 | } |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 321 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); |
| 322 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) { |
| 323 | MachineOperand &MO = Addr[i]; |
| 324 | if (MO.isRegister()) |
| 325 | MIB.addReg(MO.getReg()); |
| 326 | else if (MO.isImmediate()) |
| 327 | MIB.addImm(MO.getImmedValue()); |
| 328 | else |
| 329 | MIB.addFrameIndex(MO.getFrameIndex()); |
| 330 | } |
| 331 | NewMIs.push_back(MIB); |
| 332 | return; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 333 | } |
| 334 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 335 | void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 336 | MachineBasicBlock::iterator MI, |
| 337 | unsigned DestReg, unsigned SrcReg, |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 338 | const TargetRegisterClass *DestRC, |
| 339 | const TargetRegisterClass *SrcRC) const { |
| 340 | if (DestRC != SrcRC) { |
| 341 | cerr << "Not yet supported!"; |
| 342 | abort(); |
| 343 | } |
| 344 | |
| 345 | if (DestRC == PPC::GPRCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 346 | BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 347 | } else if (DestRC == PPC::G8RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 348 | BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 349 | } else if (DestRC == PPC::F4RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 350 | BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 351 | } else if (DestRC == PPC::F8RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 352 | BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 353 | } else if (DestRC == PPC::CRRCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 354 | BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 355 | } else if (DestRC == PPC::VRRCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 356 | BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); |
Nate Begeman | 7af0248 | 2005-04-12 07:04:16 +0000 | [diff] [blame] | 357 | } else { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 358 | cerr << "Attempt to copy register that is not GPR or FPR"; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 359 | abort(); |
| 360 | } |
| 361 | } |
| 362 | |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 363 | void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, |
| 364 | MachineBasicBlock::iterator I, |
| 365 | unsigned DestReg, |
| 366 | const MachineInstr *Orig) const { |
| 367 | MachineInstr *MI = Orig->clone(); |
| 368 | MI->getOperand(0).setReg(DestReg); |
| 369 | MBB.insert(I, MI); |
| 370 | } |
| 371 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 372 | const unsigned* |
| 373 | PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 374 | // 32-bit Darwin calling convention. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 375 | static const unsigned Macho32_CalleeSavedRegs[] = { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 376 | PPC::R13, PPC::R14, PPC::R15, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 377 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 378 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 379 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 380 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 381 | |
| 382 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 383 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 384 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 385 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 386 | PPC::F30, PPC::F31, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 387 | |
| 388 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 389 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 390 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 391 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 392 | |
| 393 | PPC::LR, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 394 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 395 | |
| 396 | static const unsigned ELF32_CalleeSavedRegs[] = { |
| 397 | PPC::R13, PPC::R14, PPC::R15, |
| 398 | PPC::R16, PPC::R17, PPC::R18, PPC::R19, |
| 399 | PPC::R20, PPC::R21, PPC::R22, PPC::R23, |
| 400 | PPC::R24, PPC::R25, PPC::R26, PPC::R27, |
| 401 | PPC::R28, PPC::R29, PPC::R30, PPC::R31, |
| 402 | |
Nicolas Geoffray | ef3c030 | 2007-04-03 10:27:07 +0000 | [diff] [blame] | 403 | PPC::F9, |
| 404 | PPC::F10, PPC::F11, PPC::F12, PPC::F13, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 405 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 406 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 407 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 408 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 409 | PPC::F30, PPC::F31, |
| 410 | |
| 411 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 412 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 413 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 414 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 415 | |
| 416 | PPC::LR, 0 |
| 417 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 418 | // 64-bit Darwin calling convention. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 419 | static const unsigned Macho64_CalleeSavedRegs[] = { |
Chris Lattner | bdc571b | 2006-11-20 19:33:51 +0000 | [diff] [blame] | 420 | PPC::X14, PPC::X15, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 421 | PPC::X16, PPC::X17, PPC::X18, PPC::X19, |
| 422 | PPC::X20, PPC::X21, PPC::X22, PPC::X23, |
| 423 | PPC::X24, PPC::X25, PPC::X26, PPC::X27, |
| 424 | PPC::X28, PPC::X29, PPC::X30, PPC::X31, |
| 425 | |
| 426 | PPC::F14, PPC::F15, PPC::F16, PPC::F17, |
| 427 | PPC::F18, PPC::F19, PPC::F20, PPC::F21, |
| 428 | PPC::F22, PPC::F23, PPC::F24, PPC::F25, |
| 429 | PPC::F26, PPC::F27, PPC::F28, PPC::F29, |
| 430 | PPC::F30, PPC::F31, |
| 431 | |
| 432 | PPC::CR2, PPC::CR3, PPC::CR4, |
| 433 | PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 434 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, |
| 435 | PPC::V28, PPC::V29, PPC::V30, PPC::V31, |
| 436 | |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 437 | PPC::LR8, 0 |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 438 | }; |
| 439 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 440 | if (Subtarget.isMachoABI()) |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 441 | return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : |
| 442 | Macho32_CalleeSavedRegs; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 443 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 444 | // ELF 32. |
| 445 | return ELF32_CalleeSavedRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | const TargetRegisterClass* const* |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 449 | PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 450 | // 32-bit Macho calling convention. |
| 451 | static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 452 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 453 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 454 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 455 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 456 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 457 | |
| 458 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 459 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 460 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 461 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 462 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 463 | |
| 464 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 465 | |
| 466 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 467 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 468 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 469 | |
| 470 | &PPC::GPRCRegClass, 0 |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 471 | }; |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 472 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 473 | static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { |
| 474 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 475 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 476 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 477 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 478 | &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, |
| 479 | |
Nicolas Geoffray | cfcd8da | 2007-04-03 10:57:49 +0000 | [diff] [blame] | 480 | &PPC::F8RCRegClass, |
| 481 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 482 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 483 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 484 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 485 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 486 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 487 | |
| 488 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 489 | |
| 490 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 491 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 492 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 493 | |
| 494 | &PPC::GPRCRegClass, 0 |
| 495 | }; |
| 496 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 497 | // 64-bit Macho calling convention. |
| 498 | static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { |
Chris Lattner | bdc571b | 2006-11-20 19:33:51 +0000 | [diff] [blame] | 499 | &PPC::G8RCRegClass,&PPC::G8RCRegClass, |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 500 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 501 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 502 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 503 | &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, |
| 504 | |
| 505 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 506 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 507 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 508 | &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 509 | &PPC::F8RCRegClass,&PPC::F8RCRegClass, |
| 510 | |
| 511 | &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, |
| 512 | |
| 513 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 514 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 515 | &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, |
| 516 | |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 517 | &PPC::G8RCRegClass, 0 |
Chris Lattner | 804e067 | 2006-07-11 00:48:23 +0000 | [diff] [blame] | 518 | }; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 519 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 520 | if (Subtarget.isMachoABI()) |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 521 | return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : |
| 522 | Macho32_CalleeSavedRegClasses; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 523 | |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 524 | // ELF 32. |
| 525 | return ELF32_CalleeSavedRegClasses; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 526 | } |
| 527 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 528 | // needsFP - Return true if the specified function should have a dedicated frame |
| 529 | // pointer register. This is true if the function has variable sized allocas or |
| 530 | // if frame pointer elimination is disabled. |
| 531 | // |
| 532 | static bool needsFP(const MachineFunction &MF) { |
| 533 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 534 | return NoFramePointerElim || MFI->hasVarSizedObjects(); |
| 535 | } |
| 536 | |
| 537 | BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 538 | BitVector Reserved(getNumRegs()); |
| 539 | Reserved.set(PPC::R0); |
| 540 | Reserved.set(PPC::R1); |
| 541 | Reserved.set(PPC::LR); |
| 542 | // In Linux, r2 is reserved for the OS. |
| 543 | if (!Subtarget.isDarwin()) |
| 544 | Reserved.set(PPC::R2); |
| 545 | // On PPC64, r13 is the thread pointer. Never allocate this register. |
| 546 | // Note that this is overconservative, as it also prevents allocation of |
| 547 | // R31 when the FP is not needed. |
| 548 | if (Subtarget.isPPC64()) { |
| 549 | Reserved.set(PPC::R13); |
| 550 | Reserved.set(PPC::R31); |
| 551 | } |
| 552 | if (needsFP(MF)) |
| 553 | Reserved.set(PPC::R31); |
| 554 | return Reserved; |
| 555 | } |
| 556 | |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 557 | /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into |
| 558 | /// copy instructions, turning them into load/store instructions. |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 559 | MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 560 | SmallVectorImpl<unsigned> &Ops, |
| 561 | int FrameIndex) const { |
| 562 | if (Ops.size() != 1) return NULL; |
| 563 | |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 564 | // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because |
| 565 | // it takes more than one instruction to store it. |
| 566 | unsigned Opc = MI->getOpcode(); |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 567 | unsigned OpNum = Ops[0]; |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 568 | |
| 569 | MachineInstr *NewMI = NULL; |
Chris Lattner | b410dc9 | 2006-06-20 23:18:58 +0000 | [diff] [blame] | 570 | if ((Opc == PPC::OR && |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 571 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { |
| 572 | if (OpNum == 0) { // move -> store |
| 573 | unsigned InReg = MI->getOperand(1).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 574 | NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), |
| 575 | FrameIndex); |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 576 | } else { // move -> load |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 577 | unsigned OutReg = MI->getOperand(0).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 578 | NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), |
| 579 | FrameIndex); |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 580 | } |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 581 | } else if ((Opc == PPC::OR8 && |
| 582 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { |
| 583 | if (OpNum == 0) { // move -> store |
| 584 | unsigned InReg = MI->getOperand(1).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 585 | NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), |
| 586 | FrameIndex); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 587 | } else { // move -> load |
| 588 | unsigned OutReg = MI->getOperand(0).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 589 | NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); |
Nate Begeman | 1d9d742 | 2005-10-18 00:28:58 +0000 | [diff] [blame] | 590 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 591 | } else if (Opc == PPC::FMRD) { |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 592 | if (OpNum == 0) { // move -> store |
| 593 | unsigned InReg = MI->getOperand(1).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 594 | NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), |
| 595 | FrameIndex); |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 596 | } else { // move -> load |
| 597 | unsigned OutReg = MI->getOperand(0).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 598 | NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); |
Chris Lattner | c9fe750 | 2005-09-09 21:59:44 +0000 | [diff] [blame] | 599 | } |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 600 | } else if (Opc == PPC::FMRS) { |
| 601 | if (OpNum == 0) { // move -> store |
| 602 | unsigned InReg = MI->getOperand(1).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 603 | NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), |
| 604 | FrameIndex); |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 605 | } else { // move -> load |
| 606 | unsigned OutReg = MI->getOperand(0).getReg(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 607 | NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); |
Chris Lattner | 919c032 | 2005-10-01 01:35:02 +0000 | [diff] [blame] | 608 | } |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 609 | } |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 610 | |
| 611 | if (NewMI) |
| 612 | NewMI->copyKillDeadInfo(MI); |
| 613 | return NewMI; |
Chris Lattner | f38df04 | 2005-09-09 21:46:49 +0000 | [diff] [blame] | 614 | } |
| 615 | |
Evan Cheng | 8c24e74 | 2007-12-05 18:41:29 +0000 | [diff] [blame] | 616 | bool PPCRegisterInfo::canFoldMemoryOperand(MachineInstr *MI, |
| 617 | SmallVectorImpl<unsigned> &Ops) const { |
Evan Cheng | 5a75961 | 2007-12-08 01:00:21 +0000 | [diff] [blame] | 618 | if (Ops.size() != 1) return false; |
Evan Cheng | 8c24e74 | 2007-12-05 18:41:29 +0000 | [diff] [blame] | 619 | |
| 620 | // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because |
| 621 | // it takes more than one instruction to store it. |
| 622 | unsigned Opc = MI->getOpcode(); |
| 623 | |
| 624 | if ((Opc == PPC::OR && |
| 625 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) |
| 626 | return true; |
| 627 | else if ((Opc == PPC::OR8 && |
| 628 | MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) |
| 629 | return true; |
| 630 | else if (Opc == PPC::FMRD || Opc == PPC::FMRS) |
| 631 | return true; |
| 632 | |
| 633 | return false; |
| 634 | } |
| 635 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 636 | //===----------------------------------------------------------------------===// |
| 637 | // Stack Frame Processing methods |
| 638 | //===----------------------------------------------------------------------===// |
| 639 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 640 | // hasFP - Return true if the specified function actually has a dedicated frame |
| 641 | // pointer register. This is true if the function needs a frame pointer and has |
| 642 | // a non-zero stack size. |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 643 | bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 644 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 645 | return MFI->getStackSize() && needsFP(MF); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 646 | } |
| 647 | |
Chris Lattner | 73944fb | 2007-12-08 06:39:11 +0000 | [diff] [blame] | 648 | /// MustSaveLR - Return true if this function requires that we save the LR |
Chris Lattner | 3fc027d | 2007-12-08 06:59:59 +0000 | [diff] [blame] | 649 | /// register onto the stack in the prolog and restore it in the epilog of the |
| 650 | /// function. |
Chris Lattner | 73944fb | 2007-12-08 06:39:11 +0000 | [diff] [blame] | 651 | static bool MustSaveLR(const MachineFunction &MF) { |
Chris Lattner | 3fc027d | 2007-12-08 06:59:59 +0000 | [diff] [blame] | 652 | const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); |
| 653 | |
| 654 | // We need an save/restore of LR if there is any use/def of LR explicitly, or |
| 655 | // if there is some use of the LR stack slot (e.g. for builtin_return_address. |
| 656 | return MFI->usesLR() || MFI->isLRStoreRequired() || |
Chris Lattner | 73944fb | 2007-12-08 06:39:11 +0000 | [diff] [blame] | 657 | // FIXME: Anything that has a call should clobber the LR register, |
| 658 | // isn't this redundant?? |
| 659 | MF.getFrameInfo()->hasCalls(); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 660 | } |
| 661 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 662 | void PPCRegisterInfo:: |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 663 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 664 | MachineBasicBlock::iterator I) const { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 665 | // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 666 | MBB.erase(I); |
| 667 | } |
| 668 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 669 | /// LowerDynamicAlloc - Generate the code for allocating an object in the |
| 670 | /// current frame. The sequence of code with be in the general form |
| 671 | /// |
| 672 | /// addi R0, SP, #frameSize ; get the address of the previous frame |
| 673 | /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size |
| 674 | /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation |
| 675 | /// |
| 676 | void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { |
| 677 | // Get the instruction. |
| 678 | MachineInstr &MI = *II; |
| 679 | // Get the instruction's basic block. |
| 680 | MachineBasicBlock &MBB = *MI.getParent(); |
| 681 | // Get the basic block's function. |
| 682 | MachineFunction &MF = *MBB.getParent(); |
| 683 | // Get the frame info. |
| 684 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 685 | // Determine whether 64-bit pointers are used. |
| 686 | bool LP64 = Subtarget.isPPC64(); |
| 687 | |
Evan Cheng | fab0439 | 2007-01-25 22:48:25 +0000 | [diff] [blame] | 688 | // Get the maximum call stack size. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 689 | unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 690 | // Get the total frame size. |
| 691 | unsigned FrameSize = MFI->getStackSize(); |
| 692 | |
| 693 | // Get stack alignments. |
| 694 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 695 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Jim Laskey | d6fa8c1 | 2006-11-17 18:49:39 +0000 | [diff] [blame] | 696 | assert(MaxAlign <= TargetAlign && |
| 697 | "Dynamic alloca with large aligns not supported"); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 698 | |
| 699 | // Determine the previous frame's address. If FrameSize can't be |
| 700 | // represented as 16 bits or we need special alignment, then we load the |
| 701 | // previous frame's address from 0(SP). Why not do an addis of the hi? |
| 702 | // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. |
| 703 | // Constructing the constant and adding would take 3 instructions. |
| 704 | // Fortunately, a frame greater than 32K is rare. |
| 705 | if (MaxAlign < TargetAlign && isInt16(FrameSize)) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 706 | BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 707 | .addReg(PPC::R31) |
| 708 | .addImm(FrameSize); |
| 709 | } else if (LP64) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 710 | BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 711 | .addImm(0) |
| 712 | .addReg(PPC::X1); |
| 713 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 714 | BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 715 | .addImm(0) |
| 716 | .addReg(PPC::R1); |
| 717 | } |
| 718 | |
| 719 | // Grow the stack and update the stack pointer link, then |
| 720 | // determine the address of new allocated space. |
| 721 | if (LP64) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 722 | BuildMI(MBB, II, TII.get(PPC::STDUX)) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 723 | .addReg(PPC::X0) |
| 724 | .addReg(PPC::X1) |
| 725 | .addReg(MI.getOperand(1).getReg()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 726 | BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 727 | .addReg(PPC::X1) |
| 728 | .addImm(maxCallFrameSize); |
| 729 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 730 | BuildMI(MBB, II, TII.get(PPC::STWUX)) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 731 | .addReg(PPC::R0) |
| 732 | .addReg(PPC::R1) |
| 733 | .addReg(MI.getOperand(1).getReg()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 734 | BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 735 | .addReg(PPC::R1) |
| 736 | .addImm(maxCallFrameSize); |
| 737 | } |
| 738 | |
| 739 | // Discard the DYNALLOC instruction. |
| 740 | MBB.erase(II); |
| 741 | } |
| 742 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 743 | void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 744 | int SPAdj, RegScavenger *RS) const { |
| 745 | assert(SPAdj == 0 && "Unexpected"); |
| 746 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 747 | // Get the instruction. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 748 | MachineInstr &MI = *II; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 749 | // Get the instruction's basic block. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 750 | MachineBasicBlock &MBB = *MI.getParent(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 751 | // Get the basic block's function. |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 752 | MachineFunction &MF = *MBB.getParent(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 753 | // Get the frame info. |
| 754 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 755 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 756 | // Find out which operand is the frame index. |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 757 | unsigned FIOperandNo = 0; |
| 758 | while (!MI.getOperand(FIOperandNo).isFrameIndex()) { |
| 759 | ++FIOperandNo; |
| 760 | assert(FIOperandNo != MI.getNumOperands() && |
| 761 | "Instr doesn't have FrameIndex operand!"); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 762 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 763 | // Take into account whether it's an add or mem instruction |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 764 | unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; |
Chris Lattner | 9aa2895 | 2007-02-01 00:39:08 +0000 | [diff] [blame] | 765 | if (MI.getOpcode() == TargetInstrInfo::INLINEASM) |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 766 | OffsetOperandNo = FIOperandNo-1; |
Chris Lattner | 9aa2895 | 2007-02-01 00:39:08 +0000 | [diff] [blame] | 767 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 768 | // Get the frame index. |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 769 | int FrameIndex = MI.getOperand(FIOperandNo).getFrameIndex(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 770 | |
| 771 | // Get the frame pointer save index. Users of this index are primarily |
| 772 | // DYNALLOC instructions. |
| 773 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 774 | int FPSI = FI->getFramePointerSaveIndex(); |
| 775 | // Get the instruction opcode. |
| 776 | unsigned OpC = MI.getOpcode(); |
| 777 | |
| 778 | // Special case for dynamic alloca. |
| 779 | if (FPSI && FrameIndex == FPSI && |
| 780 | (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { |
| 781 | lowerDynamicAlloc(II); |
| 782 | return; |
| 783 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 784 | |
| 785 | // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 786 | MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, |
| 787 | false); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 788 | |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 789 | // Figure out if the offset in the instruction is shifted right two bits. This |
| 790 | // is true for instructions like "STD", which the machine implicitly adds two |
| 791 | // low zeros to. |
| 792 | bool isIXAddr = false; |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 793 | switch (OpC) { |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 794 | case PPC::LWA: |
| 795 | case PPC::LD: |
| 796 | case PPC::STD: |
| 797 | case PPC::STD_32: |
| 798 | isIXAddr = true; |
| 799 | break; |
| 800 | } |
| 801 | |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 802 | // Now add the frame object offset to the offset from r1. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 803 | int Offset = MFI->getObjectOffset(FrameIndex); |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 804 | if (!isIXAddr) |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 805 | Offset += MI.getOperand(OffsetOperandNo).getImmedValue(); |
Chris Lattner | 7ffa9ab | 2006-06-27 18:55:49 +0000 | [diff] [blame] | 806 | else |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 807 | Offset += MI.getOperand(OffsetOperandNo).getImmedValue() << 2; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 808 | |
| 809 | // If we're not using a Frame Pointer that has been set to the value of the |
| 810 | // SP before having the stack size subtracted from it, then add the stack size |
| 811 | // to Offset to get the correct offset. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 812 | Offset += MFI->getStackSize(); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 813 | |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 814 | // If we can, encode the offset directly into the instruction. If this is a |
| 815 | // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If |
| 816 | // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits |
| 817 | // clear can be encoded. This is extremely uncommon, because normally you |
| 818 | // only "std" to a stack slot that is at least 4-byte aligned, but it can |
| 819 | // happen in invalid code. |
Chris Lattner | d964285 | 2007-12-08 07:04:58 +0000 | [diff] [blame] | 820 | if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 821 | if (isIXAddr) |
Chris Lattner | 841d12d | 2005-10-18 16:51:22 +0000 | [diff] [blame] | 822 | Offset >>= 2; // The actual encoded value has the low two bits zero. |
Chris Lattner | f602a25 | 2007-10-16 18:00:18 +0000 | [diff] [blame] | 823 | MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 824 | return; |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 825 | } |
Chris Lattner | 789db09 | 2007-11-27 22:14:42 +0000 | [diff] [blame] | 826 | |
| 827 | // Insert a set of r0 with the full offset value before the ld, st, or add |
| 828 | BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); |
| 829 | BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); |
| 830 | |
| 831 | // Convert into indexed form of the instruction |
| 832 | // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 |
| 833 | // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 |
| 834 | unsigned OperandBase; |
| 835 | if (OpC != TargetInstrInfo::INLINEASM) { |
| 836 | assert(ImmToIdxMap.count(OpC) && |
| 837 | "No indexed form of load or store available!"); |
| 838 | unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; |
| 839 | MI.setInstrDescriptor(TII.get(NewOpcode)); |
| 840 | OperandBase = 1; |
| 841 | } else { |
| 842 | OperandBase = OffsetOperandNo; |
| 843 | } |
| 844 | |
| 845 | unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); |
| 846 | MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); |
| 847 | MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 848 | } |
| 849 | |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 850 | /// VRRegNo - Map from a numbered VR register to its enum value. |
| 851 | /// |
| 852 | static const unsigned short VRRegNo[] = { |
Chris Lattner | b47e089 | 2006-06-12 21:50:57 +0000 | [diff] [blame] | 853 | PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , |
| 854 | PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 855 | PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, |
| 856 | PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 |
| 857 | }; |
| 858 | |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 859 | /// RemoveVRSaveCode - We have found that this function does not need any code |
| 860 | /// to manipulate the VRSAVE register, even though it uses vector registers. |
| 861 | /// This can happen when the only registers used are known to be live in or out |
| 862 | /// of the function. Remove all of the VRSAVE related code from the function. |
| 863 | static void RemoveVRSaveCode(MachineInstr *MI) { |
| 864 | MachineBasicBlock *Entry = MI->getParent(); |
| 865 | MachineFunction *MF = Entry->getParent(); |
| 866 | |
| 867 | // We know that the MTVRSAVE instruction immediately follows MI. Remove it. |
| 868 | MachineBasicBlock::iterator MBBI = MI; |
| 869 | ++MBBI; |
| 870 | assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); |
| 871 | MBBI->eraseFromParent(); |
| 872 | |
| 873 | bool RemovedAllMTVRSAVEs = true; |
| 874 | // See if we can find and remove the MTVRSAVE instruction from all of the |
| 875 | // epilog blocks. |
| 876 | const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); |
| 877 | for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { |
| 878 | // If last instruction is a return instruction, add an epilogue |
| 879 | if (!I->empty() && TII.isReturn(I->back().getOpcode())) { |
| 880 | bool FoundIt = false; |
| 881 | for (MBBI = I->end(); MBBI != I->begin(); ) { |
| 882 | --MBBI; |
| 883 | if (MBBI->getOpcode() == PPC::MTVRSAVE) { |
| 884 | MBBI->eraseFromParent(); // remove it. |
| 885 | FoundIt = true; |
| 886 | break; |
| 887 | } |
| 888 | } |
| 889 | RemovedAllMTVRSAVEs &= FoundIt; |
| 890 | } |
| 891 | } |
| 892 | |
| 893 | // If we found and removed all MTVRSAVE instructions, remove the read of |
| 894 | // VRSAVE as well. |
| 895 | if (RemovedAllMTVRSAVEs) { |
| 896 | MBBI = MI; |
| 897 | assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); |
| 898 | --MBBI; |
| 899 | assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); |
| 900 | MBBI->eraseFromParent(); |
| 901 | } |
| 902 | |
| 903 | // Finally, nuke the UPDATE_VRSAVE. |
| 904 | MI->eraseFromParent(); |
| 905 | } |
| 906 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 907 | // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the |
| 908 | // instruction selector. Based on the vector registers that have been used, |
| 909 | // transform this into the appropriate ORI instruction. |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 910 | static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { |
| 911 | MachineFunction *MF = MI->getParent()->getParent(); |
| 912 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 913 | unsigned UsedRegMask = 0; |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 914 | for (unsigned i = 0; i != 32; ++i) |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 915 | if (MF->isPhysRegUsed(VRRegNo[i])) |
Chris Lattner | f7d2372 | 2006-04-17 20:59:25 +0000 | [diff] [blame] | 916 | UsedRegMask |= 1 << (31-i); |
| 917 | |
Chris Lattner | 402504b | 2006-04-17 21:22:06 +0000 | [diff] [blame] | 918 | // Live in and live out values already must be in the mask, so don't bother |
| 919 | // marking them. |
Chris Lattner | 402504b | 2006-04-17 21:22:06 +0000 | [diff] [blame] | 920 | for (MachineFunction::livein_iterator I = |
| 921 | MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { |
| 922 | unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); |
| 923 | if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. |
| 924 | UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. |
| 925 | } |
| 926 | for (MachineFunction::liveout_iterator I = |
| 927 | MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { |
| 928 | unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); |
| 929 | if (VRRegNo[RegNo] == *I) // If this really is a vector reg. |
| 930 | UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. |
| 931 | } |
| 932 | |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 933 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 934 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 935 | // If no registers are used, turn this into a copy. |
| 936 | if (UsedRegMask == 0) { |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 937 | // Remove all VRSAVE code. |
| 938 | RemoveVRSaveCode(MI); |
| 939 | return; |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 940 | } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 941 | BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 942 | .addReg(SrcReg).addImm(UsedRegMask); |
| 943 | } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 944 | BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 945 | .addReg(SrcReg).addImm(UsedRegMask >> 16); |
| 946 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 947 | BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 948 | .addReg(SrcReg).addImm(UsedRegMask >> 16); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 949 | BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 950 | .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); |
| 951 | } |
| 952 | |
| 953 | // Remove the old UPDATE_VRSAVE instruction. |
Chris Lattner | f9568d8 | 2006-04-17 21:48:13 +0000 | [diff] [blame] | 954 | MI->eraseFromParent(); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 955 | } |
| 956 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 957 | /// determineFrameLayout - Determine the size of the frame and maximum call |
| 958 | /// frame size. |
| 959 | void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { |
| 960 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 961 | |
| 962 | // Get the number of bytes to allocate from the FrameInfo |
| 963 | unsigned FrameSize = MFI->getStackSize(); |
| 964 | |
| 965 | // Get the alignments provided by the target, and the maximum alignment |
| 966 | // (if any) of the fixed frame objects. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 967 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Evan Cheng | 99403b6 | 2007-01-25 22:25:04 +0000 | [diff] [blame] | 968 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 969 | unsigned AlignMask = TargetAlign - 1; // |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 970 | |
| 971 | // If we are a leaf function, and use up to 224 bytes of stack space, |
| 972 | // don't have a frame pointer, calls, or dynamic alloca then we do not need |
| 973 | // to adjust the stack pointer (we fit in the Red Zone). |
| 974 | if (FrameSize <= 224 && // Fits in red zone. |
Jim Laskey | 2ff5cdb | 2006-11-17 16:09:31 +0000 | [diff] [blame] | 975 | !MFI->hasVarSizedObjects() && // No dynamic alloca. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 976 | !MFI->hasCalls() && // No calls. |
| 977 | MaxAlign <= TargetAlign) { // No special alignment. |
| 978 | // No need for frame |
| 979 | MFI->setStackSize(0); |
| 980 | return; |
| 981 | } |
| 982 | |
| 983 | // Get the maximum call frame size of all the calls. |
| 984 | unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); |
| 985 | |
| 986 | // Maximum call frame needs to be at least big enough for linkage and 8 args. |
| 987 | unsigned minCallFrameSize = |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 988 | PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), |
| 989 | Subtarget.isMachoABI()); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 990 | maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); |
| 991 | |
| 992 | // If we have dynamic alloca then maxCallFrameSize needs to be aligned so |
| 993 | // that allocations will be aligned. |
| 994 | if (MFI->hasVarSizedObjects()) |
| 995 | maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; |
| 996 | |
| 997 | // Update maximum call frame size. |
| 998 | MFI->setMaxCallFrameSize(maxCallFrameSize); |
| 999 | |
| 1000 | // Include call frame size in total. |
| 1001 | FrameSize += maxCallFrameSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1002 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1003 | // Make sure the frame is aligned. |
| 1004 | FrameSize = (FrameSize + AlignMask) & ~AlignMask; |
| 1005 | |
| 1006 | // Update frame info. |
| 1007 | MFI->setStackSize(FrameSize); |
| 1008 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1009 | |
Evan Cheng | 28b3c45 | 2007-03-06 10:05:14 +0000 | [diff] [blame] | 1010 | void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, |
| 1011 | RegScavenger *RS) |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1012 | const { |
| 1013 | // Save and clear the LR state. |
| 1014 | PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); |
| 1015 | unsigned LR = getRARegister(); |
| 1016 | FI->setUsesLR(MF.isPhysRegUsed(LR)); |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1017 | MF.setPhysRegUnused(LR); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 1018 | |
| 1019 | // Save R31 if necessary |
| 1020 | int FPSI = FI->getFramePointerSaveIndex(); |
| 1021 | bool IsPPC64 = Subtarget.isPPC64(); |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1022 | bool IsELF32_ABI = Subtarget.isELF32_ABI(); |
| 1023 | bool IsMachoABI = Subtarget.isMachoABI(); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 1024 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1025 | |
| 1026 | // If the frame pointer save index hasn't been defined yet. |
| 1027 | if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1028 | && IsELF32_ABI) { |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 1029 | // Find out what the fix offset of the frame pointer save area. |
Nicolas Geoffray | ec58d9f | 2007-04-03 12:35:28 +0000 | [diff] [blame] | 1030 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, |
| 1031 | IsMachoABI); |
Nicolas Geoffray | 82d4264 | 2007-03-21 16:44:14 +0000 | [diff] [blame] | 1032 | // Allocate the frame index for frame pointer save area. |
| 1033 | FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); |
| 1034 | // Save the result. |
| 1035 | FI->setFramePointerSaveIndex(FPSI); |
| 1036 | } |
| 1037 | |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1038 | } |
| 1039 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1040 | void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1041 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
| 1042 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 1043 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1044 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 1045 | |
Jim Laskey | 072200c | 2007-01-29 18:51:14 +0000 | [diff] [blame] | 1046 | // Prepare for frame info. |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1047 | unsigned FrameLabelId = 0; |
| 1048 | |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 1049 | // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, |
| 1050 | // process it. |
Chris Lattner | 8aa777d | 2006-03-16 21:31:45 +0000 | [diff] [blame] | 1051 | for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 1052 | if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { |
Evan Cheng | 6c087e5 | 2007-04-25 22:13:27 +0000 | [diff] [blame] | 1053 | HandleVRSaveUpdate(MBBI, TII); |
Chris Lattner | 1877ec9 | 2006-03-13 21:52:10 +0000 | [diff] [blame] | 1054 | break; |
| 1055 | } |
| 1056 | } |
| 1057 | |
| 1058 | // Move MBBI back to the beginning of the function. |
| 1059 | MBBI = MBB.begin(); |
| 1060 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1061 | // Work out frame sizes. |
| 1062 | determineFrameLayout(MF); |
| 1063 | unsigned FrameSize = MFI->getStackSize(); |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 1064 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1065 | int NegFrameSize = -FrameSize; |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1066 | |
| 1067 | // Get processor type. |
| 1068 | bool IsPPC64 = Subtarget.isPPC64(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1069 | // Get operating system |
| 1070 | bool IsMachoABI = Subtarget.isMachoABI(); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1071 | // Check if the link register (LR) has been used. |
Chris Lattner | 73944fb | 2007-12-08 06:39:11 +0000 | [diff] [blame] | 1072 | bool UsesLR = MustSaveLR(MF); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1073 | // Do we have a frame pointer for this function? |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1074 | bool HasFP = hasFP(MF) && FrameSize; |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1075 | |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1076 | int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); |
| 1077 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1078 | |
| 1079 | if (IsPPC64) { |
| 1080 | if (UsesLR) |
| 1081 | BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); |
| 1082 | |
| 1083 | if (HasFP) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1084 | BuildMI(MBB, MBBI, TII.get(PPC::STD)) |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1085 | .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); |
| 1086 | |
| 1087 | if (UsesLR) |
| 1088 | BuildMI(MBB, MBBI, TII.get(PPC::STD)) |
| 1089 | .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); |
| 1090 | } else { |
| 1091 | if (UsesLR) |
| 1092 | BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); |
| 1093 | |
| 1094 | if (HasFP) |
| 1095 | BuildMI(MBB, MBBI, TII.get(PPC::STW)) |
| 1096 | .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); |
| 1097 | |
| 1098 | if (UsesLR) |
| 1099 | BuildMI(MBB, MBBI, TII.get(PPC::STW)) |
| 1100 | .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1101 | } |
| 1102 | |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1103 | // Skip if a leaf routine. |
| 1104 | if (!FrameSize) return; |
| 1105 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1106 | // Get stack alignments. |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 1107 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 1108 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1109 | |
Jim Laskey | e078d1a | 2007-01-29 23:20:22 +0000 | [diff] [blame] | 1110 | if (MMI && MMI->needsFrameInfo()) { |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1111 | // Mark effective beginning of when frame pointer becomes valid. |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1112 | FrameLabelId = MMI->NextLabelID(); |
Jim Laskey | 1ee2925 | 2007-01-26 14:34:52 +0000 | [diff] [blame] | 1113 | BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1114 | } |
| 1115 | |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1116 | // Adjust stack pointer: r1 += NegFrameSize. |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 1117 | // If there is a preferred stack alignment, align R1 now |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1118 | if (!IsPPC64) { |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1119 | // PPC32. |
| 1120 | if (MaxAlign > TargetAlign) { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1121 | assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); |
| 1122 | assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1123 | BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1124 | .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1125 | BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1126 | .addImm(NegFrameSize); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1127 | BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1128 | .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1129 | } else if (isInt16(NegFrameSize)) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1130 | BuildMI(MBB, MBBI, TII.get(PPC::STWU), |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1131 | PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1132 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1133 | BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); |
| 1134 | BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1135 | .addImm(NegFrameSize & 0xFFFF); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1136 | BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1137 | .addReg(PPC::R0); |
| 1138 | } |
| 1139 | } else { // PPC64. |
| 1140 | if (MaxAlign > TargetAlign) { |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1141 | assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); |
| 1142 | assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1143 | BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1144 | .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1145 | BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1146 | .addImm(NegFrameSize); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1147 | BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1148 | .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); |
Jim Laskey | 2ff5cdb | 2006-11-17 16:09:31 +0000 | [diff] [blame] | 1149 | } else if (isInt16(NegFrameSize)) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1150 | BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1151 | .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1152 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1153 | BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); |
| 1154 | BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1155 | .addImm(NegFrameSize & 0xFFFF); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1156 | BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1157 | .addReg(PPC::X0); |
| 1158 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1159 | } |
Nate Begeman | ae232e7 | 2005-11-06 09:00:38 +0000 | [diff] [blame] | 1160 | |
Jim Laskey | e078d1a | 2007-01-29 23:20:22 +0000 | [diff] [blame] | 1161 | if (MMI && MMI->needsFrameInfo()) { |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1162 | std::vector<MachineMove> &Moves = MMI->getFrameMoves(); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1163 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1164 | if (NegFrameSize) { |
| 1165 | // Show update of SP. |
| 1166 | MachineLocation SPDst(MachineLocation::VirtualFP); |
| 1167 | MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); |
| 1168 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
| 1169 | } else { |
| 1170 | MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); |
| 1171 | Moves.push_back(MachineMove(FrameLabelId, SP, SP)); |
| 1172 | } |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame] | 1173 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1174 | if (HasFP) { |
| 1175 | MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); |
| 1176 | MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); |
| 1177 | Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); |
| 1178 | } |
Jim Laskey | ce50a16 | 2006-08-29 16:24:26 +0000 | [diff] [blame] | 1179 | |
| 1180 | // Add callee saved registers to move list. |
| 1181 | const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); |
| 1182 | for (unsigned I = 0, E = CSI.size(); I != E; ++I) { |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1183 | int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); |
| 1184 | unsigned Reg = CSI[I].getReg(); |
| 1185 | if (Reg == PPC::LR || Reg == PPC::LR8) continue; |
| 1186 | MachineLocation CSDst(MachineLocation::VirtualFP, Offset); |
| 1187 | MachineLocation CSSrc(Reg); |
| 1188 | Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); |
Jim Laskey | ce50a16 | 2006-08-29 16:24:26 +0000 | [diff] [blame] | 1189 | } |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1190 | |
Jim Laskey | b82313f | 2007-02-01 16:31:34 +0000 | [diff] [blame] | 1191 | MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); |
| 1192 | MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); |
| 1193 | Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); |
| 1194 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1195 | // Mark effective beginning of when frame pointer is ready. |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1196 | unsigned ReadyLabelId = MMI->NextLabelID(); |
Jim Laskey | 1ee2925 | 2007-01-26 14:34:52 +0000 | [diff] [blame] | 1197 | BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1198 | |
| 1199 | MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : |
| 1200 | (IsPPC64 ? PPC::X1 : PPC::R1)); |
| 1201 | MachineLocation FPSrc(MachineLocation::VirtualFP); |
| 1202 | Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1203 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1204 | |
| 1205 | // If there is a frame pointer, copy R1 into R31 |
Chris Lattner | 4f91a4c | 2006-04-03 22:03:29 +0000 | [diff] [blame] | 1206 | if (HasFP) { |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1207 | if (!IsPPC64) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1208 | BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) |
| 1209 | .addReg(PPC::R1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1210 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1211 | BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) |
| 1212 | .addReg(PPC::X1); |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1213 | } |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1214 | } |
| 1215 | } |
| 1216 | |
Nate Begeman | 21e463b | 2005-10-16 05:39:50 +0000 | [diff] [blame] | 1217 | void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, |
| 1218 | MachineBasicBlock &MBB) const { |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1219 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Evan Cheng | 6da8d99 | 2006-01-09 18:28:21 +0000 | [diff] [blame] | 1220 | assert(MBBI->getOpcode() == PPC::BLR && |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1221 | "Can only insert epilog into returning blocks"); |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 1222 | |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 1223 | // Get alignment info so we know how to restore r1 |
| 1224 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1225 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1226 | unsigned MaxAlign = MFI->getMaxAlignment(); |
Nate Begeman | 030514c | 2006-04-11 19:29:21 +0000 | [diff] [blame] | 1227 | |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 1228 | // Get the number of bytes allocated from the FrameInfo. |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1229 | unsigned FrameSize = MFI->getStackSize(); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1230 | |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1231 | // Get processor type. |
| 1232 | bool IsPPC64 = Subtarget.isPPC64(); |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1233 | // Get operating system |
| 1234 | bool IsMachoABI = Subtarget.isMachoABI(); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1235 | // Check if the link register (LR) has been used. |
Chris Lattner | 73944fb | 2007-12-08 06:39:11 +0000 | [diff] [blame] | 1236 | bool UsesLR = MustSaveLR(MF); |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1237 | // Do we have a frame pointer for this function? |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1238 | bool HasFP = hasFP(MF) && FrameSize; |
Chris Lattner | 9f0bc65 | 2007-02-25 05:34:32 +0000 | [diff] [blame] | 1239 | |
| 1240 | int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); |
| 1241 | int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); |
| 1242 | |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1243 | if (FrameSize) { |
| 1244 | // The loaded (or persistent) stack pointer value is offset by the 'stwu' |
| 1245 | // on entry to the function. Add this offset back now. |
| 1246 | if (!Subtarget.isPPC64()) { |
| 1247 | if (isInt16(FrameSize) && TargetAlign >= MaxAlign && |
| 1248 | !MFI->hasVarSizedObjects()) { |
| 1249 | BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) |
| 1250 | .addReg(PPC::R1).addImm(FrameSize); |
| 1251 | } else { |
| 1252 | BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); |
| 1253 | } |
Chris Lattner | 64da172 | 2006-01-11 23:03:54 +0000 | [diff] [blame] | 1254 | } else { |
Jim Laskey | d313a9b | 2007-02-27 11:55:45 +0000 | [diff] [blame] | 1255 | if (isInt16(FrameSize) && TargetAlign >= MaxAlign && |
| 1256 | !MFI->hasVarSizedObjects()) { |
| 1257 | BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) |
| 1258 | .addReg(PPC::X1).addImm(FrameSize); |
| 1259 | } else { |
| 1260 | BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); |
| 1261 | } |
Jim Laskey | 2f616bf | 2006-11-16 22:43:37 +0000 | [diff] [blame] | 1262 | } |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1263 | } |
Jim Laskey | 51fe9d9 | 2006-12-06 17:42:06 +0000 | [diff] [blame] | 1264 | |
| 1265 | if (IsPPC64) { |
| 1266 | if (UsesLR) |
| 1267 | BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) |
| 1268 | .addImm(LROffset/4).addReg(PPC::X1); |
| 1269 | |
| 1270 | if (HasFP) |
| 1271 | BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) |
| 1272 | .addImm(FPOffset/4).addReg(PPC::X1); |
| 1273 | |
| 1274 | if (UsesLR) |
| 1275 | BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); |
| 1276 | } else { |
| 1277 | if (UsesLR) |
| 1278 | BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) |
| 1279 | .addImm(LROffset).addReg(PPC::R1); |
| 1280 | |
| 1281 | if (HasFP) |
| 1282 | BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) |
| 1283 | .addImm(FPOffset).addReg(PPC::R1); |
| 1284 | |
| 1285 | if (UsesLR) |
| 1286 | BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1287 | } |
| 1288 | } |
| 1289 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1290 | unsigned PPCRegisterInfo::getRARegister() const { |
Chris Lattner | 6a5339b | 2006-11-14 18:44:47 +0000 | [diff] [blame] | 1291 | return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1292 | } |
| 1293 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 1294 | unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Chris Lattner | a94a203 | 2006-11-11 19:05:28 +0000 | [diff] [blame] | 1295 | if (!Subtarget.isPPC64()) |
| 1296 | return hasFP(MF) ? PPC::R31 : PPC::R1; |
| 1297 | else |
| 1298 | return hasFP(MF) ? PPC::X31 : PPC::X1; |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1299 | } |
| 1300 | |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1301 | void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1302 | const { |
Jim Laskey | 4c2c903 | 2006-08-25 19:40:59 +0000 | [diff] [blame] | 1303 | // Initial state of the frame pointer is R1. |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1304 | MachineLocation Dst(MachineLocation::VirtualFP); |
| 1305 | MachineLocation Src(PPC::R1, 0); |
Jim Laskey | 5e73d5b | 2007-01-24 18:45:13 +0000 | [diff] [blame] | 1306 | Moves.push_back(MachineMove(0, Dst, Src)); |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 1307 | } |
| 1308 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 1309 | unsigned PPCRegisterInfo::getEHExceptionRegister() const { |
| 1310 | return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; |
| 1311 | } |
| 1312 | |
| 1313 | unsigned PPCRegisterInfo::getEHHandlerRegister() const { |
| 1314 | return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; |
| 1315 | } |
| 1316 | |
Dale Johannesen | b97aec6 | 2007-11-13 19:13:01 +0000 | [diff] [blame] | 1317 | int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { |
Anton Korobeynikov | 3809fbe | 2007-11-12 23:36:13 +0000 | [diff] [blame] | 1318 | // FIXME: Most probably dwarf numbers differs for Linux and Darwin |
| 1319 | return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 1320 | } |
| 1321 | |
Chris Lattner | 4c7b43b | 2005-10-14 23:37:35 +0000 | [diff] [blame] | 1322 | #include "PPCGenRegisterInfo.inc" |
Misha Brukman | f2ccb77 | 2004-08-17 04:55:41 +0000 | [diff] [blame] | 1323 | |