Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 1 | //===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===// |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 2 | // |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 7 | // |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the IA64 implementation of the TargetInstrInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "IA64InstrInfo.h" |
| 15 | #include "IA64.h" |
| 16 | #include "IA64InstrBuilder.h" |
| 17 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 18 | #include "IA64GenInstrInfo.inc" |
| 19 | using namespace llvm; |
| 20 | |
| 21 | IA64InstrInfo::IA64InstrInfo() |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 22 | : TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])), |
| 23 | RI(*this) { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 24 | } |
| 25 | |
| 26 | |
| 27 | bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI, |
| 28 | unsigned& sourceReg, |
| 29 | unsigned& destReg) const { |
| 30 | MachineOpCode oc = MI.getOpcode(); |
| 31 | if (oc == IA64::MOV || oc == IA64::FMOV) { |
Duraid Madina | badf0d9 | 2006-01-25 02:23:38 +0000 | [diff] [blame] | 32 | // TODO: this doesn't detect predicate moves |
Evan Cheng | 1e341729 | 2007-04-25 07:12:14 +0000 | [diff] [blame] | 33 | assert(MI.getNumOperands() >= 2 && |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 34 | /* MI.getOperand(0).isRegister() && |
| 35 | MI.getOperand(1).isRegister() && */ |
| 36 | "invalid register-register move instruction"); |
| 37 | if( MI.getOperand(0).isRegister() && |
Misha Brukman | 7847fca | 2005-04-22 17:54:37 +0000 | [diff] [blame] | 38 | MI.getOperand(1).isRegister() ) { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 39 | // if both operands of the MOV/FMOV are registers, then |
| 40 | // yes, this is a move instruction |
| 41 | sourceReg = MI.getOperand(1).getReg(); |
| 42 | destReg = MI.getOperand(0).getReg(); |
| 43 | return true; |
| 44 | } |
| 45 | } |
| 46 | return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a |
| 47 | // move instruction |
| 48 | } |
| 49 | |
Evan Cheng | b5cdaa2 | 2007-05-18 00:05:48 +0000 | [diff] [blame] | 50 | unsigned |
| 51 | IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, |
| 52 | MachineBasicBlock *FBB, |
| 53 | const std::vector<MachineOperand> &Cond)const { |
Chris Lattner | 11533e2 | 2006-10-24 16:44:55 +0000 | [diff] [blame] | 54 | // Can only insert uncond branches so far. |
| 55 | assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 56 | BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB); |
Evan Cheng | b5cdaa2 | 2007-05-18 00:05:48 +0000 | [diff] [blame] | 57 | return 1; |
Rafael Espindola | 3d7d39a | 2006-10-24 17:07:11 +0000 | [diff] [blame] | 58 | } |