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gerrit-public.fairphone.software / platform / external / llvm / 4ee451de366474b9c228b4e5fa573795a715216d / . / lib / Target / PowerPC / PPCScheduleG4Plus.td
blob: 7474ba494d100ddeb879b2de599202464f86c8a6 [file] [log] [blame]
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]1//===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame^]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the G4+ (7450) processor.
11//
12//===----------------------------------------------------------------------===//
13
Jim Laskey0de87962005-10-19 13:34:52 +0000[diff] [blame]14def G4PlusItineraries : ProcessorItineraries<[
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]15 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
16 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]17 InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
18 InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
19 InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
20 InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]21 InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
22 InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
23 InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]24 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
25 InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]26 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
27 InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
28 InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
29 InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
30 InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]31 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
32 InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]33 InstrItinData<LdStGeneral , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]34 InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
35 InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]36 InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]37 InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
38 InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
39 InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
40 InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]41 InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]42 InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
43 InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]44 InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
45 InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
46 InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
47 InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
48 InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
49 InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
50 InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>,
51 InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>,
52 InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>,
53 InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
54 InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
55 InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
56 InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>,
57 InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>,
58 InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>,
59 InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>,
60 InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
61 InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
62 InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
63 InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
64 InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
65 InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
66 InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
67 InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]68 InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
69 InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
70 InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
71 InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>,
72 InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>,
73 InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>,
74 InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>,
75 InstrItinData<VecVSR , [InstrStage<2, [VPU]>]>
76]>;