Misha Brukman | a85d6bc | 2002-11-22 22:42:50 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 2 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 7 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 9 | // |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 10 | // This file contains the X86 implementation of the TargetInstrInfo class. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Chris Lattner | 055c965 | 2002-10-29 21:05:24 +0000 | [diff] [blame] | 14 | #include "X86InstrInfo.h" |
Chris Lattner | 4ce42a7 | 2002-12-03 05:42:53 +0000 | [diff] [blame] | 15 | #include "X86.h" |
Chris Lattner | abf05b2 | 2003-08-03 21:55:55 +0000 | [diff] [blame] | 16 | #include "X86GenInstrInfo.inc" |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 17 | #include "X86InstrBuilder.h" |
| 18 | #include "X86Subtarget.h" |
| 19 | #include "X86TargetMachine.h" |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 20 | #include "llvm/ADT/STLExtras.h" |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/LiveVariables.h" |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/SSARegMap.h" |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 24 | #include "llvm/Target/TargetOptions.h" |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 25 | using namespace llvm; |
| 26 | |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 27 | X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 28 | : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)), |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 29 | TM(tm), RI(tm, *this) { |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 30 | } |
| 31 | |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 32 | bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, |
| 33 | unsigned& sourceReg, |
| 34 | unsigned& destReg) const { |
| 35 | MachineOpCode oc = MI.getOpcode(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 36 | if (oc == X86::MOV8rr || oc == X86::MOV16rr || |
| 37 | oc == X86::MOV32rr || oc == X86::MOV64rr || |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 38 | oc == X86::MOV16to16_ || oc == X86::MOV32to32_ || |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 39 | oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr || |
| 40 | oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 || |
Evan Cheng | fe5cb19 | 2006-02-16 22:45:17 +0000 | [diff] [blame] | 41 | oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || |
Evan Cheng | 82521dd | 2006-03-21 07:09:35 +0000 | [diff] [blame] | 42 | oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 43 | oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 44 | oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr || |
Bill Wendling | 6dd29e0 | 2007-04-24 21:17:46 +0000 | [diff] [blame] | 45 | oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) { |
Evan Cheng | 1e341729 | 2007-04-25 07:12:14 +0000 | [diff] [blame] | 46 | assert(MI.getNumOperands() >= 2 && |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 47 | MI.getOperand(0).isRegister() && |
| 48 | MI.getOperand(1).isRegister() && |
| 49 | "invalid register-register move instruction"); |
Alkis Evlogimenos | be766c7 | 2004-02-13 21:01:20 +0000 | [diff] [blame] | 50 | sourceReg = MI.getOperand(1).getReg(); |
| 51 | destReg = MI.getOperand(0).getReg(); |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 52 | return true; |
| 53 | } |
| 54 | return false; |
| 55 | } |
Alkis Evlogimenos | 36f506e | 2004-07-31 09:38:47 +0000 | [diff] [blame] | 56 | |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 57 | unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, |
| 58 | int &FrameIndex) const { |
| 59 | switch (MI->getOpcode()) { |
| 60 | default: break; |
| 61 | case X86::MOV8rm: |
| 62 | case X86::MOV16rm: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 63 | case X86::MOV16_rm: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 64 | case X86::MOV32rm: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 65 | case X86::MOV32_rm: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 66 | case X86::MOV64rm: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 67 | case X86::LD_Fp64m: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 68 | case X86::MOVSSrm: |
| 69 | case X86::MOVSDrm: |
Chris Lattner | 993c897 | 2006-04-18 16:44:51 +0000 | [diff] [blame] | 70 | case X86::MOVAPSrm: |
| 71 | case X86::MOVAPDrm: |
Bill Wendling | 823efee | 2007-04-03 06:00:37 +0000 | [diff] [blame] | 72 | case X86::MMX_MOVD64rm: |
| 73 | case X86::MMX_MOVQ64rm: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 74 | if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && |
| 75 | MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() && |
| 76 | MI->getOperand(2).getImmedValue() == 1 && |
| 77 | MI->getOperand(3).getReg() == 0 && |
| 78 | MI->getOperand(4).getImmedValue() == 0) { |
| 79 | FrameIndex = MI->getOperand(1).getFrameIndex(); |
| 80 | return MI->getOperand(0).getReg(); |
| 81 | } |
| 82 | break; |
| 83 | } |
| 84 | return 0; |
| 85 | } |
| 86 | |
| 87 | unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, |
| 88 | int &FrameIndex) const { |
| 89 | switch (MI->getOpcode()) { |
| 90 | default: break; |
| 91 | case X86::MOV8mr: |
| 92 | case X86::MOV16mr: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 93 | case X86::MOV16_mr: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 94 | case X86::MOV32mr: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 95 | case X86::MOV32_mr: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 96 | case X86::MOV64mr: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 97 | case X86::ST_FpP64m: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 98 | case X86::MOVSSmr: |
| 99 | case X86::MOVSDmr: |
Chris Lattner | 993c897 | 2006-04-18 16:44:51 +0000 | [diff] [blame] | 100 | case X86::MOVAPSmr: |
| 101 | case X86::MOVAPDmr: |
Bill Wendling | 823efee | 2007-04-03 06:00:37 +0000 | [diff] [blame] | 102 | case X86::MMX_MOVD64mr: |
| 103 | case X86::MMX_MOVQ64mr: |
Bill Wendling | 71bfd11 | 2007-04-03 23:48:32 +0000 | [diff] [blame] | 104 | case X86::MMX_MOVNTQmr: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 105 | if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && |
| 106 | MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && |
Chris Lattner | 1c07e72 | 2006-02-02 20:38:12 +0000 | [diff] [blame] | 107 | MI->getOperand(1).getImmedValue() == 1 && |
| 108 | MI->getOperand(2).getReg() == 0 && |
| 109 | MI->getOperand(3).getImmedValue() == 0) { |
| 110 | FrameIndex = MI->getOperand(0).getFrameIndex(); |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 111 | return MI->getOperand(4).getReg(); |
| 112 | } |
| 113 | break; |
| 114 | } |
| 115 | return 0; |
| 116 | } |
| 117 | |
| 118 | |
Bill Wendling | 041b3f8 | 2007-12-08 23:58:46 +0000 | [diff] [blame] | 119 | bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const { |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 120 | switch (MI->getOpcode()) { |
| 121 | default: break; |
| 122 | case X86::MOV8rm: |
| 123 | case X86::MOV16rm: |
| 124 | case X86::MOV16_rm: |
| 125 | case X86::MOV32rm: |
| 126 | case X86::MOV32_rm: |
| 127 | case X86::MOV64rm: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 128 | case X86::LD_Fp64m: |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 129 | case X86::MOVSSrm: |
| 130 | case X86::MOVSDrm: |
| 131 | case X86::MOVAPSrm: |
| 132 | case X86::MOVAPDrm: |
| 133 | case X86::MMX_MOVD64rm: |
| 134 | case X86::MMX_MOVQ64rm: |
Dan Gohman | 82a87a0 | 2007-06-19 01:48:05 +0000 | [diff] [blame] | 135 | // Loads from constant pools are trivially rematerializable. |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 136 | return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() && |
| 137 | MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() && |
| 138 | MI->getOperand(1).getReg() == 0 && |
| 139 | MI->getOperand(2).getImmedValue() == 1 && |
| 140 | MI->getOperand(3).getReg() == 0; |
| 141 | } |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 142 | // All other instructions marked M_REMATERIALIZABLE are always trivially |
| 143 | // rematerializable. |
| 144 | return true; |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 145 | } |
| 146 | |
Bill Wendling | 627c00b | 2007-12-17 23:07:56 +0000 | [diff] [blame] | 147 | /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this |
| 148 | /// method is called to determine if the specific instance of this instruction |
| 149 | /// has side effects. This is useful in cases of instructions, like loads, which |
| 150 | /// generally always have side effects. A load from a constant pool doesn't have |
| 151 | /// side effects, though. So we need to differentiate it from the general case. |
| 152 | bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const { |
| 153 | switch (MI->getOpcode()) { |
| 154 | default: break; |
| 155 | case X86::MOV8rm: |
| 156 | case X86::MOV16rm: |
| 157 | case X86::MOV16_rm: |
| 158 | case X86::MOV32rm: |
| 159 | case X86::MOV32_rm: |
| 160 | case X86::MOV64rm: |
| 161 | case X86::LD_Fp64m: |
| 162 | case X86::MOVSSrm: |
| 163 | case X86::MOVSDrm: |
| 164 | case X86::MOVAPSrm: |
| 165 | case X86::MOVAPDrm: |
| 166 | case X86::MMX_MOVD64rm: |
| 167 | case X86::MMX_MOVQ64rm: |
| 168 | // Loads from constant pools have no side effects |
| 169 | return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() && |
| 170 | MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() && |
| 171 | MI->getOperand(1).getReg() == 0 && |
| 172 | MI->getOperand(2).getImmedValue() == 1 && |
| 173 | MI->getOperand(3).getReg() == 0; |
| 174 | } |
| 175 | |
| 176 | // All other instances of these instructions are presumed to have side |
| 177 | // effects. |
| 178 | return false; |
| 179 | } |
| 180 | |
Evan Cheng | 3f411c7 | 2007-10-05 08:04:01 +0000 | [diff] [blame] | 181 | /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that |
| 182 | /// is not marked dead. |
| 183 | static bool hasLiveCondCodeDef(MachineInstr *MI) { |
Evan Cheng | 3f411c7 | 2007-10-05 08:04:01 +0000 | [diff] [blame] | 184 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 185 | MachineOperand &MO = MI->getOperand(i); |
| 186 | if (MO.isRegister() && MO.isDef() && |
| 187 | MO.getReg() == X86::EFLAGS && !MO.isDead()) { |
| 188 | return true; |
| 189 | } |
| 190 | } |
| 191 | return false; |
| 192 | } |
| 193 | |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 194 | /// convertToThreeAddress - This method must be implemented by targets that |
| 195 | /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target |
| 196 | /// may be able to convert a two-address instruction into a true |
| 197 | /// three-address instruction on demand. This allows the X86 target (for |
| 198 | /// example) to convert ADD and SHL instructions into LEA instructions if they |
| 199 | /// would require register copies due to two-addressness. |
| 200 | /// |
| 201 | /// This method returns a null pointer if the transformation cannot be |
| 202 | /// performed, otherwise it returns the new instruction. |
| 203 | /// |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 204 | MachineInstr * |
| 205 | X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, |
| 206 | MachineBasicBlock::iterator &MBBI, |
| 207 | LiveVariables &LV) const { |
| 208 | MachineInstr *MI = MBBI; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 209 | // All instructions input are two-addr instructions. Get the known operands. |
| 210 | unsigned Dest = MI->getOperand(0).getReg(); |
| 211 | unsigned Src = MI->getOperand(1).getReg(); |
| 212 | |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 213 | MachineInstr *NewMI = NULL; |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 214 | // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 215 | // we have better subtarget support, enable the 16-bit LEA generation here. |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 216 | bool DisableLEA16 = true; |
| 217 | |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 218 | unsigned MIOpc = MI->getOpcode(); |
| 219 | switch (MIOpc) { |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 220 | case X86::SHUFPSrri: { |
| 221 | assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 222 | if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; |
| 223 | |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 224 | unsigned A = MI->getOperand(0).getReg(); |
| 225 | unsigned B = MI->getOperand(1).getReg(); |
| 226 | unsigned C = MI->getOperand(2).getReg(); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 227 | unsigned M = MI->getOperand(3).getImm(); |
| 228 | if (B != C) return 0; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 229 | NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 230 | break; |
| 231 | } |
Chris Lattner | 995f550 | 2007-03-28 18:12:31 +0000 | [diff] [blame] | 232 | case X86::SHL64ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 233 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Chris Lattner | 995f550 | 2007-03-28 18:12:31 +0000 | [diff] [blame] | 234 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 235 | // the flags produced by a shift yet, so this is safe. |
| 236 | unsigned Dest = MI->getOperand(0).getReg(); |
| 237 | unsigned Src = MI->getOperand(1).getReg(); |
| 238 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 239 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
| 240 | |
| 241 | NewMI = BuildMI(get(X86::LEA64r), Dest) |
| 242 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 243 | break; |
| 244 | } |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 245 | case X86::SHL32ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 246 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 247 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 248 | // the flags produced by a shift yet, so this is safe. |
| 249 | unsigned Dest = MI->getOperand(0).getReg(); |
| 250 | unsigned Src = MI->getOperand(1).getReg(); |
| 251 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 252 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
| 253 | |
Chris Lattner | f2177b8 | 2007-03-28 00:58:40 +0000 | [diff] [blame] | 254 | unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? |
| 255 | X86::LEA64_32r : X86::LEA32r; |
| 256 | NewMI = BuildMI(get(Opc), Dest) |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 257 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 258 | break; |
| 259 | } |
| 260 | case X86::SHL16ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 261 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 262 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 263 | // the flags produced by a shift yet, so this is safe. |
| 264 | unsigned Dest = MI->getOperand(0).getReg(); |
| 265 | unsigned Src = MI->getOperand(1).getReg(); |
| 266 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 267 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 268 | |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 269 | if (DisableLEA16) { |
| 270 | // If 16-bit LEA is disabled, use 32-bit LEA via subregisters. |
| 271 | SSARegMap *RegMap = MFI->getParent()->getSSARegMap(); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 272 | unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() |
| 273 | ? X86::LEA64_32r : X86::LEA32r; |
| 274 | unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass); |
| 275 | unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 276 | |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 277 | MachineInstr *Ins = |
| 278 | BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 279 | Ins->copyKillDeadInfo(MI); |
| 280 | |
| 281 | NewMI = BuildMI(get(Opc), leaOutReg) |
| 282 | .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0); |
| 283 | |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 284 | MachineInstr *Ext = |
| 285 | BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 286 | Ext->copyKillDeadInfo(MI); |
| 287 | |
| 288 | MFI->insert(MBBI, Ins); // Insert the insert_subreg |
| 289 | LV.instructionChanged(MI, NewMI); // Update live variables |
| 290 | LV.addVirtualRegisterKilled(leaInReg, NewMI); |
| 291 | MFI->insert(MBBI, NewMI); // Insert the new inst |
| 292 | LV.addVirtualRegisterKilled(leaOutReg, Ext); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 293 | MFI->insert(MBBI, Ext); // Insert the extract_subreg |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 294 | return Ext; |
| 295 | } else { |
| 296 | NewMI = BuildMI(get(X86::LEA16r), Dest) |
| 297 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 298 | } |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 299 | break; |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 300 | } |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 301 | default: { |
| 302 | // The following opcodes also sets the condition code register(s). Only |
| 303 | // convert them to equivalent lea if the condition code register def's |
| 304 | // are dead! |
| 305 | if (hasLiveCondCodeDef(MI)) |
| 306 | return 0; |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 307 | |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 308 | bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 309 | switch (MIOpc) { |
| 310 | default: return 0; |
| 311 | case X86::INC64r: |
Evan Cheng | b75ed32 | 2007-10-05 21:55:32 +0000 | [diff] [blame] | 312 | case X86::INC32r: { |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 313 | assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 314 | unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r |
| 315 | : (is64Bit ? X86::LEA64_32r : X86::LEA32r); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 316 | NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1); |
| 317 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 318 | } |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 319 | case X86::INC16r: |
| 320 | case X86::INC64_16r: |
| 321 | if (DisableLEA16) return 0; |
| 322 | assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); |
| 323 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1); |
| 324 | break; |
| 325 | case X86::DEC64r: |
Evan Cheng | b75ed32 | 2007-10-05 21:55:32 +0000 | [diff] [blame] | 326 | case X86::DEC32r: { |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 327 | assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 328 | unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r |
| 329 | : (is64Bit ? X86::LEA64_32r : X86::LEA32r); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 330 | NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1); |
| 331 | break; |
| 332 | } |
| 333 | case X86::DEC16r: |
| 334 | case X86::DEC64_16r: |
| 335 | if (DisableLEA16) return 0; |
| 336 | assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); |
| 337 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1); |
| 338 | break; |
| 339 | case X86::ADD64rr: |
| 340 | case X86::ADD32rr: { |
| 341 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 342 | unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r |
| 343 | : (is64Bit ? X86::LEA64_32r : X86::LEA32r); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 344 | NewMI = addRegReg(BuildMI(get(Opc), Dest), Src, |
| 345 | MI->getOperand(2).getReg()); |
| 346 | break; |
| 347 | } |
| 348 | case X86::ADD16rr: |
| 349 | if (DisableLEA16) return 0; |
| 350 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
| 351 | NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src, |
| 352 | MI->getOperand(2).getReg()); |
| 353 | break; |
| 354 | case X86::ADD64ri32: |
| 355 | case X86::ADD64ri8: |
| 356 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
| 357 | if (MI->getOperand(2).isImmediate()) |
| 358 | NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src, |
| 359 | MI->getOperand(2).getImmedValue()); |
| 360 | break; |
| 361 | case X86::ADD32ri: |
| 362 | case X86::ADD32ri8: |
| 363 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 364 | if (MI->getOperand(2).isImmediate()) { |
| 365 | unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; |
| 366 | NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 367 | MI->getOperand(2).getImmedValue()); |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 368 | } |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 369 | break; |
| 370 | case X86::ADD16ri: |
| 371 | case X86::ADD16ri8: |
| 372 | if (DisableLEA16) return 0; |
| 373 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
| 374 | if (MI->getOperand(2).isImmediate()) |
| 375 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, |
| 376 | MI->getOperand(2).getImmedValue()); |
| 377 | break; |
| 378 | case X86::SHL16ri: |
| 379 | if (DisableLEA16) return 0; |
| 380 | case X86::SHL32ri: |
| 381 | case X86::SHL64ri: { |
| 382 | assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() && |
| 383 | "Unknown shl instruction!"); |
| 384 | unsigned ShAmt = MI->getOperand(2).getImmedValue(); |
| 385 | if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { |
| 386 | X86AddressMode AM; |
| 387 | AM.Scale = 1 << ShAmt; |
| 388 | AM.IndexReg = Src; |
| 389 | unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r |
Evan Cheng | b76143c | 2007-10-09 07:14:53 +0000 | [diff] [blame] | 390 | : (MIOpc == X86::SHL32ri |
| 391 | ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 392 | NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM); |
| 393 | } |
| 394 | break; |
| 395 | } |
| 396 | } |
| 397 | } |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 398 | } |
| 399 | |
Evan Cheng | 559dc46 | 2007-10-05 20:34:26 +0000 | [diff] [blame] | 400 | NewMI->copyKillDeadInfo(MI); |
| 401 | LV.instructionChanged(MI, NewMI); // Update live variables |
| 402 | MFI->insert(MBBI, NewMI); // Insert the new inst |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 403 | return NewMI; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 404 | } |
| 405 | |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 406 | /// commuteInstruction - We have a few instructions that must be hacked on to |
| 407 | /// commute them. |
| 408 | /// |
| 409 | MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { |
| 410 | switch (MI->getOpcode()) { |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 411 | case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) |
| 412 | case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 413 | case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 414 | case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) |
| 415 | case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) |
| 416 | case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 417 | unsigned Opc; |
| 418 | unsigned Size; |
| 419 | switch (MI->getOpcode()) { |
| 420 | default: assert(0 && "Unreachable!"); |
| 421 | case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; |
| 422 | case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; |
| 423 | case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; |
| 424 | case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 425 | case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; |
| 426 | case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 427 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 428 | unsigned Amt = MI->getOperand(3).getImmedValue(); |
| 429 | unsigned A = MI->getOperand(0).getReg(); |
| 430 | unsigned B = MI->getOperand(1).getReg(); |
| 431 | unsigned C = MI->getOperand(2).getReg(); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 432 | bool BisKill = MI->getOperand(1).isKill(); |
| 433 | bool CisKill = MI->getOperand(2).isKill(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 434 | return BuildMI(get(Opc), A).addReg(C, false, false, CisKill) |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 435 | .addReg(B, false, false, BisKill).addImm(Size-Amt); |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 436 | } |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 437 | case X86::CMOVB16rr: |
| 438 | case X86::CMOVB32rr: |
| 439 | case X86::CMOVB64rr: |
| 440 | case X86::CMOVAE16rr: |
| 441 | case X86::CMOVAE32rr: |
| 442 | case X86::CMOVAE64rr: |
| 443 | case X86::CMOVE16rr: |
| 444 | case X86::CMOVE32rr: |
| 445 | case X86::CMOVE64rr: |
| 446 | case X86::CMOVNE16rr: |
| 447 | case X86::CMOVNE32rr: |
| 448 | case X86::CMOVNE64rr: |
| 449 | case X86::CMOVBE16rr: |
| 450 | case X86::CMOVBE32rr: |
| 451 | case X86::CMOVBE64rr: |
| 452 | case X86::CMOVA16rr: |
| 453 | case X86::CMOVA32rr: |
| 454 | case X86::CMOVA64rr: |
| 455 | case X86::CMOVL16rr: |
| 456 | case X86::CMOVL32rr: |
| 457 | case X86::CMOVL64rr: |
| 458 | case X86::CMOVGE16rr: |
| 459 | case X86::CMOVGE32rr: |
| 460 | case X86::CMOVGE64rr: |
| 461 | case X86::CMOVLE16rr: |
| 462 | case X86::CMOVLE32rr: |
| 463 | case X86::CMOVLE64rr: |
| 464 | case X86::CMOVG16rr: |
| 465 | case X86::CMOVG32rr: |
| 466 | case X86::CMOVG64rr: |
| 467 | case X86::CMOVS16rr: |
| 468 | case X86::CMOVS32rr: |
| 469 | case X86::CMOVS64rr: |
| 470 | case X86::CMOVNS16rr: |
| 471 | case X86::CMOVNS32rr: |
| 472 | case X86::CMOVNS64rr: |
| 473 | case X86::CMOVP16rr: |
| 474 | case X86::CMOVP32rr: |
| 475 | case X86::CMOVP64rr: |
| 476 | case X86::CMOVNP16rr: |
| 477 | case X86::CMOVNP32rr: |
| 478 | case X86::CMOVNP64rr: { |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 479 | unsigned Opc = 0; |
| 480 | switch (MI->getOpcode()) { |
| 481 | default: break; |
| 482 | case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; |
| 483 | case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; |
| 484 | case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; |
| 485 | case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; |
| 486 | case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; |
| 487 | case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; |
| 488 | case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; |
| 489 | case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; |
| 490 | case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; |
| 491 | case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; |
| 492 | case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; |
| 493 | case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; |
| 494 | case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; |
| 495 | case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; |
| 496 | case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; |
| 497 | case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; |
| 498 | case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; |
| 499 | case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; |
| 500 | case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; |
| 501 | case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; |
| 502 | case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; |
| 503 | case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; |
| 504 | case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; |
| 505 | case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; |
| 506 | case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; |
| 507 | case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; |
| 508 | case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; |
| 509 | case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; |
| 510 | case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; |
| 511 | case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; |
| 512 | case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; |
| 513 | case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; |
| 514 | case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break; |
| 515 | case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; |
| 516 | case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; |
| 517 | case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; |
| 518 | case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; |
| 519 | case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; |
| 520 | case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break; |
| 521 | case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; |
| 522 | case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; |
| 523 | case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; |
| 524 | } |
| 525 | |
| 526 | MI->setInstrDescriptor(get(Opc)); |
| 527 | // Fallthrough intended. |
| 528 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 529 | default: |
| 530 | return TargetInstrInfo::commuteInstruction(MI); |
| 531 | } |
| 532 | } |
| 533 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 534 | static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { |
| 535 | switch (BrOpc) { |
| 536 | default: return X86::COND_INVALID; |
| 537 | case X86::JE: return X86::COND_E; |
| 538 | case X86::JNE: return X86::COND_NE; |
| 539 | case X86::JL: return X86::COND_L; |
| 540 | case X86::JLE: return X86::COND_LE; |
| 541 | case X86::JG: return X86::COND_G; |
| 542 | case X86::JGE: return X86::COND_GE; |
| 543 | case X86::JB: return X86::COND_B; |
| 544 | case X86::JBE: return X86::COND_BE; |
| 545 | case X86::JA: return X86::COND_A; |
| 546 | case X86::JAE: return X86::COND_AE; |
| 547 | case X86::JS: return X86::COND_S; |
| 548 | case X86::JNS: return X86::COND_NS; |
| 549 | case X86::JP: return X86::COND_P; |
| 550 | case X86::JNP: return X86::COND_NP; |
| 551 | case X86::JO: return X86::COND_O; |
| 552 | case X86::JNO: return X86::COND_NO; |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { |
| 557 | switch (CC) { |
| 558 | default: assert(0 && "Illegal condition code!"); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 559 | case X86::COND_E: return X86::JE; |
| 560 | case X86::COND_NE: return X86::JNE; |
| 561 | case X86::COND_L: return X86::JL; |
| 562 | case X86::COND_LE: return X86::JLE; |
| 563 | case X86::COND_G: return X86::JG; |
| 564 | case X86::COND_GE: return X86::JGE; |
| 565 | case X86::COND_B: return X86::JB; |
| 566 | case X86::COND_BE: return X86::JBE; |
| 567 | case X86::COND_A: return X86::JA; |
| 568 | case X86::COND_AE: return X86::JAE; |
| 569 | case X86::COND_S: return X86::JS; |
| 570 | case X86::COND_NS: return X86::JNS; |
| 571 | case X86::COND_P: return X86::JP; |
| 572 | case X86::COND_NP: return X86::JNP; |
| 573 | case X86::COND_O: return X86::JO; |
| 574 | case X86::COND_NO: return X86::JNO; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 575 | } |
| 576 | } |
| 577 | |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 578 | /// GetOppositeBranchCondition - Return the inverse of the specified condition, |
| 579 | /// e.g. turning COND_E to COND_NE. |
| 580 | X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { |
| 581 | switch (CC) { |
| 582 | default: assert(0 && "Illegal condition code!"); |
| 583 | case X86::COND_E: return X86::COND_NE; |
| 584 | case X86::COND_NE: return X86::COND_E; |
| 585 | case X86::COND_L: return X86::COND_GE; |
| 586 | case X86::COND_LE: return X86::COND_G; |
| 587 | case X86::COND_G: return X86::COND_LE; |
| 588 | case X86::COND_GE: return X86::COND_L; |
| 589 | case X86::COND_B: return X86::COND_AE; |
| 590 | case X86::COND_BE: return X86::COND_A; |
| 591 | case X86::COND_A: return X86::COND_BE; |
| 592 | case X86::COND_AE: return X86::COND_B; |
| 593 | case X86::COND_S: return X86::COND_NS; |
| 594 | case X86::COND_NS: return X86::COND_S; |
| 595 | case X86::COND_P: return X86::COND_NP; |
| 596 | case X86::COND_NP: return X86::COND_P; |
| 597 | case X86::COND_O: return X86::COND_NO; |
| 598 | case X86::COND_NO: return X86::COND_O; |
| 599 | } |
| 600 | } |
| 601 | |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 602 | bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { |
Evan Cheng | 14c4655 | 2007-07-06 23:22:03 +0000 | [diff] [blame] | 603 | const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); |
| 604 | if (TID->Flags & M_TERMINATOR_FLAG) { |
| 605 | // Conditional branch is a special case. |
| 606 | if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0) |
| 607 | return true; |
| 608 | if ((TID->Flags & M_PREDICABLE) == 0) |
| 609 | return true; |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 610 | return !isPredicated(MI); |
Evan Cheng | 14c4655 | 2007-07-06 23:22:03 +0000 | [diff] [blame] | 611 | } |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 612 | return false; |
| 613 | } |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 614 | |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 615 | // For purposes of branch analysis do not count FP_REG_KILL as a terminator. |
| 616 | static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, |
| 617 | const X86InstrInfo &TII) { |
| 618 | if (MI->getOpcode() == X86::FP_REG_KILL) |
| 619 | return false; |
| 620 | return TII.isUnpredicatedTerminator(MI); |
| 621 | } |
| 622 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 623 | bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, |
| 624 | MachineBasicBlock *&TBB, |
| 625 | MachineBasicBlock *&FBB, |
| 626 | std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 627 | // If the block has no terminators, it just falls into the block after it. |
| 628 | MachineBasicBlock::iterator I = MBB.end(); |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 629 | if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 630 | return false; |
| 631 | |
| 632 | // Get the last instruction in the block. |
| 633 | MachineInstr *LastInst = I; |
| 634 | |
| 635 | // If there is only one terminator instruction, process it. |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 636 | if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 637 | if (!isBranch(LastInst->getOpcode())) |
| 638 | return true; |
| 639 | |
| 640 | // If the block ends with a branch there are 3 possibilities: |
| 641 | // it's an unconditional, conditional, or indirect branch. |
| 642 | |
| 643 | if (LastInst->getOpcode() == X86::JMP) { |
| 644 | TBB = LastInst->getOperand(0).getMachineBasicBlock(); |
| 645 | return false; |
| 646 | } |
| 647 | X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); |
| 648 | if (BranchCode == X86::COND_INVALID) |
| 649 | return true; // Can't handle indirect branch. |
| 650 | |
| 651 | // Otherwise, block ends with fall-through condbranch. |
| 652 | TBB = LastInst->getOperand(0).getMachineBasicBlock(); |
| 653 | Cond.push_back(MachineOperand::CreateImm(BranchCode)); |
| 654 | return false; |
| 655 | } |
| 656 | |
| 657 | // Get the instruction before it if it's a terminator. |
| 658 | MachineInstr *SecondLastInst = I; |
| 659 | |
| 660 | // If there are three terminators, we don't know what sort of block this is. |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 661 | if (SecondLastInst && I != MBB.begin() && |
| 662 | isBrAnalysisUnpredicatedTerminator(--I, *this)) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 663 | return true; |
| 664 | |
Chris Lattner | 6ce6443 | 2006-10-30 22:27:23 +0000 | [diff] [blame] | 665 | // If the block ends with X86::JMP and a conditional branch, handle it. |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 666 | X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode()); |
| 667 | if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) { |
Chris Lattner | 6ce6443 | 2006-10-30 22:27:23 +0000 | [diff] [blame] | 668 | TBB = SecondLastInst->getOperand(0).getMachineBasicBlock(); |
| 669 | Cond.push_back(MachineOperand::CreateImm(BranchCode)); |
| 670 | FBB = LastInst->getOperand(0).getMachineBasicBlock(); |
| 671 | return false; |
| 672 | } |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 673 | |
Dale Johannesen | 13e8b51 | 2007-06-13 17:59:52 +0000 | [diff] [blame] | 674 | // If the block ends with two X86::JMPs, handle it. The second one is not |
| 675 | // executed, so remove it. |
| 676 | if (SecondLastInst->getOpcode() == X86::JMP && |
| 677 | LastInst->getOpcode() == X86::JMP) { |
| 678 | TBB = SecondLastInst->getOperand(0).getMachineBasicBlock(); |
| 679 | I = LastInst; |
| 680 | I->eraseFromParent(); |
| 681 | return false; |
| 682 | } |
| 683 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 684 | // Otherwise, can't handle this. |
| 685 | return true; |
| 686 | } |
| 687 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 688 | unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 689 | MachineBasicBlock::iterator I = MBB.end(); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 690 | if (I == MBB.begin()) return 0; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 691 | --I; |
| 692 | if (I->getOpcode() != X86::JMP && |
| 693 | GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 694 | return 0; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 695 | |
| 696 | // Remove the branch. |
| 697 | I->eraseFromParent(); |
| 698 | |
| 699 | I = MBB.end(); |
| 700 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 701 | if (I == MBB.begin()) return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 702 | --I; |
| 703 | if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 704 | return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 705 | |
| 706 | // Remove the branch. |
| 707 | I->eraseFromParent(); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 708 | return 2; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 709 | } |
| 710 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 711 | unsigned |
| 712 | X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 713 | MachineBasicBlock *FBB, |
| 714 | const std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 715 | // Shouldn't be a fall through. |
| 716 | assert(TBB && "InsertBranch must not be told to insert a fallthrough"); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 717 | assert((Cond.size() == 1 || Cond.size() == 0) && |
| 718 | "X86 branch conditions have one component!"); |
| 719 | |
| 720 | if (FBB == 0) { // One way branch. |
| 721 | if (Cond.empty()) { |
| 722 | // Unconditional branch? |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 723 | BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 724 | } else { |
| 725 | // Conditional branch. |
| 726 | unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 727 | BuildMI(&MBB, get(Opc)).addMBB(TBB); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 728 | } |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 729 | return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 730 | } |
| 731 | |
Chris Lattner | 879d09c | 2006-10-21 05:42:09 +0000 | [diff] [blame] | 732 | // Two-way Conditional branch. |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 733 | unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 734 | BuildMI(&MBB, get(Opc)).addMBB(TBB); |
| 735 | BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 736 | return 2; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 737 | } |
| 738 | |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 739 | bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { |
| 740 | if (MBB.empty()) return false; |
| 741 | |
| 742 | switch (MBB.back().getOpcode()) { |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 743 | case X86::TCRETURNri: |
| 744 | case X86::TCRETURNdi: |
Evan Cheng | 126f17a | 2007-05-21 18:44:17 +0000 | [diff] [blame] | 745 | case X86::RET: // Return. |
| 746 | case X86::RETI: |
| 747 | case X86::TAILJMPd: |
| 748 | case X86::TAILJMPr: |
| 749 | case X86::TAILJMPm: |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 750 | case X86::JMP: // Uncond branch. |
| 751 | case X86::JMP32r: // Indirect branch. |
Dan Gohman | a0a7c1d | 2007-09-17 15:19:08 +0000 | [diff] [blame] | 752 | case X86::JMP64r: // Indirect branch (64-bit). |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 753 | case X86::JMP32m: // Indirect branch through mem. |
Dan Gohman | a0a7c1d | 2007-09-17 15:19:08 +0000 | [diff] [blame] | 754 | case X86::JMP64m: // Indirect branch through mem (64-bit). |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 755 | return true; |
| 756 | default: return false; |
| 757 | } |
| 758 | } |
| 759 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 760 | bool X86InstrInfo:: |
| 761 | ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 762 | assert(Cond.size() == 1 && "Invalid X86 branch condition!"); |
| 763 | Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm())); |
| 764 | return false; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 765 | } |
| 766 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 767 | const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { |
| 768 | const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); |
| 769 | if (Subtarget->is64Bit()) |
| 770 | return &X86::GR64RegClass; |
| 771 | else |
| 772 | return &X86::GR32RegClass; |
| 773 | } |