Misha Brukman | cf2b9ac | 2002-11-22 22:43:47 +0000 | [diff] [blame] | 1 | //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 2 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 7 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 9 | // |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 10 | // This file contains the X86 implementation of the MRegisterInfo class. This |
| 11 | // file is responsible for the frame pointer elimination optimization on X86. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 15 | #include "X86.h" |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 16 | #include "X86RegisterInfo.h" |
Misha Brukman | cf2b9ac | 2002-11-22 22:43:47 +0000 | [diff] [blame] | 17 | #include "X86InstrBuilder.h" |
Evan Cheng | e8bd0a3 | 2006-06-06 23:30:24 +0000 | [diff] [blame] | 18 | #include "X86MachineFunctionInfo.h" |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 19 | #include "X86Subtarget.h" |
Evan Cheng | e8bd0a3 | 2006-06-06 23:30:24 +0000 | [diff] [blame] | 20 | #include "X86TargetMachine.h" |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 21 | #include "llvm/Constants.h" |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 22 | #include "llvm/Function.h" |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 23 | #include "llvm/Type.h" |
Chris Lattner | c8c377d | 2003-07-29 05:14:16 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/ValueTypes.h" |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | 198ab64 | 2002-12-15 20:06:35 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineFunction.h" |
Chris Lattner | aa09b75 | 2002-12-28 21:08:28 +0000 | [diff] [blame] | 27 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 28 | #include "llvm/CodeGen/MachineLocation.h" |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/SSARegMap.h" |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 30 | #include "llvm/Target/TargetAsmInfo.h" |
Chris Lattner | f158da2 | 2003-01-16 02:20:12 +0000 | [diff] [blame] | 31 | #include "llvm/Target/TargetFrameInfo.h" |
Evan Cheng | 51cdcd1 | 2006-12-07 01:21:59 +0000 | [diff] [blame] | 32 | #include "llvm/Target/TargetInstrInfo.h" |
Misha Brukman | 83eaa0b | 2004-06-21 21:10:24 +0000 | [diff] [blame] | 33 | #include "llvm/Target/TargetMachine.h" |
Chris Lattner | 0cf0c37 | 2004-07-11 04:17:10 +0000 | [diff] [blame] | 34 | #include "llvm/Target/TargetOptions.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 35 | #include "llvm/Support/CommandLine.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 36 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 37 | #include "llvm/ADT/STLExtras.h" |
Chris Lattner | 300d0ed | 2004-02-14 06:00:36 +0000 | [diff] [blame] | 38 | using namespace llvm; |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 39 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 40 | namespace { |
| 41 | cl::opt<bool> |
Chris Lattner | a7660be | 2004-02-17 06:30:34 +0000 | [diff] [blame] | 42 | NoFusing("disable-spill-fusing", |
| 43 | cl::desc("Disable fusing of spill code into instructions")); |
Chris Lattner | ee0919b | 2004-02-17 08:03:47 +0000 | [diff] [blame] | 44 | cl::opt<bool> |
| 45 | PrintFailedFusing("print-failed-fuse-candidates", |
| 46 | cl::desc("Print instructions that the allocator wants to" |
| 47 | " fuse, but the X86 backend currently can't"), |
| 48 | cl::Hidden); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 49 | } |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 50 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 51 | X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, |
| 52 | const TargetInstrInfo &tii) |
| 53 | : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP), |
| 54 | TM(tm), TII(tii) { |
| 55 | // Cache some information. |
| 56 | const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); |
| 57 | Is64Bit = Subtarget->is64Bit(); |
| 58 | if (Is64Bit) { |
| 59 | SlotSize = 8; |
| 60 | StackPtr = X86::RSP; |
| 61 | FramePtr = X86::RBP; |
| 62 | } else { |
| 63 | SlotSize = 4; |
| 64 | StackPtr = X86::ESP; |
| 65 | FramePtr = X86::EBP; |
| 66 | } |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 67 | |
| 68 | SmallVector<unsigned,16> AmbEntries; |
| 69 | static const unsigned OpTbl2Addr[][2] = { |
| 70 | { X86::ADC32ri, X86::ADC32mi }, |
| 71 | { X86::ADC32ri8, X86::ADC32mi8 }, |
| 72 | { X86::ADC32rr, X86::ADC32mr }, |
| 73 | { X86::ADC64ri32, X86::ADC64mi32 }, |
| 74 | { X86::ADC64ri8, X86::ADC64mi8 }, |
| 75 | { X86::ADC64rr, X86::ADC64mr }, |
| 76 | { X86::ADD16ri, X86::ADD16mi }, |
| 77 | { X86::ADD16ri8, X86::ADD16mi8 }, |
| 78 | { X86::ADD16rr, X86::ADD16mr }, |
| 79 | { X86::ADD32ri, X86::ADD32mi }, |
| 80 | { X86::ADD32ri8, X86::ADD32mi8 }, |
| 81 | { X86::ADD32rr, X86::ADD32mr }, |
| 82 | { X86::ADD64ri32, X86::ADD64mi32 }, |
| 83 | { X86::ADD64ri8, X86::ADD64mi8 }, |
| 84 | { X86::ADD64rr, X86::ADD64mr }, |
| 85 | { X86::ADD8ri, X86::ADD8mi }, |
| 86 | { X86::ADD8rr, X86::ADD8mr }, |
| 87 | { X86::AND16ri, X86::AND16mi }, |
| 88 | { X86::AND16ri8, X86::AND16mi8 }, |
| 89 | { X86::AND16rr, X86::AND16mr }, |
| 90 | { X86::AND32ri, X86::AND32mi }, |
| 91 | { X86::AND32ri8, X86::AND32mi8 }, |
| 92 | { X86::AND32rr, X86::AND32mr }, |
| 93 | { X86::AND64ri32, X86::AND64mi32 }, |
| 94 | { X86::AND64ri8, X86::AND64mi8 }, |
| 95 | { X86::AND64rr, X86::AND64mr }, |
| 96 | { X86::AND8ri, X86::AND8mi }, |
| 97 | { X86::AND8rr, X86::AND8mr }, |
| 98 | { X86::DEC16r, X86::DEC16m }, |
| 99 | { X86::DEC32r, X86::DEC32m }, |
| 100 | { X86::DEC64_16r, X86::DEC16m }, |
| 101 | { X86::DEC64_32r, X86::DEC32m }, |
| 102 | { X86::DEC64r, X86::DEC64m }, |
| 103 | { X86::DEC8r, X86::DEC8m }, |
| 104 | { X86::INC16r, X86::INC16m }, |
| 105 | { X86::INC32r, X86::INC32m }, |
| 106 | { X86::INC64_16r, X86::INC16m }, |
| 107 | { X86::INC64_32r, X86::INC32m }, |
| 108 | { X86::INC64r, X86::INC64m }, |
| 109 | { X86::INC8r, X86::INC8m }, |
| 110 | { X86::NEG16r, X86::NEG16m }, |
| 111 | { X86::NEG32r, X86::NEG32m }, |
| 112 | { X86::NEG64r, X86::NEG64m }, |
| 113 | { X86::NEG8r, X86::NEG8m }, |
| 114 | { X86::NOT16r, X86::NOT16m }, |
| 115 | { X86::NOT32r, X86::NOT32m }, |
| 116 | { X86::NOT64r, X86::NOT64m }, |
| 117 | { X86::NOT8r, X86::NOT8m }, |
| 118 | { X86::OR16ri, X86::OR16mi }, |
| 119 | { X86::OR16ri8, X86::OR16mi8 }, |
| 120 | { X86::OR16rr, X86::OR16mr }, |
| 121 | { X86::OR32ri, X86::OR32mi }, |
| 122 | { X86::OR32ri8, X86::OR32mi8 }, |
| 123 | { X86::OR32rr, X86::OR32mr }, |
| 124 | { X86::OR64ri32, X86::OR64mi32 }, |
| 125 | { X86::OR64ri8, X86::OR64mi8 }, |
| 126 | { X86::OR64rr, X86::OR64mr }, |
| 127 | { X86::OR8ri, X86::OR8mi }, |
| 128 | { X86::OR8rr, X86::OR8mr }, |
| 129 | { X86::ROL16r1, X86::ROL16m1 }, |
| 130 | { X86::ROL16rCL, X86::ROL16mCL }, |
| 131 | { X86::ROL16ri, X86::ROL16mi }, |
| 132 | { X86::ROL32r1, X86::ROL32m1 }, |
| 133 | { X86::ROL32rCL, X86::ROL32mCL }, |
| 134 | { X86::ROL32ri, X86::ROL32mi }, |
| 135 | { X86::ROL64r1, X86::ROL64m1 }, |
| 136 | { X86::ROL64rCL, X86::ROL64mCL }, |
| 137 | { X86::ROL64ri, X86::ROL64mi }, |
| 138 | { X86::ROL8r1, X86::ROL8m1 }, |
| 139 | { X86::ROL8rCL, X86::ROL8mCL }, |
| 140 | { X86::ROL8ri, X86::ROL8mi }, |
| 141 | { X86::ROR16r1, X86::ROR16m1 }, |
| 142 | { X86::ROR16rCL, X86::ROR16mCL }, |
| 143 | { X86::ROR16ri, X86::ROR16mi }, |
| 144 | { X86::ROR32r1, X86::ROR32m1 }, |
| 145 | { X86::ROR32rCL, X86::ROR32mCL }, |
| 146 | { X86::ROR32ri, X86::ROR32mi }, |
| 147 | { X86::ROR64r1, X86::ROR64m1 }, |
| 148 | { X86::ROR64rCL, X86::ROR64mCL }, |
| 149 | { X86::ROR64ri, X86::ROR64mi }, |
| 150 | { X86::ROR8r1, X86::ROR8m1 }, |
| 151 | { X86::ROR8rCL, X86::ROR8mCL }, |
| 152 | { X86::ROR8ri, X86::ROR8mi }, |
| 153 | { X86::SAR16r1, X86::SAR16m1 }, |
| 154 | { X86::SAR16rCL, X86::SAR16mCL }, |
| 155 | { X86::SAR16ri, X86::SAR16mi }, |
| 156 | { X86::SAR32r1, X86::SAR32m1 }, |
| 157 | { X86::SAR32rCL, X86::SAR32mCL }, |
| 158 | { X86::SAR32ri, X86::SAR32mi }, |
| 159 | { X86::SAR64r1, X86::SAR64m1 }, |
| 160 | { X86::SAR64rCL, X86::SAR64mCL }, |
| 161 | { X86::SAR64ri, X86::SAR64mi }, |
| 162 | { X86::SAR8r1, X86::SAR8m1 }, |
| 163 | { X86::SAR8rCL, X86::SAR8mCL }, |
| 164 | { X86::SAR8ri, X86::SAR8mi }, |
| 165 | { X86::SBB32ri, X86::SBB32mi }, |
| 166 | { X86::SBB32ri8, X86::SBB32mi8 }, |
| 167 | { X86::SBB32rr, X86::SBB32mr }, |
| 168 | { X86::SBB64ri32, X86::SBB64mi32 }, |
| 169 | { X86::SBB64ri8, X86::SBB64mi8 }, |
| 170 | { X86::SBB64rr, X86::SBB64mr }, |
| 171 | { X86::SHL16r1, X86::SHL16m1 }, |
| 172 | { X86::SHL16rCL, X86::SHL16mCL }, |
| 173 | { X86::SHL16ri, X86::SHL16mi }, |
| 174 | { X86::SHL32r1, X86::SHL32m1 }, |
| 175 | { X86::SHL32rCL, X86::SHL32mCL }, |
| 176 | { X86::SHL32ri, X86::SHL32mi }, |
| 177 | { X86::SHL64r1, X86::SHL64m1 }, |
| 178 | { X86::SHL64rCL, X86::SHL64mCL }, |
| 179 | { X86::SHL64ri, X86::SHL64mi }, |
| 180 | { X86::SHL8r1, X86::SHL8m1 }, |
| 181 | { X86::SHL8rCL, X86::SHL8mCL }, |
| 182 | { X86::SHL8ri, X86::SHL8mi }, |
| 183 | { X86::SHLD16rrCL, X86::SHLD16mrCL }, |
| 184 | { X86::SHLD16rri8, X86::SHLD16mri8 }, |
| 185 | { X86::SHLD32rrCL, X86::SHLD32mrCL }, |
| 186 | { X86::SHLD32rri8, X86::SHLD32mri8 }, |
| 187 | { X86::SHLD64rrCL, X86::SHLD64mrCL }, |
| 188 | { X86::SHLD64rri8, X86::SHLD64mri8 }, |
| 189 | { X86::SHR16r1, X86::SHR16m1 }, |
| 190 | { X86::SHR16rCL, X86::SHR16mCL }, |
| 191 | { X86::SHR16ri, X86::SHR16mi }, |
| 192 | { X86::SHR32r1, X86::SHR32m1 }, |
| 193 | { X86::SHR32rCL, X86::SHR32mCL }, |
| 194 | { X86::SHR32ri, X86::SHR32mi }, |
| 195 | { X86::SHR64r1, X86::SHR64m1 }, |
| 196 | { X86::SHR64rCL, X86::SHR64mCL }, |
| 197 | { X86::SHR64ri, X86::SHR64mi }, |
| 198 | { X86::SHR8r1, X86::SHR8m1 }, |
| 199 | { X86::SHR8rCL, X86::SHR8mCL }, |
| 200 | { X86::SHR8ri, X86::SHR8mi }, |
| 201 | { X86::SHRD16rrCL, X86::SHRD16mrCL }, |
| 202 | { X86::SHRD16rri8, X86::SHRD16mri8 }, |
| 203 | { X86::SHRD32rrCL, X86::SHRD32mrCL }, |
| 204 | { X86::SHRD32rri8, X86::SHRD32mri8 }, |
| 205 | { X86::SHRD64rrCL, X86::SHRD64mrCL }, |
| 206 | { X86::SHRD64rri8, X86::SHRD64mri8 }, |
| 207 | { X86::SUB16ri, X86::SUB16mi }, |
| 208 | { X86::SUB16ri8, X86::SUB16mi8 }, |
| 209 | { X86::SUB16rr, X86::SUB16mr }, |
| 210 | { X86::SUB32ri, X86::SUB32mi }, |
| 211 | { X86::SUB32ri8, X86::SUB32mi8 }, |
| 212 | { X86::SUB32rr, X86::SUB32mr }, |
| 213 | { X86::SUB64ri32, X86::SUB64mi32 }, |
| 214 | { X86::SUB64ri8, X86::SUB64mi8 }, |
| 215 | { X86::SUB64rr, X86::SUB64mr }, |
| 216 | { X86::SUB8ri, X86::SUB8mi }, |
| 217 | { X86::SUB8rr, X86::SUB8mr }, |
| 218 | { X86::XOR16ri, X86::XOR16mi }, |
| 219 | { X86::XOR16ri8, X86::XOR16mi8 }, |
| 220 | { X86::XOR16rr, X86::XOR16mr }, |
| 221 | { X86::XOR32ri, X86::XOR32mi }, |
| 222 | { X86::XOR32ri8, X86::XOR32mi8 }, |
| 223 | { X86::XOR32rr, X86::XOR32mr }, |
| 224 | { X86::XOR64ri32, X86::XOR64mi32 }, |
| 225 | { X86::XOR64ri8, X86::XOR64mi8 }, |
| 226 | { X86::XOR64rr, X86::XOR64mr }, |
| 227 | { X86::XOR8ri, X86::XOR8mi }, |
| 228 | { X86::XOR8rr, X86::XOR8mr } |
| 229 | }; |
| 230 | |
| 231 | for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { |
| 232 | unsigned RegOp = OpTbl2Addr[i][0]; |
| 233 | unsigned MemOp = OpTbl2Addr[i][1]; |
| 234 | if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 235 | assert(false && "Duplicated entries?"); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 236 | unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store |
| 237 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 238 | std::make_pair(RegOp, AuxInfo)))) |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 239 | AmbEntries.push_back(MemOp); |
| 240 | } |
| 241 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 242 | // If the third value is 1, then it's folding either a load or a store. |
| 243 | static const unsigned OpTbl0[][3] = { |
| 244 | { X86::CALL32r, X86::CALL32m, 1 }, |
| 245 | { X86::CALL64r, X86::CALL64m, 1 }, |
| 246 | { X86::CMP16ri, X86::CMP16mi, 1 }, |
| 247 | { X86::CMP16ri8, X86::CMP16mi8, 1 }, |
| 248 | { X86::CMP32ri, X86::CMP32mi, 1 }, |
| 249 | { X86::CMP32ri8, X86::CMP32mi8, 1 }, |
| 250 | { X86::CMP64ri32, X86::CMP64mi32, 1 }, |
| 251 | { X86::CMP64ri8, X86::CMP64mi8, 1 }, |
| 252 | { X86::CMP8ri, X86::CMP8mi, 1 }, |
| 253 | { X86::DIV16r, X86::DIV16m, 1 }, |
| 254 | { X86::DIV32r, X86::DIV32m, 1 }, |
| 255 | { X86::DIV64r, X86::DIV64m, 1 }, |
| 256 | { X86::DIV8r, X86::DIV8m, 1 }, |
| 257 | { X86::FsMOVAPDrr, X86::MOVSDmr, 0 }, |
| 258 | { X86::FsMOVAPSrr, X86::MOVSSmr, 0 }, |
| 259 | { X86::IDIV16r, X86::IDIV16m, 1 }, |
| 260 | { X86::IDIV32r, X86::IDIV32m, 1 }, |
| 261 | { X86::IDIV64r, X86::IDIV64m, 1 }, |
| 262 | { X86::IDIV8r, X86::IDIV8m, 1 }, |
| 263 | { X86::IMUL16r, X86::IMUL16m, 1 }, |
| 264 | { X86::IMUL32r, X86::IMUL32m, 1 }, |
| 265 | { X86::IMUL64r, X86::IMUL64m, 1 }, |
| 266 | { X86::IMUL8r, X86::IMUL8m, 1 }, |
| 267 | { X86::JMP32r, X86::JMP32m, 1 }, |
| 268 | { X86::JMP64r, X86::JMP64m, 1 }, |
| 269 | { X86::MOV16ri, X86::MOV16mi, 0 }, |
| 270 | { X86::MOV16rr, X86::MOV16mr, 0 }, |
| 271 | { X86::MOV32ri, X86::MOV32mi, 0 }, |
| 272 | { X86::MOV32rr, X86::MOV32mr, 0 }, |
| 273 | { X86::MOV64ri32, X86::MOV64mi32, 0 }, |
| 274 | { X86::MOV64rr, X86::MOV64mr, 0 }, |
| 275 | { X86::MOV8ri, X86::MOV8mi, 0 }, |
| 276 | { X86::MOV8rr, X86::MOV8mr, 0 }, |
| 277 | { X86::MOVAPDrr, X86::MOVAPDmr, 0 }, |
| 278 | { X86::MOVAPSrr, X86::MOVAPSmr, 0 }, |
| 279 | { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 }, |
| 280 | { X86::MOVPQIto64rr,X86::MOVPQIto64mr, 0 }, |
| 281 | { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 }, |
| 282 | { X86::MOVSDrr, X86::MOVSDmr, 0 }, |
| 283 | { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 }, |
| 284 | { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 }, |
| 285 | { X86::MOVSSrr, X86::MOVSSmr, 0 }, |
| 286 | { X86::MOVUPDrr, X86::MOVUPDmr, 0 }, |
| 287 | { X86::MOVUPSrr, X86::MOVUPSmr, 0 }, |
| 288 | { X86::MUL16r, X86::MUL16m, 1 }, |
| 289 | { X86::MUL32r, X86::MUL32m, 1 }, |
| 290 | { X86::MUL64r, X86::MUL64m, 1 }, |
| 291 | { X86::MUL8r, X86::MUL8m, 1 }, |
| 292 | { X86::SETAEr, X86::SETAEm, 0 }, |
| 293 | { X86::SETAr, X86::SETAm, 0 }, |
| 294 | { X86::SETBEr, X86::SETBEm, 0 }, |
| 295 | { X86::SETBr, X86::SETBm, 0 }, |
| 296 | { X86::SETEr, X86::SETEm, 0 }, |
| 297 | { X86::SETGEr, X86::SETGEm, 0 }, |
| 298 | { X86::SETGr, X86::SETGm, 0 }, |
| 299 | { X86::SETLEr, X86::SETLEm, 0 }, |
| 300 | { X86::SETLr, X86::SETLm, 0 }, |
| 301 | { X86::SETNEr, X86::SETNEm, 0 }, |
| 302 | { X86::SETNPr, X86::SETNPm, 0 }, |
| 303 | { X86::SETNSr, X86::SETNSm, 0 }, |
| 304 | { X86::SETPr, X86::SETPm, 0 }, |
| 305 | { X86::SETSr, X86::SETSm, 0 }, |
| 306 | { X86::TAILJMPr, X86::TAILJMPm, 1 }, |
| 307 | { X86::TEST16ri, X86::TEST16mi, 1 }, |
| 308 | { X86::TEST32ri, X86::TEST32mi, 1 }, |
| 309 | { X86::TEST64ri32, X86::TEST64mi32, 1 }, |
| 310 | { X86::TEST8ri, X86::TEST8mi, 1 }, |
| 311 | { X86::XCHG16rr, X86::XCHG16mr, 0 }, |
| 312 | { X86::XCHG32rr, X86::XCHG32mr, 0 }, |
| 313 | { X86::XCHG64rr, X86::XCHG64mr, 0 }, |
| 314 | { X86::XCHG8rr, X86::XCHG8mr, 0 } |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 315 | }; |
| 316 | |
| 317 | for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { |
| 318 | unsigned RegOp = OpTbl0[i][0]; |
| 319 | unsigned MemOp = OpTbl0[i][1]; |
| 320 | if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 321 | assert(false && "Duplicated entries?"); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 322 | unsigned FoldedLoad = OpTbl0[i][2]; |
| 323 | // Index 0, folded load or store. |
| 324 | unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); |
| 325 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 326 | std::make_pair(RegOp, AuxInfo)))) |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 327 | AmbEntries.push_back(MemOp); |
| 328 | } |
| 329 | |
| 330 | static const unsigned OpTbl1[][2] = { |
| 331 | { X86::CMP16rr, X86::CMP16rm }, |
| 332 | { X86::CMP32rr, X86::CMP32rm }, |
| 333 | { X86::CMP64rr, X86::CMP64rm }, |
| 334 | { X86::CMP8rr, X86::CMP8rm }, |
| 335 | { X86::CVTSD2SSrr, X86::CVTSD2SSrm }, |
| 336 | { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm }, |
| 337 | { X86::CVTSI2SDrr, X86::CVTSI2SDrm }, |
| 338 | { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm }, |
| 339 | { X86::CVTSI2SSrr, X86::CVTSI2SSrm }, |
| 340 | { X86::CVTSS2SDrr, X86::CVTSS2SDrm }, |
| 341 | { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm }, |
| 342 | { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm }, |
| 343 | { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm }, |
| 344 | { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm }, |
| 345 | { X86::FsMOVAPDrr, X86::MOVSDrm }, |
| 346 | { X86::FsMOVAPSrr, X86::MOVSSrm }, |
| 347 | { X86::IMUL16rri, X86::IMUL16rmi }, |
| 348 | { X86::IMUL16rri8, X86::IMUL16rmi8 }, |
| 349 | { X86::IMUL32rri, X86::IMUL32rmi }, |
| 350 | { X86::IMUL32rri8, X86::IMUL32rmi8 }, |
| 351 | { X86::IMUL64rri32, X86::IMUL64rmi32 }, |
| 352 | { X86::IMUL64rri8, X86::IMUL64rmi8 }, |
| 353 | { X86::Int_CMPSDrr, X86::Int_CMPSDrm }, |
| 354 | { X86::Int_CMPSSrr, X86::Int_CMPSSrm }, |
| 355 | { X86::Int_COMISDrr, X86::Int_COMISDrm }, |
| 356 | { X86::Int_COMISSrr, X86::Int_COMISSrm }, |
| 357 | { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm }, |
| 358 | { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm }, |
| 359 | { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm }, |
| 360 | { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm }, |
| 361 | { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm }, |
| 362 | { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm }, |
| 363 | { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm }, |
| 364 | { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm }, |
| 365 | { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm }, |
| 366 | { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm }, |
| 367 | { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm }, |
| 368 | { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm }, |
| 369 | { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm }, |
| 370 | { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm }, |
| 371 | { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm }, |
| 372 | { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm }, |
| 373 | { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm }, |
| 374 | { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm }, |
| 375 | { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm }, |
| 376 | { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm }, |
| 377 | { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm }, |
| 378 | { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm }, |
| 379 | { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm }, |
| 380 | { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm }, |
| 381 | { X86::MOV16rr, X86::MOV16rm }, |
| 382 | { X86::MOV32rr, X86::MOV32rm }, |
| 383 | { X86::MOV64rr, X86::MOV64rm }, |
| 384 | { X86::MOV64toPQIrr, X86::MOV64toPQIrm }, |
| 385 | { X86::MOV64toSDrr, X86::MOV64toSDrm }, |
| 386 | { X86::MOV8rr, X86::MOV8rm }, |
| 387 | { X86::MOVAPDrr, X86::MOVAPDrm }, |
| 388 | { X86::MOVAPSrr, X86::MOVAPSrm }, |
| 389 | { X86::MOVDDUPrr, X86::MOVDDUPrm }, |
| 390 | { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm }, |
| 391 | { X86::MOVDI2SSrr, X86::MOVDI2SSrm }, |
| 392 | { X86::MOVSD2PDrr, X86::MOVSD2PDrm }, |
| 393 | { X86::MOVSDrr, X86::MOVSDrm }, |
| 394 | { X86::MOVSHDUPrr, X86::MOVSHDUPrm }, |
| 395 | { X86::MOVSLDUPrr, X86::MOVSLDUPrm }, |
| 396 | { X86::MOVSS2PSrr, X86::MOVSS2PSrm }, |
| 397 | { X86::MOVSSrr, X86::MOVSSrm }, |
| 398 | { X86::MOVSX16rr8, X86::MOVSX16rm8 }, |
| 399 | { X86::MOVSX32rr16, X86::MOVSX32rm16 }, |
| 400 | { X86::MOVSX32rr8, X86::MOVSX32rm8 }, |
| 401 | { X86::MOVSX64rr16, X86::MOVSX64rm16 }, |
| 402 | { X86::MOVSX64rr32, X86::MOVSX64rm32 }, |
| 403 | { X86::MOVSX64rr8, X86::MOVSX64rm8 }, |
| 404 | { X86::MOVUPDrr, X86::MOVUPDrm }, |
| 405 | { X86::MOVUPSrr, X86::MOVUPSrm }, |
| 406 | { X86::MOVZX16rr8, X86::MOVZX16rm8 }, |
| 407 | { X86::MOVZX32rr16, X86::MOVZX32rm16 }, |
| 408 | { X86::MOVZX32rr8, X86::MOVZX32rm8 }, |
| 409 | { X86::MOVZX64rr16, X86::MOVZX64rm16 }, |
| 410 | { X86::MOVZX64rr8, X86::MOVZX64rm8 }, |
| 411 | { X86::PSHUFDri, X86::PSHUFDmi }, |
| 412 | { X86::PSHUFHWri, X86::PSHUFHWmi }, |
| 413 | { X86::PSHUFLWri, X86::PSHUFLWmi }, |
| 414 | { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 }, |
| 415 | { X86::RCPPSr, X86::RCPPSm }, |
| 416 | { X86::RCPPSr_Int, X86::RCPPSm_Int }, |
| 417 | { X86::RSQRTPSr, X86::RSQRTPSm }, |
| 418 | { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int }, |
| 419 | { X86::RSQRTSSr, X86::RSQRTSSm }, |
| 420 | { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int }, |
| 421 | { X86::SQRTPDr, X86::SQRTPDm }, |
| 422 | { X86::SQRTPDr_Int, X86::SQRTPDm_Int }, |
| 423 | { X86::SQRTPSr, X86::SQRTPSm }, |
| 424 | { X86::SQRTPSr_Int, X86::SQRTPSm_Int }, |
| 425 | { X86::SQRTSDr, X86::SQRTSDm }, |
| 426 | { X86::SQRTSDr_Int, X86::SQRTSDm_Int }, |
| 427 | { X86::SQRTSSr, X86::SQRTSSm }, |
| 428 | { X86::SQRTSSr_Int, X86::SQRTSSm_Int }, |
| 429 | { X86::TEST16rr, X86::TEST16rm }, |
| 430 | { X86::TEST32rr, X86::TEST32rm }, |
| 431 | { X86::TEST64rr, X86::TEST64rm }, |
| 432 | { X86::TEST8rr, X86::TEST8rm }, |
| 433 | // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 |
| 434 | { X86::UCOMISDrr, X86::UCOMISDrm }, |
| 435 | { X86::UCOMISSrr, X86::UCOMISSrm }, |
| 436 | { X86::XCHG16rr, X86::XCHG16rm }, |
| 437 | { X86::XCHG32rr, X86::XCHG32rm }, |
| 438 | { X86::XCHG64rr, X86::XCHG64rm }, |
| 439 | { X86::XCHG8rr, X86::XCHG8rm } |
| 440 | }; |
| 441 | |
| 442 | for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { |
| 443 | unsigned RegOp = OpTbl1[i][0]; |
| 444 | unsigned MemOp = OpTbl1[i][1]; |
| 445 | if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 446 | assert(false && "Duplicated entries?"); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 447 | unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load |
| 448 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 449 | std::make_pair(RegOp, AuxInfo)))) |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 450 | AmbEntries.push_back(MemOp); |
| 451 | } |
| 452 | |
| 453 | static const unsigned OpTbl2[][2] = { |
| 454 | { X86::ADC32rr, X86::ADC32rm }, |
| 455 | { X86::ADC64rr, X86::ADC64rm }, |
| 456 | { X86::ADD16rr, X86::ADD16rm }, |
| 457 | { X86::ADD32rr, X86::ADD32rm }, |
| 458 | { X86::ADD64rr, X86::ADD64rm }, |
| 459 | { X86::ADD8rr, X86::ADD8rm }, |
| 460 | { X86::ADDPDrr, X86::ADDPDrm }, |
| 461 | { X86::ADDPSrr, X86::ADDPSrm }, |
| 462 | { X86::ADDSDrr, X86::ADDSDrm }, |
| 463 | { X86::ADDSSrr, X86::ADDSSrm }, |
| 464 | { X86::ADDSUBPDrr, X86::ADDSUBPDrm }, |
| 465 | { X86::ADDSUBPSrr, X86::ADDSUBPSrm }, |
| 466 | { X86::AND16rr, X86::AND16rm }, |
| 467 | { X86::AND32rr, X86::AND32rm }, |
| 468 | { X86::AND64rr, X86::AND64rm }, |
| 469 | { X86::AND8rr, X86::AND8rm }, |
| 470 | { X86::ANDNPDrr, X86::ANDNPDrm }, |
| 471 | { X86::ANDNPSrr, X86::ANDNPSrm }, |
| 472 | { X86::ANDPDrr, X86::ANDPDrm }, |
| 473 | { X86::ANDPSrr, X86::ANDPSrm }, |
| 474 | { X86::CMOVA16rr, X86::CMOVA16rm }, |
| 475 | { X86::CMOVA32rr, X86::CMOVA32rm }, |
| 476 | { X86::CMOVA64rr, X86::CMOVA64rm }, |
| 477 | { X86::CMOVAE16rr, X86::CMOVAE16rm }, |
| 478 | { X86::CMOVAE32rr, X86::CMOVAE32rm }, |
| 479 | { X86::CMOVAE64rr, X86::CMOVAE64rm }, |
| 480 | { X86::CMOVB16rr, X86::CMOVB16rm }, |
| 481 | { X86::CMOVB32rr, X86::CMOVB32rm }, |
| 482 | { X86::CMOVB64rr, X86::CMOVB64rm }, |
| 483 | { X86::CMOVBE16rr, X86::CMOVBE16rm }, |
| 484 | { X86::CMOVBE32rr, X86::CMOVBE32rm }, |
| 485 | { X86::CMOVBE64rr, X86::CMOVBE64rm }, |
| 486 | { X86::CMOVE16rr, X86::CMOVE16rm }, |
| 487 | { X86::CMOVE32rr, X86::CMOVE32rm }, |
| 488 | { X86::CMOVE64rr, X86::CMOVE64rm }, |
| 489 | { X86::CMOVG16rr, X86::CMOVG16rm }, |
| 490 | { X86::CMOVG32rr, X86::CMOVG32rm }, |
| 491 | { X86::CMOVG64rr, X86::CMOVG64rm }, |
| 492 | { X86::CMOVGE16rr, X86::CMOVGE16rm }, |
| 493 | { X86::CMOVGE32rr, X86::CMOVGE32rm }, |
| 494 | { X86::CMOVGE64rr, X86::CMOVGE64rm }, |
| 495 | { X86::CMOVL16rr, X86::CMOVL16rm }, |
| 496 | { X86::CMOVL32rr, X86::CMOVL32rm }, |
| 497 | { X86::CMOVL64rr, X86::CMOVL64rm }, |
| 498 | { X86::CMOVLE16rr, X86::CMOVLE16rm }, |
| 499 | { X86::CMOVLE32rr, X86::CMOVLE32rm }, |
| 500 | { X86::CMOVLE64rr, X86::CMOVLE64rm }, |
| 501 | { X86::CMOVNE16rr, X86::CMOVNE16rm }, |
| 502 | { X86::CMOVNE32rr, X86::CMOVNE32rm }, |
| 503 | { X86::CMOVNE64rr, X86::CMOVNE64rm }, |
| 504 | { X86::CMOVNP16rr, X86::CMOVNP16rm }, |
| 505 | { X86::CMOVNP32rr, X86::CMOVNP32rm }, |
| 506 | { X86::CMOVNP64rr, X86::CMOVNP64rm }, |
| 507 | { X86::CMOVNS16rr, X86::CMOVNS16rm }, |
| 508 | { X86::CMOVNS32rr, X86::CMOVNS32rm }, |
| 509 | { X86::CMOVNS64rr, X86::CMOVNS64rm }, |
| 510 | { X86::CMOVP16rr, X86::CMOVP16rm }, |
| 511 | { X86::CMOVP32rr, X86::CMOVP32rm }, |
| 512 | { X86::CMOVP64rr, X86::CMOVP64rm }, |
| 513 | { X86::CMOVS16rr, X86::CMOVS16rm }, |
| 514 | { X86::CMOVS32rr, X86::CMOVS32rm }, |
| 515 | { X86::CMOVS64rr, X86::CMOVS64rm }, |
| 516 | { X86::CMPPDrri, X86::CMPPDrmi }, |
| 517 | { X86::CMPPSrri, X86::CMPPSrmi }, |
| 518 | { X86::CMPSDrr, X86::CMPSDrm }, |
| 519 | { X86::CMPSSrr, X86::CMPSSrm }, |
| 520 | { X86::DIVPDrr, X86::DIVPDrm }, |
| 521 | { X86::DIVPSrr, X86::DIVPSrm }, |
| 522 | { X86::DIVSDrr, X86::DIVSDrm }, |
| 523 | { X86::DIVSSrr, X86::DIVSSrm }, |
| 524 | { X86::HADDPDrr, X86::HADDPDrm }, |
| 525 | { X86::HADDPSrr, X86::HADDPSrm }, |
| 526 | { X86::HSUBPDrr, X86::HSUBPDrm }, |
| 527 | { X86::HSUBPSrr, X86::HSUBPSrm }, |
| 528 | { X86::IMUL16rr, X86::IMUL16rm }, |
| 529 | { X86::IMUL32rr, X86::IMUL32rm }, |
| 530 | { X86::IMUL64rr, X86::IMUL64rm }, |
| 531 | { X86::MAXPDrr, X86::MAXPDrm }, |
| 532 | { X86::MAXPDrr_Int, X86::MAXPDrm_Int }, |
| 533 | { X86::MAXPSrr, X86::MAXPSrm }, |
| 534 | { X86::MAXPSrr_Int, X86::MAXPSrm_Int }, |
| 535 | { X86::MAXSDrr, X86::MAXSDrm }, |
| 536 | { X86::MAXSDrr_Int, X86::MAXSDrm_Int }, |
| 537 | { X86::MAXSSrr, X86::MAXSSrm }, |
| 538 | { X86::MAXSSrr_Int, X86::MAXSSrm_Int }, |
| 539 | { X86::MINPDrr, X86::MINPDrm }, |
| 540 | { X86::MINPDrr_Int, X86::MINPDrm_Int }, |
| 541 | { X86::MINPSrr, X86::MINPSrm }, |
| 542 | { X86::MINPSrr_Int, X86::MINPSrm_Int }, |
| 543 | { X86::MINSDrr, X86::MINSDrm }, |
| 544 | { X86::MINSDrr_Int, X86::MINSDrm_Int }, |
| 545 | { X86::MINSSrr, X86::MINSSrm }, |
| 546 | { X86::MINSSrr_Int, X86::MINSSrm_Int }, |
| 547 | { X86::MULPDrr, X86::MULPDrm }, |
| 548 | { X86::MULPSrr, X86::MULPSrm }, |
| 549 | { X86::MULSDrr, X86::MULSDrm }, |
| 550 | { X86::MULSSrr, X86::MULSSrm }, |
| 551 | { X86::OR16rr, X86::OR16rm }, |
| 552 | { X86::OR32rr, X86::OR32rm }, |
| 553 | { X86::OR64rr, X86::OR64rm }, |
| 554 | { X86::OR8rr, X86::OR8rm }, |
| 555 | { X86::ORPDrr, X86::ORPDrm }, |
| 556 | { X86::ORPSrr, X86::ORPSrm }, |
| 557 | { X86::PACKSSDWrr, X86::PACKSSDWrm }, |
| 558 | { X86::PACKSSWBrr, X86::PACKSSWBrm }, |
| 559 | { X86::PACKUSWBrr, X86::PACKUSWBrm }, |
| 560 | { X86::PADDBrr, X86::PADDBrm }, |
| 561 | { X86::PADDDrr, X86::PADDDrm }, |
| 562 | { X86::PADDQrr, X86::PADDQrm }, |
| 563 | { X86::PADDSBrr, X86::PADDSBrm }, |
| 564 | { X86::PADDSWrr, X86::PADDSWrm }, |
| 565 | { X86::PADDWrr, X86::PADDWrm }, |
| 566 | { X86::PANDNrr, X86::PANDNrm }, |
| 567 | { X86::PANDrr, X86::PANDrm }, |
| 568 | { X86::PAVGBrr, X86::PAVGBrm }, |
| 569 | { X86::PAVGWrr, X86::PAVGWrm }, |
| 570 | { X86::PCMPEQBrr, X86::PCMPEQBrm }, |
| 571 | { X86::PCMPEQDrr, X86::PCMPEQDrm }, |
| 572 | { X86::PCMPEQWrr, X86::PCMPEQWrm }, |
| 573 | { X86::PCMPGTBrr, X86::PCMPGTBrm }, |
| 574 | { X86::PCMPGTDrr, X86::PCMPGTDrm }, |
| 575 | { X86::PCMPGTWrr, X86::PCMPGTWrm }, |
| 576 | { X86::PINSRWrri, X86::PINSRWrmi }, |
| 577 | { X86::PMADDWDrr, X86::PMADDWDrm }, |
| 578 | { X86::PMAXSWrr, X86::PMAXSWrm }, |
| 579 | { X86::PMAXUBrr, X86::PMAXUBrm }, |
| 580 | { X86::PMINSWrr, X86::PMINSWrm }, |
| 581 | { X86::PMINUBrr, X86::PMINUBrm }, |
| 582 | { X86::PMULHUWrr, X86::PMULHUWrm }, |
| 583 | { X86::PMULHWrr, X86::PMULHWrm }, |
| 584 | { X86::PMULLWrr, X86::PMULLWrm }, |
| 585 | { X86::PMULUDQrr, X86::PMULUDQrm }, |
| 586 | { X86::PORrr, X86::PORrm }, |
| 587 | { X86::PSADBWrr, X86::PSADBWrm }, |
| 588 | { X86::PSLLDrr, X86::PSLLDrm }, |
| 589 | { X86::PSLLQrr, X86::PSLLQrm }, |
| 590 | { X86::PSLLWrr, X86::PSLLWrm }, |
| 591 | { X86::PSRADrr, X86::PSRADrm }, |
| 592 | { X86::PSRAWrr, X86::PSRAWrm }, |
| 593 | { X86::PSRLDrr, X86::PSRLDrm }, |
| 594 | { X86::PSRLQrr, X86::PSRLQrm }, |
| 595 | { X86::PSRLWrr, X86::PSRLWrm }, |
| 596 | { X86::PSUBBrr, X86::PSUBBrm }, |
| 597 | { X86::PSUBDrr, X86::PSUBDrm }, |
| 598 | { X86::PSUBSBrr, X86::PSUBSBrm }, |
| 599 | { X86::PSUBSWrr, X86::PSUBSWrm }, |
| 600 | { X86::PSUBWrr, X86::PSUBWrm }, |
| 601 | { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm }, |
| 602 | { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm }, |
| 603 | { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm }, |
| 604 | { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm }, |
| 605 | { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm }, |
| 606 | { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm }, |
| 607 | { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm }, |
| 608 | { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm }, |
| 609 | { X86::PXORrr, X86::PXORrm }, |
| 610 | { X86::SBB32rr, X86::SBB32rm }, |
| 611 | { X86::SBB64rr, X86::SBB64rm }, |
| 612 | { X86::SHUFPDrri, X86::SHUFPDrmi }, |
| 613 | { X86::SHUFPSrri, X86::SHUFPSrmi }, |
| 614 | { X86::SUB16rr, X86::SUB16rm }, |
| 615 | { X86::SUB32rr, X86::SUB32rm }, |
| 616 | { X86::SUB64rr, X86::SUB64rm }, |
| 617 | { X86::SUB8rr, X86::SUB8rm }, |
| 618 | { X86::SUBPDrr, X86::SUBPDrm }, |
| 619 | { X86::SUBPSrr, X86::SUBPSrm }, |
| 620 | { X86::SUBSDrr, X86::SUBSDrm }, |
| 621 | { X86::SUBSSrr, X86::SUBSSrm }, |
| 622 | // FIXME: TEST*rr -> swapped operand of TEST*mr. |
| 623 | { X86::UNPCKHPDrr, X86::UNPCKHPDrm }, |
| 624 | { X86::UNPCKHPSrr, X86::UNPCKHPSrm }, |
| 625 | { X86::UNPCKLPDrr, X86::UNPCKLPDrm }, |
| 626 | { X86::UNPCKLPSrr, X86::UNPCKLPSrm }, |
| 627 | { X86::XOR16rr, X86::XOR16rm }, |
| 628 | { X86::XOR32rr, X86::XOR32rm }, |
| 629 | { X86::XOR64rr, X86::XOR64rm }, |
| 630 | { X86::XOR8rr, X86::XOR8rm }, |
| 631 | { X86::XORPDrr, X86::XORPDrm }, |
| 632 | { X86::XORPSrr, X86::XORPSrm } |
| 633 | }; |
| 634 | |
| 635 | for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { |
| 636 | unsigned RegOp = OpTbl2[i][0]; |
| 637 | unsigned MemOp = OpTbl2[i][1]; |
| 638 | if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp))) |
| 639 | assert(false && "Duplicated entries?"); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 640 | unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load |
| 641 | if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, |
| 642 | std::make_pair(RegOp, AuxInfo)))) |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 643 | AmbEntries.push_back(MemOp); |
| 644 | } |
| 645 | |
| 646 | // Remove ambiguous entries. |
| 647 | for (unsigned i = 0, e = AmbEntries.size(); i != e; ++i) |
| 648 | MemOp2RegOpTable.erase((unsigned*)AmbEntries[i]); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 649 | } |
Chris Lattner | 7ad3e06 | 2003-08-03 15:48:14 +0000 | [diff] [blame] | 650 | |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 651 | // getX86RegNum - This function maps LLVM register identifiers to their X86 |
| 652 | // specific numbering, which is used in various places encoding instructions. |
| 653 | // |
| 654 | unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { |
| 655 | switch(RegNo) { |
| 656 | case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; |
| 657 | case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; |
| 658 | case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; |
| 659 | case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; |
| 660 | case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: |
| 661 | return N86::ESP; |
| 662 | case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: |
| 663 | return N86::EBP; |
| 664 | case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: |
| 665 | return N86::ESI; |
| 666 | case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: |
| 667 | return N86::EDI; |
| 668 | |
| 669 | case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: |
| 670 | return N86::EAX; |
| 671 | case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: |
| 672 | return N86::ECX; |
| 673 | case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: |
| 674 | return N86::EDX; |
| 675 | case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: |
| 676 | return N86::EBX; |
| 677 | case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: |
| 678 | return N86::ESP; |
| 679 | case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: |
| 680 | return N86::EBP; |
| 681 | case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: |
| 682 | return N86::ESI; |
| 683 | case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: |
| 684 | return N86::EDI; |
| 685 | |
| 686 | case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3: |
| 687 | case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7: |
| 688 | return RegNo-X86::ST0; |
| 689 | |
| 690 | case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: |
| 691 | case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: |
| 692 | return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM0); |
| 693 | case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: |
| 694 | case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: |
| 695 | return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM8); |
| 696 | |
| 697 | default: |
| 698 | assert(isVirtualRegister(RegNo) && "Unknown physical register!"); |
| 699 | assert(0 && "Register allocator hasn't allocated reg correctly yet!"); |
| 700 | return 0; |
| 701 | } |
| 702 | } |
| 703 | |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 704 | bool X86RegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 705 | MachineBasicBlock::iterator MI, |
| 706 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 707 | if (CSI.empty()) |
| 708 | return false; |
| 709 | |
| 710 | MachineFunction &MF = *MBB.getParent(); |
| 711 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
| 712 | X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize); |
| 713 | unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r; |
| 714 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 715 | unsigned Reg = CSI[i-1].getReg(); |
| 716 | // Add the callee-saved register as live-in. It's killed at the spill. |
| 717 | MBB.addLiveIn(Reg); |
| 718 | BuildMI(MBB, MI, TII.get(Opc)).addReg(Reg); |
| 719 | } |
| 720 | return true; |
| 721 | } |
| 722 | |
| 723 | bool X86RegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 724 | MachineBasicBlock::iterator MI, |
| 725 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 726 | if (CSI.empty()) |
| 727 | return false; |
| 728 | |
| 729 | unsigned Opc = Is64Bit ? X86::POP64r : X86::POP32r; |
| 730 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 731 | unsigned Reg = CSI[i].getReg(); |
| 732 | BuildMI(MBB, MI, TII.get(Opc), Reg); |
| 733 | } |
| 734 | return true; |
| 735 | } |
| 736 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 737 | static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB, |
| 738 | MachineOperand &MO) { |
| 739 | if (MO.isRegister()) |
| 740 | MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); |
| 741 | else if (MO.isImmediate()) |
| 742 | MIB = MIB.addImm(MO.getImm()); |
| 743 | else if (MO.isFrameIndex()) |
| 744 | MIB = MIB.addFrameIndex(MO.getFrameIndex()); |
| 745 | else if (MO.isGlobalAddress()) |
| 746 | MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset()); |
| 747 | else if (MO.isConstantPoolIndex()) |
| 748 | MIB = MIB.addConstantPoolIndex(MO.getConstantPoolIndex(), MO.getOffset()); |
| 749 | else if (MO.isJumpTableIndex()) |
| 750 | MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex()); |
| 751 | else if (MO.isExternalSymbol()) |
| 752 | MIB = MIB.addExternalSymbol(MO.getSymbolName()); |
| 753 | else |
| 754 | assert(0 && "Unknown operand for X86InstrAddOperand!"); |
| 755 | |
| 756 | return MIB; |
| 757 | } |
| 758 | |
| 759 | static unsigned getStoreRegOpcode(const TargetRegisterClass *RC) { |
| 760 | unsigned Opc = 0; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 761 | if (RC == &X86::GR64RegClass) { |
| 762 | Opc = X86::MOV64mr; |
| 763 | } else if (RC == &X86::GR32RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 764 | Opc = X86::MOV32mr; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 765 | } else if (RC == &X86::GR16RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 766 | Opc = X86::MOV16mr; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 767 | } else if (RC == &X86::GR8RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 768 | Opc = X86::MOV8mr; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 769 | } else if (RC == &X86::GR32_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 770 | Opc = X86::MOV32_mr; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 771 | } else if (RC == &X86::GR16_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 772 | Opc = X86::MOV16_mr; |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 773 | } else if (RC == &X86::RFP80RegClass) { |
| 774 | Opc = X86::ST_FpP80m; // pops |
Dale Johannesen | ca8035e | 2007-09-17 20:15:38 +0000 | [diff] [blame] | 775 | } else if (RC == &X86::RFP64RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 776 | Opc = X86::ST_Fp64m; |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 777 | } else if (RC == &X86::RFP32RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 778 | Opc = X86::ST_Fp32m; |
Evan Cheng | 19ade3b | 2006-02-16 21:20:26 +0000 | [diff] [blame] | 779 | } else if (RC == &X86::FR32RegClass) { |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 780 | Opc = X86::MOVSSmr; |
Evan Cheng | 19ade3b | 2006-02-16 21:20:26 +0000 | [diff] [blame] | 781 | } else if (RC == &X86::FR64RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 782 | Opc = X86::MOVSDmr; |
Evan Cheng | 2246f84 | 2006-03-18 01:23:20 +0000 | [diff] [blame] | 783 | } else if (RC == &X86::VR128RegClass) { |
Evan Cheng | ed1492e | 2006-04-28 02:23:35 +0000 | [diff] [blame] | 784 | Opc = X86::MOVAPSmr; |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 785 | } else if (RC == &X86::VR64RegClass) { |
Bill Wendling | c9c9d2d | 2007-04-03 06:18:31 +0000 | [diff] [blame] | 786 | Opc = X86::MMX_MOVQ64mr; |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 787 | } else { |
| 788 | assert(0 && "Unknown regclass"); |
| 789 | abort(); |
| 790 | } |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 791 | |
| 792 | return Opc; |
| 793 | } |
| 794 | |
| 795 | void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| 796 | MachineBasicBlock::iterator MI, |
| 797 | unsigned SrcReg, int FrameIdx, |
| 798 | const TargetRegisterClass *RC) const { |
| 799 | unsigned Opc = getStoreRegOpcode(RC); |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 800 | addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx) |
| 801 | .addReg(SrcReg, false, false, true); |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 802 | } |
| 803 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 804 | void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, |
| 805 | SmallVector<MachineOperand,4> Addr, |
| 806 | const TargetRegisterClass *RC, |
| 807 | SmallVector<MachineInstr*,4> &NewMIs) const { |
| 808 | unsigned Opc = getStoreRegOpcode(RC); |
| 809 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc)); |
| 810 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) |
| 811 | MIB = X86InstrAddOperand(MIB, Addr[i]); |
| 812 | MIB.addReg(SrcReg, false, false, true); |
| 813 | NewMIs.push_back(MIB); |
| 814 | } |
| 815 | |
| 816 | static unsigned getLoadRegOpcode(const TargetRegisterClass *RC) { |
| 817 | unsigned Opc = 0; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 818 | if (RC == &X86::GR64RegClass) { |
| 819 | Opc = X86::MOV64rm; |
| 820 | } else if (RC == &X86::GR32RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 821 | Opc = X86::MOV32rm; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 822 | } else if (RC == &X86::GR16RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 823 | Opc = X86::MOV16rm; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 824 | } else if (RC == &X86::GR8RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 825 | Opc = X86::MOV8rm; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 826 | } else if (RC == &X86::GR32_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 827 | Opc = X86::MOV32_rm; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 828 | } else if (RC == &X86::GR16_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 829 | Opc = X86::MOV16_rm; |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 830 | } else if (RC == &X86::RFP80RegClass) { |
| 831 | Opc = X86::LD_Fp80m; |
Dale Johannesen | ca8035e | 2007-09-17 20:15:38 +0000 | [diff] [blame] | 832 | } else if (RC == &X86::RFP64RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 833 | Opc = X86::LD_Fp64m; |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 834 | } else if (RC == &X86::RFP32RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 835 | Opc = X86::LD_Fp32m; |
Evan Cheng | 19ade3b | 2006-02-16 21:20:26 +0000 | [diff] [blame] | 836 | } else if (RC == &X86::FR32RegClass) { |
Nate Begeman | 14e2cf6 | 2005-10-14 22:06:00 +0000 | [diff] [blame] | 837 | Opc = X86::MOVSSrm; |
Evan Cheng | 19ade3b | 2006-02-16 21:20:26 +0000 | [diff] [blame] | 838 | } else if (RC == &X86::FR64RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 839 | Opc = X86::MOVSDrm; |
Evan Cheng | 2246f84 | 2006-03-18 01:23:20 +0000 | [diff] [blame] | 840 | } else if (RC == &X86::VR128RegClass) { |
Evan Cheng | ed1492e | 2006-04-28 02:23:35 +0000 | [diff] [blame] | 841 | Opc = X86::MOVAPSrm; |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 842 | } else if (RC == &X86::VR64RegClass) { |
Bill Wendling | c9c9d2d | 2007-04-03 06:18:31 +0000 | [diff] [blame] | 843 | Opc = X86::MMX_MOVQ64rm; |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 844 | } else { |
| 845 | assert(0 && "Unknown regclass"); |
| 846 | abort(); |
| 847 | } |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 848 | |
| 849 | return Opc; |
| 850 | } |
| 851 | |
| 852 | void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 853 | MachineBasicBlock::iterator MI, |
| 854 | unsigned DestReg, int FrameIdx, |
| 855 | const TargetRegisterClass *RC) const{ |
| 856 | unsigned Opc = getLoadRegOpcode(RC); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 857 | addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx); |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 858 | } |
| 859 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 860 | void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
| 861 | SmallVector<MachineOperand,4> Addr, |
| 862 | const TargetRegisterClass *RC, |
| 863 | SmallVector<MachineInstr*,4> &NewMIs) const { |
| 864 | unsigned Opc = getLoadRegOpcode(RC); |
| 865 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); |
| 866 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) |
| 867 | MIB = X86InstrAddOperand(MIB, Addr[i]); |
| 868 | NewMIs.push_back(MIB); |
| 869 | } |
| 870 | |
Chris Lattner | 01d0efb | 2004-08-15 22:15:11 +0000 | [diff] [blame] | 871 | void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 872 | MachineBasicBlock::iterator MI, |
| 873 | unsigned DestReg, unsigned SrcReg, |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 874 | const TargetRegisterClass *DestRC, |
| 875 | const TargetRegisterClass *SrcRC) const { |
| 876 | if (DestRC != SrcRC) { |
Evan Cheng | ff11026 | 2007-09-26 21:31:07 +0000 | [diff] [blame] | 877 | // Moving EFLAGS to / from another register requires a push and a pop. |
| 878 | if (SrcRC == &X86::CCRRegClass) { |
| 879 | assert(SrcReg == X86::EFLAGS); |
| 880 | if (DestRC == &X86::GR64RegClass) { |
| 881 | BuildMI(MBB, MI, TII.get(X86::PUSHFQ)); |
| 882 | BuildMI(MBB, MI, TII.get(X86::POP64r), DestReg); |
| 883 | return; |
| 884 | } else if (DestRC == &X86::GR32RegClass) { |
| 885 | BuildMI(MBB, MI, TII.get(X86::PUSHFD)); |
| 886 | BuildMI(MBB, MI, TII.get(X86::POP32r), DestReg); |
| 887 | return; |
| 888 | } |
| 889 | } else if (DestRC == &X86::CCRRegClass) { |
| 890 | assert(DestReg == X86::EFLAGS); |
| 891 | if (SrcRC == &X86::GR64RegClass) { |
| 892 | BuildMI(MBB, MI, TII.get(X86::PUSH64r)).addReg(SrcReg); |
| 893 | BuildMI(MBB, MI, TII.get(X86::POPFQ)); |
| 894 | return; |
| 895 | } else if (SrcRC == &X86::GR32RegClass) { |
| 896 | BuildMI(MBB, MI, TII.get(X86::PUSH32r)).addReg(SrcReg); |
| 897 | BuildMI(MBB, MI, TII.get(X86::POPFD)); |
| 898 | return; |
| 899 | } |
| 900 | } |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 901 | cerr << "Not yet supported!"; |
| 902 | abort(); |
| 903 | } |
| 904 | |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 905 | unsigned Opc; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 906 | if (DestRC == &X86::GR64RegClass) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 907 | Opc = X86::MOV64rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 908 | } else if (DestRC == &X86::GR32RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 909 | Opc = X86::MOV32rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 910 | } else if (DestRC == &X86::GR16RegClass) { |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 911 | Opc = X86::MOV16rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 912 | } else if (DestRC == &X86::GR8RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 913 | Opc = X86::MOV8rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 914 | } else if (DestRC == &X86::GR32_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 915 | Opc = X86::MOV32_rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 916 | } else if (DestRC == &X86::GR16_RegClass) { |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 917 | Opc = X86::MOV16_rr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 918 | } else if (DestRC == &X86::RFP32RegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 919 | Opc = X86::MOV_Fp3232; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 920 | } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 921 | Opc = X86::MOV_Fp6464; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 922 | } else if (DestRC == &X86::RFP80RegClass) { |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 923 | Opc = X86::MOV_Fp8080; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 924 | } else if (DestRC == &X86::FR32RegClass) { |
Evan Cheng | fe5cb19 | 2006-02-16 22:45:17 +0000 | [diff] [blame] | 925 | Opc = X86::FsMOVAPSrr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 926 | } else if (DestRC == &X86::FR64RegClass) { |
Evan Cheng | fe5cb19 | 2006-02-16 22:45:17 +0000 | [diff] [blame] | 927 | Opc = X86::FsMOVAPDrr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 928 | } else if (DestRC == &X86::VR128RegClass) { |
Evan Cheng | a964ccd | 2006-04-10 07:21:31 +0000 | [diff] [blame] | 929 | Opc = X86::MOVAPSrr; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 930 | } else if (DestRC == &X86::VR64RegClass) { |
Bill Wendling | c9c9d2d | 2007-04-03 06:18:31 +0000 | [diff] [blame] | 931 | Opc = X86::MMX_MOVQ64rr; |
Chris Lattner | 56bcae0 | 2005-09-30 17:12:38 +0000 | [diff] [blame] | 932 | } else { |
| 933 | assert(0 && "Unknown regclass"); |
| 934 | abort(); |
| 935 | } |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 936 | BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg); |
Misha Brukman | 2b46e8e | 2002-12-13 09:54:12 +0000 | [diff] [blame] | 937 | } |
| 938 | |
Evan Cheng | ff11026 | 2007-09-26 21:31:07 +0000 | [diff] [blame] | 939 | const TargetRegisterClass * |
| 940 | X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { |
| 941 | if (RC == &X86::CCRRegClass) |
Evan Cheng | 3f2d9ec | 2007-09-27 21:50:05 +0000 | [diff] [blame] | 942 | if (Is64Bit) |
| 943 | return &X86::GR64RegClass; |
| 944 | else |
| 945 | return &X86::GR32RegClass; |
Evan Cheng | ff11026 | 2007-09-26 21:31:07 +0000 | [diff] [blame] | 946 | return NULL; |
| 947 | } |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 948 | |
| 949 | void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB, |
| 950 | MachineBasicBlock::iterator I, |
| 951 | unsigned DestReg, |
| 952 | const MachineInstr *Orig) const { |
Evan Cheng | b0869ed | 2007-09-10 20:48:53 +0000 | [diff] [blame] | 953 | // MOV32r0 etc. are implemented with xor which clobbers condition code. |
| 954 | // Re-materialize them as movri instructions to avoid side effects. |
| 955 | switch (Orig->getOpcode()) { |
| 956 | case X86::MOV8r0: |
| 957 | BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0); |
| 958 | break; |
| 959 | case X86::MOV16r0: |
| 960 | BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0); |
| 961 | break; |
| 962 | case X86::MOV32r0: |
| 963 | BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0); |
| 964 | break; |
| 965 | case X86::MOV64r0: |
| 966 | BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0); |
| 967 | break; |
| 968 | default: { |
| 969 | MachineInstr *MI = Orig->clone(); |
| 970 | MI->getOperand(0).setReg(DestReg); |
| 971 | MBB.insert(I, MI); |
| 972 | break; |
| 973 | } |
| 974 | } |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 975 | } |
| 976 | |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 977 | static MachineInstr *FuseTwoAddrInst(unsigned Opcode, |
| 978 | SmallVector<MachineOperand,4> &MOs, |
| 979 | MachineInstr *MI, const TargetInstrInfo &TII) { |
Evan Cheng | 171d09e | 2006-11-10 01:28:43 +0000 | [diff] [blame] | 980 | unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2; |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 981 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 982 | // Create the base instruction with the memory operand as the first part. |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 983 | MachineInstrBuilder MIB = BuildMI(TII.get(Opcode)); |
| 984 | unsigned NumAddrOps = MOs.size(); |
| 985 | for (unsigned i = 0; i != NumAddrOps; ++i) |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 986 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 987 | if (NumAddrOps < 4) // FrameIndex only |
| 988 | MIB.addImm(1).addReg(0).addImm(0); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 989 | |
| 990 | // Loop over the rest of the ri operands, converting them over. |
| 991 | for (unsigned i = 0; i != NumOps; ++i) { |
Evan Cheng | 6f34b43 | 2006-09-08 21:08:13 +0000 | [diff] [blame] | 992 | MachineOperand &MO = MI->getOperand(i+2); |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 993 | MIB = X86InstrAddOperand(MIB, MO); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 994 | } |
| 995 | return MIB; |
Alkis Evlogimenos | 89b0214 | 2004-02-17 08:49:20 +0000 | [diff] [blame] | 996 | } |
| 997 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 998 | static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 999 | SmallVector<MachineOperand,4> &MOs, |
| 1000 | MachineInstr *MI, const TargetInstrInfo &TII) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1001 | MachineInstrBuilder MIB = BuildMI(TII.get(Opcode)); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1002 | |
| 1003 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 1004 | MachineOperand &MO = MI->getOperand(i); |
| 1005 | if (i == OpNo) { |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 1006 | assert(MO.isRegister() && "Expected to fold into reg operand!"); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1007 | unsigned NumAddrOps = MOs.size(); |
| 1008 | for (unsigned i = 0; i != NumAddrOps; ++i) |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1009 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1010 | if (NumAddrOps < 4) // FrameIndex only |
| 1011 | MIB.addImm(1).addReg(0).addImm(0); |
| 1012 | } else { |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1013 | MIB = X86InstrAddOperand(MIB, MO); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1014 | } |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1015 | } |
| 1016 | return MIB; |
Chris Lattner | 7c035b7 | 2004-02-17 05:35:13 +0000 | [diff] [blame] | 1017 | } |
| 1018 | |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1019 | static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, |
| 1020 | SmallVector<MachineOperand,4> &MOs, |
Evan Cheng | 8586b95 | 2006-03-17 02:36:22 +0000 | [diff] [blame] | 1021 | MachineInstr *MI) { |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1022 | MachineInstrBuilder MIB = BuildMI(TII.get(Opcode)); |
| 1023 | |
| 1024 | unsigned NumAddrOps = MOs.size(); |
| 1025 | for (unsigned i = 0; i != NumAddrOps; ++i) |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1026 | MIB = X86InstrAddOperand(MIB, MOs[i]); |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1027 | if (NumAddrOps < 4) // FrameIndex only |
| 1028 | MIB.addImm(1).addReg(0).addImm(0); |
| 1029 | return MIB.addImm(0); |
Evan Cheng | 8586b95 | 2006-03-17 02:36:22 +0000 | [diff] [blame] | 1030 | } |
| 1031 | |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1032 | MachineInstr* |
| 1033 | X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, |
| 1034 | SmallVector<MachineOperand,4> &MOs) const { |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1035 | // Table (and size) to search |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1036 | const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1037 | bool isTwoAddrFold = false; |
Evan Cheng | 171d09e | 2006-11-10 01:28:43 +0000 | [diff] [blame] | 1038 | unsigned NumOps = TII.getNumOperands(MI->getOpcode()); |
| 1039 | bool isTwoAddr = NumOps > 1 && |
Evan Cheng | 51cdcd1 | 2006-12-07 01:21:59 +0000 | [diff] [blame] | 1040 | MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1; |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1041 | |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1042 | MachineInstr *NewMI = NULL; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1043 | // Folding a memory location into the two-address part of a two-address |
| 1044 | // instruction is different than folding it other places. It requires |
| 1045 | // replacing the *two* registers with the memory location. |
Evan Cheng | 171d09e | 2006-11-10 01:28:43 +0000 | [diff] [blame] | 1046 | if (isTwoAddr && NumOps >= 2 && i < 2 && |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 1047 | MI->getOperand(0).isRegister() && |
| 1048 | MI->getOperand(1).isRegister() && |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1049 | MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1050 | OpcodeTablePtr = &RegOp2MemOpTable2Addr; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1051 | isTwoAddrFold = true; |
| 1052 | } else if (i == 0) { // If operand 0 |
| 1053 | if (MI->getOpcode() == X86::MOV16r0) |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1054 | NewMI = MakeM0Inst(TII, X86::MOV16mi, MOs, MI); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1055 | else if (MI->getOpcode() == X86::MOV32r0) |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1056 | NewMI = MakeM0Inst(TII, X86::MOV32mi, MOs, MI); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1057 | else if (MI->getOpcode() == X86::MOV64r0) |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1058 | NewMI = MakeM0Inst(TII, X86::MOV64mi32, MOs, MI); |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1059 | else if (MI->getOpcode() == X86::MOV8r0) |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1060 | NewMI = MakeM0Inst(TII, X86::MOV8mi, MOs, MI); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1061 | if (NewMI) { |
| 1062 | NewMI->copyKillDeadInfo(MI); |
| 1063 | return NewMI; |
| 1064 | } |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1065 | |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1066 | OpcodeTablePtr = &RegOp2MemOpTable0; |
Chris Lattner | 7c035b7 | 2004-02-17 05:35:13 +0000 | [diff] [blame] | 1067 | } else if (i == 1) { |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1068 | OpcodeTablePtr = &RegOp2MemOpTable1; |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1069 | } else if (i == 2) { |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1070 | OpcodeTablePtr = &RegOp2MemOpTable2; |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1071 | } |
| 1072 | |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1073 | // If table selected... |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1074 | if (OpcodeTablePtr) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1075 | // Find the Opcode to fuse |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1076 | DenseMap<unsigned*, unsigned>::iterator I = |
| 1077 | OpcodeTablePtr->find((unsigned*)MI->getOpcode()); |
| 1078 | if (I != OpcodeTablePtr->end()) { |
Chris Lattner | 2926869 | 2006-09-05 02:12:02 +0000 | [diff] [blame] | 1079 | if (isTwoAddrFold) |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1080 | NewMI = FuseTwoAddrInst(I->second, MOs, MI, TII); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1081 | else |
Evan Cheng | 7f3394f | 2007-10-01 23:44:33 +0000 | [diff] [blame] | 1082 | NewMI = FuseInst(I->second, i, MOs, MI, TII); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 1083 | NewMI->copyKillDeadInfo(MI); |
| 1084 | return NewMI; |
Chris Lattner | 7c035b7 | 2004-02-17 05:35:13 +0000 | [diff] [blame] | 1085 | } |
Alkis Evlogimenos | b499866 | 2004-02-17 04:33:18 +0000 | [diff] [blame] | 1086 | } |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1087 | |
| 1088 | // No fusion |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 1089 | if (PrintFailedFusing) |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 1090 | cerr << "We failed to fuse (" |
| 1091 | << ((i == 1) ? "r" : "s") << "): " << *MI; |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 1092 | return NULL; |
Alkis Evlogimenos | b499866 | 2004-02-17 04:33:18 +0000 | [diff] [blame] | 1093 | } |
| 1094 | |
Jim Laskey | f19807c | 2006-07-19 17:53:32 +0000 | [diff] [blame] | 1095 | |
Evan Cheng | f4c3a59 | 2007-08-30 05:54:07 +0000 | [diff] [blame] | 1096 | MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum, |
| 1097 | int FrameIndex) const { |
| 1098 | // Check switch flag |
| 1099 | if (NoFusing) return NULL; |
| 1100 | SmallVector<MachineOperand,4> MOs; |
| 1101 | MOs.push_back(MachineOperand::CreateFrameIndex(FrameIndex)); |
| 1102 | return foldMemoryOperand(MI, OpNum, MOs); |
| 1103 | } |
| 1104 | |
| 1105 | MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum, |
| 1106 | MachineInstr *LoadMI) const { |
| 1107 | // Check switch flag |
| 1108 | if (NoFusing) return NULL; |
| 1109 | SmallVector<MachineOperand,4> MOs; |
| 1110 | unsigned NumOps = TII.getNumOperands(LoadMI->getOpcode()); |
| 1111 | for (unsigned i = NumOps - 4; i != NumOps; ++i) |
| 1112 | MOs.push_back(LoadMI->getOperand(i)); |
| 1113 | return foldMemoryOperand(MI, OpNum, MOs); |
| 1114 | } |
| 1115 | |
Evan Cheng | 75b4e46 | 2007-10-05 01:34:55 +0000 | [diff] [blame] | 1116 | bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, |
| 1117 | SSARegMap *RegMap, |
| 1118 | SmallVector<MachineInstr*, 4> &NewMIs) const { |
| 1119 | DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = |
| 1120 | MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); |
| 1121 | if (I == MemOp2RegOpTable.end()) |
| 1122 | return false; |
| 1123 | unsigned Opc = I->second.first; |
| 1124 | unsigned Index = I->second.second & 0xf; |
| 1125 | bool HasLoad = I->second.second & (1 << 4); |
| 1126 | bool HasStore = I->second.second & (1 << 5); |
| 1127 | const TargetInstrDescriptor &TID = TII.get(Opc); |
| 1128 | const TargetOperandInfo &TOI = TID.OpInfo[Index]; |
| 1129 | const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS) |
| 1130 | ? TII.getPointerRegClass() : getRegClass(TOI.RegClass); |
| 1131 | SmallVector<MachineOperand,4> AddrOps; |
| 1132 | SmallVector<MachineOperand,2> BeforeOps; |
| 1133 | SmallVector<MachineOperand,2> AfterOps; |
| 1134 | SmallVector<MachineOperand,4> ImpOps; |
| 1135 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 1136 | MachineOperand &Op = MI->getOperand(i); |
| 1137 | if (i >= Index && i < Index+4) |
| 1138 | AddrOps.push_back(Op); |
| 1139 | else if (Op.isRegister() && Op.isImplicit()) |
| 1140 | ImpOps.push_back(Op); |
| 1141 | else if (i < Index) |
| 1142 | BeforeOps.push_back(Op); |
| 1143 | else if (i > Index) |
| 1144 | AfterOps.push_back(Op); |
| 1145 | } |
| 1146 | |
| 1147 | // Emit the load instruction. |
| 1148 | unsigned LoadReg = 0; |
| 1149 | if (HasLoad) { |
| 1150 | LoadReg = RegMap->createVirtualRegister(RC); |
| 1151 | loadRegFromAddr(MF, LoadReg, AddrOps, RC, NewMIs); |
| 1152 | if (HasStore) { |
| 1153 | // Address operands cannot be marked isKill. |
| 1154 | for (unsigned i = 1; i != 5; ++i) { |
| 1155 | MachineOperand &MO = NewMIs[0]->getOperand(i); |
| 1156 | if (MO.isRegister()) |
| 1157 | MO.unsetIsKill(); |
| 1158 | } |
| 1159 | } |
| 1160 | } |
| 1161 | |
| 1162 | // Emit the data processing instruction. |
| 1163 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc)); |
| 1164 | unsigned StoreReg = 0; |
| 1165 | const TargetRegisterClass *DstRC = 0; |
| 1166 | if (HasStore) { |
| 1167 | const TargetOperandInfo &DstTOI = TID.OpInfo[0]; |
| 1168 | DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS) |
| 1169 | ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass); |
| 1170 | StoreReg = RegMap->createVirtualRegister(RC); |
| 1171 | MIB.addReg(StoreReg, true); |
| 1172 | } |
| 1173 | for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) |
| 1174 | MIB = X86InstrAddOperand(MIB, BeforeOps[i]); |
| 1175 | if (LoadReg) |
| 1176 | MIB.addReg(LoadReg); |
| 1177 | for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) |
| 1178 | MIB = X86InstrAddOperand(MIB, AfterOps[i]); |
| 1179 | NewMIs.push_back(MIB); |
| 1180 | |
| 1181 | // Emit the store instruction. |
| 1182 | if (HasStore) |
| 1183 | storeRegToAddr(MF, StoreReg, AddrOps, DstRC, NewMIs); |
| 1184 | |
| 1185 | return true; |
| 1186 | } |
| 1187 | |
| 1188 | |
| 1189 | bool |
| 1190 | X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, |
| 1191 | SmallVector<SDNode*, 4> &NewNodes) const { |
| 1192 | if (!N->isTargetOpcode()) |
| 1193 | return false; |
| 1194 | |
| 1195 | DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = |
| 1196 | MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode()); |
| 1197 | if (I == MemOp2RegOpTable.end()) |
| 1198 | return false; |
| 1199 | unsigned Opc = I->second.first; |
| 1200 | unsigned Index = I->second.second & 0xf; |
| 1201 | bool HasLoad = I->second.second & (1 << 4); |
| 1202 | bool HasStore = I->second.second & (1 << 5); |
| 1203 | const TargetInstrDescriptor &TID = TII.get(Opc); |
| 1204 | const TargetOperandInfo &TOI = TID.OpInfo[Index]; |
| 1205 | const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS) |
| 1206 | ? TII.getPointerRegClass() : getRegClass(TOI.RegClass); |
| 1207 | std::vector<SDOperand> AddrOps; |
| 1208 | std::vector<SDOperand> BeforeOps; |
| 1209 | std::vector<SDOperand> AfterOps; |
| 1210 | unsigned NumOps = N->getNumOperands(); |
| 1211 | for (unsigned i = 0; i != NumOps-1; ++i) { |
| 1212 | SDOperand Op = N->getOperand(i); |
| 1213 | if (i >= Index && i < Index+4) |
| 1214 | AddrOps.push_back(Op); |
| 1215 | else if (i < Index) |
| 1216 | BeforeOps.push_back(Op); |
| 1217 | else if (i > Index) |
| 1218 | AfterOps.push_back(Op); |
| 1219 | } |
| 1220 | SDOperand Chain = N->getOperand(NumOps-1); |
| 1221 | AddrOps.push_back(Chain); |
| 1222 | |
| 1223 | // Emit the load instruction. |
| 1224 | SDNode *Load = 0; |
| 1225 | if (HasLoad) { |
| 1226 | MVT::ValueType VT = *RC->vt_begin(); |
| 1227 | Load = DAG.getTargetNode(getLoadRegOpcode(RC), VT, MVT::Other, |
| 1228 | &AddrOps[0], AddrOps.size()); |
| 1229 | NewNodes.push_back(Load); |
| 1230 | } |
| 1231 | |
| 1232 | // Emit the data processing instruction. |
| 1233 | std::vector<MVT::ValueType> VTs; |
| 1234 | const TargetRegisterClass *DstRC = 0; |
| 1235 | if (TID.numDefs > 0) { |
| 1236 | const TargetOperandInfo &DstTOI = TID.OpInfo[0]; |
| 1237 | DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS) |
| 1238 | ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass); |
| 1239 | VTs.push_back(*DstRC->vt_begin()); |
| 1240 | } |
| 1241 | for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { |
| 1242 | MVT::ValueType VT = N->getValueType(i); |
| 1243 | if (VT != MVT::Other && i >= TID.numDefs) |
| 1244 | VTs.push_back(VT); |
| 1245 | } |
| 1246 | if (Load) |
| 1247 | BeforeOps.push_back(SDOperand(Load, 0)); |
| 1248 | std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); |
| 1249 | SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size()); |
| 1250 | NewNodes.push_back(NewNode); |
| 1251 | |
| 1252 | // Emit the store instruction. |
| 1253 | if (HasStore) { |
| 1254 | AddrOps.pop_back(); |
| 1255 | AddrOps.push_back(SDOperand(NewNode, 0)); |
| 1256 | AddrOps.push_back(Chain); |
| 1257 | SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC), |
| 1258 | MVT::Other, &AddrOps[0], AddrOps.size()); |
| 1259 | NewNodes.push_back(Store); |
| 1260 | } |
| 1261 | |
| 1262 | return true; |
| 1263 | } |
| 1264 | |
| 1265 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1266 | const unsigned * |
| 1267 | X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 1268 | static const unsigned CalleeSavedRegs32Bit[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 1269 | X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 |
| 1270 | }; |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1271 | |
| 1272 | static const unsigned CalleeSavedRegs32EHRet[] = { |
| 1273 | X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 |
| 1274 | }; |
| 1275 | |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 1276 | static const unsigned CalleeSavedRegs64Bit[] = { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1277 | X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 |
| 1278 | }; |
| 1279 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1280 | if (Is64Bit) |
| 1281 | return CalleeSavedRegs64Bit; |
| 1282 | else { |
| 1283 | if (MF) { |
| 1284 | MachineFrameInfo *MFI = MF->getFrameInfo(); |
| 1285 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
| 1286 | if (MMI && MMI->callsEHReturn()) |
| 1287 | return CalleeSavedRegs32EHRet; |
| 1288 | } |
| 1289 | return CalleeSavedRegs32Bit; |
| 1290 | } |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 1291 | } |
| 1292 | |
| 1293 | const TargetRegisterClass* const* |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1294 | X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 1295 | static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 1296 | &X86::GR32RegClass, &X86::GR32RegClass, |
| 1297 | &X86::GR32RegClass, &X86::GR32RegClass, 0 |
| 1298 | }; |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1299 | static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = { |
| 1300 | &X86::GR32RegClass, &X86::GR32RegClass, |
| 1301 | &X86::GR32RegClass, &X86::GR32RegClass, |
| 1302 | &X86::GR32RegClass, &X86::GR32RegClass, 0 |
| 1303 | }; |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 1304 | static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1305 | &X86::GR64RegClass, &X86::GR64RegClass, |
| 1306 | &X86::GR64RegClass, &X86::GR64RegClass, |
| 1307 | &X86::GR64RegClass, &X86::GR64RegClass, 0 |
| 1308 | }; |
| 1309 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1310 | if (Is64Bit) |
| 1311 | return CalleeSavedRegClasses64Bit; |
| 1312 | else { |
| 1313 | if (MF) { |
| 1314 | MachineFrameInfo *MFI = MF->getFrameInfo(); |
| 1315 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
| 1316 | if (MMI && MMI->callsEHReturn()) |
| 1317 | return CalleeSavedRegClasses32EHRet; |
| 1318 | } |
| 1319 | return CalleeSavedRegClasses32Bit; |
| 1320 | } |
| 1321 | |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 1322 | } |
| 1323 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 1324 | BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 1325 | BitVector Reserved(getNumRegs()); |
| 1326 | Reserved.set(X86::RSP); |
| 1327 | Reserved.set(X86::ESP); |
| 1328 | Reserved.set(X86::SP); |
| 1329 | Reserved.set(X86::SPL); |
| 1330 | if (hasFP(MF)) { |
| 1331 | Reserved.set(X86::RBP); |
| 1332 | Reserved.set(X86::EBP); |
| 1333 | Reserved.set(X86::BP); |
| 1334 | Reserved.set(X86::BPL); |
| 1335 | } |
| 1336 | return Reserved; |
| 1337 | } |
| 1338 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1339 | //===----------------------------------------------------------------------===// |
| 1340 | // Stack Frame Processing methods |
| 1341 | //===----------------------------------------------------------------------===// |
| 1342 | |
| 1343 | // hasFP - Return true if the specified function should have a dedicated frame |
| 1344 | // pointer register. This is true if the function has variable sized allocas or |
| 1345 | // if frame pointer elimination is disabled. |
| 1346 | // |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 1347 | bool X86RegisterInfo::hasFP(const MachineFunction &MF) const { |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1348 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1349 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
| 1350 | |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 1351 | return (NoFramePointerElim || |
Evan Cheng | 7e7bbf8 | 2007-07-19 00:42:05 +0000 | [diff] [blame] | 1352 | MFI->hasVarSizedObjects() || |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1353 | MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() || |
| 1354 | (MMI && MMI->callsUnwindInit())); |
Misha Brukman | 03c6faf | 2002-12-03 23:11:21 +0000 | [diff] [blame] | 1355 | } |
Misha Brukman | 2adb395 | 2002-12-04 23:57:03 +0000 | [diff] [blame] | 1356 | |
Evan Cheng | 7e7bbf8 | 2007-07-19 00:42:05 +0000 | [diff] [blame] | 1357 | bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { |
| 1358 | return !MF.getFrameInfo()->hasVarSizedObjects(); |
| 1359 | } |
| 1360 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1361 | void X86RegisterInfo:: |
| 1362 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 1363 | MachineBasicBlock::iterator I) const { |
Evan Cheng | 7e7bbf8 | 2007-07-19 00:42:05 +0000 | [diff] [blame] | 1364 | if (!hasReservedCallFrame(MF)) { |
| 1365 | // If the stack pointer can be changed after prologue, turn the |
| 1366 | // adjcallstackup instruction into a 'sub ESP, <amt>' and the |
| 1367 | // adjcallstackdown instruction into 'add ESP, <amt>' |
| 1368 | // TODO: consider using push / pop instead of sub + store / add |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1369 | MachineInstr *Old = I; |
Chris Lattner | 6180780 | 2007-04-25 04:25:10 +0000 | [diff] [blame] | 1370 | uint64_t Amount = Old->getOperand(0).getImm(); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1371 | if (Amount != 0) { |
Chris Lattner | f158da2 | 2003-01-16 02:20:12 +0000 | [diff] [blame] | 1372 | // We need to keep the stack aligned properly. To do this, we round the |
| 1373 | // amount of space needed for the outgoing arguments up to the next |
| 1374 | // alignment boundary. |
Chris Lattner | d029cd2 | 2004-06-02 05:55:25 +0000 | [diff] [blame] | 1375 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
Chris Lattner | f158da2 | 2003-01-16 02:20:12 +0000 | [diff] [blame] | 1376 | Amount = (Amount+Align-1)/Align*Align; |
| 1377 | |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 1378 | MachineInstr *New = 0; |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1379 | if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1380 | New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1381 | .addReg(StackPtr).addImm(Amount); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1382 | } else { |
Jeff Cohen | 00b16889 | 2005-07-27 06:12:32 +0000 | [diff] [blame] | 1383 | assert(Old->getOpcode() == X86::ADJCALLSTACKUP); |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 1384 | // factor out the amount the callee already popped. |
Chris Lattner | 6180780 | 2007-04-25 04:25:10 +0000 | [diff] [blame] | 1385 | uint64_t CalleeAmt = Old->getOperand(1).getImm(); |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 1386 | Amount -= CalleeAmt; |
Chris Lattner | d77525d | 2006-02-03 18:20:04 +0000 | [diff] [blame] | 1387 | if (Amount) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1388 | unsigned Opc = (Amount < 128) ? |
| 1389 | (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : |
| 1390 | (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); |
Jim Laskey | 7ac947d | 2007-01-24 18:50:57 +0000 | [diff] [blame] | 1391 | New = BuildMI(TII.get(Opc), StackPtr) |
| 1392 | .addReg(StackPtr).addImm(Amount); |
Chris Lattner | d77525d | 2006-02-03 18:20:04 +0000 | [diff] [blame] | 1393 | } |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1394 | } |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1395 | |
| 1396 | // Replace the pseudo instruction with a new instruction... |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 1397 | if (New) MBB.insert(I, New); |
| 1398 | } |
| 1399 | } else if (I->getOpcode() == X86::ADJCALLSTACKUP) { |
| 1400 | // If we are performing frame pointer elimination and if the callee pops |
| 1401 | // something off the stack pointer, add it back. We do this until we have |
| 1402 | // more advanced stack pointer tracking ability. |
Chris Lattner | 6180780 | 2007-04-25 04:25:10 +0000 | [diff] [blame] | 1403 | if (uint64_t CalleeAmt = I->getOperand(1).getImm()) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1404 | unsigned Opc = (CalleeAmt < 128) ? |
| 1405 | (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : |
| 1406 | (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); |
Jeff Cohen | 00b16889 | 2005-07-27 06:12:32 +0000 | [diff] [blame] | 1407 | MachineInstr *New = |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1408 | BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt); |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1409 | MBB.insert(I, New); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1410 | } |
| 1411 | } |
| 1412 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1413 | MBB.erase(I); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1414 | } |
| 1415 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 1416 | void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 1417 | int SPAdj, RegScavenger *RS) const{ |
| 1418 | assert(SPAdj == 0 && "Unexpected"); |
| 1419 | |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 1420 | unsigned i = 0; |
Alkis Evlogimenos | c0b9dc5 | 2004-02-12 02:27:10 +0000 | [diff] [blame] | 1421 | MachineInstr &MI = *II; |
Nate Begeman | f8be5e9 | 2004-08-14 22:05:10 +0000 | [diff] [blame] | 1422 | MachineFunction &MF = *MI.getParent()->getParent(); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1423 | while (!MI.getOperand(i).isFrameIndex()) { |
| 1424 | ++i; |
| 1425 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 1426 | } |
| 1427 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1428 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 1429 | // This must be part of a four operand memory reference. Replace the |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1430 | // FrameIndex with base register with EBP. Add an offset to the offset. |
| 1431 | MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false); |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 1432 | |
| 1433 | // Now add the frame object offset to the offset from EBP. |
Chris Lattner | 6180780 | 2007-04-25 04:25:10 +0000 | [diff] [blame] | 1434 | int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + |
| 1435 | MI.getOperand(i+3).getImm()+SlotSize; |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1436 | |
Chris Lattner | d5b7c47 | 2003-10-14 18:52:41 +0000 | [diff] [blame] | 1437 | if (!hasFP(MF)) |
| 1438 | Offset += MF.getFrameInfo()->getStackSize(); |
Chris Lattner | 96c3d2e | 2004-02-15 00:15:37 +0000 | [diff] [blame] | 1439 | else |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1440 | Offset += SlotSize; // Skip the saved EBP |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1441 | |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 1442 | MI.getOperand(i+3).ChangeToImmediate(Offset); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1443 | } |
| 1444 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1445 | void |
| 1446 | X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{ |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1447 | if (hasFP(MF)) { |
| 1448 | // Create a frame entry for the EBP register that must be saved. |
Chris Lattner | 7c6eefa | 2007-04-25 17:23:53 +0000 | [diff] [blame] | 1449 | int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, |
| 1450 | (int)SlotSize * -2); |
Chris Lattner | 96c3d2e | 2004-02-15 00:15:37 +0000 | [diff] [blame] | 1451 | assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && |
| 1452 | "Slot for EBP register must be last in order to be found!"); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1453 | } |
| 1454 | } |
| 1455 | |
Evan Cheng | a24dddd | 2007-04-26 01:09:28 +0000 | [diff] [blame] | 1456 | /// emitSPUpdate - Emit a series of instructions to increment / decrement the |
| 1457 | /// stack pointer by a constant value. |
| 1458 | static |
| 1459 | void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
| 1460 | unsigned StackPtr, int64_t NumBytes, bool Is64Bit, |
| 1461 | const TargetInstrInfo &TII) { |
| 1462 | bool isSub = NumBytes < 0; |
| 1463 | uint64_t Offset = isSub ? -NumBytes : NumBytes; |
| 1464 | unsigned Opc = isSub |
| 1465 | ? ((Offset < 128) ? |
| 1466 | (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : |
| 1467 | (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri)) |
| 1468 | : ((Offset < 128) ? |
| 1469 | (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : |
| 1470 | (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri)); |
| 1471 | uint64_t Chunk = (1LL << 31) - 1; |
| 1472 | |
| 1473 | while (Offset) { |
| 1474 | uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; |
| 1475 | BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal); |
| 1476 | Offset -= ThisVal; |
| 1477 | } |
| 1478 | } |
| 1479 | |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame^] | 1480 | // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator. |
| 1481 | static |
| 1482 | void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
| 1483 | unsigned StackPtr, uint64_t *NumBytes = NULL) { |
| 1484 | if (MBBI != MBB.begin()) { |
| 1485 | MachineBasicBlock::iterator PI = prior(MBBI); |
| 1486 | unsigned Opc = PI->getOpcode(); |
| 1487 | if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || |
| 1488 | Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && |
| 1489 | PI->getOperand(0).getReg() == StackPtr) { |
| 1490 | if (NumBytes) |
| 1491 | *NumBytes += PI->getOperand(2).getImm(); |
| 1492 | MBB.erase(PI); |
| 1493 | } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || |
| 1494 | Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && |
| 1495 | PI->getOperand(0).getReg() == StackPtr) { |
| 1496 | if (NumBytes) |
| 1497 | *NumBytes -= PI->getOperand(2).getImm(); |
| 1498 | MBB.erase(PI); |
| 1499 | } |
| 1500 | } |
| 1501 | } |
| 1502 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1503 | void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { |
Chris Lattner | 198ab64 | 2002-12-15 20:06:35 +0000 | [diff] [blame] | 1504 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
Chris Lattner | eafa423 | 2003-01-15 22:57:35 +0000 | [diff] [blame] | 1505 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 1506 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 1507 | const Function* Fn = MF.getFunction(); |
| 1508 | const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>(); |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1509 | MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1510 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
| 1511 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1512 | |
Jim Laskey | 072200c | 2007-01-29 18:51:14 +0000 | [diff] [blame] | 1513 | // Prepare for frame info. |
Dan Gohman | 5e6e93e | 2007-09-24 16:44:26 +0000 | [diff] [blame] | 1514 | unsigned FrameLabelId = 0; |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1515 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1516 | // Get the number of bytes to allocate from the FrameInfo |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1517 | uint64_t StackSize = MFI->getStackSize(); |
| 1518 | uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); |
Evan Cheng | d9245ca | 2006-04-14 07:26:43 +0000 | [diff] [blame] | 1519 | |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1520 | if (hasFP(MF)) { |
| 1521 | // Get the offset of the stack slot for the EBP register... which is |
| 1522 | // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. |
| 1523 | // Update the frame offset adjustment. |
| 1524 | MFI->setOffsetAdjustment(SlotSize-NumBytes); |
| 1525 | |
| 1526 | // Save EBP into the appropriate stack slot... |
| 1527 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) |
| 1528 | .addReg(FramePtr); |
| 1529 | NumBytes -= SlotSize; |
| 1530 | |
| 1531 | if (MMI && MMI->needsFrameInfo()) { |
| 1532 | // Mark effective beginning of when frame pointer becomes valid. |
| 1533 | FrameLabelId = MMI->NextLabelID(); |
| 1534 | BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId); |
| 1535 | } |
| 1536 | |
| 1537 | // Update EBP with the new base value... |
| 1538 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) |
| 1539 | .addReg(StackPtr); |
| 1540 | } |
| 1541 | |
| 1542 | unsigned ReadyLabelId = 0; |
| 1543 | if (MMI && MMI->needsFrameInfo()) { |
| 1544 | // Mark effective beginning of when frame pointer is ready. |
| 1545 | ReadyLabelId = MMI->NextLabelID(); |
| 1546 | BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId); |
| 1547 | } |
| 1548 | |
| 1549 | // Skip the callee-saved push instructions. |
| 1550 | while (MBBI != MBB.end() && |
| 1551 | (MBBI->getOpcode() == X86::PUSH32r || |
| 1552 | MBBI->getOpcode() == X86::PUSH64r)) |
| 1553 | ++MBBI; |
| 1554 | |
Evan Cheng | d9245ca | 2006-04-14 07:26:43 +0000 | [diff] [blame] | 1555 | if (NumBytes) { // adjust stack pointer: ESP -= numbytes |
Anton Korobeynikov | 317848f | 2007-01-03 11:43:14 +0000 | [diff] [blame] | 1556 | if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) { |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1557 | // Check, whether EAX is livein for this function |
| 1558 | bool isEAXAlive = false; |
| 1559 | for (MachineFunction::livein_iterator II = MF.livein_begin(), |
| 1560 | EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) { |
| 1561 | unsigned Reg = II->first; |
| 1562 | isEAXAlive = (Reg == X86::EAX || Reg == X86::AX || |
| 1563 | Reg == X86::AH || Reg == X86::AL); |
| 1564 | } |
| 1565 | |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1566 | // Function prologue calls _alloca to probe the stack when allocating |
| 1567 | // more than 4k bytes in one go. Touching the stack at 4K increments is |
| 1568 | // necessary to ensure that the guard pages used by the OS virtual memory |
| 1569 | // manager are allocated in correct sequence. |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1570 | if (!isEAXAlive) { |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1571 | BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes); |
| 1572 | BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) |
| 1573 | .addExternalSymbol("_alloca"); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1574 | } else { |
| 1575 | // Save EAX |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1576 | BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1577 | // Allocate NumBytes-4 bytes on stack. We'll also use 4 already |
| 1578 | // allocated bytes for EAX. |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1579 | BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4); |
| 1580 | BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) |
| 1581 | .addExternalSymbol("_alloca"); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1582 | // Restore EAX |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1583 | MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX), |
| 1584 | StackPtr, NumBytes-4); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 1585 | MBB.insert(MBBI, MI); |
| 1586 | } |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1587 | } else { |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame^] | 1588 | // If there is an ADD32ri or SUB32ri of ESP immediately before this |
Evan Cheng | 9b8c674 | 2007-07-17 21:26:42 +0000 | [diff] [blame] | 1589 | // instruction, merge the two instructions. |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame^] | 1590 | mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); |
| 1591 | |
Evan Cheng | 9b8c674 | 2007-07-17 21:26:42 +0000 | [diff] [blame] | 1592 | if (NumBytes) |
| 1593 | emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII); |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1594 | } |
Evan Cheng | d9245ca | 2006-04-14 07:26:43 +0000 | [diff] [blame] | 1595 | } |
| 1596 | |
Jim Laskey | e078d1a | 2007-01-29 23:20:22 +0000 | [diff] [blame] | 1597 | if (MMI && MMI->needsFrameInfo()) { |
Jim Laskey | 44c3b9f | 2007-01-26 21:22:28 +0000 | [diff] [blame] | 1598 | std::vector<MachineMove> &Moves = MMI->getFrameMoves(); |
Dan Gohman | 8248294 | 2007-09-27 23:12:31 +0000 | [diff] [blame] | 1599 | const TargetData *TD = MF.getTarget().getTargetData(); |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1600 | |
| 1601 | // Calculate amount of bytes used for return address storing |
| 1602 | int stackGrowth = |
| 1603 | (MF.getTarget().getFrameInfo()->getStackGrowthDirection() == |
| 1604 | TargetFrameInfo::StackGrowsUp ? |
Dan Gohman | 8248294 | 2007-09-27 23:12:31 +0000 | [diff] [blame] | 1605 | TD->getPointerSize() : -TD->getPointerSize()); |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1606 | |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1607 | if (StackSize) { |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1608 | // Show update of SP. |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1609 | if (hasFP(MF)) { |
| 1610 | // Adjust SP |
| 1611 | MachineLocation SPDst(MachineLocation::VirtualFP); |
| 1612 | MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth); |
| 1613 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
| 1614 | } else { |
| 1615 | MachineLocation SPDst(MachineLocation::VirtualFP); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1616 | MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth); |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1617 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
| 1618 | } |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1619 | } else { |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1620 | //FIXME: Verify & implement for FP |
| 1621 | MachineLocation SPDst(StackPtr); |
| 1622 | MachineLocation SPSrc(StackPtr, stackGrowth); |
| 1623 | Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1624 | } |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1625 | |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1626 | // Add callee saved registers to move list. |
| 1627 | const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); |
Anton Korobeynikov | d97b8cd | 2007-07-24 21:07:39 +0000 | [diff] [blame] | 1628 | |
| 1629 | // FIXME: This is dirty hack. The code itself is pretty mess right now. |
| 1630 | // It should be rewritten from scratch and generalized sometimes. |
| 1631 | |
| 1632 | // Determine maximum offset (minumum due to stack growth) |
| 1633 | int64_t MaxOffset = 0; |
| 1634 | for (unsigned I = 0, E = CSI.size(); I!=E; ++I) |
| 1635 | MaxOffset = std::min(MaxOffset, |
| 1636 | MFI->getObjectOffset(CSI[I].getFrameIdx())); |
| 1637 | |
| 1638 | // Calculate offsets |
| 1639 | for (unsigned I = 0, E = CSI.size(); I!=E; ++I) { |
Chris Lattner | ea84c5e | 2007-04-25 04:30:24 +0000 | [diff] [blame] | 1640 | int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1641 | unsigned Reg = CSI[I].getReg(); |
Anton Korobeynikov | d97b8cd | 2007-07-24 21:07:39 +0000 | [diff] [blame] | 1642 | Offset = (MaxOffset-Offset+3*stackGrowth); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1643 | MachineLocation CSDst(MachineLocation::VirtualFP, Offset); |
| 1644 | MachineLocation CSSrc(Reg); |
| 1645 | Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); |
| 1646 | } |
| 1647 | |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 1648 | if (hasFP(MF)) { |
| 1649 | // Save FP |
| 1650 | MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth); |
| 1651 | MachineLocation FPSrc(FramePtr); |
| 1652 | Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); |
| 1653 | } |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1654 | |
| 1655 | MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr); |
| 1656 | MachineLocation FPSrc(MachineLocation::VirtualFP); |
| 1657 | Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); |
| 1658 | } |
| 1659 | |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 1660 | // If it's main() on Cygwin\Mingw32 we should align stack as well |
| 1661 | if (Fn->hasExternalLinkage() && Fn->getName() == "main" && |
Anton Korobeynikov | 317848f | 2007-01-03 11:43:14 +0000 | [diff] [blame] | 1662 | Subtarget->isTargetCygMing()) { |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1663 | BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP) |
Jim Laskey | 7ac947d | 2007-01-24 18:50:57 +0000 | [diff] [blame] | 1664 | .addReg(X86::ESP).addImm(-Align); |
Evan Cheng | 004fb92 | 2006-06-13 05:14:44 +0000 | [diff] [blame] | 1665 | |
| 1666 | // Probe the stack |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1667 | BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(Align); |
| 1668 | BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca"); |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 1669 | } |
Misha Brukman | 2adb395 | 2002-12-04 23:57:03 +0000 | [diff] [blame] | 1670 | } |
| 1671 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 1672 | void X86RegisterInfo::emitEpilogue(MachineFunction &MF, |
| 1673 | MachineBasicBlock &MBB) const { |
Chris Lattner | aa09b75 | 2002-12-28 21:08:28 +0000 | [diff] [blame] | 1674 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Anton Korobeynikov | 29be848 | 2007-09-26 00:13:34 +0000 | [diff] [blame] | 1675 | const Function* Fn = MF.getFunction(); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1676 | X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); |
Anton Korobeynikov | 29be848 | 2007-09-26 00:13:34 +0000 | [diff] [blame] | 1677 | const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>(); |
Alkis Evlogimenos | f81af21 | 2004-02-14 01:18:34 +0000 | [diff] [blame] | 1678 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1679 | unsigned RetOpcode = MBBI->getOpcode(); |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 1680 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1681 | switch (RetOpcode) { |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 1682 | case X86::RET: |
| 1683 | case X86::RETI: |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1684 | case X86::EH_RETURN: |
Chris Lattner | 2b3d56e | 2005-05-14 23:35:21 +0000 | [diff] [blame] | 1685 | case X86::TAILJMPd: |
| 1686 | case X86::TAILJMPr: |
| 1687 | case X86::TAILJMPm: break; // These are ok |
| 1688 | default: |
| 1689 | assert(0 && "Can only insert epilog into returning blocks"); |
| 1690 | } |
Misha Brukman | 2adb395 | 2002-12-04 23:57:03 +0000 | [diff] [blame] | 1691 | |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1692 | // Get the number of bytes to allocate from the FrameInfo |
| 1693 | uint64_t StackSize = MFI->getStackSize(); |
| 1694 | unsigned CSSize = X86FI->getCalleeSavedFrameSize(); |
| 1695 | uint64_t NumBytes = StackSize - CSSize; |
| 1696 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1697 | if (hasFP(MF)) { |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1698 | // pop EBP. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 1699 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); |
Evan Cheng | 89d1659 | 2007-07-17 07:59:08 +0000 | [diff] [blame] | 1700 | NumBytes -= SlotSize; |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1701 | } |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1702 | |
Evan Cheng | f27795d | 2007-07-17 18:03:34 +0000 | [diff] [blame] | 1703 | // Skip the callee-saved pop instructions. |
| 1704 | while (MBBI != MBB.begin()) { |
Evan Cheng | fcc8793 | 2007-07-26 17:45:41 +0000 | [diff] [blame] | 1705 | MachineBasicBlock::iterator PI = prior(MBBI); |
| 1706 | unsigned Opc = PI->getOpcode(); |
| 1707 | if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc)) |
Evan Cheng | f27795d | 2007-07-17 18:03:34 +0000 | [diff] [blame] | 1708 | break; |
| 1709 | --MBBI; |
| 1710 | } |
| 1711 | |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame^] | 1712 | // If there is an ADD32ri or SUB32ri of ESP immediately before this |
| 1713 | // instruction, merge the two instructions. |
| 1714 | if (NumBytes || MFI->hasVarSizedObjects()) |
| 1715 | mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); |
Evan Cheng | 5b3332c | 2007-07-17 18:40:47 +0000 | [diff] [blame] | 1716 | |
Anton Korobeynikov | 4f1c33f | 2007-10-06 16:17:49 +0000 | [diff] [blame^] | 1717 | // If dynamic alloca is used, then reset esp to point to the last callee-saved |
| 1718 | // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we |
| 1719 | // aligned stack in the prologue, - revert stack changes back. Note: we're |
| 1720 | // assuming, that frame pointer was forced for main() |
Anton Korobeynikov | 29be848 | 2007-09-26 00:13:34 +0000 | [diff] [blame] | 1721 | if (MFI->hasVarSizedObjects() || |
| 1722 | (Fn->hasExternalLinkage() && Fn->getName() == "main" && |
| 1723 | Subtarget->isTargetCygMing())) { |
Evan Cheng | 3c46eef | 2007-07-18 21:26:06 +0000 | [diff] [blame] | 1724 | unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; |
| 1725 | if (CSSize) { |
| 1726 | MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr), |
| 1727 | FramePtr, -CSSize); |
| 1728 | MBB.insert(MBBI, MI); |
| 1729 | } else |
| 1730 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr). |
| 1731 | addReg(FramePtr); |
| 1732 | |
| 1733 | NumBytes = 0; |
| 1734 | } |
| 1735 | |
| 1736 | // adjust stack pointer back: ESP += numbytes |
| 1737 | if (NumBytes) |
| 1738 | emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII); |
| 1739 | |
Evan Cheng | 5b3332c | 2007-07-17 18:40:47 +0000 | [diff] [blame] | 1740 | // We're returning from function via eh_return. |
| 1741 | if (RetOpcode == X86::EH_RETURN) { |
| 1742 | MBBI = prior(MBB.end()); |
| 1743 | MachineOperand &DestAddr = MBBI->getOperand(0); |
Dan Gohman | 92dfe20 | 2007-09-14 20:33:02 +0000 | [diff] [blame] | 1744 | assert(DestAddr.isRegister() && "Offset should be in register!"); |
Evan Cheng | 5b3332c | 2007-07-17 18:40:47 +0000 | [diff] [blame] | 1745 | BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr). |
| 1746 | addReg(DestAddr.getReg()); |
| 1747 | } |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1748 | } |
| 1749 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1750 | unsigned X86RegisterInfo::getRARegister() const { |
Anton Korobeynikov | 038082d | 2007-05-02 08:46:03 +0000 | [diff] [blame] | 1751 | if (Is64Bit) |
| 1752 | return X86::RIP; // Should have dwarf #16 |
| 1753 | else |
| 1754 | return X86::EIP; // Should have dwarf #8 |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 1755 | } |
| 1756 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 1757 | unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1758 | return hasFP(MF) ? FramePtr : StackPtr; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 1759 | } |
| 1760 | |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1761 | void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) |
| 1762 | const { |
Anton Korobeynikov | 0ff3ca4 | 2007-05-12 22:36:25 +0000 | [diff] [blame] | 1763 | // Calculate amount of bytes used for return address storing |
| 1764 | int stackGrowth = (Is64Bit ? -8 : -4); |
| 1765 | |
| 1766 | // Initial state of the frame pointer is esp+4. |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1767 | MachineLocation Dst(MachineLocation::VirtualFP); |
Anton Korobeynikov | 0ff3ca4 | 2007-05-12 22:36:25 +0000 | [diff] [blame] | 1768 | MachineLocation Src(StackPtr, stackGrowth); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1769 | Moves.push_back(MachineMove(0, Dst, Src)); |
Anton Korobeynikov | 0ff3ca4 | 2007-05-12 22:36:25 +0000 | [diff] [blame] | 1770 | |
| 1771 | // Add return address to move list |
| 1772 | MachineLocation CSDst(StackPtr, stackGrowth); |
| 1773 | MachineLocation CSSrc(getRARegister()); |
| 1774 | Moves.push_back(MachineMove(0, CSDst, CSSrc)); |
Jim Laskey | 0e41094 | 2007-01-24 19:15:24 +0000 | [diff] [blame] | 1775 | } |
| 1776 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 1777 | unsigned X86RegisterInfo::getEHExceptionRegister() const { |
| 1778 | assert(0 && "What is the exception register"); |
| 1779 | return 0; |
| 1780 | } |
| 1781 | |
| 1782 | unsigned X86RegisterInfo::getEHHandlerRegister() const { |
| 1783 | assert(0 && "What is the exception handler register"); |
| 1784 | return 0; |
| 1785 | } |
| 1786 | |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1787 | namespace llvm { |
| 1788 | unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) { |
| 1789 | switch (VT) { |
| 1790 | default: return Reg; |
| 1791 | case MVT::i8: |
| 1792 | if (High) { |
| 1793 | switch (Reg) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1794 | default: return 0; |
| 1795 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1796 | return X86::AH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1797 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1798 | return X86::DH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1799 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1800 | return X86::CH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1801 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1802 | return X86::BH; |
| 1803 | } |
| 1804 | } else { |
| 1805 | switch (Reg) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1806 | default: return 0; |
| 1807 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1808 | return X86::AL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1809 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1810 | return X86::DL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1811 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1812 | return X86::CL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1813 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1814 | return X86::BL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1815 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
| 1816 | return X86::SIL; |
| 1817 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
| 1818 | return X86::DIL; |
| 1819 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
| 1820 | return X86::BPL; |
| 1821 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
| 1822 | return X86::SPL; |
| 1823 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 1824 | return X86::R8B; |
| 1825 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 1826 | return X86::R9B; |
| 1827 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 1828 | return X86::R10B; |
| 1829 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 1830 | return X86::R11B; |
| 1831 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 1832 | return X86::R12B; |
| 1833 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 1834 | return X86::R13B; |
| 1835 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 1836 | return X86::R14B; |
| 1837 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 1838 | return X86::R15B; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1839 | } |
| 1840 | } |
| 1841 | case MVT::i16: |
| 1842 | switch (Reg) { |
| 1843 | default: return Reg; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1844 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1845 | return X86::AX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1846 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1847 | return X86::DX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1848 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1849 | return X86::CX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1850 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1851 | return X86::BX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1852 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1853 | return X86::SI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1854 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1855 | return X86::DI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1856 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1857 | return X86::BP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1858 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1859 | return X86::SP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1860 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 1861 | return X86::R8W; |
| 1862 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 1863 | return X86::R9W; |
| 1864 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 1865 | return X86::R10W; |
| 1866 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 1867 | return X86::R11W; |
| 1868 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 1869 | return X86::R12W; |
| 1870 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 1871 | return X86::R13W; |
| 1872 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 1873 | return X86::R14W; |
| 1874 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 1875 | return X86::R15W; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1876 | } |
| 1877 | case MVT::i32: |
| 1878 | switch (Reg) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1879 | default: return Reg; |
| 1880 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1881 | return X86::EAX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1882 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1883 | return X86::EDX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1884 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1885 | return X86::ECX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1886 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1887 | return X86::EBX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1888 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1889 | return X86::ESI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1890 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1891 | return X86::EDI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1892 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1893 | return X86::EBP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1894 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1895 | return X86::ESP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1896 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 1897 | return X86::R8D; |
| 1898 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 1899 | return X86::R9D; |
| 1900 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 1901 | return X86::R10D; |
| 1902 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 1903 | return X86::R11D; |
| 1904 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 1905 | return X86::R12D; |
| 1906 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 1907 | return X86::R13D; |
| 1908 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 1909 | return X86::R14D; |
| 1910 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 1911 | return X86::R15D; |
| 1912 | } |
| 1913 | case MVT::i64: |
| 1914 | switch (Reg) { |
| 1915 | default: return Reg; |
| 1916 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
| 1917 | return X86::RAX; |
| 1918 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
| 1919 | return X86::RDX; |
| 1920 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
| 1921 | return X86::RCX; |
| 1922 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
| 1923 | return X86::RBX; |
| 1924 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
| 1925 | return X86::RSI; |
| 1926 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
| 1927 | return X86::RDI; |
| 1928 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
| 1929 | return X86::RBP; |
| 1930 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
| 1931 | return X86::RSP; |
| 1932 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 1933 | return X86::R8; |
| 1934 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 1935 | return X86::R9; |
| 1936 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 1937 | return X86::R10; |
| 1938 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 1939 | return X86::R11; |
| 1940 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 1941 | return X86::R12; |
| 1942 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 1943 | return X86::R13; |
| 1944 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 1945 | return X86::R14; |
| 1946 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 1947 | return X86::R15; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 1948 | } |
| 1949 | } |
| 1950 | |
| 1951 | return Reg; |
| 1952 | } |
| 1953 | } |
| 1954 | |
Chris Lattner | 7ad3e06 | 2003-08-03 15:48:14 +0000 | [diff] [blame] | 1955 | #include "X86GenRegisterInfo.inc" |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 1956 | |