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gerrit-public.fairphone.software / platform / external / llvm / 6b13cd415493187b4c597fc1a60fae314067cdb2 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 40d69e9ff5016b96c99be45dbcc8906079adc76b [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
12#include "ARMDisassembler.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]13#include "ARM.h"
14#include "ARMRegisterInfo.h"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]21#include "llvm/Support/Debug.h"
22#include "llvm/Support/MemoryObject.h"
23#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]24#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]25#include "llvm/Support/raw_ostream.h"
26
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]27using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29static bool Check(MCDisassembler::DecodeStatus &Out, MCDisassembler::DecodeStatus In) {
30 switch (In) {
31 case MCDisassembler::Success:
32 // Out stays the same.
33 return true;
34 case MCDisassembler::SoftFail:
35 Out = In;
36 return true;
37 case MCDisassembler::Fail:
38 Out = In;
39 return false;
40 }
41 return false;
42}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]43
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]44// Forward declare these because the autogenerated code will reference them.
45// Definitions are further down.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]46static MCDisassembler::DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]47 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]48static MCDisassembler::DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]49 unsigned RegNo, uint64_t Address,
50 const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]51static MCDisassembler::DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]52 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]53static MCDisassembler::DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]54 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]55static MCDisassembler::DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]56 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]57static MCDisassembler::DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]58 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]59static MCDisassembler::DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]60 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]61static MCDisassembler::DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]62 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]63static MCDisassembler::DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]64 unsigned RegNo,
65 uint64_t Address,
66 const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]67static MCDisassembler::DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]68 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]69
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]70static MCDisassembler::DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]71 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]72static MCDisassembler::DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]73 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]74static MCDisassembler::DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]75 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]76static MCDisassembler::DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]77 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]78static MCDisassembler::DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]79 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]80static MCDisassembler::DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]81 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]82
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]83static MCDisassembler::DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]84 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]85static MCDisassembler::DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]86 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]87static MCDisassembler::DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]88 unsigned Insn,
89 uint64_t Address,
90 const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]91static MCDisassembler::DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]92 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]93static MCDisassembler::DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]94 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]95static MCDisassembler::DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]96 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]97static MCDisassembler::DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]98 uint64_t Address, const void *Decoder);
99
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]100static MCDisassembler::DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]101 unsigned Insn,
102 uint64_t Adddress,
103 const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]104static MCDisassembler::DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]105 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]106static MCDisassembler::DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]108static MCDisassembler::DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]109 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]110static MCDisassembler::DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]112static MCDisassembler::DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]114static MCDisassembler::DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]116static MCDisassembler::DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]118static MCDisassembler::DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]120static MCDisassembler::DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]122static MCDisassembler::DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]123 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]124static MCDisassembler::DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]125 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]126static MCDisassembler::DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]128static MCDisassembler::DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]129 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]130static MCDisassembler::DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]132static MCDisassembler::DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]134static MCDisassembler::DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]136static MCDisassembler::DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]138static MCDisassembler::DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]140static MCDisassembler::DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]142static MCDisassembler::DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]144static MCDisassembler::DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]146static MCDisassembler::DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]147 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]148static MCDisassembler::DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]149 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]150static MCDisassembler::DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]152static MCDisassembler::DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]154static MCDisassembler::DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]156static MCDisassembler::DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]158static MCDisassembler::DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]159 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]160static MCDisassembler::DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]161 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]162static MCDisassembler::DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]163 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]164static MCDisassembler::DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]165 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]166static MCDisassembler::DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]167 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]168static MCDisassembler::DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]170static MCDisassembler::DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]172static MCDisassembler::DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]174static MCDisassembler::DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]176static MCDisassembler::DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]178static MCDisassembler::DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]180static MCDisassembler::DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]182static MCDisassembler::DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]184static MCDisassembler::DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]186static MCDisassembler::DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]188static MCDisassembler::DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]191static MCDisassembler::DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]193static MCDisassembler::DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]195static MCDisassembler::DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]197static MCDisassembler::DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]199static MCDisassembler::DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]201static MCDisassembler::DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]203static MCDisassembler::DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]205static MCDisassembler::DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]207static MCDisassembler::DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]209static MCDisassembler::DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]211static MCDisassembler::DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]213static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]215static MCDisassembler::DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]217static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]219static MCDisassembler::DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]221static MCDisassembler::DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]223static MCDisassembler::DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]225static MCDisassembler::DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]227static MCDisassembler::DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]229static MCDisassembler::DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]231static MCDisassembler::DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]233static MCDisassembler::DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]235static MCDisassembler::DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]237static MCDisassembler::DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]239
240#include "ARMGenDisassemblerTables.inc"
241#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]242#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]243
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]244static MCDisassembler *createARMDisassembler(const Target &T) {
245 return new ARMDisassembler;
246}
247
248static MCDisassembler *createThumbDisassembler(const Target &T) {
249 return new ThumbDisassembler;
250}
251
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]252EDInstInfo *ARMDisassembler::getEDInfo() const {
253 return instInfoARM;
254}
255
256EDInstInfo *ThumbDisassembler::getEDInfo() const {
257 return instInfoARM;
258}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]260MCDisassembler::DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]261 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]262 uint64_t Address,
263 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint8_t bytes[4];
265
266 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]267 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
268 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]269 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]270 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271
272 // Encoded as a small-endian 32-bit word in the stream.
273 uint32_t insn = (bytes[3] << 24) |
274 (bytes[2] << 16) |
275 (bytes[1] << 8) |
276 (bytes[0] << 0);
277
278 // Calling the auto-generated decoder function.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]279 MCDisassembler::DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
280 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]282 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 }
284
285 // Instructions that are shared between ARM and Thumb modes.
286 // FIXME: This shouldn't really exist. It's an artifact of the
287 // fact that we fail to encode a few instructions properly for Thumb.
288 MI.clear();
289 result = decodeCommonInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]290 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]292 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 }
294
295 // VFP and NEON instructions, similarly, are shared between ARM
296 // and Thumb modes.
297 MI.clear();
298 result = decodeVFPInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]299 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]301 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 }
303
304 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]305 result = decodeNEONDataInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]306 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]307 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]308 // Add a fake predicate operand, because we share these instruction
309 // definitions with Thumb2 where these instructions are predicable.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]310 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]311 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]312 }
313
314 MI.clear();
315 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]316 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]317 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]318 // Add a fake predicate operand, because we share these instruction
319 // definitions with Thumb2 where these instructions are predicable.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]320 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]321 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]322 }
323
324 MI.clear();
325 result = decodeNEONDupInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]326 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]327 Size = 4;
328 // Add a fake predicate operand, because we share these instruction
329 // definitions with Thumb2 where these instructions are predicable.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]330 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]331 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]332 }
333
334 MI.clear();
335
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]336 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]337 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]338}
339
340namespace llvm {
341extern MCInstrDesc ARMInsts[];
342}
343
344// Thumb1 instructions don't have explicit S bits. Rather, they
345// implicitly set CPSR. Since it's not represented in the encoding, the
346// auto-generated decoder won't inject the CPSR operand. We need to fix
347// that as a post-pass.
348static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
349 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]350 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]351 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]352 for (unsigned i = 0; i < NumOps; ++i, ++I) {
353 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]354 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]355 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]356 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
357 return;
358 }
359 }
360
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]361 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]362}
363
364// Most Thumb instructions don't have explicit predicates in the
365// encoding, but rather get their predicates from IT context. We need
366// to fix up the predicate operands using this context information as a
367// post-pass.
368void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
369 // A few instructions actually have predicates encoded in them. Don't
370 // try to overwrite it if we're seeing one of those.
371 switch (MI.getOpcode()) {
372 case ARM::tBcc:
373 case ARM::t2Bcc:
374 return;
375 default:
376 break;
377 }
378
379 // If we're in an IT block, base the predicate on that. Otherwise,
380 // assume a predicate of AL.
381 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]382 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]383 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]384 if (CC == 0xF)
385 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]386 ITBlock.pop_back();
387 } else
388 CC = ARMCC::AL;
389
390 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]391 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]392 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]393 for (unsigned i = 0; i < NumOps; ++i, ++I) {
394 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]395 if (OpInfo[i].isPredicate()) {
396 I = MI.insert(I, MCOperand::CreateImm(CC));
397 ++I;
398 if (CC == ARMCC::AL)
399 MI.insert(I, MCOperand::CreateReg(0));
400 else
401 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
402 return;
403 }
404 }
405
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]406 I = MI.insert(I, MCOperand::CreateImm(CC));
407 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]408 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]409 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]410 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]411 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]412}
413
414// Thumb VFP instructions are a special case. Because we share their
415// encodings between ARM and Thumb modes, and they are predicable in ARM
416// mode, the auto-generated decoder will give them an (incorrect)
417// predicate operand. We need to rewrite these operands based on the IT
418// context as a post-pass.
419void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
420 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]421 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]422 CC = ITBlock.back();
423 ITBlock.pop_back();
424 } else
425 CC = ARMCC::AL;
426
427 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
428 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]429 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
430 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]431 if (OpInfo[i].isPredicate() ) {
432 I->setImm(CC);
433 ++I;
434 if (CC == ARMCC::AL)
435 I->setReg(0);
436 else
437 I->setReg(ARM::CPSR);
438 return;
439 }
440 }
441}
442
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]443MCDisassembler::DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]444 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]445 uint64_t Address,
446 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]447 uint8_t bytes[4];
448
449 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]450 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
451 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]452 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]453 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]454
455 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]456 MCDisassembler::DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
457 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]458 Size = 2;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]459 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]460 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]461 }
462
463 MI.clear();
464 result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
465 if (result) {
466 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]467 bool InITBlock = !ITBlock.empty();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]468 AddThumbPredicate(MI);
469 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]470 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]471 }
472
473 MI.clear();
474 result = decodeThumb2Instruction16(MI, insn16, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]475 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]476 Size = 2;
477 AddThumbPredicate(MI);
478
479 // If we find an IT instruction, we need to parse its condition
480 // code and mask operands so that we can apply them correctly
481 // to the subsequent instructions.
482 if (MI.getOpcode() == ARM::t2IT) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]483 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]484 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]485 unsigned Mask = MI.getOperand(1).getImm();
486 unsigned CondBit0 = Mask >> 4 & 1;
487 unsigned NumTZ = CountTrailingZeros_32(Mask);
488 assert(NumTZ <= 3 && "Invalid IT mask!");
489 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
490 bool T = ((Mask >> Pos) & 1) == CondBit0;
491 if (T)
492 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]493 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]494 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]495 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]496
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]497 ITBlock.push_back(firstcond);
498 }
499
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]500 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]501 }
502
503 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]504 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
505 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]506 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]507 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]508
509 uint32_t insn32 = (bytes[3] << 8) |
510 (bytes[2] << 0) |
511 (bytes[1] << 24) |
512 (bytes[0] << 16);
513 MI.clear();
514 result = decodeThumbInstruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]515 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]516 Size = 4;
517 bool InITBlock = ITBlock.size();
518 AddThumbPredicate(MI);
519 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]520 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]521 }
522
523 MI.clear();
524 result = decodeThumb2Instruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]525 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]526 Size = 4;
527 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]528 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]529 }
530
531 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]532 result = decodeCommonInstruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]533 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]534 Size = 4;
535 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]536 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]537 }
538
539 MI.clear();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]540 result = decodeVFPInstruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]541 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]542 Size = 4;
543 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]544 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]545 }
546
547 MI.clear();
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]548 result = decodeNEONDupInstruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]549 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]550 Size = 4;
551 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]552 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]553 }
554
555 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
556 MI.clear();
557 uint32_t NEONLdStInsn = insn32;
558 NEONLdStInsn &= 0xF0FFFFFF;
559 NEONLdStInsn |= 0x04000000;
560 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]561 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]562 Size = 4;
563 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]564 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]565 }
566 }
567
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]568 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]569 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]570 uint32_t NEONDataInsn = insn32;
571 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
572 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
573 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
574 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]575 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]576 Size = 4;
577 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]578 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]579 }
580 }
581
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]582 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]583 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]584}
585
586
587extern "C" void LLVMInitializeARMDisassembler() {
588 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
589 createARMDisassembler);
590 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
591 createThumbDisassembler);
592}
593
594static const unsigned GPRDecoderTable[] = {
595 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
596 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
597 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
598 ARM::R12, ARM::SP, ARM::LR, ARM::PC
599};
600
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]601static MCDisassembler::DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]602 uint64_t Address, const void *Decoder) {
603 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]604 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]605
606 unsigned Register = GPRDecoderTable[RegNo];
607 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]608 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]609}
610
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]611static MCDisassembler::DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]612DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
613 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]614 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]615 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
616}
617
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]618static MCDisassembler::DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]619 uint64_t Address, const void *Decoder) {
620 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]621 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]622 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
623}
624
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]625static MCDisassembler::DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]626 uint64_t Address, const void *Decoder) {
627 unsigned Register = 0;
628 switch (RegNo) {
629 case 0:
630 Register = ARM::R0;
631 break;
632 case 1:
633 Register = ARM::R1;
634 break;
635 case 2:
636 Register = ARM::R2;
637 break;
638 case 3:
639 Register = ARM::R3;
640 break;
641 case 9:
642 Register = ARM::R9;
643 break;
644 case 12:
645 Register = ARM::R12;
646 break;
647 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]648 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]649 }
650
651 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]652 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]653}
654
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]655static MCDisassembler::DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]656 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]657 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]658 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
659}
660
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]661static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]662 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
663 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
664 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
665 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
666 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
667 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
668 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
669 ARM::S28, ARM::S29, ARM::S30, ARM::S31
670};
671
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]672static MCDisassembler::DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]673 uint64_t Address, const void *Decoder) {
674 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]675 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]676
677 unsigned Register = SPRDecoderTable[RegNo];
678 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]679 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]680}
681
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]682static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]683 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
684 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
685 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
686 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
687 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
688 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
689 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
690 ARM::D28, ARM::D29, ARM::D30, ARM::D31
691};
692
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]693static MCDisassembler::DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]694 uint64_t Address, const void *Decoder) {
695 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]696 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]697
698 unsigned Register = DPRDecoderTable[RegNo];
699 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]700 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]701}
702
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]703static MCDisassembler::DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704 uint64_t Address, const void *Decoder) {
705 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]706 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]707 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
708}
709
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]710static MCDisassembler::DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]711DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
712 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]713 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]714 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]715 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
716}
717
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]718static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]719 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
720 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
721 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
722 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
723};
724
725
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]726static MCDisassembler::DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]727 uint64_t Address, const void *Decoder) {
728 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]729 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]730 RegNo >>= 1;
731
732 unsigned Register = QPRDecoderTable[RegNo];
733 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]734 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]735}
736
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]737static MCDisassembler::DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]738 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]739 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]740 // AL predicate is not allowed on Thumb1 branches.
741 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]742 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]743 Inst.addOperand(MCOperand::CreateImm(Val));
744 if (Val == ARMCC::AL) {
745 Inst.addOperand(MCOperand::CreateReg(0));
746 } else
747 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]748 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]749}
750
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]751static MCDisassembler::DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]752 uint64_t Address, const void *Decoder) {
753 if (Val)
754 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
755 else
756 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]757 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]758}
759
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]760static MCDisassembler::DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]761 uint64_t Address, const void *Decoder) {
762 uint32_t imm = Val & 0xFF;
763 uint32_t rot = (Val & 0xF00) >> 7;
764 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
765 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]766 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]767}
768
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]769static MCDisassembler::DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]770 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]771 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]772
773 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
774 unsigned type = fieldFromInstruction32(Val, 5, 2);
775 unsigned imm = fieldFromInstruction32(Val, 7, 5);
776
777 // Register-immediate
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]779
780 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
781 switch (type) {
782 case 0:
783 Shift = ARM_AM::lsl;
784 break;
785 case 1:
786 Shift = ARM_AM::lsr;
787 break;
788 case 2:
789 Shift = ARM_AM::asr;
790 break;
791 case 3:
792 Shift = ARM_AM::ror;
793 break;
794 }
795
796 if (Shift == ARM_AM::ror && imm == 0)
797 Shift = ARM_AM::rrx;
798
799 unsigned Op = Shift | (imm << 3);
800 Inst.addOperand(MCOperand::CreateImm(Op));
801
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]802 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]803}
804
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]805static MCDisassembler::DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]806 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]807 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]808
809 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
810 unsigned type = fieldFromInstruction32(Val, 5, 2);
811 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
812
813 // Register-register
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]814 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
815 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]816
817 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
818 switch (type) {
819 case 0:
820 Shift = ARM_AM::lsl;
821 break;
822 case 1:
823 Shift = ARM_AM::lsr;
824 break;
825 case 2:
826 Shift = ARM_AM::asr;
827 break;
828 case 3:
829 Shift = ARM_AM::ror;
830 break;
831 }
832
833 Inst.addOperand(MCOperand::CreateImm(Shift));
834
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]835 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836}
837
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]838static MCDisassembler::DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]839 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]840 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]841
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]842 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]843 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]844 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]845 if (Val & (1 << i)) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]846 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]847 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]848 }
849
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]850 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]851}
852
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]853static MCDisassembler::DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]855 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]856
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]857 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
858 unsigned regs = Val & 0xFF;
859
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]860 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]861 for (unsigned i = 0; i < (regs - 1); ++i) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]862 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]863 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]864
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]865 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]866}
867
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]868static MCDisassembler::DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]869 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]870 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]871
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]872 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
873 unsigned regs = (Val & 0xFF) / 2;
874
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]875 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]876 for (unsigned i = 0; i < (regs - 1); ++i) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]877 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]878 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]879
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]880 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]881}
882
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]883static MCDisassembler::DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]884 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]885 // This operand encodes a mask of contiguous zeros between a specified MSB
886 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
887 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]888 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]889 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]890 unsigned msb = fieldFromInstruction32(Val, 5, 5);
891 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
892 uint32_t msb_mask = (1 << (msb+1)) - 1;
893 uint32_t lsb_mask = (1 << lsb) - 1;
894 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]895 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]896}
897
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]898static MCDisassembler::DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]899 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]900 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]901
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]902 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
903 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
904 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
905 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
906 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
907 unsigned U = fieldFromInstruction32(Insn, 23, 1);
908
909 switch (Inst.getOpcode()) {
910 case ARM::LDC_OFFSET:
911 case ARM::LDC_PRE:
912 case ARM::LDC_POST:
913 case ARM::LDC_OPTION:
914 case ARM::LDCL_OFFSET:
915 case ARM::LDCL_PRE:
916 case ARM::LDCL_POST:
917 case ARM::LDCL_OPTION:
918 case ARM::STC_OFFSET:
919 case ARM::STC_PRE:
920 case ARM::STC_POST:
921 case ARM::STC_OPTION:
922 case ARM::STCL_OFFSET:
923 case ARM::STCL_PRE:
924 case ARM::STCL_POST:
925 case ARM::STCL_OPTION:
926 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]927 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]928 break;
929 default:
930 break;
931 }
932
933 Inst.addOperand(MCOperand::CreateImm(coproc));
934 Inst.addOperand(MCOperand::CreateImm(CRd));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]936 switch (Inst.getOpcode()) {
937 case ARM::LDC_OPTION:
938 case ARM::LDCL_OPTION:
939 case ARM::LDC2_OPTION:
940 case ARM::LDC2L_OPTION:
941 case ARM::STC_OPTION:
942 case ARM::STCL_OPTION:
943 case ARM::STC2_OPTION:
944 case ARM::STC2L_OPTION:
945 case ARM::LDCL_POST:
946 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]947 case ARM::LDC2L_POST:
948 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]949 break;
950 default:
951 Inst.addOperand(MCOperand::CreateReg(0));
952 break;
953 }
954
955 unsigned P = fieldFromInstruction32(Insn, 24, 1);
956 unsigned W = fieldFromInstruction32(Insn, 21, 1);
957
958 bool writeback = (P == 0) || (W == 1);
959 unsigned idx_mode = 0;
960 if (P && writeback)
961 idx_mode = ARMII::IndexModePre;
962 else if (!P && writeback)
963 idx_mode = ARMII::IndexModePost;
964
965 switch (Inst.getOpcode()) {
966 case ARM::LDCL_POST:
967 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]968 case ARM::LDC2L_POST:
969 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]970 imm |= U << 8;
971 case ARM::LDC_OPTION:
972 case ARM::LDCL_OPTION:
973 case ARM::LDC2_OPTION:
974 case ARM::LDC2L_OPTION:
975 case ARM::STC_OPTION:
976 case ARM::STCL_OPTION:
977 case ARM::STC2_OPTION:
978 case ARM::STC2L_OPTION:
979 Inst.addOperand(MCOperand::CreateImm(imm));
980 break;
981 default:
982 if (U)
983 Inst.addOperand(MCOperand::CreateImm(
984 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
985 else
986 Inst.addOperand(MCOperand::CreateImm(
987 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
988 break;
989 }
990
991 switch (Inst.getOpcode()) {
992 case ARM::LDC_OFFSET:
993 case ARM::LDC_PRE:
994 case ARM::LDC_POST:
995 case ARM::LDC_OPTION:
996 case ARM::LDCL_OFFSET:
997 case ARM::LDCL_PRE:
998 case ARM::LDCL_POST:
999 case ARM::LDCL_OPTION:
1000 case ARM::STC_OFFSET:
1001 case ARM::STC_PRE:
1002 case ARM::STC_POST:
1003 case ARM::STC_OPTION:
1004 case ARM::STCL_OFFSET:
1005 case ARM::STCL_PRE:
1006 case ARM::STCL_POST:
1007 case ARM::STCL_OPTION:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1008 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1009 break;
1010 default:
1011 break;
1012 }
1013
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1014 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1015}
1016
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1017static MCDisassembler::DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1018DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1019 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1020 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1021
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1022 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1023 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1024 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1025 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1026 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1027 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1028 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1029 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1030
1031 // On stores, the writeback operand precedes Rt.
1032 switch (Inst.getOpcode()) {
1033 case ARM::STR_POST_IMM:
1034 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1035 case ARM::STRB_POST_IMM:
1036 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1037 case ARM::STRT_POST_REG:
1038 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1039 case ARM::STRBT_POST_REG:
1040 case ARM::STRBT_POST_IMM:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1041 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1042 break;
1043 default:
1044 break;
1045 }
1046
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1048
1049 // On loads, the writeback operand comes after Rt.
1050 switch (Inst.getOpcode()) {
1051 case ARM::LDR_POST_IMM:
1052 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1053 case ARM::LDRB_POST_IMM:
1054 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1055 case ARM::LDRBT_POST_REG:
1056 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1057 case ARM::LDRT_POST_REG:
1058 case ARM::LDRT_POST_IMM:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1059 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1060 break;
1061 default:
1062 break;
1063 }
1064
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1066
1067 ARM_AM::AddrOpc Op = ARM_AM::add;
1068 if (!fieldFromInstruction32(Insn, 23, 1))
1069 Op = ARM_AM::sub;
1070
1071 bool writeback = (P == 0) || (W == 1);
1072 unsigned idx_mode = 0;
1073 if (P && writeback)
1074 idx_mode = ARMII::IndexModePre;
1075 else if (!P && writeback)
1076 idx_mode = ARMII::IndexModePost;
1077
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1078 if (writeback && (Rn == 15 || Rn == Rt)) S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1079
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1080 if (reg) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1081 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1082 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1083 switch( fieldFromInstruction32(Insn, 5, 2)) {
1084 case 0:
1085 Opc = ARM_AM::lsl;
1086 break;
1087 case 1:
1088 Opc = ARM_AM::lsr;
1089 break;
1090 case 2:
1091 Opc = ARM_AM::asr;
1092 break;
1093 case 3:
1094 Opc = ARM_AM::ror;
1095 break;
1096 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1097 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1098 }
1099 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1100 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1101
1102 Inst.addOperand(MCOperand::CreateImm(imm));
1103 } else {
1104 Inst.addOperand(MCOperand::CreateReg(0));
1105 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1106 Inst.addOperand(MCOperand::CreateImm(tmp));
1107 }
1108
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1110
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1111 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112}
1113
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1114static MCDisassembler::DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1115 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1116 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1117
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1118 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1119 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1120 unsigned type = fieldFromInstruction32(Val, 5, 2);
1121 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1122 unsigned U = fieldFromInstruction32(Val, 12, 1);
1123
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1124 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1125 switch (type) {
1126 case 0:
1127 ShOp = ARM_AM::lsl;
1128 break;
1129 case 1:
1130 ShOp = ARM_AM::lsr;
1131 break;
1132 case 2:
1133 ShOp = ARM_AM::asr;
1134 break;
1135 case 3:
1136 ShOp = ARM_AM::ror;
1137 break;
1138 }
1139
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
1141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1142 unsigned shift;
1143 if (U)
1144 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1145 else
1146 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1147 Inst.addOperand(MCOperand::CreateImm(shift));
1148
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1149 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1150}
1151
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1152static MCDisassembler::DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1153DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1154 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1155 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1156
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1157 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1158 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1159 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1160 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1161 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1162 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1163 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1164 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1165 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1166
1167 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1168
1169 // For {LD,ST}RD, Rt must be even, else undefined.
1170 switch (Inst.getOpcode()) {
1171 case ARM::STRD:
1172 case ARM::STRD_PRE:
1173 case ARM::STRD_POST:
1174 case ARM::LDRD:
1175 case ARM::LDRD_PRE:
1176 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1177 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1178 break;
1179 default:
1180 break;
1181 }
1182
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1183 if (writeback) { // Writeback
1184 if (P)
1185 U |= ARMII::IndexModePre << 9;
1186 else
1187 U |= ARMII::IndexModePost << 9;
1188
1189 // On stores, the writeback operand precedes Rt.
1190 switch (Inst.getOpcode()) {
1191 case ARM::STRD:
1192 case ARM::STRD_PRE:
1193 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1194 case ARM::STRH:
1195 case ARM::STRH_PRE:
1196 case ARM::STRH_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1198 break;
1199 default:
1200 break;
1201 }
1202 }
1203
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1205 switch (Inst.getOpcode()) {
1206 case ARM::STRD:
1207 case ARM::STRD_PRE:
1208 case ARM::STRD_POST:
1209 case ARM::LDRD:
1210 case ARM::LDRD_PRE:
1211 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1213 break;
1214 default:
1215 break;
1216 }
1217
1218 if (writeback) {
1219 // On loads, the writeback operand comes after Rt.
1220 switch (Inst.getOpcode()) {
1221 case ARM::LDRD:
1222 case ARM::LDRD_PRE:
1223 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1224 case ARM::LDRH:
1225 case ARM::LDRH_PRE:
1226 case ARM::LDRH_POST:
1227 case ARM::LDRSH:
1228 case ARM::LDRSH_PRE:
1229 case ARM::LDRSH_POST:
1230 case ARM::LDRSB:
1231 case ARM::LDRSB_PRE:
1232 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1233 case ARM::LDRHTr:
1234 case ARM::LDRSBTr:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1236 break;
1237 default:
1238 break;
1239 }
1240 }
1241
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1243
1244 if (type) {
1245 Inst.addOperand(MCOperand::CreateReg(0));
1246 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1247 } else {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1249 Inst.addOperand(MCOperand::CreateImm(U));
1250 }
1251
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1252 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1253
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1254 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255}
1256
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1257static MCDisassembler::DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1258 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1259 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1260
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1261 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1262 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1263
1264 switch (mode) {
1265 case 0:
1266 mode = ARM_AM::da;
1267 break;
1268 case 1:
1269 mode = ARM_AM::ia;
1270 break;
1271 case 2:
1272 mode = ARM_AM::db;
1273 break;
1274 case 3:
1275 mode = ARM_AM::ib;
1276 break;
1277 }
1278
1279 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1281
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1282 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1283}
1284
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1285static MCDisassembler::DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1286 unsigned Insn,
1287 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1288 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1289
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1290 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1291 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1292 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1293
1294 if (pred == 0xF) {
1295 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1296 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1297 Inst.setOpcode(ARM::RFEDA);
1298 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1299 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1300 Inst.setOpcode(ARM::RFEDA_UPD);
1301 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1302 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1303 Inst.setOpcode(ARM::RFEDB);
1304 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1305 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1306 Inst.setOpcode(ARM::RFEDB_UPD);
1307 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1308 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1309 Inst.setOpcode(ARM::RFEIA);
1310 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1311 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1312 Inst.setOpcode(ARM::RFEIA_UPD);
1313 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1314 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1315 Inst.setOpcode(ARM::RFEIB);
1316 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1317 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1318 Inst.setOpcode(ARM::RFEIB_UPD);
1319 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1320 case ARM::STMDA:
1321 Inst.setOpcode(ARM::SRSDA);
1322 break;
1323 case ARM::STMDA_UPD:
1324 Inst.setOpcode(ARM::SRSDA_UPD);
1325 break;
1326 case ARM::STMDB:
1327 Inst.setOpcode(ARM::SRSDB);
1328 break;
1329 case ARM::STMDB_UPD:
1330 Inst.setOpcode(ARM::SRSDB_UPD);
1331 break;
1332 case ARM::STMIA:
1333 Inst.setOpcode(ARM::SRSIA);
1334 break;
1335 case ARM::STMIA_UPD:
1336 Inst.setOpcode(ARM::SRSIA_UPD);
1337 break;
1338 case ARM::STMIB:
1339 Inst.setOpcode(ARM::SRSIB);
1340 break;
1341 case ARM::STMIB_UPD:
1342 Inst.setOpcode(ARM::SRSIB_UPD);
1343 break;
1344 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1345 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1346 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1347
1348 // For stores (which become SRS's, the only operand is the mode.
1349 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1350 Inst.addOperand(
1351 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1352 return S;
1353 }
1354
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1355 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1356 }
1357
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
1359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; // Tied
1360 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
1361 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1362
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1363 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1364}
1365
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1366static MCDisassembler::DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1367 uint64_t Address, const void *Decoder) {
1368 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1369 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1370 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1371 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1372
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1373 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1374
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1375 // imod == '01' --> UNPREDICTABLE
1376 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1377 // return failure here. The '01' imod value is unprintable, so there's
1378 // nothing useful we could do even if we returned UNPREDICTABLE.
1379
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1380 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1381
1382 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1383 Inst.setOpcode(ARM::CPS3p);
1384 Inst.addOperand(MCOperand::CreateImm(imod));
1385 Inst.addOperand(MCOperand::CreateImm(iflags));
1386 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1387 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1388 Inst.setOpcode(ARM::CPS2p);
1389 Inst.addOperand(MCOperand::CreateImm(imod));
1390 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1391 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1392 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1393 Inst.setOpcode(ARM::CPS1p);
1394 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1395 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1396 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1397 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1398 Inst.setOpcode(ARM::CPS1p);
1399 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1400 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1401 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1402
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1403 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1404}
1405
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1406static MCDisassembler::DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1407 uint64_t Address, const void *Decoder) {
1408 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1409 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1410 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1411 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1412
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1413 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1414
1415 // imod == '01' --> UNPREDICTABLE
1416 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1417 // return failure here. The '01' imod value is unprintable, so there's
1418 // nothing useful we could do even if we returned UNPREDICTABLE.
1419
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1420 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1421
1422 if (imod && M) {
1423 Inst.setOpcode(ARM::t2CPS3p);
1424 Inst.addOperand(MCOperand::CreateImm(imod));
1425 Inst.addOperand(MCOperand::CreateImm(iflags));
1426 Inst.addOperand(MCOperand::CreateImm(mode));
1427 } else if (imod && !M) {
1428 Inst.setOpcode(ARM::t2CPS2p);
1429 Inst.addOperand(MCOperand::CreateImm(imod));
1430 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1431 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1432 } else if (!imod && M) {
1433 Inst.setOpcode(ARM::t2CPS1p);
1434 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1435 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1436 } else {
1437 // imod == '00' && M == '0' --> UNPREDICTABLE
1438 Inst.setOpcode(ARM::t2CPS1p);
1439 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1440 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1441 }
1442
1443 return S;
1444}
1445
1446
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1447static MCDisassembler::DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1448 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1449 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1450
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1451 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1452 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1453 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1454 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1455 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1456
1457 if (pred == 0xF)
1458 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1459
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1460 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
1461 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
1462 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
1463 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1464
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1465 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1466
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1467 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1468}
1469
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1470static MCDisassembler::DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1471 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1472 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1473
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1474 unsigned add = fieldFromInstruction32(Val, 12, 1);
1475 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1476 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1477
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1479
1480 if (!add) imm *= -1;
1481 if (imm == 0 && !add) imm = INT32_MIN;
1482 Inst.addOperand(MCOperand::CreateImm(imm));
1483
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1484 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1485}
1486
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1487static MCDisassembler::DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1488 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1489 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1490
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1491 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1492 unsigned U = fieldFromInstruction32(Val, 8, 1);
1493 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1494
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1496
1497 if (U)
1498 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1499 else
1500 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1501
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1502 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1503}
1504
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1505static MCDisassembler::DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1506 uint64_t Address, const void *Decoder) {
1507 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1508}
1509
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1510static MCDisassembler::DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1511DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1512 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1513 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1514
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1515 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1516 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1517
1518 if (pred == 0xF) {
1519 Inst.setOpcode(ARM::BLXi);
1520 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1521 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1522 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1523 }
1524
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1525 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1526 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1527
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1528 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1529}
1530
1531
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1532static MCDisassembler::DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1533 uint64_t Address, const void *Decoder) {
1534 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1535 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1536}
1537
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1538static MCDisassembler::DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1539 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1540 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1541
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1542 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1543 unsigned align = fieldFromInstruction32(Val, 4, 2);
1544
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1546 if (!align)
1547 Inst.addOperand(MCOperand::CreateImm(0));
1548 else
1549 Inst.addOperand(MCOperand::CreateImm(4 << align));
1550
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1551 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1552}
1553
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1554static MCDisassembler::DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1555 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1556 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1557
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1558 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1559 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1560 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1561 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1562 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1563 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1564
1565 // First output register
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1567
1568 // Second output register
1569 switch (Inst.getOpcode()) {
1570 case ARM::VLD1q8:
1571 case ARM::VLD1q16:
1572 case ARM::VLD1q32:
1573 case ARM::VLD1q64:
1574 case ARM::VLD1q8_UPD:
1575 case ARM::VLD1q16_UPD:
1576 case ARM::VLD1q32_UPD:
1577 case ARM::VLD1q64_UPD:
1578 case ARM::VLD1d8T:
1579 case ARM::VLD1d16T:
1580 case ARM::VLD1d32T:
1581 case ARM::VLD1d64T:
1582 case ARM::VLD1d8T_UPD:
1583 case ARM::VLD1d16T_UPD:
1584 case ARM::VLD1d32T_UPD:
1585 case ARM::VLD1d64T_UPD:
1586 case ARM::VLD1d8Q:
1587 case ARM::VLD1d16Q:
1588 case ARM::VLD1d32Q:
1589 case ARM::VLD1d64Q:
1590 case ARM::VLD1d8Q_UPD:
1591 case ARM::VLD1d16Q_UPD:
1592 case ARM::VLD1d32Q_UPD:
1593 case ARM::VLD1d64Q_UPD:
1594 case ARM::VLD2d8:
1595 case ARM::VLD2d16:
1596 case ARM::VLD2d32:
1597 case ARM::VLD2d8_UPD:
1598 case ARM::VLD2d16_UPD:
1599 case ARM::VLD2d32_UPD:
1600 case ARM::VLD2q8:
1601 case ARM::VLD2q16:
1602 case ARM::VLD2q32:
1603 case ARM::VLD2q8_UPD:
1604 case ARM::VLD2q16_UPD:
1605 case ARM::VLD2q32_UPD:
1606 case ARM::VLD3d8:
1607 case ARM::VLD3d16:
1608 case ARM::VLD3d32:
1609 case ARM::VLD3d8_UPD:
1610 case ARM::VLD3d16_UPD:
1611 case ARM::VLD3d32_UPD:
1612 case ARM::VLD4d8:
1613 case ARM::VLD4d16:
1614 case ARM::VLD4d32:
1615 case ARM::VLD4d8_UPD:
1616 case ARM::VLD4d16_UPD:
1617 case ARM::VLD4d32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1618 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1619 break;
1620 case ARM::VLD2b8:
1621 case ARM::VLD2b16:
1622 case ARM::VLD2b32:
1623 case ARM::VLD2b8_UPD:
1624 case ARM::VLD2b16_UPD:
1625 case ARM::VLD2b32_UPD:
1626 case ARM::VLD3q8:
1627 case ARM::VLD3q16:
1628 case ARM::VLD3q32:
1629 case ARM::VLD3q8_UPD:
1630 case ARM::VLD3q16_UPD:
1631 case ARM::VLD3q32_UPD:
1632 case ARM::VLD4q8:
1633 case ARM::VLD4q16:
1634 case ARM::VLD4q32:
1635 case ARM::VLD4q8_UPD:
1636 case ARM::VLD4q16_UPD:
1637 case ARM::VLD4q32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1638 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1639 default:
1640 break;
1641 }
1642
1643 // Third output register
1644 switch(Inst.getOpcode()) {
1645 case ARM::VLD1d8T:
1646 case ARM::VLD1d16T:
1647 case ARM::VLD1d32T:
1648 case ARM::VLD1d64T:
1649 case ARM::VLD1d8T_UPD:
1650 case ARM::VLD1d16T_UPD:
1651 case ARM::VLD1d32T_UPD:
1652 case ARM::VLD1d64T_UPD:
1653 case ARM::VLD1d8Q:
1654 case ARM::VLD1d16Q:
1655 case ARM::VLD1d32Q:
1656 case ARM::VLD1d64Q:
1657 case ARM::VLD1d8Q_UPD:
1658 case ARM::VLD1d16Q_UPD:
1659 case ARM::VLD1d32Q_UPD:
1660 case ARM::VLD1d64Q_UPD:
1661 case ARM::VLD2q8:
1662 case ARM::VLD2q16:
1663 case ARM::VLD2q32:
1664 case ARM::VLD2q8_UPD:
1665 case ARM::VLD2q16_UPD:
1666 case ARM::VLD2q32_UPD:
1667 case ARM::VLD3d8:
1668 case ARM::VLD3d16:
1669 case ARM::VLD3d32:
1670 case ARM::VLD3d8_UPD:
1671 case ARM::VLD3d16_UPD:
1672 case ARM::VLD3d32_UPD:
1673 case ARM::VLD4d8:
1674 case ARM::VLD4d16:
1675 case ARM::VLD4d32:
1676 case ARM::VLD4d8_UPD:
1677 case ARM::VLD4d16_UPD:
1678 case ARM::VLD4d32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1679 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1680 break;
1681 case ARM::VLD3q8:
1682 case ARM::VLD3q16:
1683 case ARM::VLD3q32:
1684 case ARM::VLD3q8_UPD:
1685 case ARM::VLD3q16_UPD:
1686 case ARM::VLD3q32_UPD:
1687 case ARM::VLD4q8:
1688 case ARM::VLD4q16:
1689 case ARM::VLD4q32:
1690 case ARM::VLD4q8_UPD:
1691 case ARM::VLD4q16_UPD:
1692 case ARM::VLD4q32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1693 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1694 break;
1695 default:
1696 break;
1697 }
1698
1699 // Fourth output register
1700 switch (Inst.getOpcode()) {
1701 case ARM::VLD1d8Q:
1702 case ARM::VLD1d16Q:
1703 case ARM::VLD1d32Q:
1704 case ARM::VLD1d64Q:
1705 case ARM::VLD1d8Q_UPD:
1706 case ARM::VLD1d16Q_UPD:
1707 case ARM::VLD1d32Q_UPD:
1708 case ARM::VLD1d64Q_UPD:
1709 case ARM::VLD2q8:
1710 case ARM::VLD2q16:
1711 case ARM::VLD2q32:
1712 case ARM::VLD2q8_UPD:
1713 case ARM::VLD2q16_UPD:
1714 case ARM::VLD2q32_UPD:
1715 case ARM::VLD4d8:
1716 case ARM::VLD4d16:
1717 case ARM::VLD4d32:
1718 case ARM::VLD4d8_UPD:
1719 case ARM::VLD4d16_UPD:
1720 case ARM::VLD4d32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1721 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1722 break;
1723 case ARM::VLD4q8:
1724 case ARM::VLD4q16:
1725 case ARM::VLD4q32:
1726 case ARM::VLD4q8_UPD:
1727 case ARM::VLD4q16_UPD:
1728 case ARM::VLD4q32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1729 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1730 break;
1731 default:
1732 break;
1733 }
1734
1735 // Writeback operand
1736 switch (Inst.getOpcode()) {
1737 case ARM::VLD1d8_UPD:
1738 case ARM::VLD1d16_UPD:
1739 case ARM::VLD1d32_UPD:
1740 case ARM::VLD1d64_UPD:
1741 case ARM::VLD1q8_UPD:
1742 case ARM::VLD1q16_UPD:
1743 case ARM::VLD1q32_UPD:
1744 case ARM::VLD1q64_UPD:
1745 case ARM::VLD1d8T_UPD:
1746 case ARM::VLD1d16T_UPD:
1747 case ARM::VLD1d32T_UPD:
1748 case ARM::VLD1d64T_UPD:
1749 case ARM::VLD1d8Q_UPD:
1750 case ARM::VLD1d16Q_UPD:
1751 case ARM::VLD1d32Q_UPD:
1752 case ARM::VLD1d64Q_UPD:
1753 case ARM::VLD2d8_UPD:
1754 case ARM::VLD2d16_UPD:
1755 case ARM::VLD2d32_UPD:
1756 case ARM::VLD2q8_UPD:
1757 case ARM::VLD2q16_UPD:
1758 case ARM::VLD2q32_UPD:
1759 case ARM::VLD2b8_UPD:
1760 case ARM::VLD2b16_UPD:
1761 case ARM::VLD2b32_UPD:
1762 case ARM::VLD3d8_UPD:
1763 case ARM::VLD3d16_UPD:
1764 case ARM::VLD3d32_UPD:
1765 case ARM::VLD3q8_UPD:
1766 case ARM::VLD3q16_UPD:
1767 case ARM::VLD3q32_UPD:
1768 case ARM::VLD4d8_UPD:
1769 case ARM::VLD4d16_UPD:
1770 case ARM::VLD4d32_UPD:
1771 case ARM::VLD4q8_UPD:
1772 case ARM::VLD4q16_UPD:
1773 case ARM::VLD4q32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1774 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1775 break;
1776 default:
1777 break;
1778 }
1779
1780 // AddrMode6 Base (register+alignment)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1781 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1782
1783 // AddrMode6 Offset (register)
1784 if (Rm == 0xD)
1785 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1786 else if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1788 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1789
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1790 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1791}
1792
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1793static MCDisassembler::DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1794 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1795 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1796
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1797 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1798 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1799 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1800 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1801 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1802 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1803
1804 // Writeback Operand
1805 switch (Inst.getOpcode()) {
1806 case ARM::VST1d8_UPD:
1807 case ARM::VST1d16_UPD:
1808 case ARM::VST1d32_UPD:
1809 case ARM::VST1d64_UPD:
1810 case ARM::VST1q8_UPD:
1811 case ARM::VST1q16_UPD:
1812 case ARM::VST1q32_UPD:
1813 case ARM::VST1q64_UPD:
1814 case ARM::VST1d8T_UPD:
1815 case ARM::VST1d16T_UPD:
1816 case ARM::VST1d32T_UPD:
1817 case ARM::VST1d64T_UPD:
1818 case ARM::VST1d8Q_UPD:
1819 case ARM::VST1d16Q_UPD:
1820 case ARM::VST1d32Q_UPD:
1821 case ARM::VST1d64Q_UPD:
1822 case ARM::VST2d8_UPD:
1823 case ARM::VST2d16_UPD:
1824 case ARM::VST2d32_UPD:
1825 case ARM::VST2q8_UPD:
1826 case ARM::VST2q16_UPD:
1827 case ARM::VST2q32_UPD:
1828 case ARM::VST2b8_UPD:
1829 case ARM::VST2b16_UPD:
1830 case ARM::VST2b32_UPD:
1831 case ARM::VST3d8_UPD:
1832 case ARM::VST3d16_UPD:
1833 case ARM::VST3d32_UPD:
1834 case ARM::VST3q8_UPD:
1835 case ARM::VST3q16_UPD:
1836 case ARM::VST3q32_UPD:
1837 case ARM::VST4d8_UPD:
1838 case ARM::VST4d16_UPD:
1839 case ARM::VST4d32_UPD:
1840 case ARM::VST4q8_UPD:
1841 case ARM::VST4q16_UPD:
1842 case ARM::VST4q32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1843 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1844 break;
1845 default:
1846 break;
1847 }
1848
1849 // AddrMode6 Base (register+alignment)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1850 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1851
1852 // AddrMode6 Offset (register)
1853 if (Rm == 0xD)
1854 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1855 else if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1857 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1858
1859 // First input register
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1860 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1861
1862 // Second input register
1863 switch (Inst.getOpcode()) {
1864 case ARM::VST1q8:
1865 case ARM::VST1q16:
1866 case ARM::VST1q32:
1867 case ARM::VST1q64:
1868 case ARM::VST1q8_UPD:
1869 case ARM::VST1q16_UPD:
1870 case ARM::VST1q32_UPD:
1871 case ARM::VST1q64_UPD:
1872 case ARM::VST1d8T:
1873 case ARM::VST1d16T:
1874 case ARM::VST1d32T:
1875 case ARM::VST1d64T:
1876 case ARM::VST1d8T_UPD:
1877 case ARM::VST1d16T_UPD:
1878 case ARM::VST1d32T_UPD:
1879 case ARM::VST1d64T_UPD:
1880 case ARM::VST1d8Q:
1881 case ARM::VST1d16Q:
1882 case ARM::VST1d32Q:
1883 case ARM::VST1d64Q:
1884 case ARM::VST1d8Q_UPD:
1885 case ARM::VST1d16Q_UPD:
1886 case ARM::VST1d32Q_UPD:
1887 case ARM::VST1d64Q_UPD:
1888 case ARM::VST2d8:
1889 case ARM::VST2d16:
1890 case ARM::VST2d32:
1891 case ARM::VST2d8_UPD:
1892 case ARM::VST2d16_UPD:
1893 case ARM::VST2d32_UPD:
1894 case ARM::VST2q8:
1895 case ARM::VST2q16:
1896 case ARM::VST2q32:
1897 case ARM::VST2q8_UPD:
1898 case ARM::VST2q16_UPD:
1899 case ARM::VST2q32_UPD:
1900 case ARM::VST3d8:
1901 case ARM::VST3d16:
1902 case ARM::VST3d32:
1903 case ARM::VST3d8_UPD:
1904 case ARM::VST3d16_UPD:
1905 case ARM::VST3d32_UPD:
1906 case ARM::VST4d8:
1907 case ARM::VST4d16:
1908 case ARM::VST4d32:
1909 case ARM::VST4d8_UPD:
1910 case ARM::VST4d16_UPD:
1911 case ARM::VST4d32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1912 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1913 break;
1914 case ARM::VST2b8:
1915 case ARM::VST2b16:
1916 case ARM::VST2b32:
1917 case ARM::VST2b8_UPD:
1918 case ARM::VST2b16_UPD:
1919 case ARM::VST2b32_UPD:
1920 case ARM::VST3q8:
1921 case ARM::VST3q16:
1922 case ARM::VST3q32:
1923 case ARM::VST3q8_UPD:
1924 case ARM::VST3q16_UPD:
1925 case ARM::VST3q32_UPD:
1926 case ARM::VST4q8:
1927 case ARM::VST4q16:
1928 case ARM::VST4q32:
1929 case ARM::VST4q8_UPD:
1930 case ARM::VST4q16_UPD:
1931 case ARM::VST4q32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1932 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1933 break;
1934 default:
1935 break;
1936 }
1937
1938 // Third input register
1939 switch (Inst.getOpcode()) {
1940 case ARM::VST1d8T:
1941 case ARM::VST1d16T:
1942 case ARM::VST1d32T:
1943 case ARM::VST1d64T:
1944 case ARM::VST1d8T_UPD:
1945 case ARM::VST1d16T_UPD:
1946 case ARM::VST1d32T_UPD:
1947 case ARM::VST1d64T_UPD:
1948 case ARM::VST1d8Q:
1949 case ARM::VST1d16Q:
1950 case ARM::VST1d32Q:
1951 case ARM::VST1d64Q:
1952 case ARM::VST1d8Q_UPD:
1953 case ARM::VST1d16Q_UPD:
1954 case ARM::VST1d32Q_UPD:
1955 case ARM::VST1d64Q_UPD:
1956 case ARM::VST2q8:
1957 case ARM::VST2q16:
1958 case ARM::VST2q32:
1959 case ARM::VST2q8_UPD:
1960 case ARM::VST2q16_UPD:
1961 case ARM::VST2q32_UPD:
1962 case ARM::VST3d8:
1963 case ARM::VST3d16:
1964 case ARM::VST3d32:
1965 case ARM::VST3d8_UPD:
1966 case ARM::VST3d16_UPD:
1967 case ARM::VST3d32_UPD:
1968 case ARM::VST4d8:
1969 case ARM::VST4d16:
1970 case ARM::VST4d32:
1971 case ARM::VST4d8_UPD:
1972 case ARM::VST4d16_UPD:
1973 case ARM::VST4d32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1974 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1975 break;
1976 case ARM::VST3q8:
1977 case ARM::VST3q16:
1978 case ARM::VST3q32:
1979 case ARM::VST3q8_UPD:
1980 case ARM::VST3q16_UPD:
1981 case ARM::VST3q32_UPD:
1982 case ARM::VST4q8:
1983 case ARM::VST4q16:
1984 case ARM::VST4q32:
1985 case ARM::VST4q8_UPD:
1986 case ARM::VST4q16_UPD:
1987 case ARM::VST4q32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1988 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1989 break;
1990 default:
1991 break;
1992 }
1993
1994 // Fourth input register
1995 switch (Inst.getOpcode()) {
1996 case ARM::VST1d8Q:
1997 case ARM::VST1d16Q:
1998 case ARM::VST1d32Q:
1999 case ARM::VST1d64Q:
2000 case ARM::VST1d8Q_UPD:
2001 case ARM::VST1d16Q_UPD:
2002 case ARM::VST1d32Q_UPD:
2003 case ARM::VST1d64Q_UPD:
2004 case ARM::VST2q8:
2005 case ARM::VST2q16:
2006 case ARM::VST2q32:
2007 case ARM::VST2q8_UPD:
2008 case ARM::VST2q16_UPD:
2009 case ARM::VST2q32_UPD:
2010 case ARM::VST4d8:
2011 case ARM::VST4d16:
2012 case ARM::VST4d32:
2013 case ARM::VST4d8_UPD:
2014 case ARM::VST4d16_UPD:
2015 case ARM::VST4d32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2016 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2017 break;
2018 case ARM::VST4q8:
2019 case ARM::VST4q16:
2020 case ARM::VST4q32:
2021 case ARM::VST4q8_UPD:
2022 case ARM::VST4q16_UPD:
2023 case ARM::VST4q32_UPD:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2024 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2025 break;
2026 default:
2027 break;
2028 }
2029
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2030 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2031}
2032
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2033static MCDisassembler::DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2034 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2035 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2036
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2037 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2038 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2039 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2040 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2041 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2042 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2043 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2044
2045 align *= (1 << size);
2046
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2047 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2048 if (regs == 2) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2049 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2050 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2051 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2053 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2054
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2056 Inst.addOperand(MCOperand::CreateImm(align));
2057
2058 if (Rm == 0xD)
2059 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2060 else if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2062 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2063
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2064 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2065}
2066
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2067static MCDisassembler::DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2068 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2069 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2070
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2071 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2072 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2073 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2074 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2075 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2076 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2077 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2078 align *= 2*size;
2079
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2080 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
2081 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2082 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2084 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2085
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2087 Inst.addOperand(MCOperand::CreateImm(align));
2088
2089 if (Rm == 0xD)
2090 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2091 else if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2093 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2094
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2095 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2096}
2097
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2098static MCDisassembler::DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2099 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2100 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2101
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2102 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2103 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2104 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2105 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2106 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2107
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2108 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
2109 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) return MCDisassembler::Fail;
2110 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2111 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2113 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2114
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2115 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2116 Inst.addOperand(MCOperand::CreateImm(0));
2117
2118 if (Rm == 0xD)
2119 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2120 else if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2122 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2123
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2124 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2125}
2126
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2127static MCDisassembler::DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2128 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2129 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2130
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2131 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2132 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2133 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2134 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2135 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2136 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2137 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2138
2139 if (size == 0x3) {
2140 size = 4;
2141 align = 16;
2142 } else {
2143 if (size == 2) {
2144 size = 1 << size;
2145 align *= 8;
2146 } else {
2147 size = 1 << size;
2148 align *= 4*size;
2149 }
2150 }
2151
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
2153 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) return MCDisassembler::Fail;
2154 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) return MCDisassembler::Fail;
2155 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2156 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2158 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2159
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2160 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2161 Inst.addOperand(MCOperand::CreateImm(align));
2162
2163 if (Rm == 0xD)
2164 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2165 else if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2167 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2168
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2169 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2170}
2171
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2172static MCDisassembler::DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2173DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2174 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2175 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2176
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2177 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2178 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2179 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2180 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2181 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2182 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2183 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2184 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2185
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2186 if (Q) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2187 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2188 } else {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2189 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2190 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2191
2192 Inst.addOperand(MCOperand::CreateImm(imm));
2193
2194 switch (Inst.getOpcode()) {
2195 case ARM::VORRiv4i16:
2196 case ARM::VORRiv2i32:
2197 case ARM::VBICiv4i16:
2198 case ARM::VBICiv2i32:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2199 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2200 break;
2201 case ARM::VORRiv8i16:
2202 case ARM::VORRiv4i32:
2203 case ARM::VBICiv8i16:
2204 case ARM::VBICiv4i32:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2205 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2206 break;
2207 default:
2208 break;
2209 }
2210
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2211 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2212}
2213
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2214static MCDisassembler::DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2215 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2216 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2217
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2218 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2219 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2220 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2221 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2222 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2223
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2224 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
2225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2226 Inst.addOperand(MCOperand::CreateImm(8 << size));
2227
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2228 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2229}
2230
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2231static MCDisassembler::DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2232 uint64_t Address, const void *Decoder) {
2233 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2234 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2235}
2236
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2237static MCDisassembler::DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2238 uint64_t Address, const void *Decoder) {
2239 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2240 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2241}
2242
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2243static MCDisassembler::DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2244 uint64_t Address, const void *Decoder) {
2245 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2246 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2247}
2248
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2249static MCDisassembler::DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2250 uint64_t Address, const void *Decoder) {
2251 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2252 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2253}
2254
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2255static MCDisassembler::DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2256 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2257 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2258
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2259 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2260 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2261 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2262 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2263 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2264 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2265 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2266 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2267
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2268 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2269 if (op) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2270 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2271 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2272
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2273 for (unsigned i = 0; i < length; ++i) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2274 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2275 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2276
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2277 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2278
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2279 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2280}
2281
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2282static MCDisassembler::DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2283 uint64_t Address, const void *Decoder) {
2284 // The immediate needs to be a fully instantiated float. However, the
2285 // auto-generated decoder is only able to fill in some of the bits
2286 // necessary. For instance, the 'b' bit is replicated multiple times,
2287 // and is even present in inverted form in one bit. We do a little
2288 // binary parsing here to fill in those missing bits, and then
2289 // reinterpret it all as a float.
2290 union {
2291 uint32_t integer;
2292 float fp;
2293 } fp_conv;
2294
2295 fp_conv.integer = Val;
2296 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2297 fp_conv.integer |= b << 26;
2298 fp_conv.integer |= b << 27;
2299 fp_conv.integer |= b << 28;
2300 fp_conv.integer |= b << 29;
2301 fp_conv.integer |= (~b & 0x1) << 30;
2302
2303 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2304 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2305}
2306
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2307static MCDisassembler::DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2308 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2309 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2310
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2311 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2312 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2313
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2314 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2315
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2316 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2317 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2318 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2319 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2320 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2321 case ARM::tADDrSPi:
2322 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2323 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2324 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2325
2326 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2327 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2328}
2329
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2330static MCDisassembler::DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2331 uint64_t Address, const void *Decoder) {
2332 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2333 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2334}
2335
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2336static MCDisassembler::DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2337 uint64_t Address, const void *Decoder) {
2338 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2339 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2340}
2341
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2342static MCDisassembler::DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2343 uint64_t Address, const void *Decoder) {
2344 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2345 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2346}
2347
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2348static MCDisassembler::DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2349 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2350 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2351
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2352 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2353 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2354
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2355 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2356 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2357
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2358 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2359}
2360
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2361static MCDisassembler::DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2362 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2363 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2364
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2365 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2366 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2367
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2368 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2369 Inst.addOperand(MCOperand::CreateImm(imm));
2370
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2371 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2372}
2373
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2374static MCDisassembler::DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2375 uint64_t Address, const void *Decoder) {
2376 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2377
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2378 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2379}
2380
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2381static MCDisassembler::DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2382 uint64_t Address, const void *Decoder) {
2383 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2384 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2385
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2386 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2387}
2388
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2389static MCDisassembler::DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2390 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2391 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2392
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2393 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2394 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2395 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2396
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2398 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2399 Inst.addOperand(MCOperand::CreateImm(imm));
2400
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2401 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2402}
2403
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2404static MCDisassembler::DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2405 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2406 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2407
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2408 switch (Inst.getOpcode()) {
2409 case ARM::t2PLDs:
2410 case ARM::t2PLDWs:
2411 case ARM::t2PLIs:
2412 break;
2413 default: {
2414 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2416 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2417 }
2418
2419 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2420 if (Rn == 0xF) {
2421 switch (Inst.getOpcode()) {
2422 case ARM::t2LDRBs:
2423 Inst.setOpcode(ARM::t2LDRBpci);
2424 break;
2425 case ARM::t2LDRHs:
2426 Inst.setOpcode(ARM::t2LDRHpci);
2427 break;
2428 case ARM::t2LDRSHs:
2429 Inst.setOpcode(ARM::t2LDRSHpci);
2430 break;
2431 case ARM::t2LDRSBs:
2432 Inst.setOpcode(ARM::t2LDRSBpci);
2433 break;
2434 case ARM::t2PLDs:
2435 Inst.setOpcode(ARM::t2PLDi12);
2436 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2437 break;
2438 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2439 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2440 }
2441
2442 int imm = fieldFromInstruction32(Insn, 0, 12);
2443 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2444 Inst.addOperand(MCOperand::CreateImm(imm));
2445
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2446 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2447 }
2448
2449 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2450 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2451 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2452 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2453
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2454 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2455}
2456
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2457static MCDisassembler::DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2458 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2459 int imm = Val & 0xFF;
2460 if (!(Val & 0x100)) imm *= -1;
2461 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2462
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2463 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2464}
2465
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2466static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2467 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2468 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2469
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2470 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2471 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2472
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2474 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2475
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2476 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2477}
2478
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2479static MCDisassembler::DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2480 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2481 int imm = Val & 0xFF;
2482 if (!(Val & 0x100)) imm *= -1;
2483 Inst.addOperand(MCOperand::CreateImm(imm));
2484
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2485 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2486}
2487
2488
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2489static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2490 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2491 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2492
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2493 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2494 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2495
2496 // Some instructions always use an additive offset.
2497 switch (Inst.getOpcode()) {
2498 case ARM::t2LDRT:
2499 case ARM::t2LDRBT:
2500 case ARM::t2LDRHT:
2501 case ARM::t2LDRSBT:
2502 case ARM::t2LDRSHT:
2503 imm |= 0x100;
2504 break;
2505 default:
2506 break;
2507 }
2508
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2510 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2511
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2512 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513}
2514
2515
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2516static MCDisassembler::DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2517 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2518 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2519
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2520 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2521 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2522
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524 Inst.addOperand(MCOperand::CreateImm(imm));
2525
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2526 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2527}
2528
2529
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2530static MCDisassembler::DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2531 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2532 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2533
2534 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2535 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2536 Inst.addOperand(MCOperand::CreateImm(imm));
2537
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2538 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2539}
2540
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2541static MCDisassembler::DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2542 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2543 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2544
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2545 if (Inst.getOpcode() == ARM::tADDrSP) {
2546 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2547 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2548
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler::Fail;
2550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2551 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2552 } else if (Inst.getOpcode() == ARM::tADDspr) {
2553 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2554
2555 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2556 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2558 }
2559
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2560 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2561}
2562
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2563static MCDisassembler::DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2564 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2565 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2566 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2567
2568 Inst.addOperand(MCOperand::CreateImm(imod));
2569 Inst.addOperand(MCOperand::CreateImm(flags));
2570
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2571 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2572}
2573
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2574static MCDisassembler::DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2575 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2576 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2577 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2578 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2579
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2581 Inst.addOperand(MCOperand::CreateImm(add));
2582
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2583 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2584}
2585
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2586static MCDisassembler::DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2587 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2588 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2589 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2590}
2591
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2592static MCDisassembler::DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2593 uint64_t Address, const void *Decoder) {
2594 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2595 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2596
2597 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2598 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2599}
2600
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2601static MCDisassembler::DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2602DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2603 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2604 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2605
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2607 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2608 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2609 switch (opc) {
2610 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2611 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2612 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2613 Inst.setOpcode(ARM::t2DSB);
2614 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2615 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2616 Inst.setOpcode(ARM::t2DMB);
2617 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2618 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2619 Inst.setOpcode(ARM::t2ISB);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2620 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2621 }
2622
2623 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2624 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2625 }
2626
2627 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2628 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2629 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2630 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2631 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2632
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2633 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) return MCDisassembler::Fail;
2634 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2635
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2636 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2637}
2638
2639// Decode a shifted immediate operand. These basically consist
2640// of an 8-bit value, and a 4-bit directive that specifies either
2641// a splat operation or a rotation.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2642static MCDisassembler::DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2643 uint64_t Address, const void *Decoder) {
2644 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2645 if (ctrl == 0) {
2646 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2647 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2648 switch (byte) {
2649 case 0:
2650 Inst.addOperand(MCOperand::CreateImm(imm));
2651 break;
2652 case 1:
2653 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2654 break;
2655 case 2:
2656 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2657 break;
2658 case 3:
2659 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2660 (imm << 8) | imm));
2661 break;
2662 }
2663 } else {
2664 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2665 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2666 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2667 Inst.addOperand(MCOperand::CreateImm(imm));
2668 }
2669
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2670 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2671}
2672
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2673static MCDisassembler::DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2674DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2675 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2676 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2677 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2678}
2679
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2680static MCDisassembler::DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2681 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2683 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684}
2685
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2686static MCDisassembler::DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2687 uint64_t Address, const void *Decoder) {
2688 switch (Val) {
2689 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2690 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2691 case 0xF: // SY
2692 case 0xE: // ST
2693 case 0xB: // ISH
2694 case 0xA: // ISHST
2695 case 0x7: // NSH
2696 case 0x6: // NSHST
2697 case 0x3: // OSH
2698 case 0x2: // OSHST
2699 break;
2700 }
2701
2702 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2703 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2704}
2705
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2706static MCDisassembler::DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2707 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2708 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2709 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2710 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2711}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2712
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2713static MCDisassembler::DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2714 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2715 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2716
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2717 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2718 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2719 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2720
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2721 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2722
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
2724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) return MCDisassembler::Fail;
2725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2726 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2727
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2728 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2729}
2730
2731
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2732static MCDisassembler::DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2733 uint64_t Address, const void *Decoder){
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2734 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2735
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2736 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2737 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2738 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]2739 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2740
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2741 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2742
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2743 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
2744 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2745
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
2747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) return MCDisassembler::Fail;
2748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2749 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2750
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2751 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2752}
2753
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2754static MCDisassembler::DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2755 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2756 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2757
2758 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2759 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2760 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2761 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2762 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2763 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2764
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2765 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2766
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
2768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2769 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;
2770 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2771
2772 return S;
2773}
2774
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2775static MCDisassembler::DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2776 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2777 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2778
2779 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2780 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2781 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2782 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2783 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2784 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2785 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2786
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2787 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
2788 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2789
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
2791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2792 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;
2793 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2794
2795 return S;
2796}
2797
2798
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2799static MCDisassembler::DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2800 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2801 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2802
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2803 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2804 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2805 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2806 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2807 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2808 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2809
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2810 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2811
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
2814 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;
2815 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2816
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2817 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2818}
2819
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2820static MCDisassembler::DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2821 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2822 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2823
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2824 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2825 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2826 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2827 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2828 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2829 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2830
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2831 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2832
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
2834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail;
2835 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) return MCDisassembler::Fail;
2836 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2837
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2838 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2839}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2840
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2841static MCDisassembler::DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2842 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2843 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2844
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2845 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2846 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2847 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2848 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2849 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2850
2851 unsigned align = 0;
2852 unsigned index = 0;
2853 switch (size) {
2854 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2855 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2856 case 0:
2857 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2858 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2859 index = fieldFromInstruction32(Insn, 5, 3);
2860 break;
2861 case 1:
2862 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2863 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2864 index = fieldFromInstruction32(Insn, 6, 2);
2865 if (fieldFromInstruction32(Insn, 4, 1))
2866 align = 2;
2867 break;
2868 case 2:
2869 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2870 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2871 index = fieldFromInstruction32(Insn, 7, 1);
2872 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2873 align = 4;
2874 }
2875
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2877 if (Rm != 0xF) { // Writeback
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2879 }
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2881 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]2882 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2883 if (Rm != 0xD) {
2884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
2885 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]2886 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2887 }
2888
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2890 Inst.addOperand(MCOperand::CreateImm(index));
2891
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2892 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2893}
2894
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2895static MCDisassembler::DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2896 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2897 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2898
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2899 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2900 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2901 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2902 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2903 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2904
2905 unsigned align = 0;
2906 unsigned index = 0;
2907 switch (size) {
2908 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2909 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2910 case 0:
2911 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2912 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2913 index = fieldFromInstruction32(Insn, 5, 3);
2914 break;
2915 case 1:
2916 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2917 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2918 index = fieldFromInstruction32(Insn, 6, 2);
2919 if (fieldFromInstruction32(Insn, 4, 1))
2920 align = 2;
2921 break;
2922 case 2:
2923 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2924 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2925 index = fieldFromInstruction32(Insn, 7, 1);
2926 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2927 align = 4;
2928 }
2929
2930 if (Rm != 0xF) { // Writeback
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2932 }
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2934 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]2935 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2936 if (Rm != 0xD) {
2937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
2938 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]2939 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2940 }
2941
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2942 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2943 Inst.addOperand(MCOperand::CreateImm(index));
2944
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2945 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2946}
2947
2948
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2949static MCDisassembler::DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2950 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2951 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2952
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2953 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2954 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2955 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2956 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2957 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2958
2959 unsigned align = 0;
2960 unsigned index = 0;
2961 unsigned inc = 1;
2962 switch (size) {
2963 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2964 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2965 case 0:
2966 index = fieldFromInstruction32(Insn, 5, 3);
2967 if (fieldFromInstruction32(Insn, 4, 1))
2968 align = 2;
2969 break;
2970 case 1:
2971 index = fieldFromInstruction32(Insn, 6, 2);
2972 if (fieldFromInstruction32(Insn, 4, 1))
2973 align = 4;
2974 if (fieldFromInstruction32(Insn, 5, 1))
2975 inc = 2;
2976 break;
2977 case 2:
2978 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2979 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2980 index = fieldFromInstruction32(Insn, 7, 1);
2981 if (fieldFromInstruction32(Insn, 4, 1) != 0)
2982 align = 8;
2983 if (fieldFromInstruction32(Insn, 6, 1))
2984 inc = 2;
2985 break;
2986 }
2987
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
2989 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2990 if (Rm != 0xF) { // Writeback
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2992 }
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]2994 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]2995 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2996 if (Rm != 0xD) {
2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
2998 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]2999 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3000 }
3001
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
3003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3004 Inst.addOperand(MCOperand::CreateImm(index));
3005
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3006 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3007}
3008
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3009static MCDisassembler::DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3010 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3011 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3012
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3013 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3014 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3015 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3016 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3017 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3018
3019 unsigned align = 0;
3020 unsigned index = 0;
3021 unsigned inc = 1;
3022 switch (size) {
3023 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3024 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3025 case 0:
3026 index = fieldFromInstruction32(Insn, 5, 3);
3027 if (fieldFromInstruction32(Insn, 4, 1))
3028 align = 2;
3029 break;
3030 case 1:
3031 index = fieldFromInstruction32(Insn, 6, 2);
3032 if (fieldFromInstruction32(Insn, 4, 1))
3033 align = 4;
3034 if (fieldFromInstruction32(Insn, 5, 1))
3035 inc = 2;
3036 break;
3037 case 2:
3038 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3039 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3040 index = fieldFromInstruction32(Insn, 7, 1);
3041 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3042 align = 8;
3043 if (fieldFromInstruction32(Insn, 6, 1))
3044 inc = 2;
3045 break;
3046 }
3047
3048 if (Rm != 0xF) { // Writeback
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3049 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3050 }
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3051 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3052 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3053 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3054 if (Rm != 0xD) {
3055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
3056 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3057 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3058 }
3059
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3060 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
3061 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3062 Inst.addOperand(MCOperand::CreateImm(index));
3063
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3064 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3065}
3066
3067
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3068static MCDisassembler::DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3069 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3070 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3071
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3072 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3073 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3074 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3075 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3076 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3077
3078 unsigned align = 0;
3079 unsigned index = 0;
3080 unsigned inc = 1;
3081 switch (size) {
3082 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3083 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3084 case 0:
3085 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3086 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3087 index = fieldFromInstruction32(Insn, 5, 3);
3088 break;
3089 case 1:
3090 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3091 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3092 index = fieldFromInstruction32(Insn, 6, 2);
3093 if (fieldFromInstruction32(Insn, 5, 1))
3094 inc = 2;
3095 break;
3096 case 2:
3097 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3098 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3099 index = fieldFromInstruction32(Insn, 7, 1);
3100 if (fieldFromInstruction32(Insn, 6, 1))
3101 inc = 2;
3102 break;
3103 }
3104
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3105 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
3106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
3107 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3108
3109 if (Rm != 0xF) { // Writeback
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3111 }
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3113 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3114 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3115 if (Rm != 0xD) {
3116 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
3117 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3118 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3119 }
3120
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3121 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
3122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
3123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3124 Inst.addOperand(MCOperand::CreateImm(index));
3125
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3126 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3127}
3128
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3129static MCDisassembler::DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3130 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3131 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3132
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3133 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3134 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3135 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3136 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3137 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3138
3139 unsigned align = 0;
3140 unsigned index = 0;
3141 unsigned inc = 1;
3142 switch (size) {
3143 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3144 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3145 case 0:
3146 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3147 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3148 index = fieldFromInstruction32(Insn, 5, 3);
3149 break;
3150 case 1:
3151 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3152 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3153 index = fieldFromInstruction32(Insn, 6, 2);
3154 if (fieldFromInstruction32(Insn, 5, 1))
3155 inc = 2;
3156 break;
3157 case 2:
3158 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3159 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3160 index = fieldFromInstruction32(Insn, 7, 1);
3161 if (fieldFromInstruction32(Insn, 6, 1))
3162 inc = 2;
3163 break;
3164 }
3165
3166 if (Rm != 0xF) { // Writeback
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3168 }
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3170 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3171 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3172 if (Rm != 0xD) {
3173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
3174 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3175 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3176 }
3177
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
3179 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
3180 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3181 Inst.addOperand(MCOperand::CreateImm(index));
3182
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3183 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3184}
3185
3186
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3187static MCDisassembler::DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3188 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3189 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3190
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3191 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3192 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3193 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3194 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3195 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3196
3197 unsigned align = 0;
3198 unsigned index = 0;
3199 unsigned inc = 1;
3200 switch (size) {
3201 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3202 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3203 case 0:
3204 if (fieldFromInstruction32(Insn, 4, 1))
3205 align = 4;
3206 index = fieldFromInstruction32(Insn, 5, 3);
3207 break;
3208 case 1:
3209 if (fieldFromInstruction32(Insn, 4, 1))
3210 align = 8;
3211 index = fieldFromInstruction32(Insn, 6, 2);
3212 if (fieldFromInstruction32(Insn, 5, 1))
3213 inc = 2;
3214 break;
3215 case 2:
3216 if (fieldFromInstruction32(Insn, 4, 2))
3217 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3218 index = fieldFromInstruction32(Insn, 7, 1);
3219 if (fieldFromInstruction32(Insn, 6, 1))
3220 inc = 2;
3221 break;
3222 }
3223
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
3225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
3226 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;
3227 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3228
3229 if (Rm != 0xF) { // Writeback
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3231 }
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3233 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3234 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3235 if (Rm != 0xD) {
3236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
3237 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3238 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3239 }
3240
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3241 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
3242 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
3243 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;
3244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3245 Inst.addOperand(MCOperand::CreateImm(index));
3246
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3247 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3248}
3249
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3250static MCDisassembler::DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3251 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3252 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3253
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3254 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3255 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3256 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3257 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3258 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3259
3260 unsigned align = 0;
3261 unsigned index = 0;
3262 unsigned inc = 1;
3263 switch (size) {
3264 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3265 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3266 case 0:
3267 if (fieldFromInstruction32(Insn, 4, 1))
3268 align = 4;
3269 index = fieldFromInstruction32(Insn, 5, 3);
3270 break;
3271 case 1:
3272 if (fieldFromInstruction32(Insn, 4, 1))
3273 align = 8;
3274 index = fieldFromInstruction32(Insn, 6, 2);
3275 if (fieldFromInstruction32(Insn, 5, 1))
3276 inc = 2;
3277 break;
3278 case 2:
3279 if (fieldFromInstruction32(Insn, 4, 2))
3280 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3281 index = fieldFromInstruction32(Insn, 7, 1);
3282 if (fieldFromInstruction32(Insn, 6, 1))
3283 inc = 2;
3284 break;
3285 }
3286
3287 if (Rm != 0xF) { // Writeback
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3289 }
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3291 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3292 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3293 if (Rm != 0xD) {
3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail;
3295 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3296 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3297 }
3298
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3299 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail;
3300 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail;
3301 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail;
3302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3303 Inst.addOperand(MCOperand::CreateImm(index));
3304
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3305 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3306}
3307
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3308static MCDisassembler::DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3309 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3310 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3311 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3312 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3313 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3314 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3315 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3316
3317 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3318 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3319
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3320 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) return MCDisassembler::Fail;
3321 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) return MCDisassembler::Fail;
3322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) return MCDisassembler::Fail;
3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) return MCDisassembler::Fail;
3324 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3325
3326 return S;
3327}
3328
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3329static MCDisassembler::DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3330 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3331 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3332 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3333 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3334 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3335 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3336 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3337
3338 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3339 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3340
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) return MCDisassembler::Fail;
3342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) return MCDisassembler::Fail;
3343 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) return MCDisassembler::Fail;
3344 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) return MCDisassembler::Fail;
3345 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3346
3347 return S;
3348}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3349
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3350static MCDisassembler::DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3351 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3352 MCDisassembler::DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3353 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3354 // The InstPrinter needs to have the low bit of the predicate in
3355 // the mask operand to be able to print it properly.
3356 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3357
3358 if (pred == 0xF) {
3359 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3360 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3361 }
3362
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3363 if ((mask & 0xF) == 0) {
3364 // Preserve the high bit of the mask, which is the low bit of
3365 // the predicate.
3366 mask &= 0x10;
3367 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3368 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3369 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3370
3371 Inst.addOperand(MCOperand::CreateImm(pred));
3372 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3373 return S;
3374}