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gerrit-public.fairphone.software / platform / external / llvm / 7011eee9b509f3a0f95a75f68787384f31ea3e01 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 5f6fc29b0894cf77e677ca61df8b5b0fe9ebf21a [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]16#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]17#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]18#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]22#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]39 ARMDisassembler(const MCSubtargetInfo &STI) :
40 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]41 }
42
43 ~ARMDisassembler() {
44 }
45
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
48 uint64_t &size,
49 const MemoryObject &region,
50 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]51 raw_ostream &vStream,
52 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]53
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62 /// Constructor - Initializes the disassembler.
63 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]64 ThumbDisassembler(const MCSubtargetInfo &STI) :
65 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]66 }
67
68 ~ThumbDisassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
74 const MemoryObject &region,
75 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]78
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
81private:
82 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]83 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]84 void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]88static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]89 switch (In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
92 return true;
93 case MCDisassembler::SoftFail:
94 Out = In;
95 return true;
96 case MCDisassembler::Fail:
97 Out = In;
98 return false;
99 }
100 return false;
101}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]102
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]103
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]120 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]122 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]129
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]148 unsigned Insn,
149 uint64_t Address,
150 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]154 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 unsigned Insn,
162 uint64_t Adddress,
163 const void *Decoder);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]182static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]184static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]186static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]188static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]190static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]192static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]194static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]196static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]198static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]200static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]202static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]204static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]210static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]212static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]214static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]216static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]218static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]224static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]226static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]228static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]230static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]232static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]234static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]236static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]238static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]240static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]242static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]244static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]246static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]252
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]253static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]255static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]257static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]259static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]261static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]277static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
278 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]279static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]287static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]293static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
294 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]295static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]296 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]297static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]299static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]301static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]303static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]304 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]305static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
306 uint64_t Address, const void *Decoder);
307static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]309static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
310 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]311static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]313static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
315
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]316
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]317
318#include "ARMGenDisassemblerTables.inc"
319#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]320#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]321
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]322static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
323 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]324}
325
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]326static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
327 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]328}
329
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]330EDInstInfo *ARMDisassembler::getEDInfo() const {
331 return instInfoARM;
332}
333
334EDInstInfo *ThumbDisassembler::getEDInfo() const {
335 return instInfoARM;
336}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]338DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]339 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]340 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]341 raw_ostream &os,
342 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]343 CommentStream = &cs;
344
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 uint8_t bytes[4];
346
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
348 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
349
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]350 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]351 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
352 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]353 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]354 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355
356 // Encoded as a small-endian 32-bit word in the stream.
357 uint32_t insn = (bytes[3] << 24) |
358 (bytes[2] << 16) |
359 (bytes[1] << 8) |
360 (bytes[0] << 0);
361
362 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]364 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]366 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 }
368
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 // VFP and NEON instructions, similarly, are shared between ARM
370 // and Thumb modes.
371 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]372 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]375 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 }
377
378 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]379 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]380 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]381 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382 // Add a fake predicate operand, because we share these instruction
383 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]384 if (!DecodePredicateOperand(MI, 0xE, Address, this))
385 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]386 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]387 }
388
389 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]390 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]391 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]392 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]393 // Add a fake predicate operand, because we share these instruction
394 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]395 if (!DecodePredicateOperand(MI, 0xE, Address, this))
396 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]397 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]398 }
399
400 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]401 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]402 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]403 Size = 4;
404 // Add a fake predicate operand, because we share these instruction
405 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]406 if (!DecodePredicateOperand(MI, 0xE, Address, this))
407 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]408 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]409 }
410
411 MI.clear();
412
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]413 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]414 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415}
416
417namespace llvm {
418extern MCInstrDesc ARMInsts[];
419}
420
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]421/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
422/// immediate Value in the MCInst. The immediate Value has had any PC
423/// adjustment made by the caller. If the instruction is a branch instruction
424/// then isBranch is true, else false. If the getOpInfo() function was set as
425/// part of the setupForSymbolicDisassembly() call then that function is called
426/// to get any symbolic information at the Address for this instruction. If
427/// that returns non-zero then the symbolic information it returns is used to
428/// create an MCExpr and that is added as an operand to the MCInst. If
429/// getOpInfo() returns zero and isBranch is true then a symbol look up for
430/// Value is done and if a symbol is found an MCExpr is created with that, else
431/// an MCExpr with Value is created. This function returns true if it adds an
432/// operand to the MCInst and false otherwise.
433static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
434 bool isBranch, uint64_t InstSize,
435 MCInst &MI, const void *Decoder) {
436 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
437 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
438 if (!getOpInfo)
439 return false;
440
441 struct LLVMOpInfo1 SymbolicOp;
442 SymbolicOp.Value = Value;
443 void *DisInfo = Dis->getDisInfoBlock();
444 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
445 if (isBranch) {
446 LLVMSymbolLookupCallback SymbolLookUp =
447 Dis->getLLVMSymbolLookupCallback();
448 if (SymbolLookUp) {
449 uint64_t ReferenceType;
450 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
451 const char *ReferenceName;
452 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
453 &ReferenceName);
454 if (Name) {
455 SymbolicOp.AddSymbol.Name = Name;
456 SymbolicOp.AddSymbol.Present = true;
457 SymbolicOp.Value = 0;
458 }
459 else {
460 SymbolicOp.Value = Value;
461 }
462 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
463 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
464 }
465 else {
466 return false;
467 }
468 }
469 else {
470 return false;
471 }
472 }
473
474 MCContext *Ctx = Dis->getMCContext();
475 const MCExpr *Add = NULL;
476 if (SymbolicOp.AddSymbol.Present) {
477 if (SymbolicOp.AddSymbol.Name) {
478 StringRef Name(SymbolicOp.AddSymbol.Name);
479 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
480 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
481 } else {
482 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
483 }
484 }
485
486 const MCExpr *Sub = NULL;
487 if (SymbolicOp.SubtractSymbol.Present) {
488 if (SymbolicOp.SubtractSymbol.Name) {
489 StringRef Name(SymbolicOp.SubtractSymbol.Name);
490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
491 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
492 } else {
493 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
494 }
495 }
496
497 const MCExpr *Off = NULL;
498 if (SymbolicOp.Value != 0)
499 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
500
501 const MCExpr *Expr;
502 if (Sub) {
503 const MCExpr *LHS;
504 if (Add)
505 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
506 else
507 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
508 if (Off != 0)
509 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
510 else
511 Expr = LHS;
512 } else if (Add) {
513 if (Off != 0)
514 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
515 else
516 Expr = Add;
517 } else {
518 if (Off != 0)
519 Expr = Off;
520 else
521 Expr = MCConstantExpr::Create(0, *Ctx);
522 }
523
524 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
526 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
529 MI.addOperand(MCOperand::CreateExpr(Expr));
530 else
531 assert("bad SymbolicOp.VariantKind");
532
533 return true;
534}
535
536/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
537/// referenced by a load instruction with the base register that is the Pc.
538/// These can often be values in a literal pool near the Address of the
539/// instruction. The Address of the instruction and its immediate Value are
540/// used as a possible literal pool entry. The SymbolLookUp call back will
541/// return the name of a symbol referenced by the the literal pool's entry if
542/// the referenced address is that of a symbol. Or it will return a pointer to
543/// a literal 'C' string if the referenced address of the literal pool's entry
544/// is an address into a section with 'C' string literals.
545static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
546 const void *Decoder) {
547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
548 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
549 if (SymbolLookUp) {
550 void *DisInfo = Dis->getDisInfoBlock();
551 uint64_t ReferenceType;
552 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
553 const char *ReferenceName;
554 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
555 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
556 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
557 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
558 }
559}
560
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]561// Thumb1 instructions don't have explicit S bits. Rather, they
562// implicitly set CPSR. Since it's not represented in the encoding, the
563// auto-generated decoder won't inject the CPSR operand. We need to fix
564// that as a post-pass.
565static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]568 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]569 for (unsigned i = 0; i < NumOps; ++i, ++I) {
570 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]572 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
574 return;
575 }
576 }
577
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579}
580
581// Most Thumb instructions don't have explicit predicates in the
582// encoding, but rather get their predicates from IT context. We need
583// to fix up the predicate operands using this context information as a
584// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]585MCDisassembler::DecodeStatus
586ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]587 MCDisassembler::DecodeStatus S = Success;
588
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]589 // A few instructions actually have predicates encoded in them. Don't
590 // try to overwrite it if we're seeing one of those.
591 switch (MI.getOpcode()) {
592 case ARM::tBcc:
593 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]594 case ARM::tCBZ:
595 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]596 case ARM::tCPS:
597 case ARM::t2CPS3p:
598 case ARM::t2CPS2p:
599 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]600 case ARM::tMOVSr:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]601 // Some instructions (mostly conditional branches) are not
602 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]603 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]604 S = SoftFail;
605 else
606 return Success;
607 break;
608 case ARM::tB:
609 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]610 case ARM::t2TBB:
611 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]612 // Some instructions (mostly unconditional branches) can
613 // only appears at the end of, or outside of, an IT.
614 if (ITBlock.size() > 1)
615 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]616 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]617 default:
618 break;
619 }
620
621 // If we're in an IT block, base the predicate on that. Otherwise,
622 // assume a predicate of AL.
623 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]624 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]625 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]626 if (CC == 0xF)
627 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]628 ITBlock.pop_back();
629 } else
630 CC = ARMCC::AL;
631
632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]634 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]635 for (unsigned i = 0; i < NumOps; ++i, ++I) {
636 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 if (OpInfo[i].isPredicate()) {
638 I = MI.insert(I, MCOperand::CreateImm(CC));
639 ++I;
640 if (CC == ARMCC::AL)
641 MI.insert(I, MCOperand::CreateReg(0));
642 else
643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]644 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]645 }
646 }
647
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]648 I = MI.insert(I, MCOperand::CreateImm(CC));
649 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]650 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]651 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]652 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]654
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]655 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]656}
657
658// Thumb VFP instructions are a special case. Because we share their
659// encodings between ARM and Thumb modes, and they are predicable in ARM
660// mode, the auto-generated decoder will give them an (incorrect)
661// predicate operand. We need to rewrite these operands based on the IT
662// context as a post-pass.
663void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
664 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]665 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]666 CC = ITBlock.back();
667 ITBlock.pop_back();
668 } else
669 CC = ARMCC::AL;
670
671 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
672 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]673 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
674 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]675 if (OpInfo[i].isPredicate() ) {
676 I->setImm(CC);
677 ++I;
678 if (CC == ARMCC::AL)
679 I->setReg(0);
680 else
681 I->setReg(ARM::CPSR);
682 return;
683 }
684 }
685}
686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]687DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]688 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]689 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]690 raw_ostream &os,
691 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]692 CommentStream = &cs;
693
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]694 uint8_t bytes[4];
695
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]696 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
697 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
698
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]699 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]700 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
701 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]702 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]703 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704
705 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]706 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]707 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]708 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]709 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]710 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]711 }
712
713 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]714 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]715 if (result) {
716 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]717 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]718 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]719 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]720 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]721 }
722
723 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]724 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]725 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]726 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame^]727
728 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
729 // the Thumb predicate.
730 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
731 result = MCDisassembler::SoftFail;
732
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]733 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]734
735 // If we find an IT instruction, we need to parse its condition
736 // code and mask operands so that we can apply them correctly
737 // to the subsequent instructions.
738 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]739
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]740 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]741 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]742 unsigned Mask = MI.getOperand(1).getImm();
743 unsigned CondBit0 = Mask >> 4 & 1;
744 unsigned NumTZ = CountTrailingZeros_32(Mask);
745 assert(NumTZ <= 3 && "Invalid IT mask!");
746 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
747 bool T = ((Mask >> Pos) & 1) == CondBit0;
748 if (T)
749 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]750 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]751 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]752 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]753
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]754 ITBlock.push_back(firstcond);
755 }
756
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]757 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]758 }
759
760 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]761 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
762 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]763 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]764 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]765
766 uint32_t insn32 = (bytes[3] << 8) |
767 (bytes[2] << 0) |
768 (bytes[1] << 24) |
769 (bytes[0] << 16);
770 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]771 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]772 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]773 Size = 4;
774 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]775 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]776 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]777 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]778 }
779
780 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]781 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]782 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]784 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]785 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 }
787
788 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]789 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]790 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 Size = 4;
792 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]793 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 }
795
796 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]797 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]798 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]799 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]800 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]801 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]802 }
803
804 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
805 MI.clear();
806 uint32_t NEONLdStInsn = insn32;
807 NEONLdStInsn &= 0xF0FFFFFF;
808 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]809 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]810 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]811 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]812 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]813 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]814 }
815 }
816
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]817 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]818 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]819 uint32_t NEONDataInsn = insn32;
820 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
821 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
822 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]823 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]824 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]825 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]826 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]827 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]828 }
829 }
830
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]831 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]832 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833}
834
835
836extern "C" void LLVMInitializeARMDisassembler() {
837 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
838 createARMDisassembler);
839 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
840 createThumbDisassembler);
841}
842
843static const unsigned GPRDecoderTable[] = {
844 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
845 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
846 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
847 ARM::R12, ARM::SP, ARM::LR, ARM::PC
848};
849
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]850static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]851 uint64_t Address, const void *Decoder) {
852 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]853 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854
855 unsigned Register = GPRDecoderTable[RegNo];
856 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]857 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]858}
859
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]860static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]861DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
862 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]863 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]864 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
865}
866
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]867static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]868 uint64_t Address, const void *Decoder) {
869 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]870 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]871 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
872}
873
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]874static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]875 uint64_t Address, const void *Decoder) {
876 unsigned Register = 0;
877 switch (RegNo) {
878 case 0:
879 Register = ARM::R0;
880 break;
881 case 1:
882 Register = ARM::R1;
883 break;
884 case 2:
885 Register = ARM::R2;
886 break;
887 case 3:
888 Register = ARM::R3;
889 break;
890 case 9:
891 Register = ARM::R9;
892 break;
893 case 12:
894 Register = ARM::R12;
895 break;
896 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]897 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]898 }
899
900 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]901 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]902}
903
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]904static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]905 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]906 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]907 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
908}
909
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]910static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]911 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
912 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
913 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
914 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
915 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
916 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
917 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
918 ARM::S28, ARM::S29, ARM::S30, ARM::S31
919};
920
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]921static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]922 uint64_t Address, const void *Decoder) {
923 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]924 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925
926 unsigned Register = SPRDecoderTable[RegNo];
927 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]928 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929}
930
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]931static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]932 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
933 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
934 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
935 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
936 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
937 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
938 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
939 ARM::D28, ARM::D29, ARM::D30, ARM::D31
940};
941
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]942static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]943 uint64_t Address, const void *Decoder) {
944 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]945 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946
947 unsigned Register = DPRDecoderTable[RegNo];
948 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]949 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]950}
951
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]952static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]953 uint64_t Address, const void *Decoder) {
954 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]955 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]956 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
957}
958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]959static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]960DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
961 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]962 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]963 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]964 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
965}
966
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]967static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
969 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
970 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
971 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
972};
973
974
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]975static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]976 uint64_t Address, const void *Decoder) {
977 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]978 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]979 RegNo >>= 1;
980
981 unsigned Register = QPRDecoderTable[RegNo];
982 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]983 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984}
985
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]986static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]987 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]988 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]989 // AL predicate is not allowed on Thumb1 branches.
990 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]991 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]992 Inst.addOperand(MCOperand::CreateImm(Val));
993 if (Val == ARMCC::AL) {
994 Inst.addOperand(MCOperand::CreateReg(0));
995 } else
996 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]997 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]998}
999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1000static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1001 uint64_t Address, const void *Decoder) {
1002 if (Val)
1003 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1004 else
1005 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1006 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1007}
1008
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1009static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1010 uint64_t Address, const void *Decoder) {
1011 uint32_t imm = Val & 0xFF;
1012 uint32_t rot = (Val & 0xF00) >> 7;
1013 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
1014 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1015 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1016}
1017
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1018static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1019 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1020 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1021
1022 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1023 unsigned type = fieldFromInstruction32(Val, 5, 2);
1024 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1025
1026 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1028 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1029
1030 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1031 switch (type) {
1032 case 0:
1033 Shift = ARM_AM::lsl;
1034 break;
1035 case 1:
1036 Shift = ARM_AM::lsr;
1037 break;
1038 case 2:
1039 Shift = ARM_AM::asr;
1040 break;
1041 case 3:
1042 Shift = ARM_AM::ror;
1043 break;
1044 }
1045
1046 if (Shift == ARM_AM::ror && imm == 0)
1047 Shift = ARM_AM::rrx;
1048
1049 unsigned Op = Shift | (imm << 3);
1050 Inst.addOperand(MCOperand::CreateImm(Op));
1051
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1052 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1053}
1054
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1055static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1056 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1057 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1058
1059 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1060 unsigned type = fieldFromInstruction32(Val, 5, 2);
1061 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1062
1063 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1065 return MCDisassembler::Fail;
1066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1067 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1068
1069 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1070 switch (type) {
1071 case 0:
1072 Shift = ARM_AM::lsl;
1073 break;
1074 case 1:
1075 Shift = ARM_AM::lsr;
1076 break;
1077 case 2:
1078 Shift = ARM_AM::asr;
1079 break;
1080 case 3:
1081 Shift = ARM_AM::ror;
1082 break;
1083 }
1084
1085 Inst.addOperand(MCOperand::CreateImm(Shift));
1086
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1087 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1088}
1089
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1090static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1091 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1092 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1093
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1094 bool writebackLoad = false;
1095 unsigned writebackReg = 0;
1096 switch (Inst.getOpcode()) {
1097 default:
1098 break;
1099 case ARM::LDMIA_UPD:
1100 case ARM::LDMDB_UPD:
1101 case ARM::LDMIB_UPD:
1102 case ARM::LDMDA_UPD:
1103 case ARM::t2LDMIA_UPD:
1104 case ARM::t2LDMDB_UPD:
1105 writebackLoad = true;
1106 writebackReg = Inst.getOperand(0).getReg();
1107 break;
1108 }
1109
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1110 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1111 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1113 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1114 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1115 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1116 // Writeback not allowed if Rn is in the target list.
1117 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1118 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1119 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1120 }
1121
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1122 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1123}
1124
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1125static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1126 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1127 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1128
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1129 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1130 unsigned regs = Val & 0xFF;
1131
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1132 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1133 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1134 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1135 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1136 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1137 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1138
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1139 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1140}
1141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1142static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1143 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1144 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1145
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1146 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1147 unsigned regs = (Val & 0xFF) / 2;
1148
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1149 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1150 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1151 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1152 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1153 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1154 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1155
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1156 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1157}
1158
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1159static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1160 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1161 // This operand encodes a mask of contiguous zeros between a specified MSB
1162 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1163 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1164 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1165 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1166 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1167 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1168
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1169 DecodeStatus S = MCDisassembler::Success;
1170 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1171
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1172 uint32_t msb_mask = 0xFFFFFFFF;
1173 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1174 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1175
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1176 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1177 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1178}
1179
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1180static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1181 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1182 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1183
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1184 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1185 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1186 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1187 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1188 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1189 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1190
1191 switch (Inst.getOpcode()) {
1192 case ARM::LDC_OFFSET:
1193 case ARM::LDC_PRE:
1194 case ARM::LDC_POST:
1195 case ARM::LDC_OPTION:
1196 case ARM::LDCL_OFFSET:
1197 case ARM::LDCL_PRE:
1198 case ARM::LDCL_POST:
1199 case ARM::LDCL_OPTION:
1200 case ARM::STC_OFFSET:
1201 case ARM::STC_PRE:
1202 case ARM::STC_POST:
1203 case ARM::STC_OPTION:
1204 case ARM::STCL_OFFSET:
1205 case ARM::STCL_PRE:
1206 case ARM::STCL_POST:
1207 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1208 case ARM::t2LDC_OFFSET:
1209 case ARM::t2LDC_PRE:
1210 case ARM::t2LDC_POST:
1211 case ARM::t2LDC_OPTION:
1212 case ARM::t2LDCL_OFFSET:
1213 case ARM::t2LDCL_PRE:
1214 case ARM::t2LDCL_POST:
1215 case ARM::t2LDCL_OPTION:
1216 case ARM::t2STC_OFFSET:
1217 case ARM::t2STC_PRE:
1218 case ARM::t2STC_POST:
1219 case ARM::t2STC_OPTION:
1220 case ARM::t2STCL_OFFSET:
1221 case ARM::t2STCL_PRE:
1222 case ARM::t2STCL_POST:
1223 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1225 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1226 break;
1227 default:
1228 break;
1229 }
1230
1231 Inst.addOperand(MCOperand::CreateImm(coproc));
1232 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1234 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235 switch (Inst.getOpcode()) {
1236 case ARM::LDC_OPTION:
1237 case ARM::LDCL_OPTION:
1238 case ARM::LDC2_OPTION:
1239 case ARM::LDC2L_OPTION:
1240 case ARM::STC_OPTION:
1241 case ARM::STCL_OPTION:
1242 case ARM::STC2_OPTION:
1243 case ARM::STC2L_OPTION:
1244 case ARM::LDCL_POST:
1245 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1246 case ARM::LDC2L_POST:
1247 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1248 case ARM::t2LDC_OPTION:
1249 case ARM::t2LDCL_OPTION:
1250 case ARM::t2STC_OPTION:
1251 case ARM::t2STCL_OPTION:
1252 case ARM::t2LDCL_POST:
1253 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1254 break;
1255 default:
1256 Inst.addOperand(MCOperand::CreateReg(0));
1257 break;
1258 }
1259
1260 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1261 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1262
1263 bool writeback = (P == 0) || (W == 1);
1264 unsigned idx_mode = 0;
1265 if (P && writeback)
1266 idx_mode = ARMII::IndexModePre;
1267 else if (!P && writeback)
1268 idx_mode = ARMII::IndexModePost;
1269
1270 switch (Inst.getOpcode()) {
1271 case ARM::LDCL_POST:
1272 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1273 case ARM::t2LDCL_POST:
1274 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1275 case ARM::LDC2L_POST:
1276 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1277 imm |= U << 8;
1278 case ARM::LDC_OPTION:
1279 case ARM::LDCL_OPTION:
1280 case ARM::LDC2_OPTION:
1281 case ARM::LDC2L_OPTION:
1282 case ARM::STC_OPTION:
1283 case ARM::STCL_OPTION:
1284 case ARM::STC2_OPTION:
1285 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1286 case ARM::t2LDC_OPTION:
1287 case ARM::t2LDCL_OPTION:
1288 case ARM::t2STC_OPTION:
1289 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1290 Inst.addOperand(MCOperand::CreateImm(imm));
1291 break;
1292 default:
1293 if (U)
1294 Inst.addOperand(MCOperand::CreateImm(
1295 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1296 else
1297 Inst.addOperand(MCOperand::CreateImm(
1298 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1299 break;
1300 }
1301
1302 switch (Inst.getOpcode()) {
1303 case ARM::LDC_OFFSET:
1304 case ARM::LDC_PRE:
1305 case ARM::LDC_POST:
1306 case ARM::LDC_OPTION:
1307 case ARM::LDCL_OFFSET:
1308 case ARM::LDCL_PRE:
1309 case ARM::LDCL_POST:
1310 case ARM::LDCL_OPTION:
1311 case ARM::STC_OFFSET:
1312 case ARM::STC_PRE:
1313 case ARM::STC_POST:
1314 case ARM::STC_OPTION:
1315 case ARM::STCL_OFFSET:
1316 case ARM::STCL_PRE:
1317 case ARM::STCL_POST:
1318 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1319 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1320 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1321 break;
1322 default:
1323 break;
1324 }
1325
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1326 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1327}
1328
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1329static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1330DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1331 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1332 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1333
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1334 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1335 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1336 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1337 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1338 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1339 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1340 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1341 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1342
1343 // On stores, the writeback operand precedes Rt.
1344 switch (Inst.getOpcode()) {
1345 case ARM::STR_POST_IMM:
1346 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1347 case ARM::STRB_POST_IMM:
1348 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1349 case ARM::STRT_POST_REG:
1350 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1351 case ARM::STRBT_POST_REG:
1352 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1354 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1355 break;
1356 default:
1357 break;
1358 }
1359
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1361 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1362
1363 // On loads, the writeback operand comes after Rt.
1364 switch (Inst.getOpcode()) {
1365 case ARM::LDR_POST_IMM:
1366 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1367 case ARM::LDRB_POST_IMM:
1368 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1369 case ARM::LDRBT_POST_REG:
1370 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1371 case ARM::LDRT_POST_REG:
1372 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1374 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1375 break;
1376 default:
1377 break;
1378 }
1379
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1381 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1382
1383 ARM_AM::AddrOpc Op = ARM_AM::add;
1384 if (!fieldFromInstruction32(Insn, 23, 1))
1385 Op = ARM_AM::sub;
1386
1387 bool writeback = (P == 0) || (W == 1);
1388 unsigned idx_mode = 0;
1389 if (P && writeback)
1390 idx_mode = ARMII::IndexModePre;
1391 else if (!P && writeback)
1392 idx_mode = ARMII::IndexModePost;
1393
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1394 if (writeback && (Rn == 15 || Rn == Rt))
1395 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1396
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1397 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1398 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1399 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1400 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1401 switch( fieldFromInstruction32(Insn, 5, 2)) {
1402 case 0:
1403 Opc = ARM_AM::lsl;
1404 break;
1405 case 1:
1406 Opc = ARM_AM::lsr;
1407 break;
1408 case 2:
1409 Opc = ARM_AM::asr;
1410 break;
1411 case 3:
1412 Opc = ARM_AM::ror;
1413 break;
1414 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1415 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1416 }
1417 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1418 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1419
1420 Inst.addOperand(MCOperand::CreateImm(imm));
1421 } else {
1422 Inst.addOperand(MCOperand::CreateReg(0));
1423 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1424 Inst.addOperand(MCOperand::CreateImm(tmp));
1425 }
1426
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1427 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1428 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1429
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1430 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1431}
1432
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1433static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1434 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1435 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1436
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1437 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1438 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1439 unsigned type = fieldFromInstruction32(Val, 5, 2);
1440 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1441 unsigned U = fieldFromInstruction32(Val, 12, 1);
1442
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1443 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1444 switch (type) {
1445 case 0:
1446 ShOp = ARM_AM::lsl;
1447 break;
1448 case 1:
1449 ShOp = ARM_AM::lsr;
1450 break;
1451 case 2:
1452 ShOp = ARM_AM::asr;
1453 break;
1454 case 3:
1455 ShOp = ARM_AM::ror;
1456 break;
1457 }
1458
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1460 return MCDisassembler::Fail;
1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1462 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1463 unsigned shift;
1464 if (U)
1465 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1466 else
1467 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1468 Inst.addOperand(MCOperand::CreateImm(shift));
1469
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1470 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1471}
1472
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1473static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1474DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1475 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1476 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1477
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1478 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1479 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1480 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1481 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1482 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1483 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1484 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1485 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1486 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1487
1488 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1489
1490 // For {LD,ST}RD, Rt must be even, else undefined.
1491 switch (Inst.getOpcode()) {
1492 case ARM::STRD:
1493 case ARM::STRD_PRE:
1494 case ARM::STRD_POST:
1495 case ARM::LDRD:
1496 case ARM::LDRD_PRE:
1497 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1498 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1499 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1500 default:
1501 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1502 }
1503
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1504 if (writeback) { // Writeback
1505 if (P)
1506 U |= ARMII::IndexModePre << 9;
1507 else
1508 U |= ARMII::IndexModePost << 9;
1509
1510 // On stores, the writeback operand precedes Rt.
1511 switch (Inst.getOpcode()) {
1512 case ARM::STRD:
1513 case ARM::STRD_PRE:
1514 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1515 case ARM::STRH:
1516 case ARM::STRH_PRE:
1517 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1519 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1520 break;
1521 default:
1522 break;
1523 }
1524 }
1525
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1526 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1527 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1528 switch (Inst.getOpcode()) {
1529 case ARM::STRD:
1530 case ARM::STRD_PRE:
1531 case ARM::STRD_POST:
1532 case ARM::LDRD:
1533 case ARM::LDRD_PRE:
1534 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1536 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1537 break;
1538 default:
1539 break;
1540 }
1541
1542 if (writeback) {
1543 // On loads, the writeback operand comes after Rt.
1544 switch (Inst.getOpcode()) {
1545 case ARM::LDRD:
1546 case ARM::LDRD_PRE:
1547 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1548 case ARM::LDRH:
1549 case ARM::LDRH_PRE:
1550 case ARM::LDRH_POST:
1551 case ARM::LDRSH:
1552 case ARM::LDRSH_PRE:
1553 case ARM::LDRSH_POST:
1554 case ARM::LDRSB:
1555 case ARM::LDRSB_PRE:
1556 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1557 case ARM::LDRHTr:
1558 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1559 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1560 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1561 break;
1562 default:
1563 break;
1564 }
1565 }
1566
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1568 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1569
1570 if (type) {
1571 Inst.addOperand(MCOperand::CreateReg(0));
1572 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1573 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1575 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1576 Inst.addOperand(MCOperand::CreateImm(U));
1577 }
1578
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1579 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1580 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1581
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1582 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1583}
1584
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1585static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1586 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1587 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1588
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1589 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1590 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1591
1592 switch (mode) {
1593 case 0:
1594 mode = ARM_AM::da;
1595 break;
1596 case 1:
1597 mode = ARM_AM::ia;
1598 break;
1599 case 2:
1600 mode = ARM_AM::db;
1601 break;
1602 case 3:
1603 mode = ARM_AM::ib;
1604 break;
1605 }
1606
1607 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1609 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1610
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1611 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1612}
1613
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1614static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1615 unsigned Insn,
1616 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1617 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1618
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1619 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1620 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1621 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1622
1623 if (pred == 0xF) {
1624 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1625 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1626 Inst.setOpcode(ARM::RFEDA);
1627 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1628 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1629 Inst.setOpcode(ARM::RFEDA_UPD);
1630 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1631 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1632 Inst.setOpcode(ARM::RFEDB);
1633 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1634 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1635 Inst.setOpcode(ARM::RFEDB_UPD);
1636 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1637 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1638 Inst.setOpcode(ARM::RFEIA);
1639 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1640 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1641 Inst.setOpcode(ARM::RFEIA_UPD);
1642 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1643 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1644 Inst.setOpcode(ARM::RFEIB);
1645 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1646 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1647 Inst.setOpcode(ARM::RFEIB_UPD);
1648 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1649 case ARM::STMDA:
1650 Inst.setOpcode(ARM::SRSDA);
1651 break;
1652 case ARM::STMDA_UPD:
1653 Inst.setOpcode(ARM::SRSDA_UPD);
1654 break;
1655 case ARM::STMDB:
1656 Inst.setOpcode(ARM::SRSDB);
1657 break;
1658 case ARM::STMDB_UPD:
1659 Inst.setOpcode(ARM::SRSDB_UPD);
1660 break;
1661 case ARM::STMIA:
1662 Inst.setOpcode(ARM::SRSIA);
1663 break;
1664 case ARM::STMIA_UPD:
1665 Inst.setOpcode(ARM::SRSIA_UPD);
1666 break;
1667 case ARM::STMIB:
1668 Inst.setOpcode(ARM::SRSIB);
1669 break;
1670 case ARM::STMIB_UPD:
1671 Inst.setOpcode(ARM::SRSIB_UPD);
1672 break;
1673 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1674 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1675 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1676
1677 // For stores (which become SRS's, the only operand is the mode.
1678 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1679 Inst.addOperand(
1680 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1681 return S;
1682 }
1683
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1684 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1685 }
1686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1688 return MCDisassembler::Fail;
1689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1690 return MCDisassembler::Fail; // Tied
1691 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1692 return MCDisassembler::Fail;
1693 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1694 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1695
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1696 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1697}
1698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1699static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1700 uint64_t Address, const void *Decoder) {
1701 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1702 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1703 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1704 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1705
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1706 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1707
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1708 // imod == '01' --> UNPREDICTABLE
1709 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1710 // return failure here. The '01' imod value is unprintable, so there's
1711 // nothing useful we could do even if we returned UNPREDICTABLE.
1712
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1713 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1714
1715 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1716 Inst.setOpcode(ARM::CPS3p);
1717 Inst.addOperand(MCOperand::CreateImm(imod));
1718 Inst.addOperand(MCOperand::CreateImm(iflags));
1719 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1720 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1721 Inst.setOpcode(ARM::CPS2p);
1722 Inst.addOperand(MCOperand::CreateImm(imod));
1723 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1724 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1725 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1726 Inst.setOpcode(ARM::CPS1p);
1727 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1728 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1729 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1730 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1731 Inst.setOpcode(ARM::CPS1p);
1732 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1733 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1734 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1735
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1736 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1737}
1738
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1739static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1740 uint64_t Address, const void *Decoder) {
1741 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1742 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1743 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1744 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1745
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1746 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1747
1748 // imod == '01' --> UNPREDICTABLE
1749 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1750 // return failure here. The '01' imod value is unprintable, so there's
1751 // nothing useful we could do even if we returned UNPREDICTABLE.
1752
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1753 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1754
1755 if (imod && M) {
1756 Inst.setOpcode(ARM::t2CPS3p);
1757 Inst.addOperand(MCOperand::CreateImm(imod));
1758 Inst.addOperand(MCOperand::CreateImm(iflags));
1759 Inst.addOperand(MCOperand::CreateImm(mode));
1760 } else if (imod && !M) {
1761 Inst.setOpcode(ARM::t2CPS2p);
1762 Inst.addOperand(MCOperand::CreateImm(imod));
1763 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1764 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1765 } else if (!imod && M) {
1766 Inst.setOpcode(ARM::t2CPS1p);
1767 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1768 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1769 } else {
1770 // imod == '00' && M == '0' --> UNPREDICTABLE
1771 Inst.setOpcode(ARM::t2CPS1p);
1772 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1773 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1774 }
1775
1776 return S;
1777}
1778
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1779static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1780 uint64_t Address, const void *Decoder) {
1781 DecodeStatus S = MCDisassembler::Success;
1782
1783 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1784 unsigned imm = 0;
1785
1786 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1787 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1788 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1789 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1790
1791 if (Inst.getOpcode() == ARM::t2MOVTi16)
1792 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1793 return MCDisassembler::Fail;
1794 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1795 return MCDisassembler::Fail;
1796
1797 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1798 Inst.addOperand(MCOperand::CreateImm(imm));
1799
1800 return S;
1801}
1802
1803static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1804 uint64_t Address, const void *Decoder) {
1805 DecodeStatus S = MCDisassembler::Success;
1806
1807 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1808 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1809 unsigned imm = 0;
1810
1811 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1812 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1813
1814 if (Inst.getOpcode() == ARM::MOVTi16)
1815 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1816 return MCDisassembler::Fail;
1817 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1818 return MCDisassembler::Fail;
1819
1820 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1821 Inst.addOperand(MCOperand::CreateImm(imm));
1822
1823 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1824 return MCDisassembler::Fail;
1825
1826 return S;
1827}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1828
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1829static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1830 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1831 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1832
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1833 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1834 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1835 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1836 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1837 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1838
1839 if (pred == 0xF)
1840 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1841
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1843 return MCDisassembler::Fail;
1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1847 return MCDisassembler::Fail;
1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1849 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1850
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1851 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1852 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1853
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1854 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1855}
1856
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1857static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1858 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1859 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1860
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1861 unsigned add = fieldFromInstruction32(Val, 12, 1);
1862 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1863 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1864
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1866 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1867
1868 if (!add) imm *= -1;
1869 if (imm == 0 && !add) imm = INT32_MIN;
1870 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1871 if (Rn == 15)
1872 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1873
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1874 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1875}
1876
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1877static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1878 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1879 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1880
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1881 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1882 unsigned U = fieldFromInstruction32(Val, 8, 1);
1883 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1884
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1885 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1886 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1887
1888 if (U)
1889 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1890 else
1891 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1892
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1893 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1894}
1895
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1896static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1897 uint64_t Address, const void *Decoder) {
1898 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1899}
1900
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1901static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1902DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1903 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1904 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1905
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1906 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1907 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1908
1909 if (pred == 0xF) {
1910 Inst.setOpcode(ARM::BLXi);
1911 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1912 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1913 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1914 }
1915
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1916 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1917 4, Inst, Decoder))
1918 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1919 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1920 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1921
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1922 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1923}
1924
1925
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1926static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1927 uint64_t Address, const void *Decoder) {
1928 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1929 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1930}
1931
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1932static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1933 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1934 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1935
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1936 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1937 unsigned align = fieldFromInstruction32(Val, 4, 2);
1938
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1940 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1941 if (!align)
1942 Inst.addOperand(MCOperand::CreateImm(0));
1943 else
1944 Inst.addOperand(MCOperand::CreateImm(4 << align));
1945
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1946 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1947}
1948
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1949static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1950 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1951 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1952
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1953 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1954 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1955 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1956 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1957 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1958 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1959
1960 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1961 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1962 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1963
1964 // Second output register
1965 switch (Inst.getOpcode()) {
1966 case ARM::VLD1q8:
1967 case ARM::VLD1q16:
1968 case ARM::VLD1q32:
1969 case ARM::VLD1q64:
1970 case ARM::VLD1q8_UPD:
1971 case ARM::VLD1q16_UPD:
1972 case ARM::VLD1q32_UPD:
1973 case ARM::VLD1q64_UPD:
1974 case ARM::VLD1d8T:
1975 case ARM::VLD1d16T:
1976 case ARM::VLD1d32T:
1977 case ARM::VLD1d64T:
1978 case ARM::VLD1d8T_UPD:
1979 case ARM::VLD1d16T_UPD:
1980 case ARM::VLD1d32T_UPD:
1981 case ARM::VLD1d64T_UPD:
1982 case ARM::VLD1d8Q:
1983 case ARM::VLD1d16Q:
1984 case ARM::VLD1d32Q:
1985 case ARM::VLD1d64Q:
1986 case ARM::VLD1d8Q_UPD:
1987 case ARM::VLD1d16Q_UPD:
1988 case ARM::VLD1d32Q_UPD:
1989 case ARM::VLD1d64Q_UPD:
1990 case ARM::VLD2d8:
1991 case ARM::VLD2d16:
1992 case ARM::VLD2d32:
1993 case ARM::VLD2d8_UPD:
1994 case ARM::VLD2d16_UPD:
1995 case ARM::VLD2d32_UPD:
1996 case ARM::VLD2q8:
1997 case ARM::VLD2q16:
1998 case ARM::VLD2q32:
1999 case ARM::VLD2q8_UPD:
2000 case ARM::VLD2q16_UPD:
2001 case ARM::VLD2q32_UPD:
2002 case ARM::VLD3d8:
2003 case ARM::VLD3d16:
2004 case ARM::VLD3d32:
2005 case ARM::VLD3d8_UPD:
2006 case ARM::VLD3d16_UPD:
2007 case ARM::VLD3d32_UPD:
2008 case ARM::VLD4d8:
2009 case ARM::VLD4d16:
2010 case ARM::VLD4d32:
2011 case ARM::VLD4d8_UPD:
2012 case ARM::VLD4d16_UPD:
2013 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2014 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2015 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2016 break;
2017 case ARM::VLD2b8:
2018 case ARM::VLD2b16:
2019 case ARM::VLD2b32:
2020 case ARM::VLD2b8_UPD:
2021 case ARM::VLD2b16_UPD:
2022 case ARM::VLD2b32_UPD:
2023 case ARM::VLD3q8:
2024 case ARM::VLD3q16:
2025 case ARM::VLD3q32:
2026 case ARM::VLD3q8_UPD:
2027 case ARM::VLD3q16_UPD:
2028 case ARM::VLD3q32_UPD:
2029 case ARM::VLD4q8:
2030 case ARM::VLD4q16:
2031 case ARM::VLD4q32:
2032 case ARM::VLD4q8_UPD:
2033 case ARM::VLD4q16_UPD:
2034 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2035 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2036 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2037 default:
2038 break;
2039 }
2040
2041 // Third output register
2042 switch(Inst.getOpcode()) {
2043 case ARM::VLD1d8T:
2044 case ARM::VLD1d16T:
2045 case ARM::VLD1d32T:
2046 case ARM::VLD1d64T:
2047 case ARM::VLD1d8T_UPD:
2048 case ARM::VLD1d16T_UPD:
2049 case ARM::VLD1d32T_UPD:
2050 case ARM::VLD1d64T_UPD:
2051 case ARM::VLD1d8Q:
2052 case ARM::VLD1d16Q:
2053 case ARM::VLD1d32Q:
2054 case ARM::VLD1d64Q:
2055 case ARM::VLD1d8Q_UPD:
2056 case ARM::VLD1d16Q_UPD:
2057 case ARM::VLD1d32Q_UPD:
2058 case ARM::VLD1d64Q_UPD:
2059 case ARM::VLD2q8:
2060 case ARM::VLD2q16:
2061 case ARM::VLD2q32:
2062 case ARM::VLD2q8_UPD:
2063 case ARM::VLD2q16_UPD:
2064 case ARM::VLD2q32_UPD:
2065 case ARM::VLD3d8:
2066 case ARM::VLD3d16:
2067 case ARM::VLD3d32:
2068 case ARM::VLD3d8_UPD:
2069 case ARM::VLD3d16_UPD:
2070 case ARM::VLD3d32_UPD:
2071 case ARM::VLD4d8:
2072 case ARM::VLD4d16:
2073 case ARM::VLD4d32:
2074 case ARM::VLD4d8_UPD:
2075 case ARM::VLD4d16_UPD:
2076 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2077 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2078 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2079 break;
2080 case ARM::VLD3q8:
2081 case ARM::VLD3q16:
2082 case ARM::VLD3q32:
2083 case ARM::VLD3q8_UPD:
2084 case ARM::VLD3q16_UPD:
2085 case ARM::VLD3q32_UPD:
2086 case ARM::VLD4q8:
2087 case ARM::VLD4q16:
2088 case ARM::VLD4q32:
2089 case ARM::VLD4q8_UPD:
2090 case ARM::VLD4q16_UPD:
2091 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2092 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2093 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2094 break;
2095 default:
2096 break;
2097 }
2098
2099 // Fourth output register
2100 switch (Inst.getOpcode()) {
2101 case ARM::VLD1d8Q:
2102 case ARM::VLD1d16Q:
2103 case ARM::VLD1d32Q:
2104 case ARM::VLD1d64Q:
2105 case ARM::VLD1d8Q_UPD:
2106 case ARM::VLD1d16Q_UPD:
2107 case ARM::VLD1d32Q_UPD:
2108 case ARM::VLD1d64Q_UPD:
2109 case ARM::VLD2q8:
2110 case ARM::VLD2q16:
2111 case ARM::VLD2q32:
2112 case ARM::VLD2q8_UPD:
2113 case ARM::VLD2q16_UPD:
2114 case ARM::VLD2q32_UPD:
2115 case ARM::VLD4d8:
2116 case ARM::VLD4d16:
2117 case ARM::VLD4d32:
2118 case ARM::VLD4d8_UPD:
2119 case ARM::VLD4d16_UPD:
2120 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2121 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2122 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2123 break;
2124 case ARM::VLD4q8:
2125 case ARM::VLD4q16:
2126 case ARM::VLD4q32:
2127 case ARM::VLD4q8_UPD:
2128 case ARM::VLD4q16_UPD:
2129 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2130 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2131 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2132 break;
2133 default:
2134 break;
2135 }
2136
2137 // Writeback operand
2138 switch (Inst.getOpcode()) {
2139 case ARM::VLD1d8_UPD:
2140 case ARM::VLD1d16_UPD:
2141 case ARM::VLD1d32_UPD:
2142 case ARM::VLD1d64_UPD:
2143 case ARM::VLD1q8_UPD:
2144 case ARM::VLD1q16_UPD:
2145 case ARM::VLD1q32_UPD:
2146 case ARM::VLD1q64_UPD:
2147 case ARM::VLD1d8T_UPD:
2148 case ARM::VLD1d16T_UPD:
2149 case ARM::VLD1d32T_UPD:
2150 case ARM::VLD1d64T_UPD:
2151 case ARM::VLD1d8Q_UPD:
2152 case ARM::VLD1d16Q_UPD:
2153 case ARM::VLD1d32Q_UPD:
2154 case ARM::VLD1d64Q_UPD:
2155 case ARM::VLD2d8_UPD:
2156 case ARM::VLD2d16_UPD:
2157 case ARM::VLD2d32_UPD:
2158 case ARM::VLD2q8_UPD:
2159 case ARM::VLD2q16_UPD:
2160 case ARM::VLD2q32_UPD:
2161 case ARM::VLD2b8_UPD:
2162 case ARM::VLD2b16_UPD:
2163 case ARM::VLD2b32_UPD:
2164 case ARM::VLD3d8_UPD:
2165 case ARM::VLD3d16_UPD:
2166 case ARM::VLD3d32_UPD:
2167 case ARM::VLD3q8_UPD:
2168 case ARM::VLD3q16_UPD:
2169 case ARM::VLD3q32_UPD:
2170 case ARM::VLD4d8_UPD:
2171 case ARM::VLD4d16_UPD:
2172 case ARM::VLD4d32_UPD:
2173 case ARM::VLD4q8_UPD:
2174 case ARM::VLD4q16_UPD:
2175 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2176 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2177 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2178 break;
2179 default:
2180 break;
2181 }
2182
2183 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2184 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2185 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2186
2187 // AddrMode6 Offset (register)
2188 if (Rm == 0xD)
2189 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2190 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2192 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2193 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2194
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2195 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2196}
2197
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2198static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2199 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2200 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2201
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2202 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2203 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2204 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2205 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2206 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2207 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2208
2209 // Writeback Operand
2210 switch (Inst.getOpcode()) {
2211 case ARM::VST1d8_UPD:
2212 case ARM::VST1d16_UPD:
2213 case ARM::VST1d32_UPD:
2214 case ARM::VST1d64_UPD:
2215 case ARM::VST1q8_UPD:
2216 case ARM::VST1q16_UPD:
2217 case ARM::VST1q32_UPD:
2218 case ARM::VST1q64_UPD:
2219 case ARM::VST1d8T_UPD:
2220 case ARM::VST1d16T_UPD:
2221 case ARM::VST1d32T_UPD:
2222 case ARM::VST1d64T_UPD:
2223 case ARM::VST1d8Q_UPD:
2224 case ARM::VST1d16Q_UPD:
2225 case ARM::VST1d32Q_UPD:
2226 case ARM::VST1d64Q_UPD:
2227 case ARM::VST2d8_UPD:
2228 case ARM::VST2d16_UPD:
2229 case ARM::VST2d32_UPD:
2230 case ARM::VST2q8_UPD:
2231 case ARM::VST2q16_UPD:
2232 case ARM::VST2q32_UPD:
2233 case ARM::VST2b8_UPD:
2234 case ARM::VST2b16_UPD:
2235 case ARM::VST2b32_UPD:
2236 case ARM::VST3d8_UPD:
2237 case ARM::VST3d16_UPD:
2238 case ARM::VST3d32_UPD:
2239 case ARM::VST3q8_UPD:
2240 case ARM::VST3q16_UPD:
2241 case ARM::VST3q32_UPD:
2242 case ARM::VST4d8_UPD:
2243 case ARM::VST4d16_UPD:
2244 case ARM::VST4d32_UPD:
2245 case ARM::VST4q8_UPD:
2246 case ARM::VST4q16_UPD:
2247 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2248 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2249 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2250 break;
2251 default:
2252 break;
2253 }
2254
2255 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2256 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2257 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2258
2259 // AddrMode6 Offset (register)
2260 if (Rm == 0xD)
2261 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2262 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2264 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2265 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2266
2267 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2268 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2269 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2270
2271 // Second input register
2272 switch (Inst.getOpcode()) {
2273 case ARM::VST1q8:
2274 case ARM::VST1q16:
2275 case ARM::VST1q32:
2276 case ARM::VST1q64:
2277 case ARM::VST1q8_UPD:
2278 case ARM::VST1q16_UPD:
2279 case ARM::VST1q32_UPD:
2280 case ARM::VST1q64_UPD:
2281 case ARM::VST1d8T:
2282 case ARM::VST1d16T:
2283 case ARM::VST1d32T:
2284 case ARM::VST1d64T:
2285 case ARM::VST1d8T_UPD:
2286 case ARM::VST1d16T_UPD:
2287 case ARM::VST1d32T_UPD:
2288 case ARM::VST1d64T_UPD:
2289 case ARM::VST1d8Q:
2290 case ARM::VST1d16Q:
2291 case ARM::VST1d32Q:
2292 case ARM::VST1d64Q:
2293 case ARM::VST1d8Q_UPD:
2294 case ARM::VST1d16Q_UPD:
2295 case ARM::VST1d32Q_UPD:
2296 case ARM::VST1d64Q_UPD:
2297 case ARM::VST2d8:
2298 case ARM::VST2d16:
2299 case ARM::VST2d32:
2300 case ARM::VST2d8_UPD:
2301 case ARM::VST2d16_UPD:
2302 case ARM::VST2d32_UPD:
2303 case ARM::VST2q8:
2304 case ARM::VST2q16:
2305 case ARM::VST2q32:
2306 case ARM::VST2q8_UPD:
2307 case ARM::VST2q16_UPD:
2308 case ARM::VST2q32_UPD:
2309 case ARM::VST3d8:
2310 case ARM::VST3d16:
2311 case ARM::VST3d32:
2312 case ARM::VST3d8_UPD:
2313 case ARM::VST3d16_UPD:
2314 case ARM::VST3d32_UPD:
2315 case ARM::VST4d8:
2316 case ARM::VST4d16:
2317 case ARM::VST4d32:
2318 case ARM::VST4d8_UPD:
2319 case ARM::VST4d16_UPD:
2320 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2321 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2322 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2323 break;
2324 case ARM::VST2b8:
2325 case ARM::VST2b16:
2326 case ARM::VST2b32:
2327 case ARM::VST2b8_UPD:
2328 case ARM::VST2b16_UPD:
2329 case ARM::VST2b32_UPD:
2330 case ARM::VST3q8:
2331 case ARM::VST3q16:
2332 case ARM::VST3q32:
2333 case ARM::VST3q8_UPD:
2334 case ARM::VST3q16_UPD:
2335 case ARM::VST3q32_UPD:
2336 case ARM::VST4q8:
2337 case ARM::VST4q16:
2338 case ARM::VST4q32:
2339 case ARM::VST4q8_UPD:
2340 case ARM::VST4q16_UPD:
2341 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2342 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2343 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2344 break;
2345 default:
2346 break;
2347 }
2348
2349 // Third input register
2350 switch (Inst.getOpcode()) {
2351 case ARM::VST1d8T:
2352 case ARM::VST1d16T:
2353 case ARM::VST1d32T:
2354 case ARM::VST1d64T:
2355 case ARM::VST1d8T_UPD:
2356 case ARM::VST1d16T_UPD:
2357 case ARM::VST1d32T_UPD:
2358 case ARM::VST1d64T_UPD:
2359 case ARM::VST1d8Q:
2360 case ARM::VST1d16Q:
2361 case ARM::VST1d32Q:
2362 case ARM::VST1d64Q:
2363 case ARM::VST1d8Q_UPD:
2364 case ARM::VST1d16Q_UPD:
2365 case ARM::VST1d32Q_UPD:
2366 case ARM::VST1d64Q_UPD:
2367 case ARM::VST2q8:
2368 case ARM::VST2q16:
2369 case ARM::VST2q32:
2370 case ARM::VST2q8_UPD:
2371 case ARM::VST2q16_UPD:
2372 case ARM::VST2q32_UPD:
2373 case ARM::VST3d8:
2374 case ARM::VST3d16:
2375 case ARM::VST3d32:
2376 case ARM::VST3d8_UPD:
2377 case ARM::VST3d16_UPD:
2378 case ARM::VST3d32_UPD:
2379 case ARM::VST4d8:
2380 case ARM::VST4d16:
2381 case ARM::VST4d32:
2382 case ARM::VST4d8_UPD:
2383 case ARM::VST4d16_UPD:
2384 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2385 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2386 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2387 break;
2388 case ARM::VST3q8:
2389 case ARM::VST3q16:
2390 case ARM::VST3q32:
2391 case ARM::VST3q8_UPD:
2392 case ARM::VST3q16_UPD:
2393 case ARM::VST3q32_UPD:
2394 case ARM::VST4q8:
2395 case ARM::VST4q16:
2396 case ARM::VST4q32:
2397 case ARM::VST4q8_UPD:
2398 case ARM::VST4q16_UPD:
2399 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2400 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2401 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2402 break;
2403 default:
2404 break;
2405 }
2406
2407 // Fourth input register
2408 switch (Inst.getOpcode()) {
2409 case ARM::VST1d8Q:
2410 case ARM::VST1d16Q:
2411 case ARM::VST1d32Q:
2412 case ARM::VST1d64Q:
2413 case ARM::VST1d8Q_UPD:
2414 case ARM::VST1d16Q_UPD:
2415 case ARM::VST1d32Q_UPD:
2416 case ARM::VST1d64Q_UPD:
2417 case ARM::VST2q8:
2418 case ARM::VST2q16:
2419 case ARM::VST2q32:
2420 case ARM::VST2q8_UPD:
2421 case ARM::VST2q16_UPD:
2422 case ARM::VST2q32_UPD:
2423 case ARM::VST4d8:
2424 case ARM::VST4d16:
2425 case ARM::VST4d32:
2426 case ARM::VST4d8_UPD:
2427 case ARM::VST4d16_UPD:
2428 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2429 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2430 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2431 break;
2432 case ARM::VST4q8:
2433 case ARM::VST4q16:
2434 case ARM::VST4q32:
2435 case ARM::VST4q8_UPD:
2436 case ARM::VST4q16_UPD:
2437 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2438 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2439 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2440 break;
2441 default:
2442 break;
2443 }
2444
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2445 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2446}
2447
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2448static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2449 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2450 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2451
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2452 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2453 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2454 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2455 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2456 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2457 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2458 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2459
2460 align *= (1 << size);
2461
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2462 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2463 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2464 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2465 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2466 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2467 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2468 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2470 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2471 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2472
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2474 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2475 Inst.addOperand(MCOperand::CreateImm(align));
2476
2477 if (Rm == 0xD)
2478 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2479 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2481 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2482 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2483
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2484 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2485}
2486
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2487static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2488 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2489 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2490
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2491 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2492 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2493 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2494 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2495 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2496 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2497 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2498 align *= 2*size;
2499
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2500 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2501 return MCDisassembler::Fail;
2502 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2503 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2504 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2506 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2507 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2508
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2510 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2511 Inst.addOperand(MCOperand::CreateImm(align));
2512
2513 if (Rm == 0xD)
2514 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2515 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2517 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2518 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2519
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2520 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521}
2522
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2523static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2525 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2526
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2527 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2528 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2529 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2530 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2531 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2532
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2533 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2534 return MCDisassembler::Fail;
2535 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2536 return MCDisassembler::Fail;
2537 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2538 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2539 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2541 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2542 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2543
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2545 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2546 Inst.addOperand(MCOperand::CreateImm(0));
2547
2548 if (Rm == 0xD)
2549 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2550 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2552 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2553 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2554
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2555 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2556}
2557
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2558static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2559 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2560 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2561
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2562 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2563 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2564 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2565 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2566 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2567 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2568 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2569
2570 if (size == 0x3) {
2571 size = 4;
2572 align = 16;
2573 } else {
2574 if (size == 2) {
2575 size = 1 << size;
2576 align *= 8;
2577 } else {
2578 size = 1 << size;
2579 align *= 4*size;
2580 }
2581 }
2582
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2583 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2584 return MCDisassembler::Fail;
2585 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2586 return MCDisassembler::Fail;
2587 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2588 return MCDisassembler::Fail;
2589 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2590 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2591 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2593 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2594 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2595
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2597 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2598 Inst.addOperand(MCOperand::CreateImm(align));
2599
2600 if (Rm == 0xD)
2601 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2602 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2604 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2605 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2607 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2608}
2609
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2610static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2611DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2612 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2613 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2614
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2615 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2616 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2617 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2618 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2619 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2620 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2621 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2622 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2623
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2624 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2625 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2626 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2627 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2628 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2629 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2630 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2631
2632 Inst.addOperand(MCOperand::CreateImm(imm));
2633
2634 switch (Inst.getOpcode()) {
2635 case ARM::VORRiv4i16:
2636 case ARM::VORRiv2i32:
2637 case ARM::VBICiv4i16:
2638 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2640 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2641 break;
2642 case ARM::VORRiv8i16:
2643 case ARM::VORRiv4i32:
2644 case ARM::VBICiv8i16:
2645 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2646 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2647 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2648 break;
2649 default:
2650 break;
2651 }
2652
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2653 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2654}
2655
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2656static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2657 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2658 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2659
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2660 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2661 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2662 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2663 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2664 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2665
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2666 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2667 return MCDisassembler::Fail;
2668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2669 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670 Inst.addOperand(MCOperand::CreateImm(8 << size));
2671
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2672 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2673}
2674
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2675static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2676 uint64_t Address, const void *Decoder) {
2677 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2678 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2679}
2680
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2681static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682 uint64_t Address, const void *Decoder) {
2683 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2684 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2685}
2686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2687static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2688 uint64_t Address, const void *Decoder) {
2689 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2690 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2691}
2692
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2693static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694 uint64_t Address, const void *Decoder) {
2695 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2696 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2697}
2698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2699static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2700 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2701 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2702
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2703 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2704 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2705 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2706 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2707 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2708 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2709 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2710 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2711
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2713 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2714 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2715 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2716 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2717 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2718
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2719 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2720 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2721 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2722 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2723
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2725 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2726
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2727 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2728}
2729
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2730static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2731 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2732 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2733
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2734 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2735 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2736
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2737 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2738 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2739
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2740 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2741 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2742 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2743 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2744 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2745 case ARM::tADDrSPi:
2746 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2747 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2748 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2749
2750 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2751 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2752}
2753
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2754static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2755 uint64_t Address, const void *Decoder) {
2756 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2757 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2758}
2759
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2760static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2761 uint64_t Address, const void *Decoder) {
2762 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2763 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2764}
2765
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2766static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2767 uint64_t Address, const void *Decoder) {
2768 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2769 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2770}
2771
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2772static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2773 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2774 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2775
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2776 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2777 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2778
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2779 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2780 return MCDisassembler::Fail;
2781 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2782 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2783
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2784 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2785}
2786
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2787static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2788 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2789 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2790
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2791 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2792 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2793
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2794 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2795 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2796 Inst.addOperand(MCOperand::CreateImm(imm));
2797
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2798 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2799}
2800
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2801static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2802 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2803 unsigned imm = Val << 2;
2804
2805 Inst.addOperand(MCOperand::CreateImm(imm));
2806 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2807
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2808 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2809}
2810
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2811static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812 uint64_t Address, const void *Decoder) {
2813 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2814 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2815
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2816 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817}
2818
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2819static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2820 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2821 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2822
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2823 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2824 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2825 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2826
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2828 return MCDisassembler::Fail;
2829 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2830 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2831 Inst.addOperand(MCOperand::CreateImm(imm));
2832
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2833 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2834}
2835
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2836static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2837 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2838 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2839
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2840 switch (Inst.getOpcode()) {
2841 case ARM::t2PLDs:
2842 case ARM::t2PLDWs:
2843 case ARM::t2PLIs:
2844 break;
2845 default: {
2846 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2847 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2848 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2849 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2850 }
2851
2852 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2853 if (Rn == 0xF) {
2854 switch (Inst.getOpcode()) {
2855 case ARM::t2LDRBs:
2856 Inst.setOpcode(ARM::t2LDRBpci);
2857 break;
2858 case ARM::t2LDRHs:
2859 Inst.setOpcode(ARM::t2LDRHpci);
2860 break;
2861 case ARM::t2LDRSHs:
2862 Inst.setOpcode(ARM::t2LDRSHpci);
2863 break;
2864 case ARM::t2LDRSBs:
2865 Inst.setOpcode(ARM::t2LDRSBpci);
2866 break;
2867 case ARM::t2PLDs:
2868 Inst.setOpcode(ARM::t2PLDi12);
2869 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2870 break;
2871 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2872 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2873 }
2874
2875 int imm = fieldFromInstruction32(Insn, 0, 12);
2876 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2877 Inst.addOperand(MCOperand::CreateImm(imm));
2878
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2879 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2880 }
2881
2882 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2883 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2884 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2885 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2886 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2887
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2888 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2889}
2890
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2891static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2892 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893 int imm = Val & 0xFF;
2894 if (!(Val & 0x100)) imm *= -1;
2895 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2896
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2897 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2898}
2899
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2900static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2901 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2902 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2903
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2904 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2905 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2906
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2908 return MCDisassembler::Fail;
2909 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2910 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2911
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2912 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2913}
2914
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2915static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2916 uint64_t Address, const void *Decoder) {
2917 DecodeStatus S = MCDisassembler::Success;
2918
2919 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2920 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2921
2922 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2923 return MCDisassembler::Fail;
2924
2925 Inst.addOperand(MCOperand::CreateImm(imm));
2926
2927 return S;
2928}
2929
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2930static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2931 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2932 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2933 if (Val == 0)
2934 imm = INT32_MIN;
2935 else if (!(Val & 0x100))
2936 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2937 Inst.addOperand(MCOperand::CreateImm(imm));
2938
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2939 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2940}
2941
2942
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2943static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2944 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2945 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2946
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2947 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2948 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2949
2950 // Some instructions always use an additive offset.
2951 switch (Inst.getOpcode()) {
2952 case ARM::t2LDRT:
2953 case ARM::t2LDRBT:
2954 case ARM::t2LDRHT:
2955 case ARM::t2LDRSBT:
2956 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2957 case ARM::t2STRT:
2958 case ARM::t2STRBT:
2959 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2960 imm |= 0x100;
2961 break;
2962 default:
2963 break;
2964 }
2965
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2967 return MCDisassembler::Fail;
2968 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2969 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2970
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2971 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2972}
2973
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2974static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2975 uint64_t Address, const void *Decoder) {
2976 DecodeStatus S = MCDisassembler::Success;
2977
2978 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2979 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2980 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2981 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2982 addr |= Rn << 9;
2983 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2984
2985 if (!load) {
2986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2987 return MCDisassembler::Fail;
2988 }
2989
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2991 return MCDisassembler::Fail;
2992
2993 if (load) {
2994 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996 }
2997
2998 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2999 return MCDisassembler::Fail;
3000
3001 return S;
3002}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3003
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3004static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3005 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3006 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3007
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3008 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3009 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3010
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3012 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3013 Inst.addOperand(MCOperand::CreateImm(imm));
3014
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3015 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3016}
3017
3018
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3019static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3020 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3021 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3022
3023 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3024 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3025 Inst.addOperand(MCOperand::CreateImm(imm));
3026
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3027 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3028}
3029
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3030static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3031 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3032 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3033
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3034 if (Inst.getOpcode() == ARM::tADDrSP) {
3035 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3036 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3037
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3039 return MCDisassembler::Fail;
3040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3041 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3042 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3043 } else if (Inst.getOpcode() == ARM::tADDspr) {
3044 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3045
3046 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3047 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3049 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3050 }
3051
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3052 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3053}
3054
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3055static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3056 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3057 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3058 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3059
3060 Inst.addOperand(MCOperand::CreateImm(imod));
3061 Inst.addOperand(MCOperand::CreateImm(flags));
3062
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3063 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3064}
3065
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3066static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3067 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3068 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3069 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3070 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3071
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3073 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3074 Inst.addOperand(MCOperand::CreateImm(add));
3075
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3076 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3077}
3078
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3079static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3080 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3081 if (!tryAddingSymbolicOperand(Address,
3082 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3083 true, 4, Inst, Decoder))
3084 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3085 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3086}
3087
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3088static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3089 uint64_t Address, const void *Decoder) {
3090 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3091 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3092
3093 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3094 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3095}
3096
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3097static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3098DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3099 uint64_t Address, const void *Decoder) {
3100 DecodeStatus S = MCDisassembler::Success;
3101
3102 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3103 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3104
3105 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3107 return MCDisassembler::Fail;
3108 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3109 return MCDisassembler::Fail;
3110 return S;
3111}
3112
3113static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3114DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3115 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3116 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3117
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3118 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3119 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3120 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3121 switch (opc) {
3122 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3123 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3124 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3125 Inst.setOpcode(ARM::t2DSB);
3126 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3127 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3128 Inst.setOpcode(ARM::t2DMB);
3129 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3130 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3131 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3132 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3133 }
3134
3135 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3136 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3137 }
3138
3139 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3140 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3141 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3142 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3143 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3144
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3145 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3146 return MCDisassembler::Fail;
3147 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3148 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3149
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3150 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3151}
3152
3153// Decode a shifted immediate operand. These basically consist
3154// of an 8-bit value, and a 4-bit directive that specifies either
3155// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3156static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3157 uint64_t Address, const void *Decoder) {
3158 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3159 if (ctrl == 0) {
3160 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3161 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3162 switch (byte) {
3163 case 0:
3164 Inst.addOperand(MCOperand::CreateImm(imm));
3165 break;
3166 case 1:
3167 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3168 break;
3169 case 2:
3170 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3171 break;
3172 case 3:
3173 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3174 (imm << 8) | imm));
3175 break;
3176 }
3177 } else {
3178 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3179 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3180 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3181 Inst.addOperand(MCOperand::CreateImm(imm));
3182 }
3183
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3184 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3185}
3186
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3187static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3188DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3189 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3190 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3191 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3192}
3193
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3194static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3195 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3196 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3197 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3198}
3199
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3200static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3201 uint64_t Address, const void *Decoder) {
3202 switch (Val) {
3203 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3204 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3205 case 0xF: // SY
3206 case 0xE: // ST
3207 case 0xB: // ISH
3208 case 0xA: // ISHST
3209 case 0x7: // NSH
3210 case 0x6: // NSHST
3211 case 0x3: // OSH
3212 case 0x2: // OSHST
3213 break;
3214 }
3215
3216 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3217 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3218}
3219
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3220static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3221 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3222 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3223 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3224 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3225}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3226
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3227static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3228 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3229 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3230
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3231 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3232 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3233 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3234
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3235 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3236
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3238 return MCDisassembler::Fail;
3239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3240 return MCDisassembler::Fail;
3241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3242 return MCDisassembler::Fail;
3243 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3244 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3245
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3246 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3247}
3248
3249
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3250static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3251 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3252 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3253
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3254 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3255 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3256 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3257 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3258
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3259 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3260 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3261
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3262 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3263 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3264
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3266 return MCDisassembler::Fail;
3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3268 return MCDisassembler::Fail;
3269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3270 return MCDisassembler::Fail;
3271 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3272 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3273
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3274 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3275}
3276
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3277static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3278 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3279 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3280
3281 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3282 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3283 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3284 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3285 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3286 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3287
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3288 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3289
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3291 return MCDisassembler::Fail;
3292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3293 return MCDisassembler::Fail;
3294 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3295 return MCDisassembler::Fail;
3296 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3297 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3298
3299 return S;
3300}
3301
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3302static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3303 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3304 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3305
3306 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3307 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3308 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3309 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3310 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3311 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3312 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3313
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3314 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3315 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3316
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3318 return MCDisassembler::Fail;
3319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3320 return MCDisassembler::Fail;
3321 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3322 return MCDisassembler::Fail;
3323 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3324 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3325
3326 return S;
3327}
3328
3329
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3330static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3331 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3332 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3333
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3334 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3335 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3336 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3337 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3338 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3339 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3340
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3341 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3342
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3343 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3344 return MCDisassembler::Fail;
3345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3346 return MCDisassembler::Fail;
3347 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3348 return MCDisassembler::Fail;
3349 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3350 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3351
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3352 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3353}
3354
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3355static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3356 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3357 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3358
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3359 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3360 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3361 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3362 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3363 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3364 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3365
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3366 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3367
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3369 return MCDisassembler::Fail;
3370 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3371 return MCDisassembler::Fail;
3372 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3373 return MCDisassembler::Fail;
3374 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3375 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3376
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3377 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3378}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3379
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3380static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3381 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3382 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3383
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3384 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3385 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3386 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3387 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3388 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3389
3390 unsigned align = 0;
3391 unsigned index = 0;
3392 switch (size) {
3393 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3394 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3395 case 0:
3396 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3397 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3398 index = fieldFromInstruction32(Insn, 5, 3);
3399 break;
3400 case 1:
3401 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3402 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3403 index = fieldFromInstruction32(Insn, 6, 2);
3404 if (fieldFromInstruction32(Insn, 4, 1))
3405 align = 2;
3406 break;
3407 case 2:
3408 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3409 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3410 index = fieldFromInstruction32(Insn, 7, 1);
3411 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3412 align = 4;
3413 }
3414
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3416 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3417 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3419 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3420 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3422 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3423 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3424 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3425 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3427 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3428 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3429 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3430 }
3431
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3432 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3433 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3434 Inst.addOperand(MCOperand::CreateImm(index));
3435
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3436 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3437}
3438
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3439static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3440 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3441 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3442
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3443 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3444 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3445 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3446 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3447 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3448
3449 unsigned align = 0;
3450 unsigned index = 0;
3451 switch (size) {
3452 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3453 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3454 case 0:
3455 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3456 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3457 index = fieldFromInstruction32(Insn, 5, 3);
3458 break;
3459 case 1:
3460 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3461 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3462 index = fieldFromInstruction32(Insn, 6, 2);
3463 if (fieldFromInstruction32(Insn, 4, 1))
3464 align = 2;
3465 break;
3466 case 2:
3467 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3468 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3469 index = fieldFromInstruction32(Insn, 7, 1);
3470 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3471 align = 4;
3472 }
3473
3474 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3476 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3477 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3479 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3480 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3481 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3482 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3484 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3485 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3486 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3487 }
3488
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3489 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3490 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3491 Inst.addOperand(MCOperand::CreateImm(index));
3492
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3493 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3494}
3495
3496
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3497static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3498 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3499 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3500
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3501 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3502 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3503 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3504 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3505 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3506
3507 unsigned align = 0;
3508 unsigned index = 0;
3509 unsigned inc = 1;
3510 switch (size) {
3511 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3512 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3513 case 0:
3514 index = fieldFromInstruction32(Insn, 5, 3);
3515 if (fieldFromInstruction32(Insn, 4, 1))
3516 align = 2;
3517 break;
3518 case 1:
3519 index = fieldFromInstruction32(Insn, 6, 2);
3520 if (fieldFromInstruction32(Insn, 4, 1))
3521 align = 4;
3522 if (fieldFromInstruction32(Insn, 5, 1))
3523 inc = 2;
3524 break;
3525 case 2:
3526 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3527 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3528 index = fieldFromInstruction32(Insn, 7, 1);
3529 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3530 align = 8;
3531 if (fieldFromInstruction32(Insn, 6, 1))
3532 inc = 2;
3533 break;
3534 }
3535
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3536 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3537 return MCDisassembler::Fail;
3538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3539 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3540 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3541 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3542 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3543 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3545 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3546 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3547 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3548 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3550 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3551 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3552 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3553 }
3554
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3555 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3556 return MCDisassembler::Fail;
3557 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3558 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3559 Inst.addOperand(MCOperand::CreateImm(index));
3560
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3561 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3562}
3563
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3564static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3565 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3566 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3567
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3568 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3569 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3570 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3571 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3572 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3573
3574 unsigned align = 0;
3575 unsigned index = 0;
3576 unsigned inc = 1;
3577 switch (size) {
3578 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3579 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3580 case 0:
3581 index = fieldFromInstruction32(Insn, 5, 3);
3582 if (fieldFromInstruction32(Insn, 4, 1))
3583 align = 2;
3584 break;
3585 case 1:
3586 index = fieldFromInstruction32(Insn, 6, 2);
3587 if (fieldFromInstruction32(Insn, 4, 1))
3588 align = 4;
3589 if (fieldFromInstruction32(Insn, 5, 1))
3590 inc = 2;
3591 break;
3592 case 2:
3593 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3594 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3595 index = fieldFromInstruction32(Insn, 7, 1);
3596 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3597 align = 8;
3598 if (fieldFromInstruction32(Insn, 6, 1))
3599 inc = 2;
3600 break;
3601 }
3602
3603 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3605 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3606 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3608 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3609 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3610 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3611 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3613 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3614 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3615 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3616 }
3617
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3618 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3619 return MCDisassembler::Fail;
3620 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3621 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3622 Inst.addOperand(MCOperand::CreateImm(index));
3623
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3624 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3625}
3626
3627
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3628static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3629 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3630 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3631
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3632 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3633 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3634 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3635 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3636 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3637
3638 unsigned align = 0;
3639 unsigned index = 0;
3640 unsigned inc = 1;
3641 switch (size) {
3642 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3643 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3644 case 0:
3645 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3646 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3647 index = fieldFromInstruction32(Insn, 5, 3);
3648 break;
3649 case 1:
3650 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3651 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3652 index = fieldFromInstruction32(Insn, 6, 2);
3653 if (fieldFromInstruction32(Insn, 5, 1))
3654 inc = 2;
3655 break;
3656 case 2:
3657 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3658 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3659 index = fieldFromInstruction32(Insn, 7, 1);
3660 if (fieldFromInstruction32(Insn, 6, 1))
3661 inc = 2;
3662 break;
3663 }
3664
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3666 return MCDisassembler::Fail;
3667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3668 return MCDisassembler::Fail;
3669 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3670 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3671
3672 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3674 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3675 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3677 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3678 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3679 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3680 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3682 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3683 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3684 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3685 }
3686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3688 return MCDisassembler::Fail;
3689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3690 return MCDisassembler::Fail;
3691 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3692 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3693 Inst.addOperand(MCOperand::CreateImm(index));
3694
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3695 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3696}
3697
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3698static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3699 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3700 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3701
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3702 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3703 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3704 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3705 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3706 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3707
3708 unsigned align = 0;
3709 unsigned index = 0;
3710 unsigned inc = 1;
3711 switch (size) {
3712 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3713 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3714 case 0:
3715 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3716 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3717 index = fieldFromInstruction32(Insn, 5, 3);
3718 break;
3719 case 1:
3720 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3721 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3722 index = fieldFromInstruction32(Insn, 6, 2);
3723 if (fieldFromInstruction32(Insn, 5, 1))
3724 inc = 2;
3725 break;
3726 case 2:
3727 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3728 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3729 index = fieldFromInstruction32(Insn, 7, 1);
3730 if (fieldFromInstruction32(Insn, 6, 1))
3731 inc = 2;
3732 break;
3733 }
3734
3735 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3737 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3738 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3740 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3741 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3742 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3743 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3745 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3746 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3747 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3748 }
3749
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3750 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3751 return MCDisassembler::Fail;
3752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3753 return MCDisassembler::Fail;
3754 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3755 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3756 Inst.addOperand(MCOperand::CreateImm(index));
3757
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3758 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3759}
3760
3761
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3762static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3763 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3764 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3765
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3766 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3767 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3768 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3769 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3770 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3771
3772 unsigned align = 0;
3773 unsigned index = 0;
3774 unsigned inc = 1;
3775 switch (size) {
3776 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3777 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3778 case 0:
3779 if (fieldFromInstruction32(Insn, 4, 1))
3780 align = 4;
3781 index = fieldFromInstruction32(Insn, 5, 3);
3782 break;
3783 case 1:
3784 if (fieldFromInstruction32(Insn, 4, 1))
3785 align = 8;
3786 index = fieldFromInstruction32(Insn, 6, 2);
3787 if (fieldFromInstruction32(Insn, 5, 1))
3788 inc = 2;
3789 break;
3790 case 2:
3791 if (fieldFromInstruction32(Insn, 4, 2))
3792 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3793 index = fieldFromInstruction32(Insn, 7, 1);
3794 if (fieldFromInstruction32(Insn, 6, 1))
3795 inc = 2;
3796 break;
3797 }
3798
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3800 return MCDisassembler::Fail;
3801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3802 return MCDisassembler::Fail;
3803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3804 return MCDisassembler::Fail;
3805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3806 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3807
3808 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3810 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3811 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3813 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3814 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3815 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3816 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3818 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3819 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3820 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3821 }
3822
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3824 return MCDisassembler::Fail;
3825 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3826 return MCDisassembler::Fail;
3827 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3828 return MCDisassembler::Fail;
3829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3830 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3831 Inst.addOperand(MCOperand::CreateImm(index));
3832
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3833 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3834}
3835
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3836static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3837 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3838 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3839
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3840 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3841 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3842 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3843 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3844 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3845
3846 unsigned align = 0;
3847 unsigned index = 0;
3848 unsigned inc = 1;
3849 switch (size) {
3850 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3851 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3852 case 0:
3853 if (fieldFromInstruction32(Insn, 4, 1))
3854 align = 4;
3855 index = fieldFromInstruction32(Insn, 5, 3);
3856 break;
3857 case 1:
3858 if (fieldFromInstruction32(Insn, 4, 1))
3859 align = 8;
3860 index = fieldFromInstruction32(Insn, 6, 2);
3861 if (fieldFromInstruction32(Insn, 5, 1))
3862 inc = 2;
3863 break;
3864 case 2:
3865 if (fieldFromInstruction32(Insn, 4, 2))
3866 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3867 index = fieldFromInstruction32(Insn, 7, 1);
3868 if (fieldFromInstruction32(Insn, 6, 1))
3869 inc = 2;
3870 break;
3871 }
3872
3873 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3875 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3876 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3878 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3879 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3880 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3881 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3883 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3884 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3885 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3886 }
3887
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3888 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3889 return MCDisassembler::Fail;
3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3893 return MCDisassembler::Fail;
3894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3895 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3896 Inst.addOperand(MCOperand::CreateImm(index));
3897
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3898 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3899}
3900
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3901static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3902 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3903 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3904 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3905 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3906 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3907 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3908 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3909
3910 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3911 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3912
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3913 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3914 return MCDisassembler::Fail;
3915 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3916 return MCDisassembler::Fail;
3917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3918 return MCDisassembler::Fail;
3919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3920 return MCDisassembler::Fail;
3921 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3922 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3923
3924 return S;
3925}
3926
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3927static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3928 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3929 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3930 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3931 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3932 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3933 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3934 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3935
3936 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3937 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3938
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3940 return MCDisassembler::Fail;
3941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3942 return MCDisassembler::Fail;
3943 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3944 return MCDisassembler::Fail;
3945 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3946 return MCDisassembler::Fail;
3947 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3948 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3949
3950 return S;
3951}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3952
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3953static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3954 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3955 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3956 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3957 // The InstPrinter needs to have the low bit of the predicate in
3958 // the mask operand to be able to print it properly.
3959 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3960
3961 if (pred == 0xF) {
3962 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3963 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3964 }
3965
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3966 if ((mask & 0xF) == 0) {
3967 // Preserve the high bit of the mask, which is the low bit of
3968 // the predicate.
3969 mask &= 0x10;
3970 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3971 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3972 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3973
3974 Inst.addOperand(MCOperand::CreateImm(pred));
3975 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3976 return S;
3977}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3978
3979static DecodeStatus
3980DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3981 uint64_t Address, const void *Decoder) {
3982 DecodeStatus S = MCDisassembler::Success;
3983
3984 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3985 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3986 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3987 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3988 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3989 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3990 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3991 bool writeback = (W == 1) | (P == 0);
3992
3993 addr |= (U << 8) | (Rn << 9);
3994
3995 if (writeback && (Rn == Rt || Rn == Rt2))
3996 Check(S, MCDisassembler::SoftFail);
3997 if (Rt == Rt2)
3998 Check(S, MCDisassembler::SoftFail);
3999
4000 // Rt
4001 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4002 return MCDisassembler::Fail;
4003 // Rt2
4004 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4005 return MCDisassembler::Fail;
4006 // Writeback operand
4007 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4008 return MCDisassembler::Fail;
4009 // addr
4010 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4011 return MCDisassembler::Fail;
4012
4013 return S;
4014}
4015
4016static DecodeStatus
4017DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4018 uint64_t Address, const void *Decoder) {
4019 DecodeStatus S = MCDisassembler::Success;
4020
4021 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4022 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4023 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4024 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4025 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4026 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4027 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4028 bool writeback = (W == 1) | (P == 0);
4029
4030 addr |= (U << 8) | (Rn << 9);
4031
4032 if (writeback && (Rn == Rt || Rn == Rt2))
4033 Check(S, MCDisassembler::SoftFail);
4034
4035 // Writeback operand
4036 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4037 return MCDisassembler::Fail;
4038 // Rt
4039 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4040 return MCDisassembler::Fail;
4041 // Rt2
4042 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4043 return MCDisassembler::Fail;
4044 // addr
4045 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4046 return MCDisassembler::Fail;
4047
4048 return S;
4049}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4050
4051static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4052 uint64_t Address, const void *Decoder) {
4053 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4054 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4055 if (sign1 != sign2) return MCDisassembler::Fail;
4056
4057 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4058 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4059 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4060 Val |= sign1 << 12;
4061 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4062
4063 return MCDisassembler::Success;
4064}
4065
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4066static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4067 uint64_t Address,
4068 const void *Decoder) {
4069 DecodeStatus S = MCDisassembler::Success;
4070
4071 // Shift of "asr #32" is not allowed in Thumb2 mode.
4072 if (Val == 0x20) S = MCDisassembler::SoftFail;
4073 Inst.addOperand(MCOperand::CreateImm(Val));
4074 return S;
4075}
4076