Blame - lib/Target/ARM/Disassembler/ARMDisassembler.cpp - platform/external/llvm

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Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	1	//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ------ C++ --===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	12	#include "ARM.h"
				13	#include "ARMRegisterInfo.h"
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	14	#include "ARMSubtarget.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	15	#include "MCTargetDesc/ARMAddressingModes.h"
				16	#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	17	#include "llvm/MC/EDInstInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	18	#include "llvm/MC/MCInst.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	19	#include "llvm/MC/MCExpr.h"
				20	#include "llvm/MC/MCContext.h"
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	21	#include "llvm/MC/MCDisassembler.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/Debug.h"
				23	#include "llvm/Support/MemoryObject.h"
				24	#include "llvm/Support/ErrorHandling.h"
Evan Cheng	3e74d6f	2011-08-24 18:08:43 +0000	[diff] [blame]	25	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	26	#include "llvm/Support/raw_ostream.h"
				27
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	28	using namespace llvm;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	29
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	30	typedef MCDisassembler::DecodeStatus DecodeStatus;
				31
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	32	namespace {
				33	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				34	class ARMDisassembler : public MCDisassembler {
				35	public:
				36	/// Constructor - Initializes the disassembler.
				37	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	38	ARMDisassembler(const MCSubtargetInfo &STI) :
				39	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	40	}
				41
				42	~ARMDisassembler() {
				43	}
				44
				45	/// getInstruction - See MCDisassembler.
				46	DecodeStatus getInstruction(MCInst &instr,
				47	uint64_t &size,
				48	const MemoryObject &region,
				49	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	50	raw_ostream &vStream,
				51	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	52
				53	/// getEDInfo - See MCDisassembler.
				54	EDInstInfo *getEDInfo() const;
				55	private:
				56	};
				57
				58	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				59	class ThumbDisassembler : public MCDisassembler {
				60	public:
				61	/// Constructor - Initializes the disassembler.
				62	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	63	ThumbDisassembler(const MCSubtargetInfo &STI) :
				64	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	65	}
				66
				67	~ThumbDisassembler() {
				68	}
				69
				70	/// getInstruction - See MCDisassembler.
				71	DecodeStatus getInstruction(MCInst &instr,
				72	uint64_t &size,
				73	const MemoryObject &region,
				74	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	75	raw_ostream &vStream,
				76	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	77
				78	/// getEDInfo - See MCDisassembler.
				79	EDInstInfo *getEDInfo() const;
				80	private:
				81	mutable std::vector<unsigned> ITBlock;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	82	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	83	void UpdateThumbVFPPredicate(MCInst&) const;
				84	};
				85	}
				86
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	87	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	88	switch (In) {
				89	case MCDisassembler::Success:
				90	// Out stays the same.
				91	return true;
				92	case MCDisassembler::SoftFail:
				93	Out = In;
				94	return true;
				95	case MCDisassembler::Fail:
				96	Out = In;
				97	return false;
				98	}
				99	return false;
				100	}
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	101
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	102
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	103	// Forward declare these because the autogenerated code will reference them.
				104	// Definitions are further down.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	105	static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	106	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	107	static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	108	unsigned RegNo, uint64_t Address,
				109	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	110	static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	111	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	112	static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	113	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	114	static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	115	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	116	static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	117	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	118	static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	119	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	120	static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	121	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	122	static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	123	unsigned RegNo,
				124	uint64_t Address,
				125	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	126	static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	127	uint64_t Address, const void *Decoder);
Johnny Chen	270159f	2010-08-12 01:40:54 +0000	[diff] [blame]	128
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	129	static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	130	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	131	static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	132	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	133	static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	134	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	135	static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	136	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	137	static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	138	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	139	static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	140	uint64_t Address, const void *Decoder);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	141
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	142	static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	143	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	144	static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	145	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	146	static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	147	unsigned Insn,
				148	uint64_t Address,
				149	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	150	static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	151	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	152	static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	153	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	154	static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	155	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	156	static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	157	uint64_t Address, const void *Decoder);
				158
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	159	static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	160	unsigned Insn,
				161	uint64_t Adddress,
				162	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	163	static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	164	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	165	static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	166	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	167	static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	168	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	169	static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	170	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	171	static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	172	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	173	static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	174	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	175	static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	176	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	177	static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	178	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	179	static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	180	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	181	static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	182	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	183	static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	184	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	185	static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	186	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	187	static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	188	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	189	static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	190	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	191	static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	192	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	193	static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	194	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	195	static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	196	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	197	static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	198	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	199	static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	200	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	201	static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	202	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	203	static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	205	static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	206	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	207	static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	209	static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	211	static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	213	static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	215	static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	217	static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	218	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	219	static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	220	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	221	static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	222	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	223	static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	224	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	225	static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	226	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	227	static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	228	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	229	static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	230	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	231	static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	232	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	233	static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	234	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	235	static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	236	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	237	static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	238	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	239	static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	240	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	241	static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	242	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	243	static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	244	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	245	static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	246	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	247	static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	248	uint64_t Address, const void *Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	249
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	250	static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	251	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	252	static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	254	static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	256	static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	258	static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	260	static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	262	static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	264	static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	266	static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	268	static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	270	static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	272	static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	274	static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
				275	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	276	static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	278	static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	280	static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	282	static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	284	static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	285	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	286	static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	288	static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	290	static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	292	static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	294	static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	296	static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	298	static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	300	static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
				301	uint64_t Address, const void *Decoder);
				302	static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
				303	uint64_t Address, const void *Decoder);
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	304	static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
				305	uint64_t Address, const void *Decoder);
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	306	static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
				307	uint64_t Address, const void *Decoder);
				308
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	309
				310	#include "ARMGenDisassemblerTables.inc"
				311	#include "ARMGenInstrInfo.inc"
Oscar Fuentes	38e1390	2010-09-28 11:48:19 +0000	[diff] [blame]	312	#include "ARMGenEDInfo.inc"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	313
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	314	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				315	return new ARMDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	316	}
				317
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	318	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				319	return new ThumbDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	320	}
				321
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	322	EDInstInfo *ARMDisassembler::getEDInfo() const {
				323	return instInfoARM;
				324	}
				325
				326	EDInstInfo *ThumbDisassembler::getEDInfo() const {
				327	return instInfoARM;
				328	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	329
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	330	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	331	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	332	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	333	raw_ostream &os,
				334	raw_ostream &cs) const {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint8_t bytes[4];
				336
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	337	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				338	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				339
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	340	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	341	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				342	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	343	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	344	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	345
				346	// Encoded as a small-endian 32-bit word in the stream.
				347	uint32_t insn = (bytes[3] << 24) \|
				348	(bytes[2] << 16) \|
				349	(bytes[1] << 8) \|
				350	(bytes[0] << 0);
				351
				352	// Calling the auto-generated decoder function.
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	353	DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	354	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	355	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	356	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	357	}
				358
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	359	// VFP and NEON instructions, similarly, are shared between ARM
				360	// and Thumb modes.
				361	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	362	result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	363	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	364	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	365	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	366	}
				367
				368	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	369	result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	370	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	371	Size = 4;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	372	// Add a fake predicate operand, because we share these instruction
				373	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	374	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				375	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	376	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	377	}
				378
				379	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	380	result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	381	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	382	Size = 4;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	383	// Add a fake predicate operand, because we share these instruction
				384	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	385	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				386	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	387	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	388	}
				389
				390	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	391	result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	392	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	393	Size = 4;
				394	// Add a fake predicate operand, because we share these instruction
				395	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	396	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				397	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	398	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	399	}
				400
				401	MI.clear();
				402
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	403	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	404	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	405	}
				406
				407	namespace llvm {
				408	extern MCInstrDesc ARMInsts[];
				409	}
				410
				411	// Thumb1 instructions don't have explicit S bits. Rather, they
				412	// implicitly set CPSR. Since it's not represented in the encoding, the
				413	// auto-generated decoder won't inject the CPSR operand. We need to fix
				414	// that as a post-pass.
				415	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				416	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	417	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	418	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	419	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				420	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	421	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	422	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	423	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				424	return;
				425	}
				426	}
				427
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	428	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	429	}
				430
				431	// Most Thumb instructions don't have explicit predicates in the
				432	// encoding, but rather get their predicates from IT context. We need
				433	// to fix up the predicate operands using this context information as a
				434	// post-pass.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	435	MCDisassembler::DecodeStatus
				436	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	437	MCDisassembler::DecodeStatus S = Success;
				438
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	439	// A few instructions actually have predicates encoded in them. Don't
				440	// try to overwrite it if we're seeing one of those.
				441	switch (MI.getOpcode()) {
				442	case ARM::tBcc:
				443	case ARM::t2Bcc:
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	444	case ARM::tCBZ:
				445	case ARM::tCBNZ:
Owen Anderson	441462f	2011-09-08 22:48:37 +0000	[diff] [blame]	446	// Some instructions (mostly conditional branches) are not
				447	// allowed in IT blocks.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	448	if (!ITBlock.empty())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	449	S = SoftFail;
				450	else
				451	return Success;
				452	break;
				453	case ARM::tB:
				454	case ARM::t2B:
				455	// Some instructions (mostly unconditional branches) can
				456	// only appears at the end of, or outside of, an IT.
				457	if (ITBlock.size() > 1)
				458	S = SoftFail;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	459	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	460	default:
				461	break;
				462	}
				463
				464	// If we're in an IT block, base the predicate on that. Otherwise,
				465	// assume a predicate of AL.
				466	unsigned CC;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	467	if (!ITBlock.empty()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	468	CC = ITBlock.back();
Owen Anderson	9bd655d	2011-08-26 06:19:51 +0000	[diff] [blame]	469	if (CC == 0xF)
				470	CC = ARMCC::AL;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	471	ITBlock.pop_back();
				472	} else
				473	CC = ARMCC::AL;
				474
				475	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	476	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	477	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	478	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				479	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	480	if (OpInfo[i].isPredicate()) {
				481	I = MI.insert(I, MCOperand::CreateImm(CC));
				482	++I;
				483	if (CC == ARMCC::AL)
				484	MI.insert(I, MCOperand::CreateReg(0));
				485	else
				486	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	487	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	488	}
				489	}
				490
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	491	I = MI.insert(I, MCOperand::CreateImm(CC));
				492	++I;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	493	if (CC == ARMCC::AL)
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	494	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	495	else
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	496	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	497
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	498	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	499	}
				500
				501	// Thumb VFP instructions are a special case. Because we share their
				502	// encodings between ARM and Thumb modes, and they are predicable in ARM
				503	// mode, the auto-generated decoder will give them an (incorrect)
				504	// predicate operand. We need to rewrite these operands based on the IT
				505	// context as a post-pass.
				506	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				507	unsigned CC;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	508	if (!ITBlock.empty()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	509	CC = ITBlock.back();
				510	ITBlock.pop_back();
				511	} else
				512	CC = ARMCC::AL;
				513
				514	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				515	MCInst::iterator I = MI.begin();
Owen Anderson	12a1e3b	2011-08-24 21:35:46 +0000	[diff] [blame]	516	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				517	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	518	if (OpInfo[i].isPredicate() ) {
				519	I->setImm(CC);
				520	++I;
				521	if (CC == ARMCC::AL)
				522	I->setReg(0);
				523	else
				524	I->setReg(ARM::CPSR);
				525	return;
				526	}
				527	}
				528	}
				529
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	530	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	531	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	532	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	533	raw_ostream &os,
				534	raw_ostream &cs) const {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	535	uint8_t bytes[4];
				536
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	537	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				538	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				539
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	540	// We want to read exactly 2 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	541	if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
				542	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	543	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	544	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	545
				546	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	547	DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	548	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	549	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	550	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	551	return result;
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	552	}
				553
				554	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	555	result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	556	if (result) {
				557	Size = 2;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	558	bool InITBlock = !ITBlock.empty();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	559	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	560	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	561	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	562	}
				563
				564	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	565	result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	566	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	567	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	568	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	569
				570	// If we find an IT instruction, we need to parse its condition
				571	// code and mask operands so that we can apply them correctly
				572	// to the subsequent instructions.
				573	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	34626ac	2011-09-14 21:06:21 +0000	[diff] [blame]	574	// Nested IT blocks are UNPREDICTABLE.
				575	if (!ITBlock.empty())
				576	return MCDisassembler::SoftFail;
				577
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	578	// (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	579	unsigned firstcond = MI.getOperand(0).getImm();
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	580	unsigned Mask = MI.getOperand(1).getImm();
				581	unsigned CondBit0 = Mask >> 4 & 1;
				582	unsigned NumTZ = CountTrailingZeros_32(Mask);
				583	assert(NumTZ <= 3 && "Invalid IT mask!");
				584	for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
				585	bool T = ((Mask >> Pos) & 1) == CondBit0;
				586	if (T)
				587	ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	588	else
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	589	ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	590	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	591
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	592	ITBlock.push_back(firstcond);
				593	}
				594
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	595	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	596	}
				597
				598	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	599	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				600	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	601	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	602	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	603
				604	uint32_t insn32 = (bytes[3] << 8) \|
				605	(bytes[2] << 0) \|
				606	(bytes[1] << 24) \|
				607	(bytes[0] << 16);
				608	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	609	result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	610	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	611	Size = 4;
				612	bool InITBlock = ITBlock.size();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	613	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	614	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	615	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	616	}
				617
				618	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	619	result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	620	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	621	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	622	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	623	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	624	}
				625
				626	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	627	result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	628	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	629	Size = 4;
				630	UpdateThumbVFPPredicate(MI);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	631	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	632	}
				633
				634	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	635	result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	636	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	637	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	638	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	639	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	640	}
				641
				642	if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
				643	MI.clear();
				644	uint32_t NEONLdStInsn = insn32;
				645	NEONLdStInsn &= 0xF0FFFFFF;
				646	NEONLdStInsn \|= 0x04000000;
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	647	result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	648	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	649	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	650	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	651	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	652	}
				653	}
				654
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	655	if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	656	MI.clear();
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	657	uint32_t NEONDataInsn = insn32;
				658	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				659	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				660	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	661	result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	662	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	663	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	664	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	665	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	666	}
				667	}
				668
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	669	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	670	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	671	}
				672
				673
				674	extern "C" void LLVMInitializeARMDisassembler() {
				675	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				676	createARMDisassembler);
				677	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				678	createThumbDisassembler);
				679	}
				680
				681	static const unsigned GPRDecoderTable[] = {
				682	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				683	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				684	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				685	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				686	};
				687
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	688	static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	689	uint64_t Address, const void *Decoder) {
				690	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	691	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	692
				693	unsigned Register = GPRDecoderTable[RegNo];
				694	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	695	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	696	}
				697
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	698	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	699	DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
				700	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	701	if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	51c9805	2011-08-09 22:48:45 +0000	[diff] [blame]	702	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				703	}
				704
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	705	static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	706	uint64_t Address, const void *Decoder) {
				707	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	708	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	709	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				710	}
				711
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	712	static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	713	uint64_t Address, const void *Decoder) {
				714	unsigned Register = 0;
				715	switch (RegNo) {
				716	case 0:
				717	Register = ARM::R0;
				718	break;
				719	case 1:
				720	Register = ARM::R1;
				721	break;
				722	case 2:
				723	Register = ARM::R2;
				724	break;
				725	case 3:
				726	Register = ARM::R3;
				727	break;
				728	case 9:
				729	Register = ARM::R9;
				730	break;
				731	case 12:
				732	Register = ARM::R12;
				733	break;
				734	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	735	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	736	}
				737
				738	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	739	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	740	}
				741
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	742	static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	743	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	744	if (RegNo == 13 \|\| RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	745	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				746	}
				747
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	748	static const unsigned SPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	749	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				750	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				751	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				752	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				753	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				754	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				755	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				756	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				757	};
				758
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	759	static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	760	uint64_t Address, const void *Decoder) {
				761	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	762	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	763
				764	unsigned Register = SPRDecoderTable[RegNo];
				765	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	766	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	767	}
				768
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	769	static const unsigned DPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	770	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				771	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				772	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				773	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				774	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				775	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				776	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				777	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				778	};
				779
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	780	static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	781	uint64_t Address, const void *Decoder) {
				782	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	783	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	784
				785	unsigned Register = DPRDecoderTable[RegNo];
				786	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	787	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	788	}
				789
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	790	static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	791	uint64_t Address, const void *Decoder) {
				792	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	793	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	794	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				795	}
				796
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	797	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	798	DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
				799	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	800	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	801	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	802	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				803	}
				804
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	805	static const unsigned QPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	806	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				807	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				808	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				809	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				810	};
				811
				812
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	813	static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	814	uint64_t Address, const void *Decoder) {
				815	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	816	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	817	RegNo >>= 1;
				818
				819	unsigned Register = QPRDecoderTable[RegNo];
				820	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	821	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	822	}
				823
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	824	static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	825	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	826	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	bd9091c	2011-08-09 21:07:45 +0000	[diff] [blame]	827	// AL predicate is not allowed on Thumb1 branches.
				828	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	829	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	830	Inst.addOperand(MCOperand::CreateImm(Val));
				831	if (Val == ARMCC::AL) {
				832	Inst.addOperand(MCOperand::CreateReg(0));
				833	} else
				834	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	835	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	836	}
				837
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	838	static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	839	uint64_t Address, const void *Decoder) {
				840	if (Val)
				841	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				842	else
				843	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	844	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	845	}
				846
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	847	static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	848	uint64_t Address, const void *Decoder) {
				849	uint32_t imm = Val & 0xFF;
				850	uint32_t rot = (Val & 0xF00) >> 7;
				851	uint32_t rot_imm = (imm >> rot) \| (imm << (32-rot));
				852	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	853	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	854	}
				855
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	856	static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	857	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	858	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	859
				860	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				861	unsigned type = fieldFromInstruction32(Val, 5, 2);
				862	unsigned imm = fieldFromInstruction32(Val, 7, 5);
				863
				864	// Register-immediate
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	865	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				866	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	867
				868	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				869	switch (type) {
				870	case 0:
				871	Shift = ARM_AM::lsl;
				872	break;
				873	case 1:
				874	Shift = ARM_AM::lsr;
				875	break;
				876	case 2:
				877	Shift = ARM_AM::asr;
				878	break;
				879	case 3:
				880	Shift = ARM_AM::ror;
				881	break;
				882	}
				883
				884	if (Shift == ARM_AM::ror && imm == 0)
				885	Shift = ARM_AM::rrx;
				886
				887	unsigned Op = Shift \| (imm << 3);
				888	Inst.addOperand(MCOperand::CreateImm(Op));
				889
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	890	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	891	}
				892
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	893	static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	894	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	895	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	896
				897	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				898	unsigned type = fieldFromInstruction32(Val, 5, 2);
				899	unsigned Rs = fieldFromInstruction32(Val, 8, 4);
				900
				901	// Register-register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	902	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				903	return MCDisassembler::Fail;
				904	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				905	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	906
				907	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				908	switch (type) {
				909	case 0:
				910	Shift = ARM_AM::lsl;
				911	break;
				912	case 1:
				913	Shift = ARM_AM::lsr;
				914	break;
				915	case 2:
				916	Shift = ARM_AM::asr;
				917	break;
				918	case 3:
				919	Shift = ARM_AM::ror;
				920	break;
				921	}
				922
				923	Inst.addOperand(MCOperand::CreateImm(Shift));
				924
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	925	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	926	}
				927
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	928	static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	929	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	930	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	931
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	932	bool writebackLoad = false;
				933	unsigned writebackReg = 0;
				934	switch (Inst.getOpcode()) {
				935	default:
				936	break;
				937	case ARM::LDMIA_UPD:
				938	case ARM::LDMDB_UPD:
				939	case ARM::LDMIB_UPD:
				940	case ARM::LDMDA_UPD:
				941	case ARM::t2LDMIA_UPD:
				942	case ARM::t2LDMDB_UPD:
				943	writebackLoad = true;
				944	writebackReg = Inst.getOperand(0).getReg();
				945	break;
				946	}
				947
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	948	// Empty register lists are not allowed.
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	949	if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	950	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	951	if (Val & (1 << i)) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	952	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				953	return MCDisassembler::Fail;
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	954	// Writeback not allowed if Rn is in the target list.
				955	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				956	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	957	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	958	}
				959
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	960	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	961	}
				962
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	963	static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	964	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	965	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	966
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	967	unsigned Vd = fieldFromInstruction32(Val, 8, 4);
				968	unsigned regs = Val & 0xFF;
				969
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	970	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				971	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	972	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	973	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				974	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	975	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	976
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	977	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	978	}
				979
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	980	static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	981	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	982	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	983
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	984	unsigned Vd = fieldFromInstruction32(Val, 8, 4);
				985	unsigned regs = (Val & 0xFF) / 2;
				986
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	987	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				988	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	989	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	990	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				991	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	992	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	993
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	994	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	995	}
				996
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	997	static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	998	uint64_t Address, const void *Decoder) {
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	999	// This operand encodes a mask of contiguous zeros between a specified MSB
				1000	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1001	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1002	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1003	// create the final mask.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1004	unsigned msb = fieldFromInstruction32(Val, 5, 5);
				1005	unsigned lsb = fieldFromInstruction32(Val, 0, 5);
				1006	uint32_t msb_mask = (1 << (msb+1)) - 1;
				1007	uint32_t lsb_mask = (1 << lsb) - 1;
				1008	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1009	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1010	}
				1011
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1012	static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1013	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1014	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1015
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1016	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1017	unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
				1018	unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
				1019	unsigned imm = fieldFromInstruction32(Insn, 0, 8);
				1020	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1021	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				1022
				1023	switch (Inst.getOpcode()) {
				1024	case ARM::LDC_OFFSET:
				1025	case ARM::LDC_PRE:
				1026	case ARM::LDC_POST:
				1027	case ARM::LDC_OPTION:
				1028	case ARM::LDCL_OFFSET:
				1029	case ARM::LDCL_PRE:
				1030	case ARM::LDCL_POST:
				1031	case ARM::LDCL_OPTION:
				1032	case ARM::STC_OFFSET:
				1033	case ARM::STC_PRE:
				1034	case ARM::STC_POST:
				1035	case ARM::STC_OPTION:
				1036	case ARM::STCL_OFFSET:
				1037	case ARM::STCL_PRE:
				1038	case ARM::STCL_POST:
				1039	case ARM::STCL_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1040	case ARM::t2LDC_OFFSET:
				1041	case ARM::t2LDC_PRE:
				1042	case ARM::t2LDC_POST:
				1043	case ARM::t2LDC_OPTION:
				1044	case ARM::t2LDCL_OFFSET:
				1045	case ARM::t2LDCL_PRE:
				1046	case ARM::t2LDCL_POST:
				1047	case ARM::t2LDCL_OPTION:
				1048	case ARM::t2STC_OFFSET:
				1049	case ARM::t2STC_PRE:
				1050	case ARM::t2STC_POST:
				1051	case ARM::t2STC_OPTION:
				1052	case ARM::t2STCL_OFFSET:
				1053	case ARM::t2STCL_PRE:
				1054	case ARM::t2STCL_POST:
				1055	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1056	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1057	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1058	break;
				1059	default:
				1060	break;
				1061	}
				1062
				1063	Inst.addOperand(MCOperand::CreateImm(coproc));
				1064	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1065	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1066	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1067	switch (Inst.getOpcode()) {
				1068	case ARM::LDC_OPTION:
				1069	case ARM::LDCL_OPTION:
				1070	case ARM::LDC2_OPTION:
				1071	case ARM::LDC2L_OPTION:
				1072	case ARM::STC_OPTION:
				1073	case ARM::STCL_OPTION:
				1074	case ARM::STC2_OPTION:
				1075	case ARM::STC2L_OPTION:
				1076	case ARM::LDCL_POST:
				1077	case ARM::STCL_POST:
Owen Anderson	78affc9	2011-08-18 22:47:44 +0000	[diff] [blame]	1078	case ARM::LDC2L_POST:
				1079	case ARM::STC2L_POST:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1080	case ARM::t2LDC_OPTION:
				1081	case ARM::t2LDCL_OPTION:
				1082	case ARM::t2STC_OPTION:
				1083	case ARM::t2STCL_OPTION:
				1084	case ARM::t2LDCL_POST:
				1085	case ARM::t2STCL_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1086	break;
				1087	default:
				1088	Inst.addOperand(MCOperand::CreateReg(0));
				1089	break;
				1090	}
				1091
				1092	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1093	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1094
				1095	bool writeback = (P == 0) \|\| (W == 1);
				1096	unsigned idx_mode = 0;
				1097	if (P && writeback)
				1098	idx_mode = ARMII::IndexModePre;
				1099	else if (!P && writeback)
				1100	idx_mode = ARMII::IndexModePost;
				1101
				1102	switch (Inst.getOpcode()) {
				1103	case ARM::LDCL_POST:
				1104	case ARM::STCL_POST:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1105	case ARM::t2LDCL_POST:
				1106	case ARM::t2STCL_POST:
Owen Anderson	78affc9	2011-08-18 22:47:44 +0000	[diff] [blame]	1107	case ARM::LDC2L_POST:
				1108	case ARM::STC2L_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1109	imm \|= U << 8;
				1110	case ARM::LDC_OPTION:
				1111	case ARM::LDCL_OPTION:
				1112	case ARM::LDC2_OPTION:
				1113	case ARM::LDC2L_OPTION:
				1114	case ARM::STC_OPTION:
				1115	case ARM::STCL_OPTION:
				1116	case ARM::STC2_OPTION:
				1117	case ARM::STC2L_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1118	case ARM::t2LDC_OPTION:
				1119	case ARM::t2LDCL_OPTION:
				1120	case ARM::t2STC_OPTION:
				1121	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1122	Inst.addOperand(MCOperand::CreateImm(imm));
				1123	break;
				1124	default:
				1125	if (U)
				1126	Inst.addOperand(MCOperand::CreateImm(
				1127	ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
				1128	else
				1129	Inst.addOperand(MCOperand::CreateImm(
				1130	ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
				1131	break;
				1132	}
				1133
				1134	switch (Inst.getOpcode()) {
				1135	case ARM::LDC_OFFSET:
				1136	case ARM::LDC_PRE:
				1137	case ARM::LDC_POST:
				1138	case ARM::LDC_OPTION:
				1139	case ARM::LDCL_OFFSET:
				1140	case ARM::LDCL_PRE:
				1141	case ARM::LDCL_POST:
				1142	case ARM::LDCL_OPTION:
				1143	case ARM::STC_OFFSET:
				1144	case ARM::STC_PRE:
				1145	case ARM::STC_POST:
				1146	case ARM::STC_OPTION:
				1147	case ARM::STCL_OFFSET:
				1148	case ARM::STCL_PRE:
				1149	case ARM::STCL_POST:
				1150	case ARM::STCL_OPTION:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1151	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1152	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1153	break;
				1154	default:
				1155	break;
				1156	}
				1157
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1158	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1159	}
				1160
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1161	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1162	DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
				1163	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1164	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1165
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1166	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1167	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				1168	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1169	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				1170	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1171	unsigned reg = fieldFromInstruction32(Insn, 25, 1);
				1172	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1173	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1174
				1175	// On stores, the writeback operand precedes Rt.
				1176	switch (Inst.getOpcode()) {
				1177	case ARM::STR_POST_IMM:
				1178	case ARM::STR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1179	case ARM::STRB_POST_IMM:
				1180	case ARM::STRB_POST_REG:
Jim Grosbach	342ebd5	2011-08-11 22:18:00 +0000	[diff] [blame]	1181	case ARM::STRT_POST_REG:
				1182	case ARM::STRT_POST_IMM:
Jim Grosbach	10348e7	2011-08-11 20:04:56 +0000	[diff] [blame]	1183	case ARM::STRBT_POST_REG:
				1184	case ARM::STRBT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1185	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1186	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1187	break;
				1188	default:
				1189	break;
				1190	}
				1191
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1192	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1193	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1194
				1195	// On loads, the writeback operand comes after Rt.
				1196	switch (Inst.getOpcode()) {
				1197	case ARM::LDR_POST_IMM:
				1198	case ARM::LDR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1199	case ARM::LDRB_POST_IMM:
				1200	case ARM::LDRB_POST_REG:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1201	case ARM::LDRBT_POST_REG:
				1202	case ARM::LDRBT_POST_IMM:
Jim Grosbach	5999926	2011-08-10 23:43:54 +0000	[diff] [blame]	1203	case ARM::LDRT_POST_REG:
				1204	case ARM::LDRT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1205	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1206	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1207	break;
				1208	default:
				1209	break;
				1210	}
				1211
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1212	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1213	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1214
				1215	ARM_AM::AddrOpc Op = ARM_AM::add;
				1216	if (!fieldFromInstruction32(Insn, 23, 1))
				1217	Op = ARM_AM::sub;
				1218
				1219	bool writeback = (P == 0) \|\| (W == 1);
				1220	unsigned idx_mode = 0;
				1221	if (P && writeback)
				1222	idx_mode = ARMII::IndexModePre;
				1223	else if (!P && writeback)
				1224	idx_mode = ARMII::IndexModePost;
				1225
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1226	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1227	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	71156a6	2011-08-11 19:00:18 +0000	[diff] [blame]	1228
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1229	if (reg) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1230	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1231	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1232	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
				1233	switch( fieldFromInstruction32(Insn, 5, 2)) {
				1234	case 0:
				1235	Opc = ARM_AM::lsl;
				1236	break;
				1237	case 1:
				1238	Opc = ARM_AM::lsr;
				1239	break;
				1240	case 2:
				1241	Opc = ARM_AM::asr;
				1242	break;
				1243	case 3:
				1244	Opc = ARM_AM::ror;
				1245	break;
				1246	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1247	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1248	}
				1249	unsigned amt = fieldFromInstruction32(Insn, 7, 5);
				1250	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1251
				1252	Inst.addOperand(MCOperand::CreateImm(imm));
				1253	} else {
				1254	Inst.addOperand(MCOperand::CreateReg(0));
				1255	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1256	Inst.addOperand(MCOperand::CreateImm(tmp));
				1257	}
				1258
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1259	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1260	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1261
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1262	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1263	}
				1264
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1265	static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1266	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1267	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1268
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1269	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				1270	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				1271	unsigned type = fieldFromInstruction32(Val, 5, 2);
				1272	unsigned imm = fieldFromInstruction32(Val, 7, 5);
				1273	unsigned U = fieldFromInstruction32(Val, 12, 1);
				1274
Owen Anderson	51157d2	2011-08-09 21:38:14 +0000	[diff] [blame]	1275	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1276	switch (type) {
				1277	case 0:
				1278	ShOp = ARM_AM::lsl;
				1279	break;
				1280	case 1:
				1281	ShOp = ARM_AM::lsr;
				1282	break;
				1283	case 2:
				1284	ShOp = ARM_AM::asr;
				1285	break;
				1286	case 3:
				1287	ShOp = ARM_AM::ror;
				1288	break;
				1289	}
				1290
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1291	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1292	return MCDisassembler::Fail;
				1293	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1294	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1295	unsigned shift;
				1296	if (U)
				1297	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1298	else
				1299	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1300	Inst.addOperand(MCOperand::CreateImm(shift));
				1301
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1302	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1303	}
				1304
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1305	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1306	DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
				1307	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1308	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1309
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1310	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				1311	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1312	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1313	unsigned type = fieldFromInstruction32(Insn, 22, 1);
				1314	unsigned imm = fieldFromInstruction32(Insn, 8, 4);
				1315	unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
				1316	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1317	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1318	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1319
				1320	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1321
				1322	// For {LD,ST}RD, Rt must be even, else undefined.
				1323	switch (Inst.getOpcode()) {
				1324	case ARM::STRD:
				1325	case ARM::STRD_PRE:
				1326	case ARM::STRD_POST:
				1327	case ARM::LDRD:
				1328	case ARM::LDRD_PRE:
				1329	case ARM::LDRD_POST:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1330	if (Rt & 0x1) return MCDisassembler::Fail;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1331	break;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1332	default:
				1333	break;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1334	}
				1335
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1336	if (writeback) { // Writeback
				1337	if (P)
				1338	U \|= ARMII::IndexModePre << 9;
				1339	else
				1340	U \|= ARMII::IndexModePost << 9;
				1341
				1342	// On stores, the writeback operand precedes Rt.
				1343	switch (Inst.getOpcode()) {
				1344	case ARM::STRD:
				1345	case ARM::STRD_PRE:
				1346	case ARM::STRD_POST:
Owen Anderson	79628e9	2011-08-12 20:02:50 +0000	[diff] [blame]	1347	case ARM::STRH:
				1348	case ARM::STRH_PRE:
				1349	case ARM::STRH_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1350	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1351	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1352	break;
				1353	default:
				1354	break;
				1355	}
				1356	}
				1357
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1358	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1359	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1360	switch (Inst.getOpcode()) {
				1361	case ARM::STRD:
				1362	case ARM::STRD_PRE:
				1363	case ARM::STRD_POST:
				1364	case ARM::LDRD:
				1365	case ARM::LDRD_PRE:
				1366	case ARM::LDRD_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1367	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1368	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1369	break;
				1370	default:
				1371	break;
				1372	}
				1373
				1374	if (writeback) {
				1375	// On loads, the writeback operand comes after Rt.
				1376	switch (Inst.getOpcode()) {
				1377	case ARM::LDRD:
				1378	case ARM::LDRD_PRE:
				1379	case ARM::LDRD_POST:
Owen Anderson	0d09499	2011-08-12 20:36:11 +0000	[diff] [blame]	1380	case ARM::LDRH:
				1381	case ARM::LDRH_PRE:
				1382	case ARM::LDRH_POST:
				1383	case ARM::LDRSH:
				1384	case ARM::LDRSH_PRE:
				1385	case ARM::LDRSH_POST:
				1386	case ARM::LDRSB:
				1387	case ARM::LDRSB_PRE:
				1388	case ARM::LDRSB_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1389	case ARM::LDRHTr:
				1390	case ARM::LDRSBTr:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1391	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1392	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1393	break;
				1394	default:
				1395	break;
				1396	}
				1397	}
				1398
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1399	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1400	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1401
				1402	if (type) {
				1403	Inst.addOperand(MCOperand::CreateReg(0));
				1404	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1405	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1406	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1407	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1408	Inst.addOperand(MCOperand::CreateImm(U));
				1409	}
				1410
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1411	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1412	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1413
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1414	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1415	}
				1416
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1417	static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1418	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1419	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1420
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1421	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1422	unsigned mode = fieldFromInstruction32(Insn, 23, 2);
				1423
				1424	switch (mode) {
				1425	case 0:
				1426	mode = ARM_AM::da;
				1427	break;
				1428	case 1:
				1429	mode = ARM_AM::ia;
				1430	break;
				1431	case 2:
				1432	mode = ARM_AM::db;
				1433	break;
				1434	case 3:
				1435	mode = ARM_AM::ib;
				1436	break;
				1437	}
				1438
				1439	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1440	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1441	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1442
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1443	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1444	}
				1445
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1446	static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1447	unsigned Insn,
				1448	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1449	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1450
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1451	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1452	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1453	unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
				1454
				1455	if (pred == 0xF) {
				1456	switch (Inst.getOpcode()) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1457	case ARM::LDMDA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1458	Inst.setOpcode(ARM::RFEDA);
				1459	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1460	case ARM::LDMDA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1461	Inst.setOpcode(ARM::RFEDA_UPD);
				1462	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1463	case ARM::LDMDB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1464	Inst.setOpcode(ARM::RFEDB);
				1465	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1466	case ARM::LDMDB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1467	Inst.setOpcode(ARM::RFEDB_UPD);
				1468	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1469	case ARM::LDMIA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1470	Inst.setOpcode(ARM::RFEIA);
				1471	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1472	case ARM::LDMIA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1473	Inst.setOpcode(ARM::RFEIA_UPD);
				1474	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1475	case ARM::LDMIB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1476	Inst.setOpcode(ARM::RFEIB);
				1477	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1478	case ARM::LDMIB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1479	Inst.setOpcode(ARM::RFEIB_UPD);
				1480	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1481	case ARM::STMDA:
				1482	Inst.setOpcode(ARM::SRSDA);
				1483	break;
				1484	case ARM::STMDA_UPD:
				1485	Inst.setOpcode(ARM::SRSDA_UPD);
				1486	break;
				1487	case ARM::STMDB:
				1488	Inst.setOpcode(ARM::SRSDB);
				1489	break;
				1490	case ARM::STMDB_UPD:
				1491	Inst.setOpcode(ARM::SRSDB_UPD);
				1492	break;
				1493	case ARM::STMIA:
				1494	Inst.setOpcode(ARM::SRSIA);
				1495	break;
				1496	case ARM::STMIA_UPD:
				1497	Inst.setOpcode(ARM::SRSIA_UPD);
				1498	break;
				1499	case ARM::STMIB:
				1500	Inst.setOpcode(ARM::SRSIB);
				1501	break;
				1502	case ARM::STMIB_UPD:
				1503	Inst.setOpcode(ARM::SRSIB_UPD);
				1504	break;
				1505	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1506	if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1507	}
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1508
				1509	// For stores (which become SRS's, the only operand is the mode.
				1510	if (fieldFromInstruction32(Insn, 20, 1) == 0) {
				1511	Inst.addOperand(
				1512	MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
				1513	return S;
				1514	}
				1515
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1516	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1517	}
				1518
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1519	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1520	return MCDisassembler::Fail;
				1521	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1522	return MCDisassembler::Fail; // Tied
				1523	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1524	return MCDisassembler::Fail;
				1525	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1526	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1527
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1528	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1529	}
				1530
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1531	static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1532	uint64_t Address, const void *Decoder) {
				1533	unsigned imod = fieldFromInstruction32(Insn, 18, 2);
				1534	unsigned M = fieldFromInstruction32(Insn, 17, 1);
				1535	unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
				1536	unsigned mode = fieldFromInstruction32(Insn, 0, 5);
				1537
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1538	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	1539
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1540	// imod == '01' --> UNPREDICTABLE
				1541	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1542	// return failure here. The '01' imod value is unprintable, so there's
				1543	// nothing useful we could do even if we returned UNPREDICTABLE.
				1544
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1545	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1546
				1547	if (imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1548	Inst.setOpcode(ARM::CPS3p);
				1549	Inst.addOperand(MCOperand::CreateImm(imod));
				1550	Inst.addOperand(MCOperand::CreateImm(iflags));
				1551	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1552	} else if (imod && !M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1553	Inst.setOpcode(ARM::CPS2p);
				1554	Inst.addOperand(MCOperand::CreateImm(imod));
				1555	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1556	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1557	} else if (!imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1558	Inst.setOpcode(ARM::CPS1p);
				1559	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1560	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1561	} else {
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1562	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1563	Inst.setOpcode(ARM::CPS1p);
				1564	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1565	S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1566	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1567
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1568	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1569	}
				1570
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1571	static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1572	uint64_t Address, const void *Decoder) {
				1573	unsigned imod = fieldFromInstruction32(Insn, 9, 2);
				1574	unsigned M = fieldFromInstruction32(Insn, 8, 1);
				1575	unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
				1576	unsigned mode = fieldFromInstruction32(Insn, 0, 5);
				1577
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1578	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1579
				1580	// imod == '01' --> UNPREDICTABLE
				1581	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1582	// return failure here. The '01' imod value is unprintable, so there's
				1583	// nothing useful we could do even if we returned UNPREDICTABLE.
				1584
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1585	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1586
				1587	if (imod && M) {
				1588	Inst.setOpcode(ARM::t2CPS3p);
				1589	Inst.addOperand(MCOperand::CreateImm(imod));
				1590	Inst.addOperand(MCOperand::CreateImm(iflags));
				1591	Inst.addOperand(MCOperand::CreateImm(mode));
				1592	} else if (imod && !M) {
				1593	Inst.setOpcode(ARM::t2CPS2p);
				1594	Inst.addOperand(MCOperand::CreateImm(imod));
				1595	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1596	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1597	} else if (!imod && M) {
				1598	Inst.setOpcode(ARM::t2CPS1p);
				1599	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1600	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1601	} else {
				1602	// imod == '00' && M == '0' --> UNPREDICTABLE
				1603	Inst.setOpcode(ARM::t2CPS1p);
				1604	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1605	S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1606	}
				1607
				1608	return S;
				1609	}
				1610
				1611
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1612	static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1613	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1614	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1615
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1616	unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
				1617	unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
				1618	unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
				1619	unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
				1620	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1621
				1622	if (pred == 0xF)
				1623	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1624
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1625	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1626	return MCDisassembler::Fail;
				1627	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1628	return MCDisassembler::Fail;
				1629	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1630	return MCDisassembler::Fail;
				1631	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				1632	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1633
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1634	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1635	return MCDisassembler::Fail;
Owen Anderson	1fb6673	2011-08-11 22:05:38 +0000	[diff] [blame]	1636
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1637	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1638	}
				1639
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1640	static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1641	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1642	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1643
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1644	unsigned add = fieldFromInstruction32(Val, 12, 1);
				1645	unsigned imm = fieldFromInstruction32(Val, 0, 12);
				1646	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				1647
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1648	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1649	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1650
				1651	if (!add) imm *= -1;
				1652	if (imm == 0 && !add) imm = INT32_MIN;
				1653	Inst.addOperand(MCOperand::CreateImm(imm));
				1654
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1655	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1656	}
				1657
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1658	static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1659	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1660	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1661
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1662	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				1663	unsigned U = fieldFromInstruction32(Val, 8, 1);
				1664	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				1665
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1666	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1667	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1668
				1669	if (U)
				1670	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				1671	else
				1672	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				1673
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1674	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1675	}
				1676
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1677	static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1678	uint64_t Address, const void *Decoder) {
				1679	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				1680	}
				1681
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1682	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1683	DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
				1684	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1685	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1686
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1687	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1688	unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
				1689
				1690	if (pred == 0xF) {
				1691	Inst.setOpcode(ARM::BLXi);
				1692	imm \|= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	1693	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1694	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1695	}
				1696
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	1697	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1698	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1699	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1700
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1701	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1702	}
				1703
				1704
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1705	static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1706	uint64_t Address, const void *Decoder) {
				1707	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1708	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1709	}
				1710
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1711	static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1712	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1713	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1714
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1715	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				1716	unsigned align = fieldFromInstruction32(Val, 4, 2);
				1717
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1718	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1719	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1720	if (!align)
				1721	Inst.addOperand(MCOperand::CreateImm(0));
				1722	else
				1723	Inst.addOperand(MCOperand::CreateImm(4 << align));
				1724
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1725	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1726	}
				1727
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1728	static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1729	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1730	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1731
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1732	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				1733	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				1734	unsigned wb = fieldFromInstruction32(Insn, 16, 4);
				1735	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1736	Rn \|= fieldFromInstruction32(Insn, 4, 2) << 4;
				1737	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1738
				1739	// First output register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1740	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				1741	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1742
				1743	// Second output register
				1744	switch (Inst.getOpcode()) {
				1745	case ARM::VLD1q8:
				1746	case ARM::VLD1q16:
				1747	case ARM::VLD1q32:
				1748	case ARM::VLD1q64:
				1749	case ARM::VLD1q8_UPD:
				1750	case ARM::VLD1q16_UPD:
				1751	case ARM::VLD1q32_UPD:
				1752	case ARM::VLD1q64_UPD:
				1753	case ARM::VLD1d8T:
				1754	case ARM::VLD1d16T:
				1755	case ARM::VLD1d32T:
				1756	case ARM::VLD1d64T:
				1757	case ARM::VLD1d8T_UPD:
				1758	case ARM::VLD1d16T_UPD:
				1759	case ARM::VLD1d32T_UPD:
				1760	case ARM::VLD1d64T_UPD:
				1761	case ARM::VLD1d8Q:
				1762	case ARM::VLD1d16Q:
				1763	case ARM::VLD1d32Q:
				1764	case ARM::VLD1d64Q:
				1765	case ARM::VLD1d8Q_UPD:
				1766	case ARM::VLD1d16Q_UPD:
				1767	case ARM::VLD1d32Q_UPD:
				1768	case ARM::VLD1d64Q_UPD:
				1769	case ARM::VLD2d8:
				1770	case ARM::VLD2d16:
				1771	case ARM::VLD2d32:
				1772	case ARM::VLD2d8_UPD:
				1773	case ARM::VLD2d16_UPD:
				1774	case ARM::VLD2d32_UPD:
				1775	case ARM::VLD2q8:
				1776	case ARM::VLD2q16:
				1777	case ARM::VLD2q32:
				1778	case ARM::VLD2q8_UPD:
				1779	case ARM::VLD2q16_UPD:
				1780	case ARM::VLD2q32_UPD:
				1781	case ARM::VLD3d8:
				1782	case ARM::VLD3d16:
				1783	case ARM::VLD3d32:
				1784	case ARM::VLD3d8_UPD:
				1785	case ARM::VLD3d16_UPD:
				1786	case ARM::VLD3d32_UPD:
				1787	case ARM::VLD4d8:
				1788	case ARM::VLD4d16:
				1789	case ARM::VLD4d32:
				1790	case ARM::VLD4d8_UPD:
				1791	case ARM::VLD4d16_UPD:
				1792	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1793	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				1794	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1795	break;
				1796	case ARM::VLD2b8:
				1797	case ARM::VLD2b16:
				1798	case ARM::VLD2b32:
				1799	case ARM::VLD2b8_UPD:
				1800	case ARM::VLD2b16_UPD:
				1801	case ARM::VLD2b32_UPD:
				1802	case ARM::VLD3q8:
				1803	case ARM::VLD3q16:
				1804	case ARM::VLD3q32:
				1805	case ARM::VLD3q8_UPD:
				1806	case ARM::VLD3q16_UPD:
				1807	case ARM::VLD3q32_UPD:
				1808	case ARM::VLD4q8:
				1809	case ARM::VLD4q16:
				1810	case ARM::VLD4q32:
				1811	case ARM::VLD4q8_UPD:
				1812	case ARM::VLD4q16_UPD:
				1813	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1814	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				1815	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1816	default:
				1817	break;
				1818	}
				1819
				1820	// Third output register
				1821	switch(Inst.getOpcode()) {
				1822	case ARM::VLD1d8T:
				1823	case ARM::VLD1d16T:
				1824	case ARM::VLD1d32T:
				1825	case ARM::VLD1d64T:
				1826	case ARM::VLD1d8T_UPD:
				1827	case ARM::VLD1d16T_UPD:
				1828	case ARM::VLD1d32T_UPD:
				1829	case ARM::VLD1d64T_UPD:
				1830	case ARM::VLD1d8Q:
				1831	case ARM::VLD1d16Q:
				1832	case ARM::VLD1d32Q:
				1833	case ARM::VLD1d64Q:
				1834	case ARM::VLD1d8Q_UPD:
				1835	case ARM::VLD1d16Q_UPD:
				1836	case ARM::VLD1d32Q_UPD:
				1837	case ARM::VLD1d64Q_UPD:
				1838	case ARM::VLD2q8:
				1839	case ARM::VLD2q16:
				1840	case ARM::VLD2q32:
				1841	case ARM::VLD2q8_UPD:
				1842	case ARM::VLD2q16_UPD:
				1843	case ARM::VLD2q32_UPD:
				1844	case ARM::VLD3d8:
				1845	case ARM::VLD3d16:
				1846	case ARM::VLD3d32:
				1847	case ARM::VLD3d8_UPD:
				1848	case ARM::VLD3d16_UPD:
				1849	case ARM::VLD3d32_UPD:
				1850	case ARM::VLD4d8:
				1851	case ARM::VLD4d16:
				1852	case ARM::VLD4d32:
				1853	case ARM::VLD4d8_UPD:
				1854	case ARM::VLD4d16_UPD:
				1855	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1856	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				1857	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1858	break;
				1859	case ARM::VLD3q8:
				1860	case ARM::VLD3q16:
				1861	case ARM::VLD3q32:
				1862	case ARM::VLD3q8_UPD:
				1863	case ARM::VLD3q16_UPD:
				1864	case ARM::VLD3q32_UPD:
				1865	case ARM::VLD4q8:
				1866	case ARM::VLD4q16:
				1867	case ARM::VLD4q32:
				1868	case ARM::VLD4q8_UPD:
				1869	case ARM::VLD4q16_UPD:
				1870	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1871	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				1872	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1873	break;
				1874	default:
				1875	break;
				1876	}
				1877
				1878	// Fourth output register
				1879	switch (Inst.getOpcode()) {
				1880	case ARM::VLD1d8Q:
				1881	case ARM::VLD1d16Q:
				1882	case ARM::VLD1d32Q:
				1883	case ARM::VLD1d64Q:
				1884	case ARM::VLD1d8Q_UPD:
				1885	case ARM::VLD1d16Q_UPD:
				1886	case ARM::VLD1d32Q_UPD:
				1887	case ARM::VLD1d64Q_UPD:
				1888	case ARM::VLD2q8:
				1889	case ARM::VLD2q16:
				1890	case ARM::VLD2q32:
				1891	case ARM::VLD2q8_UPD:
				1892	case ARM::VLD2q16_UPD:
				1893	case ARM::VLD2q32_UPD:
				1894	case ARM::VLD4d8:
				1895	case ARM::VLD4d16:
				1896	case ARM::VLD4d32:
				1897	case ARM::VLD4d8_UPD:
				1898	case ARM::VLD4d16_UPD:
				1899	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1900	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				1901	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1902	break;
				1903	case ARM::VLD4q8:
				1904	case ARM::VLD4q16:
				1905	case ARM::VLD4q32:
				1906	case ARM::VLD4q8_UPD:
				1907	case ARM::VLD4q16_UPD:
				1908	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1909	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				1910	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1911	break;
				1912	default:
				1913	break;
				1914	}
				1915
				1916	// Writeback operand
				1917	switch (Inst.getOpcode()) {
				1918	case ARM::VLD1d8_UPD:
				1919	case ARM::VLD1d16_UPD:
				1920	case ARM::VLD1d32_UPD:
				1921	case ARM::VLD1d64_UPD:
				1922	case ARM::VLD1q8_UPD:
				1923	case ARM::VLD1q16_UPD:
				1924	case ARM::VLD1q32_UPD:
				1925	case ARM::VLD1q64_UPD:
				1926	case ARM::VLD1d8T_UPD:
				1927	case ARM::VLD1d16T_UPD:
				1928	case ARM::VLD1d32T_UPD:
				1929	case ARM::VLD1d64T_UPD:
				1930	case ARM::VLD1d8Q_UPD:
				1931	case ARM::VLD1d16Q_UPD:
				1932	case ARM::VLD1d32Q_UPD:
				1933	case ARM::VLD1d64Q_UPD:
				1934	case ARM::VLD2d8_UPD:
				1935	case ARM::VLD2d16_UPD:
				1936	case ARM::VLD2d32_UPD:
				1937	case ARM::VLD2q8_UPD:
				1938	case ARM::VLD2q16_UPD:
				1939	case ARM::VLD2q32_UPD:
				1940	case ARM::VLD2b8_UPD:
				1941	case ARM::VLD2b16_UPD:
				1942	case ARM::VLD2b32_UPD:
				1943	case ARM::VLD3d8_UPD:
				1944	case ARM::VLD3d16_UPD:
				1945	case ARM::VLD3d32_UPD:
				1946	case ARM::VLD3q8_UPD:
				1947	case ARM::VLD3q16_UPD:
				1948	case ARM::VLD3q32_UPD:
				1949	case ARM::VLD4d8_UPD:
				1950	case ARM::VLD4d16_UPD:
				1951	case ARM::VLD4d32_UPD:
				1952	case ARM::VLD4q8_UPD:
				1953	case ARM::VLD4q16_UPD:
				1954	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1955	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				1956	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1957	break;
				1958	default:
				1959	break;
				1960	}
				1961
				1962	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1963	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				1964	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1965
				1966	// AddrMode6 Offset (register)
				1967	if (Rm == 0xD)
				1968	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1969	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1970	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1971	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1972	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1973
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1974	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1975	}
				1976
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1977	static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1978	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1979	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1980
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1981	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				1982	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				1983	unsigned wb = fieldFromInstruction32(Insn, 16, 4);
				1984	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1985	Rn \|= fieldFromInstruction32(Insn, 4, 2) << 4;
				1986	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1987
				1988	// Writeback Operand
				1989	switch (Inst.getOpcode()) {
				1990	case ARM::VST1d8_UPD:
				1991	case ARM::VST1d16_UPD:
				1992	case ARM::VST1d32_UPD:
				1993	case ARM::VST1d64_UPD:
				1994	case ARM::VST1q8_UPD:
				1995	case ARM::VST1q16_UPD:
				1996	case ARM::VST1q32_UPD:
				1997	case ARM::VST1q64_UPD:
				1998	case ARM::VST1d8T_UPD:
				1999	case ARM::VST1d16T_UPD:
				2000	case ARM::VST1d32T_UPD:
				2001	case ARM::VST1d64T_UPD:
				2002	case ARM::VST1d8Q_UPD:
				2003	case ARM::VST1d16Q_UPD:
				2004	case ARM::VST1d32Q_UPD:
				2005	case ARM::VST1d64Q_UPD:
				2006	case ARM::VST2d8_UPD:
				2007	case ARM::VST2d16_UPD:
				2008	case ARM::VST2d32_UPD:
				2009	case ARM::VST2q8_UPD:
				2010	case ARM::VST2q16_UPD:
				2011	case ARM::VST2q32_UPD:
				2012	case ARM::VST2b8_UPD:
				2013	case ARM::VST2b16_UPD:
				2014	case ARM::VST2b32_UPD:
				2015	case ARM::VST3d8_UPD:
				2016	case ARM::VST3d16_UPD:
				2017	case ARM::VST3d32_UPD:
				2018	case ARM::VST3q8_UPD:
				2019	case ARM::VST3q16_UPD:
				2020	case ARM::VST3q32_UPD:
				2021	case ARM::VST4d8_UPD:
				2022	case ARM::VST4d16_UPD:
				2023	case ARM::VST4d32_UPD:
				2024	case ARM::VST4q8_UPD:
				2025	case ARM::VST4q16_UPD:
				2026	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2027	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2028	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2029	break;
				2030	default:
				2031	break;
				2032	}
				2033
				2034	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2035	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2036	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2037
				2038	// AddrMode6 Offset (register)
				2039	if (Rm == 0xD)
				2040	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2041	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2042	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2043	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2044	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2045
				2046	// First input register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2047	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2048	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2049
				2050	// Second input register
				2051	switch (Inst.getOpcode()) {
				2052	case ARM::VST1q8:
				2053	case ARM::VST1q16:
				2054	case ARM::VST1q32:
				2055	case ARM::VST1q64:
				2056	case ARM::VST1q8_UPD:
				2057	case ARM::VST1q16_UPD:
				2058	case ARM::VST1q32_UPD:
				2059	case ARM::VST1q64_UPD:
				2060	case ARM::VST1d8T:
				2061	case ARM::VST1d16T:
				2062	case ARM::VST1d32T:
				2063	case ARM::VST1d64T:
				2064	case ARM::VST1d8T_UPD:
				2065	case ARM::VST1d16T_UPD:
				2066	case ARM::VST1d32T_UPD:
				2067	case ARM::VST1d64T_UPD:
				2068	case ARM::VST1d8Q:
				2069	case ARM::VST1d16Q:
				2070	case ARM::VST1d32Q:
				2071	case ARM::VST1d64Q:
				2072	case ARM::VST1d8Q_UPD:
				2073	case ARM::VST1d16Q_UPD:
				2074	case ARM::VST1d32Q_UPD:
				2075	case ARM::VST1d64Q_UPD:
				2076	case ARM::VST2d8:
				2077	case ARM::VST2d16:
				2078	case ARM::VST2d32:
				2079	case ARM::VST2d8_UPD:
				2080	case ARM::VST2d16_UPD:
				2081	case ARM::VST2d32_UPD:
				2082	case ARM::VST2q8:
				2083	case ARM::VST2q16:
				2084	case ARM::VST2q32:
				2085	case ARM::VST2q8_UPD:
				2086	case ARM::VST2q16_UPD:
				2087	case ARM::VST2q32_UPD:
				2088	case ARM::VST3d8:
				2089	case ARM::VST3d16:
				2090	case ARM::VST3d32:
				2091	case ARM::VST3d8_UPD:
				2092	case ARM::VST3d16_UPD:
				2093	case ARM::VST3d32_UPD:
				2094	case ARM::VST4d8:
				2095	case ARM::VST4d16:
				2096	case ARM::VST4d32:
				2097	case ARM::VST4d8_UPD:
				2098	case ARM::VST4d16_UPD:
				2099	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2100	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2101	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2102	break;
				2103	case ARM::VST2b8:
				2104	case ARM::VST2b16:
				2105	case ARM::VST2b32:
				2106	case ARM::VST2b8_UPD:
				2107	case ARM::VST2b16_UPD:
				2108	case ARM::VST2b32_UPD:
				2109	case ARM::VST3q8:
				2110	case ARM::VST3q16:
				2111	case ARM::VST3q32:
				2112	case ARM::VST3q8_UPD:
				2113	case ARM::VST3q16_UPD:
				2114	case ARM::VST3q32_UPD:
				2115	case ARM::VST4q8:
				2116	case ARM::VST4q16:
				2117	case ARM::VST4q32:
				2118	case ARM::VST4q8_UPD:
				2119	case ARM::VST4q16_UPD:
				2120	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2121	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2122	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2123	break;
				2124	default:
				2125	break;
				2126	}
				2127
				2128	// Third input register
				2129	switch (Inst.getOpcode()) {
				2130	case ARM::VST1d8T:
				2131	case ARM::VST1d16T:
				2132	case ARM::VST1d32T:
				2133	case ARM::VST1d64T:
				2134	case ARM::VST1d8T_UPD:
				2135	case ARM::VST1d16T_UPD:
				2136	case ARM::VST1d32T_UPD:
				2137	case ARM::VST1d64T_UPD:
				2138	case ARM::VST1d8Q:
				2139	case ARM::VST1d16Q:
				2140	case ARM::VST1d32Q:
				2141	case ARM::VST1d64Q:
				2142	case ARM::VST1d8Q_UPD:
				2143	case ARM::VST1d16Q_UPD:
				2144	case ARM::VST1d32Q_UPD:
				2145	case ARM::VST1d64Q_UPD:
				2146	case ARM::VST2q8:
				2147	case ARM::VST2q16:
				2148	case ARM::VST2q32:
				2149	case ARM::VST2q8_UPD:
				2150	case ARM::VST2q16_UPD:
				2151	case ARM::VST2q32_UPD:
				2152	case ARM::VST3d8:
				2153	case ARM::VST3d16:
				2154	case ARM::VST3d32:
				2155	case ARM::VST3d8_UPD:
				2156	case ARM::VST3d16_UPD:
				2157	case ARM::VST3d32_UPD:
				2158	case ARM::VST4d8:
				2159	case ARM::VST4d16:
				2160	case ARM::VST4d32:
				2161	case ARM::VST4d8_UPD:
				2162	case ARM::VST4d16_UPD:
				2163	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2164	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2165	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2166	break;
				2167	case ARM::VST3q8:
				2168	case ARM::VST3q16:
				2169	case ARM::VST3q32:
				2170	case ARM::VST3q8_UPD:
				2171	case ARM::VST3q16_UPD:
				2172	case ARM::VST3q32_UPD:
				2173	case ARM::VST4q8:
				2174	case ARM::VST4q16:
				2175	case ARM::VST4q32:
				2176	case ARM::VST4q8_UPD:
				2177	case ARM::VST4q16_UPD:
				2178	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2179	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2180	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2181	break;
				2182	default:
				2183	break;
				2184	}
				2185
				2186	// Fourth input register
				2187	switch (Inst.getOpcode()) {
				2188	case ARM::VST1d8Q:
				2189	case ARM::VST1d16Q:
				2190	case ARM::VST1d32Q:
				2191	case ARM::VST1d64Q:
				2192	case ARM::VST1d8Q_UPD:
				2193	case ARM::VST1d16Q_UPD:
				2194	case ARM::VST1d32Q_UPD:
				2195	case ARM::VST1d64Q_UPD:
				2196	case ARM::VST2q8:
				2197	case ARM::VST2q16:
				2198	case ARM::VST2q32:
				2199	case ARM::VST2q8_UPD:
				2200	case ARM::VST2q16_UPD:
				2201	case ARM::VST2q32_UPD:
				2202	case ARM::VST4d8:
				2203	case ARM::VST4d16:
				2204	case ARM::VST4d32:
				2205	case ARM::VST4d8_UPD:
				2206	case ARM::VST4d16_UPD:
				2207	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2208	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2209	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2210	break;
				2211	case ARM::VST4q8:
				2212	case ARM::VST4q16:
				2213	case ARM::VST4q32:
				2214	case ARM::VST4q8_UPD:
				2215	case ARM::VST4q16_UPD:
				2216	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2217	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2218	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2219	break;
				2220	default:
				2221	break;
				2222	}
				2223
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2224	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2225	}
				2226
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2227	static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2228	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2229	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2230
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2231	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2232	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2233	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2234	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2235	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2236	unsigned size = fieldFromInstruction32(Insn, 6, 2);
				2237	unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
				2238
				2239	align *= (1 << size);
				2240
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2241	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2242	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2243	if (regs == 2) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2244	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2245	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2246	}
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2247	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2248	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2249	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2250	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2251
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2252	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2253	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2254	Inst.addOperand(MCOperand::CreateImm(align));
				2255
				2256	if (Rm == 0xD)
				2257	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2258	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2259	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2260	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2261	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2262
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2263	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2264	}
				2265
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2266	static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2267	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2268	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2269
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2270	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2271	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2272	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2273	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2274	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2275	unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
				2276	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2277	align = 2size;
				2278
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2279	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2280	return MCDisassembler::Fail;
				2281	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2282	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2283	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2284	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2285	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2286	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2287
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2288	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2289	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2290	Inst.addOperand(MCOperand::CreateImm(align));
				2291
				2292	if (Rm == 0xD)
				2293	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2294	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2295	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2296	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2297	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2298
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2299	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2300	}
				2301
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2302	static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2303	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2304	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2305
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2306	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2307	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2308	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2309	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2310	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2311
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2312	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2313	return MCDisassembler::Fail;
				2314	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2315	return MCDisassembler::Fail;
				2316	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2317	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2318	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2319	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2320	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2321	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2322
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2323	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2324	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2325	Inst.addOperand(MCOperand::CreateImm(0));
				2326
				2327	if (Rm == 0xD)
				2328	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2329	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2330	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2331	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2332	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2333
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2334	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2335	}
				2336
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2337	static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2338	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2339	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2340
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2341	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2342	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2343	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2344	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2345	unsigned size = fieldFromInstruction32(Insn, 6, 2);
				2346	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2347	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2348
				2349	if (size == 0x3) {
				2350	size = 4;
				2351	align = 16;
				2352	} else {
				2353	if (size == 2) {
				2354	size = 1 << size;
				2355	align *= 8;
				2356	} else {
				2357	size = 1 << size;
				2358	align = 4size;
				2359	}
				2360	}
				2361
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2362	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2363	return MCDisassembler::Fail;
				2364	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2365	return MCDisassembler::Fail;
				2366	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2367	return MCDisassembler::Fail;
				2368	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2369	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2370	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2371	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2372	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2373	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2374
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2375	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2376	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2377	Inst.addOperand(MCOperand::CreateImm(align));
				2378
				2379	if (Rm == 0xD)
				2380	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2381	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2382	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2383	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2384	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2385
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2386	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2387	}
				2388
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2389	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2390	DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
				2391	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2392	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2393
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2394	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2395	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2396	unsigned imm = fieldFromInstruction32(Insn, 0, 4);
				2397	imm \|= fieldFromInstruction32(Insn, 16, 3) << 4;
				2398	imm \|= fieldFromInstruction32(Insn, 24, 1) << 7;
				2399	imm \|= fieldFromInstruction32(Insn, 8, 4) << 8;
				2400	imm \|= fieldFromInstruction32(Insn, 5, 1) << 12;
				2401	unsigned Q = fieldFromInstruction32(Insn, 6, 1);
				2402
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2403	if (Q) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2404	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2405	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2406	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2407	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2408	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2409	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2410
				2411	Inst.addOperand(MCOperand::CreateImm(imm));
				2412
				2413	switch (Inst.getOpcode()) {
				2414	case ARM::VORRiv4i16:
				2415	case ARM::VORRiv2i32:
				2416	case ARM::VBICiv4i16:
				2417	case ARM::VBICiv2i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2418	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2419	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2420	break;
				2421	case ARM::VORRiv8i16:
				2422	case ARM::VORRiv4i32:
				2423	case ARM::VBICiv8i16:
				2424	case ARM::VBICiv4i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2425	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2426	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2427	break;
				2428	default:
				2429	break;
				2430	}
				2431
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2432	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2433	}
				2434
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2435	static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2436	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2437	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2438
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2439	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2440	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2441	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2442	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				2443	unsigned size = fieldFromInstruction32(Insn, 18, 2);
				2444
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2445	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2446	return MCDisassembler::Fail;
				2447	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2448	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2449	Inst.addOperand(MCOperand::CreateImm(8 << size));
				2450
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2451	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2452	}
				2453
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2454	static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2455	uint64_t Address, const void *Decoder) {
				2456	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2457	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2458	}
				2459
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2460	static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2461	uint64_t Address, const void *Decoder) {
				2462	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2463	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2464	}
				2465
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2466	static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2467	uint64_t Address, const void *Decoder) {
				2468	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2469	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2470	}
				2471
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2472	static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2473	uint64_t Address, const void *Decoder) {
				2474	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2475	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2476	}
				2477
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2478	static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2479	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2480	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2481
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2482	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2483	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2484	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2485	Rn \|= fieldFromInstruction32(Insn, 7, 1) << 4;
				2486	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2487	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				2488	unsigned op = fieldFromInstruction32(Insn, 6, 1);
				2489	unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
				2490
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2491	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2492	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2493	if (op) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2494	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2495	return MCDisassembler::Fail; // Writeback
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2496	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2497
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2498	for (unsigned i = 0; i < length; ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2499	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
				2500	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2501	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2502
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2503	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2504	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2505
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2506	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2507	}
				2508
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2509	static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2510	uint64_t Address, const void *Decoder) {
				2511	// The immediate needs to be a fully instantiated float. However, the
				2512	// auto-generated decoder is only able to fill in some of the bits
				2513	// necessary. For instance, the 'b' bit is replicated multiple times,
				2514	// and is even present in inverted form in one bit. We do a little
				2515	// binary parsing here to fill in those missing bits, and then
				2516	// reinterpret it all as a float.
				2517	union {
				2518	uint32_t integer;
				2519	float fp;
				2520	} fp_conv;
				2521
				2522	fp_conv.integer = Val;
				2523	uint32_t b = fieldFromInstruction32(Val, 25, 1);
				2524	fp_conv.integer \|= b << 26;
				2525	fp_conv.integer \|= b << 27;
				2526	fp_conv.integer \|= b << 28;
				2527	fp_conv.integer \|= b << 29;
				2528	fp_conv.integer \|= (~b & 0x1) << 30;
				2529
				2530	Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2531	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2532	}
				2533
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2534	static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2535	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2536	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2537
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2538	unsigned dst = fieldFromInstruction16(Insn, 8, 3);
				2539	unsigned imm = fieldFromInstruction16(Insn, 0, 8);
				2540
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2541	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				2542	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2543
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2544	switch(Inst.getOpcode()) {
Owen Anderson	1af7f72	2011-08-26 19:39:26 +0000	[diff] [blame]	2545	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2546	return MCDisassembler::Fail;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2547	case ARM::tADR:
Owen Anderson	9f7e831	2011-08-26 21:47:57 +0000	[diff] [blame]	2548	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2549	case ARM::tADDrSPi:
				2550	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2551	break;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2552	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2553
				2554	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2555	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2556	}
				2557
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2558	static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2559	uint64_t Address, const void *Decoder) {
				2560	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2561	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2562	}
				2563
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2564	static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2565	uint64_t Address, const void *Decoder) {
				2566	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2567	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2568	}
				2569
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2570	static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2571	uint64_t Address, const void *Decoder) {
				2572	Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2573	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2574	}
				2575
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2576	static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2577	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2578	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2579
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2580	unsigned Rn = fieldFromInstruction32(Val, 0, 3);
				2581	unsigned Rm = fieldFromInstruction32(Val, 3, 3);
				2582
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2583	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2584	return MCDisassembler::Fail;
				2585	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2586	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2587
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2588	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2589	}
				2590
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2591	static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2592	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2593	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2594
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2595	unsigned Rn = fieldFromInstruction32(Val, 0, 3);
				2596	unsigned imm = fieldFromInstruction32(Val, 3, 5);
				2597
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2598	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2599	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2600	Inst.addOperand(MCOperand::CreateImm(imm));
				2601
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2602	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2603	}
				2604
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2605	static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2606	uint64_t Address, const void *Decoder) {
				2607	Inst.addOperand(MCOperand::CreateImm(Val << 2));
				2608
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2609	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2610	}
				2611
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2612	static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2613	uint64_t Address, const void *Decoder) {
				2614	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b113ec5	2011-08-22 17:56:58 +0000	[diff] [blame]	2615	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2616
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2617	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2618	}
				2619
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2620	static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2621	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2622	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2623
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2624	unsigned Rn = fieldFromInstruction32(Val, 6, 4);
				2625	unsigned Rm = fieldFromInstruction32(Val, 2, 4);
				2626	unsigned imm = fieldFromInstruction32(Val, 0, 2);
				2627
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2628	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2629	return MCDisassembler::Fail;
				2630	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2631	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2632	Inst.addOperand(MCOperand::CreateImm(imm));
				2633
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2634	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2635	}
				2636
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2637	static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2638	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2639	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2640
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	2641	switch (Inst.getOpcode()) {
				2642	case ARM::t2PLDs:
				2643	case ARM::t2PLDWs:
				2644	case ARM::t2PLIs:
				2645	break;
				2646	default: {
				2647	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2648	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				2649	return MCDisassembler::Fail;
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	2650	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2651	}
				2652
				2653	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2654	if (Rn == 0xF) {
				2655	switch (Inst.getOpcode()) {
				2656	case ARM::t2LDRBs:
				2657	Inst.setOpcode(ARM::t2LDRBpci);
				2658	break;
				2659	case ARM::t2LDRHs:
				2660	Inst.setOpcode(ARM::t2LDRHpci);
				2661	break;
				2662	case ARM::t2LDRSHs:
				2663	Inst.setOpcode(ARM::t2LDRSHpci);
				2664	break;
				2665	case ARM::t2LDRSBs:
				2666	Inst.setOpcode(ARM::t2LDRSBpci);
				2667	break;
				2668	case ARM::t2PLDs:
				2669	Inst.setOpcode(ARM::t2PLDi12);
				2670	Inst.addOperand(MCOperand::CreateReg(ARM::PC));
				2671	break;
				2672	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2673	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2674	}
				2675
				2676	int imm = fieldFromInstruction32(Insn, 0, 12);
				2677	if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
				2678	Inst.addOperand(MCOperand::CreateImm(imm));
				2679
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2680	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2681	}
				2682
				2683	unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
				2684	addrmode \|= fieldFromInstruction32(Insn, 0, 4) << 2;
				2685	addrmode \|= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2686	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				2687	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2688
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2689	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2690	}
				2691
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2692	static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2693	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2694	int imm = Val & 0xFF;
				2695	if (!(Val & 0x100)) imm *= -1;
				2696	Inst.addOperand(MCOperand::CreateImm(imm << 2));
				2697
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2698	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2699	}
				2700
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2701	static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2702	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2703	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2704
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2705	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				2706	unsigned imm = fieldFromInstruction32(Val, 0, 9);
				2707
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2708	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2709	return MCDisassembler::Fail;
				2710	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				2711	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2712
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2713	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2714	}
				2715
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	2716	static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
				2717	uint64_t Address, const void *Decoder) {
				2718	DecodeStatus S = MCDisassembler::Success;
				2719
				2720	unsigned Rn = fieldFromInstruction32(Val, 8, 4);
				2721	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				2722
				2723	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2724	return MCDisassembler::Fail;
				2725
				2726	Inst.addOperand(MCOperand::CreateImm(imm));
				2727
				2728	return S;
				2729	}
				2730
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2731	static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2732	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2733	int imm = Val & 0xFF;
Owen Anderson	705b48f	2011-09-16 21:08:33 +0000	[diff] [blame^]	2734	if (Val == 0)
				2735	imm = INT32_MIN;
				2736	else if (!(Val & 0x100))
				2737	imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2738	Inst.addOperand(MCOperand::CreateImm(imm));
				2739
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2740	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2741	}
				2742
				2743
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2744	static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2745	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2746	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2747
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2748	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				2749	unsigned imm = fieldFromInstruction32(Val, 0, 9);
				2750
				2751	// Some instructions always use an additive offset.
				2752	switch (Inst.getOpcode()) {
				2753	case ARM::t2LDRT:
				2754	case ARM::t2LDRBT:
				2755	case ARM::t2LDRHT:
				2756	case ARM::t2LDRSBT:
				2757	case ARM::t2LDRSHT:
				2758	imm \|= 0x100;
				2759	break;
				2760	default:
				2761	break;
				2762	}
				2763
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2764	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2765	return MCDisassembler::Fail;
				2766	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				2767	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2768
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2769	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2770	}
				2771
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	2772	static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
				2773	uint64_t Address, const void *Decoder) {
				2774	DecodeStatus S = MCDisassembler::Success;
				2775
				2776	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				2777	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2778	unsigned addr = fieldFromInstruction32(Insn, 0, 8);
				2779	addr \|= fieldFromInstruction32(Insn, 9, 1) << 8;
				2780	addr \|= Rn << 9;
				2781	unsigned load = fieldFromInstruction32(Insn, 20, 1);
				2782
				2783	if (!load) {
				2784	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2785	return MCDisassembler::Fail;
				2786	}
				2787
				2788	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				2789	return MCDisassembler::Fail;
				2790
				2791	if (load) {
				2792	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2793	return MCDisassembler::Fail;
				2794	}
				2795
				2796	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				2797	return MCDisassembler::Fail;
				2798
				2799	return S;
				2800	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2801
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2802	static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2803	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2804	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2805
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2806	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				2807	unsigned imm = fieldFromInstruction32(Val, 0, 12);
				2808
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2809	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2810	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2811	Inst.addOperand(MCOperand::CreateImm(imm));
				2812
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2813	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2814	}
				2815
				2816
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2817	static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2818	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2819	unsigned imm = fieldFromInstruction16(Insn, 0, 7);
				2820
				2821	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2822	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2823	Inst.addOperand(MCOperand::CreateImm(imm));
				2824
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2825	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2826	}
				2827
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2828	static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2829	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2830	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2831
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2832	if (Inst.getOpcode() == ARM::tADDrSP) {
				2833	unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
				2834	Rdm \|= fieldFromInstruction16(Insn, 7, 1) << 3;
				2835
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2836	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				2837	return MCDisassembler::Fail;
				2838	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				2839	return MCDisassembler::Fail;
Owen Anderson	9990683	2011-08-25 18:30:18 +0000	[diff] [blame]	2840	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2841	} else if (Inst.getOpcode() == ARM::tADDspr) {
				2842	unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
				2843
				2844	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2845	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2846	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2847	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2848	}
				2849
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2850	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2851	}
				2852
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2853	static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2854	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2855	unsigned imod = fieldFromInstruction16(Insn, 4, 1) \| 0x2;
				2856	unsigned flags = fieldFromInstruction16(Insn, 0, 3);
				2857
				2858	Inst.addOperand(MCOperand::CreateImm(imod));
				2859	Inst.addOperand(MCOperand::CreateImm(flags));
				2860
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2861	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2862	}
				2863
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2864	static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2865	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2866	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2867	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2868	unsigned add = fieldFromInstruction32(Insn, 4, 1);
				2869
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2870	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2871	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2872	Inst.addOperand(MCOperand::CreateImm(add));
				2873
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2874	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2875	}
				2876
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2877	static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2878	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2879	Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2880	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2881	}
				2882
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2883	static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2884	uint64_t Address, const void *Decoder) {
				2885	if (Val == 0xA \|\| Val == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2886	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2887
				2888	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2889	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2890	}
				2891
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2892	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2893	DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
				2894	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2895	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2896
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2897	unsigned pred = fieldFromInstruction32(Insn, 22, 4);
				2898	if (pred == 0xE \|\| pred == 0xF) {
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2899	unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2900	switch (opc) {
				2901	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2902	return MCDisassembler::Fail;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2903	case 0xf3bf8f4:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2904	Inst.setOpcode(ARM::t2DSB);
				2905	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2906	case 0xf3bf8f5:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2907	Inst.setOpcode(ARM::t2DMB);
				2908	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2909	case 0xf3bf8f6:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2910	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	6de3c6f	2011-09-07 17:55:19 +0000	[diff] [blame]	2911	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2912	}
				2913
				2914	unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2915	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2916	}
				2917
				2918	unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
				2919	brtarget \|= fieldFromInstruction32(Insn, 11, 1) << 19;
				2920	brtarget \|= fieldFromInstruction32(Insn, 13, 1) << 18;
				2921	brtarget \|= fieldFromInstruction32(Insn, 16, 6) << 12;
				2922	brtarget \|= fieldFromInstruction32(Insn, 26, 1) << 20;
				2923
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2924	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				2925	return MCDisassembler::Fail;
				2926	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2927	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2928
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2929	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2930	}
				2931
				2932	// Decode a shifted immediate operand. These basically consist
				2933	// of an 8-bit value, and a 4-bit directive that specifies either
				2934	// a splat operation or a rotation.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2935	static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2936	uint64_t Address, const void *Decoder) {
				2937	unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
				2938	if (ctrl == 0) {
				2939	unsigned byte = fieldFromInstruction32(Val, 8, 2);
				2940	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				2941	switch (byte) {
				2942	case 0:
				2943	Inst.addOperand(MCOperand::CreateImm(imm));
				2944	break;
				2945	case 1:
				2946	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				2947	break;
				2948	case 2:
				2949	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				2950	break;
				2951	case 3:
				2952	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				2953	(imm << 8) \| imm));
				2954	break;
				2955	}
				2956	} else {
				2957	unsigned unrot = fieldFromInstruction32(Val, 0, 7) \| 0x80;
				2958	unsigned rot = fieldFromInstruction32(Val, 7, 5);
				2959	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				2960	Inst.addOperand(MCOperand::CreateImm(imm));
				2961	}
				2962
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2963	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2964	}
				2965
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2966	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2967	DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
				2968	uint64_t Address, const void *Decoder){
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2969	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2970	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2971	}
				2972
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2973	static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2974	uint64_t Address, const void *Decoder){
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2975	Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2976	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2977	}
				2978
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2979	static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2980	uint64_t Address, const void *Decoder) {
				2981	switch (Val) {
				2982	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2983	return MCDisassembler::Fail;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2984	case 0xF: // SY
				2985	case 0xE: // ST
				2986	case 0xB: // ISH
				2987	case 0xA: // ISHST
				2988	case 0x7: // NSH
				2989	case 0x6: // NSHST
				2990	case 0x3: // OSH
				2991	case 0x2: // OSHST
				2992	break;
				2993	}
				2994
				2995	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2996	return MCDisassembler::Success;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2997	}
				2998
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2999	static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3000	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3001	if (!Val) return MCDisassembler::Fail;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3002	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3003	return MCDisassembler::Success;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3004	}
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3005
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3006	static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3007	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3008	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3009
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3010	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3011	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3012	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3013
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3014	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3015
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3016	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3017	return MCDisassembler::Fail;
				3018	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3019	return MCDisassembler::Fail;
				3020	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3021	return MCDisassembler::Fail;
				3022	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3023	return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3024
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3025	return S;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3026	}
				3027
				3028
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3029	static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3030	uint64_t Address, const void *Decoder){
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3031	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3032
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3033	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3034	unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
				3035	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Anderson	adf2b09	2011-08-11 22:08:38 +0000	[diff] [blame]	3036	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3037
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3038	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				3039	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3040
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3041	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
				3042	if (Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1) return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3043
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3044	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3045	return MCDisassembler::Fail;
				3046	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3047	return MCDisassembler::Fail;
				3048	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3049	return MCDisassembler::Fail;
				3050	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3051	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3052
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3053	return S;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3054	}
				3055
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3056	static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3057	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3058	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3059
				3060	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3061	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3062	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3063	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3064	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3065	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3066
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3067	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3068
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3069	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3070	return MCDisassembler::Fail;
				3071	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3072	return MCDisassembler::Fail;
				3073	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3074	return MCDisassembler::Fail;
				3075	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3076	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3077
				3078	return S;
				3079	}
				3080
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3081	static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3082	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3083	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3084
				3085	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3086	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3087	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3088	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3089	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3090	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3091	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3092
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3093	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				3094	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3095
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3096	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3097	return MCDisassembler::Fail;
				3098	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3099	return MCDisassembler::Fail;
				3100	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3101	return MCDisassembler::Fail;
				3102	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3103	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3104
				3105	return S;
				3106	}
				3107
				3108
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3109	static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3110	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3111	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3112
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3113	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3114	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3115	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3116	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3117	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3118	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3119
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3120	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3121
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3122	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3123	return MCDisassembler::Fail;
				3124	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3125	return MCDisassembler::Fail;
				3126	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3127	return MCDisassembler::Fail;
				3128	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3129	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3130
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3131	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3132	}
				3133
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3134	static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3135	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3136	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3137
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3138	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3139	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3140	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3141	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3142	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3143	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3144
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3145	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3146
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3147	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3148	return MCDisassembler::Fail;
				3149	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3150	return MCDisassembler::Fail;
				3151	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3152	return MCDisassembler::Fail;
				3153	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3154	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3155
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3156	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3157	}
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3158
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3159	static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3160	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3161	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3162
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3163	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3164	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3165	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3166	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3167	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3168
				3169	unsigned align = 0;
				3170	unsigned index = 0;
				3171	switch (size) {
				3172	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3173	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3174	case 0:
				3175	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3176	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3177	index = fieldFromInstruction32(Insn, 5, 3);
				3178	break;
				3179	case 1:
				3180	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3181	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3182	index = fieldFromInstruction32(Insn, 6, 2);
				3183	if (fieldFromInstruction32(Insn, 4, 1))
				3184	align = 2;
				3185	break;
				3186	case 2:
				3187	if (fieldFromInstruction32(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3188	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3189	index = fieldFromInstruction32(Insn, 7, 1);
				3190	if (fieldFromInstruction32(Insn, 4, 2) != 0)
				3191	align = 4;
				3192	}
				3193
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3194	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3195	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3196	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3197	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3198	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3199	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3200	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3201	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3202	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3203	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3204	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3205	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3206	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3207	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3208	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3209	}
				3210
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3211	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3212	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3213	Inst.addOperand(MCOperand::CreateImm(index));
				3214
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3215	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3216	}
				3217
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3218	static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3219	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3220	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3221
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3222	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3223	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3224	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3225	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3226	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3227
				3228	unsigned align = 0;
				3229	unsigned index = 0;
				3230	switch (size) {
				3231	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3232	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3233	case 0:
				3234	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3235	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3236	index = fieldFromInstruction32(Insn, 5, 3);
				3237	break;
				3238	case 1:
				3239	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3240	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3241	index = fieldFromInstruction32(Insn, 6, 2);
				3242	if (fieldFromInstruction32(Insn, 4, 1))
				3243	align = 2;
				3244	break;
				3245	case 2:
				3246	if (fieldFromInstruction32(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3247	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3248	index = fieldFromInstruction32(Insn, 7, 1);
				3249	if (fieldFromInstruction32(Insn, 4, 2) != 0)
				3250	align = 4;
				3251	}
				3252
				3253	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3254	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3255	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3256	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3257	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3258	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3259	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3260	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3261	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3262	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3263	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3264	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3265	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3266	}
				3267
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3268	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3269	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3270	Inst.addOperand(MCOperand::CreateImm(index));
				3271
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3272	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3273	}
				3274
				3275
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3276	static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3277	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3278	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3279
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3280	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3281	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3282	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3283	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3284	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3285
				3286	unsigned align = 0;
				3287	unsigned index = 0;
				3288	unsigned inc = 1;
				3289	switch (size) {
				3290	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3291	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3292	case 0:
				3293	index = fieldFromInstruction32(Insn, 5, 3);
				3294	if (fieldFromInstruction32(Insn, 4, 1))
				3295	align = 2;
				3296	break;
				3297	case 1:
				3298	index = fieldFromInstruction32(Insn, 6, 2);
				3299	if (fieldFromInstruction32(Insn, 4, 1))
				3300	align = 4;
				3301	if (fieldFromInstruction32(Insn, 5, 1))
				3302	inc = 2;
				3303	break;
				3304	case 2:
				3305	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3306	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3307	index = fieldFromInstruction32(Insn, 7, 1);
				3308	if (fieldFromInstruction32(Insn, 4, 1) != 0)
				3309	align = 8;
				3310	if (fieldFromInstruction32(Insn, 6, 1))
				3311	inc = 2;
				3312	break;
				3313	}
				3314
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3315	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3316	return MCDisassembler::Fail;
				3317	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3318	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3319	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3320	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3321	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3322	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3323	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3324	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3325	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3326	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3327	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3328	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3329	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3330	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3331	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3332	}
				3333
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3334	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3335	return MCDisassembler::Fail;
				3336	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3337	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3338	Inst.addOperand(MCOperand::CreateImm(index));
				3339
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3340	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3341	}
				3342
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3343	static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3344	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3345	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3346
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3347	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3348	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3349	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3350	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3351	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3352
				3353	unsigned align = 0;
				3354	unsigned index = 0;
				3355	unsigned inc = 1;
				3356	switch (size) {
				3357	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3358	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3359	case 0:
				3360	index = fieldFromInstruction32(Insn, 5, 3);
				3361	if (fieldFromInstruction32(Insn, 4, 1))
				3362	align = 2;
				3363	break;
				3364	case 1:
				3365	index = fieldFromInstruction32(Insn, 6, 2);
				3366	if (fieldFromInstruction32(Insn, 4, 1))
				3367	align = 4;
				3368	if (fieldFromInstruction32(Insn, 5, 1))
				3369	inc = 2;
				3370	break;
				3371	case 2:
				3372	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3373	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3374	index = fieldFromInstruction32(Insn, 7, 1);
				3375	if (fieldFromInstruction32(Insn, 4, 1) != 0)
				3376	align = 8;
				3377	if (fieldFromInstruction32(Insn, 6, 1))
				3378	inc = 2;
				3379	break;
				3380	}
				3381
				3382	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3383	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3384	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3385	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3386	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3387	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3388	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3389	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3390	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3391	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3392	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3393	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3394	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3395	}
				3396
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3397	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3398	return MCDisassembler::Fail;
				3399	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3400	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3401	Inst.addOperand(MCOperand::CreateImm(index));
				3402
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3403	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3404	}
				3405
				3406
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3407	static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3408	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3409	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3410
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3411	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3412	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3413	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3414	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3415	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3416
				3417	unsigned align = 0;
				3418	unsigned index = 0;
				3419	unsigned inc = 1;
				3420	switch (size) {
				3421	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3422	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3423	case 0:
				3424	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3425	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3426	index = fieldFromInstruction32(Insn, 5, 3);
				3427	break;
				3428	case 1:
				3429	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3430	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3431	index = fieldFromInstruction32(Insn, 6, 2);
				3432	if (fieldFromInstruction32(Insn, 5, 1))
				3433	inc = 2;
				3434	break;
				3435	case 2:
				3436	if (fieldFromInstruction32(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3437	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3438	index = fieldFromInstruction32(Insn, 7, 1);
				3439	if (fieldFromInstruction32(Insn, 6, 1))
				3440	inc = 2;
				3441	break;
				3442	}
				3443
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3444	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3445	return MCDisassembler::Fail;
				3446	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3447	return MCDisassembler::Fail;
				3448	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3449	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3450
				3451	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3452	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3453	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3454	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3455	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3456	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3457	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3458	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3459	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3460	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3461	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3462	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3463	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3464	}
				3465
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3466	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3467	return MCDisassembler::Fail;
				3468	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3469	return MCDisassembler::Fail;
				3470	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3471	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3472	Inst.addOperand(MCOperand::CreateImm(index));
				3473
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3474	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3475	}
				3476
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3477	static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3478	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3479	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3480
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3481	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3482	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3483	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3484	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3485	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3486
				3487	unsigned align = 0;
				3488	unsigned index = 0;
				3489	unsigned inc = 1;
				3490	switch (size) {
				3491	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3492	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3493	case 0:
				3494	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3495	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3496	index = fieldFromInstruction32(Insn, 5, 3);
				3497	break;
				3498	case 1:
				3499	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3500	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3501	index = fieldFromInstruction32(Insn, 6, 2);
				3502	if (fieldFromInstruction32(Insn, 5, 1))
				3503	inc = 2;
				3504	break;
				3505	case 2:
				3506	if (fieldFromInstruction32(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3507	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3508	index = fieldFromInstruction32(Insn, 7, 1);
				3509	if (fieldFromInstruction32(Insn, 6, 1))
				3510	inc = 2;
				3511	break;
				3512	}
				3513
				3514	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3515	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3516	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3517	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3518	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3519	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3520	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3521	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3522	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3523	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3524	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3525	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3526	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3527	}
				3528
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3529	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3530	return MCDisassembler::Fail;
				3531	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3532	return MCDisassembler::Fail;
				3533	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3534	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3535	Inst.addOperand(MCOperand::CreateImm(index));
				3536
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3537	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3538	}
				3539
				3540
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3541	static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3542	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3543	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3544
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3545	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3546	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3547	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3548	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3549	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3550
				3551	unsigned align = 0;
				3552	unsigned index = 0;
				3553	unsigned inc = 1;
				3554	switch (size) {
				3555	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3556	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3557	case 0:
				3558	if (fieldFromInstruction32(Insn, 4, 1))
				3559	align = 4;
				3560	index = fieldFromInstruction32(Insn, 5, 3);
				3561	break;
				3562	case 1:
				3563	if (fieldFromInstruction32(Insn, 4, 1))
				3564	align = 8;
				3565	index = fieldFromInstruction32(Insn, 6, 2);
				3566	if (fieldFromInstruction32(Insn, 5, 1))
				3567	inc = 2;
				3568	break;
				3569	case 2:
				3570	if (fieldFromInstruction32(Insn, 4, 2))
				3571	align = 4 << fieldFromInstruction32(Insn, 4, 2);
				3572	index = fieldFromInstruction32(Insn, 7, 1);
				3573	if (fieldFromInstruction32(Insn, 6, 1))
				3574	inc = 2;
				3575	break;
				3576	}
				3577
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3578	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3579	return MCDisassembler::Fail;
				3580	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3581	return MCDisassembler::Fail;
				3582	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3583	return MCDisassembler::Fail;
				3584	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3585	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3586
				3587	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3588	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3589	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3590	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3591	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3592	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3593	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3594	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3595	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3596	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3597	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3598	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3599	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3600	}
				3601
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3602	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3603	return MCDisassembler::Fail;
				3604	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3605	return MCDisassembler::Fail;
				3606	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3607	return MCDisassembler::Fail;
				3608	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3609	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3610	Inst.addOperand(MCOperand::CreateImm(index));
				3611
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3612	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3613	}
				3614
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3615	static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3616	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3617	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3618
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3619	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3620	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3621	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3622	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3623	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3624
				3625	unsigned align = 0;
				3626	unsigned index = 0;
				3627	unsigned inc = 1;
				3628	switch (size) {
				3629	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3630	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3631	case 0:
				3632	if (fieldFromInstruction32(Insn, 4, 1))
				3633	align = 4;
				3634	index = fieldFromInstruction32(Insn, 5, 3);
				3635	break;
				3636	case 1:
				3637	if (fieldFromInstruction32(Insn, 4, 1))
				3638	align = 8;
				3639	index = fieldFromInstruction32(Insn, 6, 2);
				3640	if (fieldFromInstruction32(Insn, 5, 1))
				3641	inc = 2;
				3642	break;
				3643	case 2:
				3644	if (fieldFromInstruction32(Insn, 4, 2))
				3645	align = 4 << fieldFromInstruction32(Insn, 4, 2);
				3646	index = fieldFromInstruction32(Insn, 7, 1);
				3647	if (fieldFromInstruction32(Insn, 6, 1))
				3648	inc = 2;
				3649	break;
				3650	}
				3651
				3652	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3653	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3654	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3655	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3656	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3657	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3658	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3659	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3660	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3661	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3662	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3663	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3664	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3665	}
				3666
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3667	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3668	return MCDisassembler::Fail;
				3669	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3670	return MCDisassembler::Fail;
				3671	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3672	return MCDisassembler::Fail;
				3673	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3674	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3675	Inst.addOperand(MCOperand::CreateImm(index));
				3676
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3677	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3678	}
				3679
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3680	static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3681	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3682	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3683	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3684	unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
				3685	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3686	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3687	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				3688
				3689	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3690	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3691
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3692	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				3693	return MCDisassembler::Fail;
				3694	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				3695	return MCDisassembler::Fail;
				3696	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				3697	return MCDisassembler::Fail;
				3698	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				3699	return MCDisassembler::Fail;
				3700	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3701	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3702
				3703	return S;
				3704	}
				3705
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3706	static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3707	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3708	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3709	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3710	unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
				3711	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3712	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3713	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				3714
				3715	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3716	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3717
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3718	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				3719	return MCDisassembler::Fail;
				3720	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				3721	return MCDisassembler::Fail;
				3722	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				3723	return MCDisassembler::Fail;
				3724	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				3725	return MCDisassembler::Fail;
				3726	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3727	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3728
				3729	return S;
				3730	}
Owen Anderson	8e1e60b	2011-08-22 23:44:04 +0000	[diff] [blame]	3731
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3732	static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3733	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3734	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3735	unsigned pred = fieldFromInstruction16(Insn, 4, 4);
				3736	// The InstPrinter needs to have the low bit of the predicate in
				3737	// the mask operand to be able to print it properly.
				3738	unsigned mask = fieldFromInstruction16(Insn, 0, 5);
				3739
				3740	if (pred == 0xF) {
				3741	pred = 0xE;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3742	S = MCDisassembler::SoftFail;
Owen Anderson	e234d02	2011-08-24 17:21:43 +0000	[diff] [blame]	3743	}
				3744
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3745	if ((mask & 0xF) == 0) {
				3746	// Preserve the high bit of the mask, which is the low bit of
				3747	// the predicate.
				3748	mask &= 0x10;
				3749	mask \|= 0x8;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3750	S = MCDisassembler::SoftFail;
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	3751	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3752
				3753	Inst.addOperand(MCOperand::CreateImm(pred));
				3754	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	3755	return S;
				3756	}
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	3757
				3758	static DecodeStatus
				3759	DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
				3760	uint64_t Address, const void *Decoder) {
				3761	DecodeStatus S = MCDisassembler::Success;
				3762
				3763	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3764	unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
				3765	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3766	unsigned addr = fieldFromInstruction32(Insn, 0, 8);
				3767	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				3768	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				3769	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				3770	bool writeback = (W == 1) \| (P == 0);
				3771
				3772	addr \|= (U << 8) \| (Rn << 9);
				3773
				3774	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				3775	Check(S, MCDisassembler::SoftFail);
				3776	if (Rt == Rt2)
				3777	Check(S, MCDisassembler::SoftFail);
				3778
				3779	// Rt
				3780	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3781	return MCDisassembler::Fail;
				3782	// Rt2
				3783	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				3784	return MCDisassembler::Fail;
				3785	// Writeback operand
				3786	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3787	return MCDisassembler::Fail;
				3788	// addr
				3789	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				3790	return MCDisassembler::Fail;
				3791
				3792	return S;
				3793	}
				3794
				3795	static DecodeStatus
				3796	DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
				3797	uint64_t Address, const void *Decoder) {
				3798	DecodeStatus S = MCDisassembler::Success;
				3799
				3800	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3801	unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
				3802	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3803	unsigned addr = fieldFromInstruction32(Insn, 0, 8);
				3804	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				3805	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				3806	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				3807	bool writeback = (W == 1) \| (P == 0);
				3808
				3809	addr \|= (U << 8) \| (Rn << 9);
				3810
				3811	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				3812	Check(S, MCDisassembler::SoftFail);
				3813
				3814	// Writeback operand
				3815	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3816	return MCDisassembler::Fail;
				3817	// Rt
				3818	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3819	return MCDisassembler::Fail;
				3820	// Rt2
				3821	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				3822	return MCDisassembler::Fail;
				3823	// addr
				3824	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				3825	return MCDisassembler::Fail;
				3826
				3827	return S;
				3828	}
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	3829
				3830	static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
				3831	uint64_t Address, const void *Decoder) {
				3832	unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
				3833	unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
				3834	if (sign1 != sign2) return MCDisassembler::Fail;
				3835
				3836	unsigned Val = fieldFromInstruction32(Insn, 0, 8);
				3837	Val \|= fieldFromInstruction32(Insn, 12, 3) << 8;
				3838	Val \|= fieldFromInstruction32(Insn, 26, 1) << 11;
				3839	Val \|= sign1 << 12;
				3840	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				3841
				3842	return MCDisassembler::Success;
				3843	}
				3844