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gerrit-public.fairphone.software / platform / external / llvm / 753e02ad5d7042bc6bf175c676327ae9486a8341 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: d33cb9491682a095a8cd449c5f7fe83f442206ef [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]16#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]17#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]18#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]22#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]39 ARMDisassembler(const MCSubtargetInfo &STI) :
40 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]41 }
42
43 ~ARMDisassembler() {
44 }
45
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
48 uint64_t &size,
49 const MemoryObject &region,
50 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]51 raw_ostream &vStream,
52 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]53
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62 /// Constructor - Initializes the disassembler.
63 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]64 ThumbDisassembler(const MCSubtargetInfo &STI) :
65 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]66 }
67
68 ~ThumbDisassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
74 const MemoryObject &region,
75 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]78
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
81private:
82 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]83 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]84 void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]88static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]89 switch (In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
92 return true;
93 case MCDisassembler::SoftFail:
94 Out = In;
95 return true;
96 case MCDisassembler::Fail:
97 Out = In;
98 return false;
99 }
100 return false;
101}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]102
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]103
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]120 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]122 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]129
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]148 unsigned Insn,
149 uint64_t Address,
150 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]154 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 unsigned Insn,
162 uint64_t Adddress,
163 const void *Decoder);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]182static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]184static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]186static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]188static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]190static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]192static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]194static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]196static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]198static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]200static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]202static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]204static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]210static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]212static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]214static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]216static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]218static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]224static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]226static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]228static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]230static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]232static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]234static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]236static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]238static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]240static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]242static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]244static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]246static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]252
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]253static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]255static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]257static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]259static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]261static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]277static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
278 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]279static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]287static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]293static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
294 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]295static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]296 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]297static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]299static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]301static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]303static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]304 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]305static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
306 uint64_t Address, const void *Decoder);
307static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]309static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
310 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]311static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]313static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
315
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]316
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]317
318#include "ARMGenDisassemblerTables.inc"
319#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]320#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]321
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]322static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
323 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]324}
325
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]326static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
327 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]328}
329
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]330EDInstInfo *ARMDisassembler::getEDInfo() const {
331 return instInfoARM;
332}
333
334EDInstInfo *ThumbDisassembler::getEDInfo() const {
335 return instInfoARM;
336}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]338DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]339 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]340 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]341 raw_ostream &os,
342 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]343 CommentStream = &cs;
344
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 uint8_t bytes[4];
346
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
348 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
349
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]350 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]351 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
352 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]353 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]354 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355
356 // Encoded as a small-endian 32-bit word in the stream.
357 uint32_t insn = (bytes[3] << 24) |
358 (bytes[2] << 16) |
359 (bytes[1] << 8) |
360 (bytes[0] << 0);
361
362 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]364 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]366 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 }
368
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 // VFP and NEON instructions, similarly, are shared between ARM
370 // and Thumb modes.
371 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]372 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]375 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 }
377
378 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]379 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]380 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]381 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382 // Add a fake predicate operand, because we share these instruction
383 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]384 if (!DecodePredicateOperand(MI, 0xE, Address, this))
385 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]386 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]387 }
388
389 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]390 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]391 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]392 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]393 // Add a fake predicate operand, because we share these instruction
394 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]395 if (!DecodePredicateOperand(MI, 0xE, Address, this))
396 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]397 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]398 }
399
400 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]401 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]402 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]403 Size = 4;
404 // Add a fake predicate operand, because we share these instruction
405 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]406 if (!DecodePredicateOperand(MI, 0xE, Address, this))
407 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]408 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]409 }
410
411 MI.clear();
412
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]413 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]414 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415}
416
417namespace llvm {
418extern MCInstrDesc ARMInsts[];
419}
420
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]421/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
422/// immediate Value in the MCInst. The immediate Value has had any PC
423/// adjustment made by the caller. If the instruction is a branch instruction
424/// then isBranch is true, else false. If the getOpInfo() function was set as
425/// part of the setupForSymbolicDisassembly() call then that function is called
426/// to get any symbolic information at the Address for this instruction. If
427/// that returns non-zero then the symbolic information it returns is used to
428/// create an MCExpr and that is added as an operand to the MCInst. If
429/// getOpInfo() returns zero and isBranch is true then a symbol look up for
430/// Value is done and if a symbol is found an MCExpr is created with that, else
431/// an MCExpr with Value is created. This function returns true if it adds an
432/// operand to the MCInst and false otherwise.
433static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
434 bool isBranch, uint64_t InstSize,
435 MCInst &MI, const void *Decoder) {
436 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
437 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
438 if (!getOpInfo)
439 return false;
440
441 struct LLVMOpInfo1 SymbolicOp;
442 SymbolicOp.Value = Value;
443 void *DisInfo = Dis->getDisInfoBlock();
444 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
445 if (isBranch) {
446 LLVMSymbolLookupCallback SymbolLookUp =
447 Dis->getLLVMSymbolLookupCallback();
448 if (SymbolLookUp) {
449 uint64_t ReferenceType;
450 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
451 const char *ReferenceName;
452 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
453 &ReferenceName);
454 if (Name) {
455 SymbolicOp.AddSymbol.Name = Name;
456 SymbolicOp.AddSymbol.Present = true;
457 SymbolicOp.Value = 0;
458 }
459 else {
460 SymbolicOp.Value = Value;
461 }
462 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
463 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
464 }
465 else {
466 return false;
467 }
468 }
469 else {
470 return false;
471 }
472 }
473
474 MCContext *Ctx = Dis->getMCContext();
475 const MCExpr *Add = NULL;
476 if (SymbolicOp.AddSymbol.Present) {
477 if (SymbolicOp.AddSymbol.Name) {
478 StringRef Name(SymbolicOp.AddSymbol.Name);
479 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
480 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
481 } else {
482 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
483 }
484 }
485
486 const MCExpr *Sub = NULL;
487 if (SymbolicOp.SubtractSymbol.Present) {
488 if (SymbolicOp.SubtractSymbol.Name) {
489 StringRef Name(SymbolicOp.SubtractSymbol.Name);
490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
491 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
492 } else {
493 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
494 }
495 }
496
497 const MCExpr *Off = NULL;
498 if (SymbolicOp.Value != 0)
499 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
500
501 const MCExpr *Expr;
502 if (Sub) {
503 const MCExpr *LHS;
504 if (Add)
505 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
506 else
507 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
508 if (Off != 0)
509 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
510 else
511 Expr = LHS;
512 } else if (Add) {
513 if (Off != 0)
514 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
515 else
516 Expr = Add;
517 } else {
518 if (Off != 0)
519 Expr = Off;
520 else
521 Expr = MCConstantExpr::Create(0, *Ctx);
522 }
523
524 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
526 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
529 MI.addOperand(MCOperand::CreateExpr(Expr));
530 else
531 assert("bad SymbolicOp.VariantKind");
532
533 return true;
534}
535
536/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
537/// referenced by a load instruction with the base register that is the Pc.
538/// These can often be values in a literal pool near the Address of the
539/// instruction. The Address of the instruction and its immediate Value are
540/// used as a possible literal pool entry. The SymbolLookUp call back will
541/// return the name of a symbol referenced by the the literal pool's entry if
542/// the referenced address is that of a symbol. Or it will return a pointer to
543/// a literal 'C' string if the referenced address of the literal pool's entry
544/// is an address into a section with 'C' string literals.
545static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
546 const void *Decoder) {
547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
548 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
549 if (SymbolLookUp) {
550 void *DisInfo = Dis->getDisInfoBlock();
551 uint64_t ReferenceType;
552 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
553 const char *ReferenceName;
554 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
555 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
556 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
557 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
558 }
559}
560
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]561// Thumb1 instructions don't have explicit S bits. Rather, they
562// implicitly set CPSR. Since it's not represented in the encoding, the
563// auto-generated decoder won't inject the CPSR operand. We need to fix
564// that as a post-pass.
565static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]568 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]569 for (unsigned i = 0; i < NumOps; ++i, ++I) {
570 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]572 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
574 return;
575 }
576 }
577
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579}
580
581// Most Thumb instructions don't have explicit predicates in the
582// encoding, but rather get their predicates from IT context. We need
583// to fix up the predicate operands using this context information as a
584// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]585MCDisassembler::DecodeStatus
586ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]587 MCDisassembler::DecodeStatus S = Success;
588
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]589 // A few instructions actually have predicates encoded in them. Don't
590 // try to overwrite it if we're seeing one of those.
591 switch (MI.getOpcode()) {
592 case ARM::tBcc:
593 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]594 case ARM::tCBZ:
595 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]596 case ARM::tCPS:
597 case ARM::t2CPS3p:
598 case ARM::t2CPS2p:
599 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]600 case ARM::tMOVSr:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]601 // Some instructions (mostly conditional branches) are not
602 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]603 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]604 S = SoftFail;
605 else
606 return Success;
607 break;
608 case ARM::tB:
609 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]610 case ARM::t2TBB:
611 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]612 // Some instructions (mostly unconditional branches) can
613 // only appears at the end of, or outside of, an IT.
614 if (ITBlock.size() > 1)
615 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]616 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]617 default:
618 break;
619 }
620
621 // If we're in an IT block, base the predicate on that. Otherwise,
622 // assume a predicate of AL.
623 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]624 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]625 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]626 if (CC == 0xF)
627 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]628 ITBlock.pop_back();
629 } else
630 CC = ARMCC::AL;
631
632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]634 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]635 for (unsigned i = 0; i < NumOps; ++i, ++I) {
636 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 if (OpInfo[i].isPredicate()) {
638 I = MI.insert(I, MCOperand::CreateImm(CC));
639 ++I;
640 if (CC == ARMCC::AL)
641 MI.insert(I, MCOperand::CreateReg(0));
642 else
643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]644 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]645 }
646 }
647
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]648 I = MI.insert(I, MCOperand::CreateImm(CC));
649 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]650 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]651 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]652 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]654
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]655 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]656}
657
658// Thumb VFP instructions are a special case. Because we share their
659// encodings between ARM and Thumb modes, and they are predicable in ARM
660// mode, the auto-generated decoder will give them an (incorrect)
661// predicate operand. We need to rewrite these operands based on the IT
662// context as a post-pass.
663void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
664 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]665 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]666 CC = ITBlock.back();
667 ITBlock.pop_back();
668 } else
669 CC = ARMCC::AL;
670
671 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
672 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]673 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
674 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]675 if (OpInfo[i].isPredicate() ) {
676 I->setImm(CC);
677 ++I;
678 if (CC == ARMCC::AL)
679 I->setReg(0);
680 else
681 I->setReg(ARM::CPSR);
682 return;
683 }
684 }
685}
686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]687DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]688 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]689 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]690 raw_ostream &os,
691 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]692 CommentStream = &cs;
693
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]694 uint8_t bytes[4];
695
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]696 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
697 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
698
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]699 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]700 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
701 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]702 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]703 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704
705 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]706 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]707 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]708 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]709 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]710 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]711 }
712
713 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]714 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]715 if (result) {
716 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]717 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]718 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]719 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]720 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]721 }
722
723 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]724 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]725 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]726 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]727
728 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
729 // the Thumb predicate.
730 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
731 result = MCDisassembler::SoftFail;
732
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]733 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]734
735 // If we find an IT instruction, we need to parse its condition
736 // code and mask operands so that we can apply them correctly
737 // to the subsequent instructions.
738 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]739
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]740 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]741 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]742 unsigned Mask = MI.getOperand(1).getImm();
743 unsigned CondBit0 = Mask >> 4 & 1;
744 unsigned NumTZ = CountTrailingZeros_32(Mask);
745 assert(NumTZ <= 3 && "Invalid IT mask!");
746 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
747 bool T = ((Mask >> Pos) & 1) == CondBit0;
748 if (T)
749 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]750 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]751 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]752 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]753
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]754 ITBlock.push_back(firstcond);
755 }
756
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]757 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]758 }
759
760 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]761 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
762 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]763 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]764 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]765
766 uint32_t insn32 = (bytes[3] << 8) |
767 (bytes[2] << 0) |
768 (bytes[1] << 24) |
769 (bytes[0] << 16);
770 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]771 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]772 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]773 Size = 4;
774 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]775 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]776 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]777 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]778 }
779
780 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]781 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]782 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]784 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]785 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 }
787
788 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]789 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]790 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 Size = 4;
792 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]793 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 }
795
796 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]797 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]798 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]799 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]800 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]801 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]802 }
803
804 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
805 MI.clear();
806 uint32_t NEONLdStInsn = insn32;
807 NEONLdStInsn &= 0xF0FFFFFF;
808 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]809 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]810 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]811 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]812 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]813 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]814 }
815 }
816
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]817 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]818 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]819 uint32_t NEONDataInsn = insn32;
820 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
821 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
822 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]823 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]824 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]825 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]826 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]827 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]828 }
829 }
830
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]831 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]832 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833}
834
835
836extern "C" void LLVMInitializeARMDisassembler() {
837 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
838 createARMDisassembler);
839 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
840 createThumbDisassembler);
841}
842
843static const unsigned GPRDecoderTable[] = {
844 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
845 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
846 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
847 ARM::R12, ARM::SP, ARM::LR, ARM::PC
848};
849
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]850static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]851 uint64_t Address, const void *Decoder) {
852 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]853 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854
855 unsigned Register = GPRDecoderTable[RegNo];
856 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]857 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]858}
859
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]860static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]861DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
862 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]863 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]864 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
865}
866
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]867static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]868 uint64_t Address, const void *Decoder) {
869 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]870 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]871 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
872}
873
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]874static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]875 uint64_t Address, const void *Decoder) {
876 unsigned Register = 0;
877 switch (RegNo) {
878 case 0:
879 Register = ARM::R0;
880 break;
881 case 1:
882 Register = ARM::R1;
883 break;
884 case 2:
885 Register = ARM::R2;
886 break;
887 case 3:
888 Register = ARM::R3;
889 break;
890 case 9:
891 Register = ARM::R9;
892 break;
893 case 12:
894 Register = ARM::R12;
895 break;
896 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]897 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]898 }
899
900 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]901 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]902}
903
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]904static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]905 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]906 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]907 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
908}
909
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]910static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]911 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
912 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
913 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
914 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
915 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
916 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
917 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
918 ARM::S28, ARM::S29, ARM::S30, ARM::S31
919};
920
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]921static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]922 uint64_t Address, const void *Decoder) {
923 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]924 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925
926 unsigned Register = SPRDecoderTable[RegNo];
927 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]928 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929}
930
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]931static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]932 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
933 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
934 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
935 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
936 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
937 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
938 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
939 ARM::D28, ARM::D29, ARM::D30, ARM::D31
940};
941
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]942static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]943 uint64_t Address, const void *Decoder) {
944 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]945 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946
947 unsigned Register = DPRDecoderTable[RegNo];
948 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]949 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]950}
951
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]952static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]953 uint64_t Address, const void *Decoder) {
954 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]955 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]956 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
957}
958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]959static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]960DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
961 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]962 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]963 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]964 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
965}
966
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]967static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
969 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
970 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
971 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
972};
973
974
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]975static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]976 uint64_t Address, const void *Decoder) {
977 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]978 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]979 RegNo >>= 1;
980
981 unsigned Register = QPRDecoderTable[RegNo];
982 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]983 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984}
985
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]986static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]987 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]988 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]989 // AL predicate is not allowed on Thumb1 branches.
990 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]991 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]992 Inst.addOperand(MCOperand::CreateImm(Val));
993 if (Val == ARMCC::AL) {
994 Inst.addOperand(MCOperand::CreateReg(0));
995 } else
996 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]997 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]998}
999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1000static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1001 uint64_t Address, const void *Decoder) {
1002 if (Val)
1003 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1004 else
1005 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1006 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1007}
1008
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1009static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1010 uint64_t Address, const void *Decoder) {
1011 uint32_t imm = Val & 0xFF;
1012 uint32_t rot = (Val & 0xF00) >> 7;
1013 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
1014 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1015 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1016}
1017
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1018static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1019 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1020 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1021
1022 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1023 unsigned type = fieldFromInstruction32(Val, 5, 2);
1024 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1025
1026 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1028 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1029
1030 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1031 switch (type) {
1032 case 0:
1033 Shift = ARM_AM::lsl;
1034 break;
1035 case 1:
1036 Shift = ARM_AM::lsr;
1037 break;
1038 case 2:
1039 Shift = ARM_AM::asr;
1040 break;
1041 case 3:
1042 Shift = ARM_AM::ror;
1043 break;
1044 }
1045
1046 if (Shift == ARM_AM::ror && imm == 0)
1047 Shift = ARM_AM::rrx;
1048
1049 unsigned Op = Shift | (imm << 3);
1050 Inst.addOperand(MCOperand::CreateImm(Op));
1051
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1052 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1053}
1054
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1055static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1056 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1057 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1058
1059 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1060 unsigned type = fieldFromInstruction32(Val, 5, 2);
1061 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1062
1063 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1065 return MCDisassembler::Fail;
1066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1067 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1068
1069 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1070 switch (type) {
1071 case 0:
1072 Shift = ARM_AM::lsl;
1073 break;
1074 case 1:
1075 Shift = ARM_AM::lsr;
1076 break;
1077 case 2:
1078 Shift = ARM_AM::asr;
1079 break;
1080 case 3:
1081 Shift = ARM_AM::ror;
1082 break;
1083 }
1084
1085 Inst.addOperand(MCOperand::CreateImm(Shift));
1086
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1087 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1088}
1089
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1090static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1091 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1092 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1093
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1094 bool writebackLoad = false;
1095 unsigned writebackReg = 0;
1096 switch (Inst.getOpcode()) {
1097 default:
1098 break;
1099 case ARM::LDMIA_UPD:
1100 case ARM::LDMDB_UPD:
1101 case ARM::LDMIB_UPD:
1102 case ARM::LDMDA_UPD:
1103 case ARM::t2LDMIA_UPD:
1104 case ARM::t2LDMDB_UPD:
1105 writebackLoad = true;
1106 writebackReg = Inst.getOperand(0).getReg();
1107 break;
1108 }
1109
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1110 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1111 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1113 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1114 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1115 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1116 // Writeback not allowed if Rn is in the target list.
1117 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1118 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1119 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1120 }
1121
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1122 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1123}
1124
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1125static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1126 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1127 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1128
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1129 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1130 unsigned regs = Val & 0xFF;
1131
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1132 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1133 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1134 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1135 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1136 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1137 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1138
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1139 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1140}
1141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1142static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1143 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1144 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1145
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1146 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1147 unsigned regs = (Val & 0xFF) / 2;
1148
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1149 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1150 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1151 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1152 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1153 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1154 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1155
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1156 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1157}
1158
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1159static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1160 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1161 // This operand encodes a mask of contiguous zeros between a specified MSB
1162 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1163 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1164 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1165 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1166 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1167 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1168
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1169 DecodeStatus S = MCDisassembler::Success;
1170 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1171
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1172 uint32_t msb_mask = 0xFFFFFFFF;
1173 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1174 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1175
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1176 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1177 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1178}
1179
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1180static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1181 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1182 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1183
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1184 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1185 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1186 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1187 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1188 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1189 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1190
1191 switch (Inst.getOpcode()) {
1192 case ARM::LDC_OFFSET:
1193 case ARM::LDC_PRE:
1194 case ARM::LDC_POST:
1195 case ARM::LDC_OPTION:
1196 case ARM::LDCL_OFFSET:
1197 case ARM::LDCL_PRE:
1198 case ARM::LDCL_POST:
1199 case ARM::LDCL_OPTION:
1200 case ARM::STC_OFFSET:
1201 case ARM::STC_PRE:
1202 case ARM::STC_POST:
1203 case ARM::STC_OPTION:
1204 case ARM::STCL_OFFSET:
1205 case ARM::STCL_PRE:
1206 case ARM::STCL_POST:
1207 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1208 case ARM::t2LDC_OFFSET:
1209 case ARM::t2LDC_PRE:
1210 case ARM::t2LDC_POST:
1211 case ARM::t2LDC_OPTION:
1212 case ARM::t2LDCL_OFFSET:
1213 case ARM::t2LDCL_PRE:
1214 case ARM::t2LDCL_POST:
1215 case ARM::t2LDCL_OPTION:
1216 case ARM::t2STC_OFFSET:
1217 case ARM::t2STC_PRE:
1218 case ARM::t2STC_POST:
1219 case ARM::t2STC_OPTION:
1220 case ARM::t2STCL_OFFSET:
1221 case ARM::t2STCL_PRE:
1222 case ARM::t2STCL_POST:
1223 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1225 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1226 break;
1227 default:
1228 break;
1229 }
1230
1231 Inst.addOperand(MCOperand::CreateImm(coproc));
1232 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1234 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235
1236 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1237 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1238
1239 bool writeback = (P == 0) || (W == 1);
1240 unsigned idx_mode = 0;
1241 if (P && writeback)
1242 idx_mode = ARMII::IndexModePre;
1243 else if (!P && writeback)
1244 idx_mode = ARMII::IndexModePost;
1245
1246 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1247 case ARM::t2LDC2_OFFSET:
1248 case ARM::t2LDC2L_OFFSET:
1249 case ARM::t2LDC2_PRE:
1250 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1251 case ARM::t2STC2_OFFSET:
1252 case ARM::t2STC2L_OFFSET:
1253 case ARM::t2STC2_PRE:
1254 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1255 case ARM::LDC2_OFFSET:
1256 case ARM::LDC2L_OFFSET:
1257 case ARM::LDC2_PRE:
1258 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1259 case ARM::STC2_OFFSET:
1260 case ARM::STC2L_OFFSET:
1261 case ARM::STC2_PRE:
1262 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1263 case ARM::t2LDC_OFFSET:
1264 case ARM::t2LDCL_OFFSET:
1265 case ARM::t2LDC_PRE:
1266 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1267 case ARM::t2STC_OFFSET:
1268 case ARM::t2STCL_OFFSET:
1269 case ARM::t2STC_PRE:
1270 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1271 case ARM::LDC_OFFSET:
1272 case ARM::LDCL_OFFSET:
1273 case ARM::LDC_PRE:
1274 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1275 case ARM::STC_OFFSET:
1276 case ARM::STCL_OFFSET:
1277 case ARM::STC_PRE:
1278 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1279 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1280 Inst.addOperand(MCOperand::CreateImm(imm));
1281 break;
1282 case ARM::t2LDC2_POST:
1283 case ARM::t2LDC2L_POST:
1284 case ARM::t2STC2_POST:
1285 case ARM::t2STC2L_POST:
1286 case ARM::LDC2_POST:
1287 case ARM::LDC2L_POST:
1288 case ARM::STC2_POST:
1289 case ARM::STC2L_POST:
1290 case ARM::t2LDC_POST:
1291 case ARM::t2LDCL_POST:
1292 case ARM::t2STC_POST:
1293 case ARM::t2STCL_POST:
1294 case ARM::LDC_POST:
1295 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1296 case ARM::STC_POST:
1297 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1298 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1299 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1300 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1301 // The 'option' variant doesn't encode 'U' in the immediate since
1302 // the immediate is unsigned [0,255].
1303 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1304 break;
1305 }
1306
1307 switch (Inst.getOpcode()) {
1308 case ARM::LDC_OFFSET:
1309 case ARM::LDC_PRE:
1310 case ARM::LDC_POST:
1311 case ARM::LDC_OPTION:
1312 case ARM::LDCL_OFFSET:
1313 case ARM::LDCL_PRE:
1314 case ARM::LDCL_POST:
1315 case ARM::LDCL_OPTION:
1316 case ARM::STC_OFFSET:
1317 case ARM::STC_PRE:
1318 case ARM::STC_POST:
1319 case ARM::STC_OPTION:
1320 case ARM::STCL_OFFSET:
1321 case ARM::STCL_PRE:
1322 case ARM::STCL_POST:
1323 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1324 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1325 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1326 break;
1327 default:
1328 break;
1329 }
1330
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1331 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1332}
1333
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1334static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1335DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1336 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1337 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1338
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1339 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1340 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1341 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1342 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1343 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1344 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1345 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1346 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1347
1348 // On stores, the writeback operand precedes Rt.
1349 switch (Inst.getOpcode()) {
1350 case ARM::STR_POST_IMM:
1351 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1352 case ARM::STRB_POST_IMM:
1353 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1354 case ARM::STRT_POST_REG:
1355 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1356 case ARM::STRBT_POST_REG:
1357 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1359 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1360 break;
1361 default:
1362 break;
1363 }
1364
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1366 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1367
1368 // On loads, the writeback operand comes after Rt.
1369 switch (Inst.getOpcode()) {
1370 case ARM::LDR_POST_IMM:
1371 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1372 case ARM::LDRB_POST_IMM:
1373 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1374 case ARM::LDRBT_POST_REG:
1375 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1376 case ARM::LDRT_POST_REG:
1377 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1379 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1380 break;
1381 default:
1382 break;
1383 }
1384
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1386 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1387
1388 ARM_AM::AddrOpc Op = ARM_AM::add;
1389 if (!fieldFromInstruction32(Insn, 23, 1))
1390 Op = ARM_AM::sub;
1391
1392 bool writeback = (P == 0) || (W == 1);
1393 unsigned idx_mode = 0;
1394 if (P && writeback)
1395 idx_mode = ARMII::IndexModePre;
1396 else if (!P && writeback)
1397 idx_mode = ARMII::IndexModePost;
1398
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1399 if (writeback && (Rn == 15 || Rn == Rt))
1400 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1401
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1402 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1403 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1404 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1405 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1406 switch( fieldFromInstruction32(Insn, 5, 2)) {
1407 case 0:
1408 Opc = ARM_AM::lsl;
1409 break;
1410 case 1:
1411 Opc = ARM_AM::lsr;
1412 break;
1413 case 2:
1414 Opc = ARM_AM::asr;
1415 break;
1416 case 3:
1417 Opc = ARM_AM::ror;
1418 break;
1419 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1420 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1421 }
1422 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1423 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1424
1425 Inst.addOperand(MCOperand::CreateImm(imm));
1426 } else {
1427 Inst.addOperand(MCOperand::CreateReg(0));
1428 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1429 Inst.addOperand(MCOperand::CreateImm(tmp));
1430 }
1431
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1432 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1433 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1434
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1435 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1436}
1437
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1438static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1439 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1440 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1441
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1442 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1443 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1444 unsigned type = fieldFromInstruction32(Val, 5, 2);
1445 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1446 unsigned U = fieldFromInstruction32(Val, 12, 1);
1447
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1448 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1449 switch (type) {
1450 case 0:
1451 ShOp = ARM_AM::lsl;
1452 break;
1453 case 1:
1454 ShOp = ARM_AM::lsr;
1455 break;
1456 case 2:
1457 ShOp = ARM_AM::asr;
1458 break;
1459 case 3:
1460 ShOp = ARM_AM::ror;
1461 break;
1462 }
1463
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1465 return MCDisassembler::Fail;
1466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1467 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1468 unsigned shift;
1469 if (U)
1470 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1471 else
1472 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1473 Inst.addOperand(MCOperand::CreateImm(shift));
1474
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1475 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1476}
1477
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1478static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1479DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1480 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1481 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1482
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1483 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1484 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1485 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1486 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1487 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1488 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1489 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1490 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1491 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1492
1493 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1494
1495 // For {LD,ST}RD, Rt must be even, else undefined.
1496 switch (Inst.getOpcode()) {
1497 case ARM::STRD:
1498 case ARM::STRD_PRE:
1499 case ARM::STRD_POST:
1500 case ARM::LDRD:
1501 case ARM::LDRD_PRE:
1502 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1503 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1504 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1505 default:
1506 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1507 }
1508
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1509 if (writeback) { // Writeback
1510 if (P)
1511 U |= ARMII::IndexModePre << 9;
1512 else
1513 U |= ARMII::IndexModePost << 9;
1514
1515 // On stores, the writeback operand precedes Rt.
1516 switch (Inst.getOpcode()) {
1517 case ARM::STRD:
1518 case ARM::STRD_PRE:
1519 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1520 case ARM::STRH:
1521 case ARM::STRH_PRE:
1522 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1524 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1525 break;
1526 default:
1527 break;
1528 }
1529 }
1530
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1532 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1533 switch (Inst.getOpcode()) {
1534 case ARM::STRD:
1535 case ARM::STRD_PRE:
1536 case ARM::STRD_POST:
1537 case ARM::LDRD:
1538 case ARM::LDRD_PRE:
1539 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1541 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1542 break;
1543 default:
1544 break;
1545 }
1546
1547 if (writeback) {
1548 // On loads, the writeback operand comes after Rt.
1549 switch (Inst.getOpcode()) {
1550 case ARM::LDRD:
1551 case ARM::LDRD_PRE:
1552 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1553 case ARM::LDRH:
1554 case ARM::LDRH_PRE:
1555 case ARM::LDRH_POST:
1556 case ARM::LDRSH:
1557 case ARM::LDRSH_PRE:
1558 case ARM::LDRSH_POST:
1559 case ARM::LDRSB:
1560 case ARM::LDRSB_PRE:
1561 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1562 case ARM::LDRHTr:
1563 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1565 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1566 break;
1567 default:
1568 break;
1569 }
1570 }
1571
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1573 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1574
1575 if (type) {
1576 Inst.addOperand(MCOperand::CreateReg(0));
1577 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1578 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1580 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1581 Inst.addOperand(MCOperand::CreateImm(U));
1582 }
1583
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1584 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1585 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1586
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1587 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1588}
1589
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1590static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1591 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1592 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1593
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1594 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1595 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1596
1597 switch (mode) {
1598 case 0:
1599 mode = ARM_AM::da;
1600 break;
1601 case 1:
1602 mode = ARM_AM::ia;
1603 break;
1604 case 2:
1605 mode = ARM_AM::db;
1606 break;
1607 case 3:
1608 mode = ARM_AM::ib;
1609 break;
1610 }
1611
1612 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1614 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1615
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1616 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1617}
1618
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1619static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1620 unsigned Insn,
1621 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1622 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1623
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1624 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1625 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1626 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1627
1628 if (pred == 0xF) {
1629 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1630 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1631 Inst.setOpcode(ARM::RFEDA);
1632 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1633 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1634 Inst.setOpcode(ARM::RFEDA_UPD);
1635 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1636 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 Inst.setOpcode(ARM::RFEDB);
1638 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1639 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1640 Inst.setOpcode(ARM::RFEDB_UPD);
1641 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1642 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1643 Inst.setOpcode(ARM::RFEIA);
1644 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1645 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1646 Inst.setOpcode(ARM::RFEIA_UPD);
1647 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1648 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1649 Inst.setOpcode(ARM::RFEIB);
1650 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1651 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1652 Inst.setOpcode(ARM::RFEIB_UPD);
1653 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1654 case ARM::STMDA:
1655 Inst.setOpcode(ARM::SRSDA);
1656 break;
1657 case ARM::STMDA_UPD:
1658 Inst.setOpcode(ARM::SRSDA_UPD);
1659 break;
1660 case ARM::STMDB:
1661 Inst.setOpcode(ARM::SRSDB);
1662 break;
1663 case ARM::STMDB_UPD:
1664 Inst.setOpcode(ARM::SRSDB_UPD);
1665 break;
1666 case ARM::STMIA:
1667 Inst.setOpcode(ARM::SRSIA);
1668 break;
1669 case ARM::STMIA_UPD:
1670 Inst.setOpcode(ARM::SRSIA_UPD);
1671 break;
1672 case ARM::STMIB:
1673 Inst.setOpcode(ARM::SRSIB);
1674 break;
1675 case ARM::STMIB_UPD:
1676 Inst.setOpcode(ARM::SRSIB_UPD);
1677 break;
1678 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1679 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1680 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1681
1682 // For stores (which become SRS's, the only operand is the mode.
1683 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1684 Inst.addOperand(
1685 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1686 return S;
1687 }
1688
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1689 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1690 }
1691
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1693 return MCDisassembler::Fail;
1694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1695 return MCDisassembler::Fail; // Tied
1696 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1697 return MCDisassembler::Fail;
1698 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1699 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1700
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1701 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1702}
1703
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1704static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1705 uint64_t Address, const void *Decoder) {
1706 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1707 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1708 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1709 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1710
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1711 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1712
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1713 // imod == '01' --> UNPREDICTABLE
1714 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1715 // return failure here. The '01' imod value is unprintable, so there's
1716 // nothing useful we could do even if we returned UNPREDICTABLE.
1717
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1718 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1719
1720 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1721 Inst.setOpcode(ARM::CPS3p);
1722 Inst.addOperand(MCOperand::CreateImm(imod));
1723 Inst.addOperand(MCOperand::CreateImm(iflags));
1724 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1725 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1726 Inst.setOpcode(ARM::CPS2p);
1727 Inst.addOperand(MCOperand::CreateImm(imod));
1728 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1729 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1730 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1731 Inst.setOpcode(ARM::CPS1p);
1732 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1733 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1734 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1735 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1736 Inst.setOpcode(ARM::CPS1p);
1737 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1738 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1739 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1740
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1741 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1742}
1743
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1744static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1745 uint64_t Address, const void *Decoder) {
1746 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1747 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1748 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1749 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1750
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1751 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1752
1753 // imod == '01' --> UNPREDICTABLE
1754 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1755 // return failure here. The '01' imod value is unprintable, so there's
1756 // nothing useful we could do even if we returned UNPREDICTABLE.
1757
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1758 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1759
1760 if (imod && M) {
1761 Inst.setOpcode(ARM::t2CPS3p);
1762 Inst.addOperand(MCOperand::CreateImm(imod));
1763 Inst.addOperand(MCOperand::CreateImm(iflags));
1764 Inst.addOperand(MCOperand::CreateImm(mode));
1765 } else if (imod && !M) {
1766 Inst.setOpcode(ARM::t2CPS2p);
1767 Inst.addOperand(MCOperand::CreateImm(imod));
1768 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1769 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1770 } else if (!imod && M) {
1771 Inst.setOpcode(ARM::t2CPS1p);
1772 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1773 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1774 } else {
1775 // imod == '00' && M == '0' --> UNPREDICTABLE
1776 Inst.setOpcode(ARM::t2CPS1p);
1777 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1778 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1779 }
1780
1781 return S;
1782}
1783
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1784static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1785 uint64_t Address, const void *Decoder) {
1786 DecodeStatus S = MCDisassembler::Success;
1787
1788 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1789 unsigned imm = 0;
1790
1791 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1792 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1793 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1794 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1795
1796 if (Inst.getOpcode() == ARM::t2MOVTi16)
1797 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1798 return MCDisassembler::Fail;
1799 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1800 return MCDisassembler::Fail;
1801
1802 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1803 Inst.addOperand(MCOperand::CreateImm(imm));
1804
1805 return S;
1806}
1807
1808static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1809 uint64_t Address, const void *Decoder) {
1810 DecodeStatus S = MCDisassembler::Success;
1811
1812 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1813 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1814 unsigned imm = 0;
1815
1816 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1817 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1818
1819 if (Inst.getOpcode() == ARM::MOVTi16)
1820 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1821 return MCDisassembler::Fail;
1822 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1823 return MCDisassembler::Fail;
1824
1825 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1826 Inst.addOperand(MCOperand::CreateImm(imm));
1827
1828 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1829 return MCDisassembler::Fail;
1830
1831 return S;
1832}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1833
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1834static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1835 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1836 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1837
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1838 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1839 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1840 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1841 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1842 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1843
1844 if (pred == 0xF)
1845 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1846
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1847 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1848 return MCDisassembler::Fail;
1849 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1850 return MCDisassembler::Fail;
1851 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1852 return MCDisassembler::Fail;
1853 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1854 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1855
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1856 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1857 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1858
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1859 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1860}
1861
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1862static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1863 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1864 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1865
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1866 unsigned add = fieldFromInstruction32(Val, 12, 1);
1867 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1868 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1869
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1871 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1872
1873 if (!add) imm *= -1;
1874 if (imm == 0 && !add) imm = INT32_MIN;
1875 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1876 if (Rn == 15)
1877 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1878
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1879 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1880}
1881
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1882static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1883 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1884 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1885
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1886 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1887 unsigned U = fieldFromInstruction32(Val, 8, 1);
1888 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1889
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1891 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1892
1893 if (U)
1894 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1895 else
1896 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1897
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1898 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1899}
1900
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1901static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1902 uint64_t Address, const void *Decoder) {
1903 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1904}
1905
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1906static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1907DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1908 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1909 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1910
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1911 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1912 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1913
1914 if (pred == 0xF) {
1915 Inst.setOpcode(ARM::BLXi);
1916 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1917 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1918 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1919 }
1920
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1921 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1922 4, Inst, Decoder))
1923 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1924 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1925 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1926
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1927 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1928}
1929
1930
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1931static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1932 uint64_t Address, const void *Decoder) {
1933 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1934 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1935}
1936
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1937static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1938 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1939 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1940
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1941 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1942 unsigned align = fieldFromInstruction32(Val, 4, 2);
1943
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1945 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1946 if (!align)
1947 Inst.addOperand(MCOperand::CreateImm(0));
1948 else
1949 Inst.addOperand(MCOperand::CreateImm(4 << align));
1950
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1951 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1952}
1953
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1954static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1955 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1956 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1957
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1958 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1959 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1960 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1961 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1962 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1963 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1964
1965 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1967 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1968
1969 // Second output register
1970 switch (Inst.getOpcode()) {
1971 case ARM::VLD1q8:
1972 case ARM::VLD1q16:
1973 case ARM::VLD1q32:
1974 case ARM::VLD1q64:
1975 case ARM::VLD1q8_UPD:
1976 case ARM::VLD1q16_UPD:
1977 case ARM::VLD1q32_UPD:
1978 case ARM::VLD1q64_UPD:
1979 case ARM::VLD1d8T:
1980 case ARM::VLD1d16T:
1981 case ARM::VLD1d32T:
1982 case ARM::VLD1d64T:
1983 case ARM::VLD1d8T_UPD:
1984 case ARM::VLD1d16T_UPD:
1985 case ARM::VLD1d32T_UPD:
1986 case ARM::VLD1d64T_UPD:
1987 case ARM::VLD1d8Q:
1988 case ARM::VLD1d16Q:
1989 case ARM::VLD1d32Q:
1990 case ARM::VLD1d64Q:
1991 case ARM::VLD1d8Q_UPD:
1992 case ARM::VLD1d16Q_UPD:
1993 case ARM::VLD1d32Q_UPD:
1994 case ARM::VLD1d64Q_UPD:
1995 case ARM::VLD2d8:
1996 case ARM::VLD2d16:
1997 case ARM::VLD2d32:
1998 case ARM::VLD2d8_UPD:
1999 case ARM::VLD2d16_UPD:
2000 case ARM::VLD2d32_UPD:
2001 case ARM::VLD2q8:
2002 case ARM::VLD2q16:
2003 case ARM::VLD2q32:
2004 case ARM::VLD2q8_UPD:
2005 case ARM::VLD2q16_UPD:
2006 case ARM::VLD2q32_UPD:
2007 case ARM::VLD3d8:
2008 case ARM::VLD3d16:
2009 case ARM::VLD3d32:
2010 case ARM::VLD3d8_UPD:
2011 case ARM::VLD3d16_UPD:
2012 case ARM::VLD3d32_UPD:
2013 case ARM::VLD4d8:
2014 case ARM::VLD4d16:
2015 case ARM::VLD4d32:
2016 case ARM::VLD4d8_UPD:
2017 case ARM::VLD4d16_UPD:
2018 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2019 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2020 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2021 break;
2022 case ARM::VLD2b8:
2023 case ARM::VLD2b16:
2024 case ARM::VLD2b32:
2025 case ARM::VLD2b8_UPD:
2026 case ARM::VLD2b16_UPD:
2027 case ARM::VLD2b32_UPD:
2028 case ARM::VLD3q8:
2029 case ARM::VLD3q16:
2030 case ARM::VLD3q32:
2031 case ARM::VLD3q8_UPD:
2032 case ARM::VLD3q16_UPD:
2033 case ARM::VLD3q32_UPD:
2034 case ARM::VLD4q8:
2035 case ARM::VLD4q16:
2036 case ARM::VLD4q32:
2037 case ARM::VLD4q8_UPD:
2038 case ARM::VLD4q16_UPD:
2039 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2040 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2041 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2042 default:
2043 break;
2044 }
2045
2046 // Third output register
2047 switch(Inst.getOpcode()) {
2048 case ARM::VLD1d8T:
2049 case ARM::VLD1d16T:
2050 case ARM::VLD1d32T:
2051 case ARM::VLD1d64T:
2052 case ARM::VLD1d8T_UPD:
2053 case ARM::VLD1d16T_UPD:
2054 case ARM::VLD1d32T_UPD:
2055 case ARM::VLD1d64T_UPD:
2056 case ARM::VLD1d8Q:
2057 case ARM::VLD1d16Q:
2058 case ARM::VLD1d32Q:
2059 case ARM::VLD1d64Q:
2060 case ARM::VLD1d8Q_UPD:
2061 case ARM::VLD1d16Q_UPD:
2062 case ARM::VLD1d32Q_UPD:
2063 case ARM::VLD1d64Q_UPD:
2064 case ARM::VLD2q8:
2065 case ARM::VLD2q16:
2066 case ARM::VLD2q32:
2067 case ARM::VLD2q8_UPD:
2068 case ARM::VLD2q16_UPD:
2069 case ARM::VLD2q32_UPD:
2070 case ARM::VLD3d8:
2071 case ARM::VLD3d16:
2072 case ARM::VLD3d32:
2073 case ARM::VLD3d8_UPD:
2074 case ARM::VLD3d16_UPD:
2075 case ARM::VLD3d32_UPD:
2076 case ARM::VLD4d8:
2077 case ARM::VLD4d16:
2078 case ARM::VLD4d32:
2079 case ARM::VLD4d8_UPD:
2080 case ARM::VLD4d16_UPD:
2081 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2082 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2083 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2084 break;
2085 case ARM::VLD3q8:
2086 case ARM::VLD3q16:
2087 case ARM::VLD3q32:
2088 case ARM::VLD3q8_UPD:
2089 case ARM::VLD3q16_UPD:
2090 case ARM::VLD3q32_UPD:
2091 case ARM::VLD4q8:
2092 case ARM::VLD4q16:
2093 case ARM::VLD4q32:
2094 case ARM::VLD4q8_UPD:
2095 case ARM::VLD4q16_UPD:
2096 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2097 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2098 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2099 break;
2100 default:
2101 break;
2102 }
2103
2104 // Fourth output register
2105 switch (Inst.getOpcode()) {
2106 case ARM::VLD1d8Q:
2107 case ARM::VLD1d16Q:
2108 case ARM::VLD1d32Q:
2109 case ARM::VLD1d64Q:
2110 case ARM::VLD1d8Q_UPD:
2111 case ARM::VLD1d16Q_UPD:
2112 case ARM::VLD1d32Q_UPD:
2113 case ARM::VLD1d64Q_UPD:
2114 case ARM::VLD2q8:
2115 case ARM::VLD2q16:
2116 case ARM::VLD2q32:
2117 case ARM::VLD2q8_UPD:
2118 case ARM::VLD2q16_UPD:
2119 case ARM::VLD2q32_UPD:
2120 case ARM::VLD4d8:
2121 case ARM::VLD4d16:
2122 case ARM::VLD4d32:
2123 case ARM::VLD4d8_UPD:
2124 case ARM::VLD4d16_UPD:
2125 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2126 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2127 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2128 break;
2129 case ARM::VLD4q8:
2130 case ARM::VLD4q16:
2131 case ARM::VLD4q32:
2132 case ARM::VLD4q8_UPD:
2133 case ARM::VLD4q16_UPD:
2134 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2135 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2136 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2137 break;
2138 default:
2139 break;
2140 }
2141
2142 // Writeback operand
2143 switch (Inst.getOpcode()) {
2144 case ARM::VLD1d8_UPD:
2145 case ARM::VLD1d16_UPD:
2146 case ARM::VLD1d32_UPD:
2147 case ARM::VLD1d64_UPD:
2148 case ARM::VLD1q8_UPD:
2149 case ARM::VLD1q16_UPD:
2150 case ARM::VLD1q32_UPD:
2151 case ARM::VLD1q64_UPD:
2152 case ARM::VLD1d8T_UPD:
2153 case ARM::VLD1d16T_UPD:
2154 case ARM::VLD1d32T_UPD:
2155 case ARM::VLD1d64T_UPD:
2156 case ARM::VLD1d8Q_UPD:
2157 case ARM::VLD1d16Q_UPD:
2158 case ARM::VLD1d32Q_UPD:
2159 case ARM::VLD1d64Q_UPD:
2160 case ARM::VLD2d8_UPD:
2161 case ARM::VLD2d16_UPD:
2162 case ARM::VLD2d32_UPD:
2163 case ARM::VLD2q8_UPD:
2164 case ARM::VLD2q16_UPD:
2165 case ARM::VLD2q32_UPD:
2166 case ARM::VLD2b8_UPD:
2167 case ARM::VLD2b16_UPD:
2168 case ARM::VLD2b32_UPD:
2169 case ARM::VLD3d8_UPD:
2170 case ARM::VLD3d16_UPD:
2171 case ARM::VLD3d32_UPD:
2172 case ARM::VLD3q8_UPD:
2173 case ARM::VLD3q16_UPD:
2174 case ARM::VLD3q32_UPD:
2175 case ARM::VLD4d8_UPD:
2176 case ARM::VLD4d16_UPD:
2177 case ARM::VLD4d32_UPD:
2178 case ARM::VLD4q8_UPD:
2179 case ARM::VLD4q16_UPD:
2180 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2181 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2182 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2183 break;
2184 default:
2185 break;
2186 }
2187
2188 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2189 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2190 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2191
2192 // AddrMode6 Offset (register)
2193 if (Rm == 0xD)
2194 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2195 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2197 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2198 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2199
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2200 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2201}
2202
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2203static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2204 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2205 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2206
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2207 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2208 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2209 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2210 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2211 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2212 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2213
2214 // Writeback Operand
2215 switch (Inst.getOpcode()) {
2216 case ARM::VST1d8_UPD:
2217 case ARM::VST1d16_UPD:
2218 case ARM::VST1d32_UPD:
2219 case ARM::VST1d64_UPD:
2220 case ARM::VST1q8_UPD:
2221 case ARM::VST1q16_UPD:
2222 case ARM::VST1q32_UPD:
2223 case ARM::VST1q64_UPD:
2224 case ARM::VST1d8T_UPD:
2225 case ARM::VST1d16T_UPD:
2226 case ARM::VST1d32T_UPD:
2227 case ARM::VST1d64T_UPD:
2228 case ARM::VST1d8Q_UPD:
2229 case ARM::VST1d16Q_UPD:
2230 case ARM::VST1d32Q_UPD:
2231 case ARM::VST1d64Q_UPD:
2232 case ARM::VST2d8_UPD:
2233 case ARM::VST2d16_UPD:
2234 case ARM::VST2d32_UPD:
2235 case ARM::VST2q8_UPD:
2236 case ARM::VST2q16_UPD:
2237 case ARM::VST2q32_UPD:
2238 case ARM::VST2b8_UPD:
2239 case ARM::VST2b16_UPD:
2240 case ARM::VST2b32_UPD:
2241 case ARM::VST3d8_UPD:
2242 case ARM::VST3d16_UPD:
2243 case ARM::VST3d32_UPD:
2244 case ARM::VST3q8_UPD:
2245 case ARM::VST3q16_UPD:
2246 case ARM::VST3q32_UPD:
2247 case ARM::VST4d8_UPD:
2248 case ARM::VST4d16_UPD:
2249 case ARM::VST4d32_UPD:
2250 case ARM::VST4q8_UPD:
2251 case ARM::VST4q16_UPD:
2252 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2253 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2254 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2255 break;
2256 default:
2257 break;
2258 }
2259
2260 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2261 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2262 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2263
2264 // AddrMode6 Offset (register)
2265 if (Rm == 0xD)
2266 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2267 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2269 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2270 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2271
2272 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2273 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2274 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2275
2276 // Second input register
2277 switch (Inst.getOpcode()) {
2278 case ARM::VST1q8:
2279 case ARM::VST1q16:
2280 case ARM::VST1q32:
2281 case ARM::VST1q64:
2282 case ARM::VST1q8_UPD:
2283 case ARM::VST1q16_UPD:
2284 case ARM::VST1q32_UPD:
2285 case ARM::VST1q64_UPD:
2286 case ARM::VST1d8T:
2287 case ARM::VST1d16T:
2288 case ARM::VST1d32T:
2289 case ARM::VST1d64T:
2290 case ARM::VST1d8T_UPD:
2291 case ARM::VST1d16T_UPD:
2292 case ARM::VST1d32T_UPD:
2293 case ARM::VST1d64T_UPD:
2294 case ARM::VST1d8Q:
2295 case ARM::VST1d16Q:
2296 case ARM::VST1d32Q:
2297 case ARM::VST1d64Q:
2298 case ARM::VST1d8Q_UPD:
2299 case ARM::VST1d16Q_UPD:
2300 case ARM::VST1d32Q_UPD:
2301 case ARM::VST1d64Q_UPD:
2302 case ARM::VST2d8:
2303 case ARM::VST2d16:
2304 case ARM::VST2d32:
2305 case ARM::VST2d8_UPD:
2306 case ARM::VST2d16_UPD:
2307 case ARM::VST2d32_UPD:
2308 case ARM::VST2q8:
2309 case ARM::VST2q16:
2310 case ARM::VST2q32:
2311 case ARM::VST2q8_UPD:
2312 case ARM::VST2q16_UPD:
2313 case ARM::VST2q32_UPD:
2314 case ARM::VST3d8:
2315 case ARM::VST3d16:
2316 case ARM::VST3d32:
2317 case ARM::VST3d8_UPD:
2318 case ARM::VST3d16_UPD:
2319 case ARM::VST3d32_UPD:
2320 case ARM::VST4d8:
2321 case ARM::VST4d16:
2322 case ARM::VST4d32:
2323 case ARM::VST4d8_UPD:
2324 case ARM::VST4d16_UPD:
2325 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2326 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2327 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2328 break;
2329 case ARM::VST2b8:
2330 case ARM::VST2b16:
2331 case ARM::VST2b32:
2332 case ARM::VST2b8_UPD:
2333 case ARM::VST2b16_UPD:
2334 case ARM::VST2b32_UPD:
2335 case ARM::VST3q8:
2336 case ARM::VST3q16:
2337 case ARM::VST3q32:
2338 case ARM::VST3q8_UPD:
2339 case ARM::VST3q16_UPD:
2340 case ARM::VST3q32_UPD:
2341 case ARM::VST4q8:
2342 case ARM::VST4q16:
2343 case ARM::VST4q32:
2344 case ARM::VST4q8_UPD:
2345 case ARM::VST4q16_UPD:
2346 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2347 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2348 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2349 break;
2350 default:
2351 break;
2352 }
2353
2354 // Third input register
2355 switch (Inst.getOpcode()) {
2356 case ARM::VST1d8T:
2357 case ARM::VST1d16T:
2358 case ARM::VST1d32T:
2359 case ARM::VST1d64T:
2360 case ARM::VST1d8T_UPD:
2361 case ARM::VST1d16T_UPD:
2362 case ARM::VST1d32T_UPD:
2363 case ARM::VST1d64T_UPD:
2364 case ARM::VST1d8Q:
2365 case ARM::VST1d16Q:
2366 case ARM::VST1d32Q:
2367 case ARM::VST1d64Q:
2368 case ARM::VST1d8Q_UPD:
2369 case ARM::VST1d16Q_UPD:
2370 case ARM::VST1d32Q_UPD:
2371 case ARM::VST1d64Q_UPD:
2372 case ARM::VST2q8:
2373 case ARM::VST2q16:
2374 case ARM::VST2q32:
2375 case ARM::VST2q8_UPD:
2376 case ARM::VST2q16_UPD:
2377 case ARM::VST2q32_UPD:
2378 case ARM::VST3d8:
2379 case ARM::VST3d16:
2380 case ARM::VST3d32:
2381 case ARM::VST3d8_UPD:
2382 case ARM::VST3d16_UPD:
2383 case ARM::VST3d32_UPD:
2384 case ARM::VST4d8:
2385 case ARM::VST4d16:
2386 case ARM::VST4d32:
2387 case ARM::VST4d8_UPD:
2388 case ARM::VST4d16_UPD:
2389 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2390 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2391 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2392 break;
2393 case ARM::VST3q8:
2394 case ARM::VST3q16:
2395 case ARM::VST3q32:
2396 case ARM::VST3q8_UPD:
2397 case ARM::VST3q16_UPD:
2398 case ARM::VST3q32_UPD:
2399 case ARM::VST4q8:
2400 case ARM::VST4q16:
2401 case ARM::VST4q32:
2402 case ARM::VST4q8_UPD:
2403 case ARM::VST4q16_UPD:
2404 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2405 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2406 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2407 break;
2408 default:
2409 break;
2410 }
2411
2412 // Fourth input register
2413 switch (Inst.getOpcode()) {
2414 case ARM::VST1d8Q:
2415 case ARM::VST1d16Q:
2416 case ARM::VST1d32Q:
2417 case ARM::VST1d64Q:
2418 case ARM::VST1d8Q_UPD:
2419 case ARM::VST1d16Q_UPD:
2420 case ARM::VST1d32Q_UPD:
2421 case ARM::VST1d64Q_UPD:
2422 case ARM::VST2q8:
2423 case ARM::VST2q16:
2424 case ARM::VST2q32:
2425 case ARM::VST2q8_UPD:
2426 case ARM::VST2q16_UPD:
2427 case ARM::VST2q32_UPD:
2428 case ARM::VST4d8:
2429 case ARM::VST4d16:
2430 case ARM::VST4d32:
2431 case ARM::VST4d8_UPD:
2432 case ARM::VST4d16_UPD:
2433 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2434 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2435 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2436 break;
2437 case ARM::VST4q8:
2438 case ARM::VST4q16:
2439 case ARM::VST4q32:
2440 case ARM::VST4q8_UPD:
2441 case ARM::VST4q16_UPD:
2442 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2443 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2444 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2445 break;
2446 default:
2447 break;
2448 }
2449
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2450 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2451}
2452
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2453static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2454 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2455 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2456
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2457 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2458 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2459 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2460 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2461 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2462 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2463 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2464
2465 align *= (1 << size);
2466
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2468 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2469 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2470 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2471 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2472 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2473 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2475 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2476 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2477
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2479 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2480 Inst.addOperand(MCOperand::CreateImm(align));
2481
2482 if (Rm == 0xD)
2483 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2484 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2486 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2487 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2488
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2489 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2490}
2491
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2492static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2493 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2494 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2495
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2496 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2497 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2498 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2499 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2500 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2501 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2502 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2503 align *= 2*size;
2504
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2506 return MCDisassembler::Fail;
2507 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2508 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2509 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2511 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2512 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2515 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2516 Inst.addOperand(MCOperand::CreateImm(align));
2517
2518 if (Rm == 0xD)
2519 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2520 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2522 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2523 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2525 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2526}
2527
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2528static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2529 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2530 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2531
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2532 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2533 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2534 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2535 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2536 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2537
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2539 return MCDisassembler::Fail;
2540 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2541 return MCDisassembler::Fail;
2542 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2543 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2544 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2546 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2547 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2548
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2550 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2551 Inst.addOperand(MCOperand::CreateImm(0));
2552
2553 if (Rm == 0xD)
2554 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2555 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2557 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2558 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2559
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2560 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2561}
2562
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2563static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2564 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2565 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2566
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2567 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2568 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2569 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2570 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2571 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2572 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2573 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2574
2575 if (size == 0x3) {
2576 size = 4;
2577 align = 16;
2578 } else {
2579 if (size == 2) {
2580 size = 1 << size;
2581 align *= 8;
2582 } else {
2583 size = 1 << size;
2584 align *= 4*size;
2585 }
2586 }
2587
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2588 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2589 return MCDisassembler::Fail;
2590 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2591 return MCDisassembler::Fail;
2592 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2593 return MCDisassembler::Fail;
2594 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2595 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2596 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2598 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2599 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2600
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2602 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2603 Inst.addOperand(MCOperand::CreateImm(align));
2604
2605 if (Rm == 0xD)
2606 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2607 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2609 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2610 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2611
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2612 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2613}
2614
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2615static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2616DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2617 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2618 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2619
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2620 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2621 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2622 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2623 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2624 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2625 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2626 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2627 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2628
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2629 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2630 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2631 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2632 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2634 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2635 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2636
2637 Inst.addOperand(MCOperand::CreateImm(imm));
2638
2639 switch (Inst.getOpcode()) {
2640 case ARM::VORRiv4i16:
2641 case ARM::VORRiv2i32:
2642 case ARM::VBICiv4i16:
2643 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2644 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2645 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2646 break;
2647 case ARM::VORRiv8i16:
2648 case ARM::VORRiv4i32:
2649 case ARM::VBICiv8i16:
2650 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2651 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2652 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2653 break;
2654 default:
2655 break;
2656 }
2657
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2658 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2659}
2660
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2661static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2662 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2663 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2664
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2665 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2666 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2667 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2668 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2669 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2670
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2671 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2672 return MCDisassembler::Fail;
2673 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2674 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2675 Inst.addOperand(MCOperand::CreateImm(8 << size));
2676
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2677 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2678}
2679
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2680static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2681 uint64_t Address, const void *Decoder) {
2682 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2683 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684}
2685
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2686static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2687 uint64_t Address, const void *Decoder) {
2688 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2689 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2690}
2691
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2692static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2693 uint64_t Address, const void *Decoder) {
2694 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2695 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2696}
2697
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2698static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2699 uint64_t Address, const void *Decoder) {
2700 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2701 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2702}
2703
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2704static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2705 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2706 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2707
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2708 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2709 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2710 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2711 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2712 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2713 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2714 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2715 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2716
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2718 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2719 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2721 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2722 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2723
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2724 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2725 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2726 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2727 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2728
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2730 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2731
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2732 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2733}
2734
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2735static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2736 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2737 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2738
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2739 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2740 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2741
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2742 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2743 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2744
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2745 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2746 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2747 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2748 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2749 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2750 case ARM::tADDrSPi:
2751 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2752 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2753 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2754
2755 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2756 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757}
2758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2759static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2760 uint64_t Address, const void *Decoder) {
2761 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2762 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2763}
2764
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2765static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2766 uint64_t Address, const void *Decoder) {
2767 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2768 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2769}
2770
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2771static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2772 uint64_t Address, const void *Decoder) {
2773 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2774 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2775}
2776
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2777static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2778 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2779 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2780
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2781 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2782 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2783
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2784 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2785 return MCDisassembler::Fail;
2786 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2787 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2788
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2789 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2790}
2791
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2792static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2793 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2794 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2795
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2796 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2797 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2798
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2799 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2800 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2801 Inst.addOperand(MCOperand::CreateImm(imm));
2802
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2803 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804}
2805
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2806static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2807 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2808 unsigned imm = Val << 2;
2809
2810 Inst.addOperand(MCOperand::CreateImm(imm));
2811 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2813 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2814}
2815
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2816static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817 uint64_t Address, const void *Decoder) {
2818 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2819 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2820
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2821 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2822}
2823
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2824static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2825 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2826 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2827
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2828 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2829 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2830 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2831
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2833 return MCDisassembler::Fail;
2834 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2835 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2836 Inst.addOperand(MCOperand::CreateImm(imm));
2837
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2838 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2839}
2840
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2841static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2842 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2843 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2844
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2845 switch (Inst.getOpcode()) {
2846 case ARM::t2PLDs:
2847 case ARM::t2PLDWs:
2848 case ARM::t2PLIs:
2849 break;
2850 default: {
2851 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2852 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2853 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2854 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2855 }
2856
2857 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2858 if (Rn == 0xF) {
2859 switch (Inst.getOpcode()) {
2860 case ARM::t2LDRBs:
2861 Inst.setOpcode(ARM::t2LDRBpci);
2862 break;
2863 case ARM::t2LDRHs:
2864 Inst.setOpcode(ARM::t2LDRHpci);
2865 break;
2866 case ARM::t2LDRSHs:
2867 Inst.setOpcode(ARM::t2LDRSHpci);
2868 break;
2869 case ARM::t2LDRSBs:
2870 Inst.setOpcode(ARM::t2LDRSBpci);
2871 break;
2872 case ARM::t2PLDs:
2873 Inst.setOpcode(ARM::t2PLDi12);
2874 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2875 break;
2876 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2877 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2878 }
2879
2880 int imm = fieldFromInstruction32(Insn, 0, 12);
2881 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2882 Inst.addOperand(MCOperand::CreateImm(imm));
2883
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2884 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2885 }
2886
2887 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2888 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2889 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2890 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2891 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2892
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2893 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2894}
2895
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2896static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2897 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2898 int imm = Val & 0xFF;
2899 if (!(Val & 0x100)) imm *= -1;
2900 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2901
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2902 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2903}
2904
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2905static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2906 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2907 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2908
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2909 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2910 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2911
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2912 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2913 return MCDisassembler::Fail;
2914 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2915 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2916
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2917 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2918}
2919
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2920static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2921 uint64_t Address, const void *Decoder) {
2922 DecodeStatus S = MCDisassembler::Success;
2923
2924 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2925 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2926
2927 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2928 return MCDisassembler::Fail;
2929
2930 Inst.addOperand(MCOperand::CreateImm(imm));
2931
2932 return S;
2933}
2934
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2935static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2936 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2937 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2938 if (Val == 0)
2939 imm = INT32_MIN;
2940 else if (!(Val & 0x100))
2941 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2942 Inst.addOperand(MCOperand::CreateImm(imm));
2943
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2944 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2945}
2946
2947
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2948static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2949 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2950 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2951
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2952 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2953 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2954
2955 // Some instructions always use an additive offset.
2956 switch (Inst.getOpcode()) {
2957 case ARM::t2LDRT:
2958 case ARM::t2LDRBT:
2959 case ARM::t2LDRHT:
2960 case ARM::t2LDRSBT:
2961 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2962 case ARM::t2STRT:
2963 case ARM::t2STRBT:
2964 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2965 imm |= 0x100;
2966 break;
2967 default:
2968 break;
2969 }
2970
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2971 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2972 return MCDisassembler::Fail;
2973 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2974 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2975
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2976 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2977}
2978
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2979static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2980 uint64_t Address, const void *Decoder) {
2981 DecodeStatus S = MCDisassembler::Success;
2982
2983 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2984 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2985 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2986 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2987 addr |= Rn << 9;
2988 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2989
2990 if (!load) {
2991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2992 return MCDisassembler::Fail;
2993 }
2994
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2995 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2996 return MCDisassembler::Fail;
2997
2998 if (load) {
2999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3000 return MCDisassembler::Fail;
3001 }
3002
3003 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3004 return MCDisassembler::Fail;
3005
3006 return S;
3007}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3008
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3009static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3010 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3011 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3012
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3013 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3014 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3015
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3017 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3018 Inst.addOperand(MCOperand::CreateImm(imm));
3019
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3020 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3021}
3022
3023
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3024static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3025 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3026 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3027
3028 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3029 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3030 Inst.addOperand(MCOperand::CreateImm(imm));
3031
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3032 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3033}
3034
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3035static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3036 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3037 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3038
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3039 if (Inst.getOpcode() == ARM::tADDrSP) {
3040 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3041 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3042
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3043 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3044 return MCDisassembler::Fail;
3045 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3046 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3047 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3048 } else if (Inst.getOpcode() == ARM::tADDspr) {
3049 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3050
3051 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3052 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3054 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3055 }
3056
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3057 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3058}
3059
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3060static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3061 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3062 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3063 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3064
3065 Inst.addOperand(MCOperand::CreateImm(imod));
3066 Inst.addOperand(MCOperand::CreateImm(flags));
3067
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3068 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3069}
3070
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3071static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3072 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3073 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3074 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3075 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3076
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3078 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3079 Inst.addOperand(MCOperand::CreateImm(add));
3080
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3081 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3082}
3083
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3084static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3085 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3086 if (!tryAddingSymbolicOperand(Address,
3087 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3088 true, 4, Inst, Decoder))
3089 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3090 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3091}
3092
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3093static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3094 uint64_t Address, const void *Decoder) {
3095 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3096 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3097
3098 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3099 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3100}
3101
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3102static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3103DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3104 uint64_t Address, const void *Decoder) {
3105 DecodeStatus S = MCDisassembler::Success;
3106
3107 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3108 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3109
3110 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3112 return MCDisassembler::Fail;
3113 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3114 return MCDisassembler::Fail;
3115 return S;
3116}
3117
3118static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3119DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3120 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3121 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3122
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3123 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3124 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3125 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3126 switch (opc) {
3127 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3128 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3129 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3130 Inst.setOpcode(ARM::t2DSB);
3131 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3132 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3133 Inst.setOpcode(ARM::t2DMB);
3134 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3135 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3136 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3137 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3138 }
3139
3140 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3141 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3142 }
3143
3144 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3145 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3146 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3147 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3148 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3149
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3150 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3151 return MCDisassembler::Fail;
3152 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3153 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3154
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3155 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3156}
3157
3158// Decode a shifted immediate operand. These basically consist
3159// of an 8-bit value, and a 4-bit directive that specifies either
3160// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3161static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3162 uint64_t Address, const void *Decoder) {
3163 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3164 if (ctrl == 0) {
3165 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3166 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3167 switch (byte) {
3168 case 0:
3169 Inst.addOperand(MCOperand::CreateImm(imm));
3170 break;
3171 case 1:
3172 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3173 break;
3174 case 2:
3175 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3176 break;
3177 case 3:
3178 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3179 (imm << 8) | imm));
3180 break;
3181 }
3182 } else {
3183 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3184 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3185 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3186 Inst.addOperand(MCOperand::CreateImm(imm));
3187 }
3188
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3189 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3190}
3191
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3192static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3193DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3194 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3195 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3196 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3197}
3198
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3199static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3200 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3201 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3202 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3203}
3204
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3205static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3206 uint64_t Address, const void *Decoder) {
3207 switch (Val) {
3208 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3209 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3210 case 0xF: // SY
3211 case 0xE: // ST
3212 case 0xB: // ISH
3213 case 0xA: // ISHST
3214 case 0x7: // NSH
3215 case 0x6: // NSHST
3216 case 0x3: // OSH
3217 case 0x2: // OSHST
3218 break;
3219 }
3220
3221 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3222 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3223}
3224
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3225static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3226 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3227 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3228 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3229 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3230}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3231
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3232static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3233 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3234 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3235
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3236 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3237 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3238 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3239
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3240 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3241
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3243 return MCDisassembler::Fail;
3244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3245 return MCDisassembler::Fail;
3246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3247 return MCDisassembler::Fail;
3248 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3249 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3250
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3251 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3252}
3253
3254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3255static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3256 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3257 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3258
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3259 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3260 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3261 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3262 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3263
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3264 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3265 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3266
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3267 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3268 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3269
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3270 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3271 return MCDisassembler::Fail;
3272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3273 return MCDisassembler::Fail;
3274 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3275 return MCDisassembler::Fail;
3276 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3277 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3278
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3279 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3280}
3281
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3282static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3283 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3284 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3285
3286 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3287 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3288 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3289 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3290 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3291 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3292
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3293 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3294
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3296 return MCDisassembler::Fail;
3297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3298 return MCDisassembler::Fail;
3299 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3300 return MCDisassembler::Fail;
3301 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3302 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3303
3304 return S;
3305}
3306
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3307static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3308 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3309 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3310
3311 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3312 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3313 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3314 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3315 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3316 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3317 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3318
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3319 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3320 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3321
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3323 return MCDisassembler::Fail;
3324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3325 return MCDisassembler::Fail;
3326 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3327 return MCDisassembler::Fail;
3328 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3329 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3330
3331 return S;
3332}
3333
3334
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3335static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3336 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3337 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3338
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3339 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3340 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3341 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3342 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3343 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3344 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3345
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3346 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3347
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3349 return MCDisassembler::Fail;
3350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3351 return MCDisassembler::Fail;
3352 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3353 return MCDisassembler::Fail;
3354 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3355 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3356
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3357 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3358}
3359
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3360static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3361 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3362 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3363
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3364 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3365 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3366 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3367 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3368 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3369 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3370
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3371 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3372
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3374 return MCDisassembler::Fail;
3375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3376 return MCDisassembler::Fail;
3377 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3378 return MCDisassembler::Fail;
3379 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3380 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3381
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3382 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3383}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3384
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3385static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3386 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3387 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3388
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3389 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3390 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3391 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3392 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3393 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3394
3395 unsigned align = 0;
3396 unsigned index = 0;
3397 switch (size) {
3398 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3399 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3400 case 0:
3401 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3402 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3403 index = fieldFromInstruction32(Insn, 5, 3);
3404 break;
3405 case 1:
3406 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3407 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3408 index = fieldFromInstruction32(Insn, 6, 2);
3409 if (fieldFromInstruction32(Insn, 4, 1))
3410 align = 2;
3411 break;
3412 case 2:
3413 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3414 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3415 index = fieldFromInstruction32(Insn, 7, 1);
3416 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3417 align = 4;
3418 }
3419
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3421 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3422 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3424 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3425 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3427 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3428 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3429 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3430 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3432 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3433 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3434 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3435 }
3436
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3438 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3439 Inst.addOperand(MCOperand::CreateImm(index));
3440
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3441 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3442}
3443
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3444static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3445 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3446 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3447
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3448 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3449 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3450 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3451 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3452 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3453
3454 unsigned align = 0;
3455 unsigned index = 0;
3456 switch (size) {
3457 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3458 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3459 case 0:
3460 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3461 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3462 index = fieldFromInstruction32(Insn, 5, 3);
3463 break;
3464 case 1:
3465 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3466 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3467 index = fieldFromInstruction32(Insn, 6, 2);
3468 if (fieldFromInstruction32(Insn, 4, 1))
3469 align = 2;
3470 break;
3471 case 2:
3472 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3473 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3474 index = fieldFromInstruction32(Insn, 7, 1);
3475 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3476 align = 4;
3477 }
3478
3479 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3481 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3482 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3484 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3485 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3486 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3487 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3489 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3490 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3491 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3492 }
3493
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3494 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3495 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3496 Inst.addOperand(MCOperand::CreateImm(index));
3497
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3498 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3499}
3500
3501
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3502static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3503 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3504 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3505
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3506 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3507 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3508 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3509 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3510 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3511
3512 unsigned align = 0;
3513 unsigned index = 0;
3514 unsigned inc = 1;
3515 switch (size) {
3516 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3517 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3518 case 0:
3519 index = fieldFromInstruction32(Insn, 5, 3);
3520 if (fieldFromInstruction32(Insn, 4, 1))
3521 align = 2;
3522 break;
3523 case 1:
3524 index = fieldFromInstruction32(Insn, 6, 2);
3525 if (fieldFromInstruction32(Insn, 4, 1))
3526 align = 4;
3527 if (fieldFromInstruction32(Insn, 5, 1))
3528 inc = 2;
3529 break;
3530 case 2:
3531 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3532 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3533 index = fieldFromInstruction32(Insn, 7, 1);
3534 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3535 align = 8;
3536 if (fieldFromInstruction32(Insn, 6, 1))
3537 inc = 2;
3538 break;
3539 }
3540
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3541 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3542 return MCDisassembler::Fail;
3543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3544 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3545 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3546 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3547 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3548 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3550 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3551 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3552 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3553 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3555 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3556 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3557 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3558 }
3559
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3560 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3561 return MCDisassembler::Fail;
3562 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3563 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3564 Inst.addOperand(MCOperand::CreateImm(index));
3565
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3566 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3567}
3568
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3569static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3570 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3571 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3572
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3573 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3574 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3575 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3576 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3577 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3578
3579 unsigned align = 0;
3580 unsigned index = 0;
3581 unsigned inc = 1;
3582 switch (size) {
3583 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3584 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3585 case 0:
3586 index = fieldFromInstruction32(Insn, 5, 3);
3587 if (fieldFromInstruction32(Insn, 4, 1))
3588 align = 2;
3589 break;
3590 case 1:
3591 index = fieldFromInstruction32(Insn, 6, 2);
3592 if (fieldFromInstruction32(Insn, 4, 1))
3593 align = 4;
3594 if (fieldFromInstruction32(Insn, 5, 1))
3595 inc = 2;
3596 break;
3597 case 2:
3598 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3599 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3600 index = fieldFromInstruction32(Insn, 7, 1);
3601 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3602 align = 8;
3603 if (fieldFromInstruction32(Insn, 6, 1))
3604 inc = 2;
3605 break;
3606 }
3607
3608 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3610 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3611 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3613 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3614 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3615 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3616 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3618 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3619 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3620 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3621 }
3622
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3623 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3624 return MCDisassembler::Fail;
3625 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3626 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3627 Inst.addOperand(MCOperand::CreateImm(index));
3628
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3629 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3630}
3631
3632
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3633static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3634 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3635 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3636
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3637 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3638 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3639 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3640 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3641 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3642
3643 unsigned align = 0;
3644 unsigned index = 0;
3645 unsigned inc = 1;
3646 switch (size) {
3647 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3648 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3649 case 0:
3650 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3651 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3652 index = fieldFromInstruction32(Insn, 5, 3);
3653 break;
3654 case 1:
3655 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3656 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3657 index = fieldFromInstruction32(Insn, 6, 2);
3658 if (fieldFromInstruction32(Insn, 5, 1))
3659 inc = 2;
3660 break;
3661 case 2:
3662 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3663 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3664 index = fieldFromInstruction32(Insn, 7, 1);
3665 if (fieldFromInstruction32(Insn, 6, 1))
3666 inc = 2;
3667 break;
3668 }
3669
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3670 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3671 return MCDisassembler::Fail;
3672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3673 return MCDisassembler::Fail;
3674 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3675 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3676
3677 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3679 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3680 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3682 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3683 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3684 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3685 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3687 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3688 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3689 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3690 }
3691
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3692 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3693 return MCDisassembler::Fail;
3694 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3695 return MCDisassembler::Fail;
3696 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3697 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3698 Inst.addOperand(MCOperand::CreateImm(index));
3699
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3700 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3701}
3702
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3703static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3704 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3705 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3706
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3707 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3708 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3709 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3710 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3711 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3712
3713 unsigned align = 0;
3714 unsigned index = 0;
3715 unsigned inc = 1;
3716 switch (size) {
3717 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3718 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3719 case 0:
3720 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3721 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3722 index = fieldFromInstruction32(Insn, 5, 3);
3723 break;
3724 case 1:
3725 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3726 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3727 index = fieldFromInstruction32(Insn, 6, 2);
3728 if (fieldFromInstruction32(Insn, 5, 1))
3729 inc = 2;
3730 break;
3731 case 2:
3732 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3733 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3734 index = fieldFromInstruction32(Insn, 7, 1);
3735 if (fieldFromInstruction32(Insn, 6, 1))
3736 inc = 2;
3737 break;
3738 }
3739
3740 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3743 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3745 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3746 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3747 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3748 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3750 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3751 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3752 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3753 }
3754
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3755 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3756 return MCDisassembler::Fail;
3757 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3758 return MCDisassembler::Fail;
3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3760 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3761 Inst.addOperand(MCOperand::CreateImm(index));
3762
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3763 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3764}
3765
3766
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3767static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3768 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3769 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3770
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3771 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3772 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3773 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3774 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3775 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3776
3777 unsigned align = 0;
3778 unsigned index = 0;
3779 unsigned inc = 1;
3780 switch (size) {
3781 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3782 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3783 case 0:
3784 if (fieldFromInstruction32(Insn, 4, 1))
3785 align = 4;
3786 index = fieldFromInstruction32(Insn, 5, 3);
3787 break;
3788 case 1:
3789 if (fieldFromInstruction32(Insn, 4, 1))
3790 align = 8;
3791 index = fieldFromInstruction32(Insn, 6, 2);
3792 if (fieldFromInstruction32(Insn, 5, 1))
3793 inc = 2;
3794 break;
3795 case 2:
3796 if (fieldFromInstruction32(Insn, 4, 2))
3797 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3798 index = fieldFromInstruction32(Insn, 7, 1);
3799 if (fieldFromInstruction32(Insn, 6, 1))
3800 inc = 2;
3801 break;
3802 }
3803
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3804 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3805 return MCDisassembler::Fail;
3806 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3807 return MCDisassembler::Fail;
3808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3809 return MCDisassembler::Fail;
3810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3811 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3812
3813 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3815 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3816 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3818 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3819 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3820 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3821 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3823 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3824 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3825 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3826 }
3827
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3828 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3829 return MCDisassembler::Fail;
3830 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3831 return MCDisassembler::Fail;
3832 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3833 return MCDisassembler::Fail;
3834 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3835 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3836 Inst.addOperand(MCOperand::CreateImm(index));
3837
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3838 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3839}
3840
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3841static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3842 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3843 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3844
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3845 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3846 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3847 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3848 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3849 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3850
3851 unsigned align = 0;
3852 unsigned index = 0;
3853 unsigned inc = 1;
3854 switch (size) {
3855 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3856 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3857 case 0:
3858 if (fieldFromInstruction32(Insn, 4, 1))
3859 align = 4;
3860 index = fieldFromInstruction32(Insn, 5, 3);
3861 break;
3862 case 1:
3863 if (fieldFromInstruction32(Insn, 4, 1))
3864 align = 8;
3865 index = fieldFromInstruction32(Insn, 6, 2);
3866 if (fieldFromInstruction32(Insn, 5, 1))
3867 inc = 2;
3868 break;
3869 case 2:
3870 if (fieldFromInstruction32(Insn, 4, 2))
3871 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3872 index = fieldFromInstruction32(Insn, 7, 1);
3873 if (fieldFromInstruction32(Insn, 6, 1))
3874 inc = 2;
3875 break;
3876 }
3877
3878 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3880 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3881 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3883 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3884 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3885 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3886 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3888 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3889 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3890 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3891 }
3892
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3893 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3894 return MCDisassembler::Fail;
3895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3896 return MCDisassembler::Fail;
3897 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3898 return MCDisassembler::Fail;
3899 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3900 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3901 Inst.addOperand(MCOperand::CreateImm(index));
3902
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3903 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3904}
3905
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3906static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3907 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3908 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3909 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3910 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3911 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3912 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3913 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3914
3915 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3916 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3917
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3918 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3919 return MCDisassembler::Fail;
3920 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3921 return MCDisassembler::Fail;
3922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3923 return MCDisassembler::Fail;
3924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3925 return MCDisassembler::Fail;
3926 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3927 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3928
3929 return S;
3930}
3931
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3932static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3933 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3934 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3935 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3936 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3937 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3938 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3939 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3940
3941 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3942 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3943
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3945 return MCDisassembler::Fail;
3946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3947 return MCDisassembler::Fail;
3948 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3949 return MCDisassembler::Fail;
3950 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3951 return MCDisassembler::Fail;
3952 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3953 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3954
3955 return S;
3956}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3957
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3958static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3959 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3960 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3961 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3962 // The InstPrinter needs to have the low bit of the predicate in
3963 // the mask operand to be able to print it properly.
3964 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3965
3966 if (pred == 0xF) {
3967 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3968 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3969 }
3970
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3971 if ((mask & 0xF) == 0) {
3972 // Preserve the high bit of the mask, which is the low bit of
3973 // the predicate.
3974 mask &= 0x10;
3975 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3976 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3977 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3978
3979 Inst.addOperand(MCOperand::CreateImm(pred));
3980 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3981 return S;
3982}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3983
3984static DecodeStatus
3985DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3986 uint64_t Address, const void *Decoder) {
3987 DecodeStatus S = MCDisassembler::Success;
3988
3989 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3990 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3991 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3992 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3993 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3994 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3995 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3996 bool writeback = (W == 1) | (P == 0);
3997
3998 addr |= (U << 8) | (Rn << 9);
3999
4000 if (writeback && (Rn == Rt || Rn == Rt2))
4001 Check(S, MCDisassembler::SoftFail);
4002 if (Rt == Rt2)
4003 Check(S, MCDisassembler::SoftFail);
4004
4005 // Rt
4006 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4007 return MCDisassembler::Fail;
4008 // Rt2
4009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4010 return MCDisassembler::Fail;
4011 // Writeback operand
4012 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4013 return MCDisassembler::Fail;
4014 // addr
4015 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4016 return MCDisassembler::Fail;
4017
4018 return S;
4019}
4020
4021static DecodeStatus
4022DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4023 uint64_t Address, const void *Decoder) {
4024 DecodeStatus S = MCDisassembler::Success;
4025
4026 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4027 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4028 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4029 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4030 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4031 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4032 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4033 bool writeback = (W == 1) | (P == 0);
4034
4035 addr |= (U << 8) | (Rn << 9);
4036
4037 if (writeback && (Rn == Rt || Rn == Rt2))
4038 Check(S, MCDisassembler::SoftFail);
4039
4040 // Writeback operand
4041 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4042 return MCDisassembler::Fail;
4043 // Rt
4044 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4045 return MCDisassembler::Fail;
4046 // Rt2
4047 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4048 return MCDisassembler::Fail;
4049 // addr
4050 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4051 return MCDisassembler::Fail;
4052
4053 return S;
4054}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4055
4056static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4057 uint64_t Address, const void *Decoder) {
4058 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4059 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4060 if (sign1 != sign2) return MCDisassembler::Fail;
4061
4062 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4063 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4064 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4065 Val |= sign1 << 12;
4066 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4067
4068 return MCDisassembler::Success;
4069}
4070
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4071static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4072 uint64_t Address,
4073 const void *Decoder) {
4074 DecodeStatus S = MCDisassembler::Success;
4075
4076 // Shift of "asr #32" is not allowed in Thumb2 mode.
4077 if (Val == 0x20) S = MCDisassembler::SoftFail;
4078 Inst.addOperand(MCOperand::CreateImm(Val));
4079 return S;
4080}
4081