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gerrit-public.fairphone.software / platform / external / llvm / 7c4cf030a898b5b4e0d2c66adf8dc068b1f1f070 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 9c81eceb40f5db32eb72a489504c565780b58263 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]12#include "llvm/MC/MCDisassembler.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]13#include "MCTargetDesc/ARMAddressingModes.h"
14#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]15#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]20#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]21#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/ErrorHandling.h"
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]24#include "llvm/Support/LEB128.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]25#include "llvm/Support/MemoryObject.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]28#include <vector>
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]29
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]30using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]31
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]32typedef MCDisassembler::DecodeStatus DecodeStatus;
33
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]34namespace {
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]35 // Handles the condition code status of instructions in IT blocks
36 class ITStatus
37 {
38 public:
39 // Returns the condition code for instruction in IT block
40 unsigned getITCC() {
41 unsigned CC = ARMCC::AL;
42 if (instrInITBlock())
43 CC = ITStates.back();
44 return CC;
45 }
46
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
49 ITStates.pop_back();
50 }
51
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
55 }
56
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
60 }
61
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]67 unsigned CondBit0 = Firstcond & 1;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]68 unsigned NumTZ = CountTrailingZeros_32(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 if (T)
75 ITStates.push_back(CCBits);
76 else
77 ITStates.push_back(CCBits ^ 1);
78 }
79 ITStates.push_back(CCBits);
80 }
81
82 private:
83 std::vector<unsigned char> ITStates;
84 };
85}
86
87namespace {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]88/// ARMDisassembler - ARM disassembler for all ARM platforms.
89class ARMDisassembler : public MCDisassembler {
90public:
91 /// Constructor - Initializes the disassembler.
92 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]93 ARMDisassembler(const MCSubtargetInfo &STI) :
94 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]95 }
96
97 ~ARMDisassembler() {
98 }
99
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr,
102 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]103 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]104 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]105 raw_ostream &vStream,
106 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]107};
108
109/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
110class ThumbDisassembler : public MCDisassembler {
111public:
112 /// Constructor - Initializes the disassembler.
113 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]114 ThumbDisassembler(const MCSubtargetInfo &STI) :
115 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]116 }
117
118 ~ThumbDisassembler() {
119 }
120
121 /// getInstruction - See MCDisassembler.
122 DecodeStatus getInstruction(MCInst &instr,
123 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]124 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]125 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]126 raw_ostream &vStream,
127 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]128
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]129private:
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]130 mutable ITStatus ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]131 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]132 void UpdateThumbVFPPredicate(MCInst&) const;
133};
134}
135
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]137 switch (In) {
138 case MCDisassembler::Success:
139 // Out stays the same.
140 return true;
141 case MCDisassembler::SoftFail:
142 Out = In;
143 return true;
144 case MCDisassembler::Fail:
145 Out = In;
146 return false;
147 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]148 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]149}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]150
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]151
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152// Forward declare these because the autogenerated code will reference them.
153// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]154static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]156static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]157 unsigned RegNo, uint64_t Address,
158 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]159static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]161static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]163static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]165static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]167static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]169static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]171static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]172 unsigned RegNo,
173 uint64_t Address,
174 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]175static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]177static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]179static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]180 unsigned RegNo, uint64_t Address,
181 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]182
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]183static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]185static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]187static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]189static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]191static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]193static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]195
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]198static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]200static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]201 unsigned Insn,
202 uint64_t Address,
203 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]204static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]206static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]208static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]210static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
212
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]213static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]214 unsigned Insn,
215 uint64_t Adddress,
216 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]217static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]219static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]221static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]223static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]225static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]227static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]229static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]231static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]233static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
234 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]235static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]237static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]239static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]241static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]243static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]245static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]247static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]248 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]249static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]250 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]251static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]252 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]253static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]255static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]257static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]259static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]261static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]263static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]265static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]267static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]269static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]271static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]273static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]275static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]277static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]278 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]279static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]280 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]281static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]283static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]285static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]287static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]289static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]291static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]293static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]294 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]295static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]296 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]297static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]299static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]301static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]303static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]304 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]305static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]306 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]307static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]308 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]309static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]310 uint64_t Address, const void *Decoder);
Quentin Colombet7c4cf032013-04-17 18:46:12 +0000[diff] [blame^]311static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
312 const void *Decoder);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]313
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]314
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]315static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]316 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]317static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]318 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]319static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]320 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]321static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]322 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]323static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]324 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]325static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]326 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]327static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]328 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]329static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]330 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]331static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]332 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]333static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]334 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]335static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]336 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]337static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]338 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]339static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]340 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]341static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]342 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]343static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]344 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]345static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]346 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]347static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]348 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]349static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]350 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]351static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]352 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]353static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]354 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]355static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]356 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]357static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]358 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]359static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]360 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]361static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]362 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]363static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]364 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]365static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]366 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]367static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]368 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]369static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]370 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]371static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]372 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]373static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]374 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]375static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]376 uint64_t Address, const void *Decoder);
377
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]378static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]379 uint64_t Address, const void *Decoder);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]380static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382#include "ARMGenDisassemblerTables.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]383
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]384static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
385 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]386}
387
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]388static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
389 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]390}
391
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]392DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]393 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]394 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]395 raw_ostream &os,
396 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]397 CommentStream = &cs;
398
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]399 uint8_t bytes[4];
400
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]401 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
402 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
403
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]404 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]405 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
406 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]407 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]408 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]409
410 // Encoded as a small-endian 32-bit word in the stream.
411 uint32_t insn = (bytes[3] << 24) |
412 (bytes[2] << 16) |
413 (bytes[1] << 8) |
414 (bytes[0] << 0);
415
416 // Calling the auto-generated decoder function.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]417 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
418 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]419 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]420 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]421 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]422 }
423
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]424 // VFP and NEON instructions, similarly, are shared between ARM
425 // and Thumb modes.
426 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]427 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]428 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]429 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]430 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]431 }
432
433 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]434 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
435 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]436 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]437 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]438 // Add a fake predicate operand, because we share these instruction
439 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]440 if (!DecodePredicateOperand(MI, 0xE, Address, this))
441 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]442 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]443 }
444
445 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]446 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
447 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]448 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]449 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]450 // Add a fake predicate operand, because we share these instruction
451 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]452 if (!DecodePredicateOperand(MI, 0xE, Address, this))
453 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]454 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]455 }
456
457 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]458 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
459 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]460 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]461 Size = 4;
462 // Add a fake predicate operand, because we share these instruction
463 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]464 if (!DecodePredicateOperand(MI, 0xE, Address, this))
465 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]466 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]467 }
468
469 MI.clear();
470
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]471 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]472 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]473}
474
475namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]476extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]477}
478
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]479/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
480/// immediate Value in the MCInst. The immediate Value has had any PC
481/// adjustment made by the caller. If the instruction is a branch instruction
482/// then isBranch is true, else false. If the getOpInfo() function was set as
483/// part of the setupForSymbolicDisassembly() call then that function is called
484/// to get any symbolic information at the Address for this instruction. If
485/// that returns non-zero then the symbolic information it returns is used to
486/// create an MCExpr and that is added as an operand to the MCInst. If
487/// getOpInfo() returns zero and isBranch is true then a symbol look up for
488/// Value is done and if a symbol is found an MCExpr is created with that, else
489/// an MCExpr with Value is created. This function returns true if it adds an
490/// operand to the MCInst and false otherwise.
491static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
492 bool isBranch, uint64_t InstSize,
493 MCInst &MI, const void *Decoder) {
494 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
495 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]496 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]497 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]498 SymbolicOp.Value = Value;
499 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]500
501 if (!getOpInfo ||
502 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
503 // Clear SymbolicOp.Value from above and also all other fields.
504 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
505 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
506 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]507 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]508 uint64_t ReferenceType;
509 if (isBranch)
510 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
511 else
512 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
513 const char *ReferenceName;
Kevin Enderby88d12662012-10-18 21:49:18 +0000[diff] [blame]514 uint64_t SymbolValue = 0x00000000ffffffffULL & Value;
515 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType,
516 Address, &ReferenceName);
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]517 if (Name) {
518 SymbolicOp.AddSymbol.Name = Name;
519 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]520 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]521 // For branches always create an MCExpr so it gets printed as hex address.
522 else if (isBranch) {
523 SymbolicOp.Value = Value;
524 }
525 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
526 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
527 if (!Name && !isBranch)
528 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]529 }
530
531 MCContext *Ctx = Dis->getMCContext();
532 const MCExpr *Add = NULL;
533 if (SymbolicOp.AddSymbol.Present) {
534 if (SymbolicOp.AddSymbol.Name) {
535 StringRef Name(SymbolicOp.AddSymbol.Name);
536 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
537 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
538 } else {
539 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
540 }
541 }
542
543 const MCExpr *Sub = NULL;
544 if (SymbolicOp.SubtractSymbol.Present) {
545 if (SymbolicOp.SubtractSymbol.Name) {
546 StringRef Name(SymbolicOp.SubtractSymbol.Name);
547 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
548 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
549 } else {
550 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
551 }
552 }
553
554 const MCExpr *Off = NULL;
555 if (SymbolicOp.Value != 0)
556 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
557
558 const MCExpr *Expr;
559 if (Sub) {
560 const MCExpr *LHS;
561 if (Add)
562 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
563 else
564 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
565 if (Off != 0)
566 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
567 else
568 Expr = LHS;
569 } else if (Add) {
570 if (Off != 0)
571 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
572 else
573 Expr = Add;
574 } else {
575 if (Off != 0)
576 Expr = Off;
577 else
578 Expr = MCConstantExpr::Create(0, *Ctx);
579 }
580
581 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
582 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
583 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
584 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
585 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
586 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]587 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]588 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]589
590 return true;
591}
592
593/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
594/// referenced by a load instruction with the base register that is the Pc.
595/// These can often be values in a literal pool near the Address of the
596/// instruction. The Address of the instruction and its immediate Value are
597/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledruc8e41c52012-07-23 08:51:15 +0000[diff] [blame]598/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]599/// the referenced address is that of a symbol. Or it will return a pointer to
600/// a literal 'C' string if the referenced address of the literal pool's entry
601/// is an address into a section with 'C' string literals.
602static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]603 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]604 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
605 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
606 if (SymbolLookUp) {
607 void *DisInfo = Dis->getDisInfoBlock();
608 uint64_t ReferenceType;
609 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
610 const char *ReferenceName;
611 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
612 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
613 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
614 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
615 }
616}
617
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]618// Thumb1 instructions don't have explicit S bits. Rather, they
619// implicitly set CPSR. Since it's not represented in the encoding, the
620// auto-generated decoder won't inject the CPSR operand. We need to fix
621// that as a post-pass.
622static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
623 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]624 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]625 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]626 for (unsigned i = 0; i < NumOps; ++i, ++I) {
627 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]628 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]629 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]630 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
631 return;
632 }
633 }
634
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]635 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]636}
637
638// Most Thumb instructions don't have explicit predicates in the
639// encoding, but rather get their predicates from IT context. We need
640// to fix up the predicate operands using this context information as a
641// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]642MCDisassembler::DecodeStatus
643ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]644 MCDisassembler::DecodeStatus S = Success;
645
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]646 // A few instructions actually have predicates encoded in them. Don't
647 // try to overwrite it if we're seeing one of those.
648 switch (MI.getOpcode()) {
649 case ARM::tBcc:
650 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]651 case ARM::tCBZ:
652 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]653 case ARM::tCPS:
654 case ARM::t2CPS3p:
655 case ARM::t2CPS2p:
656 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]657 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]658 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]659 // Some instructions (mostly conditional branches) are not
660 // allowed in IT blocks.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]661 if (ITBlock.instrInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]662 S = SoftFail;
663 else
664 return Success;
665 break;
666 case ARM::tB:
667 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]668 case ARM::t2TBB:
669 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]670 // Some instructions (mostly unconditional branches) can
671 // only appears at the end of, or outside of, an IT.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]672 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]673 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]674 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]675 default:
676 break;
677 }
678
679 // If we're in an IT block, base the predicate on that. Otherwise,
680 // assume a predicate of AL.
681 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]682 CC = ITBlock.getITCC();
683 if (CC == 0xF)
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]684 CC = ARMCC::AL;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]685 if (ITBlock.instrInITBlock())
686 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]687
688 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]689 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]690 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]691 for (unsigned i = 0; i < NumOps; ++i, ++I) {
692 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]693 if (OpInfo[i].isPredicate()) {
694 I = MI.insert(I, MCOperand::CreateImm(CC));
695 ++I;
696 if (CC == ARMCC::AL)
697 MI.insert(I, MCOperand::CreateReg(0));
698 else
699 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]700 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]701 }
702 }
703
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]704 I = MI.insert(I, MCOperand::CreateImm(CC));
705 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]706 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]707 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]708 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]709 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]710
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]711 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]712}
713
714// Thumb VFP instructions are a special case. Because we share their
715// encodings between ARM and Thumb modes, and they are predicable in ARM
716// mode, the auto-generated decoder will give them an (incorrect)
717// predicate operand. We need to rewrite these operands based on the IT
718// context as a post-pass.
719void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
720 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]721 CC = ITBlock.getITCC();
722 if (ITBlock.instrInITBlock())
723 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]724
725 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
726 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]727 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
728 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]729 if (OpInfo[i].isPredicate() ) {
730 I->setImm(CC);
731 ++I;
732 if (CC == ARMCC::AL)
733 I->setReg(0);
734 else
735 I->setReg(ARM::CPSR);
736 return;
737 }
738 }
739}
740
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]741DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]742 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]743 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]744 raw_ostream &os,
745 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]746 CommentStream = &cs;
747
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]748 uint8_t bytes[4];
749
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]750 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
751 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
752
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]754 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
755 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]756 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]757 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]758
759 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]760 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
761 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]762 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]763 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]764 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]765 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]766 }
767
768 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]769 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
770 Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]771 if (result) {
772 Size = 2;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]773 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]774 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]775 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]776 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777 }
778
779 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]780 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
781 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]782 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]784
785 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
786 // the Thumb predicate.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]787 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]788 result = MCDisassembler::SoftFail;
789
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]790 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791
792 // If we find an IT instruction, we need to parse its condition
793 // code and mask operands so that we can apply them correctly
794 // to the subsequent instructions.
795 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]796
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]797 unsigned Firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]798 unsigned Mask = MI.getOperand(1).getImm();
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]799 ITBlock.setITState(Firstcond, Mask);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]800 }
801
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]802 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]803 }
804
805 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]806 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
807 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]808 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]809 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]810
811 uint32_t insn32 = (bytes[3] << 8) |
812 (bytes[2] << 0) |
813 (bytes[1] << 24) |
814 (bytes[0] << 16);
815 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]816 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
817 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]818 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]819 Size = 4;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]820 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]821 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]822 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]823 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]824 }
825
826 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]827 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
828 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]829 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]830 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]831 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]832 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833 }
834
835 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]836 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]837 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]838 Size = 4;
839 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]840 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]841 }
842
843 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]844 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
845 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]846 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]847 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]848 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]849 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]850 }
851
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]852 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]853 MI.clear();
854 uint32_t NEONLdStInsn = insn32;
855 NEONLdStInsn &= 0xF0FFFFFF;
856 NEONLdStInsn |= 0x04000000;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]857 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
858 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]859 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]860 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]861 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]862 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]863 }
864 }
865
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]866 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]867 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]868 uint32_t NEONDataInsn = insn32;
869 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
870 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
871 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]872 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
873 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]874 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]875 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]876 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]877 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]878 }
879 }
880
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]881 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]882 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]883}
884
885
886extern "C" void LLVMInitializeARMDisassembler() {
887 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
888 createARMDisassembler);
889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
890 createThumbDisassembler);
891}
892
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]893static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]894 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
895 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
896 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
897 ARM::R12, ARM::SP, ARM::LR, ARM::PC
898};
899
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]900static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]901 uint64_t Address, const void *Decoder) {
902 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]903 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]904
905 unsigned Register = GPRDecoderTable[RegNo];
906 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]907 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908}
909
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]910static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]911DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]912 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]913 DecodeStatus S = MCDisassembler::Success;
914
915 if (RegNo == 15)
916 S = MCDisassembler::SoftFail;
917
918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
919
920 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]921}
922
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]923static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]924 uint64_t Address, const void *Decoder) {
925 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]926 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
928}
929
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]930static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]931 uint64_t Address, const void *Decoder) {
932 unsigned Register = 0;
933 switch (RegNo) {
934 case 0:
935 Register = ARM::R0;
936 break;
937 case 1:
938 Register = ARM::R1;
939 break;
940 case 2:
941 Register = ARM::R2;
942 break;
943 case 3:
944 Register = ARM::R3;
945 break;
946 case 9:
947 Register = ARM::R9;
948 break;
949 case 12:
950 Register = ARM::R12;
951 break;
952 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]953 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]954 }
955
956 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]957 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958}
959
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]960static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]961 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
964}
965
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]966static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
968 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
969 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
970 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
971 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
972 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
973 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
974 ARM::S28, ARM::S29, ARM::S30, ARM::S31
975};
976
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]977static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978 uint64_t Address, const void *Decoder) {
979 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]980 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]981
982 unsigned Register = SPRDecoderTable[RegNo];
983 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]984 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]985}
986
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]987static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]988 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
989 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
990 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
991 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
992 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
993 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
994 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
995 ARM::D28, ARM::D29, ARM::D30, ARM::D31
996};
997
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]998static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999 uint64_t Address, const void *Decoder) {
1000 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1001 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002
1003 unsigned Register = DPRDecoderTable[RegNo];
1004 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1005 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1006}
1007
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1008static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1009 uint64_t Address, const void *Decoder) {
1010 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1011 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1013}
1014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1015static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1016DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1017 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1018 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1019 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1021}
1022
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1023static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1028};
1029
1030
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1031static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1032 uint64_t Address, const void *Decoder) {
1033 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1034 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1035 RegNo >>= 1;
1036
1037 unsigned Register = QPRDecoderTable[RegNo];
1038 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1039 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1040}
1041
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1042static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1048 ARM::Q15
1049};
1050
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1051static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1052 uint64_t Address, const void *Decoder) {
1053 if (RegNo > 30)
1054 return MCDisassembler::Fail;
1055
1056 unsigned Register = DPairDecoderTable[RegNo];
1057 Inst.addOperand(MCOperand::CreateReg(Register));
1058 return MCDisassembler::Success;
1059}
1060
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1061static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1069 ARM::D28_D30, ARM::D29_D31
1070};
1071
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1072static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1073 unsigned RegNo,
1074 uint64_t Address,
1075 const void *Decoder) {
1076 if (RegNo > 29)
1077 return MCDisassembler::Fail;
1078
1079 unsigned Register = DPairSpacedDecoderTable[RegNo];
1080 Inst.addOperand(MCOperand::CreateReg(Register));
1081 return MCDisassembler::Success;
1082}
1083
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1084static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1085 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1086 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1087 // AL predicate is not allowed on Thumb1 branches.
1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1089 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1090 Inst.addOperand(MCOperand::CreateImm(Val));
1091 if (Val == ARMCC::AL) {
1092 Inst.addOperand(MCOperand::CreateReg(0));
1093 } else
1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1095 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1096}
1097
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1098static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1099 uint64_t Address, const void *Decoder) {
1100 if (Val)
1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1102 else
1103 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1104 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1105}
1106
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1107static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1108 uint64_t Address, const void *Decoder) {
1109 uint32_t imm = Val & 0xFF;
1110 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1113 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1114}
1115
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1116static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1117 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1118 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1119
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1120 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1121 unsigned type = fieldFromInstruction(Val, 5, 2);
1122 unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1123
1124 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1126 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1127
1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1129 switch (type) {
1130 case 0:
1131 Shift = ARM_AM::lsl;
1132 break;
1133 case 1:
1134 Shift = ARM_AM::lsr;
1135 break;
1136 case 2:
1137 Shift = ARM_AM::asr;
1138 break;
1139 case 3:
1140 Shift = ARM_AM::ror;
1141 break;
1142 }
1143
1144 if (Shift == ARM_AM::ror && imm == 0)
1145 Shift = ARM_AM::rrx;
1146
1147 unsigned Op = Shift | (imm << 3);
1148 Inst.addOperand(MCOperand::CreateImm(Op));
1149
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1150 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1151}
1152
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1153static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1154 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1155 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1156
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1157 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1158 unsigned type = fieldFromInstruction(Val, 5, 2);
1159 unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1160
1161 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1163 return MCDisassembler::Fail;
1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1165 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1166
1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1168 switch (type) {
1169 case 0:
1170 Shift = ARM_AM::lsl;
1171 break;
1172 case 1:
1173 Shift = ARM_AM::lsr;
1174 break;
1175 case 2:
1176 Shift = ARM_AM::asr;
1177 break;
1178 case 3:
1179 Shift = ARM_AM::ror;
1180 break;
1181 }
1182
1183 Inst.addOperand(MCOperand::CreateImm(Shift));
1184
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1185 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1186}
1187
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1188static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1189 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1190 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1191
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1192 bool writebackLoad = false;
1193 unsigned writebackReg = 0;
1194 switch (Inst.getOpcode()) {
1195 default:
1196 break;
1197 case ARM::LDMIA_UPD:
1198 case ARM::LDMDB_UPD:
1199 case ARM::LDMIB_UPD:
1200 case ARM::LDMDA_UPD:
1201 case ARM::t2LDMIA_UPD:
1202 case ARM::t2LDMDB_UPD:
1203 writebackLoad = true;
1204 writebackReg = Inst.getOperand(0).getReg();
1205 break;
1206 }
1207
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1208 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1210 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1211 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1213 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1214 // Writeback not allowed if Rn is in the target list.
1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1216 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1217 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1218 }
1219
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1220 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1221}
1222
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1223static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1224 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1225 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1226
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1227 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1228 unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1231 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1232 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1234 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1235 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1236
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1237 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238}
1239
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1240static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1241 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1242 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1243
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1244 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1245 unsigned regs = fieldFromInstruction(Val, 0, 8);
Silviu Barangab422d0b2012-05-03 16:38:40 +0000[diff] [blame]1246
1247 regs = regs >> 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1248
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1249 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1250 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1251 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1252 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1253 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1254 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1256 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1257}
1258
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1259static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1260 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1261 // This operand encodes a mask of contiguous zeros between a specified MSB
1262 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1263 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1264 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1265 // create the final mask.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1266 unsigned msb = fieldFromInstruction(Val, 5, 5);
1267 unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1268
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1269 DecodeStatus S = MCDisassembler::Success;
Kevin Enderby1c830932012-11-29 23:47:11 +0000[diff] [blame]1270 if (lsb > msb) {
1271 Check(S, MCDisassembler::SoftFail);
1272 // The check above will cause the warning for the "potentially undefined
1273 // instruction encoding" but we can't build a bad MCOperand value here
1274 // with a lsb > msb or else printing the MCInst will cause a crash.
1275 lsb = msb;
1276 }
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1277
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1278 uint32_t msb_mask = 0xFFFFFFFF;
1279 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1280 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1281
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1282 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1283 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1284}
1285
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1286static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1287 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1288 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1289
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1290 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1291 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1292 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1293 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1294 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1295 unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1296
1297 switch (Inst.getOpcode()) {
1298 case ARM::LDC_OFFSET:
1299 case ARM::LDC_PRE:
1300 case ARM::LDC_POST:
1301 case ARM::LDC_OPTION:
1302 case ARM::LDCL_OFFSET:
1303 case ARM::LDCL_PRE:
1304 case ARM::LDCL_POST:
1305 case ARM::LDCL_OPTION:
1306 case ARM::STC_OFFSET:
1307 case ARM::STC_PRE:
1308 case ARM::STC_POST:
1309 case ARM::STC_OPTION:
1310 case ARM::STCL_OFFSET:
1311 case ARM::STCL_PRE:
1312 case ARM::STCL_POST:
1313 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1314 case ARM::t2LDC_OFFSET:
1315 case ARM::t2LDC_PRE:
1316 case ARM::t2LDC_POST:
1317 case ARM::t2LDC_OPTION:
1318 case ARM::t2LDCL_OFFSET:
1319 case ARM::t2LDCL_PRE:
1320 case ARM::t2LDCL_POST:
1321 case ARM::t2LDCL_OPTION:
1322 case ARM::t2STC_OFFSET:
1323 case ARM::t2STC_PRE:
1324 case ARM::t2STC_POST:
1325 case ARM::t2STC_OPTION:
1326 case ARM::t2STCL_OFFSET:
1327 case ARM::t2STCL_PRE:
1328 case ARM::t2STCL_POST:
1329 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1330 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1331 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1332 break;
1333 default:
1334 break;
1335 }
1336
1337 Inst.addOperand(MCOperand::CreateImm(coproc));
1338 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1340 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1341
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1342 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1343 case ARM::t2LDC2_OFFSET:
1344 case ARM::t2LDC2L_OFFSET:
1345 case ARM::t2LDC2_PRE:
1346 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1347 case ARM::t2STC2_OFFSET:
1348 case ARM::t2STC2L_OFFSET:
1349 case ARM::t2STC2_PRE:
1350 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1351 case ARM::LDC2_OFFSET:
1352 case ARM::LDC2L_OFFSET:
1353 case ARM::LDC2_PRE:
1354 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1355 case ARM::STC2_OFFSET:
1356 case ARM::STC2L_OFFSET:
1357 case ARM::STC2_PRE:
1358 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1359 case ARM::t2LDC_OFFSET:
1360 case ARM::t2LDCL_OFFSET:
1361 case ARM::t2LDC_PRE:
1362 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1363 case ARM::t2STC_OFFSET:
1364 case ARM::t2STCL_OFFSET:
1365 case ARM::t2STC_PRE:
1366 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1367 case ARM::LDC_OFFSET:
1368 case ARM::LDCL_OFFSET:
1369 case ARM::LDC_PRE:
1370 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1371 case ARM::STC_OFFSET:
1372 case ARM::STCL_OFFSET:
1373 case ARM::STC_PRE:
1374 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1375 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1376 Inst.addOperand(MCOperand::CreateImm(imm));
1377 break;
1378 case ARM::t2LDC2_POST:
1379 case ARM::t2LDC2L_POST:
1380 case ARM::t2STC2_POST:
1381 case ARM::t2STC2L_POST:
1382 case ARM::LDC2_POST:
1383 case ARM::LDC2L_POST:
1384 case ARM::STC2_POST:
1385 case ARM::STC2L_POST:
1386 case ARM::t2LDC_POST:
1387 case ARM::t2LDCL_POST:
1388 case ARM::t2STC_POST:
1389 case ARM::t2STCL_POST:
1390 case ARM::LDC_POST:
1391 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1392 case ARM::STC_POST:
1393 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1394 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1395 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1396 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1397 // The 'option' variant doesn't encode 'U' in the immediate since
1398 // the immediate is unsigned [0,255].
1399 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1400 break;
1401 }
1402
1403 switch (Inst.getOpcode()) {
1404 case ARM::LDC_OFFSET:
1405 case ARM::LDC_PRE:
1406 case ARM::LDC_POST:
1407 case ARM::LDC_OPTION:
1408 case ARM::LDCL_OFFSET:
1409 case ARM::LDCL_PRE:
1410 case ARM::LDCL_POST:
1411 case ARM::LDCL_OPTION:
1412 case ARM::STC_OFFSET:
1413 case ARM::STC_PRE:
1414 case ARM::STC_POST:
1415 case ARM::STC_OPTION:
1416 case ARM::STCL_OFFSET:
1417 case ARM::STCL_PRE:
1418 case ARM::STCL_POST:
1419 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1420 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1421 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1422 break;
1423 default:
1424 break;
1425 }
1426
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1427 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1428}
1429
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1430static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1431DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1432 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1433 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1434
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1435 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1436 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1437 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1438 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1439 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1440 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1441 unsigned P = fieldFromInstruction(Insn, 24, 1);
1442 unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1443
1444 // On stores, the writeback operand precedes Rt.
1445 switch (Inst.getOpcode()) {
1446 case ARM::STR_POST_IMM:
1447 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1448 case ARM::STRB_POST_IMM:
1449 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1450 case ARM::STRT_POST_REG:
1451 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1452 case ARM::STRBT_POST_REG:
1453 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1455 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1456 break;
1457 default:
1458 break;
1459 }
1460
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1462 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1463
1464 // On loads, the writeback operand comes after Rt.
1465 switch (Inst.getOpcode()) {
1466 case ARM::LDR_POST_IMM:
1467 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1468 case ARM::LDRB_POST_IMM:
1469 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1470 case ARM::LDRBT_POST_REG:
1471 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1472 case ARM::LDRT_POST_REG:
1473 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1475 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1476 break;
1477 default:
1478 break;
1479 }
1480
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1482 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1483
1484 ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1485 if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1486 Op = ARM_AM::sub;
1487
1488 bool writeback = (P == 0) || (W == 1);
1489 unsigned idx_mode = 0;
1490 if (P && writeback)
1491 idx_mode = ARMII::IndexModePre;
1492 else if (!P && writeback)
1493 idx_mode = ARMII::IndexModePost;
1494
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1495 if (writeback && (Rn == 15 || Rn == Rt))
1496 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1497
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1498 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1499 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1500 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1501 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1502 switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1503 case 0:
1504 Opc = ARM_AM::lsl;
1505 break;
1506 case 1:
1507 Opc = ARM_AM::lsr;
1508 break;
1509 case 2:
1510 Opc = ARM_AM::asr;
1511 break;
1512 case 3:
1513 Opc = ARM_AM::ror;
1514 break;
1515 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1516 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1517 }
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1518 unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover93c7c442012-09-22 11:18:12 +0000[diff] [blame]1519 if (Opc == ARM_AM::ror && amt == 0)
1520 Opc = ARM_AM::rrx;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1521 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1522
1523 Inst.addOperand(MCOperand::CreateImm(imm));
1524 } else {
1525 Inst.addOperand(MCOperand::CreateReg(0));
1526 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1527 Inst.addOperand(MCOperand::CreateImm(tmp));
1528 }
1529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1530 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1531 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1532
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1533 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1534}
1535
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1536static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1537 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1538 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1539
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1540 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1541 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1542 unsigned type = fieldFromInstruction(Val, 5, 2);
1543 unsigned imm = fieldFromInstruction(Val, 7, 5);
1544 unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1545
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1546 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1547 switch (type) {
1548 case 0:
1549 ShOp = ARM_AM::lsl;
1550 break;
1551 case 1:
1552 ShOp = ARM_AM::lsr;
1553 break;
1554 case 2:
1555 ShOp = ARM_AM::asr;
1556 break;
1557 case 3:
1558 ShOp = ARM_AM::ror;
1559 break;
1560 }
1561
Tim Northover93c7c442012-09-22 11:18:12 +0000[diff] [blame]1562 if (ShOp == ARM_AM::ror && imm == 0)
1563 ShOp = ARM_AM::rrx;
1564
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1566 return MCDisassembler::Fail;
1567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1568 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1569 unsigned shift;
1570 if (U)
1571 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1572 else
1573 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1574 Inst.addOperand(MCOperand::CreateImm(shift));
1575
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1576 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1577}
1578
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1579static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1580DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1581 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1582 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1583
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1584 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1585 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1586 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1587 unsigned type = fieldFromInstruction(Insn, 22, 1);
1588 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1589 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1590 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1591 unsigned W = fieldFromInstruction(Insn, 21, 1);
1592 unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1593 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1594
1595 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1596
1597 // For {LD,ST}RD, Rt must be even, else undefined.
1598 switch (Inst.getOpcode()) {
1599 case ARM::STRD:
1600 case ARM::STRD_PRE:
1601 case ARM::STRD_POST:
1602 case ARM::LDRD:
1603 case ARM::LDRD_PRE:
1604 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1605 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1606 break;
1607 default:
1608 break;
1609 }
1610 switch (Inst.getOpcode()) {
1611 case ARM::STRD:
1612 case ARM::STRD_PRE:
1613 case ARM::STRD_POST:
1614 if (P == 0 && W == 1)
1615 S = MCDisassembler::SoftFail;
1616
1617 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1618 S = MCDisassembler::SoftFail;
1619 if (type && Rm == 15)
1620 S = MCDisassembler::SoftFail;
1621 if (Rt2 == 15)
1622 S = MCDisassembler::SoftFail;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1623 if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1624 S = MCDisassembler::SoftFail;
1625 break;
1626 case ARM::STRH:
1627 case ARM::STRH_PRE:
1628 case ARM::STRH_POST:
1629 if (Rt == 15)
1630 S = MCDisassembler::SoftFail;
1631 if (writeback && (Rn == 15 || Rn == Rt))
1632 S = MCDisassembler::SoftFail;
1633 if (!type && Rm == 15)
1634 S = MCDisassembler::SoftFail;
1635 break;
1636 case ARM::LDRD:
1637 case ARM::LDRD_PRE:
1638 case ARM::LDRD_POST:
1639 if (type && Rn == 15){
1640 if (Rt2 == 15)
1641 S = MCDisassembler::SoftFail;
1642 break;
1643 }
1644 if (P == 0 && W == 1)
1645 S = MCDisassembler::SoftFail;
1646 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1647 S = MCDisassembler::SoftFail;
1648 if (!type && writeback && Rn == 15)
1649 S = MCDisassembler::SoftFail;
1650 if (writeback && (Rn == Rt || Rn == Rt2))
1651 S = MCDisassembler::SoftFail;
1652 break;
1653 case ARM::LDRH:
1654 case ARM::LDRH_PRE:
1655 case ARM::LDRH_POST:
1656 if (type && Rn == 15){
1657 if (Rt == 15)
1658 S = MCDisassembler::SoftFail;
1659 break;
1660 }
1661 if (Rt == 15)
1662 S = MCDisassembler::SoftFail;
1663 if (!type && Rm == 15)
1664 S = MCDisassembler::SoftFail;
1665 if (!type && writeback && (Rn == 15 || Rn == Rt))
1666 S = MCDisassembler::SoftFail;
1667 break;
1668 case ARM::LDRSH:
1669 case ARM::LDRSH_PRE:
1670 case ARM::LDRSH_POST:
1671 case ARM::LDRSB:
1672 case ARM::LDRSB_PRE:
1673 case ARM::LDRSB_POST:
1674 if (type && Rn == 15){
1675 if (Rt == 15)
1676 S = MCDisassembler::SoftFail;
1677 break;
1678 }
1679 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1680 S = MCDisassembler::SoftFail;
1681 if (!type && (Rt == 15 || Rm == 15))
1682 S = MCDisassembler::SoftFail;
1683 if (!type && writeback && (Rn == 15 || Rn == Rt))
1684 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1685 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1686 default:
1687 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1688 }
1689
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1690 if (writeback) { // Writeback
1691 if (P)
1692 U |= ARMII::IndexModePre << 9;
1693 else
1694 U |= ARMII::IndexModePost << 9;
1695
1696 // On stores, the writeback operand precedes Rt.
1697 switch (Inst.getOpcode()) {
1698 case ARM::STRD:
1699 case ARM::STRD_PRE:
1700 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1701 case ARM::STRH:
1702 case ARM::STRH_PRE:
1703 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1705 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1706 break;
1707 default:
1708 break;
1709 }
1710 }
1711
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1713 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1714 switch (Inst.getOpcode()) {
1715 case ARM::STRD:
1716 case ARM::STRD_PRE:
1717 case ARM::STRD_POST:
1718 case ARM::LDRD:
1719 case ARM::LDRD_PRE:
1720 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1722 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1723 break;
1724 default:
1725 break;
1726 }
1727
1728 if (writeback) {
1729 // On loads, the writeback operand comes after Rt.
1730 switch (Inst.getOpcode()) {
1731 case ARM::LDRD:
1732 case ARM::LDRD_PRE:
1733 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1734 case ARM::LDRH:
1735 case ARM::LDRH_PRE:
1736 case ARM::LDRH_POST:
1737 case ARM::LDRSH:
1738 case ARM::LDRSH_PRE:
1739 case ARM::LDRSH_POST:
1740 case ARM::LDRSB:
1741 case ARM::LDRSB_PRE:
1742 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1743 case ARM::LDRHTr:
1744 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1746 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1747 break;
1748 default:
1749 break;
1750 }
1751 }
1752
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1754 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1755
1756 if (type) {
1757 Inst.addOperand(MCOperand::CreateReg(0));
1758 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1759 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1761 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1762 Inst.addOperand(MCOperand::CreateImm(U));
1763 }
1764
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1765 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1766 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1767
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1768 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1769}
1770
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1771static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1772 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1773 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1774
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1775 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1776 unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1777
1778 switch (mode) {
1779 case 0:
1780 mode = ARM_AM::da;
1781 break;
1782 case 1:
1783 mode = ARM_AM::ia;
1784 break;
1785 case 2:
1786 mode = ARM_AM::db;
1787 break;
1788 case 3:
1789 mode = ARM_AM::ib;
1790 break;
1791 }
1792
1793 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1795 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1796
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1797 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1798}
1799
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1800static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1801 unsigned Insn,
1802 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1803 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1804
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1805 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1806 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1807 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1808
1809 if (pred == 0xF) {
1810 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1811 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1812 Inst.setOpcode(ARM::RFEDA);
1813 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1814 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1815 Inst.setOpcode(ARM::RFEDA_UPD);
1816 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1817 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1818 Inst.setOpcode(ARM::RFEDB);
1819 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1820 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1821 Inst.setOpcode(ARM::RFEDB_UPD);
1822 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1823 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1824 Inst.setOpcode(ARM::RFEIA);
1825 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1826 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1827 Inst.setOpcode(ARM::RFEIA_UPD);
1828 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1829 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1830 Inst.setOpcode(ARM::RFEIB);
1831 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1832 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1833 Inst.setOpcode(ARM::RFEIB_UPD);
1834 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1835 case ARM::STMDA:
1836 Inst.setOpcode(ARM::SRSDA);
1837 break;
1838 case ARM::STMDA_UPD:
1839 Inst.setOpcode(ARM::SRSDA_UPD);
1840 break;
1841 case ARM::STMDB:
1842 Inst.setOpcode(ARM::SRSDB);
1843 break;
1844 case ARM::STMDB_UPD:
1845 Inst.setOpcode(ARM::SRSDB_UPD);
1846 break;
1847 case ARM::STMIA:
1848 Inst.setOpcode(ARM::SRSIA);
1849 break;
1850 case ARM::STMIA_UPD:
1851 Inst.setOpcode(ARM::SRSIA_UPD);
1852 break;
1853 case ARM::STMIB:
1854 Inst.setOpcode(ARM::SRSIB);
1855 break;
1856 case ARM::STMIB_UPD:
1857 Inst.setOpcode(ARM::SRSIB_UPD);
1858 break;
1859 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1860 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1861 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1862
1863 // For stores (which become SRS's, the only operand is the mode.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1864 if (fieldFromInstruction(Insn, 20, 1) == 0) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1865 Inst.addOperand(
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1866 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1867 return S;
1868 }
1869
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1870 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1871 }
1872
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1874 return MCDisassembler::Fail;
1875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1876 return MCDisassembler::Fail; // Tied
1877 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1878 return MCDisassembler::Fail;
1879 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1880 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1881
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1882 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1883}
1884
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1885static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1886 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1887 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1888 unsigned M = fieldFromInstruction(Insn, 17, 1);
1889 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1890 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1891
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1892 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1893
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1894 // imod == '01' --> UNPREDICTABLE
1895 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1896 // return failure here. The '01' imod value is unprintable, so there's
1897 // nothing useful we could do even if we returned UNPREDICTABLE.
1898
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1899 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1900
1901 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1902 Inst.setOpcode(ARM::CPS3p);
1903 Inst.addOperand(MCOperand::CreateImm(imod));
1904 Inst.addOperand(MCOperand::CreateImm(iflags));
1905 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1906 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1907 Inst.setOpcode(ARM::CPS2p);
1908 Inst.addOperand(MCOperand::CreateImm(imod));
1909 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1910 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1911 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1912 Inst.setOpcode(ARM::CPS1p);
1913 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1914 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1915 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1916 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1917 Inst.setOpcode(ARM::CPS1p);
1918 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1919 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1920 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1921
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1922 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1923}
1924
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1925static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1926 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1927 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1928 unsigned M = fieldFromInstruction(Insn, 8, 1);
1929 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1930 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1931
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1932 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1933
1934 // imod == '01' --> UNPREDICTABLE
1935 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1936 // return failure here. The '01' imod value is unprintable, so there's
1937 // nothing useful we could do even if we returned UNPREDICTABLE.
1938
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1939 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1940
1941 if (imod && M) {
1942 Inst.setOpcode(ARM::t2CPS3p);
1943 Inst.addOperand(MCOperand::CreateImm(imod));
1944 Inst.addOperand(MCOperand::CreateImm(iflags));
1945 Inst.addOperand(MCOperand::CreateImm(mode));
1946 } else if (imod && !M) {
1947 Inst.setOpcode(ARM::t2CPS2p);
1948 Inst.addOperand(MCOperand::CreateImm(imod));
1949 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1950 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1951 } else if (!imod && M) {
1952 Inst.setOpcode(ARM::t2CPS1p);
1953 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1954 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1955 } else {
1956 // imod == '00' && M == '0' --> UNPREDICTABLE
1957 Inst.setOpcode(ARM::t2CPS1p);
1958 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1959 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1960 }
1961
1962 return S;
1963}
1964
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1965static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1966 uint64_t Address, const void *Decoder) {
1967 DecodeStatus S = MCDisassembler::Success;
1968
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1969 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1970 unsigned imm = 0;
1971
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1972 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1973 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1974 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1975 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1976
1977 if (Inst.getOpcode() == ARM::t2MOVTi16)
1978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1979 return MCDisassembler::Fail;
1980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1981 return MCDisassembler::Fail;
1982
1983 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1984 Inst.addOperand(MCOperand::CreateImm(imm));
1985
1986 return S;
1987}
1988
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1989static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1990 uint64_t Address, const void *Decoder) {
1991 DecodeStatus S = MCDisassembler::Success;
1992
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1993 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1994 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1995 unsigned imm = 0;
1996
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1997 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
1998 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1999
2000 if (Inst.getOpcode() == ARM::MOVTi16)
2001 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2002 return MCDisassembler::Fail;
2003 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2004 return MCDisassembler::Fail;
2005
2006 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2007 Inst.addOperand(MCOperand::CreateImm(imm));
2008
2009 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2010 return MCDisassembler::Fail;
2011
2012 return S;
2013}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]2014
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2015static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2016 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2017 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2018
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2019 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2020 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2021 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2022 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2023 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2024
2025 if (pred == 0xF)
2026 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2027
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2028 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2029 return MCDisassembler::Fail;
2030 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2031 return MCDisassembler::Fail;
2032 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2033 return MCDisassembler::Fail;
2034 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2035 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2036
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2037 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2038 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]2039
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2040 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2041}
2042
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2043static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2044 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2045 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2046
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2047 unsigned add = fieldFromInstruction(Val, 12, 1);
2048 unsigned imm = fieldFromInstruction(Val, 0, 12);
2049 unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2050
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2051 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2052 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2053
2054 if (!add) imm *= -1;
2055 if (imm == 0 && !add) imm = INT32_MIN;
2056 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2057 if (Rn == 15)
2058 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2059
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2060 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2061}
2062
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2063static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2064 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2065 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2066
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2067 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2068 unsigned U = fieldFromInstruction(Val, 8, 1);
2069 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2070
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2072 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2073
2074 if (U)
2075 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2076 else
2077 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2078
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2079 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2080}
2081
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2082static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2083 uint64_t Address, const void *Decoder) {
2084 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2085}
2086
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2087static DecodeStatus
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2088DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2089 uint64_t Address, const void *Decoder) {
Kevin Enderby445ba852012-10-29 23:27:20 +0000[diff] [blame]2090 DecodeStatus Status = MCDisassembler::Success;
2091
2092 // Note the J1 and J2 values are from the encoded instruction. So here
2093 // change them to I1 and I2 values via as documented:
2094 // I1 = NOT(J1 EOR S);
2095 // I2 = NOT(J2 EOR S);
2096 // and build the imm32 with one trailing zero as documented:
2097 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2098 unsigned S = fieldFromInstruction(Insn, 26, 1);
2099 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2100 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2101 unsigned I1 = !(J1 ^ S);
2102 unsigned I2 = !(J2 ^ S);
2103 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2104 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2105 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2106 int imm32 = SignExtend32<24>(tmp << 1);
2107 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2108 true, 4, Inst, Decoder))
Kevin Enderby445ba852012-10-29 23:27:20 +0000[diff] [blame]2109 Inst.addOperand(MCOperand::CreateImm(imm32));
2110
2111 return Status;
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2112}
2113
2114static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2115DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2116 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2117 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2118
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2119 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2120 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2121
2122 if (pred == 0xF) {
2123 Inst.setOpcode(ARM::BLXi);
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2124 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2125 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2126 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2127 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2128 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2129 }
2130
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2131 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2132 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2133 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2134 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2135 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2136
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2137 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2138}
2139
2140
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2141static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2142 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2143 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2144
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2145 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2146 unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2147
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2149 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2150 if (!align)
2151 Inst.addOperand(MCOperand::CreateImm(0));
2152 else
2153 Inst.addOperand(MCOperand::CreateImm(4 << align));
2154
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2155 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2156}
2157
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2158static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2159 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2160 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2161
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2162 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2163 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2164 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2165 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2166 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2167 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2168
2169 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2170 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2171 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2172 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2173 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2174 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2175 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2176 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2177 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2178 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2179 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2180 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2181 return MCDisassembler::Fail;
2182 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2183 case ARM::VLD2b16:
2184 case ARM::VLD2b32:
2185 case ARM::VLD2b8:
2186 case ARM::VLD2b16wb_fixed:
2187 case ARM::VLD2b16wb_register:
2188 case ARM::VLD2b32wb_fixed:
2189 case ARM::VLD2b32wb_register:
2190 case ARM::VLD2b8wb_fixed:
2191 case ARM::VLD2b8wb_register:
2192 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2193 return MCDisassembler::Fail;
2194 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2195 default:
2196 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2197 return MCDisassembler::Fail;
2198 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2199
2200 // Second output register
2201 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2202 case ARM::VLD3d8:
2203 case ARM::VLD3d16:
2204 case ARM::VLD3d32:
2205 case ARM::VLD3d8_UPD:
2206 case ARM::VLD3d16_UPD:
2207 case ARM::VLD3d32_UPD:
2208 case ARM::VLD4d8:
2209 case ARM::VLD4d16:
2210 case ARM::VLD4d32:
2211 case ARM::VLD4d8_UPD:
2212 case ARM::VLD4d16_UPD:
2213 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2215 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2216 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2217 case ARM::VLD3q8:
2218 case ARM::VLD3q16:
2219 case ARM::VLD3q32:
2220 case ARM::VLD3q8_UPD:
2221 case ARM::VLD3q16_UPD:
2222 case ARM::VLD3q32_UPD:
2223 case ARM::VLD4q8:
2224 case ARM::VLD4q16:
2225 case ARM::VLD4q32:
2226 case ARM::VLD4q8_UPD:
2227 case ARM::VLD4q16_UPD:
2228 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2229 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2230 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2231 default:
2232 break;
2233 }
2234
2235 // Third output register
2236 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2237 case ARM::VLD3d8:
2238 case ARM::VLD3d16:
2239 case ARM::VLD3d32:
2240 case ARM::VLD3d8_UPD:
2241 case ARM::VLD3d16_UPD:
2242 case ARM::VLD3d32_UPD:
2243 case ARM::VLD4d8:
2244 case ARM::VLD4d16:
2245 case ARM::VLD4d32:
2246 case ARM::VLD4d8_UPD:
2247 case ARM::VLD4d16_UPD:
2248 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2249 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2250 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2251 break;
2252 case ARM::VLD3q8:
2253 case ARM::VLD3q16:
2254 case ARM::VLD3q32:
2255 case ARM::VLD3q8_UPD:
2256 case ARM::VLD3q16_UPD:
2257 case ARM::VLD3q32_UPD:
2258 case ARM::VLD4q8:
2259 case ARM::VLD4q16:
2260 case ARM::VLD4q32:
2261 case ARM::VLD4q8_UPD:
2262 case ARM::VLD4q16_UPD:
2263 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2264 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2265 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2266 break;
2267 default:
2268 break;
2269 }
2270
2271 // Fourth output register
2272 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2273 case ARM::VLD4d8:
2274 case ARM::VLD4d16:
2275 case ARM::VLD4d32:
2276 case ARM::VLD4d8_UPD:
2277 case ARM::VLD4d16_UPD:
2278 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2279 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2280 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2281 break;
2282 case ARM::VLD4q8:
2283 case ARM::VLD4q16:
2284 case ARM::VLD4q32:
2285 case ARM::VLD4q8_UPD:
2286 case ARM::VLD4q16_UPD:
2287 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2288 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2289 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2290 break;
2291 default:
2292 break;
2293 }
2294
2295 // Writeback operand
2296 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2297 case ARM::VLD1d8wb_fixed:
2298 case ARM::VLD1d16wb_fixed:
2299 case ARM::VLD1d32wb_fixed:
2300 case ARM::VLD1d64wb_fixed:
2301 case ARM::VLD1d8wb_register:
2302 case ARM::VLD1d16wb_register:
2303 case ARM::VLD1d32wb_register:
2304 case ARM::VLD1d64wb_register:
2305 case ARM::VLD1q8wb_fixed:
2306 case ARM::VLD1q16wb_fixed:
2307 case ARM::VLD1q32wb_fixed:
2308 case ARM::VLD1q64wb_fixed:
2309 case ARM::VLD1q8wb_register:
2310 case ARM::VLD1q16wb_register:
2311 case ARM::VLD1q32wb_register:
2312 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2313 case ARM::VLD1d8Twb_fixed:
2314 case ARM::VLD1d8Twb_register:
2315 case ARM::VLD1d16Twb_fixed:
2316 case ARM::VLD1d16Twb_register:
2317 case ARM::VLD1d32Twb_fixed:
2318 case ARM::VLD1d32Twb_register:
2319 case ARM::VLD1d64Twb_fixed:
2320 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2321 case ARM::VLD1d8Qwb_fixed:
2322 case ARM::VLD1d8Qwb_register:
2323 case ARM::VLD1d16Qwb_fixed:
2324 case ARM::VLD1d16Qwb_register:
2325 case ARM::VLD1d32Qwb_fixed:
2326 case ARM::VLD1d32Qwb_register:
2327 case ARM::VLD1d64Qwb_fixed:
2328 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2329 case ARM::VLD2d8wb_fixed:
2330 case ARM::VLD2d16wb_fixed:
2331 case ARM::VLD2d32wb_fixed:
2332 case ARM::VLD2q8wb_fixed:
2333 case ARM::VLD2q16wb_fixed:
2334 case ARM::VLD2q32wb_fixed:
2335 case ARM::VLD2d8wb_register:
2336 case ARM::VLD2d16wb_register:
2337 case ARM::VLD2d32wb_register:
2338 case ARM::VLD2q8wb_register:
2339 case ARM::VLD2q16wb_register:
2340 case ARM::VLD2q32wb_register:
2341 case ARM::VLD2b8wb_fixed:
2342 case ARM::VLD2b16wb_fixed:
2343 case ARM::VLD2b32wb_fixed:
2344 case ARM::VLD2b8wb_register:
2345 case ARM::VLD2b16wb_register:
2346 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2347 Inst.addOperand(MCOperand::CreateImm(0));
2348 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2349 case ARM::VLD3d8_UPD:
2350 case ARM::VLD3d16_UPD:
2351 case ARM::VLD3d32_UPD:
2352 case ARM::VLD3q8_UPD:
2353 case ARM::VLD3q16_UPD:
2354 case ARM::VLD3q32_UPD:
2355 case ARM::VLD4d8_UPD:
2356 case ARM::VLD4d16_UPD:
2357 case ARM::VLD4d32_UPD:
2358 case ARM::VLD4q8_UPD:
2359 case ARM::VLD4q16_UPD:
2360 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2361 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2362 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2363 break;
2364 default:
2365 break;
2366 }
2367
2368 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2369 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2370 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2371
2372 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2373 switch (Inst.getOpcode()) {
2374 default:
2375 // The below have been updated to have explicit am6offset split
2376 // between fixed and register offset. For those instructions not
2377 // yet updated, we need to add an additional reg0 operand for the
2378 // fixed variant.
2379 //
2380 // The fixed offset encodes as Rm == 0xd, so we check for that.
2381 if (Rm == 0xd) {
2382 Inst.addOperand(MCOperand::CreateReg(0));
2383 break;
2384 }
2385 // Fall through to handle the register offset variant.
2386 case ARM::VLD1d8wb_fixed:
2387 case ARM::VLD1d16wb_fixed:
2388 case ARM::VLD1d32wb_fixed:
2389 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2390 case ARM::VLD1d8Twb_fixed:
2391 case ARM::VLD1d16Twb_fixed:
2392 case ARM::VLD1d32Twb_fixed:
2393 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2394 case ARM::VLD1d8Qwb_fixed:
2395 case ARM::VLD1d16Qwb_fixed:
2396 case ARM::VLD1d32Qwb_fixed:
2397 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2398 case ARM::VLD1d8wb_register:
2399 case ARM::VLD1d16wb_register:
2400 case ARM::VLD1d32wb_register:
2401 case ARM::VLD1d64wb_register:
2402 case ARM::VLD1q8wb_fixed:
2403 case ARM::VLD1q16wb_fixed:
2404 case ARM::VLD1q32wb_fixed:
2405 case ARM::VLD1q64wb_fixed:
2406 case ARM::VLD1q8wb_register:
2407 case ARM::VLD1q16wb_register:
2408 case ARM::VLD1q32wb_register:
2409 case ARM::VLD1q64wb_register:
2410 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2411 // variant encodes Rm == 0xf. Anything else is a register offset post-
2412 // increment and we need to add the register operand to the instruction.
2413 if (Rm != 0xD && Rm != 0xF &&
2414 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2415 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2416 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2417 case ARM::VLD2d8wb_fixed:
2418 case ARM::VLD2d16wb_fixed:
2419 case ARM::VLD2d32wb_fixed:
2420 case ARM::VLD2b8wb_fixed:
2421 case ARM::VLD2b16wb_fixed:
2422 case ARM::VLD2b32wb_fixed:
2423 case ARM::VLD2q8wb_fixed:
2424 case ARM::VLD2q16wb_fixed:
2425 case ARM::VLD2q32wb_fixed:
2426 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2427 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2428
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2429 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2430}
2431
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2432static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2433 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2434 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2435
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2436 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2437 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2438 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2439 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2440 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2441 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2442
2443 // Writeback Operand
2444 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2445 case ARM::VST1d8wb_fixed:
2446 case ARM::VST1d16wb_fixed:
2447 case ARM::VST1d32wb_fixed:
2448 case ARM::VST1d64wb_fixed:
2449 case ARM::VST1d8wb_register:
2450 case ARM::VST1d16wb_register:
2451 case ARM::VST1d32wb_register:
2452 case ARM::VST1d64wb_register:
2453 case ARM::VST1q8wb_fixed:
2454 case ARM::VST1q16wb_fixed:
2455 case ARM::VST1q32wb_fixed:
2456 case ARM::VST1q64wb_fixed:
2457 case ARM::VST1q8wb_register:
2458 case ARM::VST1q16wb_register:
2459 case ARM::VST1q32wb_register:
2460 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2461 case ARM::VST1d8Twb_fixed:
2462 case ARM::VST1d16Twb_fixed:
2463 case ARM::VST1d32Twb_fixed:
2464 case ARM::VST1d64Twb_fixed:
2465 case ARM::VST1d8Twb_register:
2466 case ARM::VST1d16Twb_register:
2467 case ARM::VST1d32Twb_register:
2468 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2469 case ARM::VST1d8Qwb_fixed:
2470 case ARM::VST1d16Qwb_fixed:
2471 case ARM::VST1d32Qwb_fixed:
2472 case ARM::VST1d64Qwb_fixed:
2473 case ARM::VST1d8Qwb_register:
2474 case ARM::VST1d16Qwb_register:
2475 case ARM::VST1d32Qwb_register:
2476 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2477 case ARM::VST2d8wb_fixed:
2478 case ARM::VST2d16wb_fixed:
2479 case ARM::VST2d32wb_fixed:
2480 case ARM::VST2d8wb_register:
2481 case ARM::VST2d16wb_register:
2482 case ARM::VST2d32wb_register:
2483 case ARM::VST2q8wb_fixed:
2484 case ARM::VST2q16wb_fixed:
2485 case ARM::VST2q32wb_fixed:
2486 case ARM::VST2q8wb_register:
2487 case ARM::VST2q16wb_register:
2488 case ARM::VST2q32wb_register:
2489 case ARM::VST2b8wb_fixed:
2490 case ARM::VST2b16wb_fixed:
2491 case ARM::VST2b32wb_fixed:
2492 case ARM::VST2b8wb_register:
2493 case ARM::VST2b16wb_register:
2494 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame]2495 if (Rm == 0xF)
2496 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2497 Inst.addOperand(MCOperand::CreateImm(0));
2498 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2499 case ARM::VST3d8_UPD:
2500 case ARM::VST3d16_UPD:
2501 case ARM::VST3d32_UPD:
2502 case ARM::VST3q8_UPD:
2503 case ARM::VST3q16_UPD:
2504 case ARM::VST3q32_UPD:
2505 case ARM::VST4d8_UPD:
2506 case ARM::VST4d16_UPD:
2507 case ARM::VST4d32_UPD:
2508 case ARM::VST4q8_UPD:
2509 case ARM::VST4q16_UPD:
2510 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2511 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2512 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513 break;
2514 default:
2515 break;
2516 }
2517
2518 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2519 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2520 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521
2522 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2523 switch (Inst.getOpcode()) {
2524 default:
2525 if (Rm == 0xD)
2526 Inst.addOperand(MCOperand::CreateReg(0));
2527 else if (Rm != 0xF) {
2528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2529 return MCDisassembler::Fail;
2530 }
2531 break;
2532 case ARM::VST1d8wb_fixed:
2533 case ARM::VST1d16wb_fixed:
2534 case ARM::VST1d32wb_fixed:
2535 case ARM::VST1d64wb_fixed:
2536 case ARM::VST1q8wb_fixed:
2537 case ARM::VST1q16wb_fixed:
2538 case ARM::VST1q32wb_fixed:
2539 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2540 case ARM::VST1d8Twb_fixed:
2541 case ARM::VST1d16Twb_fixed:
2542 case ARM::VST1d32Twb_fixed:
2543 case ARM::VST1d64Twb_fixed:
2544 case ARM::VST1d8Qwb_fixed:
2545 case ARM::VST1d16Qwb_fixed:
2546 case ARM::VST1d32Qwb_fixed:
2547 case ARM::VST1d64Qwb_fixed:
2548 case ARM::VST2d8wb_fixed:
2549 case ARM::VST2d16wb_fixed:
2550 case ARM::VST2d32wb_fixed:
2551 case ARM::VST2q8wb_fixed:
2552 case ARM::VST2q16wb_fixed:
2553 case ARM::VST2q32wb_fixed:
2554 case ARM::VST2b8wb_fixed:
2555 case ARM::VST2b16wb_fixed:
2556 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2557 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2558 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2559
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2560
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2561 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2562 switch (Inst.getOpcode()) {
2563 case ARM::VST1q16:
2564 case ARM::VST1q32:
2565 case ARM::VST1q64:
2566 case ARM::VST1q8:
2567 case ARM::VST1q16wb_fixed:
2568 case ARM::VST1q16wb_register:
2569 case ARM::VST1q32wb_fixed:
2570 case ARM::VST1q32wb_register:
2571 case ARM::VST1q64wb_fixed:
2572 case ARM::VST1q64wb_register:
2573 case ARM::VST1q8wb_fixed:
2574 case ARM::VST1q8wb_register:
2575 case ARM::VST2d16:
2576 case ARM::VST2d32:
2577 case ARM::VST2d8:
2578 case ARM::VST2d16wb_fixed:
2579 case ARM::VST2d16wb_register:
2580 case ARM::VST2d32wb_fixed:
2581 case ARM::VST2d32wb_register:
2582 case ARM::VST2d8wb_fixed:
2583 case ARM::VST2d8wb_register:
2584 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2585 return MCDisassembler::Fail;
2586 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2587 case ARM::VST2b16:
2588 case ARM::VST2b32:
2589 case ARM::VST2b8:
2590 case ARM::VST2b16wb_fixed:
2591 case ARM::VST2b16wb_register:
2592 case ARM::VST2b32wb_fixed:
2593 case ARM::VST2b32wb_register:
2594 case ARM::VST2b8wb_fixed:
2595 case ARM::VST2b8wb_register:
2596 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2597 return MCDisassembler::Fail;
2598 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2599 default:
2600 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2601 return MCDisassembler::Fail;
2602 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2603
2604 // Second input register
2605 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606 case ARM::VST3d8:
2607 case ARM::VST3d16:
2608 case ARM::VST3d32:
2609 case ARM::VST3d8_UPD:
2610 case ARM::VST3d16_UPD:
2611 case ARM::VST3d32_UPD:
2612 case ARM::VST4d8:
2613 case ARM::VST4d16:
2614 case ARM::VST4d32:
2615 case ARM::VST4d8_UPD:
2616 case ARM::VST4d16_UPD:
2617 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2618 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2619 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2620 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2621 case ARM::VST3q8:
2622 case ARM::VST3q16:
2623 case ARM::VST3q32:
2624 case ARM::VST3q8_UPD:
2625 case ARM::VST3q16_UPD:
2626 case ARM::VST3q32_UPD:
2627 case ARM::VST4q8:
2628 case ARM::VST4q16:
2629 case ARM::VST4q32:
2630 case ARM::VST4q8_UPD:
2631 case ARM::VST4q16_UPD:
2632 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2633 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2634 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2635 break;
2636 default:
2637 break;
2638 }
2639
2640 // Third input register
2641 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2642 case ARM::VST3d8:
2643 case ARM::VST3d16:
2644 case ARM::VST3d32:
2645 case ARM::VST3d8_UPD:
2646 case ARM::VST3d16_UPD:
2647 case ARM::VST3d32_UPD:
2648 case ARM::VST4d8:
2649 case ARM::VST4d16:
2650 case ARM::VST4d32:
2651 case ARM::VST4d8_UPD:
2652 case ARM::VST4d16_UPD:
2653 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2654 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2655 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2656 break;
2657 case ARM::VST3q8:
2658 case ARM::VST3q16:
2659 case ARM::VST3q32:
2660 case ARM::VST3q8_UPD:
2661 case ARM::VST3q16_UPD:
2662 case ARM::VST3q32_UPD:
2663 case ARM::VST4q8:
2664 case ARM::VST4q16:
2665 case ARM::VST4q32:
2666 case ARM::VST4q8_UPD:
2667 case ARM::VST4q16_UPD:
2668 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2669 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2670 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2671 break;
2672 default:
2673 break;
2674 }
2675
2676 // Fourth input register
2677 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2678 case ARM::VST4d8:
2679 case ARM::VST4d16:
2680 case ARM::VST4d32:
2681 case ARM::VST4d8_UPD:
2682 case ARM::VST4d16_UPD:
2683 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2684 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2685 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2686 break;
2687 case ARM::VST4q8:
2688 case ARM::VST4q16:
2689 case ARM::VST4q32:
2690 case ARM::VST4q8_UPD:
2691 case ARM::VST4q16_UPD:
2692 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2693 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2694 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2695 break;
2696 default:
2697 break;
2698 }
2699
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2700 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2701}
2702
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2703static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2704 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2705 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2706
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2707 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2708 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2709 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2710 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2711 unsigned align = fieldFromInstruction(Insn, 4, 1);
2712 unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2713
Tim Northover24b9f252012-09-06 15:27:12 +0000[diff] [blame]2714 if (size == 0 && align == 1)
2715 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2716 align *= (1 << size);
2717
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2718 switch (Inst.getOpcode()) {
2719 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2720 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2721 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2722 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2723 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2724 return MCDisassembler::Fail;
2725 break;
2726 default:
2727 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2728 return MCDisassembler::Fail;
2729 break;
2730 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2731 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2733 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2734 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2735
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2737 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2738 Inst.addOperand(MCOperand::CreateImm(align));
2739
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2740 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2741 // variant encodes Rm == 0xf. Anything else is a register offset post-
2742 // increment and we need to add the register operand to the instruction.
2743 if (Rm != 0xD && Rm != 0xF &&
2744 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2745 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2746
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2747 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2748}
2749
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2750static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2751 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2752 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2753
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2754 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2755 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2756 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2757 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2758 unsigned align = fieldFromInstruction(Insn, 4, 1);
2759 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2760 align *= 2*size;
2761
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2762 switch (Inst.getOpcode()) {
2763 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2764 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2765 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2766 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2767 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2768 return MCDisassembler::Fail;
2769 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2770 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2771 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2772 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2773 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2774 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2775 return MCDisassembler::Fail;
2776 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2777 default:
2778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2779 return MCDisassembler::Fail;
2780 break;
2781 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2782
2783 if (Rm != 0xF)
2784 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2785
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2787 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2788 Inst.addOperand(MCOperand::CreateImm(align));
2789
Kevin Enderbyc5a2a332012-04-17 00:49:27 +0000[diff] [blame]2790 if (Rm != 0xD && Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2792 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2793 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2794
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2795 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2796}
2797
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2798static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2799 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2800 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2801
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2802 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2803 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2804 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2805 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2806 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2807
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2809 return MCDisassembler::Fail;
2810 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2811 return MCDisassembler::Fail;
2812 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2813 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2814 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2816 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2817 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2818
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2820 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2821 Inst.addOperand(MCOperand::CreateImm(0));
2822
2823 if (Rm == 0xD)
2824 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2825 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2827 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2828 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2829
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2830 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2831}
2832
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2833static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2834 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2835 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2836
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2837 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2838 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2839 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2840 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2841 unsigned size = fieldFromInstruction(Insn, 6, 2);
2842 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2843 unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2844
2845 if (size == 0x3) {
Tim Northover24b9f252012-09-06 15:27:12 +0000[diff] [blame]2846 if (align == 0)
2847 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2848 size = 4;
2849 align = 16;
2850 } else {
2851 if (size == 2) {
2852 size = 1 << size;
2853 align *= 8;
2854 } else {
2855 size = 1 << size;
2856 align *= 4*size;
2857 }
2858 }
2859
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2860 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2861 return MCDisassembler::Fail;
2862 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2863 return MCDisassembler::Fail;
2864 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2865 return MCDisassembler::Fail;
2866 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2867 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2868 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2870 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2871 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2872
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2874 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2875 Inst.addOperand(MCOperand::CreateImm(align));
2876
2877 if (Rm == 0xD)
2878 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2879 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2881 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2882 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2883
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2884 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2885}
2886
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2887static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2888DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2889 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2890 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2891
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2892 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2893 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2894 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2895 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2896 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2897 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2898 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2899 unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2901 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2902 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2903 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2904 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2905 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2906 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2907 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2908
2909 Inst.addOperand(MCOperand::CreateImm(imm));
2910
2911 switch (Inst.getOpcode()) {
2912 case ARM::VORRiv4i16:
2913 case ARM::VORRiv2i32:
2914 case ARM::VBICiv4i16:
2915 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2917 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2918 break;
2919 case ARM::VORRiv8i16:
2920 case ARM::VORRiv4i32:
2921 case ARM::VBICiv8i16:
2922 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2923 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2924 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2925 break;
2926 default:
2927 break;
2928 }
2929
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2930 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2931}
2932
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2933static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2934 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2935 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2936
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2937 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2938 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2939 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2940 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2941 unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2942
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2943 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2944 return MCDisassembler::Fail;
2945 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2946 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2947 Inst.addOperand(MCOperand::CreateImm(8 << size));
2948
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2949 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2950}
2951
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2952static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2953 uint64_t Address, const void *Decoder) {
2954 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2955 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2956}
2957
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2958static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2959 uint64_t Address, const void *Decoder) {
2960 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2961 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2962}
2963
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2964static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2965 uint64_t Address, const void *Decoder) {
2966 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2967 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2968}
2969
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2970static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2971 uint64_t Address, const void *Decoder) {
2972 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2973 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2974}
2975
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2976static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2977 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2978 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2979
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2980 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2981 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2982 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2983 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2984 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2985 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2986 unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2987
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2989 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2990 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2991 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2992 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2993 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2994
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2995 switch (Inst.getOpcode()) {
2996 case ARM::VTBL2:
2997 case ARM::VTBX2:
2998 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2999 return MCDisassembler::Fail;
3000 break;
3001 default:
3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3003 return MCDisassembler::Fail;
3004 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3005
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3006 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3007 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3008
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3009 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3010}
3011
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3012static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3013 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3014 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3015
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3016 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3017 unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3018
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3019 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3020 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3021
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3022 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]3023 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3024 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3025 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]3026 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3027 case ARM::tADDrSPi:
3028 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3029 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]3030 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3031
3032 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3033 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3034}
3035
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3036static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3037 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3038 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3039 true, 2, Inst, Decoder))
3040 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3041 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3042}
3043
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3044static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3045 uint64_t Address, const void *Decoder) {
Kevin Enderby3610a152012-05-04 22:09:52 +0000[diff] [blame]3046 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3047 true, 4, Inst, Decoder))
3048 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3049 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3050}
3051
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3052static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3053 uint64_t Address, const void *Decoder) {
Gordon Keiserce888352013-03-28 19:22:28 +0000[diff] [blame]3054 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3055 true, 2, Inst, Decoder))
Gordon Keiserce888352013-03-28 19:22:28 +0000[diff] [blame]3056 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3057 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3058}
3059
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3060static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3061 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3062 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3063
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3064 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3065 unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3066
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3067 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3068 return MCDisassembler::Fail;
3069 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3070 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3071
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3072 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3073}
3074
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3075static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3076 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3077 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3078
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3079 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3080 unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3081
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3082 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3083 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3084 Inst.addOperand(MCOperand::CreateImm(imm));
3085
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3086 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3087}
3088
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3089static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3090 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3091 unsigned imm = Val << 2;
3092
3093 Inst.addOperand(MCOperand::CreateImm(imm));
3094 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3095
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3096 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3097}
3098
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3099static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3100 uint64_t Address, const void *Decoder) {
3101 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3102 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3103
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3104 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3105}
3106
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3107static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3108 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3109 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3110
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3111 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3112 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3113 unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3114
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3115 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3116 return MCDisassembler::Fail;
3117 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3118 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3119 Inst.addOperand(MCOperand::CreateImm(imm));
3120
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3121 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3122}
3123
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3124static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3125 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3126 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3127
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3128 switch (Inst.getOpcode()) {
3129 case ARM::t2PLDs:
3130 case ARM::t2PLDWs:
3131 case ARM::t2PLIs:
3132 break;
3133 default: {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3134 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3135 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3136 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3137 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3138 }
3139
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3140 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3141 if (Rn == 0xF) {
3142 switch (Inst.getOpcode()) {
3143 case ARM::t2LDRBs:
3144 Inst.setOpcode(ARM::t2LDRBpci);
3145 break;
3146 case ARM::t2LDRHs:
3147 Inst.setOpcode(ARM::t2LDRHpci);
3148 break;
3149 case ARM::t2LDRSHs:
3150 Inst.setOpcode(ARM::t2LDRSHpci);
3151 break;
3152 case ARM::t2LDRSBs:
3153 Inst.setOpcode(ARM::t2LDRSBpci);
3154 break;
3155 case ARM::t2PLDs:
3156 Inst.setOpcode(ARM::t2PLDi12);
3157 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3158 break;
3159 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3160 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3161 }
3162
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3163 int imm = fieldFromInstruction(Insn, 0, 12);
3164 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3165 Inst.addOperand(MCOperand::CreateImm(imm));
3166
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3167 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3168 }
3169
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3170 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3171 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3172 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3173 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3174 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3175
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3176 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3177}
3178
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3179static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3180 uint64_t Address, const void *Decoder) {
Jiangning Liufd652df2012-08-02 08:29:50 +0000[diff] [blame]3181 if (Val == 0)
3182 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3183 else {
3184 int imm = Val & 0xFF;
3185
3186 if (!(Val & 0x100)) imm *= -1;
Richard Smith1144af32012-08-24 23:29:28 +0000[diff] [blame]3187 Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liufd652df2012-08-02 08:29:50 +0000[diff] [blame]3188 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3189
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3190 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3191}
3192
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3193static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3194 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3195 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3196
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3197 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3198 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3199
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3201 return MCDisassembler::Fail;
3202 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3203 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3204
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3205 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3206}
3207
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3208static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3209 uint64_t Address, const void *Decoder) {
3210 DecodeStatus S = MCDisassembler::Success;
3211
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3212 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3213 unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3214
3215 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3216 return MCDisassembler::Fail;
3217
3218 Inst.addOperand(MCOperand::CreateImm(imm));
3219
3220 return S;
3221}
3222
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3223static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3224 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3225 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3226 if (Val == 0)
3227 imm = INT32_MIN;
3228 else if (!(Val & 0x100))
3229 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3230 Inst.addOperand(MCOperand::CreateImm(imm));
3231
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3232 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3233}
3234
3235
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3236static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3237 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3238 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3239
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3240 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3241 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3242
3243 // Some instructions always use an additive offset.
3244 switch (Inst.getOpcode()) {
3245 case ARM::t2LDRT:
3246 case ARM::t2LDRBT:
3247 case ARM::t2LDRHT:
3248 case ARM::t2LDRSBT:
3249 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3250 case ARM::t2STRT:
3251 case ARM::t2STRBT:
3252 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3253 imm |= 0x100;
3254 break;
3255 default:
3256 break;
3257 }
3258
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3260 return MCDisassembler::Fail;
3261 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3262 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3263
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3264 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3265}
3266
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3267static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3268 uint64_t Address, const void *Decoder) {
3269 DecodeStatus S = MCDisassembler::Success;
3270
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3271 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3272 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3273 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3274 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3275 addr |= Rn << 9;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3276 unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3277
3278 if (!load) {
3279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3280 return MCDisassembler::Fail;
3281 }
3282
Joe Abbeyb78821d2013-03-26 13:58:53 +0000[diff] [blame]3283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3284 return MCDisassembler::Fail;
3285
3286 if (load) {
3287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3288 return MCDisassembler::Fail;
3289 }
3290
3291 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3292 return MCDisassembler::Fail;
3293
3294 return S;
3295}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3296
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3297static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3298 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3299 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3300
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3301 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3302 unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3303
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3305 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3306 Inst.addOperand(MCOperand::CreateImm(imm));
3307
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3308 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3309}
3310
3311
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3312static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3313 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3314 unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3315
3316 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3317 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3318 Inst.addOperand(MCOperand::CreateImm(imm));
3319
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3320 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3321}
3322
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3323static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3324 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3325 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3326
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3327 if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3328 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3329 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3330
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3332 return MCDisassembler::Fail;
Jim Grosbachbb32f1d2012-04-27 23:51:33 +0000[diff] [blame]3333 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3335 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3336 } else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3337 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3338
3339 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3340 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3342 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3343 }
3344
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3345 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3346}
3347
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3348static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3349 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3350 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3351 unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3352
3353 Inst.addOperand(MCOperand::CreateImm(imod));
3354 Inst.addOperand(MCOperand::CreateImm(flags));
3355
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3356 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3357}
3358
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3359static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3360 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3361 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3362 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3363 unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3364
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3365 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3366 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3367 Inst.addOperand(MCOperand::CreateImm(add));
3368
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3369 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3370}
3371
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3372static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3373 uint64_t Address, const void *Decoder) {
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3374 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3375 // Note only one trailing zero not two. Also the J1 and J2 values are from
3376 // the encoded instruction. So here change to I1 and I2 values via:
3377 // I1 = NOT(J1 EOR S);
3378 // I2 = NOT(J2 EOR S);
3379 // and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3380 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3381 unsigned S = (Val >> 23) & 1;
3382 unsigned J1 = (Val >> 22) & 1;
3383 unsigned J2 = (Val >> 21) & 1;
3384 unsigned I1 = !(J1 ^ S);
3385 unsigned I2 = !(J2 ^ S);
3386 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3387 int imm32 = SignExtend32<25>(tmp << 1);
3388
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3389 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3390 (Address & ~2u) + imm32 + 4,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3391 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3392 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3393 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3394}
3395
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3396static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3397 uint64_t Address, const void *Decoder) {
3398 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3399 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3400
3401 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3402 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3403}
3404
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3405static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3406DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3407 uint64_t Address, const void *Decoder) {
3408 DecodeStatus S = MCDisassembler::Success;
3409
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3410 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3411 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3412
3413 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3415 return MCDisassembler::Fail;
3416 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3417 return MCDisassembler::Fail;
3418 return S;
3419}
3420
3421static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3422DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3423 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3424 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3425
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3426 unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3427 if (pred == 0xE || pred == 0xF) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3428 unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3429 switch (opc) {
3430 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3431 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3432 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3433 Inst.setOpcode(ARM::t2DSB);
3434 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3435 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3436 Inst.setOpcode(ARM::t2DMB);
3437 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3438 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3439 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3440 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3441 }
3442
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3443 unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3444 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3445 }
3446
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3447 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3448 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3449 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3450 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3451 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3452
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3453 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3454 return MCDisassembler::Fail;
3455 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3456 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3457
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3458 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3459}
3460
3461// Decode a shifted immediate operand. These basically consist
3462// of an 8-bit value, and a 4-bit directive that specifies either
3463// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3464static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3465 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3466 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3467 if (ctrl == 0) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3468 unsigned byte = fieldFromInstruction(Val, 8, 2);
3469 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3470 switch (byte) {
3471 case 0:
3472 Inst.addOperand(MCOperand::CreateImm(imm));
3473 break;
3474 case 1:
3475 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3476 break;
3477 case 2:
3478 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3479 break;
3480 case 3:
3481 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3482 (imm << 8) | imm));
3483 break;
3484 }
3485 } else {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3486 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3487 unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3488 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3489 Inst.addOperand(MCOperand::CreateImm(imm));
3490 }
3491
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3492 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3493}
3494
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3495static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3496DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3497 uint64_t Address, const void *Decoder){
Richard Bartonc8f2fcc2012-06-06 09:12:53 +0000[diff] [blame]3498 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3499 true, 2, Inst, Decoder))
Richard Bartonc8f2fcc2012-06-06 09:12:53 +0000[diff] [blame]3500 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3501 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3502}
3503
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3504static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3505 uint64_t Address, const void *Decoder){
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3506 // Val is passed in as S:J1:J2:imm10:imm11
3507 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3508 // the encoded instruction. So here change to I1 and I2 values via:
3509 // I1 = NOT(J1 EOR S);
3510 // I2 = NOT(J2 EOR S);
3511 // and build the imm32 with one trailing zero as documented:
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3512 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3513 unsigned S = (Val >> 23) & 1;
3514 unsigned J1 = (Val >> 22) & 1;
3515 unsigned J2 = (Val >> 21) & 1;
3516 unsigned I1 = !(J1 ^ S);
3517 unsigned I2 = !(J2 ^ S);
3518 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3519 int imm32 = SignExtend32<25>(tmp << 1);
3520
3521 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3522 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3523 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3524 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3525}
3526
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3527static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3528 uint64_t Address, const void *Decoder) {
Jiangning Liuc1b7ca52012-08-02 08:21:27 +0000[diff] [blame]3529 if (Val & ~0xf)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3530 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3531
3532 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3533 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3534}
3535
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3536static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3537 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3538 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3539 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3540 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3541}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3542
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3543static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3544 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3545 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3546
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3547 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3548 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3549 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3550
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3551 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3552
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3554 return MCDisassembler::Fail;
3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3556 return MCDisassembler::Fail;
3557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3558 return MCDisassembler::Fail;
3559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3560 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3561
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3562 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3563}
3564
3565
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3566static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3567 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3568 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3569
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3570 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3571 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3572 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3573 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3574
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3575 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3576 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3577
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3578 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3579 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3580
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3582 return MCDisassembler::Fail;
3583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3584 return MCDisassembler::Fail;
3585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3586 return MCDisassembler::Fail;
3587 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3588 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3589
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3590 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3591}
3592
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3593static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3594 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3595 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3596
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3597 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3598 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3599 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3600 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3601 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3602 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3603
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3604 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3605
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3607 return MCDisassembler::Fail;
3608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3609 return MCDisassembler::Fail;
3610 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3611 return MCDisassembler::Fail;
3612 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3613 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3614
3615 return S;
3616}
3617
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3618static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3619 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3620 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3621
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3622 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3623 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3624 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3625 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3626 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3627 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3628 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3629
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3630 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3631 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3632
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3634 return MCDisassembler::Fail;
3635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3636 return MCDisassembler::Fail;
3637 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3638 return MCDisassembler::Fail;
3639 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3640 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3641
3642 return S;
3643}
3644
3645
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3646static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3647 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3648 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3649
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3650 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3651 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3652 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3653 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3654 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3655 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3656
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3657 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3658
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3660 return MCDisassembler::Fail;
3661 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3662 return MCDisassembler::Fail;
3663 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3664 return MCDisassembler::Fail;
3665 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3666 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3667
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3668 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3669}
3670
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3671static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3672 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3673 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3674
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3675 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3676 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3677 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3678 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3679 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3680 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3681
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3682 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3683
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3685 return MCDisassembler::Fail;
3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3687 return MCDisassembler::Fail;
3688 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3689 return MCDisassembler::Fail;
3690 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3691 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3692
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3693 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3694}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3695
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3696static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3697 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3698 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3699
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3700 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3701 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3702 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3703 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3704 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3705
3706 unsigned align = 0;
3707 unsigned index = 0;
3708 switch (size) {
3709 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3710 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3711 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3712 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3713 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3714 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3715 break;
3716 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3717 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3718 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3719 index = fieldFromInstruction(Insn, 6, 2);
3720 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3721 align = 2;
3722 break;
3723 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3724 if (fieldFromInstruction(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3725 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3726 index = fieldFromInstruction(Insn, 7, 1);
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]3727
3728 switch (fieldFromInstruction(Insn, 4, 2)) {
3729 case 0 :
3730 align = 0; break;
3731 case 3:
3732 align = 4; break;
3733 default:
3734 return MCDisassembler::Fail;
3735 }
3736 break;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3737 }
3738
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3739 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3740 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3741 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3743 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3744 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3746 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3747 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3748 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3749 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3751 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3752 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3753 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3754 }
3755
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3756 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3757 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3758 Inst.addOperand(MCOperand::CreateImm(index));
3759
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3760 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3761}
3762
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3763static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3764 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3765 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3766
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3767 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3768 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3769 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3770 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3771 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3772
3773 unsigned align = 0;
3774 unsigned index = 0;
3775 switch (size) {
3776 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3777 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3778 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3779 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3780 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3781 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3782 break;
3783 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3784 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3785 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3786 index = fieldFromInstruction(Insn, 6, 2);
3787 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3788 align = 2;
3789 break;
3790 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3791 if (fieldFromInstruction(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3792 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3793 index = fieldFromInstruction(Insn, 7, 1);
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]3794
3795 switch (fieldFromInstruction(Insn, 4, 2)) {
3796 case 0:
3797 align = 0; break;
3798 case 3:
3799 align = 4; break;
3800 default:
3801 return MCDisassembler::Fail;
3802 }
3803 break;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3804 }
3805
3806 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3808 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3809 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3811 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3812 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3813 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3814 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3816 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3817 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3818 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3819 }
3820
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3821 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3822 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3823 Inst.addOperand(MCOperand::CreateImm(index));
3824
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3825 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3826}
3827
3828
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3829static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3830 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3831 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3832
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3833 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3834 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3835 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3836 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3837 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3838
3839 unsigned align = 0;
3840 unsigned index = 0;
3841 unsigned inc = 1;
3842 switch (size) {
3843 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3844 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3845 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3846 index = fieldFromInstruction(Insn, 5, 3);
3847 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3848 align = 2;
3849 break;
3850 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3851 index = fieldFromInstruction(Insn, 6, 2);
3852 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3853 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3854 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3855 inc = 2;
3856 break;
3857 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3858 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3859 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3860 index = fieldFromInstruction(Insn, 7, 1);
3861 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3862 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3863 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3864 inc = 2;
3865 break;
3866 }
3867
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3869 return MCDisassembler::Fail;
3870 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3871 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3872 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3874 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3875 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3877 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3878 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3879 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3880 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3882 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3883 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3884 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3885 }
3886
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3888 return MCDisassembler::Fail;
3889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3890 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3891 Inst.addOperand(MCOperand::CreateImm(index));
3892
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3893 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3894}
3895
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3896static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3897 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3898 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3899
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3900 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3901 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3902 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3903 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3904 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3905
3906 unsigned align = 0;
3907 unsigned index = 0;
3908 unsigned inc = 1;
3909 switch (size) {
3910 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3911 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3912 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3913 index = fieldFromInstruction(Insn, 5, 3);
3914 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3915 align = 2;
3916 break;
3917 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3918 index = fieldFromInstruction(Insn, 6, 2);
3919 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3920 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3921 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3922 inc = 2;
3923 break;
3924 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3925 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3926 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3927 index = fieldFromInstruction(Insn, 7, 1);
3928 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3929 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3930 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3931 inc = 2;
3932 break;
3933 }
3934
3935 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3937 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3938 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3940 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3941 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3942 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3943 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3945 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3946 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3947 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3948 }
3949
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3950 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3951 return MCDisassembler::Fail;
3952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3953 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3954 Inst.addOperand(MCOperand::CreateImm(index));
3955
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3956 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3957}
3958
3959
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3960static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3961 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3962 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3963
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3964 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3965 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3966 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3967 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3968 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3969
3970 unsigned align = 0;
3971 unsigned index = 0;
3972 unsigned inc = 1;
3973 switch (size) {
3974 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3975 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3976 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3977 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3978 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3979 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3980 break;
3981 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3982 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3983 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3984 index = fieldFromInstruction(Insn, 6, 2);
3985 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3986 inc = 2;
3987 break;
3988 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3989 if (fieldFromInstruction(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3990 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3991 index = fieldFromInstruction(Insn, 7, 1);
3992 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3993 inc = 2;
3994 break;
3995 }
3996
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3997 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3998 return MCDisassembler::Fail;
3999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4000 return MCDisassembler::Fail;
4001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4002 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4003
4004 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4006 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4007 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4009 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4010 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4011 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4012 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4014 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4015 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4016 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4017 }
4018
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4019 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4020 return MCDisassembler::Fail;
4021 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4022 return MCDisassembler::Fail;
4023 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4024 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4025 Inst.addOperand(MCOperand::CreateImm(index));
4026
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4027 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4028}
4029
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4030static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4031 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4032 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4033
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4034 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4035 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4036 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4037 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4038 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4039
4040 unsigned align = 0;
4041 unsigned index = 0;
4042 unsigned inc = 1;
4043 switch (size) {
4044 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4045 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4046 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4047 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4048 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4049 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4050 break;
4051 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4052 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4053 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4054 index = fieldFromInstruction(Insn, 6, 2);
4055 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4056 inc = 2;
4057 break;
4058 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4059 if (fieldFromInstruction(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4060 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4061 index = fieldFromInstruction(Insn, 7, 1);
4062 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4063 inc = 2;
4064 break;
4065 }
4066
4067 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4068 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4069 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4070 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4072 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4073 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4074 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4075 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4077 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4078 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4079 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4080 }
4081
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4082 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4083 return MCDisassembler::Fail;
4084 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4085 return MCDisassembler::Fail;
4086 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4087 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4088 Inst.addOperand(MCOperand::CreateImm(index));
4089
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4090 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4091}
4092
4093
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4094static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4095 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4096 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4097
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4098 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4099 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4100 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4101 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4102 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4103
4104 unsigned align = 0;
4105 unsigned index = 0;
4106 unsigned inc = 1;
4107 switch (size) {
4108 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4109 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4110 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4111 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4112 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4113 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4114 break;
4115 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4116 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4117 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4118 index = fieldFromInstruction(Insn, 6, 2);
4119 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4120 inc = 2;
4121 break;
4122 case 2:
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]4123 switch (fieldFromInstruction(Insn, 4, 2)) {
4124 case 0:
4125 align = 0; break;
4126 case 3:
4127 return MCDisassembler::Fail;
4128 default:
4129 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4130 }
4131
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4132 index = fieldFromInstruction(Insn, 7, 1);
4133 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4134 inc = 2;
4135 break;
4136 }
4137
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4138 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4139 return MCDisassembler::Fail;
4140 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4141 return MCDisassembler::Fail;
4142 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4143 return MCDisassembler::Fail;
4144 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4145 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4146
4147 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4149 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4150 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4152 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4153 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4154 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4155 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4157 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4158 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4159 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4160 }
4161
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4162 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4163 return MCDisassembler::Fail;
4164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4165 return MCDisassembler::Fail;
4166 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4167 return MCDisassembler::Fail;
4168 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4169 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4170 Inst.addOperand(MCOperand::CreateImm(index));
4171
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4172 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4173}
4174
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4175static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4176 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4177 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4178
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4179 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4180 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4181 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4182 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4183 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4184
4185 unsigned align = 0;
4186 unsigned index = 0;
4187 unsigned inc = 1;
4188 switch (size) {
4189 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4190 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4191 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4192 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4193 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4194 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4195 break;
4196 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4197 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4198 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4199 index = fieldFromInstruction(Insn, 6, 2);
4200 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4201 inc = 2;
4202 break;
4203 case 2:
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]4204 switch (fieldFromInstruction(Insn, 4, 2)) {
4205 case 0:
4206 align = 0; break;
4207 case 3:
4208 return MCDisassembler::Fail;
4209 default:
4210 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4211 }
4212
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4213 index = fieldFromInstruction(Insn, 7, 1);
4214 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4215 inc = 2;
4216 break;
4217 }
4218
4219 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4221 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4222 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4224 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4225 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4226 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4227 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4229 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4230 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4231 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4232 }
4233
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4234 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4235 return MCDisassembler::Fail;
4236 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4237 return MCDisassembler::Fail;
4238 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4239 return MCDisassembler::Fail;
4240 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4241 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4242 Inst.addOperand(MCOperand::CreateImm(index));
4243
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4244 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4245}
4246
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4247static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4248 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4249 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4250 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4251 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4252 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4253 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4254 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4255
4256 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4257 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4258
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4259 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4260 return MCDisassembler::Fail;
4261 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4262 return MCDisassembler::Fail;
4263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4264 return MCDisassembler::Fail;
4265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4266 return MCDisassembler::Fail;
4267 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4268 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4269
4270 return S;
4271}
4272
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4273static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4274 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4275 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4276 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4277 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4278 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4279 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4280 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4281
4282 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4283 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4284
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4286 return MCDisassembler::Fail;
4287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4288 return MCDisassembler::Fail;
4289 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4290 return MCDisassembler::Fail;
4291 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4292 return MCDisassembler::Fail;
4293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4294 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4295
4296 return S;
4297}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4298
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4299static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4300 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4301 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4302 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4303 unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4304
4305 if (pred == 0xF) {
4306 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4307 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4308 }
4309
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]4310 if (mask == 0x0) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4311 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4312 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4313 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4314
4315 Inst.addOperand(MCOperand::CreateImm(pred));
4316 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4317 return S;
4318}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4319
4320static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4321DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4322 uint64_t Address, const void *Decoder) {
4323 DecodeStatus S = MCDisassembler::Success;
4324
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4325 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4326 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4327 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4328 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4329 unsigned W = fieldFromInstruction(Insn, 21, 1);
4330 unsigned U = fieldFromInstruction(Insn, 23, 1);
4331 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4332 bool writeback = (W == 1) | (P == 0);
4333
4334 addr |= (U << 8) | (Rn << 9);
4335
4336 if (writeback && (Rn == Rt || Rn == Rt2))
4337 Check(S, MCDisassembler::SoftFail);
4338 if (Rt == Rt2)
4339 Check(S, MCDisassembler::SoftFail);
4340
4341 // Rt
4342 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4343 return MCDisassembler::Fail;
4344 // Rt2
4345 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4346 return MCDisassembler::Fail;
4347 // Writeback operand
4348 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4349 return MCDisassembler::Fail;
4350 // addr
4351 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4352 return MCDisassembler::Fail;
4353
4354 return S;
4355}
4356
4357static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4358DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4359 uint64_t Address, const void *Decoder) {
4360 DecodeStatus S = MCDisassembler::Success;
4361
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4362 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4363 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4364 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4365 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4366 unsigned W = fieldFromInstruction(Insn, 21, 1);
4367 unsigned U = fieldFromInstruction(Insn, 23, 1);
4368 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4369 bool writeback = (W == 1) | (P == 0);
4370
4371 addr |= (U << 8) | (Rn << 9);
4372
4373 if (writeback && (Rn == Rt || Rn == Rt2))
4374 Check(S, MCDisassembler::SoftFail);
4375
4376 // Writeback operand
4377 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4378 return MCDisassembler::Fail;
4379 // Rt
4380 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4381 return MCDisassembler::Fail;
4382 // Rt2
4383 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4384 return MCDisassembler::Fail;
4385 // addr
4386 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4387 return MCDisassembler::Fail;
4388
4389 return S;
4390}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4391
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4392static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4393 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4394 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4395 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4396 if (sign1 != sign2) return MCDisassembler::Fail;
4397
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4398 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4399 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4400 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4401 Val |= sign1 << 12;
4402 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4403
4404 return MCDisassembler::Success;
4405}
4406
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4407static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4408 uint64_t Address,
4409 const void *Decoder) {
4410 DecodeStatus S = MCDisassembler::Success;
4411
4412 // Shift of "asr #32" is not allowed in Thumb2 mode.
4413 if (Val == 0x20) S = MCDisassembler::SoftFail;
4414 Inst.addOperand(MCOperand::CreateImm(Val));
4415 return S;
4416}
4417
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4418static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4419 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4420 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4421 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4422 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4423 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4424
4425 if (pred == 0xF)
4426 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4427
4428 DecodeStatus S = MCDisassembler::Success;
Silviu Baranga35ee7d22012-04-18 14:18:57 +0000[diff] [blame]4429
4430 if (Rt == Rn || Rn == Rt2)
4431 S = MCDisassembler::SoftFail;
4432
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4433 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4434 return MCDisassembler::Fail;
4435 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4436 return MCDisassembler::Fail;
4437 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4438 return MCDisassembler::Fail;
4439 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4440 return MCDisassembler::Fail;
4441
4442 return S;
4443}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4444
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4445static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4446 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4447 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4448 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4449 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4450 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4451 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4452 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4453
4454 DecodeStatus S = MCDisassembler::Success;
4455
4456 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4457 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4458 Inst.setOpcode(ARM::VMOVv2f32);
4459 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4460 }
4461
4462 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4463
4464 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4465 return MCDisassembler::Fail;
4466 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4467 return MCDisassembler::Fail;
4468 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4469
4470 return S;
4471}
4472
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4473static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4474 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4475 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4476 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4477 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4478 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4479 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4480 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4481
4482 DecodeStatus S = MCDisassembler::Success;
4483
4484 // VMOVv4f32 is ambiguous with these decodings.
4485 if (!(imm & 0x38) && cmode == 0xF) {
4486 Inst.setOpcode(ARM::VMOVv4f32);
4487 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4488 }
4489
4490 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4491
4492 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4493 return MCDisassembler::Fail;
4494 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4495 return MCDisassembler::Fail;
4496 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4497
4498 return S;
4499}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4500
Quentin Colombet7c4cf032013-04-17 18:46:12 +0000[diff] [blame^]4501static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
4502 const void *Decoder)
4503{
4504 unsigned Imm = fieldFromInstruction(Insn, 0, 3);
4505 if (Imm > 4) return MCDisassembler::Fail;
4506 Inst.addOperand(MCOperand::CreateImm(Imm));
4507 return MCDisassembler::Success;
4508}
4509
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4510static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4511 uint64_t Address, const void *Decoder) {
4512 DecodeStatus S = MCDisassembler::Success;
4513
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4514 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4515 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4516 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4517 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4518 unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4519
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4520 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4521 S = MCDisassembler::SoftFail;
4522
4523 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4524 return MCDisassembler::Fail;
4525 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4526 return MCDisassembler::Fail;
4527 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4528 return MCDisassembler::Fail;
4529 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4530 return MCDisassembler::Fail;
4531 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4532 return MCDisassembler::Fail;
4533
4534 return S;
4535}
4536
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4537static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4538 uint64_t Address, const void *Decoder) {
4539
4540 DecodeStatus S = MCDisassembler::Success;
4541
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4542 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4543 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4544 unsigned cop = fieldFromInstruction(Val, 8, 4);
4545 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4546 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4547
4548 if ((cop & ~0x1) == 0xa)
4549 return MCDisassembler::Fail;
4550
4551 if (Rt == Rt2)
4552 S = MCDisassembler::SoftFail;
4553
4554 Inst.addOperand(MCOperand::CreateImm(cop));
4555 Inst.addOperand(MCOperand::CreateImm(opc1));
4556 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4557 return MCDisassembler::Fail;
4558 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4559 return MCDisassembler::Fail;
4560 Inst.addOperand(MCOperand::CreateImm(CRm));
4561
4562 return S;
4563}
4564