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gerrit-public.fairphone.software / platform / external / llvm / 7f739bee261debdf56bd89ac922b57eca53e91dc / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: dea38bf00a36d831149086c568f434e2ef241ba5 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]50 raw_ostream &vStream,
51 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]52
53 /// getEDInfo - See MCDisassembler.
54 EDInstInfo *getEDInfo() const;
55private:
56};
57
58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59class ThumbDisassembler : public MCDisassembler {
60public:
61 /// Constructor - Initializes the disassembler.
62 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]65 }
66
67 ~ThumbDisassembler() {
68 }
69
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
72 uint64_t &size,
73 const MemoryObject &region,
74 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]75 raw_ostream &vStream,
76 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]77
78 /// getEDInfo - See MCDisassembler.
79 EDInstInfo *getEDInfo() const;
80private:
81 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]82 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]83 void UpdateThumbVFPPredicate(MCInst&) const;
84};
85}
86
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]87static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]88 switch (In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
91 return true;
92 case MCDisassembler::SoftFail:
93 Out = In;
94 return true;
95 case MCDisassembler::Fail:
96 Out = In;
97 return false;
98 }
99 return false;
100}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]101
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]102
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103// Forward declare these because the autogenerated code will reference them.
104// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]106 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]107static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]122static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]126static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]128
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]139static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]140 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]146static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]147 unsigned Insn,
148 uint64_t Address,
149 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]156static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
158
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]159static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 unsigned Insn,
161 uint64_t Adddress,
162 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]247static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]248 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]274static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame^]290static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]298static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]300static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]302static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
303 uint64_t Address, const void *Decoder);
304static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
305 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]306static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]308static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
309 uint64_t Address, const void *Decoder);
310
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]311
312#include "ARMGenDisassemblerTables.inc"
313#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]314#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]315
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]316static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
317 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]318}
319
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]320static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
321 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]322}
323
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]324EDInstInfo *ARMDisassembler::getEDInfo() const {
325 return instInfoARM;
326}
327
328EDInstInfo *ThumbDisassembler::getEDInfo() const {
329 return instInfoARM;
330}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]332DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]333 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]334 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]335 raw_ostream &os,
336 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 uint8_t bytes[4];
338
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]339 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
340 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
341
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]342 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]343 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
344 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]345 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]346 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347
348 // Encoded as a small-endian 32-bit word in the stream.
349 uint32_t insn = (bytes[3] << 24) |
350 (bytes[2] << 16) |
351 (bytes[1] << 8) |
352 (bytes[0] << 0);
353
354 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]355 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]356 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]358 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]359 }
360
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]361 // VFP and NEON instructions, similarly, are shared between ARM
362 // and Thumb modes.
363 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]364 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]365 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]366 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]367 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]368 }
369
370 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]371 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]372 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]373 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 // Add a fake predicate operand, because we share these instruction
375 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]376 if (!DecodePredicateOperand(MI, 0xE, Address, this))
377 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]378 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]379 }
380
381 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]382 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]383 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]384 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]385 // Add a fake predicate operand, because we share these instruction
386 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]387 if (!DecodePredicateOperand(MI, 0xE, Address, this))
388 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]389 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]390 }
391
392 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]393 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]394 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]395 Size = 4;
396 // Add a fake predicate operand, because we share these instruction
397 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]398 if (!DecodePredicateOperand(MI, 0xE, Address, this))
399 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]400 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]401 }
402
403 MI.clear();
404
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]405 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]406 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]407}
408
409namespace llvm {
410extern MCInstrDesc ARMInsts[];
411}
412
413// Thumb1 instructions don't have explicit S bits. Rather, they
414// implicitly set CPSR. Since it's not represented in the encoding, the
415// auto-generated decoder won't inject the CPSR operand. We need to fix
416// that as a post-pass.
417static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
418 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]419 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]420 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]421 for (unsigned i = 0; i < NumOps; ++i, ++I) {
422 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]423 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]424 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]425 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
426 return;
427 }
428 }
429
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]430 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]431}
432
433// Most Thumb instructions don't have explicit predicates in the
434// encoding, but rather get their predicates from IT context. We need
435// to fix up the predicate operands using this context information as a
436// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]437MCDisassembler::DecodeStatus
438ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]439 MCDisassembler::DecodeStatus S = Success;
440
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]441 // A few instructions actually have predicates encoded in them. Don't
442 // try to overwrite it if we're seeing one of those.
443 switch (MI.getOpcode()) {
444 case ARM::tBcc:
445 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]446 case ARM::tCBZ:
447 case ARM::tCBNZ:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]448 // Some instructions (mostly conditional branches) are not
449 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]450 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]451 S = SoftFail;
452 else
453 return Success;
454 break;
455 case ARM::tB:
456 case ARM::t2B:
457 // Some instructions (mostly unconditional branches) can
458 // only appears at the end of, or outside of, an IT.
459 if (ITBlock.size() > 1)
460 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]461 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]462 default:
463 break;
464 }
465
466 // If we're in an IT block, base the predicate on that. Otherwise,
467 // assume a predicate of AL.
468 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]469 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]470 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]471 if (CC == 0xF)
472 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]473 ITBlock.pop_back();
474 } else
475 CC = ARMCC::AL;
476
477 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]478 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]479 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]480 for (unsigned i = 0; i < NumOps; ++i, ++I) {
481 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]482 if (OpInfo[i].isPredicate()) {
483 I = MI.insert(I, MCOperand::CreateImm(CC));
484 ++I;
485 if (CC == ARMCC::AL)
486 MI.insert(I, MCOperand::CreateReg(0));
487 else
488 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]489 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]490 }
491 }
492
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]493 I = MI.insert(I, MCOperand::CreateImm(CC));
494 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]495 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]496 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]497 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]498 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]499
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]500 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]501}
502
503// Thumb VFP instructions are a special case. Because we share their
504// encodings between ARM and Thumb modes, and they are predicable in ARM
505// mode, the auto-generated decoder will give them an (incorrect)
506// predicate operand. We need to rewrite these operands based on the IT
507// context as a post-pass.
508void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
509 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]510 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]511 CC = ITBlock.back();
512 ITBlock.pop_back();
513 } else
514 CC = ARMCC::AL;
515
516 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
517 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]518 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
519 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]520 if (OpInfo[i].isPredicate() ) {
521 I->setImm(CC);
522 ++I;
523 if (CC == ARMCC::AL)
524 I->setReg(0);
525 else
526 I->setReg(ARM::CPSR);
527 return;
528 }
529 }
530}
531
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]532DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]533 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]534 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]535 raw_ostream &os,
536 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]537 uint8_t bytes[4];
538
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]539 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
540 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
541
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]542 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]543 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
544 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]545 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]546 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]547
548 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]549 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]550 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]551 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]552 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]553 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]554 }
555
556 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]557 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]558 if (result) {
559 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]560 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]561 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]562 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]563 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]564 }
565
566 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]567 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]568 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]569 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]570 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]571
572 // If we find an IT instruction, we need to parse its condition
573 // code and mask operands so that we can apply them correctly
574 // to the subsequent instructions.
575 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]576 // Nested IT blocks are UNPREDICTABLE.
577 if (!ITBlock.empty())
578 return MCDisassembler::SoftFail;
579
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]580 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]581 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]582 unsigned Mask = MI.getOperand(1).getImm();
583 unsigned CondBit0 = Mask >> 4 & 1;
584 unsigned NumTZ = CountTrailingZeros_32(Mask);
585 assert(NumTZ <= 3 && "Invalid IT mask!");
586 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
587 bool T = ((Mask >> Pos) & 1) == CondBit0;
588 if (T)
589 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]590 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]591 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]592 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]593
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]594 ITBlock.push_back(firstcond);
595 }
596
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]597 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]598 }
599
600 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]601 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
602 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]603 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]604 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]605
606 uint32_t insn32 = (bytes[3] << 8) |
607 (bytes[2] << 0) |
608 (bytes[1] << 24) |
609 (bytes[0] << 16);
610 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]611 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]612 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]613 Size = 4;
614 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]615 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]616 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]617 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]618 }
619
620 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]621 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]622 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]623 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]624 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]625 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]626 }
627
628 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]629 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]630 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]631 Size = 4;
632 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]633 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]634 }
635
636 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]637 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]638 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]639 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]640 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]641 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]642 }
643
644 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
645 MI.clear();
646 uint32_t NEONLdStInsn = insn32;
647 NEONLdStInsn &= 0xF0FFFFFF;
648 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]649 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]650 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]651 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]652 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]653 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]654 }
655 }
656
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]657 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]658 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]659 uint32_t NEONDataInsn = insn32;
660 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
661 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
662 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]663 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]664 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]665 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]666 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]667 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]668 }
669 }
670
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]671 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]672 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]673}
674
675
676extern "C" void LLVMInitializeARMDisassembler() {
677 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
678 createARMDisassembler);
679 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
680 createThumbDisassembler);
681}
682
683static const unsigned GPRDecoderTable[] = {
684 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
685 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
686 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
687 ARM::R12, ARM::SP, ARM::LR, ARM::PC
688};
689
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]690static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]691 uint64_t Address, const void *Decoder) {
692 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]693 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]694
695 unsigned Register = GPRDecoderTable[RegNo];
696 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]697 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]698}
699
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]700static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]701DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
702 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]703 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]704 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
705}
706
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]707static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]708 uint64_t Address, const void *Decoder) {
709 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]710 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]711 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
712}
713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]714static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]715 uint64_t Address, const void *Decoder) {
716 unsigned Register = 0;
717 switch (RegNo) {
718 case 0:
719 Register = ARM::R0;
720 break;
721 case 1:
722 Register = ARM::R1;
723 break;
724 case 2:
725 Register = ARM::R2;
726 break;
727 case 3:
728 Register = ARM::R3;
729 break;
730 case 9:
731 Register = ARM::R9;
732 break;
733 case 12:
734 Register = ARM::R12;
735 break;
736 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]737 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]738 }
739
740 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]741 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]742}
743
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]744static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]745 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]746 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]747 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
748}
749
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]750static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]751 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
752 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
753 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
754 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
755 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
756 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
757 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
758 ARM::S28, ARM::S29, ARM::S30, ARM::S31
759};
760
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]761static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]762 uint64_t Address, const void *Decoder) {
763 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]764 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]765
766 unsigned Register = SPRDecoderTable[RegNo];
767 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]768 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]769}
770
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]771static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]772 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
773 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
774 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
775 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
776 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
777 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
778 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
779 ARM::D28, ARM::D29, ARM::D30, ARM::D31
780};
781
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]782static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783 uint64_t Address, const void *Decoder) {
784 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]785 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786
787 unsigned Register = DPRDecoderTable[RegNo];
788 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]789 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]790}
791
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]792static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]793 uint64_t Address, const void *Decoder) {
794 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]795 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]796 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
797}
798
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]799static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]800DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
801 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]802 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]803 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]804 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
805}
806
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]807static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]808 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
809 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
810 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
811 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
812};
813
814
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]815static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]816 uint64_t Address, const void *Decoder) {
817 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]818 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]819 RegNo >>= 1;
820
821 unsigned Register = QPRDecoderTable[RegNo];
822 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]823 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]824}
825
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]826static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]827 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]828 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]829 // AL predicate is not allowed on Thumb1 branches.
830 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]831 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]832 Inst.addOperand(MCOperand::CreateImm(Val));
833 if (Val == ARMCC::AL) {
834 Inst.addOperand(MCOperand::CreateReg(0));
835 } else
836 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]837 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]838}
839
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]840static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]841 uint64_t Address, const void *Decoder) {
842 if (Val)
843 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
844 else
845 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]846 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]847}
848
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]849static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]850 uint64_t Address, const void *Decoder) {
851 uint32_t imm = Val & 0xFF;
852 uint32_t rot = (Val & 0xF00) >> 7;
853 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
854 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]855 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]856}
857
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]858static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]859 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]860 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]861
862 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
863 unsigned type = fieldFromInstruction32(Val, 5, 2);
864 unsigned imm = fieldFromInstruction32(Val, 7, 5);
865
866 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
868 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]869
870 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
871 switch (type) {
872 case 0:
873 Shift = ARM_AM::lsl;
874 break;
875 case 1:
876 Shift = ARM_AM::lsr;
877 break;
878 case 2:
879 Shift = ARM_AM::asr;
880 break;
881 case 3:
882 Shift = ARM_AM::ror;
883 break;
884 }
885
886 if (Shift == ARM_AM::ror && imm == 0)
887 Shift = ARM_AM::rrx;
888
889 unsigned Op = Shift | (imm << 3);
890 Inst.addOperand(MCOperand::CreateImm(Op));
891
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]892 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]893}
894
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]895static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]896 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]897 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]898
899 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
900 unsigned type = fieldFromInstruction32(Val, 5, 2);
901 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
902
903 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]904 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
905 return MCDisassembler::Fail;
906 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
907 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908
909 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
910 switch (type) {
911 case 0:
912 Shift = ARM_AM::lsl;
913 break;
914 case 1:
915 Shift = ARM_AM::lsr;
916 break;
917 case 2:
918 Shift = ARM_AM::asr;
919 break;
920 case 3:
921 Shift = ARM_AM::ror;
922 break;
923 }
924
925 Inst.addOperand(MCOperand::CreateImm(Shift));
926
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]927 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]928}
929
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]930static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]931 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]932 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]933
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]934 bool writebackLoad = false;
935 unsigned writebackReg = 0;
936 switch (Inst.getOpcode()) {
937 default:
938 break;
939 case ARM::LDMIA_UPD:
940 case ARM::LDMDB_UPD:
941 case ARM::LDMIB_UPD:
942 case ARM::LDMDA_UPD:
943 case ARM::t2LDMIA_UPD:
944 case ARM::t2LDMDB_UPD:
945 writebackLoad = true;
946 writebackReg = Inst.getOperand(0).getReg();
947 break;
948 }
949
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]950 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]951 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]952 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]953 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]954 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
955 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]956 // Writeback not allowed if Rn is in the target list.
957 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
958 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]959 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]960 }
961
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]962 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963}
964
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]965static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]966 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]967 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]968
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]969 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
970 unsigned regs = Val & 0xFF;
971
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]972 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
973 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]974 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]975 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
976 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]977 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]979 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]980}
981
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]982static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]983 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]984 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]985
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]986 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
987 unsigned regs = (Val & 0xFF) / 2;
988
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]989 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
990 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]991 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]992 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
993 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]994 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]996 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]997}
998
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]999static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1000 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1001 // This operand encodes a mask of contiguous zeros between a specified MSB
1002 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1003 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1004 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1005 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1006 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1007 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1008
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1009 DecodeStatus S = MCDisassembler::Success;
1010 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1011
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1012 uint32_t msb_mask = 0xFFFFFFFF;
1013 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1014 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1015
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1016 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1017 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1018}
1019
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1020static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1021 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1022 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1023
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1025 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1026 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1027 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1028 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1029 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1030
1031 switch (Inst.getOpcode()) {
1032 case ARM::LDC_OFFSET:
1033 case ARM::LDC_PRE:
1034 case ARM::LDC_POST:
1035 case ARM::LDC_OPTION:
1036 case ARM::LDCL_OFFSET:
1037 case ARM::LDCL_PRE:
1038 case ARM::LDCL_POST:
1039 case ARM::LDCL_OPTION:
1040 case ARM::STC_OFFSET:
1041 case ARM::STC_PRE:
1042 case ARM::STC_POST:
1043 case ARM::STC_OPTION:
1044 case ARM::STCL_OFFSET:
1045 case ARM::STCL_PRE:
1046 case ARM::STCL_POST:
1047 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1048 case ARM::t2LDC_OFFSET:
1049 case ARM::t2LDC_PRE:
1050 case ARM::t2LDC_POST:
1051 case ARM::t2LDC_OPTION:
1052 case ARM::t2LDCL_OFFSET:
1053 case ARM::t2LDCL_PRE:
1054 case ARM::t2LDCL_POST:
1055 case ARM::t2LDCL_OPTION:
1056 case ARM::t2STC_OFFSET:
1057 case ARM::t2STC_PRE:
1058 case ARM::t2STC_POST:
1059 case ARM::t2STC_OPTION:
1060 case ARM::t2STCL_OFFSET:
1061 case ARM::t2STCL_PRE:
1062 case ARM::t2STCL_POST:
1063 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1064 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1065 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1066 break;
1067 default:
1068 break;
1069 }
1070
1071 Inst.addOperand(MCOperand::CreateImm(coproc));
1072 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1074 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1075 switch (Inst.getOpcode()) {
1076 case ARM::LDC_OPTION:
1077 case ARM::LDCL_OPTION:
1078 case ARM::LDC2_OPTION:
1079 case ARM::LDC2L_OPTION:
1080 case ARM::STC_OPTION:
1081 case ARM::STCL_OPTION:
1082 case ARM::STC2_OPTION:
1083 case ARM::STC2L_OPTION:
1084 case ARM::LDCL_POST:
1085 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1086 case ARM::LDC2L_POST:
1087 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1088 case ARM::t2LDC_OPTION:
1089 case ARM::t2LDCL_OPTION:
1090 case ARM::t2STC_OPTION:
1091 case ARM::t2STCL_OPTION:
1092 case ARM::t2LDCL_POST:
1093 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1094 break;
1095 default:
1096 Inst.addOperand(MCOperand::CreateReg(0));
1097 break;
1098 }
1099
1100 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1101 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1102
1103 bool writeback = (P == 0) || (W == 1);
1104 unsigned idx_mode = 0;
1105 if (P && writeback)
1106 idx_mode = ARMII::IndexModePre;
1107 else if (!P && writeback)
1108 idx_mode = ARMII::IndexModePost;
1109
1110 switch (Inst.getOpcode()) {
1111 case ARM::LDCL_POST:
1112 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1113 case ARM::t2LDCL_POST:
1114 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1115 case ARM::LDC2L_POST:
1116 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1117 imm |= U << 8;
1118 case ARM::LDC_OPTION:
1119 case ARM::LDCL_OPTION:
1120 case ARM::LDC2_OPTION:
1121 case ARM::LDC2L_OPTION:
1122 case ARM::STC_OPTION:
1123 case ARM::STCL_OPTION:
1124 case ARM::STC2_OPTION:
1125 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1126 case ARM::t2LDC_OPTION:
1127 case ARM::t2LDCL_OPTION:
1128 case ARM::t2STC_OPTION:
1129 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1130 Inst.addOperand(MCOperand::CreateImm(imm));
1131 break;
1132 default:
1133 if (U)
1134 Inst.addOperand(MCOperand::CreateImm(
1135 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1136 else
1137 Inst.addOperand(MCOperand::CreateImm(
1138 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1139 break;
1140 }
1141
1142 switch (Inst.getOpcode()) {
1143 case ARM::LDC_OFFSET:
1144 case ARM::LDC_PRE:
1145 case ARM::LDC_POST:
1146 case ARM::LDC_OPTION:
1147 case ARM::LDCL_OFFSET:
1148 case ARM::LDCL_PRE:
1149 case ARM::LDCL_POST:
1150 case ARM::LDCL_OPTION:
1151 case ARM::STC_OFFSET:
1152 case ARM::STC_PRE:
1153 case ARM::STC_POST:
1154 case ARM::STC_OPTION:
1155 case ARM::STCL_OFFSET:
1156 case ARM::STCL_PRE:
1157 case ARM::STCL_POST:
1158 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1159 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1160 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1161 break;
1162 default:
1163 break;
1164 }
1165
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1166 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1167}
1168
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1169static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1170DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1171 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1172 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1173
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1174 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1175 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1176 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1177 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1178 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1179 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1180 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1181 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1182
1183 // On stores, the writeback operand precedes Rt.
1184 switch (Inst.getOpcode()) {
1185 case ARM::STR_POST_IMM:
1186 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1187 case ARM::STRB_POST_IMM:
1188 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1189 case ARM::STRT_POST_REG:
1190 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1191 case ARM::STRBT_POST_REG:
1192 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1193 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1194 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1195 break;
1196 default:
1197 break;
1198 }
1199
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1201 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1202
1203 // On loads, the writeback operand comes after Rt.
1204 switch (Inst.getOpcode()) {
1205 case ARM::LDR_POST_IMM:
1206 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1207 case ARM::LDRB_POST_IMM:
1208 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1209 case ARM::LDRBT_POST_REG:
1210 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1211 case ARM::LDRT_POST_REG:
1212 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1214 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1215 break;
1216 default:
1217 break;
1218 }
1219
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1221 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1222
1223 ARM_AM::AddrOpc Op = ARM_AM::add;
1224 if (!fieldFromInstruction32(Insn, 23, 1))
1225 Op = ARM_AM::sub;
1226
1227 bool writeback = (P == 0) || (W == 1);
1228 unsigned idx_mode = 0;
1229 if (P && writeback)
1230 idx_mode = ARMII::IndexModePre;
1231 else if (!P && writeback)
1232 idx_mode = ARMII::IndexModePost;
1233
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1234 if (writeback && (Rn == 15 || Rn == Rt))
1235 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1236
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1237 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1238 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1239 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1240 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1241 switch( fieldFromInstruction32(Insn, 5, 2)) {
1242 case 0:
1243 Opc = ARM_AM::lsl;
1244 break;
1245 case 1:
1246 Opc = ARM_AM::lsr;
1247 break;
1248 case 2:
1249 Opc = ARM_AM::asr;
1250 break;
1251 case 3:
1252 Opc = ARM_AM::ror;
1253 break;
1254 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1255 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1256 }
1257 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1258 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1259
1260 Inst.addOperand(MCOperand::CreateImm(imm));
1261 } else {
1262 Inst.addOperand(MCOperand::CreateReg(0));
1263 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1264 Inst.addOperand(MCOperand::CreateImm(tmp));
1265 }
1266
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1267 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1268 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1269
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1270 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1271}
1272
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1273static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1274 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1275 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1276
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1277 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1278 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1279 unsigned type = fieldFromInstruction32(Val, 5, 2);
1280 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1281 unsigned U = fieldFromInstruction32(Val, 12, 1);
1282
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1283 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1284 switch (type) {
1285 case 0:
1286 ShOp = ARM_AM::lsl;
1287 break;
1288 case 1:
1289 ShOp = ARM_AM::lsr;
1290 break;
1291 case 2:
1292 ShOp = ARM_AM::asr;
1293 break;
1294 case 3:
1295 ShOp = ARM_AM::ror;
1296 break;
1297 }
1298
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1300 return MCDisassembler::Fail;
1301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1302 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1303 unsigned shift;
1304 if (U)
1305 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1306 else
1307 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1308 Inst.addOperand(MCOperand::CreateImm(shift));
1309
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1310 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1311}
1312
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1313static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1314DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1315 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1316 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1317
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1318 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1319 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1320 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1321 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1322 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1323 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1324 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1325 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1326 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1327
1328 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1329
1330 // For {LD,ST}RD, Rt must be even, else undefined.
1331 switch (Inst.getOpcode()) {
1332 case ARM::STRD:
1333 case ARM::STRD_PRE:
1334 case ARM::STRD_POST:
1335 case ARM::LDRD:
1336 case ARM::LDRD_PRE:
1337 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1338 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1339 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1340 default:
1341 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1342 }
1343
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1344 if (writeback) { // Writeback
1345 if (P)
1346 U |= ARMII::IndexModePre << 9;
1347 else
1348 U |= ARMII::IndexModePost << 9;
1349
1350 // On stores, the writeback operand precedes Rt.
1351 switch (Inst.getOpcode()) {
1352 case ARM::STRD:
1353 case ARM::STRD_PRE:
1354 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1355 case ARM::STRH:
1356 case ARM::STRH_PRE:
1357 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1359 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1360 break;
1361 default:
1362 break;
1363 }
1364 }
1365
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1367 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1368 switch (Inst.getOpcode()) {
1369 case ARM::STRD:
1370 case ARM::STRD_PRE:
1371 case ARM::STRD_POST:
1372 case ARM::LDRD:
1373 case ARM::LDRD_PRE:
1374 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1376 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1377 break;
1378 default:
1379 break;
1380 }
1381
1382 if (writeback) {
1383 // On loads, the writeback operand comes after Rt.
1384 switch (Inst.getOpcode()) {
1385 case ARM::LDRD:
1386 case ARM::LDRD_PRE:
1387 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1388 case ARM::LDRH:
1389 case ARM::LDRH_PRE:
1390 case ARM::LDRH_POST:
1391 case ARM::LDRSH:
1392 case ARM::LDRSH_PRE:
1393 case ARM::LDRSH_POST:
1394 case ARM::LDRSB:
1395 case ARM::LDRSB_PRE:
1396 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1397 case ARM::LDRHTr:
1398 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1400 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1401 break;
1402 default:
1403 break;
1404 }
1405 }
1406
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1408 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1409
1410 if (type) {
1411 Inst.addOperand(MCOperand::CreateReg(0));
1412 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1413 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1415 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1416 Inst.addOperand(MCOperand::CreateImm(U));
1417 }
1418
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1419 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1420 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1421
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1422 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1423}
1424
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1425static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1426 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1427 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1428
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1429 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1430 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1431
1432 switch (mode) {
1433 case 0:
1434 mode = ARM_AM::da;
1435 break;
1436 case 1:
1437 mode = ARM_AM::ia;
1438 break;
1439 case 2:
1440 mode = ARM_AM::db;
1441 break;
1442 case 3:
1443 mode = ARM_AM::ib;
1444 break;
1445 }
1446
1447 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1449 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1450
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1451 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1452}
1453
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1454static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1455 unsigned Insn,
1456 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1457 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1458
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1459 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1460 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1461 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1462
1463 if (pred == 0xF) {
1464 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1465 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1466 Inst.setOpcode(ARM::RFEDA);
1467 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1468 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1469 Inst.setOpcode(ARM::RFEDA_UPD);
1470 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1471 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1472 Inst.setOpcode(ARM::RFEDB);
1473 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1474 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1475 Inst.setOpcode(ARM::RFEDB_UPD);
1476 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1477 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1478 Inst.setOpcode(ARM::RFEIA);
1479 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1480 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1481 Inst.setOpcode(ARM::RFEIA_UPD);
1482 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1483 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1484 Inst.setOpcode(ARM::RFEIB);
1485 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1486 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1487 Inst.setOpcode(ARM::RFEIB_UPD);
1488 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1489 case ARM::STMDA:
1490 Inst.setOpcode(ARM::SRSDA);
1491 break;
1492 case ARM::STMDA_UPD:
1493 Inst.setOpcode(ARM::SRSDA_UPD);
1494 break;
1495 case ARM::STMDB:
1496 Inst.setOpcode(ARM::SRSDB);
1497 break;
1498 case ARM::STMDB_UPD:
1499 Inst.setOpcode(ARM::SRSDB_UPD);
1500 break;
1501 case ARM::STMIA:
1502 Inst.setOpcode(ARM::SRSIA);
1503 break;
1504 case ARM::STMIA_UPD:
1505 Inst.setOpcode(ARM::SRSIA_UPD);
1506 break;
1507 case ARM::STMIB:
1508 Inst.setOpcode(ARM::SRSIB);
1509 break;
1510 case ARM::STMIB_UPD:
1511 Inst.setOpcode(ARM::SRSIB_UPD);
1512 break;
1513 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1514 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1515 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1516
1517 // For stores (which become SRS's, the only operand is the mode.
1518 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1519 Inst.addOperand(
1520 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1521 return S;
1522 }
1523
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1524 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1525 }
1526
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1528 return MCDisassembler::Fail;
1529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1530 return MCDisassembler::Fail; // Tied
1531 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1532 return MCDisassembler::Fail;
1533 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1534 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1535
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1536 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1537}
1538
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1539static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1540 uint64_t Address, const void *Decoder) {
1541 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1542 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1543 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1544 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1545
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1546 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1547
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1548 // imod == '01' --> UNPREDICTABLE
1549 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1550 // return failure here. The '01' imod value is unprintable, so there's
1551 // nothing useful we could do even if we returned UNPREDICTABLE.
1552
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1553 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1554
1555 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1556 Inst.setOpcode(ARM::CPS3p);
1557 Inst.addOperand(MCOperand::CreateImm(imod));
1558 Inst.addOperand(MCOperand::CreateImm(iflags));
1559 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1560 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1561 Inst.setOpcode(ARM::CPS2p);
1562 Inst.addOperand(MCOperand::CreateImm(imod));
1563 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1564 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1565 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1566 Inst.setOpcode(ARM::CPS1p);
1567 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1568 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1569 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1570 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1571 Inst.setOpcode(ARM::CPS1p);
1572 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1573 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1574 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1575
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1576 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1577}
1578
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1579static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1580 uint64_t Address, const void *Decoder) {
1581 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1582 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1583 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1584 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1585
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1586 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1587
1588 // imod == '01' --> UNPREDICTABLE
1589 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1590 // return failure here. The '01' imod value is unprintable, so there's
1591 // nothing useful we could do even if we returned UNPREDICTABLE.
1592
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1593 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1594
1595 if (imod && M) {
1596 Inst.setOpcode(ARM::t2CPS3p);
1597 Inst.addOperand(MCOperand::CreateImm(imod));
1598 Inst.addOperand(MCOperand::CreateImm(iflags));
1599 Inst.addOperand(MCOperand::CreateImm(mode));
1600 } else if (imod && !M) {
1601 Inst.setOpcode(ARM::t2CPS2p);
1602 Inst.addOperand(MCOperand::CreateImm(imod));
1603 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1604 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1605 } else if (!imod && M) {
1606 Inst.setOpcode(ARM::t2CPS1p);
1607 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1608 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1609 } else {
1610 // imod == '00' && M == '0' --> UNPREDICTABLE
1611 Inst.setOpcode(ARM::t2CPS1p);
1612 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1613 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1614 }
1615
1616 return S;
1617}
1618
1619
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1620static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1621 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1622 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1623
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1624 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1625 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1626 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1627 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1628 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1629
1630 if (pred == 0xF)
1631 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1632
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1633 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1634 return MCDisassembler::Fail;
1635 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1636 return MCDisassembler::Fail;
1637 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1638 return MCDisassembler::Fail;
1639 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1640 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1641
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1642 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1643 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1644
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1645 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1646}
1647
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1648static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1649 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1650 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1651
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1652 unsigned add = fieldFromInstruction32(Val, 12, 1);
1653 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1654 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1655
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1657 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1658
1659 if (!add) imm *= -1;
1660 if (imm == 0 && !add) imm = INT32_MIN;
1661 Inst.addOperand(MCOperand::CreateImm(imm));
1662
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1663 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1664}
1665
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1666static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1667 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1668 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1669
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1670 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1671 unsigned U = fieldFromInstruction32(Val, 8, 1);
1672 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1673
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1675 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1676
1677 if (U)
1678 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1679 else
1680 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1681
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1682 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1683}
1684
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1685static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1686 uint64_t Address, const void *Decoder) {
1687 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1688}
1689
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1690static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1691DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1692 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1693 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1694
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1695 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1696 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1697
1698 if (pred == 0xF) {
1699 Inst.setOpcode(ARM::BLXi);
1700 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1701 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1702 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1703 }
1704
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1705 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1706 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1707 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1708
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1709 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1710}
1711
1712
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1713static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1714 uint64_t Address, const void *Decoder) {
1715 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1716 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1717}
1718
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1719static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1720 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1721 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1722
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1723 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1724 unsigned align = fieldFromInstruction32(Val, 4, 2);
1725
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1727 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1728 if (!align)
1729 Inst.addOperand(MCOperand::CreateImm(0));
1730 else
1731 Inst.addOperand(MCOperand::CreateImm(4 << align));
1732
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1733 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1734}
1735
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1736static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1737 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1738 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1739
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1740 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1741 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1742 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1743 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1744 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1745 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1746
1747 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1748 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1749 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1750
1751 // Second output register
1752 switch (Inst.getOpcode()) {
1753 case ARM::VLD1q8:
1754 case ARM::VLD1q16:
1755 case ARM::VLD1q32:
1756 case ARM::VLD1q64:
1757 case ARM::VLD1q8_UPD:
1758 case ARM::VLD1q16_UPD:
1759 case ARM::VLD1q32_UPD:
1760 case ARM::VLD1q64_UPD:
1761 case ARM::VLD1d8T:
1762 case ARM::VLD1d16T:
1763 case ARM::VLD1d32T:
1764 case ARM::VLD1d64T:
1765 case ARM::VLD1d8T_UPD:
1766 case ARM::VLD1d16T_UPD:
1767 case ARM::VLD1d32T_UPD:
1768 case ARM::VLD1d64T_UPD:
1769 case ARM::VLD1d8Q:
1770 case ARM::VLD1d16Q:
1771 case ARM::VLD1d32Q:
1772 case ARM::VLD1d64Q:
1773 case ARM::VLD1d8Q_UPD:
1774 case ARM::VLD1d16Q_UPD:
1775 case ARM::VLD1d32Q_UPD:
1776 case ARM::VLD1d64Q_UPD:
1777 case ARM::VLD2d8:
1778 case ARM::VLD2d16:
1779 case ARM::VLD2d32:
1780 case ARM::VLD2d8_UPD:
1781 case ARM::VLD2d16_UPD:
1782 case ARM::VLD2d32_UPD:
1783 case ARM::VLD2q8:
1784 case ARM::VLD2q16:
1785 case ARM::VLD2q32:
1786 case ARM::VLD2q8_UPD:
1787 case ARM::VLD2q16_UPD:
1788 case ARM::VLD2q32_UPD:
1789 case ARM::VLD3d8:
1790 case ARM::VLD3d16:
1791 case ARM::VLD3d32:
1792 case ARM::VLD3d8_UPD:
1793 case ARM::VLD3d16_UPD:
1794 case ARM::VLD3d32_UPD:
1795 case ARM::VLD4d8:
1796 case ARM::VLD4d16:
1797 case ARM::VLD4d32:
1798 case ARM::VLD4d8_UPD:
1799 case ARM::VLD4d16_UPD:
1800 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1801 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1802 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1803 break;
1804 case ARM::VLD2b8:
1805 case ARM::VLD2b16:
1806 case ARM::VLD2b32:
1807 case ARM::VLD2b8_UPD:
1808 case ARM::VLD2b16_UPD:
1809 case ARM::VLD2b32_UPD:
1810 case ARM::VLD3q8:
1811 case ARM::VLD3q16:
1812 case ARM::VLD3q32:
1813 case ARM::VLD3q8_UPD:
1814 case ARM::VLD3q16_UPD:
1815 case ARM::VLD3q32_UPD:
1816 case ARM::VLD4q8:
1817 case ARM::VLD4q16:
1818 case ARM::VLD4q32:
1819 case ARM::VLD4q8_UPD:
1820 case ARM::VLD4q16_UPD:
1821 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1822 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1823 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1824 default:
1825 break;
1826 }
1827
1828 // Third output register
1829 switch(Inst.getOpcode()) {
1830 case ARM::VLD1d8T:
1831 case ARM::VLD1d16T:
1832 case ARM::VLD1d32T:
1833 case ARM::VLD1d64T:
1834 case ARM::VLD1d8T_UPD:
1835 case ARM::VLD1d16T_UPD:
1836 case ARM::VLD1d32T_UPD:
1837 case ARM::VLD1d64T_UPD:
1838 case ARM::VLD1d8Q:
1839 case ARM::VLD1d16Q:
1840 case ARM::VLD1d32Q:
1841 case ARM::VLD1d64Q:
1842 case ARM::VLD1d8Q_UPD:
1843 case ARM::VLD1d16Q_UPD:
1844 case ARM::VLD1d32Q_UPD:
1845 case ARM::VLD1d64Q_UPD:
1846 case ARM::VLD2q8:
1847 case ARM::VLD2q16:
1848 case ARM::VLD2q32:
1849 case ARM::VLD2q8_UPD:
1850 case ARM::VLD2q16_UPD:
1851 case ARM::VLD2q32_UPD:
1852 case ARM::VLD3d8:
1853 case ARM::VLD3d16:
1854 case ARM::VLD3d32:
1855 case ARM::VLD3d8_UPD:
1856 case ARM::VLD3d16_UPD:
1857 case ARM::VLD3d32_UPD:
1858 case ARM::VLD4d8:
1859 case ARM::VLD4d16:
1860 case ARM::VLD4d32:
1861 case ARM::VLD4d8_UPD:
1862 case ARM::VLD4d16_UPD:
1863 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1864 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1865 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1866 break;
1867 case ARM::VLD3q8:
1868 case ARM::VLD3q16:
1869 case ARM::VLD3q32:
1870 case ARM::VLD3q8_UPD:
1871 case ARM::VLD3q16_UPD:
1872 case ARM::VLD3q32_UPD:
1873 case ARM::VLD4q8:
1874 case ARM::VLD4q16:
1875 case ARM::VLD4q32:
1876 case ARM::VLD4q8_UPD:
1877 case ARM::VLD4q16_UPD:
1878 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1879 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1880 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1881 break;
1882 default:
1883 break;
1884 }
1885
1886 // Fourth output register
1887 switch (Inst.getOpcode()) {
1888 case ARM::VLD1d8Q:
1889 case ARM::VLD1d16Q:
1890 case ARM::VLD1d32Q:
1891 case ARM::VLD1d64Q:
1892 case ARM::VLD1d8Q_UPD:
1893 case ARM::VLD1d16Q_UPD:
1894 case ARM::VLD1d32Q_UPD:
1895 case ARM::VLD1d64Q_UPD:
1896 case ARM::VLD2q8:
1897 case ARM::VLD2q16:
1898 case ARM::VLD2q32:
1899 case ARM::VLD2q8_UPD:
1900 case ARM::VLD2q16_UPD:
1901 case ARM::VLD2q32_UPD:
1902 case ARM::VLD4d8:
1903 case ARM::VLD4d16:
1904 case ARM::VLD4d32:
1905 case ARM::VLD4d8_UPD:
1906 case ARM::VLD4d16_UPD:
1907 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1908 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1909 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1910 break;
1911 case ARM::VLD4q8:
1912 case ARM::VLD4q16:
1913 case ARM::VLD4q32:
1914 case ARM::VLD4q8_UPD:
1915 case ARM::VLD4q16_UPD:
1916 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1917 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1918 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1919 break;
1920 default:
1921 break;
1922 }
1923
1924 // Writeback operand
1925 switch (Inst.getOpcode()) {
1926 case ARM::VLD1d8_UPD:
1927 case ARM::VLD1d16_UPD:
1928 case ARM::VLD1d32_UPD:
1929 case ARM::VLD1d64_UPD:
1930 case ARM::VLD1q8_UPD:
1931 case ARM::VLD1q16_UPD:
1932 case ARM::VLD1q32_UPD:
1933 case ARM::VLD1q64_UPD:
1934 case ARM::VLD1d8T_UPD:
1935 case ARM::VLD1d16T_UPD:
1936 case ARM::VLD1d32T_UPD:
1937 case ARM::VLD1d64T_UPD:
1938 case ARM::VLD1d8Q_UPD:
1939 case ARM::VLD1d16Q_UPD:
1940 case ARM::VLD1d32Q_UPD:
1941 case ARM::VLD1d64Q_UPD:
1942 case ARM::VLD2d8_UPD:
1943 case ARM::VLD2d16_UPD:
1944 case ARM::VLD2d32_UPD:
1945 case ARM::VLD2q8_UPD:
1946 case ARM::VLD2q16_UPD:
1947 case ARM::VLD2q32_UPD:
1948 case ARM::VLD2b8_UPD:
1949 case ARM::VLD2b16_UPD:
1950 case ARM::VLD2b32_UPD:
1951 case ARM::VLD3d8_UPD:
1952 case ARM::VLD3d16_UPD:
1953 case ARM::VLD3d32_UPD:
1954 case ARM::VLD3q8_UPD:
1955 case ARM::VLD3q16_UPD:
1956 case ARM::VLD3q32_UPD:
1957 case ARM::VLD4d8_UPD:
1958 case ARM::VLD4d16_UPD:
1959 case ARM::VLD4d32_UPD:
1960 case ARM::VLD4q8_UPD:
1961 case ARM::VLD4q16_UPD:
1962 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1963 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1964 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1965 break;
1966 default:
1967 break;
1968 }
1969
1970 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1971 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1972 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1973
1974 // AddrMode6 Offset (register)
1975 if (Rm == 0xD)
1976 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1977 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1978 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1979 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1980 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1981
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1982 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1983}
1984
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1985static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1986 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1987 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1988
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1989 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1990 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1991 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1992 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1993 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1994 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1995
1996 // Writeback Operand
1997 switch (Inst.getOpcode()) {
1998 case ARM::VST1d8_UPD:
1999 case ARM::VST1d16_UPD:
2000 case ARM::VST1d32_UPD:
2001 case ARM::VST1d64_UPD:
2002 case ARM::VST1q8_UPD:
2003 case ARM::VST1q16_UPD:
2004 case ARM::VST1q32_UPD:
2005 case ARM::VST1q64_UPD:
2006 case ARM::VST1d8T_UPD:
2007 case ARM::VST1d16T_UPD:
2008 case ARM::VST1d32T_UPD:
2009 case ARM::VST1d64T_UPD:
2010 case ARM::VST1d8Q_UPD:
2011 case ARM::VST1d16Q_UPD:
2012 case ARM::VST1d32Q_UPD:
2013 case ARM::VST1d64Q_UPD:
2014 case ARM::VST2d8_UPD:
2015 case ARM::VST2d16_UPD:
2016 case ARM::VST2d32_UPD:
2017 case ARM::VST2q8_UPD:
2018 case ARM::VST2q16_UPD:
2019 case ARM::VST2q32_UPD:
2020 case ARM::VST2b8_UPD:
2021 case ARM::VST2b16_UPD:
2022 case ARM::VST2b32_UPD:
2023 case ARM::VST3d8_UPD:
2024 case ARM::VST3d16_UPD:
2025 case ARM::VST3d32_UPD:
2026 case ARM::VST3q8_UPD:
2027 case ARM::VST3q16_UPD:
2028 case ARM::VST3q32_UPD:
2029 case ARM::VST4d8_UPD:
2030 case ARM::VST4d16_UPD:
2031 case ARM::VST4d32_UPD:
2032 case ARM::VST4q8_UPD:
2033 case ARM::VST4q16_UPD:
2034 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2035 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2036 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2037 break;
2038 default:
2039 break;
2040 }
2041
2042 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2043 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2044 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2045
2046 // AddrMode6 Offset (register)
2047 if (Rm == 0xD)
2048 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2049 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2051 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2052 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2053
2054 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2055 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2056 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2057
2058 // Second input register
2059 switch (Inst.getOpcode()) {
2060 case ARM::VST1q8:
2061 case ARM::VST1q16:
2062 case ARM::VST1q32:
2063 case ARM::VST1q64:
2064 case ARM::VST1q8_UPD:
2065 case ARM::VST1q16_UPD:
2066 case ARM::VST1q32_UPD:
2067 case ARM::VST1q64_UPD:
2068 case ARM::VST1d8T:
2069 case ARM::VST1d16T:
2070 case ARM::VST1d32T:
2071 case ARM::VST1d64T:
2072 case ARM::VST1d8T_UPD:
2073 case ARM::VST1d16T_UPD:
2074 case ARM::VST1d32T_UPD:
2075 case ARM::VST1d64T_UPD:
2076 case ARM::VST1d8Q:
2077 case ARM::VST1d16Q:
2078 case ARM::VST1d32Q:
2079 case ARM::VST1d64Q:
2080 case ARM::VST1d8Q_UPD:
2081 case ARM::VST1d16Q_UPD:
2082 case ARM::VST1d32Q_UPD:
2083 case ARM::VST1d64Q_UPD:
2084 case ARM::VST2d8:
2085 case ARM::VST2d16:
2086 case ARM::VST2d32:
2087 case ARM::VST2d8_UPD:
2088 case ARM::VST2d16_UPD:
2089 case ARM::VST2d32_UPD:
2090 case ARM::VST2q8:
2091 case ARM::VST2q16:
2092 case ARM::VST2q32:
2093 case ARM::VST2q8_UPD:
2094 case ARM::VST2q16_UPD:
2095 case ARM::VST2q32_UPD:
2096 case ARM::VST3d8:
2097 case ARM::VST3d16:
2098 case ARM::VST3d32:
2099 case ARM::VST3d8_UPD:
2100 case ARM::VST3d16_UPD:
2101 case ARM::VST3d32_UPD:
2102 case ARM::VST4d8:
2103 case ARM::VST4d16:
2104 case ARM::VST4d32:
2105 case ARM::VST4d8_UPD:
2106 case ARM::VST4d16_UPD:
2107 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2108 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2109 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2110 break;
2111 case ARM::VST2b8:
2112 case ARM::VST2b16:
2113 case ARM::VST2b32:
2114 case ARM::VST2b8_UPD:
2115 case ARM::VST2b16_UPD:
2116 case ARM::VST2b32_UPD:
2117 case ARM::VST3q8:
2118 case ARM::VST3q16:
2119 case ARM::VST3q32:
2120 case ARM::VST3q8_UPD:
2121 case ARM::VST3q16_UPD:
2122 case ARM::VST3q32_UPD:
2123 case ARM::VST4q8:
2124 case ARM::VST4q16:
2125 case ARM::VST4q32:
2126 case ARM::VST4q8_UPD:
2127 case ARM::VST4q16_UPD:
2128 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2129 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2130 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2131 break;
2132 default:
2133 break;
2134 }
2135
2136 // Third input register
2137 switch (Inst.getOpcode()) {
2138 case ARM::VST1d8T:
2139 case ARM::VST1d16T:
2140 case ARM::VST1d32T:
2141 case ARM::VST1d64T:
2142 case ARM::VST1d8T_UPD:
2143 case ARM::VST1d16T_UPD:
2144 case ARM::VST1d32T_UPD:
2145 case ARM::VST1d64T_UPD:
2146 case ARM::VST1d8Q:
2147 case ARM::VST1d16Q:
2148 case ARM::VST1d32Q:
2149 case ARM::VST1d64Q:
2150 case ARM::VST1d8Q_UPD:
2151 case ARM::VST1d16Q_UPD:
2152 case ARM::VST1d32Q_UPD:
2153 case ARM::VST1d64Q_UPD:
2154 case ARM::VST2q8:
2155 case ARM::VST2q16:
2156 case ARM::VST2q32:
2157 case ARM::VST2q8_UPD:
2158 case ARM::VST2q16_UPD:
2159 case ARM::VST2q32_UPD:
2160 case ARM::VST3d8:
2161 case ARM::VST3d16:
2162 case ARM::VST3d32:
2163 case ARM::VST3d8_UPD:
2164 case ARM::VST3d16_UPD:
2165 case ARM::VST3d32_UPD:
2166 case ARM::VST4d8:
2167 case ARM::VST4d16:
2168 case ARM::VST4d32:
2169 case ARM::VST4d8_UPD:
2170 case ARM::VST4d16_UPD:
2171 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2172 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2173 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2174 break;
2175 case ARM::VST3q8:
2176 case ARM::VST3q16:
2177 case ARM::VST3q32:
2178 case ARM::VST3q8_UPD:
2179 case ARM::VST3q16_UPD:
2180 case ARM::VST3q32_UPD:
2181 case ARM::VST4q8:
2182 case ARM::VST4q16:
2183 case ARM::VST4q32:
2184 case ARM::VST4q8_UPD:
2185 case ARM::VST4q16_UPD:
2186 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2187 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2188 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2189 break;
2190 default:
2191 break;
2192 }
2193
2194 // Fourth input register
2195 switch (Inst.getOpcode()) {
2196 case ARM::VST1d8Q:
2197 case ARM::VST1d16Q:
2198 case ARM::VST1d32Q:
2199 case ARM::VST1d64Q:
2200 case ARM::VST1d8Q_UPD:
2201 case ARM::VST1d16Q_UPD:
2202 case ARM::VST1d32Q_UPD:
2203 case ARM::VST1d64Q_UPD:
2204 case ARM::VST2q8:
2205 case ARM::VST2q16:
2206 case ARM::VST2q32:
2207 case ARM::VST2q8_UPD:
2208 case ARM::VST2q16_UPD:
2209 case ARM::VST2q32_UPD:
2210 case ARM::VST4d8:
2211 case ARM::VST4d16:
2212 case ARM::VST4d32:
2213 case ARM::VST4d8_UPD:
2214 case ARM::VST4d16_UPD:
2215 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2216 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2217 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2218 break;
2219 case ARM::VST4q8:
2220 case ARM::VST4q16:
2221 case ARM::VST4q32:
2222 case ARM::VST4q8_UPD:
2223 case ARM::VST4q16_UPD:
2224 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2225 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2226 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2227 break;
2228 default:
2229 break;
2230 }
2231
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2232 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2233}
2234
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2235static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2236 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2237 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2238
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2239 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2240 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2241 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2242 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2243 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2244 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2245 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2246
2247 align *= (1 << size);
2248
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2249 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2250 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2251 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2252 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2253 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2254 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2255 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2257 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2258 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2259
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2261 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2262 Inst.addOperand(MCOperand::CreateImm(align));
2263
2264 if (Rm == 0xD)
2265 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2266 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2268 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2269 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2270
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2271 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2272}
2273
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2274static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2275 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2276 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2277
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2278 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2279 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2280 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2281 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2282 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2283 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2284 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2285 align *= 2*size;
2286
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2287 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2288 return MCDisassembler::Fail;
2289 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2290 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2291 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2293 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2294 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2295
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2297 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2298 Inst.addOperand(MCOperand::CreateImm(align));
2299
2300 if (Rm == 0xD)
2301 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2302 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2304 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2305 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2306
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2307 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2308}
2309
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2310static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2311 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2312 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2313
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2314 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2315 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2316 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2317 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2318 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2319
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2320 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2321 return MCDisassembler::Fail;
2322 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2323 return MCDisassembler::Fail;
2324 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2325 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2326 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2328 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2329 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2330
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2332 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2333 Inst.addOperand(MCOperand::CreateImm(0));
2334
2335 if (Rm == 0xD)
2336 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2337 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2339 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2340 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2341
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2342 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2343}
2344
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2345static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2346 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2347 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2348
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2349 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2350 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2351 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2352 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2353 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2354 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2355 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2356
2357 if (size == 0x3) {
2358 size = 4;
2359 align = 16;
2360 } else {
2361 if (size == 2) {
2362 size = 1 << size;
2363 align *= 8;
2364 } else {
2365 size = 1 << size;
2366 align *= 4*size;
2367 }
2368 }
2369
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2370 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2371 return MCDisassembler::Fail;
2372 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2373 return MCDisassembler::Fail;
2374 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2375 return MCDisassembler::Fail;
2376 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2377 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2378 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2380 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2381 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2382
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2384 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2385 Inst.addOperand(MCOperand::CreateImm(align));
2386
2387 if (Rm == 0xD)
2388 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2389 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2391 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2392 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2393
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2394 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2395}
2396
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2397static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2398DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2399 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2400 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2401
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2402 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2403 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2404 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2405 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2406 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2407 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2408 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2409 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2410
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2411 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2412 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2413 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2414 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2416 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2417 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2418
2419 Inst.addOperand(MCOperand::CreateImm(imm));
2420
2421 switch (Inst.getOpcode()) {
2422 case ARM::VORRiv4i16:
2423 case ARM::VORRiv2i32:
2424 case ARM::VBICiv4i16:
2425 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2427 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2428 break;
2429 case ARM::VORRiv8i16:
2430 case ARM::VORRiv4i32:
2431 case ARM::VBICiv8i16:
2432 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2433 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2434 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2435 break;
2436 default:
2437 break;
2438 }
2439
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2440 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2441}
2442
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2443static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2444 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2445 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2446
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2447 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2448 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2449 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2450 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2451 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2452
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2453 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2454 return MCDisassembler::Fail;
2455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2456 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2457 Inst.addOperand(MCOperand::CreateImm(8 << size));
2458
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2459 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2460}
2461
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2462static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2463 uint64_t Address, const void *Decoder) {
2464 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2465 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2466}
2467
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2468static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2469 uint64_t Address, const void *Decoder) {
2470 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2471 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2472}
2473
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2474static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2475 uint64_t Address, const void *Decoder) {
2476 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2477 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2478}
2479
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2480static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2481 uint64_t Address, const void *Decoder) {
2482 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2483 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2484}
2485
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2486static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2487 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2488 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2489
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2490 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2491 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2492 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2493 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2494 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2495 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2496 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2497 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2498
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2500 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2501 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2503 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2504 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2505
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2506 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2507 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2508 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2509 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2510
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2512 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2514 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2515}
2516
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2517static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2518 uint64_t Address, const void *Decoder) {
2519 // The immediate needs to be a fully instantiated float. However, the
2520 // auto-generated decoder is only able to fill in some of the bits
2521 // necessary. For instance, the 'b' bit is replicated multiple times,
2522 // and is even present in inverted form in one bit. We do a little
2523 // binary parsing here to fill in those missing bits, and then
2524 // reinterpret it all as a float.
2525 union {
2526 uint32_t integer;
2527 float fp;
2528 } fp_conv;
2529
2530 fp_conv.integer = Val;
2531 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2532 fp_conv.integer |= b << 26;
2533 fp_conv.integer |= b << 27;
2534 fp_conv.integer |= b << 28;
2535 fp_conv.integer |= b << 29;
2536 fp_conv.integer |= (~b & 0x1) << 30;
2537
2538 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2539 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2540}
2541
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2542static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2543 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2544 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2545
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2546 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2547 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2548
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2549 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2550 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2551
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2552 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2553 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2554 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2555 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2556 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2557 case ARM::tADDrSPi:
2558 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2559 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2560 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2561
2562 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2563 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2564}
2565
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2566static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2567 uint64_t Address, const void *Decoder) {
2568 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2569 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2570}
2571
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2572static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2573 uint64_t Address, const void *Decoder) {
2574 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2575 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2576}
2577
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2578static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2579 uint64_t Address, const void *Decoder) {
2580 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2581 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2582}
2583
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2584static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2585 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2586 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2587
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2588 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2589 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2590
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2591 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2592 return MCDisassembler::Fail;
2593 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2594 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2595
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2596 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2597}
2598
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2599static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2600 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2601 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2602
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2603 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2604 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2605
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2606 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2607 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2608 Inst.addOperand(MCOperand::CreateImm(imm));
2609
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2610 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2611}
2612
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2613static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2614 uint64_t Address, const void *Decoder) {
2615 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2616
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2617 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2618}
2619
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2620static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2621 uint64_t Address, const void *Decoder) {
2622 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2623 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2624
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2625 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2626}
2627
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2628static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2629 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2630 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2631
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2632 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2633 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2634 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2635
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2637 return MCDisassembler::Fail;
2638 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2639 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2640 Inst.addOperand(MCOperand::CreateImm(imm));
2641
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2642 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2643}
2644
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2645static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2646 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2647 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2648
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2649 switch (Inst.getOpcode()) {
2650 case ARM::t2PLDs:
2651 case ARM::t2PLDWs:
2652 case ARM::t2PLIs:
2653 break;
2654 default: {
2655 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2657 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2658 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2659 }
2660
2661 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2662 if (Rn == 0xF) {
2663 switch (Inst.getOpcode()) {
2664 case ARM::t2LDRBs:
2665 Inst.setOpcode(ARM::t2LDRBpci);
2666 break;
2667 case ARM::t2LDRHs:
2668 Inst.setOpcode(ARM::t2LDRHpci);
2669 break;
2670 case ARM::t2LDRSHs:
2671 Inst.setOpcode(ARM::t2LDRSHpci);
2672 break;
2673 case ARM::t2LDRSBs:
2674 Inst.setOpcode(ARM::t2LDRSBpci);
2675 break;
2676 case ARM::t2PLDs:
2677 Inst.setOpcode(ARM::t2PLDi12);
2678 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2679 break;
2680 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2681 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682 }
2683
2684 int imm = fieldFromInstruction32(Insn, 0, 12);
2685 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2686 Inst.addOperand(MCOperand::CreateImm(imm));
2687
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2688 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2689 }
2690
2691 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2692 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2693 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2694 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2695 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2696
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2697 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2698}
2699
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2700static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2701 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2702 int imm = Val & 0xFF;
2703 if (!(Val & 0x100)) imm *= -1;
2704 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2705
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2706 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2707}
2708
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2709static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2710 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2711 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2712
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2713 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2714 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2715
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2717 return MCDisassembler::Fail;
2718 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2719 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2720
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2721 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2722}
2723
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2724static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2725 uint64_t Address, const void *Decoder) {
2726 DecodeStatus S = MCDisassembler::Success;
2727
2728 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2729 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2730
2731 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2732 return MCDisassembler::Fail;
2733
2734 Inst.addOperand(MCOperand::CreateImm(imm));
2735
2736 return S;
2737}
2738
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2739static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2740 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2741 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2742 if (Val == 0)
2743 imm = INT32_MIN;
2744 else if (!(Val & 0x100))
2745 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2746 Inst.addOperand(MCOperand::CreateImm(imm));
2747
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2748 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2749}
2750
2751
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2752static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2753 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2754 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2755
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2756 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2757 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2758
2759 // Some instructions always use an additive offset.
2760 switch (Inst.getOpcode()) {
2761 case ARM::t2LDRT:
2762 case ARM::t2LDRBT:
2763 case ARM::t2LDRHT:
2764 case ARM::t2LDRSBT:
2765 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2766 case ARM::t2STRT:
2767 case ARM::t2STRBT:
2768 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2769 imm |= 0x100;
2770 break;
2771 default:
2772 break;
2773 }
2774
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2776 return MCDisassembler::Fail;
2777 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2778 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2779
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2780 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2781}
2782
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2783static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2784 uint64_t Address, const void *Decoder) {
2785 DecodeStatus S = MCDisassembler::Success;
2786
2787 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2788 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2789 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2790 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2791 addr |= Rn << 9;
2792 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2793
2794 if (!load) {
2795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2796 return MCDisassembler::Fail;
2797 }
2798
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2799 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2800 return MCDisassembler::Fail;
2801
2802 if (load) {
2803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2804 return MCDisassembler::Fail;
2805 }
2806
2807 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2808 return MCDisassembler::Fail;
2809
2810 return S;
2811}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2813static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2814 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2815 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2816
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2818 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2819
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2821 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2822 Inst.addOperand(MCOperand::CreateImm(imm));
2823
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2824 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2825}
2826
2827
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2828static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2829 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2830 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2831
2832 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2833 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2834 Inst.addOperand(MCOperand::CreateImm(imm));
2835
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2836 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2837}
2838
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2839static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2840 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2841 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2842
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2843 if (Inst.getOpcode() == ARM::tADDrSP) {
2844 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2845 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2846
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2848 return MCDisassembler::Fail;
2849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2850 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2851 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2852 } else if (Inst.getOpcode() == ARM::tADDspr) {
2853 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2854
2855 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2856 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2858 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2859 }
2860
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2861 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2862}
2863
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2864static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2865 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2866 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2867 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2868
2869 Inst.addOperand(MCOperand::CreateImm(imod));
2870 Inst.addOperand(MCOperand::CreateImm(flags));
2871
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2872 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2873}
2874
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2875static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2876 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2877 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2878 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2879 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2882 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2883 Inst.addOperand(MCOperand::CreateImm(add));
2884
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2885 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2886}
2887
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2888static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2889 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2890 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2891 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2892}
2893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2894static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2895 uint64_t Address, const void *Decoder) {
2896 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2897 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2898
2899 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2900 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2901}
2902
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2903static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame^]2904DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
2905 uint64_t Address, const void *Decoder) {
2906 DecodeStatus S = MCDisassembler::Success;
2907
2908 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2909 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2910
2911 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
2912 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2913 return MCDisassembler::Fail;
2914 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2915 return MCDisassembler::Fail;
2916 return S;
2917}
2918
2919static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2920DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2921 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2922 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2923
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2924 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2925 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2926 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2927 switch (opc) {
2928 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2929 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2930 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2931 Inst.setOpcode(ARM::t2DSB);
2932 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2933 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2934 Inst.setOpcode(ARM::t2DMB);
2935 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2936 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2937 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2938 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2939 }
2940
2941 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2942 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2943 }
2944
2945 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2946 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2947 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2948 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2949 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2950
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2951 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2952 return MCDisassembler::Fail;
2953 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2954 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2955
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2956 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2957}
2958
2959// Decode a shifted immediate operand. These basically consist
2960// of an 8-bit value, and a 4-bit directive that specifies either
2961// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2962static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2963 uint64_t Address, const void *Decoder) {
2964 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2965 if (ctrl == 0) {
2966 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2967 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2968 switch (byte) {
2969 case 0:
2970 Inst.addOperand(MCOperand::CreateImm(imm));
2971 break;
2972 case 1:
2973 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2974 break;
2975 case 2:
2976 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2977 break;
2978 case 3:
2979 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2980 (imm << 8) | imm));
2981 break;
2982 }
2983 } else {
2984 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2985 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2986 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2987 Inst.addOperand(MCOperand::CreateImm(imm));
2988 }
2989
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2990 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2991}
2992
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2993static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2994DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2995 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2996 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2997 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2998}
2999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3000static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3001 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3002 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3003 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3004}
3005
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3006static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3007 uint64_t Address, const void *Decoder) {
3008 switch (Val) {
3009 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3010 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3011 case 0xF: // SY
3012 case 0xE: // ST
3013 case 0xB: // ISH
3014 case 0xA: // ISHST
3015 case 0x7: // NSH
3016 case 0x6: // NSHST
3017 case 0x3: // OSH
3018 case 0x2: // OSHST
3019 break;
3020 }
3021
3022 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3023 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3024}
3025
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3026static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3027 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3028 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3029 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3030 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3031}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3032
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3033static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3034 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3035 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3036
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3037 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3038 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3039 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3040
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3041 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3042
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3043 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3044 return MCDisassembler::Fail;
3045 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3046 return MCDisassembler::Fail;
3047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3048 return MCDisassembler::Fail;
3049 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3050 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3051
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3052 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3053}
3054
3055
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3056static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3057 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3058 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3059
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3060 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3061 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3062 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3063 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3064
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3065 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3066 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3067
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3068 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3069 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3070
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3072 return MCDisassembler::Fail;
3073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3074 return MCDisassembler::Fail;
3075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3076 return MCDisassembler::Fail;
3077 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3078 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3079
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3080 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3081}
3082
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3083static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3084 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3085 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3086
3087 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3088 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3089 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3090 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3091 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3092 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3093
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3094 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3095
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3097 return MCDisassembler::Fail;
3098 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3099 return MCDisassembler::Fail;
3100 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3101 return MCDisassembler::Fail;
3102 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3103 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3104
3105 return S;
3106}
3107
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3108static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3109 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3110 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3111
3112 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3113 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3114 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3115 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3116 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3117 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3118 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3119
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3120 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3121 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3122
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3124 return MCDisassembler::Fail;
3125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3126 return MCDisassembler::Fail;
3127 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3128 return MCDisassembler::Fail;
3129 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3130 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3131
3132 return S;
3133}
3134
3135
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3136static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3137 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3138 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3139
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3140 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3141 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3142 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3143 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3144 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3145 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3146
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3147 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3148
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3150 return MCDisassembler::Fail;
3151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3152 return MCDisassembler::Fail;
3153 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3154 return MCDisassembler::Fail;
3155 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3156 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3157
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3158 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3159}
3160
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3161static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3162 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3163 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3164
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3165 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3166 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3167 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3168 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3169 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3170 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3171
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3172 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3173
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3174 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3175 return MCDisassembler::Fail;
3176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3177 return MCDisassembler::Fail;
3178 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3179 return MCDisassembler::Fail;
3180 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3181 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3182
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3183 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3184}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3185
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3186static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3187 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3188 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3189
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3190 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3191 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3192 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3193 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3194 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3195
3196 unsigned align = 0;
3197 unsigned index = 0;
3198 switch (size) {
3199 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3200 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3201 case 0:
3202 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3203 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3204 index = fieldFromInstruction32(Insn, 5, 3);
3205 break;
3206 case 1:
3207 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3208 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3209 index = fieldFromInstruction32(Insn, 6, 2);
3210 if (fieldFromInstruction32(Insn, 4, 1))
3211 align = 2;
3212 break;
3213 case 2:
3214 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3215 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3216 index = fieldFromInstruction32(Insn, 7, 1);
3217 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3218 align = 4;
3219 }
3220
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3222 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3223 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3225 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3226 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3228 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3229 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3230 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3231 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3233 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3234 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3235 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3236 }
3237
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3238 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3239 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3240 Inst.addOperand(MCOperand::CreateImm(index));
3241
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3242 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3243}
3244
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3245static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3246 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3247 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3248
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3249 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3250 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3251 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3252 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3253 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3254
3255 unsigned align = 0;
3256 unsigned index = 0;
3257 switch (size) {
3258 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3259 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3260 case 0:
3261 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3262 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3263 index = fieldFromInstruction32(Insn, 5, 3);
3264 break;
3265 case 1:
3266 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3267 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3268 index = fieldFromInstruction32(Insn, 6, 2);
3269 if (fieldFromInstruction32(Insn, 4, 1))
3270 align = 2;
3271 break;
3272 case 2:
3273 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3274 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3275 index = fieldFromInstruction32(Insn, 7, 1);
3276 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3277 align = 4;
3278 }
3279
3280 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3282 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3283 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3285 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3286 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3287 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3288 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3290 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3291 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3292 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3293 }
3294
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3295 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3296 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3297 Inst.addOperand(MCOperand::CreateImm(index));
3298
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3299 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3300}
3301
3302
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3303static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3304 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3305 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3306
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3307 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3308 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3309 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3310 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3311 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3312
3313 unsigned align = 0;
3314 unsigned index = 0;
3315 unsigned inc = 1;
3316 switch (size) {
3317 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3318 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3319 case 0:
3320 index = fieldFromInstruction32(Insn, 5, 3);
3321 if (fieldFromInstruction32(Insn, 4, 1))
3322 align = 2;
3323 break;
3324 case 1:
3325 index = fieldFromInstruction32(Insn, 6, 2);
3326 if (fieldFromInstruction32(Insn, 4, 1))
3327 align = 4;
3328 if (fieldFromInstruction32(Insn, 5, 1))
3329 inc = 2;
3330 break;
3331 case 2:
3332 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3333 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3334 index = fieldFromInstruction32(Insn, 7, 1);
3335 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3336 align = 8;
3337 if (fieldFromInstruction32(Insn, 6, 1))
3338 inc = 2;
3339 break;
3340 }
3341
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3342 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3343 return MCDisassembler::Fail;
3344 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3345 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3346 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3348 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3349 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3351 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3352 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3353 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3354 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3356 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3357 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3358 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3359 }
3360
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3361 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3362 return MCDisassembler::Fail;
3363 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3364 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3365 Inst.addOperand(MCOperand::CreateImm(index));
3366
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3367 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3368}
3369
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3370static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3371 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3372 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3373
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3374 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3375 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3376 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3377 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3378 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3379
3380 unsigned align = 0;
3381 unsigned index = 0;
3382 unsigned inc = 1;
3383 switch (size) {
3384 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3385 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3386 case 0:
3387 index = fieldFromInstruction32(Insn, 5, 3);
3388 if (fieldFromInstruction32(Insn, 4, 1))
3389 align = 2;
3390 break;
3391 case 1:
3392 index = fieldFromInstruction32(Insn, 6, 2);
3393 if (fieldFromInstruction32(Insn, 4, 1))
3394 align = 4;
3395 if (fieldFromInstruction32(Insn, 5, 1))
3396 inc = 2;
3397 break;
3398 case 2:
3399 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3400 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3401 index = fieldFromInstruction32(Insn, 7, 1);
3402 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3403 align = 8;
3404 if (fieldFromInstruction32(Insn, 6, 1))
3405 inc = 2;
3406 break;
3407 }
3408
3409 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3411 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3412 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3414 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3415 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3416 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3417 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3419 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3420 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3421 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3422 }
3423
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3425 return MCDisassembler::Fail;
3426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3427 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3428 Inst.addOperand(MCOperand::CreateImm(index));
3429
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3430 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3431}
3432
3433
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3434static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3435 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3436 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3437
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3438 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3439 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3440 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3441 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3442 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3443
3444 unsigned align = 0;
3445 unsigned index = 0;
3446 unsigned inc = 1;
3447 switch (size) {
3448 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3449 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3450 case 0:
3451 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3452 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3453 index = fieldFromInstruction32(Insn, 5, 3);
3454 break;
3455 case 1:
3456 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3457 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3458 index = fieldFromInstruction32(Insn, 6, 2);
3459 if (fieldFromInstruction32(Insn, 5, 1))
3460 inc = 2;
3461 break;
3462 case 2:
3463 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3464 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3465 index = fieldFromInstruction32(Insn, 7, 1);
3466 if (fieldFromInstruction32(Insn, 6, 1))
3467 inc = 2;
3468 break;
3469 }
3470
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3471 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3472 return MCDisassembler::Fail;
3473 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3474 return MCDisassembler::Fail;
3475 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3476 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3477
3478 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3480 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3481 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3483 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3484 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3485 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3486 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3488 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3489 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3490 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3491 }
3492
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3493 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3494 return MCDisassembler::Fail;
3495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3496 return MCDisassembler::Fail;
3497 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3498 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3499 Inst.addOperand(MCOperand::CreateImm(index));
3500
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3501 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3502}
3503
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3504static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3505 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3506 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3507
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3508 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3509 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3510 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3511 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3512 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3513
3514 unsigned align = 0;
3515 unsigned index = 0;
3516 unsigned inc = 1;
3517 switch (size) {
3518 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3519 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3520 case 0:
3521 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3522 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3523 index = fieldFromInstruction32(Insn, 5, 3);
3524 break;
3525 case 1:
3526 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3527 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3528 index = fieldFromInstruction32(Insn, 6, 2);
3529 if (fieldFromInstruction32(Insn, 5, 1))
3530 inc = 2;
3531 break;
3532 case 2:
3533 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3534 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3535 index = fieldFromInstruction32(Insn, 7, 1);
3536 if (fieldFromInstruction32(Insn, 6, 1))
3537 inc = 2;
3538 break;
3539 }
3540
3541 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3543 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3544 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3546 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3547 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3548 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3549 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3551 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3552 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3553 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3554 }
3555
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3556 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3557 return MCDisassembler::Fail;
3558 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3559 return MCDisassembler::Fail;
3560 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3561 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3562 Inst.addOperand(MCOperand::CreateImm(index));
3563
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3564 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3565}
3566
3567
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3568static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3569 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3570 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3571
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3572 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3573 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3574 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3575 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3576 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3577
3578 unsigned align = 0;
3579 unsigned index = 0;
3580 unsigned inc = 1;
3581 switch (size) {
3582 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3583 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3584 case 0:
3585 if (fieldFromInstruction32(Insn, 4, 1))
3586 align = 4;
3587 index = fieldFromInstruction32(Insn, 5, 3);
3588 break;
3589 case 1:
3590 if (fieldFromInstruction32(Insn, 4, 1))
3591 align = 8;
3592 index = fieldFromInstruction32(Insn, 6, 2);
3593 if (fieldFromInstruction32(Insn, 5, 1))
3594 inc = 2;
3595 break;
3596 case 2:
3597 if (fieldFromInstruction32(Insn, 4, 2))
3598 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3599 index = fieldFromInstruction32(Insn, 7, 1);
3600 if (fieldFromInstruction32(Insn, 6, 1))
3601 inc = 2;
3602 break;
3603 }
3604
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3606 return MCDisassembler::Fail;
3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3608 return MCDisassembler::Fail;
3609 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3610 return MCDisassembler::Fail;
3611 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3612 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3613
3614 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3616 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3617 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3619 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3620 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3621 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3622 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3624 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3625 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3626 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3627 }
3628
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3629 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3630 return MCDisassembler::Fail;
3631 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3632 return MCDisassembler::Fail;
3633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3634 return MCDisassembler::Fail;
3635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3636 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3637 Inst.addOperand(MCOperand::CreateImm(index));
3638
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3639 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3640}
3641
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3642static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3643 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3644 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3645
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3646 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3647 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3648 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3649 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3650 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3651
3652 unsigned align = 0;
3653 unsigned index = 0;
3654 unsigned inc = 1;
3655 switch (size) {
3656 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3657 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3658 case 0:
3659 if (fieldFromInstruction32(Insn, 4, 1))
3660 align = 4;
3661 index = fieldFromInstruction32(Insn, 5, 3);
3662 break;
3663 case 1:
3664 if (fieldFromInstruction32(Insn, 4, 1))
3665 align = 8;
3666 index = fieldFromInstruction32(Insn, 6, 2);
3667 if (fieldFromInstruction32(Insn, 5, 1))
3668 inc = 2;
3669 break;
3670 case 2:
3671 if (fieldFromInstruction32(Insn, 4, 2))
3672 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3673 index = fieldFromInstruction32(Insn, 7, 1);
3674 if (fieldFromInstruction32(Insn, 6, 1))
3675 inc = 2;
3676 break;
3677 }
3678
3679 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3681 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3682 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3684 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3685 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3686 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3687 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3689 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3690 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3691 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3692 }
3693
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3694 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3695 return MCDisassembler::Fail;
3696 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3697 return MCDisassembler::Fail;
3698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3699 return MCDisassembler::Fail;
3700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3701 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3702 Inst.addOperand(MCOperand::CreateImm(index));
3703
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3704 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3705}
3706
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3707static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3708 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3709 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3710 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3711 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3712 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3713 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3714 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3715
3716 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3717 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3718
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3719 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3720 return MCDisassembler::Fail;
3721 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3722 return MCDisassembler::Fail;
3723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3724 return MCDisassembler::Fail;
3725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3726 return MCDisassembler::Fail;
3727 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3728 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3729
3730 return S;
3731}
3732
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3733static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3734 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3735 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3736 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3737 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3738 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3739 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3740 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3741
3742 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3743 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3744
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3746 return MCDisassembler::Fail;
3747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3748 return MCDisassembler::Fail;
3749 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3750 return MCDisassembler::Fail;
3751 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3752 return MCDisassembler::Fail;
3753 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3754 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3755
3756 return S;
3757}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3759static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3760 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3761 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3762 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3763 // The InstPrinter needs to have the low bit of the predicate in
3764 // the mask operand to be able to print it properly.
3765 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3766
3767 if (pred == 0xF) {
3768 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3769 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3770 }
3771
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3772 if ((mask & 0xF) == 0) {
3773 // Preserve the high bit of the mask, which is the low bit of
3774 // the predicate.
3775 mask &= 0x10;
3776 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3777 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3778 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3779
3780 Inst.addOperand(MCOperand::CreateImm(pred));
3781 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3782 return S;
3783}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3784
3785static DecodeStatus
3786DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3787 uint64_t Address, const void *Decoder) {
3788 DecodeStatus S = MCDisassembler::Success;
3789
3790 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3791 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3792 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3793 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3794 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3795 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3796 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3797 bool writeback = (W == 1) | (P == 0);
3798
3799 addr |= (U << 8) | (Rn << 9);
3800
3801 if (writeback && (Rn == Rt || Rn == Rt2))
3802 Check(S, MCDisassembler::SoftFail);
3803 if (Rt == Rt2)
3804 Check(S, MCDisassembler::SoftFail);
3805
3806 // Rt
3807 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3808 return MCDisassembler::Fail;
3809 // Rt2
3810 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3811 return MCDisassembler::Fail;
3812 // Writeback operand
3813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3814 return MCDisassembler::Fail;
3815 // addr
3816 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3817 return MCDisassembler::Fail;
3818
3819 return S;
3820}
3821
3822static DecodeStatus
3823DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3824 uint64_t Address, const void *Decoder) {
3825 DecodeStatus S = MCDisassembler::Success;
3826
3827 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3828 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3829 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3830 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3831 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3832 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3833 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3834 bool writeback = (W == 1) | (P == 0);
3835
3836 addr |= (U << 8) | (Rn << 9);
3837
3838 if (writeback && (Rn == Rt || Rn == Rt2))
3839 Check(S, MCDisassembler::SoftFail);
3840
3841 // Writeback operand
3842 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3843 return MCDisassembler::Fail;
3844 // Rt
3845 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3846 return MCDisassembler::Fail;
3847 // Rt2
3848 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3849 return MCDisassembler::Fail;
3850 // addr
3851 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3852 return MCDisassembler::Fail;
3853
3854 return S;
3855}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]3856
3857static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3858 uint64_t Address, const void *Decoder) {
3859 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3860 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3861 if (sign1 != sign2) return MCDisassembler::Fail;
3862
3863 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3864 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3865 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3866 Val |= sign1 << 12;
3867 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3868
3869 return MCDisassembler::Success;
3870}
3871