Duncan Sands | 9d32f60 | 2011-01-20 13:21:55 +0000 | [diff] [blame] | 1 | ; RUN: opt < %s -instsimplify -S | FileCheck %s |
| 2 | target datalayout = "p:32:32" |
| 3 | |
| 4 | define i1 @ptrtoint() { |
| 5 | ; CHECK: @ptrtoint |
| 6 | %a = alloca i8 |
| 7 | %tmp = ptrtoint i8* %a to i32 |
| 8 | %r = icmp eq i32 %tmp, 0 |
| 9 | ret i1 %r |
| 10 | ; CHECK: ret i1 false |
| 11 | } |
| 12 | |
| 13 | define i1 @zext(i32 %x) { |
| 14 | ; CHECK: @zext |
| 15 | %e1 = zext i32 %x to i64 |
| 16 | %e2 = zext i32 %x to i64 |
| 17 | %r = icmp eq i64 %e1, %e2 |
| 18 | ret i1 %r |
| 19 | ; CHECK: ret i1 true |
| 20 | } |
| 21 | |
| 22 | define i1 @zext2(i1 %x) { |
| 23 | ; CHECK: @zext2 |
| 24 | %e = zext i1 %x to i32 |
| 25 | %c = icmp ne i32 %e, 0 |
| 26 | ret i1 %c |
| 27 | ; CHECK: ret i1 %x |
| 28 | } |
| 29 | |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 30 | define i1 @zext3() { |
| 31 | ; CHECK: @zext3 |
| 32 | %e = zext i1 1 to i32 |
| 33 | %c = icmp ne i32 %e, 0 |
| 34 | ret i1 %c |
| 35 | ; CHECK: ret i1 true |
| 36 | } |
| 37 | |
Duncan Sands | 9d32f60 | 2011-01-20 13:21:55 +0000 | [diff] [blame] | 38 | define i1 @sext(i32 %x) { |
| 39 | ; CHECK: @sext |
| 40 | %e1 = sext i32 %x to i64 |
| 41 | %e2 = sext i32 %x to i64 |
| 42 | %r = icmp eq i64 %e1, %e2 |
| 43 | ret i1 %r |
| 44 | ; CHECK: ret i1 true |
| 45 | } |
| 46 | |
| 47 | define i1 @sext2(i1 %x) { |
| 48 | ; CHECK: @sext2 |
| 49 | %e = sext i1 %x to i32 |
| 50 | %c = icmp ne i32 %e, 0 |
| 51 | ret i1 %c |
| 52 | ; CHECK: ret i1 %x |
| 53 | } |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 54 | |
| 55 | define i1 @sext3() { |
| 56 | ; CHECK: @sext3 |
| 57 | %e = sext i1 1 to i32 |
| 58 | %c = icmp ne i32 %e, 0 |
| 59 | ret i1 %c |
| 60 | ; CHECK: ret i1 true |
| 61 | } |
| 62 | |
| 63 | define i1 @add(i32 %x, i32 %y) { |
Duncan Sands | 227fba1 | 2011-01-25 15:14:15 +0000 | [diff] [blame] | 64 | ; CHECK: @add |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 65 | %l = lshr i32 %x, 1 |
Duncan Sands | 227fba1 | 2011-01-25 15:14:15 +0000 | [diff] [blame] | 66 | %q = lshr i32 %y, 1 |
| 67 | %r = or i32 %q, 1 |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 68 | %s = add i32 %l, %r |
| 69 | %c = icmp eq i32 %s, 0 |
| 70 | ret i1 %c |
Duncan Sands | 227fba1 | 2011-01-25 15:14:15 +0000 | [diff] [blame] | 71 | ; CHECK: ret i1 false |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | define i1 @add2(i8 %x, i8 %y) { |
| 75 | ; CHECK: @add2 |
| 76 | %l = or i8 %x, 128 |
| 77 | %r = or i8 %y, 129 |
| 78 | %s = add i8 %l, %r |
| 79 | %c = icmp eq i8 %s, 0 |
| 80 | ret i1 %c |
| 81 | ; CHECK: ret i1 false |
| 82 | } |
| 83 | |
Duncan Sands | 227fba1 | 2011-01-25 15:14:15 +0000 | [diff] [blame] | 84 | define i1 @add3(i8 %x, i8 %y) { |
| 85 | ; CHECK: @add3 |
| 86 | %l = zext i8 %x to i32 |
| 87 | %r = zext i8 %y to i32 |
| 88 | %s = add i32 %l, %r |
| 89 | %c = icmp eq i32 %s, 0 |
| 90 | ret i1 %c |
| 91 | ; CHECK: ret i1 %c |
| 92 | } |
| 93 | |
Duncan Sands | 52fb846 | 2011-02-13 17:15:40 +0000 | [diff] [blame] | 94 | define i1 @add4(i32 %x, i32 %y) { |
| 95 | ; CHECK: @add4 |
| 96 | %z = add nsw i32 %y, 1 |
| 97 | %s1 = add nsw i32 %x, %y |
| 98 | %s2 = add nsw i32 %x, %z |
| 99 | %c = icmp slt i32 %s1, %s2 |
| 100 | ret i1 %c |
| 101 | ; CHECK: ret i1 true |
| 102 | } |
| 103 | |
| 104 | define i1 @add5(i32 %x, i32 %y) { |
| 105 | ; CHECK: @add5 |
| 106 | %z = add nuw i32 %y, 1 |
| 107 | %s1 = add nuw i32 %x, %z |
| 108 | %s2 = add nuw i32 %x, %y |
| 109 | %c = icmp ugt i32 %s1, %s2 |
| 110 | ret i1 %c |
| 111 | ; CHECK: ret i1 true |
| 112 | } |
| 113 | |
Duncan Sands | d70d1a5 | 2011-01-25 09:38:29 +0000 | [diff] [blame] | 114 | define i1 @addpowtwo(i32 %x, i32 %y) { |
| 115 | ; CHECK: @addpowtwo |
| 116 | %l = lshr i32 %x, 1 |
| 117 | %r = shl i32 1, %y |
| 118 | %s = add i32 %l, %r |
| 119 | %c = icmp eq i32 %s, 0 |
| 120 | ret i1 %c |
| 121 | ; CHECK: ret i1 false |
| 122 | } |
| 123 | |
| 124 | define i1 @or(i32 %x) { |
| 125 | ; CHECK: @or |
| 126 | %o = or i32 %x, 1 |
| 127 | %c = icmp eq i32 %o, 0 |
| 128 | ret i1 %c |
| 129 | ; CHECK: ret i1 false |
| 130 | } |
Duncan Sands | 9136782 | 2011-01-29 13:27:00 +0000 | [diff] [blame] | 131 | |
| 132 | define i1 @shl(i32 %x) { |
| 133 | ; CHECK: @shl |
| 134 | %s = shl i32 1, %x |
| 135 | %c = icmp eq i32 %s, 0 |
| 136 | ret i1 %c |
| 137 | ; CHECK: ret i1 false |
| 138 | } |
| 139 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 140 | define i1 @lshr1(i32 %x) { |
| 141 | ; CHECK: @lshr1 |
Duncan Sands | 9136782 | 2011-01-29 13:27:00 +0000 | [diff] [blame] | 142 | %s = lshr i32 -1, %x |
| 143 | %c = icmp eq i32 %s, 0 |
| 144 | ret i1 %c |
| 145 | ; CHECK: ret i1 false |
| 146 | } |
| 147 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 148 | define i1 @lshr2(i32 %x) { |
| 149 | ; CHECK: @lshr2 |
| 150 | %s = lshr i32 %x, 30 |
| 151 | %c = icmp ugt i32 %s, 8 |
| 152 | ret i1 %c |
| 153 | ; CHECK: ret i1 false |
| 154 | } |
| 155 | |
| 156 | define i1 @ashr1(i32 %x) { |
| 157 | ; CHECK: @ashr1 |
Duncan Sands | 9136782 | 2011-01-29 13:27:00 +0000 | [diff] [blame] | 158 | %s = ashr i32 -1, %x |
| 159 | %c = icmp eq i32 %s, 0 |
| 160 | ret i1 %c |
| 161 | ; CHECK: ret i1 false |
| 162 | } |
Duncan Sands | 50ca4d3 | 2011-02-03 09:37:39 +0000 | [diff] [blame] | 163 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 164 | define i1 @ashr2(i32 %x) { |
| 165 | ; CHECK: @ashr2 |
| 166 | %s = ashr i32 %x, 30 |
| 167 | %c = icmp slt i32 %s, -5 |
| 168 | ret i1 %c |
| 169 | ; CHECK: ret i1 false |
| 170 | } |
| 171 | |
Duncan Sands | 50ca4d3 | 2011-02-03 09:37:39 +0000 | [diff] [blame] | 172 | define i1 @select1(i1 %cond) { |
| 173 | ; CHECK: @select1 |
| 174 | %s = select i1 %cond, i32 1, i32 0 |
| 175 | %c = icmp eq i32 %s, 1 |
| 176 | ret i1 %c |
| 177 | ; CHECK: ret i1 %cond |
| 178 | } |
| 179 | |
| 180 | define i1 @select2(i1 %cond) { |
| 181 | ; CHECK: @select2 |
| 182 | %x = zext i1 %cond to i32 |
| 183 | %s = select i1 %cond, i32 %x, i32 0 |
| 184 | %c = icmp ne i32 %s, 0 |
| 185 | ret i1 %c |
| 186 | ; CHECK: ret i1 %cond |
| 187 | } |
| 188 | |
| 189 | define i1 @select3(i1 %cond) { |
| 190 | ; CHECK: @select3 |
| 191 | %x = zext i1 %cond to i32 |
| 192 | %s = select i1 %cond, i32 1, i32 %x |
| 193 | %c = icmp ne i32 %s, 0 |
| 194 | ret i1 %c |
| 195 | ; CHECK: ret i1 %cond |
| 196 | } |
| 197 | |
| 198 | define i1 @select4(i1 %cond) { |
| 199 | ; CHECK: @select4 |
| 200 | %invert = xor i1 %cond, 1 |
| 201 | %s = select i1 %invert, i32 0, i32 1 |
| 202 | %c = icmp ne i32 %s, 0 |
| 203 | ret i1 %c |
| 204 | ; CHECK: ret i1 %cond |
| 205 | } |
Nick Lewycky | 88cd0aa | 2011-03-01 08:15:50 +0000 | [diff] [blame] | 206 | |
| 207 | define i1 @urem1(i32 %X, i32 %Y) { |
| 208 | ; CHECK: @urem1 |
| 209 | %A = urem i32 %X, %Y |
| 210 | %B = icmp ult i32 %A, %Y |
| 211 | ret i1 %B |
| 212 | ; CHECK: ret i1 true |
| 213 | } |
| 214 | |
| 215 | define i1 @urem2(i32 %X, i32 %Y) { |
| 216 | ; CHECK: @urem2 |
| 217 | %A = urem i32 %X, %Y |
| 218 | %B = icmp eq i32 %A, %Y |
| 219 | ret i1 %B |
| 220 | ; CHECK ret i1 false |
| 221 | } |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 222 | |
| 223 | define i1 @urem3(i32 %X) { |
| 224 | ; CHECK: @urem3 |
| 225 | %A = urem i32 %X, 10 |
| 226 | %B = icmp ult i32 %A, 15 |
| 227 | ret i1 %B |
| 228 | ; CHECK: ret i1 true |
| 229 | } |
| 230 | |
| 231 | define i1 @urem4(i32 %X) { |
| 232 | ; CHECK: @urem4 |
| 233 | %A = urem i32 %X, 15 |
| 234 | %B = icmp ult i32 %A, 10 |
| 235 | ret i1 %B |
| 236 | ; CHECK: ret i1 %B |
| 237 | } |
| 238 | |
Nick Lewycky | 7867927 | 2011-03-04 10:06:52 +0000 | [diff] [blame] | 239 | define i1 @urem5(i16 %X, i32 %Y) { |
| 240 | ; CHECK: @urem5 |
| 241 | %A = zext i16 %X to i32 |
| 242 | %B = urem i32 %A, %Y |
| 243 | %C = icmp slt i32 %B, %Y |
| 244 | ret i1 %C |
| 245 | ; CHECK: ret i1 true |
| 246 | } |
| 247 | |
Nick Lewycky | 84dd4fa | 2011-03-09 06:26:03 +0000 | [diff] [blame^] | 248 | define i1 @urem6(i32 %X, i32 %Y) { |
| 249 | ; CHECK: @urem6 |
| 250 | %A = urem i32 %X, %Y |
| 251 | %B = icmp ugt i32 %Y, %A |
| 252 | ret i1 %B |
| 253 | ; CHECK: ret i1 true |
| 254 | } |
| 255 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 256 | define i1 @srem1(i32 %X) { |
| 257 | ; CHECK: @srem1 |
| 258 | %A = srem i32 %X, -5 |
| 259 | %B = icmp sgt i32 %A, 5 |
| 260 | ret i1 %B |
| 261 | ; CHECK: ret i1 false |
| 262 | } |
| 263 | |
| 264 | define i1 @udiv1(i32 %X) { |
| 265 | ; CHECK: @udiv1 |
| 266 | %A = udiv i32 %X, 1000000 |
| 267 | %B = icmp ult i32 %A, 5000 |
| 268 | ret i1 %B |
| 269 | ; CHECK: ret i1 true |
| 270 | } |
| 271 | |
Nick Lewycky | 58bfcdb | 2011-03-05 05:19:11 +0000 | [diff] [blame] | 272 | define i1 @udiv2(i32 %X, i32 %Y, i32 %Z) { |
| 273 | ; CHECK: @udiv2 |
| 274 | %A = udiv exact i32 10, %Z |
| 275 | %B = udiv exact i32 20, %Z |
| 276 | %C = icmp ult i32 %A, %B |
| 277 | ret i1 %C |
| 278 | ; CHECK: ret i1 true |
| 279 | } |
| 280 | |
Nick Lewycky | 3a73e34 | 2011-03-04 07:00:57 +0000 | [diff] [blame] | 281 | define i1 @sdiv1(i32 %X) { |
| 282 | ; CHECK: @sdiv1 |
| 283 | %A = sdiv i32 %X, 1000000 |
| 284 | %B = icmp slt i32 %A, 3000 |
| 285 | ret i1 %B |
| 286 | ; CHECK: ret i1 true |
| 287 | } |
| 288 | |
| 289 | define i1 @or1(i32 %X) { |
| 290 | ; CHECK: @or1 |
| 291 | %A = or i32 %X, 62 |
| 292 | %B = icmp ult i32 %A, 50 |
| 293 | ret i1 %B |
| 294 | ; CHECK: ret i1 false |
| 295 | } |
| 296 | |
| 297 | define i1 @and1(i32 %X) { |
| 298 | ; CHECK: @and1 |
| 299 | %A = and i32 %X, 62 |
| 300 | %B = icmp ugt i32 %A, 70 |
| 301 | ret i1 %B |
| 302 | ; CHECK: ret i1 false |
| 303 | } |