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Evan Cheng78a9f132011-07-06 22:02:34 +00001//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMMCTARGETDESC_H
15#define ARMMCTARGETDESC_H
16
Evan Cheng94ca42f2011-07-07 00:08:19 +000017#include <string>
18
Evan Cheng78a9f132011-07-06 22:02:34 +000019namespace llvm {
Evan Chengbe740292011-07-23 00:00:19 +000020class MCCodeEmitter;
21class MCContext;
22class MCInstrInfo;
23class MCObjectWriter;
Evan Chengebdeeab2011-07-08 01:53:10 +000024class MCSubtargetInfo;
Evan Cheng94ca42f2011-07-07 00:08:19 +000025class StringRef;
Evan Chengbe740292011-07-23 00:00:19 +000026class Target;
27class TargetAsmBackend;
28class raw_ostream;
Evan Cheng78a9f132011-07-06 22:02:34 +000029
30extern Target TheARMTarget, TheThumbTarget;
Evan Cheng94ca42f2011-07-07 00:08:19 +000031
32namespace ARM_MC {
Evan Chengdb068732011-07-07 08:26:46 +000033 std::string ParseARMTriple(StringRef TT);
Evan Chengebdeeab2011-07-08 01:53:10 +000034
35 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
36 /// This is exposed so Asm parser, etc. do not need to go through
37 /// TargetRegistry.
38 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
39 StringRef FS);
Evan Cheng94ca42f2011-07-07 00:08:19 +000040}
41
Evan Chengbe740292011-07-23 00:00:19 +000042MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII,
43 const MCSubtargetInfo &STI,
44 MCContext &Ctx);
45
46TargetAsmBackend *createARMAsmBackend(const Target&, const std::string &);
47
48/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
49MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
50 bool Is64Bit,
51 uint32_t CPUType,
52 uint32_t CPUSubtype);
53
Evan Cheng78a9f132011-07-06 22:02:34 +000054} // End llvm namespace
55
56// Defines symbolic names for ARM registers. This defines a mapping from
57// register name to register number.
58//
59#define GET_REGINFO_ENUM
60#include "ARMGenRegisterInfo.inc"
61
62// Defines symbolic names for the ARM instructions.
63//
64#define GET_INSTRINFO_ENUM
65#include "ARMGenInstrInfo.inc"
66
Evan Chengc60f9b72011-07-14 20:59:42 +000067#define GET_SUBTARGETINFO_ENUM
68#include "ARMGenSubtargetInfo.inc"
69
Evan Cheng78a9f132011-07-06 22:02:34 +000070#endif