Misha Brukman | cf2b9ac | 2002-11-22 22:43:47 +0000 | [diff] [blame] | 1 | //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 2 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Alkis Evlogimenos | 39354c9 | 2004-03-14 07:19:51 +0000 | [diff] [blame] | 7 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 9 | // |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 10 | // This file contains the X86 implementation of the TargetRegisterInfo class. |
| 11 | // This file is responsible for the frame pointer elimination optimization |
| 12 | // on X86. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 16 | #include "X86.h" |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 17 | #include "X86RegisterInfo.h" |
Misha Brukman | cf2b9ac | 2002-11-22 22:43:47 +0000 | [diff] [blame] | 18 | #include "X86InstrBuilder.h" |
Evan Cheng | e8bd0a3 | 2006-06-06 23:30:24 +0000 | [diff] [blame] | 19 | #include "X86MachineFunctionInfo.h" |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 20 | #include "X86Subtarget.h" |
Evan Cheng | e8bd0a3 | 2006-06-06 23:30:24 +0000 | [diff] [blame] | 21 | #include "X86TargetMachine.h" |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 22 | #include "llvm/Constants.h" |
Evan Cheng | 3649b0e | 2006-06-02 22:38:37 +0000 | [diff] [blame] | 23 | #include "llvm/Function.h" |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 24 | #include "llvm/Type.h" |
Chris Lattner | c8c377d | 2003-07-29 05:14:16 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/ValueTypes.h" |
Misha Brukman | b83b286 | 2002-11-20 18:59:43 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | 198ab64 | 2002-12-15 20:06:35 +0000 | [diff] [blame] | 27 | #include "llvm/CodeGen/MachineFunction.h" |
Dan Gohman | 2dad025 | 2008-07-01 18:15:35 +0000 | [diff] [blame] | 28 | #include "llvm/CodeGen/MachineFunctionPass.h" |
Chris Lattner | aa09b75 | 2002-12-28 21:08:28 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 30 | #include "llvm/CodeGen/MachineModuleInfo.h" |
| 31 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Chris Lattner | af76e59 | 2009-08-22 20:48:53 +0000 | [diff] [blame] | 32 | #include "llvm/MC/MCAsmInfo.h" |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 33 | #include "llvm/Target/TargetFrameLowering.h" |
Evan Cheng | 51cdcd1 | 2006-12-07 01:21:59 +0000 | [diff] [blame] | 34 | #include "llvm/Target/TargetInstrInfo.h" |
Misha Brukman | 83eaa0b | 2004-06-21 21:10:24 +0000 | [diff] [blame] | 35 | #include "llvm/Target/TargetMachine.h" |
Chris Lattner | 0cf0c37 | 2004-07-11 04:17:10 +0000 | [diff] [blame] | 36 | #include "llvm/Target/TargetOptions.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 37 | #include "llvm/ADT/BitVector.h" |
Reid Spencer | 551ccae | 2004-09-01 22:55:40 +0000 | [diff] [blame] | 38 | #include "llvm/ADT/STLExtras.h" |
Torok Edwin | c25e758 | 2009-07-11 20:10:48 +0000 | [diff] [blame] | 39 | #include "llvm/Support/ErrorHandling.h" |
Eric Christopher | e74a088 | 2010-08-05 23:57:43 +0000 | [diff] [blame] | 40 | #include "llvm/Support/CommandLine.h" |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 41 | |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 42 | #define GET_REGINFO_TARGET_DESC |
Evan Cheng | a347f85 | 2011-06-24 01:44:41 +0000 | [diff] [blame] | 43 | #include "X86GenRegisterInfo.inc" |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 44 | |
Chris Lattner | 300d0ed | 2004-02-14 06:00:36 +0000 | [diff] [blame] | 45 | using namespace llvm; |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 46 | |
Anton Korobeynikov | 3346491 | 2010-11-15 00:06:54 +0000 | [diff] [blame] | 47 | cl::opt<bool> |
Eric Christopher | e74a088 | 2010-08-05 23:57:43 +0000 | [diff] [blame] | 48 | ForceStackAlign("force-align-stack", |
| 49 | cl::desc("Force align the stack to the minimum alignment" |
| 50 | " needed for the function."), |
| 51 | cl::init(false), cl::Hidden); |
| 52 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 53 | X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, |
| 54 | const TargetInstrInfo &tii) |
Evan Cheng | 0e6a052 | 2011-07-18 20:57:22 +0000 | [diff] [blame] | 55 | : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() |
| 56 | ? X86::RIP : X86::EIP, |
| 57 | X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false), |
| 58 | X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)), |
| 59 | TM(tm), TII(tii) { |
| 60 | X86_MC::InitLLVM2SEHRegisterMapping(this); |
| 61 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 62 | // Cache some information. |
| 63 | const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); |
| 64 | Is64Bit = Subtarget->is64Bit(); |
Anton Korobeynikov | 1dcce21 | 2008-03-22 21:04:01 +0000 | [diff] [blame] | 65 | IsWin64 = Subtarget->isTargetWin64(); |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 66 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 67 | if (Is64Bit) { |
| 68 | SlotSize = 8; |
| 69 | StackPtr = X86::RSP; |
| 70 | FramePtr = X86::RBP; |
| 71 | } else { |
| 72 | SlotSize = 4; |
| 73 | StackPtr = X86::ESP; |
| 74 | FramePtr = X86::EBP; |
| 75 | } |
| 76 | } |
Chris Lattner | 7ad3e06 | 2003-08-03 15:48:14 +0000 | [diff] [blame] | 77 | |
Bill Wendling | 5cd2791 | 2011-06-30 23:20:32 +0000 | [diff] [blame] | 78 | /// getCompactUnwindRegNum - This function maps the register to the number for |
| 79 | /// compact unwind encoding. Return -1 if the register isn't valid. |
Bill Wendling | 486dd90 | 2011-07-06 20:33:48 +0000 | [diff] [blame] | 80 | int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { |
| 81 | switch (getLLVMRegNum(RegNum, isEH)) { |
Bill Wendling | 5cd2791 | 2011-06-30 23:20:32 +0000 | [diff] [blame] | 82 | case X86::EBX: case X86::RBX: return 1; |
Bill Wendling | 2374cb8 | 2011-06-30 23:47:14 +0000 | [diff] [blame] | 83 | case X86::ECX: case X86::R12: return 2; |
| 84 | case X86::EDX: case X86::R13: return 3; |
| 85 | case X86::EDI: case X86::R14: return 4; |
| 86 | case X86::ESI: case X86::R15: return 5; |
Bill Wendling | 5cd2791 | 2011-06-30 23:20:32 +0000 | [diff] [blame] | 87 | case X86::EBP: case X86::RBP: return 6; |
| 88 | } |
| 89 | |
| 90 | return -1; |
| 91 | } |
| 92 | |
Charles Davis | 6b918b8 | 2011-05-24 16:57:53 +0000 | [diff] [blame] | 93 | int |
| 94 | X86RegisterInfo::getSEHRegNum(unsigned i) const { |
Evan Cheng | 0e6a052 | 2011-07-18 20:57:22 +0000 | [diff] [blame] | 95 | int reg = X86_MC::getX86RegNum(i); |
Charles Davis | 6b918b8 | 2011-05-24 16:57:53 +0000 | [diff] [blame] | 96 | switch (i) { |
| 97 | case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: |
| 98 | case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: |
| 99 | case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: |
| 100 | case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: |
| 101 | case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: |
| 102 | case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: |
| 103 | case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: |
| 104 | case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: |
| 105 | case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: |
| 106 | case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: |
| 107 | case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: |
| 108 | case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: |
| 109 | reg += 8; |
| 110 | } |
| 111 | return reg; |
| 112 | } |
| 113 | |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 114 | const TargetRegisterClass * |
Jakob Stoklund Olesen | 9bb272c | 2011-10-05 20:26:33 +0000 | [diff] [blame] | 115 | X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, |
| 116 | unsigned Idx) const { |
| 117 | // The sub_8bit sub-register index is more constrained in 32-bit mode. |
| 118 | // It behaves just like the sub_8bit_hi index. |
| 119 | if (!Is64Bit && Idx == X86::sub_8bit) |
| 120 | Idx = X86::sub_8bit_hi; |
| 121 | |
| 122 | // Forward to TableGen's default version. |
| 123 | return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); |
| 124 | } |
| 125 | |
| 126 | const TargetRegisterClass * |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 127 | X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, |
| 128 | const TargetRegisterClass *B, |
| 129 | unsigned SubIdx) const { |
| 130 | switch (SubIdx) { |
| 131 | default: return 0; |
Jakob Stoklund Olesen | 22c0e97 | 2010-05-25 17:04:16 +0000 | [diff] [blame] | 132 | case X86::sub_8bit: |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 133 | if (B == &X86::GR8RegClass) { |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 134 | if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8) |
| 135 | return A; |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 136 | } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) { |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 137 | if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass || |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 138 | A == &X86::GR64_NOREXRegClass || |
| 139 | A == &X86::GR64_NOSPRegClass || |
| 140 | A == &X86::GR64_NOREX_NOSPRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 141 | return &X86::GR64_ABCDRegClass; |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 142 | else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass || |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 143 | A == &X86::GR32_NOREXRegClass || |
| 144 | A == &X86::GR32_NOSPRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 145 | return &X86::GR32_ABCDRegClass; |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 146 | else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass || |
| 147 | A == &X86::GR16_NOREXRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 148 | return &X86::GR16_ABCDRegClass; |
| 149 | } else if (B == &X86::GR8_NOREXRegClass) { |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 150 | if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass || |
| 151 | A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 152 | return &X86::GR64_NOREXRegClass; |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 153 | else if (A == &X86::GR64_ABCDRegClass) |
| 154 | return &X86::GR64_ABCDRegClass; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 155 | else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass || |
| 156 | A == &X86::GR32_NOSPRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 157 | return &X86::GR32_NOREXRegClass; |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 158 | else if (A == &X86::GR32_ABCDRegClass) |
| 159 | return &X86::GR32_ABCDRegClass; |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 160 | else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass) |
| 161 | return &X86::GR16_NOREXRegClass; |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 162 | else if (A == &X86::GR16_ABCDRegClass) |
| 163 | return &X86::GR16_ABCDRegClass; |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 164 | } |
| 165 | break; |
Jakob Stoklund Olesen | 22c0e97 | 2010-05-25 17:04:16 +0000 | [diff] [blame] | 166 | case X86::sub_8bit_hi: |
Jakob Stoklund Olesen | fa226bc | 2011-06-02 05:43:46 +0000 | [diff] [blame] | 167 | if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass)) |
Jakob Stoklund Olesen | 4f5de9b | 2011-05-04 23:54:54 +0000 | [diff] [blame] | 168 | switch (A->getSize()) { |
| 169 | case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass); |
| 170 | case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass); |
| 171 | case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass); |
| 172 | default: return 0; |
| 173 | } |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 174 | break; |
Jakob Stoklund Olesen | 22c0e97 | 2010-05-25 17:04:16 +0000 | [diff] [blame] | 175 | case X86::sub_16bit: |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 176 | if (B == &X86::GR16RegClass) { |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 177 | if (A->getSize() == 4 || A->getSize() == 8) |
| 178 | return A; |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 179 | } else if (B == &X86::GR16_ABCDRegClass) { |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 180 | if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass || |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 181 | A == &X86::GR64_NOREXRegClass || |
| 182 | A == &X86::GR64_NOSPRegClass || |
| 183 | A == &X86::GR64_NOREX_NOSPRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 184 | return &X86::GR64_ABCDRegClass; |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 185 | else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass || |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 186 | A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 187 | return &X86::GR32_ABCDRegClass; |
| 188 | } else if (B == &X86::GR16_NOREXRegClass) { |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 189 | if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass || |
| 190 | A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 191 | return &X86::GR64_NOREXRegClass; |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 192 | else if (A == &X86::GR64_ABCDRegClass) |
| 193 | return &X86::GR64_ABCDRegClass; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 194 | else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass || |
| 195 | A == &X86::GR32_NOSPRegClass) |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 196 | return &X86::GR32_NOREXRegClass; |
| 197 | else if (A == &X86::GR32_ABCDRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 198 | return &X86::GR64_ABCDRegClass; |
| 199 | } |
| 200 | break; |
Jakob Stoklund Olesen | 22c0e97 | 2010-05-25 17:04:16 +0000 | [diff] [blame] | 201 | case X86::sub_32bit: |
Jakob Stoklund Olesen | 8f42a19 | 2010-10-06 23:56:46 +0000 | [diff] [blame] | 202 | if (B == &X86::GR32RegClass) { |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 203 | if (A->getSize() == 8) |
| 204 | return A; |
Jakob Stoklund Olesen | 8f42a19 | 2010-10-06 23:56:46 +0000 | [diff] [blame] | 205 | } else if (B == &X86::GR32_NOSPRegClass) { |
Jakob Stoklund Olesen | 8456c4f | 2010-10-07 18:47:10 +0000 | [diff] [blame] | 206 | if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass) |
Jakob Stoklund Olesen | 8f42a19 | 2010-10-06 23:56:46 +0000 | [diff] [blame] | 207 | return &X86::GR64_NOSPRegClass; |
| 208 | if (A->getSize() == 8) |
| 209 | return getCommonSubClass(A, &X86::GR64_NOSPRegClass); |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 210 | } else if (B == &X86::GR32_ABCDRegClass) { |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 211 | if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass || |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 212 | A == &X86::GR64_NOREXRegClass || |
| 213 | A == &X86::GR64_NOSPRegClass || |
| 214 | A == &X86::GR64_NOREX_NOSPRegClass) |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 215 | return &X86::GR64_ABCDRegClass; |
| 216 | } else if (B == &X86::GR32_NOREXRegClass) { |
Cameron Zwarich | f5e771d | 2011-05-27 22:26:04 +0000 | [diff] [blame] | 217 | if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass) |
| 218 | return &X86::GR64_NOREXRegClass; |
| 219 | else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) |
| 220 | return &X86::GR64_NOREX_NOSPRegClass; |
| 221 | else if (A == &X86::GR64_ABCDRegClass) |
| 222 | return &X86::GR64_ABCDRegClass; |
| 223 | } else if (B == &X86::GR32_NOREX_NOSPRegClass) { |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 224 | if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass || |
| 225 | A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) |
Cameron Zwarich | f5e771d | 2011-05-27 22:26:04 +0000 | [diff] [blame] | 226 | return &X86::GR64_NOREX_NOSPRegClass; |
Evan Cheng | 753480a | 2009-07-20 19:47:55 +0000 | [diff] [blame] | 227 | else if (A == &X86::GR64_ABCDRegClass) |
| 228 | return &X86::GR64_ABCDRegClass; |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 229 | } |
| 230 | break; |
Jakob Stoklund Olesen | b539852 | 2010-05-25 19:49:40 +0000 | [diff] [blame] | 231 | case X86::sub_ss: |
| 232 | if (B == &X86::FR32RegClass) |
| 233 | return A; |
| 234 | break; |
| 235 | case X86::sub_sd: |
| 236 | if (B == &X86::FR64RegClass) |
| 237 | return A; |
| 238 | break; |
| 239 | case X86::sub_xmm: |
| 240 | if (B == &X86::VR128RegClass) |
| 241 | return A; |
| 242 | break; |
Evan Cheng | 5248468 | 2009-07-18 02:10:10 +0000 | [diff] [blame] | 243 | } |
| 244 | return 0; |
| 245 | } |
| 246 | |
Jakob Stoklund Olesen | c9e5015 | 2011-04-26 18:52:33 +0000 | [diff] [blame] | 247 | const TargetRegisterClass* |
| 248 | X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{ |
Jakob Stoklund Olesen | b7994fe | 2011-10-08 20:20:03 +0000 | [diff] [blame] | 249 | // Don't allow super-classes of GR8_NOREX. This class is only used after |
| 250 | // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied |
| 251 | // to the full GR8 register class in 64-bit mode, so we cannot allow the |
| 252 | // reigster class inflation. |
| 253 | // |
| 254 | // The GR8_NOREX class is always used in a way that won't be constrained to a |
| 255 | // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the |
| 256 | // full GR8 class. |
| 257 | if (RC == X86::GR8_NOREXRegisterClass) |
| 258 | return RC; |
| 259 | |
Jakob Stoklund Olesen | c9e5015 | 2011-04-26 18:52:33 +0000 | [diff] [blame] | 260 | const TargetRegisterClass *Super = RC; |
Jakob Stoklund Olesen | c8e2bb6 | 2011-09-30 22:19:07 +0000 | [diff] [blame] | 261 | TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); |
Jakob Stoklund Olesen | c9e5015 | 2011-04-26 18:52:33 +0000 | [diff] [blame] | 262 | do { |
| 263 | switch (Super->getID()) { |
| 264 | case X86::GR8RegClassID: |
| 265 | case X86::GR16RegClassID: |
| 266 | case X86::GR32RegClassID: |
| 267 | case X86::GR64RegClassID: |
| 268 | case X86::FR32RegClassID: |
| 269 | case X86::FR64RegClassID: |
| 270 | case X86::RFP32RegClassID: |
| 271 | case X86::RFP64RegClassID: |
| 272 | case X86::RFP80RegClassID: |
| 273 | case X86::VR128RegClassID: |
| 274 | case X86::VR256RegClassID: |
| 275 | // Don't return a super-class that would shrink the spill size. |
| 276 | // That can happen with the vector and float classes. |
| 277 | if (Super->getSize() == RC->getSize()) |
| 278 | return Super; |
| 279 | } |
| 280 | Super = *I++; |
| 281 | } while (Super); |
| 282 | return RC; |
| 283 | } |
| 284 | |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 285 | const TargetRegisterClass * |
| 286 | X86RegisterInfo::getPointerRegClass(unsigned Kind) const { |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 287 | switch (Kind) { |
| 288 | default: llvm_unreachable("Unexpected Kind in getPointerRegClass!"); |
| 289 | case 0: // Normal GPRs. |
| 290 | if (TM.getSubtarget<X86Subtarget>().is64Bit()) |
| 291 | return &X86::GR64RegClass; |
| 292 | return &X86::GR32RegClass; |
NAKAMURA Takumi | b901076 | 2011-01-26 01:27:58 +0000 | [diff] [blame] | 293 | case 1: // Normal GPRs except the stack pointer (for encoding reasons). |
Dan Gohman | 74f6f9a | 2009-08-05 17:40:24 +0000 | [diff] [blame] | 294 | if (TM.getSubtarget<X86Subtarget>().is64Bit()) |
| 295 | return &X86::GR64_NOSPRegClass; |
| 296 | return &X86::GR32_NOSPRegClass; |
NAKAMURA Takumi | 7754f85 | 2011-01-26 02:04:09 +0000 | [diff] [blame] | 297 | case 2: // Available for tailcall (not callee-saved GPRs). |
| 298 | if (TM.getSubtarget<X86Subtarget>().isTargetWin64()) |
| 299 | return &X86::GR64_TCW64RegClass; |
| 300 | if (TM.getSubtarget<X86Subtarget>().is64Bit()) |
| 301 | return &X86::GR64_TCRegClass; |
| 302 | return &X86::GR32_TCRegClass; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 303 | } |
Evan Cheng | 770bcc7 | 2009-02-06 17:43:24 +0000 | [diff] [blame] | 304 | } |
| 305 | |
Evan Cheng | ff11026 | 2007-09-26 21:31:07 +0000 | [diff] [blame] | 306 | const TargetRegisterClass * |
| 307 | X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { |
Anton Korobeynikov | 4aefd6b | 2008-02-20 12:07:57 +0000 | [diff] [blame] | 308 | if (RC == &X86::CCRRegClass) { |
Evan Cheng | 3f2d9ec | 2007-09-27 21:50:05 +0000 | [diff] [blame] | 309 | if (Is64Bit) |
| 310 | return &X86::GR64RegClass; |
| 311 | else |
| 312 | return &X86::GR32RegClass; |
Anton Korobeynikov | 4aefd6b | 2008-02-20 12:07:57 +0000 | [diff] [blame] | 313 | } |
Evan Cheng | b0519e1 | 2011-03-10 00:16:32 +0000 | [diff] [blame] | 314 | return RC; |
Evan Cheng | ff11026 | 2007-09-26 21:31:07 +0000 | [diff] [blame] | 315 | } |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 316 | |
Cameron Zwarich | be2119e | 2011-03-07 21:56:36 +0000 | [diff] [blame] | 317 | unsigned |
| 318 | X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, |
| 319 | MachineFunction &MF) const { |
| 320 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
| 321 | |
| 322 | unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; |
| 323 | switch (RC->getID()) { |
| 324 | default: |
| 325 | return 0; |
| 326 | case X86::GR32RegClassID: |
| 327 | return 4 - FPDiff; |
| 328 | case X86::GR64RegClassID: |
| 329 | return 12 - FPDiff; |
| 330 | case X86::VR128RegClassID: |
| 331 | return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4; |
| 332 | case X86::VR64RegClassID: |
| 333 | return 4; |
| 334 | } |
| 335 | } |
| 336 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 337 | const unsigned * |
| 338 | X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
Anton Korobeynikov | b84c167 | 2008-09-08 21:12:47 +0000 | [diff] [blame] | 339 | bool callsEHReturn = false; |
Chris Lattner | 2968943 | 2010-03-11 00:22:57 +0000 | [diff] [blame] | 340 | bool ghcCall = false; |
Anton Korobeynikov | b84c167 | 2008-09-08 21:12:47 +0000 | [diff] [blame] | 341 | |
| 342 | if (MF) { |
Chris Lattner | a267b00 | 2010-04-05 05:57:52 +0000 | [diff] [blame] | 343 | callsEHReturn = MF->getMMI().callsEHReturn(); |
Chris Lattner | 2968943 | 2010-03-11 00:22:57 +0000 | [diff] [blame] | 344 | const Function *F = MF->getFunction(); |
| 345 | ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); |
Anton Korobeynikov | b84c167 | 2008-09-08 21:12:47 +0000 | [diff] [blame] | 346 | } |
| 347 | |
Chris Lattner | 2968943 | 2010-03-11 00:22:57 +0000 | [diff] [blame] | 348 | static const unsigned GhcCalleeSavedRegs[] = { |
| 349 | 0 |
| 350 | }; |
| 351 | |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 352 | static const unsigned CalleeSavedRegs32Bit[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 353 | X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 |
| 354 | }; |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 355 | |
| 356 | static const unsigned CalleeSavedRegs32EHRet[] = { |
| 357 | X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 |
| 358 | }; |
| 359 | |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 360 | static const unsigned CalleeSavedRegs64Bit[] = { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 361 | X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 |
| 362 | }; |
| 363 | |
Anton Korobeynikov | b84c167 | 2008-09-08 21:12:47 +0000 | [diff] [blame] | 364 | static const unsigned CalleeSavedRegs64EHRet[] = { |
| 365 | X86::RAX, X86::RDX, X86::RBX, X86::R12, |
| 366 | X86::R13, X86::R14, X86::R15, X86::RBP, 0 |
| 367 | }; |
| 368 | |
Anton Korobeynikov | 1dcce21 | 2008-03-22 21:04:01 +0000 | [diff] [blame] | 369 | static const unsigned CalleeSavedRegsWin64[] = { |
Anton Korobeynikov | 5979d71 | 2008-09-24 22:03:04 +0000 | [diff] [blame] | 370 | X86::RBX, X86::RBP, X86::RDI, X86::RSI, |
| 371 | X86::R12, X86::R13, X86::R14, X86::R15, |
| 372 | X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, |
| 373 | X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, |
| 374 | X86::XMM14, X86::XMM15, 0 |
Anton Korobeynikov | 1dcce21 | 2008-03-22 21:04:01 +0000 | [diff] [blame] | 375 | }; |
| 376 | |
Chris Lattner | 2968943 | 2010-03-11 00:22:57 +0000 | [diff] [blame] | 377 | if (ghcCall) { |
| 378 | return GhcCalleeSavedRegs; |
| 379 | } else if (Is64Bit) { |
Anton Korobeynikov | 1dcce21 | 2008-03-22 21:04:01 +0000 | [diff] [blame] | 380 | if (IsWin64) |
| 381 | return CalleeSavedRegsWin64; |
| 382 | else |
Anton Korobeynikov | b84c167 | 2008-09-08 21:12:47 +0000 | [diff] [blame] | 383 | return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit); |
Anton Korobeynikov | 1dcce21 | 2008-03-22 21:04:01 +0000 | [diff] [blame] | 384 | } else { |
Anton Korobeynikov | b84c167 | 2008-09-08 21:12:47 +0000 | [diff] [blame] | 385 | return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 386 | } |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 387 | } |
| 388 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 389 | BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 390 | BitVector Reserved(getNumRegs()); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 391 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 392 | |
Dan Gohman | a32b7ac | 2008-12-18 01:05:09 +0000 | [diff] [blame] | 393 | // Set the stack-pointer register and its aliases as reserved. |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 394 | Reserved.set(X86::RSP); |
| 395 | Reserved.set(X86::ESP); |
| 396 | Reserved.set(X86::SP); |
| 397 | Reserved.set(X86::SPL); |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 398 | |
Jakob Stoklund Olesen | 52cd548 | 2009-11-13 21:56:01 +0000 | [diff] [blame] | 399 | // Set the instruction pointer register and its aliases as reserved. |
| 400 | Reserved.set(X86::RIP); |
| 401 | Reserved.set(X86::EIP); |
| 402 | Reserved.set(X86::IP); |
| 403 | |
Dan Gohman | a32b7ac | 2008-12-18 01:05:09 +0000 | [diff] [blame] | 404 | // Set the frame-pointer register and its aliases as reserved if needed. |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 405 | if (TFI->hasFP(MF)) { |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 406 | Reserved.set(X86::RBP); |
| 407 | Reserved.set(X86::EBP); |
| 408 | Reserved.set(X86::BP); |
| 409 | Reserved.set(X86::BPL); |
| 410 | } |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 411 | |
Cameron Zwarich | e4c6445 | 2011-05-18 22:24:48 +0000 | [diff] [blame] | 412 | // Mark the segment registers as reserved. |
| 413 | Reserved.set(X86::CS); |
| 414 | Reserved.set(X86::SS); |
| 415 | Reserved.set(X86::DS); |
| 416 | Reserved.set(X86::ES); |
| 417 | Reserved.set(X86::FS); |
| 418 | Reserved.set(X86::GS); |
| 419 | |
Jakob Stoklund Olesen | 2a9d1ca | 2011-06-09 16:56:59 +0000 | [diff] [blame] | 420 | // Reserve the registers that only exist in 64-bit mode. |
| 421 | if (!Is64Bit) { |
Jakob Stoklund Olesen | aad458d | 2011-06-17 23:15:00 +0000 | [diff] [blame] | 422 | // These 8-bit registers are part of the x86-64 extension even though their |
| 423 | // super-registers are old 32-bits. |
| 424 | Reserved.set(X86::SIL); |
| 425 | Reserved.set(X86::DIL); |
| 426 | Reserved.set(X86::BPL); |
| 427 | Reserved.set(X86::SPL); |
| 428 | |
Jakob Stoklund Olesen | 2a9d1ca | 2011-06-09 16:56:59 +0000 | [diff] [blame] | 429 | for (unsigned n = 0; n != 8; ++n) { |
Jakob Stoklund Olesen | aad458d | 2011-06-17 23:15:00 +0000 | [diff] [blame] | 430 | // R8, R9, ... |
Jakob Stoklund Olesen | 2a9d1ca | 2011-06-09 16:56:59 +0000 | [diff] [blame] | 431 | const unsigned GPR64[] = { |
| 432 | X86::R8, X86::R9, X86::R10, X86::R11, |
| 433 | X86::R12, X86::R13, X86::R14, X86::R15 |
| 434 | }; |
Jakob Stoklund Olesen | aad458d | 2011-06-17 23:15:00 +0000 | [diff] [blame] | 435 | for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI) |
Jakob Stoklund Olesen | 2a9d1ca | 2011-06-09 16:56:59 +0000 | [diff] [blame] | 436 | Reserved.set(Reg); |
| 437 | |
| 438 | // XMM8, XMM9, ... |
| 439 | assert(X86::XMM15 == X86::XMM8+7); |
| 440 | for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI; |
| 441 | ++AI) |
| 442 | Reserved.set(Reg); |
| 443 | } |
| 444 | } |
| 445 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 446 | return Reserved; |
| 447 | } |
| 448 | |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 449 | //===----------------------------------------------------------------------===// |
| 450 | // Stack Frame Processing methods |
| 451 | //===----------------------------------------------------------------------===// |
| 452 | |
Jim Grosbach | e45ab8a | 2010-01-19 18:31:11 +0000 | [diff] [blame] | 453 | bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const { |
| 454 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Nick Lewycky | 8a8d479 | 2011-12-02 22:16:29 +0000 | [diff] [blame^] | 455 | return (MF.getTarget().Options.RealignStack && |
Jim Grosbach | e45ab8a | 2010-01-19 18:31:11 +0000 | [diff] [blame] | 456 | !MFI->hasVarSizedObjects()); |
| 457 | } |
| 458 | |
Anton Korobeynikov | 9bbbea5 | 2008-04-23 18:15:48 +0000 | [diff] [blame] | 459 | bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { |
Nick Lewycky | 9c0f146 | 2009-03-19 05:51:39 +0000 | [diff] [blame] | 460 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Charles Davis | 5dfa267 | 2010-02-19 18:17:13 +0000 | [diff] [blame] | 461 | const Function *F = MF.getFunction(); |
Evan Cheng | 2fa82bc | 2011-06-23 01:53:43 +0000 | [diff] [blame] | 462 | unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); |
Eric Christopher | 697cba8 | 2010-07-17 00:33:04 +0000 | [diff] [blame] | 463 | bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || |
| 464 | F->hasFnAttr(Attribute::StackAlignment)); |
Anton Korobeynikov | 9bbbea5 | 2008-04-23 18:15:48 +0000 | [diff] [blame] | 465 | |
Anton Korobeynikov | 35410a4 | 2008-04-23 18:16:43 +0000 | [diff] [blame] | 466 | // FIXME: Currently we don't support stack realignment for functions with |
Anton Korobeynikov | b23f3aa | 2009-11-14 18:01:41 +0000 | [diff] [blame] | 467 | // variable-sized allocas. |
Eric Christopher | acdb4b9 | 2010-07-17 00:25:41 +0000 | [diff] [blame] | 468 | // FIXME: It's more complicated than this... |
Anton Korobeynikov | b23f3aa | 2009-11-14 18:01:41 +0000 | [diff] [blame] | 469 | if (0 && requiresRealignment && MFI->hasVarSizedObjects()) |
Chris Lattner | 75361b6 | 2010-04-07 22:58:41 +0000 | [diff] [blame] | 470 | report_fatal_error( |
Chris Lattner | 7a2bdde | 2011-04-15 05:18:47 +0000 | [diff] [blame] | 471 | "Stack realignment in presence of dynamic allocas is not supported"); |
NAKAMURA Takumi | c5b7a42 | 2011-01-26 01:28:06 +0000 | [diff] [blame] | 472 | |
Eric Christopher | e74a088 | 2010-08-05 23:57:43 +0000 | [diff] [blame] | 473 | // If we've requested that we force align the stack do so now. |
| 474 | if (ForceStackAlign) |
| 475 | return canRealignStack(MF); |
NAKAMURA Takumi | c5b7a42 | 2011-01-26 01:28:06 +0000 | [diff] [blame] | 476 | |
Eric Christopher | acdb4b9 | 2010-07-17 00:25:41 +0000 | [diff] [blame] | 477 | return requiresRealignment && canRealignStack(MF); |
Anton Korobeynikov | 9bbbea5 | 2008-04-23 18:15:48 +0000 | [diff] [blame] | 478 | } |
| 479 | |
Eric Christopher | 72852a8 | 2010-07-20 06:52:21 +0000 | [diff] [blame] | 480 | bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, |
| 481 | unsigned Reg, int &FrameIdx) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 482 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 483 | |
| 484 | if (Reg == FramePtr && TFI->hasFP(MF)) { |
Evan Cheng | 910139f | 2009-07-09 06:53:48 +0000 | [diff] [blame] | 485 | FrameIdx = MF.getFrameInfo()->getObjectIndexBegin(); |
| 486 | return true; |
| 487 | } |
| 488 | return false; |
| 489 | } |
| 490 | |
Dan Gohman | 7c2e039 | 2010-05-19 00:53:19 +0000 | [diff] [blame] | 491 | static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) { |
| 492 | if (is64Bit) { |
| 493 | if (isInt<8>(Imm)) |
| 494 | return X86::SUB64ri8; |
| 495 | return X86::SUB64ri32; |
| 496 | } else { |
| 497 | if (isInt<8>(Imm)) |
| 498 | return X86::SUB32ri8; |
| 499 | return X86::SUB32ri; |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) { |
| 504 | if (is64Bit) { |
| 505 | if (isInt<8>(Imm)) |
| 506 | return X86::ADD64ri8; |
| 507 | return X86::ADD64ri32; |
| 508 | } else { |
| 509 | if (isInt<8>(Imm)) |
| 510 | return X86::ADD32ri8; |
| 511 | return X86::ADD32ri; |
| 512 | } |
| 513 | } |
| 514 | |
Chris Lattner | bb07ef9 | 2004-02-14 19:49:54 +0000 | [diff] [blame] | 515 | void X86RegisterInfo:: |
| 516 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 517 | MachineBasicBlock::iterator I) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 518 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 519 | bool reseveCallFrame = TFI->hasReservedCallFrame(MF); |
| 520 | int Opcode = I->getOpcode(); |
Evan Cheng | d5b03f2 | 2011-06-28 21:14:33 +0000 | [diff] [blame] | 521 | bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode(); |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 522 | DebugLoc DL = I->getDebugLoc(); |
| 523 | uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0; |
| 524 | uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0; |
| 525 | I = MBB.erase(I); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 526 | |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 527 | if (!reseveCallFrame) { |
Evan Cheng | 7e7bbf8 | 2007-07-19 00:42:05 +0000 | [diff] [blame] | 528 | // If the stack pointer can be changed after prologue, turn the |
| 529 | // adjcallstackup instruction into a 'sub ESP, <amt>' and the |
| 530 | // adjcallstackdown instruction into 'add ESP, <amt>' |
| 531 | // TODO: consider using push / pop instead of sub + store / add |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 532 | if (Amount == 0) |
| 533 | return; |
Chris Lattner | f158da2 | 2003-01-16 02:20:12 +0000 | [diff] [blame] | 534 | |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 535 | // We need to keep the stack aligned properly. To do this, we round the |
| 536 | // amount of space needed for the outgoing arguments up to the next |
| 537 | // alignment boundary. |
Evan Cheng | 2fa82bc | 2011-06-23 01:53:43 +0000 | [diff] [blame] | 538 | unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 539 | Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign; |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 540 | |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 541 | MachineInstr *New = 0; |
Evan Cheng | d5b03f2 | 2011-06-28 21:14:33 +0000 | [diff] [blame] | 542 | if (Opcode == TII.getCallFrameSetupOpcode()) { |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 543 | New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)), |
| 544 | StackPtr) |
| 545 | .addReg(StackPtr) |
| 546 | .addImm(Amount); |
| 547 | } else { |
Evan Cheng | d5b03f2 | 2011-06-28 21:14:33 +0000 | [diff] [blame] | 548 | assert(Opcode == TII.getCallFrameDestroyOpcode()); |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 549 | |
| 550 | // Factor out the amount the callee already popped. |
| 551 | Amount -= CalleeAmt; |
NAKAMURA Takumi | c5b7a42 | 2011-01-26 01:28:06 +0000 | [diff] [blame] | 552 | |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 553 | if (Amount) { |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 554 | unsigned Opc = getADDriOpcode(Is64Bit, Amount); |
| 555 | New = BuildMI(MF, DL, TII.get(Opc), StackPtr) |
| 556 | .addReg(StackPtr).addImm(Amount); |
Dan Gohman | d293e0d | 2009-02-11 19:50:24 +0000 | [diff] [blame] | 557 | } |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 558 | } |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 559 | |
| 560 | if (New) { |
| 561 | // The EFLAGS implicit def is dead. |
| 562 | New->getOperand(3).setIsDead(); |
| 563 | |
| 564 | // Replace the pseudo instruction with a new instruction. |
| 565 | MBB.insert(I, New); |
| 566 | } |
| 567 | |
| 568 | return; |
| 569 | } |
| 570 | |
Evan Cheng | d5b03f2 | 2011-06-28 21:14:33 +0000 | [diff] [blame] | 571 | if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) { |
Chris Lattner | 3648c67 | 2005-05-13 21:44:04 +0000 | [diff] [blame] | 572 | // If we are performing frame pointer elimination and if the callee pops |
| 573 | // something off the stack pointer, add it back. We do this until we have |
| 574 | // more advanced stack pointer tracking ability. |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 575 | unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt); |
| 576 | MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr) |
| 577 | .addReg(StackPtr).addImm(CalleeAmt); |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 578 | |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 579 | // The EFLAGS implicit def is dead. |
| 580 | New->getOperand(3).setIsDead(); |
Jakob Stoklund Olesen | 6531bdd | 2011-06-29 23:11:39 +0000 | [diff] [blame] | 581 | |
| 582 | // We are not tracking the stack pointer adjustment by the callee, so make |
| 583 | // sure we restore the stack pointer immediately after the call, there may |
| 584 | // be spill code inserted between the CALL and ADJCALLSTACKUP instructions. |
| 585 | MachineBasicBlock::iterator B = MBB.begin(); |
| 586 | while (I != B && !llvm::prior(I)->getDesc().isCall()) |
| 587 | --I; |
Evan Cheng | e4a2dd2 | 2010-12-23 23:54:17 +0000 | [diff] [blame] | 588 | MBB.insert(I, New); |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 589 | } |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 590 | } |
| 591 | |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 592 | void |
Jim Grosbach | b58f498 | 2009-10-07 17:12:56 +0000 | [diff] [blame] | 593 | X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 594 | int SPAdj, RegScavenger *RS) const{ |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 595 | assert(SPAdj == 0 && "Unexpected"); |
| 596 | |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 597 | unsigned i = 0; |
Alkis Evlogimenos | c0b9dc5 | 2004-02-12 02:27:10 +0000 | [diff] [blame] | 598 | MachineInstr &MI = *II; |
Nate Begeman | f8be5e9 | 2004-08-14 22:05:10 +0000 | [diff] [blame] | 599 | MachineFunction &MF = *MI.getParent()->getParent(); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 600 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 601 | |
Dan Gohman | d735b80 | 2008-10-03 15:45:36 +0000 | [diff] [blame] | 602 | while (!MI.getOperand(i).isFI()) { |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 603 | ++i; |
| 604 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 605 | } |
| 606 | |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 607 | int FrameIndex = MI.getOperand(i).getIndex(); |
Anton Korobeynikov | 8e91ec5 | 2008-04-23 18:21:02 +0000 | [diff] [blame] | 608 | unsigned BasePtr; |
Bill Wendling | 80c7643 | 2009-08-16 11:00:26 +0000 | [diff] [blame] | 609 | |
Evan Cheng | 3f54c64 | 2010-04-29 05:08:22 +0000 | [diff] [blame] | 610 | unsigned Opc = MI.getOpcode(); |
| 611 | bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm; |
Anton Korobeynikov | 8e91ec5 | 2008-04-23 18:21:02 +0000 | [diff] [blame] | 612 | if (needsStackRealignment(MF)) |
| 613 | BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); |
Evan Cheng | 3f54c64 | 2010-04-29 05:08:22 +0000 | [diff] [blame] | 614 | else if (AfterFPPop) |
| 615 | BasePtr = StackPtr; |
Anton Korobeynikov | 8e91ec5 | 2008-04-23 18:21:02 +0000 | [diff] [blame] | 616 | else |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 617 | BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr); |
Anton Korobeynikov | 8e91ec5 | 2008-04-23 18:21:02 +0000 | [diff] [blame] | 618 | |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 619 | // This must be part of a four operand memory reference. Replace the |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 620 | // FrameIndex with base register with EBP. Add an offset to the offset. |
Anton Korobeynikov | 8e91ec5 | 2008-04-23 18:21:02 +0000 | [diff] [blame] | 621 | MI.getOperand(i).ChangeToRegister(BasePtr, false); |
Chris Lattner | d264bec | 2003-01-13 00:50:33 +0000 | [diff] [blame] | 622 | |
Dan Gohman | 8277970 | 2008-12-24 00:27:51 +0000 | [diff] [blame] | 623 | // Now add the frame object offset to the offset from EBP. |
Evan Cheng | 3f54c64 | 2010-04-29 05:08:22 +0000 | [diff] [blame] | 624 | int FIOffset; |
| 625 | if (AfterFPPop) { |
| 626 | // Tail call jmp happens after FP is popped. |
Evan Cheng | 3f54c64 | 2010-04-29 05:08:22 +0000 | [diff] [blame] | 627 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 628 | FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea(); |
Evan Cheng | 3f54c64 | 2010-04-29 05:08:22 +0000 | [diff] [blame] | 629 | } else |
Anton Korobeynikov | 82f5874 | 2010-11-20 15:59:32 +0000 | [diff] [blame] | 630 | FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex); |
Evan Cheng | 3f54c64 | 2010-04-29 05:08:22 +0000 | [diff] [blame] | 631 | |
Dan Gohman | 8277970 | 2008-12-24 00:27:51 +0000 | [diff] [blame] | 632 | if (MI.getOperand(i+3).isImm()) { |
| 633 | // Offset is a 32-bit integer. |
Eli Friedman | 5cf2ee1 | 2011-07-13 00:44:29 +0000 | [diff] [blame] | 634 | int Imm = (int)(MI.getOperand(i + 3).getImm()); |
| 635 | int Offset = FIOffset + Imm; |
Eli Friedman | 7e94501 | 2011-07-14 00:22:31 +0000 | [diff] [blame] | 636 | assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) && |
| 637 | "Requesting 64-bit offset in 32-bit immediate!"); |
David Greene | 3f2bf85 | 2009-11-12 20:49:22 +0000 | [diff] [blame] | 638 | MI.getOperand(i + 3).ChangeToImmediate(Offset); |
Dan Gohman | 8277970 | 2008-12-24 00:27:51 +0000 | [diff] [blame] | 639 | } else { |
| 640 | // Offset is symbolic. This is extremely rare. |
Evan Cheng | 3f54c64 | 2010-04-29 05:08:22 +0000 | [diff] [blame] | 641 | uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset(); |
Dan Gohman | 8277970 | 2008-12-24 00:27:51 +0000 | [diff] [blame] | 642 | MI.getOperand(i+3).setOffset(Offset); |
| 643 | } |
Chris Lattner | 3c1c03d | 2002-12-28 20:32:28 +0000 | [diff] [blame] | 644 | } |
| 645 | |
David Greene | 3f2bf85 | 2009-11-12 20:49:22 +0000 | [diff] [blame] | 646 | unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 647 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 648 | return TFI->hasFP(MF) ? FramePtr : StackPtr; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 649 | } |
| 650 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 651 | unsigned X86RegisterInfo::getEHExceptionRegister() const { |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 652 | llvm_unreachable("What is the exception register"); |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | unsigned X86RegisterInfo::getEHHandlerRegister() const { |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 657 | llvm_unreachable("What is the exception handler register"); |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 658 | return 0; |
| 659 | } |
| 660 | |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 661 | namespace llvm { |
Owen Anderson | e50ed30 | 2009-08-10 22:56:29 +0000 | [diff] [blame] | 662 | unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) { |
Owen Anderson | 825b72b | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 663 | switch (VT.getSimpleVT().SimpleTy) { |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 664 | default: return Reg; |
Owen Anderson | 825b72b | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 665 | case MVT::i8: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 666 | if (High) { |
| 667 | switch (Reg) { |
Eric Christopher | 7d5a61e | 2011-12-01 08:12:41 +0000 | [diff] [blame] | 668 | default: return getX86SubSuperRegister(Reg, MVT::i64, High); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 669 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 670 | return X86::AH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 671 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 672 | return X86::DH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 673 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 674 | return X86::CH; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 675 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 676 | return X86::BH; |
| 677 | } |
| 678 | } else { |
| 679 | switch (Reg) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 680 | default: return 0; |
| 681 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 682 | return X86::AL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 683 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 684 | return X86::DL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 685 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 686 | return X86::CL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 687 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 688 | return X86::BL; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 689 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
| 690 | return X86::SIL; |
| 691 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
| 692 | return X86::DIL; |
| 693 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
| 694 | return X86::BPL; |
| 695 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
| 696 | return X86::SPL; |
| 697 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 698 | return X86::R8B; |
| 699 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 700 | return X86::R9B; |
| 701 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 702 | return X86::R10B; |
| 703 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 704 | return X86::R11B; |
| 705 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 706 | return X86::R12B; |
| 707 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 708 | return X86::R13B; |
| 709 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 710 | return X86::R14B; |
| 711 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 712 | return X86::R15B; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 713 | } |
| 714 | } |
Owen Anderson | 825b72b | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 715 | case MVT::i16: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 716 | switch (Reg) { |
| 717 | default: return Reg; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 718 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 719 | return X86::AX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 720 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 721 | return X86::DX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 722 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 723 | return X86::CX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 724 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 725 | return X86::BX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 726 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 727 | return X86::SI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 728 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 729 | return X86::DI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 730 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 731 | return X86::BP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 732 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 733 | return X86::SP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 734 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 735 | return X86::R8W; |
| 736 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 737 | return X86::R9W; |
| 738 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 739 | return X86::R10W; |
| 740 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 741 | return X86::R11W; |
| 742 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 743 | return X86::R12W; |
| 744 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 745 | return X86::R13W; |
| 746 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 747 | return X86::R14W; |
| 748 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 749 | return X86::R15W; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 750 | } |
Owen Anderson | 825b72b | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 751 | case MVT::i32: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 752 | switch (Reg) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 753 | default: return Reg; |
| 754 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 755 | return X86::EAX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 756 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 757 | return X86::EDX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 758 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 759 | return X86::ECX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 760 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 761 | return X86::EBX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 762 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 763 | return X86::ESI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 764 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 765 | return X86::EDI; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 766 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 767 | return X86::EBP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 768 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 769 | return X86::ESP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 770 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 771 | return X86::R8D; |
| 772 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 773 | return X86::R9D; |
| 774 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 775 | return X86::R10D; |
| 776 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 777 | return X86::R11D; |
| 778 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 779 | return X86::R12D; |
| 780 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 781 | return X86::R13D; |
| 782 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 783 | return X86::R14D; |
| 784 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 785 | return X86::R15D; |
| 786 | } |
Owen Anderson | 825b72b | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 787 | case MVT::i64: |
Eric Christopher | 7d5a61e | 2011-12-01 08:12:41 +0000 | [diff] [blame] | 788 | // For 64-bit mode if we've requested a "high" register and the |
| 789 | // Q or r constraints we want one of these high registers or |
| 790 | // just the register name otherwise. |
| 791 | if (High) { |
| 792 | switch (Reg) { |
| 793 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
| 794 | return X86::SI; |
| 795 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
| 796 | return X86::DI; |
| 797 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
| 798 | return X86::BP; |
| 799 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
| 800 | return X86::SP; |
| 801 | // Fallthrough. |
| 802 | } |
| 803 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 804 | switch (Reg) { |
| 805 | default: return Reg; |
| 806 | case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: |
| 807 | return X86::RAX; |
| 808 | case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: |
| 809 | return X86::RDX; |
| 810 | case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: |
| 811 | return X86::RCX; |
| 812 | case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: |
| 813 | return X86::RBX; |
| 814 | case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: |
| 815 | return X86::RSI; |
| 816 | case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: |
| 817 | return X86::RDI; |
| 818 | case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: |
| 819 | return X86::RBP; |
| 820 | case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: |
| 821 | return X86::RSP; |
| 822 | case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: |
| 823 | return X86::R8; |
| 824 | case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: |
| 825 | return X86::R9; |
| 826 | case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: |
| 827 | return X86::R10; |
| 828 | case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: |
| 829 | return X86::R11; |
| 830 | case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: |
| 831 | return X86::R12; |
| 832 | case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: |
| 833 | return X86::R13; |
| 834 | case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: |
| 835 | return X86::R14; |
| 836 | case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: |
| 837 | return X86::R15; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 838 | } |
| 839 | } |
| 840 | |
| 841 | return Reg; |
| 842 | } |
| 843 | } |
| 844 | |
Jim Grosbach | fa85eb6 | 2010-04-06 20:26:37 +0000 | [diff] [blame] | 845 | namespace { |
| 846 | struct MSAH : public MachineFunctionPass { |
| 847 | static char ID; |
Owen Anderson | 90c579d | 2010-08-06 18:33:48 +0000 | [diff] [blame] | 848 | MSAH() : MachineFunctionPass(ID) {} |
Jim Grosbach | fa85eb6 | 2010-04-06 20:26:37 +0000 | [diff] [blame] | 849 | |
| 850 | virtual bool runOnMachineFunction(MachineFunction &MF) { |
| 851 | const X86TargetMachine *TM = |
| 852 | static_cast<const X86TargetMachine *>(&MF.getTarget()); |
Evan Cheng | 2fa82bc | 2011-06-23 01:53:43 +0000 | [diff] [blame] | 853 | const TargetFrameLowering *TFI = TM->getFrameLowering(); |
Jim Grosbach | fa85eb6 | 2010-04-06 20:26:37 +0000 | [diff] [blame] | 854 | MachineRegisterInfo &RI = MF.getRegInfo(); |
| 855 | X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); |
Evan Cheng | 2fa82bc | 2011-06-23 01:53:43 +0000 | [diff] [blame] | 856 | unsigned StackAlignment = TFI->getStackAlignment(); |
Jim Grosbach | fa85eb6 | 2010-04-06 20:26:37 +0000 | [diff] [blame] | 857 | |
| 858 | // Be over-conservative: scan over all vreg defs and find whether vector |
| 859 | // registers are used. If yes, there is a possibility that vector register |
| 860 | // will be spilled and thus require dynamic stack realignment. |
Jakob Stoklund Olesen | b258135 | 2011-01-08 23:11:11 +0000 | [diff] [blame] | 861 | for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) { |
| 862 | unsigned Reg = TargetRegisterInfo::index2VirtReg(i); |
| 863 | if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) { |
Bruno Cardoso Lopes | 08ecb71 | 2011-09-16 20:58:28 +0000 | [diff] [blame] | 864 | FuncInfo->setForceFramePointer(true); |
Jim Grosbach | fa85eb6 | 2010-04-06 20:26:37 +0000 | [diff] [blame] | 865 | return true; |
| 866 | } |
Jakob Stoklund Olesen | b258135 | 2011-01-08 23:11:11 +0000 | [diff] [blame] | 867 | } |
Jim Grosbach | fa85eb6 | 2010-04-06 20:26:37 +0000 | [diff] [blame] | 868 | // Nothing to do |
| 869 | return false; |
| 870 | } |
| 871 | |
| 872 | virtual const char *getPassName() const { |
| 873 | return "X86 Maximal Stack Alignment Check"; |
| 874 | } |
| 875 | |
| 876 | virtual void getAnalysisUsage(AnalysisUsage &AU) const { |
| 877 | AU.setPreservesCFG(); |
| 878 | MachineFunctionPass::getAnalysisUsage(AU); |
| 879 | } |
| 880 | }; |
| 881 | |
| 882 | char MSAH::ID = 0; |
| 883 | } |
| 884 | |
| 885 | FunctionPass* |
| 886 | llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); } |