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gerrit-public.fairphone.software / platform / external / llvm / 8b22778431cdeb112366ed5dc6283b3a7af19018 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 4e9c3e58a5f3cbeb59bff60c783af782a2fb76af [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]50 raw_ostream &vStream,
51 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]52
53 /// getEDInfo - See MCDisassembler.
54 EDInstInfo *getEDInfo() const;
55private:
56};
57
58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59class ThumbDisassembler : public MCDisassembler {
60public:
61 /// Constructor - Initializes the disassembler.
62 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]65 }
66
67 ~ThumbDisassembler() {
68 }
69
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
72 uint64_t &size,
73 const MemoryObject &region,
74 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]75 raw_ostream &vStream,
76 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]77
78 /// getEDInfo - See MCDisassembler.
79 EDInstInfo *getEDInfo() const;
80private:
81 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]82 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]83 void UpdateThumbVFPPredicate(MCInst&) const;
84};
85}
86
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]87static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]88 switch (In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
91 return true;
92 case MCDisassembler::SoftFail:
93 Out = In;
94 return true;
95 case MCDisassembler::Fail:
96 Out = In;
97 return false;
98 }
99 return false;
100}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]101
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]102
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103// Forward declare these because the autogenerated code will reference them.
104// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]106 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]107static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]122static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]126static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]128
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]139static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]140 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]146static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]147 unsigned Insn,
148 uint64_t Address,
149 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]156static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
158
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]159static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 unsigned Insn,
161 uint64_t Adddress,
162 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]247static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]248 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]274static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]290static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]298static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]300static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
301 uint64_t Address, const void *Decoder);
302static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
303 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]304static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]306static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
308
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]309
310#include "ARMGenDisassemblerTables.inc"
311#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]312#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]313
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]314static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
315 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]316}
317
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]318static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
319 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]320}
321
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]322EDInstInfo *ARMDisassembler::getEDInfo() const {
323 return instInfoARM;
324}
325
326EDInstInfo *ThumbDisassembler::getEDInfo() const {
327 return instInfoARM;
328}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]330DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]331 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]332 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]333 raw_ostream &os,
334 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]335 uint8_t bytes[4];
336
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]337 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
338 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
339
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]340 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]341 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
342 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]343 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]344 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345
346 // Encoded as a small-endian 32-bit word in the stream.
347 uint32_t insn = (bytes[3] << 24) |
348 (bytes[2] << 16) |
349 (bytes[1] << 8) |
350 (bytes[0] << 0);
351
352 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]353 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]354 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]356 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 }
358
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]359 // VFP and NEON instructions, similarly, are shared between ARM
360 // and Thumb modes.
361 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]362 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]363 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]364 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]365 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]366 }
367
368 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]369 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]370 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]371 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]372 // Add a fake predicate operand, because we share these instruction
373 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]374 if (!DecodePredicateOperand(MI, 0xE, Address, this))
375 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]376 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]377 }
378
379 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]380 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]381 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]383 // Add a fake predicate operand, because we share these instruction
384 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]385 if (!DecodePredicateOperand(MI, 0xE, Address, this))
386 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]387 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]388 }
389
390 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]391 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]392 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]393 Size = 4;
394 // Add a fake predicate operand, because we share these instruction
395 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]396 if (!DecodePredicateOperand(MI, 0xE, Address, this))
397 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]398 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]399 }
400
401 MI.clear();
402
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]403 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]404 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]405}
406
407namespace llvm {
408extern MCInstrDesc ARMInsts[];
409}
410
411// Thumb1 instructions don't have explicit S bits. Rather, they
412// implicitly set CPSR. Since it's not represented in the encoding, the
413// auto-generated decoder won't inject the CPSR operand. We need to fix
414// that as a post-pass.
415static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
416 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]417 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]418 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]419 for (unsigned i = 0; i < NumOps; ++i, ++I) {
420 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]421 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]422 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]423 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
424 return;
425 }
426 }
427
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]428 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]429}
430
431// Most Thumb instructions don't have explicit predicates in the
432// encoding, but rather get their predicates from IT context. We need
433// to fix up the predicate operands using this context information as a
434// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]435MCDisassembler::DecodeStatus
436ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]437 MCDisassembler::DecodeStatus S = Success;
438
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]439 // A few instructions actually have predicates encoded in them. Don't
440 // try to overwrite it if we're seeing one of those.
441 switch (MI.getOpcode()) {
442 case ARM::tBcc:
443 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]444 case ARM::tCBZ:
445 case ARM::tCBNZ:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]446 // Some instructions (mostly conditional branches) are not
447 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]448 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]449 S = SoftFail;
450 else
451 return Success;
452 break;
453 case ARM::tB:
454 case ARM::t2B:
455 // Some instructions (mostly unconditional branches) can
456 // only appears at the end of, or outside of, an IT.
457 if (ITBlock.size() > 1)
458 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]459 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]460 default:
461 break;
462 }
463
464 // If we're in an IT block, base the predicate on that. Otherwise,
465 // assume a predicate of AL.
466 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]467 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]468 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]469 if (CC == 0xF)
470 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]471 ITBlock.pop_back();
472 } else
473 CC = ARMCC::AL;
474
475 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]476 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]477 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]478 for (unsigned i = 0; i < NumOps; ++i, ++I) {
479 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]480 if (OpInfo[i].isPredicate()) {
481 I = MI.insert(I, MCOperand::CreateImm(CC));
482 ++I;
483 if (CC == ARMCC::AL)
484 MI.insert(I, MCOperand::CreateReg(0));
485 else
486 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]487 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]488 }
489 }
490
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]491 I = MI.insert(I, MCOperand::CreateImm(CC));
492 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]493 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]494 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]495 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]496 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]497
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]498 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]499}
500
501// Thumb VFP instructions are a special case. Because we share their
502// encodings between ARM and Thumb modes, and they are predicable in ARM
503// mode, the auto-generated decoder will give them an (incorrect)
504// predicate operand. We need to rewrite these operands based on the IT
505// context as a post-pass.
506void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
507 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]508 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]509 CC = ITBlock.back();
510 ITBlock.pop_back();
511 } else
512 CC = ARMCC::AL;
513
514 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
515 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]516 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
517 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]518 if (OpInfo[i].isPredicate() ) {
519 I->setImm(CC);
520 ++I;
521 if (CC == ARMCC::AL)
522 I->setReg(0);
523 else
524 I->setReg(ARM::CPSR);
525 return;
526 }
527 }
528}
529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]530DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]531 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]532 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]533 raw_ostream &os,
534 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]535 uint8_t bytes[4];
536
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]537 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
538 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
539
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]540 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]541 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
542 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]543 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]544 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]545
546 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]547 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]548 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]549 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]550 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]551 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]552 }
553
554 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]555 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]556 if (result) {
557 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]558 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]559 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]560 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]561 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]562 }
563
564 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]565 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]566 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]567 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]568 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]569
570 // If we find an IT instruction, we need to parse its condition
571 // code and mask operands so that we can apply them correctly
572 // to the subsequent instructions.
573 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]574 // Nested IT blocks are UNPREDICTABLE.
575 if (!ITBlock.empty())
576 return MCDisassembler::SoftFail;
577
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]578 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]580 unsigned Mask = MI.getOperand(1).getImm();
581 unsigned CondBit0 = Mask >> 4 & 1;
582 unsigned NumTZ = CountTrailingZeros_32(Mask);
583 assert(NumTZ <= 3 && "Invalid IT mask!");
584 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
585 bool T = ((Mask >> Pos) & 1) == CondBit0;
586 if (T)
587 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]588 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]589 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]590 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]591
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]592 ITBlock.push_back(firstcond);
593 }
594
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]595 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]596 }
597
598 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]599 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
600 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]601 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]602 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]603
604 uint32_t insn32 = (bytes[3] << 8) |
605 (bytes[2] << 0) |
606 (bytes[1] << 24) |
607 (bytes[0] << 16);
608 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]609 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]610 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]611 Size = 4;
612 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]613 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]614 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]615 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]616 }
617
618 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]619 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]620 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]621 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]622 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]623 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]624 }
625
626 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]627 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]628 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]629 Size = 4;
630 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]631 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]632 }
633
634 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]635 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]636 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]637 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]638 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]639 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]640 }
641
642 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
643 MI.clear();
644 uint32_t NEONLdStInsn = insn32;
645 NEONLdStInsn &= 0xF0FFFFFF;
646 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]647 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]648 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]649 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]650 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]651 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]652 }
653 }
654
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]655 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]656 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]657 uint32_t NEONDataInsn = insn32;
658 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
659 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
660 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]661 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]662 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]663 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]664 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]665 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]666 }
667 }
668
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]669 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]670 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]671}
672
673
674extern "C" void LLVMInitializeARMDisassembler() {
675 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
676 createARMDisassembler);
677 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
678 createThumbDisassembler);
679}
680
681static const unsigned GPRDecoderTable[] = {
682 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
683 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
684 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
685 ARM::R12, ARM::SP, ARM::LR, ARM::PC
686};
687
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]688static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]689 uint64_t Address, const void *Decoder) {
690 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]691 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]692
693 unsigned Register = GPRDecoderTable[RegNo];
694 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]695 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]696}
697
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]698static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]699DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
700 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]701 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]702 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
703}
704
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]705static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]706 uint64_t Address, const void *Decoder) {
707 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]708 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]709 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
710}
711
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]712static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]713 uint64_t Address, const void *Decoder) {
714 unsigned Register = 0;
715 switch (RegNo) {
716 case 0:
717 Register = ARM::R0;
718 break;
719 case 1:
720 Register = ARM::R1;
721 break;
722 case 2:
723 Register = ARM::R2;
724 break;
725 case 3:
726 Register = ARM::R3;
727 break;
728 case 9:
729 Register = ARM::R9;
730 break;
731 case 12:
732 Register = ARM::R12;
733 break;
734 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]735 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]736 }
737
738 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]739 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]740}
741
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]742static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]743 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]744 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]745 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
746}
747
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]748static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]749 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
750 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
751 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
752 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
753 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
754 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
755 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
756 ARM::S28, ARM::S29, ARM::S30, ARM::S31
757};
758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]759static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]760 uint64_t Address, const void *Decoder) {
761 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]762 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]763
764 unsigned Register = SPRDecoderTable[RegNo];
765 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]766 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]767}
768
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]769static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]770 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
771 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
772 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
773 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
774 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
775 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
776 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
777 ARM::D28, ARM::D29, ARM::D30, ARM::D31
778};
779
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]780static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]781 uint64_t Address, const void *Decoder) {
782 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]783 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]784
785 unsigned Register = DPRDecoderTable[RegNo];
786 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]787 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]788}
789
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]790static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 uint64_t Address, const void *Decoder) {
792 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]793 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
795}
796
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]797static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]798DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
799 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]800 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]801 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]802 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
803}
804
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]805static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]806 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
807 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
808 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
809 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
810};
811
812
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]813static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]814 uint64_t Address, const void *Decoder) {
815 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]816 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]817 RegNo >>= 1;
818
819 unsigned Register = QPRDecoderTable[RegNo];
820 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]821 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]822}
823
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]824static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]825 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]826 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]827 // AL predicate is not allowed on Thumb1 branches.
828 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]829 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]830 Inst.addOperand(MCOperand::CreateImm(Val));
831 if (Val == ARMCC::AL) {
832 Inst.addOperand(MCOperand::CreateReg(0));
833 } else
834 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]835 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]836}
837
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]838static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]839 uint64_t Address, const void *Decoder) {
840 if (Val)
841 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
842 else
843 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]844 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]845}
846
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]847static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]848 uint64_t Address, const void *Decoder) {
849 uint32_t imm = Val & 0xFF;
850 uint32_t rot = (Val & 0xF00) >> 7;
851 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
852 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]853 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854}
855
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]856static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]857 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]858 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]859
860 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
861 unsigned type = fieldFromInstruction32(Val, 5, 2);
862 unsigned imm = fieldFromInstruction32(Val, 7, 5);
863
864 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
866 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]867
868 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
869 switch (type) {
870 case 0:
871 Shift = ARM_AM::lsl;
872 break;
873 case 1:
874 Shift = ARM_AM::lsr;
875 break;
876 case 2:
877 Shift = ARM_AM::asr;
878 break;
879 case 3:
880 Shift = ARM_AM::ror;
881 break;
882 }
883
884 if (Shift == ARM_AM::ror && imm == 0)
885 Shift = ARM_AM::rrx;
886
887 unsigned Op = Shift | (imm << 3);
888 Inst.addOperand(MCOperand::CreateImm(Op));
889
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]890 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]891}
892
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]893static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]894 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]895 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]896
897 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
898 unsigned type = fieldFromInstruction32(Val, 5, 2);
899 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
900
901 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]902 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
903 return MCDisassembler::Fail;
904 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
905 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]906
907 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
908 switch (type) {
909 case 0:
910 Shift = ARM_AM::lsl;
911 break;
912 case 1:
913 Shift = ARM_AM::lsr;
914 break;
915 case 2:
916 Shift = ARM_AM::asr;
917 break;
918 case 3:
919 Shift = ARM_AM::ror;
920 break;
921 }
922
923 Inst.addOperand(MCOperand::CreateImm(Shift));
924
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]925 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]926}
927
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]928static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]930 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]931
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]932 bool writebackLoad = false;
933 unsigned writebackReg = 0;
934 switch (Inst.getOpcode()) {
935 default:
936 break;
937 case ARM::LDMIA_UPD:
938 case ARM::LDMDB_UPD:
939 case ARM::LDMIB_UPD:
940 case ARM::LDMDA_UPD:
941 case ARM::t2LDMIA_UPD:
942 case ARM::t2LDMDB_UPD:
943 writebackLoad = true;
944 writebackReg = Inst.getOperand(0).getReg();
945 break;
946 }
947
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]948 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]949 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]950 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]951 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]952 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
953 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]954 // Writeback not allowed if Rn is in the target list.
955 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
956 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]957 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958 }
959
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]960 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]961}
962
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]963static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]964 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]965 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]966
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
968 unsigned regs = Val & 0xFF;
969
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]970 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
971 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]972 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]973 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
974 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]975 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]976
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]977 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978}
979
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]980static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]981 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]982 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]983
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
985 unsigned regs = (Val & 0xFF) / 2;
986
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]987 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
988 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]989 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]990 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
991 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]992 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]993
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]994 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995}
996
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]997static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]998 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]999 // This operand encodes a mask of contiguous zeros between a specified MSB
1000 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1001 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1002 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1003 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1004 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1005 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1006
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame^]1007 uint32_t msb_mask = 0xFFFFFFFF;
1008 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1009 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1010
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1011 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1012 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1013}
1014
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1015static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1016 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1017 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1018
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1019 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1020 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1021 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1022 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1023 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1024 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1025
1026 switch (Inst.getOpcode()) {
1027 case ARM::LDC_OFFSET:
1028 case ARM::LDC_PRE:
1029 case ARM::LDC_POST:
1030 case ARM::LDC_OPTION:
1031 case ARM::LDCL_OFFSET:
1032 case ARM::LDCL_PRE:
1033 case ARM::LDCL_POST:
1034 case ARM::LDCL_OPTION:
1035 case ARM::STC_OFFSET:
1036 case ARM::STC_PRE:
1037 case ARM::STC_POST:
1038 case ARM::STC_OPTION:
1039 case ARM::STCL_OFFSET:
1040 case ARM::STCL_PRE:
1041 case ARM::STCL_POST:
1042 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1043 case ARM::t2LDC_OFFSET:
1044 case ARM::t2LDC_PRE:
1045 case ARM::t2LDC_POST:
1046 case ARM::t2LDC_OPTION:
1047 case ARM::t2LDCL_OFFSET:
1048 case ARM::t2LDCL_PRE:
1049 case ARM::t2LDCL_POST:
1050 case ARM::t2LDCL_OPTION:
1051 case ARM::t2STC_OFFSET:
1052 case ARM::t2STC_PRE:
1053 case ARM::t2STC_POST:
1054 case ARM::t2STC_OPTION:
1055 case ARM::t2STCL_OFFSET:
1056 case ARM::t2STCL_PRE:
1057 case ARM::t2STCL_POST:
1058 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1059 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1060 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1061 break;
1062 default:
1063 break;
1064 }
1065
1066 Inst.addOperand(MCOperand::CreateImm(coproc));
1067 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1068 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1069 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1070 switch (Inst.getOpcode()) {
1071 case ARM::LDC_OPTION:
1072 case ARM::LDCL_OPTION:
1073 case ARM::LDC2_OPTION:
1074 case ARM::LDC2L_OPTION:
1075 case ARM::STC_OPTION:
1076 case ARM::STCL_OPTION:
1077 case ARM::STC2_OPTION:
1078 case ARM::STC2L_OPTION:
1079 case ARM::LDCL_POST:
1080 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1081 case ARM::LDC2L_POST:
1082 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1083 case ARM::t2LDC_OPTION:
1084 case ARM::t2LDCL_OPTION:
1085 case ARM::t2STC_OPTION:
1086 case ARM::t2STCL_OPTION:
1087 case ARM::t2LDCL_POST:
1088 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1089 break;
1090 default:
1091 Inst.addOperand(MCOperand::CreateReg(0));
1092 break;
1093 }
1094
1095 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1096 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1097
1098 bool writeback = (P == 0) || (W == 1);
1099 unsigned idx_mode = 0;
1100 if (P && writeback)
1101 idx_mode = ARMII::IndexModePre;
1102 else if (!P && writeback)
1103 idx_mode = ARMII::IndexModePost;
1104
1105 switch (Inst.getOpcode()) {
1106 case ARM::LDCL_POST:
1107 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1108 case ARM::t2LDCL_POST:
1109 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1110 case ARM::LDC2L_POST:
1111 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 imm |= U << 8;
1113 case ARM::LDC_OPTION:
1114 case ARM::LDCL_OPTION:
1115 case ARM::LDC2_OPTION:
1116 case ARM::LDC2L_OPTION:
1117 case ARM::STC_OPTION:
1118 case ARM::STCL_OPTION:
1119 case ARM::STC2_OPTION:
1120 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1121 case ARM::t2LDC_OPTION:
1122 case ARM::t2LDCL_OPTION:
1123 case ARM::t2STC_OPTION:
1124 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1125 Inst.addOperand(MCOperand::CreateImm(imm));
1126 break;
1127 default:
1128 if (U)
1129 Inst.addOperand(MCOperand::CreateImm(
1130 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1131 else
1132 Inst.addOperand(MCOperand::CreateImm(
1133 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1134 break;
1135 }
1136
1137 switch (Inst.getOpcode()) {
1138 case ARM::LDC_OFFSET:
1139 case ARM::LDC_PRE:
1140 case ARM::LDC_POST:
1141 case ARM::LDC_OPTION:
1142 case ARM::LDCL_OFFSET:
1143 case ARM::LDCL_PRE:
1144 case ARM::LDCL_POST:
1145 case ARM::LDCL_OPTION:
1146 case ARM::STC_OFFSET:
1147 case ARM::STC_PRE:
1148 case ARM::STC_POST:
1149 case ARM::STC_OPTION:
1150 case ARM::STCL_OFFSET:
1151 case ARM::STCL_PRE:
1152 case ARM::STCL_POST:
1153 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1154 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1155 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1156 break;
1157 default:
1158 break;
1159 }
1160
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1161 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1162}
1163
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1164static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1165DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1166 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1167 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1168
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1169 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1170 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1171 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1172 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1173 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1174 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1175 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1176 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1177
1178 // On stores, the writeback operand precedes Rt.
1179 switch (Inst.getOpcode()) {
1180 case ARM::STR_POST_IMM:
1181 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1182 case ARM::STRB_POST_IMM:
1183 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1184 case ARM::STRT_POST_REG:
1185 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1186 case ARM::STRBT_POST_REG:
1187 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1189 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1190 break;
1191 default:
1192 break;
1193 }
1194
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1195 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1196 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1197
1198 // On loads, the writeback operand comes after Rt.
1199 switch (Inst.getOpcode()) {
1200 case ARM::LDR_POST_IMM:
1201 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1202 case ARM::LDRB_POST_IMM:
1203 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1204 case ARM::LDRBT_POST_REG:
1205 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1206 case ARM::LDRT_POST_REG:
1207 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1209 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1210 break;
1211 default:
1212 break;
1213 }
1214
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1216 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1217
1218 ARM_AM::AddrOpc Op = ARM_AM::add;
1219 if (!fieldFromInstruction32(Insn, 23, 1))
1220 Op = ARM_AM::sub;
1221
1222 bool writeback = (P == 0) || (W == 1);
1223 unsigned idx_mode = 0;
1224 if (P && writeback)
1225 idx_mode = ARMII::IndexModePre;
1226 else if (!P && writeback)
1227 idx_mode = ARMII::IndexModePost;
1228
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1229 if (writeback && (Rn == 15 || Rn == Rt))
1230 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1231
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1232 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1234 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1236 switch( fieldFromInstruction32(Insn, 5, 2)) {
1237 case 0:
1238 Opc = ARM_AM::lsl;
1239 break;
1240 case 1:
1241 Opc = ARM_AM::lsr;
1242 break;
1243 case 2:
1244 Opc = ARM_AM::asr;
1245 break;
1246 case 3:
1247 Opc = ARM_AM::ror;
1248 break;
1249 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1250 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1251 }
1252 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1253 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1254
1255 Inst.addOperand(MCOperand::CreateImm(imm));
1256 } else {
1257 Inst.addOperand(MCOperand::CreateReg(0));
1258 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1259 Inst.addOperand(MCOperand::CreateImm(tmp));
1260 }
1261
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1262 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1263 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1264
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1265 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1266}
1267
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1268static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1269 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1270 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1271
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1272 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1273 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1274 unsigned type = fieldFromInstruction32(Val, 5, 2);
1275 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1276 unsigned U = fieldFromInstruction32(Val, 12, 1);
1277
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1278 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1279 switch (type) {
1280 case 0:
1281 ShOp = ARM_AM::lsl;
1282 break;
1283 case 1:
1284 ShOp = ARM_AM::lsr;
1285 break;
1286 case 2:
1287 ShOp = ARM_AM::asr;
1288 break;
1289 case 3:
1290 ShOp = ARM_AM::ror;
1291 break;
1292 }
1293
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1295 return MCDisassembler::Fail;
1296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1297 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1298 unsigned shift;
1299 if (U)
1300 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1301 else
1302 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1303 Inst.addOperand(MCOperand::CreateImm(shift));
1304
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1305 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1306}
1307
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1308static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1309DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1310 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1311 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1312
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1313 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1314 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1315 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1316 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1317 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1318 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1319 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1320 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1321 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1322
1323 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1324
1325 // For {LD,ST}RD, Rt must be even, else undefined.
1326 switch (Inst.getOpcode()) {
1327 case ARM::STRD:
1328 case ARM::STRD_PRE:
1329 case ARM::STRD_POST:
1330 case ARM::LDRD:
1331 case ARM::LDRD_PRE:
1332 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1333 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1334 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1335 default:
1336 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1337 }
1338
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1339 if (writeback) { // Writeback
1340 if (P)
1341 U |= ARMII::IndexModePre << 9;
1342 else
1343 U |= ARMII::IndexModePost << 9;
1344
1345 // On stores, the writeback operand precedes Rt.
1346 switch (Inst.getOpcode()) {
1347 case ARM::STRD:
1348 case ARM::STRD_PRE:
1349 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1350 case ARM::STRH:
1351 case ARM::STRH_PRE:
1352 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1354 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1355 break;
1356 default:
1357 break;
1358 }
1359 }
1360
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1362 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1363 switch (Inst.getOpcode()) {
1364 case ARM::STRD:
1365 case ARM::STRD_PRE:
1366 case ARM::STRD_POST:
1367 case ARM::LDRD:
1368 case ARM::LDRD_PRE:
1369 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1370 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1371 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1372 break;
1373 default:
1374 break;
1375 }
1376
1377 if (writeback) {
1378 // On loads, the writeback operand comes after Rt.
1379 switch (Inst.getOpcode()) {
1380 case ARM::LDRD:
1381 case ARM::LDRD_PRE:
1382 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1383 case ARM::LDRH:
1384 case ARM::LDRH_PRE:
1385 case ARM::LDRH_POST:
1386 case ARM::LDRSH:
1387 case ARM::LDRSH_PRE:
1388 case ARM::LDRSH_POST:
1389 case ARM::LDRSB:
1390 case ARM::LDRSB_PRE:
1391 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1392 case ARM::LDRHTr:
1393 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1395 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1396 break;
1397 default:
1398 break;
1399 }
1400 }
1401
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1402 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1403 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1404
1405 if (type) {
1406 Inst.addOperand(MCOperand::CreateReg(0));
1407 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1408 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1410 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1411 Inst.addOperand(MCOperand::CreateImm(U));
1412 }
1413
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1414 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1415 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1416
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1417 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1418}
1419
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1420static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1421 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1422 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1423
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1424 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1425 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1426
1427 switch (mode) {
1428 case 0:
1429 mode = ARM_AM::da;
1430 break;
1431 case 1:
1432 mode = ARM_AM::ia;
1433 break;
1434 case 2:
1435 mode = ARM_AM::db;
1436 break;
1437 case 3:
1438 mode = ARM_AM::ib;
1439 break;
1440 }
1441
1442 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1444 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1445
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1446 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1447}
1448
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1449static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1450 unsigned Insn,
1451 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1452 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1453
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1454 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1455 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1456 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1457
1458 if (pred == 0xF) {
1459 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1460 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1461 Inst.setOpcode(ARM::RFEDA);
1462 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1463 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1464 Inst.setOpcode(ARM::RFEDA_UPD);
1465 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1466 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1467 Inst.setOpcode(ARM::RFEDB);
1468 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1469 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1470 Inst.setOpcode(ARM::RFEDB_UPD);
1471 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1472 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1473 Inst.setOpcode(ARM::RFEIA);
1474 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1475 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1476 Inst.setOpcode(ARM::RFEIA_UPD);
1477 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1478 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1479 Inst.setOpcode(ARM::RFEIB);
1480 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1481 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1482 Inst.setOpcode(ARM::RFEIB_UPD);
1483 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1484 case ARM::STMDA:
1485 Inst.setOpcode(ARM::SRSDA);
1486 break;
1487 case ARM::STMDA_UPD:
1488 Inst.setOpcode(ARM::SRSDA_UPD);
1489 break;
1490 case ARM::STMDB:
1491 Inst.setOpcode(ARM::SRSDB);
1492 break;
1493 case ARM::STMDB_UPD:
1494 Inst.setOpcode(ARM::SRSDB_UPD);
1495 break;
1496 case ARM::STMIA:
1497 Inst.setOpcode(ARM::SRSIA);
1498 break;
1499 case ARM::STMIA_UPD:
1500 Inst.setOpcode(ARM::SRSIA_UPD);
1501 break;
1502 case ARM::STMIB:
1503 Inst.setOpcode(ARM::SRSIB);
1504 break;
1505 case ARM::STMIB_UPD:
1506 Inst.setOpcode(ARM::SRSIB_UPD);
1507 break;
1508 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1509 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1510 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1511
1512 // For stores (which become SRS's, the only operand is the mode.
1513 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1514 Inst.addOperand(
1515 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1516 return S;
1517 }
1518
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1519 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1520 }
1521
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1523 return MCDisassembler::Fail;
1524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1525 return MCDisassembler::Fail; // Tied
1526 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1527 return MCDisassembler::Fail;
1528 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1529 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1530
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1531 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1532}
1533
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1534static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1535 uint64_t Address, const void *Decoder) {
1536 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1537 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1538 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1539 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1540
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1541 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1542
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1543 // imod == '01' --> UNPREDICTABLE
1544 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1545 // return failure here. The '01' imod value is unprintable, so there's
1546 // nothing useful we could do even if we returned UNPREDICTABLE.
1547
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1548 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1549
1550 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1551 Inst.setOpcode(ARM::CPS3p);
1552 Inst.addOperand(MCOperand::CreateImm(imod));
1553 Inst.addOperand(MCOperand::CreateImm(iflags));
1554 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1555 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1556 Inst.setOpcode(ARM::CPS2p);
1557 Inst.addOperand(MCOperand::CreateImm(imod));
1558 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1559 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1560 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1561 Inst.setOpcode(ARM::CPS1p);
1562 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1563 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1564 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1565 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1566 Inst.setOpcode(ARM::CPS1p);
1567 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1568 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1569 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1570
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1571 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1572}
1573
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1574static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1575 uint64_t Address, const void *Decoder) {
1576 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1577 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1578 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1579 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1580
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1581 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1582
1583 // imod == '01' --> UNPREDICTABLE
1584 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1585 // return failure here. The '01' imod value is unprintable, so there's
1586 // nothing useful we could do even if we returned UNPREDICTABLE.
1587
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1588 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1589
1590 if (imod && M) {
1591 Inst.setOpcode(ARM::t2CPS3p);
1592 Inst.addOperand(MCOperand::CreateImm(imod));
1593 Inst.addOperand(MCOperand::CreateImm(iflags));
1594 Inst.addOperand(MCOperand::CreateImm(mode));
1595 } else if (imod && !M) {
1596 Inst.setOpcode(ARM::t2CPS2p);
1597 Inst.addOperand(MCOperand::CreateImm(imod));
1598 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1599 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1600 } else if (!imod && M) {
1601 Inst.setOpcode(ARM::t2CPS1p);
1602 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1603 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1604 } else {
1605 // imod == '00' && M == '0' --> UNPREDICTABLE
1606 Inst.setOpcode(ARM::t2CPS1p);
1607 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1608 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1609 }
1610
1611 return S;
1612}
1613
1614
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1615static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1616 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1617 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1618
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1619 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1620 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1621 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1622 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1623 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1624
1625 if (pred == 0xF)
1626 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1627
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1628 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1629 return MCDisassembler::Fail;
1630 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1631 return MCDisassembler::Fail;
1632 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1633 return MCDisassembler::Fail;
1634 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1635 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1636
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1637 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1638 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1639
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1640 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1641}
1642
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1643static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1644 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1645 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1646
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1647 unsigned add = fieldFromInstruction32(Val, 12, 1);
1648 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1649 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1650
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1652 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1653
1654 if (!add) imm *= -1;
1655 if (imm == 0 && !add) imm = INT32_MIN;
1656 Inst.addOperand(MCOperand::CreateImm(imm));
1657
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1658 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1659}
1660
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1661static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1662 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1663 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1664
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1665 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1666 unsigned U = fieldFromInstruction32(Val, 8, 1);
1667 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1668
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1670 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1671
1672 if (U)
1673 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1674 else
1675 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1676
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1677 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1678}
1679
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1680static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1681 uint64_t Address, const void *Decoder) {
1682 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1683}
1684
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1685static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1686DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1687 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1688 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1689
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1690 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1691 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1692
1693 if (pred == 0xF) {
1694 Inst.setOpcode(ARM::BLXi);
1695 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1696 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1697 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1698 }
1699
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1700 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1701 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1702 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1703
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1704 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1705}
1706
1707
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1708static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1709 uint64_t Address, const void *Decoder) {
1710 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1711 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1712}
1713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1714static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1715 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1716 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1717
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1718 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1719 unsigned align = fieldFromInstruction32(Val, 4, 2);
1720
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1722 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1723 if (!align)
1724 Inst.addOperand(MCOperand::CreateImm(0));
1725 else
1726 Inst.addOperand(MCOperand::CreateImm(4 << align));
1727
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1728 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1729}
1730
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1731static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1732 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1733 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1734
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1735 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1736 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1737 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1738 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1739 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1740 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1741
1742 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1744 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1745
1746 // Second output register
1747 switch (Inst.getOpcode()) {
1748 case ARM::VLD1q8:
1749 case ARM::VLD1q16:
1750 case ARM::VLD1q32:
1751 case ARM::VLD1q64:
1752 case ARM::VLD1q8_UPD:
1753 case ARM::VLD1q16_UPD:
1754 case ARM::VLD1q32_UPD:
1755 case ARM::VLD1q64_UPD:
1756 case ARM::VLD1d8T:
1757 case ARM::VLD1d16T:
1758 case ARM::VLD1d32T:
1759 case ARM::VLD1d64T:
1760 case ARM::VLD1d8T_UPD:
1761 case ARM::VLD1d16T_UPD:
1762 case ARM::VLD1d32T_UPD:
1763 case ARM::VLD1d64T_UPD:
1764 case ARM::VLD1d8Q:
1765 case ARM::VLD1d16Q:
1766 case ARM::VLD1d32Q:
1767 case ARM::VLD1d64Q:
1768 case ARM::VLD1d8Q_UPD:
1769 case ARM::VLD1d16Q_UPD:
1770 case ARM::VLD1d32Q_UPD:
1771 case ARM::VLD1d64Q_UPD:
1772 case ARM::VLD2d8:
1773 case ARM::VLD2d16:
1774 case ARM::VLD2d32:
1775 case ARM::VLD2d8_UPD:
1776 case ARM::VLD2d16_UPD:
1777 case ARM::VLD2d32_UPD:
1778 case ARM::VLD2q8:
1779 case ARM::VLD2q16:
1780 case ARM::VLD2q32:
1781 case ARM::VLD2q8_UPD:
1782 case ARM::VLD2q16_UPD:
1783 case ARM::VLD2q32_UPD:
1784 case ARM::VLD3d8:
1785 case ARM::VLD3d16:
1786 case ARM::VLD3d32:
1787 case ARM::VLD3d8_UPD:
1788 case ARM::VLD3d16_UPD:
1789 case ARM::VLD3d32_UPD:
1790 case ARM::VLD4d8:
1791 case ARM::VLD4d16:
1792 case ARM::VLD4d32:
1793 case ARM::VLD4d8_UPD:
1794 case ARM::VLD4d16_UPD:
1795 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1796 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1797 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1798 break;
1799 case ARM::VLD2b8:
1800 case ARM::VLD2b16:
1801 case ARM::VLD2b32:
1802 case ARM::VLD2b8_UPD:
1803 case ARM::VLD2b16_UPD:
1804 case ARM::VLD2b32_UPD:
1805 case ARM::VLD3q8:
1806 case ARM::VLD3q16:
1807 case ARM::VLD3q32:
1808 case ARM::VLD3q8_UPD:
1809 case ARM::VLD3q16_UPD:
1810 case ARM::VLD3q32_UPD:
1811 case ARM::VLD4q8:
1812 case ARM::VLD4q16:
1813 case ARM::VLD4q32:
1814 case ARM::VLD4q8_UPD:
1815 case ARM::VLD4q16_UPD:
1816 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1817 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1818 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1819 default:
1820 break;
1821 }
1822
1823 // Third output register
1824 switch(Inst.getOpcode()) {
1825 case ARM::VLD1d8T:
1826 case ARM::VLD1d16T:
1827 case ARM::VLD1d32T:
1828 case ARM::VLD1d64T:
1829 case ARM::VLD1d8T_UPD:
1830 case ARM::VLD1d16T_UPD:
1831 case ARM::VLD1d32T_UPD:
1832 case ARM::VLD1d64T_UPD:
1833 case ARM::VLD1d8Q:
1834 case ARM::VLD1d16Q:
1835 case ARM::VLD1d32Q:
1836 case ARM::VLD1d64Q:
1837 case ARM::VLD1d8Q_UPD:
1838 case ARM::VLD1d16Q_UPD:
1839 case ARM::VLD1d32Q_UPD:
1840 case ARM::VLD1d64Q_UPD:
1841 case ARM::VLD2q8:
1842 case ARM::VLD2q16:
1843 case ARM::VLD2q32:
1844 case ARM::VLD2q8_UPD:
1845 case ARM::VLD2q16_UPD:
1846 case ARM::VLD2q32_UPD:
1847 case ARM::VLD3d8:
1848 case ARM::VLD3d16:
1849 case ARM::VLD3d32:
1850 case ARM::VLD3d8_UPD:
1851 case ARM::VLD3d16_UPD:
1852 case ARM::VLD3d32_UPD:
1853 case ARM::VLD4d8:
1854 case ARM::VLD4d16:
1855 case ARM::VLD4d32:
1856 case ARM::VLD4d8_UPD:
1857 case ARM::VLD4d16_UPD:
1858 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1859 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1860 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1861 break;
1862 case ARM::VLD3q8:
1863 case ARM::VLD3q16:
1864 case ARM::VLD3q32:
1865 case ARM::VLD3q8_UPD:
1866 case ARM::VLD3q16_UPD:
1867 case ARM::VLD3q32_UPD:
1868 case ARM::VLD4q8:
1869 case ARM::VLD4q16:
1870 case ARM::VLD4q32:
1871 case ARM::VLD4q8_UPD:
1872 case ARM::VLD4q16_UPD:
1873 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1874 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1875 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1876 break;
1877 default:
1878 break;
1879 }
1880
1881 // Fourth output register
1882 switch (Inst.getOpcode()) {
1883 case ARM::VLD1d8Q:
1884 case ARM::VLD1d16Q:
1885 case ARM::VLD1d32Q:
1886 case ARM::VLD1d64Q:
1887 case ARM::VLD1d8Q_UPD:
1888 case ARM::VLD1d16Q_UPD:
1889 case ARM::VLD1d32Q_UPD:
1890 case ARM::VLD1d64Q_UPD:
1891 case ARM::VLD2q8:
1892 case ARM::VLD2q16:
1893 case ARM::VLD2q32:
1894 case ARM::VLD2q8_UPD:
1895 case ARM::VLD2q16_UPD:
1896 case ARM::VLD2q32_UPD:
1897 case ARM::VLD4d8:
1898 case ARM::VLD4d16:
1899 case ARM::VLD4d32:
1900 case ARM::VLD4d8_UPD:
1901 case ARM::VLD4d16_UPD:
1902 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1903 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1904 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1905 break;
1906 case ARM::VLD4q8:
1907 case ARM::VLD4q16:
1908 case ARM::VLD4q32:
1909 case ARM::VLD4q8_UPD:
1910 case ARM::VLD4q16_UPD:
1911 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1912 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1913 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1914 break;
1915 default:
1916 break;
1917 }
1918
1919 // Writeback operand
1920 switch (Inst.getOpcode()) {
1921 case ARM::VLD1d8_UPD:
1922 case ARM::VLD1d16_UPD:
1923 case ARM::VLD1d32_UPD:
1924 case ARM::VLD1d64_UPD:
1925 case ARM::VLD1q8_UPD:
1926 case ARM::VLD1q16_UPD:
1927 case ARM::VLD1q32_UPD:
1928 case ARM::VLD1q64_UPD:
1929 case ARM::VLD1d8T_UPD:
1930 case ARM::VLD1d16T_UPD:
1931 case ARM::VLD1d32T_UPD:
1932 case ARM::VLD1d64T_UPD:
1933 case ARM::VLD1d8Q_UPD:
1934 case ARM::VLD1d16Q_UPD:
1935 case ARM::VLD1d32Q_UPD:
1936 case ARM::VLD1d64Q_UPD:
1937 case ARM::VLD2d8_UPD:
1938 case ARM::VLD2d16_UPD:
1939 case ARM::VLD2d32_UPD:
1940 case ARM::VLD2q8_UPD:
1941 case ARM::VLD2q16_UPD:
1942 case ARM::VLD2q32_UPD:
1943 case ARM::VLD2b8_UPD:
1944 case ARM::VLD2b16_UPD:
1945 case ARM::VLD2b32_UPD:
1946 case ARM::VLD3d8_UPD:
1947 case ARM::VLD3d16_UPD:
1948 case ARM::VLD3d32_UPD:
1949 case ARM::VLD3q8_UPD:
1950 case ARM::VLD3q16_UPD:
1951 case ARM::VLD3q32_UPD:
1952 case ARM::VLD4d8_UPD:
1953 case ARM::VLD4d16_UPD:
1954 case ARM::VLD4d32_UPD:
1955 case ARM::VLD4q8_UPD:
1956 case ARM::VLD4q16_UPD:
1957 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1958 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1959 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1960 break;
1961 default:
1962 break;
1963 }
1964
1965 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1966 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1967 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1968
1969 // AddrMode6 Offset (register)
1970 if (Rm == 0xD)
1971 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1972 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1973 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1974 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1975 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1976
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1977 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1978}
1979
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1980static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1981 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1982 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1983
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1984 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1985 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1986 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1987 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1988 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1989 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1990
1991 // Writeback Operand
1992 switch (Inst.getOpcode()) {
1993 case ARM::VST1d8_UPD:
1994 case ARM::VST1d16_UPD:
1995 case ARM::VST1d32_UPD:
1996 case ARM::VST1d64_UPD:
1997 case ARM::VST1q8_UPD:
1998 case ARM::VST1q16_UPD:
1999 case ARM::VST1q32_UPD:
2000 case ARM::VST1q64_UPD:
2001 case ARM::VST1d8T_UPD:
2002 case ARM::VST1d16T_UPD:
2003 case ARM::VST1d32T_UPD:
2004 case ARM::VST1d64T_UPD:
2005 case ARM::VST1d8Q_UPD:
2006 case ARM::VST1d16Q_UPD:
2007 case ARM::VST1d32Q_UPD:
2008 case ARM::VST1d64Q_UPD:
2009 case ARM::VST2d8_UPD:
2010 case ARM::VST2d16_UPD:
2011 case ARM::VST2d32_UPD:
2012 case ARM::VST2q8_UPD:
2013 case ARM::VST2q16_UPD:
2014 case ARM::VST2q32_UPD:
2015 case ARM::VST2b8_UPD:
2016 case ARM::VST2b16_UPD:
2017 case ARM::VST2b32_UPD:
2018 case ARM::VST3d8_UPD:
2019 case ARM::VST3d16_UPD:
2020 case ARM::VST3d32_UPD:
2021 case ARM::VST3q8_UPD:
2022 case ARM::VST3q16_UPD:
2023 case ARM::VST3q32_UPD:
2024 case ARM::VST4d8_UPD:
2025 case ARM::VST4d16_UPD:
2026 case ARM::VST4d32_UPD:
2027 case ARM::VST4q8_UPD:
2028 case ARM::VST4q16_UPD:
2029 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2030 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2031 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2032 break;
2033 default:
2034 break;
2035 }
2036
2037 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2038 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2039 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2040
2041 // AddrMode6 Offset (register)
2042 if (Rm == 0xD)
2043 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2044 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2045 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2046 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2047 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2048
2049 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2051 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2052
2053 // Second input register
2054 switch (Inst.getOpcode()) {
2055 case ARM::VST1q8:
2056 case ARM::VST1q16:
2057 case ARM::VST1q32:
2058 case ARM::VST1q64:
2059 case ARM::VST1q8_UPD:
2060 case ARM::VST1q16_UPD:
2061 case ARM::VST1q32_UPD:
2062 case ARM::VST1q64_UPD:
2063 case ARM::VST1d8T:
2064 case ARM::VST1d16T:
2065 case ARM::VST1d32T:
2066 case ARM::VST1d64T:
2067 case ARM::VST1d8T_UPD:
2068 case ARM::VST1d16T_UPD:
2069 case ARM::VST1d32T_UPD:
2070 case ARM::VST1d64T_UPD:
2071 case ARM::VST1d8Q:
2072 case ARM::VST1d16Q:
2073 case ARM::VST1d32Q:
2074 case ARM::VST1d64Q:
2075 case ARM::VST1d8Q_UPD:
2076 case ARM::VST1d16Q_UPD:
2077 case ARM::VST1d32Q_UPD:
2078 case ARM::VST1d64Q_UPD:
2079 case ARM::VST2d8:
2080 case ARM::VST2d16:
2081 case ARM::VST2d32:
2082 case ARM::VST2d8_UPD:
2083 case ARM::VST2d16_UPD:
2084 case ARM::VST2d32_UPD:
2085 case ARM::VST2q8:
2086 case ARM::VST2q16:
2087 case ARM::VST2q32:
2088 case ARM::VST2q8_UPD:
2089 case ARM::VST2q16_UPD:
2090 case ARM::VST2q32_UPD:
2091 case ARM::VST3d8:
2092 case ARM::VST3d16:
2093 case ARM::VST3d32:
2094 case ARM::VST3d8_UPD:
2095 case ARM::VST3d16_UPD:
2096 case ARM::VST3d32_UPD:
2097 case ARM::VST4d8:
2098 case ARM::VST4d16:
2099 case ARM::VST4d32:
2100 case ARM::VST4d8_UPD:
2101 case ARM::VST4d16_UPD:
2102 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2103 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2104 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2105 break;
2106 case ARM::VST2b8:
2107 case ARM::VST2b16:
2108 case ARM::VST2b32:
2109 case ARM::VST2b8_UPD:
2110 case ARM::VST2b16_UPD:
2111 case ARM::VST2b32_UPD:
2112 case ARM::VST3q8:
2113 case ARM::VST3q16:
2114 case ARM::VST3q32:
2115 case ARM::VST3q8_UPD:
2116 case ARM::VST3q16_UPD:
2117 case ARM::VST3q32_UPD:
2118 case ARM::VST4q8:
2119 case ARM::VST4q16:
2120 case ARM::VST4q32:
2121 case ARM::VST4q8_UPD:
2122 case ARM::VST4q16_UPD:
2123 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2124 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2125 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2126 break;
2127 default:
2128 break;
2129 }
2130
2131 // Third input register
2132 switch (Inst.getOpcode()) {
2133 case ARM::VST1d8T:
2134 case ARM::VST1d16T:
2135 case ARM::VST1d32T:
2136 case ARM::VST1d64T:
2137 case ARM::VST1d8T_UPD:
2138 case ARM::VST1d16T_UPD:
2139 case ARM::VST1d32T_UPD:
2140 case ARM::VST1d64T_UPD:
2141 case ARM::VST1d8Q:
2142 case ARM::VST1d16Q:
2143 case ARM::VST1d32Q:
2144 case ARM::VST1d64Q:
2145 case ARM::VST1d8Q_UPD:
2146 case ARM::VST1d16Q_UPD:
2147 case ARM::VST1d32Q_UPD:
2148 case ARM::VST1d64Q_UPD:
2149 case ARM::VST2q8:
2150 case ARM::VST2q16:
2151 case ARM::VST2q32:
2152 case ARM::VST2q8_UPD:
2153 case ARM::VST2q16_UPD:
2154 case ARM::VST2q32_UPD:
2155 case ARM::VST3d8:
2156 case ARM::VST3d16:
2157 case ARM::VST3d32:
2158 case ARM::VST3d8_UPD:
2159 case ARM::VST3d16_UPD:
2160 case ARM::VST3d32_UPD:
2161 case ARM::VST4d8:
2162 case ARM::VST4d16:
2163 case ARM::VST4d32:
2164 case ARM::VST4d8_UPD:
2165 case ARM::VST4d16_UPD:
2166 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2167 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2168 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2169 break;
2170 case ARM::VST3q8:
2171 case ARM::VST3q16:
2172 case ARM::VST3q32:
2173 case ARM::VST3q8_UPD:
2174 case ARM::VST3q16_UPD:
2175 case ARM::VST3q32_UPD:
2176 case ARM::VST4q8:
2177 case ARM::VST4q16:
2178 case ARM::VST4q32:
2179 case ARM::VST4q8_UPD:
2180 case ARM::VST4q16_UPD:
2181 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2182 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2183 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2184 break;
2185 default:
2186 break;
2187 }
2188
2189 // Fourth input register
2190 switch (Inst.getOpcode()) {
2191 case ARM::VST1d8Q:
2192 case ARM::VST1d16Q:
2193 case ARM::VST1d32Q:
2194 case ARM::VST1d64Q:
2195 case ARM::VST1d8Q_UPD:
2196 case ARM::VST1d16Q_UPD:
2197 case ARM::VST1d32Q_UPD:
2198 case ARM::VST1d64Q_UPD:
2199 case ARM::VST2q8:
2200 case ARM::VST2q16:
2201 case ARM::VST2q32:
2202 case ARM::VST2q8_UPD:
2203 case ARM::VST2q16_UPD:
2204 case ARM::VST2q32_UPD:
2205 case ARM::VST4d8:
2206 case ARM::VST4d16:
2207 case ARM::VST4d32:
2208 case ARM::VST4d8_UPD:
2209 case ARM::VST4d16_UPD:
2210 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2211 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2212 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2213 break;
2214 case ARM::VST4q8:
2215 case ARM::VST4q16:
2216 case ARM::VST4q32:
2217 case ARM::VST4q8_UPD:
2218 case ARM::VST4q16_UPD:
2219 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2220 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2221 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2222 break;
2223 default:
2224 break;
2225 }
2226
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2227 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2228}
2229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2230static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2231 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2232 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2233
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2234 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2235 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2236 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2237 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2238 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2239 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2240 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2241
2242 align *= (1 << size);
2243
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2245 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2246 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2247 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2248 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2249 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2250 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2252 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2253 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2256 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2257 Inst.addOperand(MCOperand::CreateImm(align));
2258
2259 if (Rm == 0xD)
2260 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2261 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2263 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2264 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2265
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2266 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2267}
2268
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2269static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2270 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2271 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2272
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2273 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2274 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2275 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2276 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2277 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2278 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2279 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2280 align *= 2*size;
2281
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2282 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2283 return MCDisassembler::Fail;
2284 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2285 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2286 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2288 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2289 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2290
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2292 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2293 Inst.addOperand(MCOperand::CreateImm(align));
2294
2295 if (Rm == 0xD)
2296 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2297 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2299 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2300 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2301
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2302 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2303}
2304
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2305static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2306 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2307 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2308
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2309 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2310 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2311 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2312 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2313 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2314
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2315 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2316 return MCDisassembler::Fail;
2317 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2318 return MCDisassembler::Fail;
2319 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2320 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2321 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2323 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2324 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2325
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2327 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2328 Inst.addOperand(MCOperand::CreateImm(0));
2329
2330 if (Rm == 0xD)
2331 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2332 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2334 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2335 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2336
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2337 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2338}
2339
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2340static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2341 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2342 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2343
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2344 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2345 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2346 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2347 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2348 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2349 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2350 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2351
2352 if (size == 0x3) {
2353 size = 4;
2354 align = 16;
2355 } else {
2356 if (size == 2) {
2357 size = 1 << size;
2358 align *= 8;
2359 } else {
2360 size = 1 << size;
2361 align *= 4*size;
2362 }
2363 }
2364
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2366 return MCDisassembler::Fail;
2367 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2368 return MCDisassembler::Fail;
2369 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2370 return MCDisassembler::Fail;
2371 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2372 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2373 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2375 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2376 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2377
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2379 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2380 Inst.addOperand(MCOperand::CreateImm(align));
2381
2382 if (Rm == 0xD)
2383 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2384 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2386 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2387 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2388
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2389 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2390}
2391
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2392static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2393DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2394 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2395 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2396
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2397 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2398 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2399 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2400 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2401 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2402 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2403 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2404 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2405
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2406 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2407 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2408 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2409 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2410 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2411 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2412 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2413
2414 Inst.addOperand(MCOperand::CreateImm(imm));
2415
2416 switch (Inst.getOpcode()) {
2417 case ARM::VORRiv4i16:
2418 case ARM::VORRiv2i32:
2419 case ARM::VBICiv4i16:
2420 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2421 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2422 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2423 break;
2424 case ARM::VORRiv8i16:
2425 case ARM::VORRiv4i32:
2426 case ARM::VBICiv8i16:
2427 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2428 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2429 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2430 break;
2431 default:
2432 break;
2433 }
2434
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2435 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2436}
2437
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2438static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2439 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2440 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2441
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2442 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2443 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2444 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2445 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2446 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2447
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2448 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2449 return MCDisassembler::Fail;
2450 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2451 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2452 Inst.addOperand(MCOperand::CreateImm(8 << size));
2453
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2454 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2455}
2456
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2457static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2458 uint64_t Address, const void *Decoder) {
2459 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2460 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2461}
2462
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2463static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2464 uint64_t Address, const void *Decoder) {
2465 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2466 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2467}
2468
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2469static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2470 uint64_t Address, const void *Decoder) {
2471 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2472 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2473}
2474
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2475static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2476 uint64_t Address, const void *Decoder) {
2477 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2478 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2479}
2480
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2481static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2482 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2483 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2484
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2485 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2486 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2487 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2488 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2489 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2490 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2491 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2492 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2493
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2494 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2495 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2496 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2497 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2498 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2499 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2500
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2501 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2502 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2503 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2504 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2505
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2506 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2507 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2508
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2509 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2510}
2511
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2512static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513 uint64_t Address, const void *Decoder) {
2514 // The immediate needs to be a fully instantiated float. However, the
2515 // auto-generated decoder is only able to fill in some of the bits
2516 // necessary. For instance, the 'b' bit is replicated multiple times,
2517 // and is even present in inverted form in one bit. We do a little
2518 // binary parsing here to fill in those missing bits, and then
2519 // reinterpret it all as a float.
2520 union {
2521 uint32_t integer;
2522 float fp;
2523 } fp_conv;
2524
2525 fp_conv.integer = Val;
2526 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2527 fp_conv.integer |= b << 26;
2528 fp_conv.integer |= b << 27;
2529 fp_conv.integer |= b << 28;
2530 fp_conv.integer |= b << 29;
2531 fp_conv.integer |= (~b & 0x1) << 30;
2532
2533 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2534 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2535}
2536
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2537static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2538 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2539 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2540
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2541 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2542 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2543
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2544 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2545 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2546
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2547 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2548 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2549 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2550 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2551 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2552 case ARM::tADDrSPi:
2553 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2554 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2555 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2556
2557 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2558 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2559}
2560
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2561static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2562 uint64_t Address, const void *Decoder) {
2563 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2564 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2565}
2566
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2567static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2568 uint64_t Address, const void *Decoder) {
2569 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2570 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2571}
2572
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2573static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2574 uint64_t Address, const void *Decoder) {
2575 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2576 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2577}
2578
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2579static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2580 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2581 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2582
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2583 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2584 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2585
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2586 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2587 return MCDisassembler::Fail;
2588 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2589 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2590
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2591 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2592}
2593
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2594static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2595 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2596 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2597
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2598 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2599 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2600
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2601 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2602 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2603 Inst.addOperand(MCOperand::CreateImm(imm));
2604
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2605 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606}
2607
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2608static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2609 uint64_t Address, const void *Decoder) {
2610 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2611
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2612 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2613}
2614
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2615static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2616 uint64_t Address, const void *Decoder) {
2617 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2618 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2619
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2620 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2621}
2622
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2623static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2624 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2625 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2626
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2627 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2628 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2629 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2630
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2632 return MCDisassembler::Fail;
2633 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2634 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2635 Inst.addOperand(MCOperand::CreateImm(imm));
2636
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2637 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2638}
2639
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2640static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2641 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2642 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2643
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2644 switch (Inst.getOpcode()) {
2645 case ARM::t2PLDs:
2646 case ARM::t2PLDWs:
2647 case ARM::t2PLIs:
2648 break;
2649 default: {
2650 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2652 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2653 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2654 }
2655
2656 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2657 if (Rn == 0xF) {
2658 switch (Inst.getOpcode()) {
2659 case ARM::t2LDRBs:
2660 Inst.setOpcode(ARM::t2LDRBpci);
2661 break;
2662 case ARM::t2LDRHs:
2663 Inst.setOpcode(ARM::t2LDRHpci);
2664 break;
2665 case ARM::t2LDRSHs:
2666 Inst.setOpcode(ARM::t2LDRSHpci);
2667 break;
2668 case ARM::t2LDRSBs:
2669 Inst.setOpcode(ARM::t2LDRSBpci);
2670 break;
2671 case ARM::t2PLDs:
2672 Inst.setOpcode(ARM::t2PLDi12);
2673 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2674 break;
2675 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2676 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2677 }
2678
2679 int imm = fieldFromInstruction32(Insn, 0, 12);
2680 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2681 Inst.addOperand(MCOperand::CreateImm(imm));
2682
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2683 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684 }
2685
2686 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2687 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2688 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2689 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2690 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2691
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2692 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2693}
2694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2695static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2696 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2697 int imm = Val & 0xFF;
2698 if (!(Val & 0x100)) imm *= -1;
2699 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2700
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2701 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2702}
2703
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2704static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2705 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2706 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2707
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2708 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2709 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2710
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2712 return MCDisassembler::Fail;
2713 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2714 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2715
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2716 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2717}
2718
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2719static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2720 uint64_t Address, const void *Decoder) {
2721 DecodeStatus S = MCDisassembler::Success;
2722
2723 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2724 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2725
2726 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2727 return MCDisassembler::Fail;
2728
2729 Inst.addOperand(MCOperand::CreateImm(imm));
2730
2731 return S;
2732}
2733
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2734static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2735 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2736 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2737 if (Val == 0)
2738 imm = INT32_MIN;
2739 else if (!(Val & 0x100))
2740 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2741 Inst.addOperand(MCOperand::CreateImm(imm));
2742
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2743 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2744}
2745
2746
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2747static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2748 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2749 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2750
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2751 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2752 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2753
2754 // Some instructions always use an additive offset.
2755 switch (Inst.getOpcode()) {
2756 case ARM::t2LDRT:
2757 case ARM::t2LDRBT:
2758 case ARM::t2LDRHT:
2759 case ARM::t2LDRSBT:
2760 case ARM::t2LDRSHT:
2761 imm |= 0x100;
2762 break;
2763 default:
2764 break;
2765 }
2766
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2768 return MCDisassembler::Fail;
2769 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2770 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2771
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2772 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2773}
2774
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2775static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2776 uint64_t Address, const void *Decoder) {
2777 DecodeStatus S = MCDisassembler::Success;
2778
2779 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2780 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2781 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2782 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2783 addr |= Rn << 9;
2784 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2785
2786 if (!load) {
2787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2788 return MCDisassembler::Fail;
2789 }
2790
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2791 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2792 return MCDisassembler::Fail;
2793
2794 if (load) {
2795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2796 return MCDisassembler::Fail;
2797 }
2798
2799 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2800 return MCDisassembler::Fail;
2801
2802 return S;
2803}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2805static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2806 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2807 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2808
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2809 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2810 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2811
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2813 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2814 Inst.addOperand(MCOperand::CreateImm(imm));
2815
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2816 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817}
2818
2819
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2820static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2821 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2822 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2823
2824 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2825 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2826 Inst.addOperand(MCOperand::CreateImm(imm));
2827
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2828 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2829}
2830
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2831static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2832 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2833 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2834
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2835 if (Inst.getOpcode() == ARM::tADDrSP) {
2836 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2837 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2838
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2840 return MCDisassembler::Fail;
2841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2842 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2843 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2844 } else if (Inst.getOpcode() == ARM::tADDspr) {
2845 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2846
2847 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2848 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2850 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2851 }
2852
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2853 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2854}
2855
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2856static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2857 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2858 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2859 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2860
2861 Inst.addOperand(MCOperand::CreateImm(imod));
2862 Inst.addOperand(MCOperand::CreateImm(flags));
2863
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2864 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2865}
2866
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2867static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2868 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2869 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2870 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2871 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2872
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2874 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2875 Inst.addOperand(MCOperand::CreateImm(add));
2876
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2877 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2878}
2879
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2880static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2881 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2882 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2883 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2884}
2885
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2886static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2887 uint64_t Address, const void *Decoder) {
2888 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2889 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2890
2891 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2892 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893}
2894
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2895static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2896DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2897 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2898 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2899
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2901 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2902 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2903 switch (opc) {
2904 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2905 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2906 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907 Inst.setOpcode(ARM::t2DSB);
2908 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2909 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2910 Inst.setOpcode(ARM::t2DMB);
2911 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2912 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2913 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2914 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2915 }
2916
2917 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2918 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2919 }
2920
2921 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2922 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2923 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2924 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2925 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2926
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2927 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2928 return MCDisassembler::Fail;
2929 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2930 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2931
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2932 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2933}
2934
2935// Decode a shifted immediate operand. These basically consist
2936// of an 8-bit value, and a 4-bit directive that specifies either
2937// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2938static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2939 uint64_t Address, const void *Decoder) {
2940 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2941 if (ctrl == 0) {
2942 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2943 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2944 switch (byte) {
2945 case 0:
2946 Inst.addOperand(MCOperand::CreateImm(imm));
2947 break;
2948 case 1:
2949 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2950 break;
2951 case 2:
2952 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2953 break;
2954 case 3:
2955 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2956 (imm << 8) | imm));
2957 break;
2958 }
2959 } else {
2960 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2961 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2962 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2963 Inst.addOperand(MCOperand::CreateImm(imm));
2964 }
2965
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2966 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2967}
2968
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2969static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2970DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2971 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2972 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2973 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2974}
2975
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2976static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2977 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2978 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2979 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2980}
2981
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2982static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2983 uint64_t Address, const void *Decoder) {
2984 switch (Val) {
2985 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2986 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2987 case 0xF: // SY
2988 case 0xE: // ST
2989 case 0xB: // ISH
2990 case 0xA: // ISHST
2991 case 0x7: // NSH
2992 case 0x6: // NSHST
2993 case 0x3: // OSH
2994 case 0x2: // OSHST
2995 break;
2996 }
2997
2998 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2999 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3000}
3001
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3002static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3003 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3004 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3005 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3006 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3007}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3008
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3009static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3010 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3011 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3012
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3013 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3014 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3015 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3016
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3017 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3018
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3020 return MCDisassembler::Fail;
3021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3022 return MCDisassembler::Fail;
3023 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3024 return MCDisassembler::Fail;
3025 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3026 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3027
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3028 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3029}
3030
3031
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3032static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3033 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3034 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3035
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3036 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3037 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3038 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3039 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3040
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3041 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3042 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3043
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3044 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3045 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3046
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3048 return MCDisassembler::Fail;
3049 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3050 return MCDisassembler::Fail;
3051 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3052 return MCDisassembler::Fail;
3053 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3054 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3055
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3056 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3057}
3058
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3059static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3060 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3061 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3062
3063 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3064 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3065 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3066 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3067 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3068 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3069
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3070 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3071
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3073 return MCDisassembler::Fail;
3074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3075 return MCDisassembler::Fail;
3076 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3077 return MCDisassembler::Fail;
3078 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3079 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3080
3081 return S;
3082}
3083
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3084static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3085 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3086 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3087
3088 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3089 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3090 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3091 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3092 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3093 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3094 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3095
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3096 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3097 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3098
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3100 return MCDisassembler::Fail;
3101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3102 return MCDisassembler::Fail;
3103 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3104 return MCDisassembler::Fail;
3105 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3106 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3107
3108 return S;
3109}
3110
3111
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3112static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3113 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3114 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3115
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3116 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3117 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3118 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3119 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3120 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3121 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3122
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3123 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3124
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3126 return MCDisassembler::Fail;
3127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3128 return MCDisassembler::Fail;
3129 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3130 return MCDisassembler::Fail;
3131 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3132 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3133
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3134 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3135}
3136
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3137static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3138 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3139 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3140
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3141 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3142 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3143 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3144 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3145 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3146 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3147
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3148 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3149
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3151 return MCDisassembler::Fail;
3152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3153 return MCDisassembler::Fail;
3154 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3155 return MCDisassembler::Fail;
3156 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3157 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3158
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3159 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3160}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3161
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3162static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3163 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3164 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3165
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3166 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3167 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3168 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3169 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3170 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3171
3172 unsigned align = 0;
3173 unsigned index = 0;
3174 switch (size) {
3175 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3176 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3177 case 0:
3178 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3179 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3180 index = fieldFromInstruction32(Insn, 5, 3);
3181 break;
3182 case 1:
3183 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3184 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3185 index = fieldFromInstruction32(Insn, 6, 2);
3186 if (fieldFromInstruction32(Insn, 4, 1))
3187 align = 2;
3188 break;
3189 case 2:
3190 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3191 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3192 index = fieldFromInstruction32(Insn, 7, 1);
3193 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3194 align = 4;
3195 }
3196
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3197 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3198 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3199 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3201 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3202 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3204 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3205 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3206 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3207 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3209 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3210 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3211 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3212 }
3213
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3214 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3215 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3216 Inst.addOperand(MCOperand::CreateImm(index));
3217
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3218 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3219}
3220
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3221static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3222 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3223 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3224
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3225 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3226 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3227 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3228 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3229 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3230
3231 unsigned align = 0;
3232 unsigned index = 0;
3233 switch (size) {
3234 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3235 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3236 case 0:
3237 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3238 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3239 index = fieldFromInstruction32(Insn, 5, 3);
3240 break;
3241 case 1:
3242 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3243 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3244 index = fieldFromInstruction32(Insn, 6, 2);
3245 if (fieldFromInstruction32(Insn, 4, 1))
3246 align = 2;
3247 break;
3248 case 2:
3249 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3250 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3251 index = fieldFromInstruction32(Insn, 7, 1);
3252 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3253 align = 4;
3254 }
3255
3256 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3258 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3259 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3261 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3262 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3263 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3264 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3266 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3267 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3268 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3269 }
3270
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3271 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3272 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3273 Inst.addOperand(MCOperand::CreateImm(index));
3274
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3275 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3276}
3277
3278
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3279static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3280 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3281 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3282
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3283 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3284 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3285 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3286 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3287 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3288
3289 unsigned align = 0;
3290 unsigned index = 0;
3291 unsigned inc = 1;
3292 switch (size) {
3293 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3294 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3295 case 0:
3296 index = fieldFromInstruction32(Insn, 5, 3);
3297 if (fieldFromInstruction32(Insn, 4, 1))
3298 align = 2;
3299 break;
3300 case 1:
3301 index = fieldFromInstruction32(Insn, 6, 2);
3302 if (fieldFromInstruction32(Insn, 4, 1))
3303 align = 4;
3304 if (fieldFromInstruction32(Insn, 5, 1))
3305 inc = 2;
3306 break;
3307 case 2:
3308 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3309 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3310 index = fieldFromInstruction32(Insn, 7, 1);
3311 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3312 align = 8;
3313 if (fieldFromInstruction32(Insn, 6, 1))
3314 inc = 2;
3315 break;
3316 }
3317
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3318 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3319 return MCDisassembler::Fail;
3320 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3321 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3322 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3324 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3325 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3327 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3328 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3329 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3330 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3332 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3333 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3334 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3335 }
3336
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3337 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3338 return MCDisassembler::Fail;
3339 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3340 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3341 Inst.addOperand(MCOperand::CreateImm(index));
3342
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3343 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3344}
3345
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3346static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3347 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3348 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3349
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3350 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3351 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3352 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3353 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3354 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3355
3356 unsigned align = 0;
3357 unsigned index = 0;
3358 unsigned inc = 1;
3359 switch (size) {
3360 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3361 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3362 case 0:
3363 index = fieldFromInstruction32(Insn, 5, 3);
3364 if (fieldFromInstruction32(Insn, 4, 1))
3365 align = 2;
3366 break;
3367 case 1:
3368 index = fieldFromInstruction32(Insn, 6, 2);
3369 if (fieldFromInstruction32(Insn, 4, 1))
3370 align = 4;
3371 if (fieldFromInstruction32(Insn, 5, 1))
3372 inc = 2;
3373 break;
3374 case 2:
3375 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3376 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3377 index = fieldFromInstruction32(Insn, 7, 1);
3378 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3379 align = 8;
3380 if (fieldFromInstruction32(Insn, 6, 1))
3381 inc = 2;
3382 break;
3383 }
3384
3385 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3387 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3388 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3390 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3391 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3392 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3393 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3395 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3396 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3397 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3398 }
3399
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3400 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3401 return MCDisassembler::Fail;
3402 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3403 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3404 Inst.addOperand(MCOperand::CreateImm(index));
3405
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3406 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3407}
3408
3409
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3410static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3411 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3412 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3413
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3414 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3415 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3416 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3417 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3418 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3419
3420 unsigned align = 0;
3421 unsigned index = 0;
3422 unsigned inc = 1;
3423 switch (size) {
3424 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3425 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3426 case 0:
3427 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3428 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3429 index = fieldFromInstruction32(Insn, 5, 3);
3430 break;
3431 case 1:
3432 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3433 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3434 index = fieldFromInstruction32(Insn, 6, 2);
3435 if (fieldFromInstruction32(Insn, 5, 1))
3436 inc = 2;
3437 break;
3438 case 2:
3439 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3440 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3441 index = fieldFromInstruction32(Insn, 7, 1);
3442 if (fieldFromInstruction32(Insn, 6, 1))
3443 inc = 2;
3444 break;
3445 }
3446
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3447 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3448 return MCDisassembler::Fail;
3449 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3450 return MCDisassembler::Fail;
3451 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3452 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3453
3454 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3456 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3457 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3459 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3460 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3461 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3462 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3464 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3465 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3466 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3467 }
3468
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3469 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3470 return MCDisassembler::Fail;
3471 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3472 return MCDisassembler::Fail;
3473 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3474 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3475 Inst.addOperand(MCOperand::CreateImm(index));
3476
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3477 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3478}
3479
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3480static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3481 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3482 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3483
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3484 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3485 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3486 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3487 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3488 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3489
3490 unsigned align = 0;
3491 unsigned index = 0;
3492 unsigned inc = 1;
3493 switch (size) {
3494 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3495 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3496 case 0:
3497 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3498 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3499 index = fieldFromInstruction32(Insn, 5, 3);
3500 break;
3501 case 1:
3502 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3503 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3504 index = fieldFromInstruction32(Insn, 6, 2);
3505 if (fieldFromInstruction32(Insn, 5, 1))
3506 inc = 2;
3507 break;
3508 case 2:
3509 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3510 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3511 index = fieldFromInstruction32(Insn, 7, 1);
3512 if (fieldFromInstruction32(Insn, 6, 1))
3513 inc = 2;
3514 break;
3515 }
3516
3517 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3519 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3520 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3522 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3523 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3524 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3525 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3526 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3527 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3528 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3529 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3530 }
3531
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3532 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3533 return MCDisassembler::Fail;
3534 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3535 return MCDisassembler::Fail;
3536 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3537 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3538 Inst.addOperand(MCOperand::CreateImm(index));
3539
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3540 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3541}
3542
3543
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3544static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3545 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3546 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3547
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3548 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3549 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3550 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3551 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3552 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3553
3554 unsigned align = 0;
3555 unsigned index = 0;
3556 unsigned inc = 1;
3557 switch (size) {
3558 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3559 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3560 case 0:
3561 if (fieldFromInstruction32(Insn, 4, 1))
3562 align = 4;
3563 index = fieldFromInstruction32(Insn, 5, 3);
3564 break;
3565 case 1:
3566 if (fieldFromInstruction32(Insn, 4, 1))
3567 align = 8;
3568 index = fieldFromInstruction32(Insn, 6, 2);
3569 if (fieldFromInstruction32(Insn, 5, 1))
3570 inc = 2;
3571 break;
3572 case 2:
3573 if (fieldFromInstruction32(Insn, 4, 2))
3574 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3575 index = fieldFromInstruction32(Insn, 7, 1);
3576 if (fieldFromInstruction32(Insn, 6, 1))
3577 inc = 2;
3578 break;
3579 }
3580
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3581 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3582 return MCDisassembler::Fail;
3583 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3584 return MCDisassembler::Fail;
3585 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3586 return MCDisassembler::Fail;
3587 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3588 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3589
3590 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3592 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3593 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3595 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3596 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3597 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3598 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3600 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3601 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3602 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3603 }
3604
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3606 return MCDisassembler::Fail;
3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3608 return MCDisassembler::Fail;
3609 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3610 return MCDisassembler::Fail;
3611 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3612 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3613 Inst.addOperand(MCOperand::CreateImm(index));
3614
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3615 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3616}
3617
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3618static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3619 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3620 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3621
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3622 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3623 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3624 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3625 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3626 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3627
3628 unsigned align = 0;
3629 unsigned index = 0;
3630 unsigned inc = 1;
3631 switch (size) {
3632 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3633 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3634 case 0:
3635 if (fieldFromInstruction32(Insn, 4, 1))
3636 align = 4;
3637 index = fieldFromInstruction32(Insn, 5, 3);
3638 break;
3639 case 1:
3640 if (fieldFromInstruction32(Insn, 4, 1))
3641 align = 8;
3642 index = fieldFromInstruction32(Insn, 6, 2);
3643 if (fieldFromInstruction32(Insn, 5, 1))
3644 inc = 2;
3645 break;
3646 case 2:
3647 if (fieldFromInstruction32(Insn, 4, 2))
3648 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3649 index = fieldFromInstruction32(Insn, 7, 1);
3650 if (fieldFromInstruction32(Insn, 6, 1))
3651 inc = 2;
3652 break;
3653 }
3654
3655 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3657 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3658 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3660 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3661 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3662 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3663 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3665 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3666 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3667 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3668 }
3669
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3670 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3671 return MCDisassembler::Fail;
3672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3673 return MCDisassembler::Fail;
3674 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3675 return MCDisassembler::Fail;
3676 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3677 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3678 Inst.addOperand(MCOperand::CreateImm(index));
3679
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3680 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3681}
3682
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3683static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3684 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3685 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3686 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3687 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3688 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3689 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3690 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3691
3692 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3693 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3695 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3696 return MCDisassembler::Fail;
3697 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3698 return MCDisassembler::Fail;
3699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3700 return MCDisassembler::Fail;
3701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3702 return MCDisassembler::Fail;
3703 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3704 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3705
3706 return S;
3707}
3708
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3709static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3710 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3711 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3712 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3713 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3714 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3715 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3716 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3717
3718 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3719 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3720
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3722 return MCDisassembler::Fail;
3723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3724 return MCDisassembler::Fail;
3725 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3726 return MCDisassembler::Fail;
3727 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3728 return MCDisassembler::Fail;
3729 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3730 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3731
3732 return S;
3733}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3734
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3735static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3736 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3737 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3738 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3739 // The InstPrinter needs to have the low bit of the predicate in
3740 // the mask operand to be able to print it properly.
3741 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3742
3743 if (pred == 0xF) {
3744 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3745 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3746 }
3747
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3748 if ((mask & 0xF) == 0) {
3749 // Preserve the high bit of the mask, which is the low bit of
3750 // the predicate.
3751 mask &= 0x10;
3752 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3753 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3754 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3755
3756 Inst.addOperand(MCOperand::CreateImm(pred));
3757 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3758 return S;
3759}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3760
3761static DecodeStatus
3762DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3763 uint64_t Address, const void *Decoder) {
3764 DecodeStatus S = MCDisassembler::Success;
3765
3766 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3767 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3768 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3769 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3770 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3771 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3772 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3773 bool writeback = (W == 1) | (P == 0);
3774
3775 addr |= (U << 8) | (Rn << 9);
3776
3777 if (writeback && (Rn == Rt || Rn == Rt2))
3778 Check(S, MCDisassembler::SoftFail);
3779 if (Rt == Rt2)
3780 Check(S, MCDisassembler::SoftFail);
3781
3782 // Rt
3783 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3784 return MCDisassembler::Fail;
3785 // Rt2
3786 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3787 return MCDisassembler::Fail;
3788 // Writeback operand
3789 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3790 return MCDisassembler::Fail;
3791 // addr
3792 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3793 return MCDisassembler::Fail;
3794
3795 return S;
3796}
3797
3798static DecodeStatus
3799DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3800 uint64_t Address, const void *Decoder) {
3801 DecodeStatus S = MCDisassembler::Success;
3802
3803 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3804 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3805 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3806 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3807 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3808 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3809 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3810 bool writeback = (W == 1) | (P == 0);
3811
3812 addr |= (U << 8) | (Rn << 9);
3813
3814 if (writeback && (Rn == Rt || Rn == Rt2))
3815 Check(S, MCDisassembler::SoftFail);
3816
3817 // Writeback operand
3818 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3819 return MCDisassembler::Fail;
3820 // Rt
3821 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3822 return MCDisassembler::Fail;
3823 // Rt2
3824 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3825 return MCDisassembler::Fail;
3826 // addr
3827 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3828 return MCDisassembler::Fail;
3829
3830 return S;
3831}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]3832
3833static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3834 uint64_t Address, const void *Decoder) {
3835 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3836 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3837 if (sign1 != sign2) return MCDisassembler::Fail;
3838
3839 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3840 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3841 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3842 Val |= sign1 << 12;
3843 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3844
3845 return MCDisassembler::Success;
3846}
3847