Blame - lib/Target/ARM/Disassembler/ARMDisassembler.cpp - platform/external/llvm

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Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	1	//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ------ C++ --===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	12	#include "ARM.h"
				13	#include "ARMRegisterInfo.h"
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	14	#include "ARMSubtarget.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	15	#include "MCTargetDesc/ARMAddressingModes.h"
				16	#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	17	#include "llvm/MC/EDInstInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	18	#include "llvm/MC/MCInst.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	19	#include "llvm/MC/MCExpr.h"
				20	#include "llvm/MC/MCContext.h"
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	21	#include "llvm/MC/MCDisassembler.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/Debug.h"
				23	#include "llvm/Support/MemoryObject.h"
				24	#include "llvm/Support/ErrorHandling.h"
Evan Cheng	3e74d6f	2011-08-24 18:08:43 +0000	[diff] [blame]	25	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	26	#include "llvm/Support/raw_ostream.h"
				27
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	28	using namespace llvm;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	29
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	30	typedef MCDisassembler::DecodeStatus DecodeStatus;
				31
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	32	namespace {
				33	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				34	class ARMDisassembler : public MCDisassembler {
				35	public:
				36	/// Constructor - Initializes the disassembler.
				37	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	38	ARMDisassembler(const MCSubtargetInfo &STI) :
				39	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	40	}
				41
				42	~ARMDisassembler() {
				43	}
				44
				45	/// getInstruction - See MCDisassembler.
				46	DecodeStatus getInstruction(MCInst &instr,
				47	uint64_t &size,
				48	const MemoryObject &region,
				49	uint64_t address,
				50	raw_ostream &vStream) const;
				51
				52	/// getEDInfo - See MCDisassembler.
				53	EDInstInfo *getEDInfo() const;
				54	private:
				55	};
				56
				57	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				58	class ThumbDisassembler : public MCDisassembler {
				59	public:
				60	/// Constructor - Initializes the disassembler.
				61	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	62	ThumbDisassembler(const MCSubtargetInfo &STI) :
				63	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	64	}
				65
				66	~ThumbDisassembler() {
				67	}
				68
				69	/// getInstruction - See MCDisassembler.
				70	DecodeStatus getInstruction(MCInst &instr,
				71	uint64_t &size,
				72	const MemoryObject &region,
				73	uint64_t address,
				74	raw_ostream &vStream) const;
				75
				76	/// getEDInfo - See MCDisassembler.
				77	EDInstInfo *getEDInfo() const;
				78	private:
				79	mutable std::vector<unsigned> ITBlock;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	80	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	81	void UpdateThumbVFPPredicate(MCInst&) const;
				82	};
				83	}
				84
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	85	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	86	switch (In) {
				87	case MCDisassembler::Success:
				88	// Out stays the same.
				89	return true;
				90	case MCDisassembler::SoftFail:
				91	Out = In;
				92	return true;
				93	case MCDisassembler::Fail:
				94	Out = In;
				95	return false;
				96	}
				97	return false;
				98	}
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	99
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	100
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	101	// Forward declare these because the autogenerated code will reference them.
				102	// Definitions are further down.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	103	static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	104	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	105	static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	106	unsigned RegNo, uint64_t Address,
				107	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	108	static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	109	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	110	static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	111	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	112	static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	113	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	114	static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	115	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	116	static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	117	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	118	static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	119	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	120	static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	121	unsigned RegNo,
				122	uint64_t Address,
				123	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	124	static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	125	uint64_t Address, const void *Decoder);
Johnny Chen	270159f	2010-08-12 01:40:54 +0000	[diff] [blame]	126
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	127	static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	128	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	129	static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	130	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	131	static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	132	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	133	static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	134	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	135	static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	136	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	137	static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	138	uint64_t Address, const void *Decoder);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	139
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	140	static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	141	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	142	static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	143	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	144	static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	145	unsigned Insn,
				146	uint64_t Address,
				147	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	148	static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	149	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	150	static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	151	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	152	static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	153	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	154	static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	155	uint64_t Address, const void *Decoder);
				156
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	157	static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	158	unsigned Insn,
				159	uint64_t Adddress,
				160	const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	161	static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	162	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	163	static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	164	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	165	static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	166	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	167	static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	168	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	169	static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	170	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	171	static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	172	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	173	static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	174	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	175	static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	176	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	177	static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	178	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	179	static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	180	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	181	static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	182	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	183	static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	184	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	185	static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	186	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	187	static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	188	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	189	static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	190	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	191	static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	192	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	193	static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	194	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	195	static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	196	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	197	static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	198	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	199	static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	200	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	201	static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	202	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	203	static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	205	static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	206	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	207	static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	209	static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	211	static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	213	static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	215	static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	217	static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	218	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	219	static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	220	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	221	static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	222	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	223	static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	224	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	225	static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	226	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	227	static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	228	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	229	static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	230	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	231	static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	232	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	233	static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	234	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	235	static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	236	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	237	static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	238	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	239	static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	240	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	241	static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	242	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	243	static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	244	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	245	static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	246	uint64_t Address, const void *Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	247
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	248	static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	249	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	250	static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	251	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	252	static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	254	static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	256	static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	258	static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	260	static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	262	static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	264	static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	266	static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	268	static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	270	static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	272	static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
				273	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	274	static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	276	static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	278	static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	280	static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	282	static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	284	static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	285	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	286	static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	288	static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	290	static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	292	static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	294	static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	296	static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	298	static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
				299	uint64_t Address, const void *Decoder);
				300	static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
				301	uint64_t Address, const void *Decoder);
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	302	static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
				303	uint64_t Address, const void *Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	304
				305	#include "ARMGenDisassemblerTables.inc"
				306	#include "ARMGenInstrInfo.inc"
Oscar Fuentes	38e1390	2010-09-28 11:48:19 +0000	[diff] [blame]	307	#include "ARMGenEDInfo.inc"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	308
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	309	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				310	return new ARMDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	311	}
				312
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	313	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				314	return new ThumbDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	315	}
				316
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	317	EDInstInfo *ARMDisassembler::getEDInfo() const {
				318	return instInfoARM;
				319	}
				320
				321	EDInstInfo *ThumbDisassembler::getEDInfo() const {
				322	return instInfoARM;
				323	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	324
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	325	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	326	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	327	uint64_t Address,
				328	raw_ostream &os) const {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	329	uint8_t bytes[4];
				330
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	331	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				332	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				333
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	334	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	335	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				336	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	337	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	338	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	339
				340	// Encoded as a small-endian 32-bit word in the stream.
				341	uint32_t insn = (bytes[3] << 24) \|
				342	(bytes[2] << 16) \|
				343	(bytes[1] << 8) \|
				344	(bytes[0] << 0);
				345
				346	// Calling the auto-generated decoder function.
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	347	DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	348	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	349	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	350	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	351	}
				352
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	353	// VFP and NEON instructions, similarly, are shared between ARM
				354	// and Thumb modes.
				355	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	356	result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	357	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	358	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	359	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	360	}
				361
				362	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	363	result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	364	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	365	Size = 4;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	366	// Add a fake predicate operand, because we share these instruction
				367	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	368	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				369	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	370	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	371	}
				372
				373	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	374	result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	375	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	376	Size = 4;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	377	// Add a fake predicate operand, because we share these instruction
				378	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	379	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				380	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	381	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	382	}
				383
				384	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	385	result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	386	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	387	Size = 4;
				388	// Add a fake predicate operand, because we share these instruction
				389	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	390	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				391	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	392	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	393	}
				394
				395	MI.clear();
				396
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	397	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	398	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	399	}
				400
				401	namespace llvm {
				402	extern MCInstrDesc ARMInsts[];
				403	}
				404
				405	// Thumb1 instructions don't have explicit S bits. Rather, they
				406	// implicitly set CPSR. Since it's not represented in the encoding, the
				407	// auto-generated decoder won't inject the CPSR operand. We need to fix
				408	// that as a post-pass.
				409	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				410	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	411	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	412	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	413	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				414	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	415	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	416	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	417	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				418	return;
				419	}
				420	}
				421
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	422	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	423	}
				424
				425	// Most Thumb instructions don't have explicit predicates in the
				426	// encoding, but rather get their predicates from IT context. We need
				427	// to fix up the predicate operands using this context information as a
				428	// post-pass.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	429	MCDisassembler::DecodeStatus
				430	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	431	MCDisassembler::DecodeStatus S = Success;
				432
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	433	// A few instructions actually have predicates encoded in them. Don't
				434	// try to overwrite it if we're seeing one of those.
				435	switch (MI.getOpcode()) {
				436	case ARM::tBcc:
				437	case ARM::t2Bcc:
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	438	case ARM::tCBZ:
				439	case ARM::tCBNZ:
Owen Anderson	441462f	2011-09-08 22:48:37 +0000	[diff] [blame]	440	// Some instructions (mostly conditional branches) are not
				441	// allowed in IT blocks.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	442	if (!ITBlock.empty())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	443	S = SoftFail;
				444	else
				445	return Success;
				446	break;
				447	case ARM::tB:
				448	case ARM::t2B:
				449	// Some instructions (mostly unconditional branches) can
				450	// only appears at the end of, or outside of, an IT.
				451	if (ITBlock.size() > 1)
				452	S = SoftFail;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	453	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	454	default:
				455	break;
				456	}
				457
				458	// If we're in an IT block, base the predicate on that. Otherwise,
				459	// assume a predicate of AL.
				460	unsigned CC;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	461	if (!ITBlock.empty()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	462	CC = ITBlock.back();
Owen Anderson	9bd655d	2011-08-26 06:19:51 +0000	[diff] [blame]	463	if (CC == 0xF)
				464	CC = ARMCC::AL;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	465	ITBlock.pop_back();
				466	} else
				467	CC = ARMCC::AL;
				468
				469	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	470	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	471	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	472	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				473	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	474	if (OpInfo[i].isPredicate()) {
				475	I = MI.insert(I, MCOperand::CreateImm(CC));
				476	++I;
				477	if (CC == ARMCC::AL)
				478	MI.insert(I, MCOperand::CreateReg(0));
				479	else
				480	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	481	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	482	}
				483	}
				484
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	485	I = MI.insert(I, MCOperand::CreateImm(CC));
				486	++I;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	487	if (CC == ARMCC::AL)
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	488	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	489	else
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	490	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	491
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	492	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	493	}
				494
				495	// Thumb VFP instructions are a special case. Because we share their
				496	// encodings between ARM and Thumb modes, and they are predicable in ARM
				497	// mode, the auto-generated decoder will give them an (incorrect)
				498	// predicate operand. We need to rewrite these operands based on the IT
				499	// context as a post-pass.
				500	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				501	unsigned CC;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	502	if (!ITBlock.empty()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	503	CC = ITBlock.back();
				504	ITBlock.pop_back();
				505	} else
				506	CC = ARMCC::AL;
				507
				508	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				509	MCInst::iterator I = MI.begin();
Owen Anderson	12a1e3b	2011-08-24 21:35:46 +0000	[diff] [blame]	510	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				511	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	512	if (OpInfo[i].isPredicate() ) {
				513	I->setImm(CC);
				514	++I;
				515	if (CC == ARMCC::AL)
				516	I->setReg(0);
				517	else
				518	I->setReg(ARM::CPSR);
				519	return;
				520	}
				521	}
				522	}
				523
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	524	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	525	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	526	uint64_t Address,
				527	raw_ostream &os) const {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	528	uint8_t bytes[4];
				529
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	530	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				531	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				532
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	533	// We want to read exactly 2 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	534	if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
				535	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	536	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	537	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	538
				539	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	540	DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	541	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	542	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	543	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	544	return result;
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	545	}
				546
				547	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	548	result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	549	if (result) {
				550	Size = 2;
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	551	bool InITBlock = !ITBlock.empty();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	552	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	553	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	554	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	555	}
				556
				557	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	558	result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	559	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	560	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	561	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	562
				563	// If we find an IT instruction, we need to parse its condition
				564	// code and mask operands so that we can apply them correctly
				565	// to the subsequent instructions.
				566	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	567	// (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	568	unsigned firstcond = MI.getOperand(0).getImm();
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	569	unsigned Mask = MI.getOperand(1).getImm();
				570	unsigned CondBit0 = Mask >> 4 & 1;
				571	unsigned NumTZ = CountTrailingZeros_32(Mask);
				572	assert(NumTZ <= 3 && "Invalid IT mask!");
				573	for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
				574	bool T = ((Mask >> Pos) & 1) == CondBit0;
				575	if (T)
				576	ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	577	else
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	578	ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	579	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	580
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	581	ITBlock.push_back(firstcond);
				582	}
				583
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	584	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	585	}
				586
				587	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	588	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				589	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	590	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	591	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	592
				593	uint32_t insn32 = (bytes[3] << 8) \|
				594	(bytes[2] << 0) \|
				595	(bytes[1] << 24) \|
				596	(bytes[0] << 16);
				597	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	598	result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	599	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	600	Size = 4;
				601	bool InITBlock = ITBlock.size();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	602	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	603	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	604	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	605	}
				606
				607	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	608	result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	609	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	610	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	611	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	612	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	613	}
				614
				615	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	616	result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	617	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	618	Size = 4;
				619	UpdateThumbVFPPredicate(MI);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	620	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	621	}
				622
				623	MI.clear();
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	624	result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	625	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	626	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	627	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	628	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	629	}
				630
				631	if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
				632	MI.clear();
				633	uint32_t NEONLdStInsn = insn32;
				634	NEONLdStInsn &= 0xF0FFFFFF;
				635	NEONLdStInsn \|= 0x04000000;
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	636	result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	637	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	638	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	639	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	640	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	641	}
				642	}
				643
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	644	if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	645	MI.clear();
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	646	uint32_t NEONDataInsn = insn32;
				647	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				648	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				649	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	650	result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	651	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	652	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	653	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	654	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	655	}
				656	}
				657
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	658	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	659	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	660	}
				661
				662
				663	extern "C" void LLVMInitializeARMDisassembler() {
				664	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				665	createARMDisassembler);
				666	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				667	createThumbDisassembler);
				668	}
				669
				670	static const unsigned GPRDecoderTable[] = {
				671	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				672	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				673	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				674	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				675	};
				676
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	677	static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	678	uint64_t Address, const void *Decoder) {
				679	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	680	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	681
				682	unsigned Register = GPRDecoderTable[RegNo];
				683	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	684	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	685	}
				686
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	687	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	688	DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
				689	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	690	if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	51c9805	2011-08-09 22:48:45 +0000	[diff] [blame]	691	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				692	}
				693
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	694	static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	695	uint64_t Address, const void *Decoder) {
				696	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	697	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	698	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				699	}
				700
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	701	static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	702	uint64_t Address, const void *Decoder) {
				703	unsigned Register = 0;
				704	switch (RegNo) {
				705	case 0:
				706	Register = ARM::R0;
				707	break;
				708	case 1:
				709	Register = ARM::R1;
				710	break;
				711	case 2:
				712	Register = ARM::R2;
				713	break;
				714	case 3:
				715	Register = ARM::R3;
				716	break;
				717	case 9:
				718	Register = ARM::R9;
				719	break;
				720	case 12:
				721	Register = ARM::R12;
				722	break;
				723	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	724	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	725	}
				726
				727	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	728	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	729	}
				730
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	731	static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	732	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	733	if (RegNo == 13 \|\| RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	734	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				735	}
				736
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	737	static const unsigned SPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	738	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				739	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				740	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				741	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				742	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				743	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				744	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				745	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				746	};
				747
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	748	static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	749	uint64_t Address, const void *Decoder) {
				750	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	751	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	752
				753	unsigned Register = SPRDecoderTable[RegNo];
				754	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	755	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	756	}
				757
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	758	static const unsigned DPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	759	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				760	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				761	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				762	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				763	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				764	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				765	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				766	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				767	};
				768
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	769	static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	770	uint64_t Address, const void *Decoder) {
				771	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	772	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	773
				774	unsigned Register = DPRDecoderTable[RegNo];
				775	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	776	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	777	}
				778
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	779	static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	780	uint64_t Address, const void *Decoder) {
				781	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	782	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	783	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				784	}
				785
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	786	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	787	DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
				788	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	789	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	790	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	791	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				792	}
				793
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	794	static const unsigned QPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	795	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				796	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				797	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				798	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				799	};
				800
				801
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	802	static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	803	uint64_t Address, const void *Decoder) {
				804	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	805	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	806	RegNo >>= 1;
				807
				808	unsigned Register = QPRDecoderTable[RegNo];
				809	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	810	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	811	}
				812
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	813	static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	814	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	815	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	bd9091c	2011-08-09 21:07:45 +0000	[diff] [blame]	816	// AL predicate is not allowed on Thumb1 branches.
				817	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	818	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	819	Inst.addOperand(MCOperand::CreateImm(Val));
				820	if (Val == ARMCC::AL) {
				821	Inst.addOperand(MCOperand::CreateReg(0));
				822	} else
				823	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	824	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	825	}
				826
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	827	static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	828	uint64_t Address, const void *Decoder) {
				829	if (Val)
				830	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				831	else
				832	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	833	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	834	}
				835
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	836	static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	837	uint64_t Address, const void *Decoder) {
				838	uint32_t imm = Val & 0xFF;
				839	uint32_t rot = (Val & 0xF00) >> 7;
				840	uint32_t rot_imm = (imm >> rot) \| (imm << (32-rot));
				841	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	842	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	843	}
				844
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	845	static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	846	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	847	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	848
				849	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				850	unsigned type = fieldFromInstruction32(Val, 5, 2);
				851	unsigned imm = fieldFromInstruction32(Val, 7, 5);
				852
				853	// Register-immediate
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	854	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				855	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	856
				857	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				858	switch (type) {
				859	case 0:
				860	Shift = ARM_AM::lsl;
				861	break;
				862	case 1:
				863	Shift = ARM_AM::lsr;
				864	break;
				865	case 2:
				866	Shift = ARM_AM::asr;
				867	break;
				868	case 3:
				869	Shift = ARM_AM::ror;
				870	break;
				871	}
				872
				873	if (Shift == ARM_AM::ror && imm == 0)
				874	Shift = ARM_AM::rrx;
				875
				876	unsigned Op = Shift \| (imm << 3);
				877	Inst.addOperand(MCOperand::CreateImm(Op));
				878
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	879	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	880	}
				881
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	882	static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	883	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	884	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	885
				886	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				887	unsigned type = fieldFromInstruction32(Val, 5, 2);
				888	unsigned Rs = fieldFromInstruction32(Val, 8, 4);
				889
				890	// Register-register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	891	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				892	return MCDisassembler::Fail;
				893	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				894	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	895
				896	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				897	switch (type) {
				898	case 0:
				899	Shift = ARM_AM::lsl;
				900	break;
				901	case 1:
				902	Shift = ARM_AM::lsr;
				903	break;
				904	case 2:
				905	Shift = ARM_AM::asr;
				906	break;
				907	case 3:
				908	Shift = ARM_AM::ror;
				909	break;
				910	}
				911
				912	Inst.addOperand(MCOperand::CreateImm(Shift));
				913
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	914	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	915	}
				916
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	917	static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	918	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	919	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	920
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	921	// Empty register lists are not allowed.
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	922	if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	923	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	924	if (Val & (1 << i)) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	925	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				926	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	927	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	928	}
				929
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	930	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	931	}
				932
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	933	static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	934	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	935	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	936
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	937	unsigned Vd = fieldFromInstruction32(Val, 8, 4);
				938	unsigned regs = Val & 0xFF;
				939
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	940	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				941	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	942	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	943	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				944	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	945	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	946
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	947	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	948	}
				949
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	950	static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	951	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	952	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	953
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	954	unsigned Vd = fieldFromInstruction32(Val, 8, 4);
				955	unsigned regs = (Val & 0xFF) / 2;
				956
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	957	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				958	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	959	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	960	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				961	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	962	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	963
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	964	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	965	}
				966
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	967	static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	968	uint64_t Address, const void *Decoder) {
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	969	// This operand encodes a mask of contiguous zeros between a specified MSB
				970	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				971	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	972	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	973	// create the final mask.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	974	unsigned msb = fieldFromInstruction32(Val, 5, 5);
				975	unsigned lsb = fieldFromInstruction32(Val, 0, 5);
				976	uint32_t msb_mask = (1 << (msb+1)) - 1;
				977	uint32_t lsb_mask = (1 << lsb) - 1;
				978	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	979	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	980	}
				981
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	982	static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	983	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	984	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	985
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	986	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				987	unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
				988	unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
				989	unsigned imm = fieldFromInstruction32(Insn, 0, 8);
				990	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				991	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				992
				993	switch (Inst.getOpcode()) {
				994	case ARM::LDC_OFFSET:
				995	case ARM::LDC_PRE:
				996	case ARM::LDC_POST:
				997	case ARM::LDC_OPTION:
				998	case ARM::LDCL_OFFSET:
				999	case ARM::LDCL_PRE:
				1000	case ARM::LDCL_POST:
				1001	case ARM::LDCL_OPTION:
				1002	case ARM::STC_OFFSET:
				1003	case ARM::STC_PRE:
				1004	case ARM::STC_POST:
				1005	case ARM::STC_OPTION:
				1006	case ARM::STCL_OFFSET:
				1007	case ARM::STCL_PRE:
				1008	case ARM::STCL_POST:
				1009	case ARM::STCL_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1010	case ARM::t2LDC_OFFSET:
				1011	case ARM::t2LDC_PRE:
				1012	case ARM::t2LDC_POST:
				1013	case ARM::t2LDC_OPTION:
				1014	case ARM::t2LDCL_OFFSET:
				1015	case ARM::t2LDCL_PRE:
				1016	case ARM::t2LDCL_POST:
				1017	case ARM::t2LDCL_OPTION:
				1018	case ARM::t2STC_OFFSET:
				1019	case ARM::t2STC_PRE:
				1020	case ARM::t2STC_POST:
				1021	case ARM::t2STC_OPTION:
				1022	case ARM::t2STCL_OFFSET:
				1023	case ARM::t2STCL_PRE:
				1024	case ARM::t2STCL_POST:
				1025	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1026	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1027	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1028	break;
				1029	default:
				1030	break;
				1031	}
				1032
				1033	Inst.addOperand(MCOperand::CreateImm(coproc));
				1034	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1035	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1036	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1037	switch (Inst.getOpcode()) {
				1038	case ARM::LDC_OPTION:
				1039	case ARM::LDCL_OPTION:
				1040	case ARM::LDC2_OPTION:
				1041	case ARM::LDC2L_OPTION:
				1042	case ARM::STC_OPTION:
				1043	case ARM::STCL_OPTION:
				1044	case ARM::STC2_OPTION:
				1045	case ARM::STC2L_OPTION:
				1046	case ARM::LDCL_POST:
				1047	case ARM::STCL_POST:
Owen Anderson	78affc9	2011-08-18 22:47:44 +0000	[diff] [blame]	1048	case ARM::LDC2L_POST:
				1049	case ARM::STC2L_POST:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1050	case ARM::t2LDC_OPTION:
				1051	case ARM::t2LDCL_OPTION:
				1052	case ARM::t2STC_OPTION:
				1053	case ARM::t2STCL_OPTION:
				1054	case ARM::t2LDCL_POST:
				1055	case ARM::t2STCL_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1056	break;
				1057	default:
				1058	Inst.addOperand(MCOperand::CreateReg(0));
				1059	break;
				1060	}
				1061
				1062	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1063	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1064
				1065	bool writeback = (P == 0) \|\| (W == 1);
				1066	unsigned idx_mode = 0;
				1067	if (P && writeback)
				1068	idx_mode = ARMII::IndexModePre;
				1069	else if (!P && writeback)
				1070	idx_mode = ARMII::IndexModePost;
				1071
				1072	switch (Inst.getOpcode()) {
				1073	case ARM::LDCL_POST:
				1074	case ARM::STCL_POST:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1075	case ARM::t2LDCL_POST:
				1076	case ARM::t2STCL_POST:
Owen Anderson	78affc9	2011-08-18 22:47:44 +0000	[diff] [blame]	1077	case ARM::LDC2L_POST:
				1078	case ARM::STC2L_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1079	imm \|= U << 8;
				1080	case ARM::LDC_OPTION:
				1081	case ARM::LDCL_OPTION:
				1082	case ARM::LDC2_OPTION:
				1083	case ARM::LDC2L_OPTION:
				1084	case ARM::STC_OPTION:
				1085	case ARM::STCL_OPTION:
				1086	case ARM::STC2_OPTION:
				1087	case ARM::STC2L_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1088	case ARM::t2LDC_OPTION:
				1089	case ARM::t2LDCL_OPTION:
				1090	case ARM::t2STC_OPTION:
				1091	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1092	Inst.addOperand(MCOperand::CreateImm(imm));
				1093	break;
				1094	default:
				1095	if (U)
				1096	Inst.addOperand(MCOperand::CreateImm(
				1097	ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
				1098	else
				1099	Inst.addOperand(MCOperand::CreateImm(
				1100	ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
				1101	break;
				1102	}
				1103
				1104	switch (Inst.getOpcode()) {
				1105	case ARM::LDC_OFFSET:
				1106	case ARM::LDC_PRE:
				1107	case ARM::LDC_POST:
				1108	case ARM::LDC_OPTION:
				1109	case ARM::LDCL_OFFSET:
				1110	case ARM::LDCL_PRE:
				1111	case ARM::LDCL_POST:
				1112	case ARM::LDCL_OPTION:
				1113	case ARM::STC_OFFSET:
				1114	case ARM::STC_PRE:
				1115	case ARM::STC_POST:
				1116	case ARM::STC_OPTION:
				1117	case ARM::STCL_OFFSET:
				1118	case ARM::STCL_PRE:
				1119	case ARM::STCL_POST:
				1120	case ARM::STCL_OPTION:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1121	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1122	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1123	break;
				1124	default:
				1125	break;
				1126	}
				1127
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1128	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1129	}
				1130
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1131	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1132	DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
				1133	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1134	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1135
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1136	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1137	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				1138	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1139	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				1140	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1141	unsigned reg = fieldFromInstruction32(Insn, 25, 1);
				1142	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1143	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1144
				1145	// On stores, the writeback operand precedes Rt.
				1146	switch (Inst.getOpcode()) {
				1147	case ARM::STR_POST_IMM:
				1148	case ARM::STR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1149	case ARM::STRB_POST_IMM:
				1150	case ARM::STRB_POST_REG:
Jim Grosbach	342ebd5	2011-08-11 22:18:00 +0000	[diff] [blame]	1151	case ARM::STRT_POST_REG:
				1152	case ARM::STRT_POST_IMM:
Jim Grosbach	10348e7	2011-08-11 20:04:56 +0000	[diff] [blame]	1153	case ARM::STRBT_POST_REG:
				1154	case ARM::STRBT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1155	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1156	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1157	break;
				1158	default:
				1159	break;
				1160	}
				1161
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1162	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1163	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1164
				1165	// On loads, the writeback operand comes after Rt.
				1166	switch (Inst.getOpcode()) {
				1167	case ARM::LDR_POST_IMM:
				1168	case ARM::LDR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1169	case ARM::LDRB_POST_IMM:
				1170	case ARM::LDRB_POST_REG:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1171	case ARM::LDRBT_POST_REG:
				1172	case ARM::LDRBT_POST_IMM:
Jim Grosbach	5999926	2011-08-10 23:43:54 +0000	[diff] [blame]	1173	case ARM::LDRT_POST_REG:
				1174	case ARM::LDRT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1175	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1176	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1177	break;
				1178	default:
				1179	break;
				1180	}
				1181
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1182	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1183	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1184
				1185	ARM_AM::AddrOpc Op = ARM_AM::add;
				1186	if (!fieldFromInstruction32(Insn, 23, 1))
				1187	Op = ARM_AM::sub;
				1188
				1189	bool writeback = (P == 0) \|\| (W == 1);
				1190	unsigned idx_mode = 0;
				1191	if (P && writeback)
				1192	idx_mode = ARMII::IndexModePre;
				1193	else if (!P && writeback)
				1194	idx_mode = ARMII::IndexModePost;
				1195
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1196	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1197	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	71156a6	2011-08-11 19:00:18 +0000	[diff] [blame]	1198
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1199	if (reg) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1200	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1201	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1202	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
				1203	switch( fieldFromInstruction32(Insn, 5, 2)) {
				1204	case 0:
				1205	Opc = ARM_AM::lsl;
				1206	break;
				1207	case 1:
				1208	Opc = ARM_AM::lsr;
				1209	break;
				1210	case 2:
				1211	Opc = ARM_AM::asr;
				1212	break;
				1213	case 3:
				1214	Opc = ARM_AM::ror;
				1215	break;
				1216	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1217	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1218	}
				1219	unsigned amt = fieldFromInstruction32(Insn, 7, 5);
				1220	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1221
				1222	Inst.addOperand(MCOperand::CreateImm(imm));
				1223	} else {
				1224	Inst.addOperand(MCOperand::CreateReg(0));
				1225	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1226	Inst.addOperand(MCOperand::CreateImm(tmp));
				1227	}
				1228
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1229	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1230	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1231
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1232	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1233	}
				1234
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1235	static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1236	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1237	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1238
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1239	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				1240	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				1241	unsigned type = fieldFromInstruction32(Val, 5, 2);
				1242	unsigned imm = fieldFromInstruction32(Val, 7, 5);
				1243	unsigned U = fieldFromInstruction32(Val, 12, 1);
				1244
Owen Anderson	51157d2	2011-08-09 21:38:14 +0000	[diff] [blame]	1245	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1246	switch (type) {
				1247	case 0:
				1248	ShOp = ARM_AM::lsl;
				1249	break;
				1250	case 1:
				1251	ShOp = ARM_AM::lsr;
				1252	break;
				1253	case 2:
				1254	ShOp = ARM_AM::asr;
				1255	break;
				1256	case 3:
				1257	ShOp = ARM_AM::ror;
				1258	break;
				1259	}
				1260
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1261	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1262	return MCDisassembler::Fail;
				1263	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1264	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1265	unsigned shift;
				1266	if (U)
				1267	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1268	else
				1269	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1270	Inst.addOperand(MCOperand::CreateImm(shift));
				1271
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1272	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1273	}
				1274
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1275	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1276	DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
				1277	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1278	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1279
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1280	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				1281	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1282	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1283	unsigned type = fieldFromInstruction32(Insn, 22, 1);
				1284	unsigned imm = fieldFromInstruction32(Insn, 8, 4);
				1285	unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
				1286	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1287	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				1288	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				1289
				1290	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1291
				1292	// For {LD,ST}RD, Rt must be even, else undefined.
				1293	switch (Inst.getOpcode()) {
				1294	case ARM::STRD:
				1295	case ARM::STRD_PRE:
				1296	case ARM::STRD_POST:
				1297	case ARM::LDRD:
				1298	case ARM::LDRD_PRE:
				1299	case ARM::LDRD_POST:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1300	if (Rt & 0x1) return MCDisassembler::Fail;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1301	break;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1302	default:
				1303	break;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1304	}
				1305
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1306	if (writeback) { // Writeback
				1307	if (P)
				1308	U \|= ARMII::IndexModePre << 9;
				1309	else
				1310	U \|= ARMII::IndexModePost << 9;
				1311
				1312	// On stores, the writeback operand precedes Rt.
				1313	switch (Inst.getOpcode()) {
				1314	case ARM::STRD:
				1315	case ARM::STRD_PRE:
				1316	case ARM::STRD_POST:
Owen Anderson	79628e9	2011-08-12 20:02:50 +0000	[diff] [blame]	1317	case ARM::STRH:
				1318	case ARM::STRH_PRE:
				1319	case ARM::STRH_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1320	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1321	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1322	break;
				1323	default:
				1324	break;
				1325	}
				1326	}
				1327
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1328	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1329	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1330	switch (Inst.getOpcode()) {
				1331	case ARM::STRD:
				1332	case ARM::STRD_PRE:
				1333	case ARM::STRD_POST:
				1334	case ARM::LDRD:
				1335	case ARM::LDRD_PRE:
				1336	case ARM::LDRD_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1337	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1338	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1339	break;
				1340	default:
				1341	break;
				1342	}
				1343
				1344	if (writeback) {
				1345	// On loads, the writeback operand comes after Rt.
				1346	switch (Inst.getOpcode()) {
				1347	case ARM::LDRD:
				1348	case ARM::LDRD_PRE:
				1349	case ARM::LDRD_POST:
Owen Anderson	0d09499	2011-08-12 20:36:11 +0000	[diff] [blame]	1350	case ARM::LDRH:
				1351	case ARM::LDRH_PRE:
				1352	case ARM::LDRH_POST:
				1353	case ARM::LDRSH:
				1354	case ARM::LDRSH_PRE:
				1355	case ARM::LDRSH_POST:
				1356	case ARM::LDRSB:
				1357	case ARM::LDRSB_PRE:
				1358	case ARM::LDRSB_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1359	case ARM::LDRHTr:
				1360	case ARM::LDRSBTr:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1361	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1362	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1363	break;
				1364	default:
				1365	break;
				1366	}
				1367	}
				1368
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1369	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1370	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1371
				1372	if (type) {
				1373	Inst.addOperand(MCOperand::CreateReg(0));
				1374	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1375	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1376	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1377	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1378	Inst.addOperand(MCOperand::CreateImm(U));
				1379	}
				1380
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1381	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1382	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1383
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1384	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1385	}
				1386
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1387	static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1388	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1389	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1390
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1391	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1392	unsigned mode = fieldFromInstruction32(Insn, 23, 2);
				1393
				1394	switch (mode) {
				1395	case 0:
				1396	mode = ARM_AM::da;
				1397	break;
				1398	case 1:
				1399	mode = ARM_AM::ia;
				1400	break;
				1401	case 2:
				1402	mode = ARM_AM::db;
				1403	break;
				1404	case 3:
				1405	mode = ARM_AM::ib;
				1406	break;
				1407	}
				1408
				1409	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1410	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1411	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1412
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1413	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1414	}
				1415
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1416	static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1417	unsigned Insn,
				1418	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1419	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1420
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1421	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1422	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1423	unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
				1424
				1425	if (pred == 0xF) {
				1426	switch (Inst.getOpcode()) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1427	case ARM::LDMDA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1428	Inst.setOpcode(ARM::RFEDA);
				1429	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1430	case ARM::LDMDA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1431	Inst.setOpcode(ARM::RFEDA_UPD);
				1432	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1433	case ARM::LDMDB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1434	Inst.setOpcode(ARM::RFEDB);
				1435	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1436	case ARM::LDMDB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1437	Inst.setOpcode(ARM::RFEDB_UPD);
				1438	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1439	case ARM::LDMIA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1440	Inst.setOpcode(ARM::RFEIA);
				1441	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1442	case ARM::LDMIA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1443	Inst.setOpcode(ARM::RFEIA_UPD);
				1444	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1445	case ARM::LDMIB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1446	Inst.setOpcode(ARM::RFEIB);
				1447	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1448	case ARM::LDMIB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1449	Inst.setOpcode(ARM::RFEIB_UPD);
				1450	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1451	case ARM::STMDA:
				1452	Inst.setOpcode(ARM::SRSDA);
				1453	break;
				1454	case ARM::STMDA_UPD:
				1455	Inst.setOpcode(ARM::SRSDA_UPD);
				1456	break;
				1457	case ARM::STMDB:
				1458	Inst.setOpcode(ARM::SRSDB);
				1459	break;
				1460	case ARM::STMDB_UPD:
				1461	Inst.setOpcode(ARM::SRSDB_UPD);
				1462	break;
				1463	case ARM::STMIA:
				1464	Inst.setOpcode(ARM::SRSIA);
				1465	break;
				1466	case ARM::STMIA_UPD:
				1467	Inst.setOpcode(ARM::SRSIA_UPD);
				1468	break;
				1469	case ARM::STMIB:
				1470	Inst.setOpcode(ARM::SRSIB);
				1471	break;
				1472	case ARM::STMIB_UPD:
				1473	Inst.setOpcode(ARM::SRSIB_UPD);
				1474	break;
				1475	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1476	if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1477	}
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1478
				1479	// For stores (which become SRS's, the only operand is the mode.
				1480	if (fieldFromInstruction32(Insn, 20, 1) == 0) {
				1481	Inst.addOperand(
				1482	MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
				1483	return S;
				1484	}
				1485
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1486	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1487	}
				1488
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1489	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1490	return MCDisassembler::Fail;
				1491	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1492	return MCDisassembler::Fail; // Tied
				1493	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1494	return MCDisassembler::Fail;
				1495	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1496	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1497
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1498	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1499	}
				1500
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1501	static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1502	uint64_t Address, const void *Decoder) {
				1503	unsigned imod = fieldFromInstruction32(Insn, 18, 2);
				1504	unsigned M = fieldFromInstruction32(Insn, 17, 1);
				1505	unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
				1506	unsigned mode = fieldFromInstruction32(Insn, 0, 5);
				1507
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1508	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	1509
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1510	// imod == '01' --> UNPREDICTABLE
				1511	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1512	// return failure here. The '01' imod value is unprintable, so there's
				1513	// nothing useful we could do even if we returned UNPREDICTABLE.
				1514
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1515	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1516
				1517	if (imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1518	Inst.setOpcode(ARM::CPS3p);
				1519	Inst.addOperand(MCOperand::CreateImm(imod));
				1520	Inst.addOperand(MCOperand::CreateImm(iflags));
				1521	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1522	} else if (imod && !M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1523	Inst.setOpcode(ARM::CPS2p);
				1524	Inst.addOperand(MCOperand::CreateImm(imod));
				1525	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1526	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1527	} else if (!imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1528	Inst.setOpcode(ARM::CPS1p);
				1529	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1530	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1531	} else {
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1532	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1533	Inst.setOpcode(ARM::CPS1p);
				1534	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1535	S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1536	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1537
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1538	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1539	}
				1540
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1541	static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1542	uint64_t Address, const void *Decoder) {
				1543	unsigned imod = fieldFromInstruction32(Insn, 9, 2);
				1544	unsigned M = fieldFromInstruction32(Insn, 8, 1);
				1545	unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
				1546	unsigned mode = fieldFromInstruction32(Insn, 0, 5);
				1547
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1548	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1549
				1550	// imod == '01' --> UNPREDICTABLE
				1551	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1552	// return failure here. The '01' imod value is unprintable, so there's
				1553	// nothing useful we could do even if we returned UNPREDICTABLE.
				1554
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1555	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1556
				1557	if (imod && M) {
				1558	Inst.setOpcode(ARM::t2CPS3p);
				1559	Inst.addOperand(MCOperand::CreateImm(imod));
				1560	Inst.addOperand(MCOperand::CreateImm(iflags));
				1561	Inst.addOperand(MCOperand::CreateImm(mode));
				1562	} else if (imod && !M) {
				1563	Inst.setOpcode(ARM::t2CPS2p);
				1564	Inst.addOperand(MCOperand::CreateImm(imod));
				1565	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1566	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1567	} else if (!imod && M) {
				1568	Inst.setOpcode(ARM::t2CPS1p);
				1569	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1570	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1571	} else {
				1572	// imod == '00' && M == '0' --> UNPREDICTABLE
				1573	Inst.setOpcode(ARM::t2CPS1p);
				1574	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1575	S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1576	}
				1577
				1578	return S;
				1579	}
				1580
				1581
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1582	static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1583	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1584	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1585
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1586	unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
				1587	unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
				1588	unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
				1589	unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
				1590	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1591
				1592	if (pred == 0xF)
				1593	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1594
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1595	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1596	return MCDisassembler::Fail;
				1597	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1598	return MCDisassembler::Fail;
				1599	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1600	return MCDisassembler::Fail;
				1601	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				1602	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1603
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1604	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1605	return MCDisassembler::Fail;
Owen Anderson	1fb6673	2011-08-11 22:05:38 +0000	[diff] [blame]	1606
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1607	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1608	}
				1609
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1610	static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1611	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1612	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1613
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1614	unsigned add = fieldFromInstruction32(Val, 12, 1);
				1615	unsigned imm = fieldFromInstruction32(Val, 0, 12);
				1616	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				1617
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1618	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1619	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1620
				1621	if (!add) imm *= -1;
				1622	if (imm == 0 && !add) imm = INT32_MIN;
				1623	Inst.addOperand(MCOperand::CreateImm(imm));
				1624
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1625	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1626	}
				1627
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1628	static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1629	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1630	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1631
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1632	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				1633	unsigned U = fieldFromInstruction32(Val, 8, 1);
				1634	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				1635
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1636	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1637	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1638
				1639	if (U)
				1640	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				1641	else
				1642	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				1643
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1644	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1645	}
				1646
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1647	static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1648	uint64_t Address, const void *Decoder) {
				1649	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				1650	}
				1651
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1652	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1653	DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
				1654	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1655	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1656
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1657	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				1658	unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
				1659
				1660	if (pred == 0xF) {
				1661	Inst.setOpcode(ARM::BLXi);
				1662	imm \|= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	1663	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1664	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1665	}
				1666
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	1667	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1668	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1669	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1670
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1671	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1672	}
				1673
				1674
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1675	static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1676	uint64_t Address, const void *Decoder) {
				1677	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1678	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1679	}
				1680
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1681	static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1682	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1683	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1684
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1685	unsigned Rm = fieldFromInstruction32(Val, 0, 4);
				1686	unsigned align = fieldFromInstruction32(Val, 4, 2);
				1687
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1688	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1689	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1690	if (!align)
				1691	Inst.addOperand(MCOperand::CreateImm(0));
				1692	else
				1693	Inst.addOperand(MCOperand::CreateImm(4 << align));
				1694
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1695	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1696	}
				1697
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1698	static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1699	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1700	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1701
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1702	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				1703	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				1704	unsigned wb = fieldFromInstruction32(Insn, 16, 4);
				1705	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1706	Rn \|= fieldFromInstruction32(Insn, 4, 2) << 4;
				1707	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1708
				1709	// First output register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1710	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				1711	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1712
				1713	// Second output register
				1714	switch (Inst.getOpcode()) {
				1715	case ARM::VLD1q8:
				1716	case ARM::VLD1q16:
				1717	case ARM::VLD1q32:
				1718	case ARM::VLD1q64:
				1719	case ARM::VLD1q8_UPD:
				1720	case ARM::VLD1q16_UPD:
				1721	case ARM::VLD1q32_UPD:
				1722	case ARM::VLD1q64_UPD:
				1723	case ARM::VLD1d8T:
				1724	case ARM::VLD1d16T:
				1725	case ARM::VLD1d32T:
				1726	case ARM::VLD1d64T:
				1727	case ARM::VLD1d8T_UPD:
				1728	case ARM::VLD1d16T_UPD:
				1729	case ARM::VLD1d32T_UPD:
				1730	case ARM::VLD1d64T_UPD:
				1731	case ARM::VLD1d8Q:
				1732	case ARM::VLD1d16Q:
				1733	case ARM::VLD1d32Q:
				1734	case ARM::VLD1d64Q:
				1735	case ARM::VLD1d8Q_UPD:
				1736	case ARM::VLD1d16Q_UPD:
				1737	case ARM::VLD1d32Q_UPD:
				1738	case ARM::VLD1d64Q_UPD:
				1739	case ARM::VLD2d8:
				1740	case ARM::VLD2d16:
				1741	case ARM::VLD2d32:
				1742	case ARM::VLD2d8_UPD:
				1743	case ARM::VLD2d16_UPD:
				1744	case ARM::VLD2d32_UPD:
				1745	case ARM::VLD2q8:
				1746	case ARM::VLD2q16:
				1747	case ARM::VLD2q32:
				1748	case ARM::VLD2q8_UPD:
				1749	case ARM::VLD2q16_UPD:
				1750	case ARM::VLD2q32_UPD:
				1751	case ARM::VLD3d8:
				1752	case ARM::VLD3d16:
				1753	case ARM::VLD3d32:
				1754	case ARM::VLD3d8_UPD:
				1755	case ARM::VLD3d16_UPD:
				1756	case ARM::VLD3d32_UPD:
				1757	case ARM::VLD4d8:
				1758	case ARM::VLD4d16:
				1759	case ARM::VLD4d32:
				1760	case ARM::VLD4d8_UPD:
				1761	case ARM::VLD4d16_UPD:
				1762	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1763	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				1764	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1765	break;
				1766	case ARM::VLD2b8:
				1767	case ARM::VLD2b16:
				1768	case ARM::VLD2b32:
				1769	case ARM::VLD2b8_UPD:
				1770	case ARM::VLD2b16_UPD:
				1771	case ARM::VLD2b32_UPD:
				1772	case ARM::VLD3q8:
				1773	case ARM::VLD3q16:
				1774	case ARM::VLD3q32:
				1775	case ARM::VLD3q8_UPD:
				1776	case ARM::VLD3q16_UPD:
				1777	case ARM::VLD3q32_UPD:
				1778	case ARM::VLD4q8:
				1779	case ARM::VLD4q16:
				1780	case ARM::VLD4q32:
				1781	case ARM::VLD4q8_UPD:
				1782	case ARM::VLD4q16_UPD:
				1783	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1784	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				1785	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1786	default:
				1787	break;
				1788	}
				1789
				1790	// Third output register
				1791	switch(Inst.getOpcode()) {
				1792	case ARM::VLD1d8T:
				1793	case ARM::VLD1d16T:
				1794	case ARM::VLD1d32T:
				1795	case ARM::VLD1d64T:
				1796	case ARM::VLD1d8T_UPD:
				1797	case ARM::VLD1d16T_UPD:
				1798	case ARM::VLD1d32T_UPD:
				1799	case ARM::VLD1d64T_UPD:
				1800	case ARM::VLD1d8Q:
				1801	case ARM::VLD1d16Q:
				1802	case ARM::VLD1d32Q:
				1803	case ARM::VLD1d64Q:
				1804	case ARM::VLD1d8Q_UPD:
				1805	case ARM::VLD1d16Q_UPD:
				1806	case ARM::VLD1d32Q_UPD:
				1807	case ARM::VLD1d64Q_UPD:
				1808	case ARM::VLD2q8:
				1809	case ARM::VLD2q16:
				1810	case ARM::VLD2q32:
				1811	case ARM::VLD2q8_UPD:
				1812	case ARM::VLD2q16_UPD:
				1813	case ARM::VLD2q32_UPD:
				1814	case ARM::VLD3d8:
				1815	case ARM::VLD3d16:
				1816	case ARM::VLD3d32:
				1817	case ARM::VLD3d8_UPD:
				1818	case ARM::VLD3d16_UPD:
				1819	case ARM::VLD3d32_UPD:
				1820	case ARM::VLD4d8:
				1821	case ARM::VLD4d16:
				1822	case ARM::VLD4d32:
				1823	case ARM::VLD4d8_UPD:
				1824	case ARM::VLD4d16_UPD:
				1825	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1826	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				1827	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1828	break;
				1829	case ARM::VLD3q8:
				1830	case ARM::VLD3q16:
				1831	case ARM::VLD3q32:
				1832	case ARM::VLD3q8_UPD:
				1833	case ARM::VLD3q16_UPD:
				1834	case ARM::VLD3q32_UPD:
				1835	case ARM::VLD4q8:
				1836	case ARM::VLD4q16:
				1837	case ARM::VLD4q32:
				1838	case ARM::VLD4q8_UPD:
				1839	case ARM::VLD4q16_UPD:
				1840	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1841	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				1842	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1843	break;
				1844	default:
				1845	break;
				1846	}
				1847
				1848	// Fourth output register
				1849	switch (Inst.getOpcode()) {
				1850	case ARM::VLD1d8Q:
				1851	case ARM::VLD1d16Q:
				1852	case ARM::VLD1d32Q:
				1853	case ARM::VLD1d64Q:
				1854	case ARM::VLD1d8Q_UPD:
				1855	case ARM::VLD1d16Q_UPD:
				1856	case ARM::VLD1d32Q_UPD:
				1857	case ARM::VLD1d64Q_UPD:
				1858	case ARM::VLD2q8:
				1859	case ARM::VLD2q16:
				1860	case ARM::VLD2q32:
				1861	case ARM::VLD2q8_UPD:
				1862	case ARM::VLD2q16_UPD:
				1863	case ARM::VLD2q32_UPD:
				1864	case ARM::VLD4d8:
				1865	case ARM::VLD4d16:
				1866	case ARM::VLD4d32:
				1867	case ARM::VLD4d8_UPD:
				1868	case ARM::VLD4d16_UPD:
				1869	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1870	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				1871	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1872	break;
				1873	case ARM::VLD4q8:
				1874	case ARM::VLD4q16:
				1875	case ARM::VLD4q32:
				1876	case ARM::VLD4q8_UPD:
				1877	case ARM::VLD4q16_UPD:
				1878	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1879	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				1880	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1881	break;
				1882	default:
				1883	break;
				1884	}
				1885
				1886	// Writeback operand
				1887	switch (Inst.getOpcode()) {
				1888	case ARM::VLD1d8_UPD:
				1889	case ARM::VLD1d16_UPD:
				1890	case ARM::VLD1d32_UPD:
				1891	case ARM::VLD1d64_UPD:
				1892	case ARM::VLD1q8_UPD:
				1893	case ARM::VLD1q16_UPD:
				1894	case ARM::VLD1q32_UPD:
				1895	case ARM::VLD1q64_UPD:
				1896	case ARM::VLD1d8T_UPD:
				1897	case ARM::VLD1d16T_UPD:
				1898	case ARM::VLD1d32T_UPD:
				1899	case ARM::VLD1d64T_UPD:
				1900	case ARM::VLD1d8Q_UPD:
				1901	case ARM::VLD1d16Q_UPD:
				1902	case ARM::VLD1d32Q_UPD:
				1903	case ARM::VLD1d64Q_UPD:
				1904	case ARM::VLD2d8_UPD:
				1905	case ARM::VLD2d16_UPD:
				1906	case ARM::VLD2d32_UPD:
				1907	case ARM::VLD2q8_UPD:
				1908	case ARM::VLD2q16_UPD:
				1909	case ARM::VLD2q32_UPD:
				1910	case ARM::VLD2b8_UPD:
				1911	case ARM::VLD2b16_UPD:
				1912	case ARM::VLD2b32_UPD:
				1913	case ARM::VLD3d8_UPD:
				1914	case ARM::VLD3d16_UPD:
				1915	case ARM::VLD3d32_UPD:
				1916	case ARM::VLD3q8_UPD:
				1917	case ARM::VLD3q16_UPD:
				1918	case ARM::VLD3q32_UPD:
				1919	case ARM::VLD4d8_UPD:
				1920	case ARM::VLD4d16_UPD:
				1921	case ARM::VLD4d32_UPD:
				1922	case ARM::VLD4q8_UPD:
				1923	case ARM::VLD4q16_UPD:
				1924	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1925	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				1926	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1927	break;
				1928	default:
				1929	break;
				1930	}
				1931
				1932	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1933	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				1934	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1935
				1936	// AddrMode6 Offset (register)
				1937	if (Rm == 0xD)
				1938	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1939	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1940	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1941	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1942	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1943
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1944	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1945	}
				1946
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1947	static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1948	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1949	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1950
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1951	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				1952	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				1953	unsigned wb = fieldFromInstruction32(Insn, 16, 4);
				1954	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				1955	Rn \|= fieldFromInstruction32(Insn, 4, 2) << 4;
				1956	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				1957
				1958	// Writeback Operand
				1959	switch (Inst.getOpcode()) {
				1960	case ARM::VST1d8_UPD:
				1961	case ARM::VST1d16_UPD:
				1962	case ARM::VST1d32_UPD:
				1963	case ARM::VST1d64_UPD:
				1964	case ARM::VST1q8_UPD:
				1965	case ARM::VST1q16_UPD:
				1966	case ARM::VST1q32_UPD:
				1967	case ARM::VST1q64_UPD:
				1968	case ARM::VST1d8T_UPD:
				1969	case ARM::VST1d16T_UPD:
				1970	case ARM::VST1d32T_UPD:
				1971	case ARM::VST1d64T_UPD:
				1972	case ARM::VST1d8Q_UPD:
				1973	case ARM::VST1d16Q_UPD:
				1974	case ARM::VST1d32Q_UPD:
				1975	case ARM::VST1d64Q_UPD:
				1976	case ARM::VST2d8_UPD:
				1977	case ARM::VST2d16_UPD:
				1978	case ARM::VST2d32_UPD:
				1979	case ARM::VST2q8_UPD:
				1980	case ARM::VST2q16_UPD:
				1981	case ARM::VST2q32_UPD:
				1982	case ARM::VST2b8_UPD:
				1983	case ARM::VST2b16_UPD:
				1984	case ARM::VST2b32_UPD:
				1985	case ARM::VST3d8_UPD:
				1986	case ARM::VST3d16_UPD:
				1987	case ARM::VST3d32_UPD:
				1988	case ARM::VST3q8_UPD:
				1989	case ARM::VST3q16_UPD:
				1990	case ARM::VST3q32_UPD:
				1991	case ARM::VST4d8_UPD:
				1992	case ARM::VST4d16_UPD:
				1993	case ARM::VST4d32_UPD:
				1994	case ARM::VST4q8_UPD:
				1995	case ARM::VST4q16_UPD:
				1996	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1997	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				1998	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1999	break;
				2000	default:
				2001	break;
				2002	}
				2003
				2004	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2005	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2006	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2007
				2008	// AddrMode6 Offset (register)
				2009	if (Rm == 0xD)
				2010	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2011	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2012	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2013	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2014	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2015
				2016	// First input register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2017	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2018	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2019
				2020	// Second input register
				2021	switch (Inst.getOpcode()) {
				2022	case ARM::VST1q8:
				2023	case ARM::VST1q16:
				2024	case ARM::VST1q32:
				2025	case ARM::VST1q64:
				2026	case ARM::VST1q8_UPD:
				2027	case ARM::VST1q16_UPD:
				2028	case ARM::VST1q32_UPD:
				2029	case ARM::VST1q64_UPD:
				2030	case ARM::VST1d8T:
				2031	case ARM::VST1d16T:
				2032	case ARM::VST1d32T:
				2033	case ARM::VST1d64T:
				2034	case ARM::VST1d8T_UPD:
				2035	case ARM::VST1d16T_UPD:
				2036	case ARM::VST1d32T_UPD:
				2037	case ARM::VST1d64T_UPD:
				2038	case ARM::VST1d8Q:
				2039	case ARM::VST1d16Q:
				2040	case ARM::VST1d32Q:
				2041	case ARM::VST1d64Q:
				2042	case ARM::VST1d8Q_UPD:
				2043	case ARM::VST1d16Q_UPD:
				2044	case ARM::VST1d32Q_UPD:
				2045	case ARM::VST1d64Q_UPD:
				2046	case ARM::VST2d8:
				2047	case ARM::VST2d16:
				2048	case ARM::VST2d32:
				2049	case ARM::VST2d8_UPD:
				2050	case ARM::VST2d16_UPD:
				2051	case ARM::VST2d32_UPD:
				2052	case ARM::VST2q8:
				2053	case ARM::VST2q16:
				2054	case ARM::VST2q32:
				2055	case ARM::VST2q8_UPD:
				2056	case ARM::VST2q16_UPD:
				2057	case ARM::VST2q32_UPD:
				2058	case ARM::VST3d8:
				2059	case ARM::VST3d16:
				2060	case ARM::VST3d32:
				2061	case ARM::VST3d8_UPD:
				2062	case ARM::VST3d16_UPD:
				2063	case ARM::VST3d32_UPD:
				2064	case ARM::VST4d8:
				2065	case ARM::VST4d16:
				2066	case ARM::VST4d32:
				2067	case ARM::VST4d8_UPD:
				2068	case ARM::VST4d16_UPD:
				2069	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2070	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2071	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2072	break;
				2073	case ARM::VST2b8:
				2074	case ARM::VST2b16:
				2075	case ARM::VST2b32:
				2076	case ARM::VST2b8_UPD:
				2077	case ARM::VST2b16_UPD:
				2078	case ARM::VST2b32_UPD:
				2079	case ARM::VST3q8:
				2080	case ARM::VST3q16:
				2081	case ARM::VST3q32:
				2082	case ARM::VST3q8_UPD:
				2083	case ARM::VST3q16_UPD:
				2084	case ARM::VST3q32_UPD:
				2085	case ARM::VST4q8:
				2086	case ARM::VST4q16:
				2087	case ARM::VST4q32:
				2088	case ARM::VST4q8_UPD:
				2089	case ARM::VST4q16_UPD:
				2090	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2091	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2092	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2093	break;
				2094	default:
				2095	break;
				2096	}
				2097
				2098	// Third input register
				2099	switch (Inst.getOpcode()) {
				2100	case ARM::VST1d8T:
				2101	case ARM::VST1d16T:
				2102	case ARM::VST1d32T:
				2103	case ARM::VST1d64T:
				2104	case ARM::VST1d8T_UPD:
				2105	case ARM::VST1d16T_UPD:
				2106	case ARM::VST1d32T_UPD:
				2107	case ARM::VST1d64T_UPD:
				2108	case ARM::VST1d8Q:
				2109	case ARM::VST1d16Q:
				2110	case ARM::VST1d32Q:
				2111	case ARM::VST1d64Q:
				2112	case ARM::VST1d8Q_UPD:
				2113	case ARM::VST1d16Q_UPD:
				2114	case ARM::VST1d32Q_UPD:
				2115	case ARM::VST1d64Q_UPD:
				2116	case ARM::VST2q8:
				2117	case ARM::VST2q16:
				2118	case ARM::VST2q32:
				2119	case ARM::VST2q8_UPD:
				2120	case ARM::VST2q16_UPD:
				2121	case ARM::VST2q32_UPD:
				2122	case ARM::VST3d8:
				2123	case ARM::VST3d16:
				2124	case ARM::VST3d32:
				2125	case ARM::VST3d8_UPD:
				2126	case ARM::VST3d16_UPD:
				2127	case ARM::VST3d32_UPD:
				2128	case ARM::VST4d8:
				2129	case ARM::VST4d16:
				2130	case ARM::VST4d32:
				2131	case ARM::VST4d8_UPD:
				2132	case ARM::VST4d16_UPD:
				2133	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2134	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2135	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2136	break;
				2137	case ARM::VST3q8:
				2138	case ARM::VST3q16:
				2139	case ARM::VST3q32:
				2140	case ARM::VST3q8_UPD:
				2141	case ARM::VST3q16_UPD:
				2142	case ARM::VST3q32_UPD:
				2143	case ARM::VST4q8:
				2144	case ARM::VST4q16:
				2145	case ARM::VST4q32:
				2146	case ARM::VST4q8_UPD:
				2147	case ARM::VST4q16_UPD:
				2148	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2149	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2150	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2151	break;
				2152	default:
				2153	break;
				2154	}
				2155
				2156	// Fourth input register
				2157	switch (Inst.getOpcode()) {
				2158	case ARM::VST1d8Q:
				2159	case ARM::VST1d16Q:
				2160	case ARM::VST1d32Q:
				2161	case ARM::VST1d64Q:
				2162	case ARM::VST1d8Q_UPD:
				2163	case ARM::VST1d16Q_UPD:
				2164	case ARM::VST1d32Q_UPD:
				2165	case ARM::VST1d64Q_UPD:
				2166	case ARM::VST2q8:
				2167	case ARM::VST2q16:
				2168	case ARM::VST2q32:
				2169	case ARM::VST2q8_UPD:
				2170	case ARM::VST2q16_UPD:
				2171	case ARM::VST2q32_UPD:
				2172	case ARM::VST4d8:
				2173	case ARM::VST4d16:
				2174	case ARM::VST4d32:
				2175	case ARM::VST4d8_UPD:
				2176	case ARM::VST4d16_UPD:
				2177	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2178	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2179	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2180	break;
				2181	case ARM::VST4q8:
				2182	case ARM::VST4q16:
				2183	case ARM::VST4q32:
				2184	case ARM::VST4q8_UPD:
				2185	case ARM::VST4q16_UPD:
				2186	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2187	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2188	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2189	break;
				2190	default:
				2191	break;
				2192	}
				2193
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2194	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2195	}
				2196
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2197	static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2198	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2199	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2200
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2201	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2202	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2203	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2204	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2205	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2206	unsigned size = fieldFromInstruction32(Insn, 6, 2);
				2207	unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
				2208
				2209	align *= (1 << size);
				2210
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2211	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2212	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2213	if (regs == 2) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2214	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2215	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2216	}
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2217	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2218	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2219	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2220	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2221
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2222	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2223	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2224	Inst.addOperand(MCOperand::CreateImm(align));
				2225
				2226	if (Rm == 0xD)
				2227	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2228	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2229	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2230	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2231	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2232
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2233	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2234	}
				2235
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2236	static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2237	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2238	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2239
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2240	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2241	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2242	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2243	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2244	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2245	unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
				2246	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2247	align = 2size;
				2248
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2249	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2250	return MCDisassembler::Fail;
				2251	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2252	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2253	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2254	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2255	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2256	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2257
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2258	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2259	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2260	Inst.addOperand(MCOperand::CreateImm(align));
				2261
				2262	if (Rm == 0xD)
				2263	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2264	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2265	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2266	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2267	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2268
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2269	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2270	}
				2271
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2272	static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2273	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2274	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2275
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2276	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2277	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2278	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2279	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2280	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2281
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2282	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2283	return MCDisassembler::Fail;
				2284	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2285	return MCDisassembler::Fail;
				2286	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2287	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2288	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2289	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2290	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2291	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2292
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2293	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2294	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2295	Inst.addOperand(MCOperand::CreateImm(0));
				2296
				2297	if (Rm == 0xD)
				2298	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2299	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2300	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2301	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2302	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2303
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2304	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2305	}
				2306
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2307	static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2308	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2309	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2310
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2311	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2312	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2313	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2314	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2315	unsigned size = fieldFromInstruction32(Insn, 6, 2);
				2316	unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
				2317	unsigned align = fieldFromInstruction32(Insn, 4, 1);
				2318
				2319	if (size == 0x3) {
				2320	size = 4;
				2321	align = 16;
				2322	} else {
				2323	if (size == 2) {
				2324	size = 1 << size;
				2325	align *= 8;
				2326	} else {
				2327	size = 1 << size;
				2328	align = 4size;
				2329	}
				2330	}
				2331
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2332	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2333	return MCDisassembler::Fail;
				2334	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2335	return MCDisassembler::Fail;
				2336	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2337	return MCDisassembler::Fail;
				2338	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2339	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2340	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2341	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2342	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2343	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2344
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2345	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2346	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2347	Inst.addOperand(MCOperand::CreateImm(align));
				2348
				2349	if (Rm == 0xD)
				2350	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2351	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2352	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2353	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2354	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2355
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2356	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2357	}
				2358
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2359	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2360	DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
				2361	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2362	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2363
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2364	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2365	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2366	unsigned imm = fieldFromInstruction32(Insn, 0, 4);
				2367	imm \|= fieldFromInstruction32(Insn, 16, 3) << 4;
				2368	imm \|= fieldFromInstruction32(Insn, 24, 1) << 7;
				2369	imm \|= fieldFromInstruction32(Insn, 8, 4) << 8;
				2370	imm \|= fieldFromInstruction32(Insn, 5, 1) << 12;
				2371	unsigned Q = fieldFromInstruction32(Insn, 6, 1);
				2372
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2373	if (Q) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2374	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2375	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2376	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2377	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2378	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2379	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2380
				2381	Inst.addOperand(MCOperand::CreateImm(imm));
				2382
				2383	switch (Inst.getOpcode()) {
				2384	case ARM::VORRiv4i16:
				2385	case ARM::VORRiv2i32:
				2386	case ARM::VBICiv4i16:
				2387	case ARM::VBICiv2i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2388	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2389	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2390	break;
				2391	case ARM::VORRiv8i16:
				2392	case ARM::VORRiv4i32:
				2393	case ARM::VBICiv8i16:
				2394	case ARM::VBICiv4i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2395	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2396	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2397	break;
				2398	default:
				2399	break;
				2400	}
				2401
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2402	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2403	}
				2404
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2405	static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2406	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2407	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2408
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2409	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2410	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2411	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2412	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				2413	unsigned size = fieldFromInstruction32(Insn, 18, 2);
				2414
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2415	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2416	return MCDisassembler::Fail;
				2417	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2418	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2419	Inst.addOperand(MCOperand::CreateImm(8 << size));
				2420
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2421	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2422	}
				2423
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2424	static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2425	uint64_t Address, const void *Decoder) {
				2426	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2427	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2428	}
				2429
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2430	static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2431	uint64_t Address, const void *Decoder) {
				2432	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2433	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2434	}
				2435
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2436	static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2437	uint64_t Address, const void *Decoder) {
				2438	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2439	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2440	}
				2441
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2442	static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2443	uint64_t Address, const void *Decoder) {
				2444	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2445	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2446	}
				2447
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2448	static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2449	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2450	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2451
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2452	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2453	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				2454	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2455	Rn \|= fieldFromInstruction32(Insn, 7, 1) << 4;
				2456	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2457	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				2458	unsigned op = fieldFromInstruction32(Insn, 6, 1);
				2459	unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
				2460
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2461	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2462	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2463	if (op) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2464	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2465	return MCDisassembler::Fail; // Writeback
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2466	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2467
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2468	for (unsigned i = 0; i < length; ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2469	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
				2470	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2471	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2472
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2473	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2474	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2475
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2476	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2477	}
				2478
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2479	static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2480	uint64_t Address, const void *Decoder) {
				2481	// The immediate needs to be a fully instantiated float. However, the
				2482	// auto-generated decoder is only able to fill in some of the bits
				2483	// necessary. For instance, the 'b' bit is replicated multiple times,
				2484	// and is even present in inverted form in one bit. We do a little
				2485	// binary parsing here to fill in those missing bits, and then
				2486	// reinterpret it all as a float.
				2487	union {
				2488	uint32_t integer;
				2489	float fp;
				2490	} fp_conv;
				2491
				2492	fp_conv.integer = Val;
				2493	uint32_t b = fieldFromInstruction32(Val, 25, 1);
				2494	fp_conv.integer \|= b << 26;
				2495	fp_conv.integer \|= b << 27;
				2496	fp_conv.integer \|= b << 28;
				2497	fp_conv.integer \|= b << 29;
				2498	fp_conv.integer \|= (~b & 0x1) << 30;
				2499
				2500	Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2501	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2502	}
				2503
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2504	static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2505	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2506	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2507
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2508	unsigned dst = fieldFromInstruction16(Insn, 8, 3);
				2509	unsigned imm = fieldFromInstruction16(Insn, 0, 8);
				2510
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2511	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				2512	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2513
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2514	switch(Inst.getOpcode()) {
Owen Anderson	1af7f72	2011-08-26 19:39:26 +0000	[diff] [blame]	2515	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2516	return MCDisassembler::Fail;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2517	case ARM::tADR:
Owen Anderson	9f7e831	2011-08-26 21:47:57 +0000	[diff] [blame]	2518	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2519	case ARM::tADDrSPi:
				2520	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2521	break;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	2522	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2523
				2524	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2525	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2526	}
				2527
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2528	static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2529	uint64_t Address, const void *Decoder) {
				2530	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2531	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2532	}
				2533
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2534	static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2535	uint64_t Address, const void *Decoder) {
				2536	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2537	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2538	}
				2539
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2540	static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2541	uint64_t Address, const void *Decoder) {
				2542	Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2543	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2544	}
				2545
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2546	static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2547	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2548	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2549
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2550	unsigned Rn = fieldFromInstruction32(Val, 0, 3);
				2551	unsigned Rm = fieldFromInstruction32(Val, 3, 3);
				2552
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2553	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2554	return MCDisassembler::Fail;
				2555	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2556	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2557
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2558	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2559	}
				2560
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2561	static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2562	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2563	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2564
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2565	unsigned Rn = fieldFromInstruction32(Val, 0, 3);
				2566	unsigned imm = fieldFromInstruction32(Val, 3, 5);
				2567
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2568	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2569	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2570	Inst.addOperand(MCOperand::CreateImm(imm));
				2571
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2572	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2573	}
				2574
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2575	static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2576	uint64_t Address, const void *Decoder) {
				2577	Inst.addOperand(MCOperand::CreateImm(Val << 2));
				2578
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2579	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2580	}
				2581
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2582	static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2583	uint64_t Address, const void *Decoder) {
				2584	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b113ec5	2011-08-22 17:56:58 +0000	[diff] [blame]	2585	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2586
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2587	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2588	}
				2589
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2590	static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2591	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2592	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2593
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2594	unsigned Rn = fieldFromInstruction32(Val, 6, 4);
				2595	unsigned Rm = fieldFromInstruction32(Val, 2, 4);
				2596	unsigned imm = fieldFromInstruction32(Val, 0, 2);
				2597
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2598	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2599	return MCDisassembler::Fail;
				2600	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2601	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2602	Inst.addOperand(MCOperand::CreateImm(imm));
				2603
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2604	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2605	}
				2606
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2607	static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2608	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2609	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2610
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	2611	switch (Inst.getOpcode()) {
				2612	case ARM::t2PLDs:
				2613	case ARM::t2PLDWs:
				2614	case ARM::t2PLIs:
				2615	break;
				2616	default: {
				2617	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2618	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				2619	return MCDisassembler::Fail;
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	2620	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2621	}
				2622
				2623	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2624	if (Rn == 0xF) {
				2625	switch (Inst.getOpcode()) {
				2626	case ARM::t2LDRBs:
				2627	Inst.setOpcode(ARM::t2LDRBpci);
				2628	break;
				2629	case ARM::t2LDRHs:
				2630	Inst.setOpcode(ARM::t2LDRHpci);
				2631	break;
				2632	case ARM::t2LDRSHs:
				2633	Inst.setOpcode(ARM::t2LDRSHpci);
				2634	break;
				2635	case ARM::t2LDRSBs:
				2636	Inst.setOpcode(ARM::t2LDRSBpci);
				2637	break;
				2638	case ARM::t2PLDs:
				2639	Inst.setOpcode(ARM::t2PLDi12);
				2640	Inst.addOperand(MCOperand::CreateReg(ARM::PC));
				2641	break;
				2642	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2643	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2644	}
				2645
				2646	int imm = fieldFromInstruction32(Insn, 0, 12);
				2647	if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
				2648	Inst.addOperand(MCOperand::CreateImm(imm));
				2649
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2650	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2651	}
				2652
				2653	unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
				2654	addrmode \|= fieldFromInstruction32(Insn, 0, 4) << 2;
				2655	addrmode \|= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2656	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				2657	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2658
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2659	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2660	}
				2661
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2662	static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2663	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2664	int imm = Val & 0xFF;
				2665	if (!(Val & 0x100)) imm *= -1;
				2666	Inst.addOperand(MCOperand::CreateImm(imm << 2));
				2667
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2668	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2669	}
				2670
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2671	static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2672	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2673	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2674
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2675	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				2676	unsigned imm = fieldFromInstruction32(Val, 0, 9);
				2677
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2678	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2679	return MCDisassembler::Fail;
				2680	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				2681	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2682
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2683	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2684	}
				2685
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	2686	static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
				2687	uint64_t Address, const void *Decoder) {
				2688	DecodeStatus S = MCDisassembler::Success;
				2689
				2690	unsigned Rn = fieldFromInstruction32(Val, 8, 4);
				2691	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				2692
				2693	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2694	return MCDisassembler::Fail;
				2695
				2696	Inst.addOperand(MCOperand::CreateImm(imm));
				2697
				2698	return S;
				2699	}
				2700
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2701	static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2702	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2703	int imm = Val & 0xFF;
				2704	if (!(Val & 0x100)) imm *= -1;
				2705	Inst.addOperand(MCOperand::CreateImm(imm));
				2706
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2707	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2708	}
				2709
				2710
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2711	static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2712	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2713	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2714
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2715	unsigned Rn = fieldFromInstruction32(Val, 9, 4);
				2716	unsigned imm = fieldFromInstruction32(Val, 0, 9);
				2717
				2718	// Some instructions always use an additive offset.
				2719	switch (Inst.getOpcode()) {
				2720	case ARM::t2LDRT:
				2721	case ARM::t2LDRBT:
				2722	case ARM::t2LDRHT:
				2723	case ARM::t2LDRSBT:
				2724	case ARM::t2LDRSHT:
				2725	imm \|= 0x100;
				2726	break;
				2727	default:
				2728	break;
				2729	}
				2730
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2731	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2732	return MCDisassembler::Fail;
				2733	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				2734	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2735
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2736	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2737	}
				2738
				2739
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2740	static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2741	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2742	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2743
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2744	unsigned Rn = fieldFromInstruction32(Val, 13, 4);
				2745	unsigned imm = fieldFromInstruction32(Val, 0, 12);
				2746
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2747	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2748	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2749	Inst.addOperand(MCOperand::CreateImm(imm));
				2750
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2751	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2752	}
				2753
				2754
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2755	static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2756	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2757	unsigned imm = fieldFromInstruction16(Insn, 0, 7);
				2758
				2759	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2760	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2761	Inst.addOperand(MCOperand::CreateImm(imm));
				2762
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2763	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2764	}
				2765
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2766	static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2767	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2768	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2769
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2770	if (Inst.getOpcode() == ARM::tADDrSP) {
				2771	unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
				2772	Rdm \|= fieldFromInstruction16(Insn, 7, 1) << 3;
				2773
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2774	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				2775	return MCDisassembler::Fail;
				2776	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				2777	return MCDisassembler::Fail;
Owen Anderson	9990683	2011-08-25 18:30:18 +0000	[diff] [blame]	2778	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2779	} else if (Inst.getOpcode() == ARM::tADDspr) {
				2780	unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
				2781
				2782	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				2783	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2784	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2785	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2786	}
				2787
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2788	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2789	}
				2790
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2791	static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2792	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2793	unsigned imod = fieldFromInstruction16(Insn, 4, 1) \| 0x2;
				2794	unsigned flags = fieldFromInstruction16(Insn, 0, 3);
				2795
				2796	Inst.addOperand(MCOperand::CreateImm(imod));
				2797	Inst.addOperand(MCOperand::CreateImm(flags));
				2798
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2799	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2800	}
				2801
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2802	static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2803	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2804	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2805	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				2806	unsigned add = fieldFromInstruction32(Insn, 4, 1);
				2807
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2808	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2809	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2810	Inst.addOperand(MCOperand::CreateImm(add));
				2811
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2812	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2813	}
				2814
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2815	static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2816	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2817	Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2818	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2819	}
				2820
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2821	static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2822	uint64_t Address, const void *Decoder) {
				2823	if (Val == 0xA \|\| Val == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2824	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2825
				2826	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2827	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2828	}
				2829
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2830	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2831	DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
				2832	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2833	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2834
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2835	unsigned pred = fieldFromInstruction32(Insn, 22, 4);
				2836	if (pred == 0xE \|\| pred == 0xF) {
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2837	unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2838	switch (opc) {
				2839	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2840	return MCDisassembler::Fail;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2841	case 0xf3bf8f4:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2842	Inst.setOpcode(ARM::t2DSB);
				2843	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2844	case 0xf3bf8f5:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2845	Inst.setOpcode(ARM::t2DMB);
				2846	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	2847	case 0xf3bf8f6:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2848	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	6de3c6f	2011-09-07 17:55:19 +0000	[diff] [blame]	2849	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2850	}
				2851
				2852	unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2853	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2854	}
				2855
				2856	unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
				2857	brtarget \|= fieldFromInstruction32(Insn, 11, 1) << 19;
				2858	brtarget \|= fieldFromInstruction32(Insn, 13, 1) << 18;
				2859	brtarget \|= fieldFromInstruction32(Insn, 16, 6) << 12;
				2860	brtarget \|= fieldFromInstruction32(Insn, 26, 1) << 20;
				2861
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2862	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				2863	return MCDisassembler::Fail;
				2864	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2865	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2866
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2867	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2868	}
				2869
				2870	// Decode a shifted immediate operand. These basically consist
				2871	// of an 8-bit value, and a 4-bit directive that specifies either
				2872	// a splat operation or a rotation.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2873	static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2874	uint64_t Address, const void *Decoder) {
				2875	unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
				2876	if (ctrl == 0) {
				2877	unsigned byte = fieldFromInstruction32(Val, 8, 2);
				2878	unsigned imm = fieldFromInstruction32(Val, 0, 8);
				2879	switch (byte) {
				2880	case 0:
				2881	Inst.addOperand(MCOperand::CreateImm(imm));
				2882	break;
				2883	case 1:
				2884	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				2885	break;
				2886	case 2:
				2887	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				2888	break;
				2889	case 3:
				2890	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				2891	(imm << 8) \| imm));
				2892	break;
				2893	}
				2894	} else {
				2895	unsigned unrot = fieldFromInstruction32(Val, 0, 7) \| 0x80;
				2896	unsigned rot = fieldFromInstruction32(Val, 7, 5);
				2897	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				2898	Inst.addOperand(MCOperand::CreateImm(imm));
				2899	}
				2900
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2901	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2902	}
				2903
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2904	static DecodeStatus
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2905	DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
				2906	uint64_t Address, const void *Decoder){
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2907	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2908	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2909	}
				2910
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2911	static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	2912	uint64_t Address, const void *Decoder){
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2913	Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2914	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2915	}
				2916
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2917	static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2918	uint64_t Address, const void *Decoder) {
				2919	switch (Val) {
				2920	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2921	return MCDisassembler::Fail;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2922	case 0xF: // SY
				2923	case 0xE: // ST
				2924	case 0xB: // ISH
				2925	case 0xA: // ISHST
				2926	case 0x7: // NSH
				2927	case 0x6: // NSHST
				2928	case 0x3: // OSH
				2929	case 0x2: // OSHST
				2930	break;
				2931	}
				2932
				2933	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2934	return MCDisassembler::Success;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	2935	}
				2936
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2937	static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	2938	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2939	if (!Val) return MCDisassembler::Fail;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	2940	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2941	return MCDisassembler::Success;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	2942	}
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	2943
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2944	static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2945	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2946	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2947
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	2948	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				2949	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2950	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				2951
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2952	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	2953
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2954	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				2955	return MCDisassembler::Fail;
				2956	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				2957	return MCDisassembler::Fail;
				2958	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2959	return MCDisassembler::Fail;
				2960	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2961	return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	2962
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2963	return S;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	2964	}
				2965
				2966
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2967	static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2968	uint64_t Address, const void *Decoder){
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2969	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2970
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	2971	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				2972	unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
				2973	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Anderson	adf2b09	2011-08-11 22:08:38 +0000	[diff] [blame]	2974	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	2975
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2976	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2977	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	2978
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2979	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
				2980	if (Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1) return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	2981
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2982	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				2983	return MCDisassembler::Fail;
				2984	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				2985	return MCDisassembler::Fail;
				2986	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2987	return MCDisassembler::Fail;
				2988	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2989	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	2990
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2991	return S;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	2992	}
				2993
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2994	static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	2995	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2996	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	2997
				2998	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				2999	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3000	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3001	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3002	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3003	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3004
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3005	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3006
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3007	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3008	return MCDisassembler::Fail;
				3009	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3010	return MCDisassembler::Fail;
				3011	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3012	return MCDisassembler::Fail;
				3013	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3014	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3015
				3016	return S;
				3017	}
				3018
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3019	static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3020	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3021	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3022
				3023	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3024	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3025	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3026	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3027	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3028	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3029	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3030
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3031	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				3032	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3033
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3034	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3035	return MCDisassembler::Fail;
				3036	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3037	return MCDisassembler::Fail;
				3038	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3039	return MCDisassembler::Fail;
				3040	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3041	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3042
				3043	return S;
				3044	}
				3045
				3046
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3047	static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3048	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3049	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3050
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3051	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3052	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3053	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3054	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3055	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3056	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3057
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3058	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3059
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3060	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3061	return MCDisassembler::Fail;
				3062	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3063	return MCDisassembler::Fail;
				3064	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3065	return MCDisassembler::Fail;
				3066	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3067	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3068
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3069	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3070	}
				3071
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3072	static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3073	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3074	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3075
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3076	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3077	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3078	unsigned imm = fieldFromInstruction32(Insn, 0, 12);
				3079	imm \|= fieldFromInstruction32(Insn, 16, 4) << 13;
				3080	imm \|= fieldFromInstruction32(Insn, 23, 1) << 12;
				3081	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3082
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3083	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3084
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3085	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3086	return MCDisassembler::Fail;
				3087	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3088	return MCDisassembler::Fail;
				3089	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3090	return MCDisassembler::Fail;
				3091	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3092	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3093
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3094	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3095	}
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3096
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3097	static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3098	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3099	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3100
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3101	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3102	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3103	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3104	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3105	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3106
				3107	unsigned align = 0;
				3108	unsigned index = 0;
				3109	switch (size) {
				3110	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3111	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3112	case 0:
				3113	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3114	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3115	index = fieldFromInstruction32(Insn, 5, 3);
				3116	break;
				3117	case 1:
				3118	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3119	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3120	index = fieldFromInstruction32(Insn, 6, 2);
				3121	if (fieldFromInstruction32(Insn, 4, 1))
				3122	align = 2;
				3123	break;
				3124	case 2:
				3125	if (fieldFromInstruction32(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3126	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3127	index = fieldFromInstruction32(Insn, 7, 1);
				3128	if (fieldFromInstruction32(Insn, 4, 2) != 0)
				3129	align = 4;
				3130	}
				3131
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3132	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3133	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3134	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3135	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3136	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3137	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3138	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3139	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3140	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3141	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3142	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3143	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3144	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3145	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3146	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3147	}
				3148
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3149	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3150	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3151	Inst.addOperand(MCOperand::CreateImm(index));
				3152
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3153	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3154	}
				3155
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3156	static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3157	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3158	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3159
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3160	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3161	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3162	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3163	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3164	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3165
				3166	unsigned align = 0;
				3167	unsigned index = 0;
				3168	switch (size) {
				3169	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3170	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3171	case 0:
				3172	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3173	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3174	index = fieldFromInstruction32(Insn, 5, 3);
				3175	break;
				3176	case 1:
				3177	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3178	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3179	index = fieldFromInstruction32(Insn, 6, 2);
				3180	if (fieldFromInstruction32(Insn, 4, 1))
				3181	align = 2;
				3182	break;
				3183	case 2:
				3184	if (fieldFromInstruction32(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3185	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3186	index = fieldFromInstruction32(Insn, 7, 1);
				3187	if (fieldFromInstruction32(Insn, 4, 2) != 0)
				3188	align = 4;
				3189	}
				3190
				3191	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3192	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3193	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3194	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3195	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3196	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3197	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3198	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3199	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3200	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3201	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3202	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3203	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3204	}
				3205
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3206	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3207	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3208	Inst.addOperand(MCOperand::CreateImm(index));
				3209
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3210	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3211	}
				3212
				3213
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3214	static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3215	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3216	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3217
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3218	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3219	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3220	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3221	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3222	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3223
				3224	unsigned align = 0;
				3225	unsigned index = 0;
				3226	unsigned inc = 1;
				3227	switch (size) {
				3228	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3229	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3230	case 0:
				3231	index = fieldFromInstruction32(Insn, 5, 3);
				3232	if (fieldFromInstruction32(Insn, 4, 1))
				3233	align = 2;
				3234	break;
				3235	case 1:
				3236	index = fieldFromInstruction32(Insn, 6, 2);
				3237	if (fieldFromInstruction32(Insn, 4, 1))
				3238	align = 4;
				3239	if (fieldFromInstruction32(Insn, 5, 1))
				3240	inc = 2;
				3241	break;
				3242	case 2:
				3243	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3244	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3245	index = fieldFromInstruction32(Insn, 7, 1);
				3246	if (fieldFromInstruction32(Insn, 4, 1) != 0)
				3247	align = 8;
				3248	if (fieldFromInstruction32(Insn, 6, 1))
				3249	inc = 2;
				3250	break;
				3251	}
				3252
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3253	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3254	return MCDisassembler::Fail;
				3255	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3256	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3257	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3258	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3259	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3260	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3261	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3262	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3263	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3264	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3265	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3266	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3267	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3268	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3269	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3270	}
				3271
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3272	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3273	return MCDisassembler::Fail;
				3274	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3275	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3276	Inst.addOperand(MCOperand::CreateImm(index));
				3277
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3278	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3279	}
				3280
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3281	static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3282	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3283	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3284
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3285	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3286	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3287	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3288	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3289	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3290
				3291	unsigned align = 0;
				3292	unsigned index = 0;
				3293	unsigned inc = 1;
				3294	switch (size) {
				3295	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3296	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3297	case 0:
				3298	index = fieldFromInstruction32(Insn, 5, 3);
				3299	if (fieldFromInstruction32(Insn, 4, 1))
				3300	align = 2;
				3301	break;
				3302	case 1:
				3303	index = fieldFromInstruction32(Insn, 6, 2);
				3304	if (fieldFromInstruction32(Insn, 4, 1))
				3305	align = 4;
				3306	if (fieldFromInstruction32(Insn, 5, 1))
				3307	inc = 2;
				3308	break;
				3309	case 2:
				3310	if (fieldFromInstruction32(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3311	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3312	index = fieldFromInstruction32(Insn, 7, 1);
				3313	if (fieldFromInstruction32(Insn, 4, 1) != 0)
				3314	align = 8;
				3315	if (fieldFromInstruction32(Insn, 6, 1))
				3316	inc = 2;
				3317	break;
				3318	}
				3319
				3320	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3321	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3322	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3323	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3324	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3325	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3326	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3327	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3328	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3329	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3330	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3331	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3332	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3333	}
				3334
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3335	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3336	return MCDisassembler::Fail;
				3337	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3338	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3339	Inst.addOperand(MCOperand::CreateImm(index));
				3340
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3341	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3342	}
				3343
				3344
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3345	static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3346	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3347	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3348
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3349	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3350	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3351	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3352	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3353	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3354
				3355	unsigned align = 0;
				3356	unsigned index = 0;
				3357	unsigned inc = 1;
				3358	switch (size) {
				3359	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3360	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3361	case 0:
				3362	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3363	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3364	index = fieldFromInstruction32(Insn, 5, 3);
				3365	break;
				3366	case 1:
				3367	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3368	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3369	index = fieldFromInstruction32(Insn, 6, 2);
				3370	if (fieldFromInstruction32(Insn, 5, 1))
				3371	inc = 2;
				3372	break;
				3373	case 2:
				3374	if (fieldFromInstruction32(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3375	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3376	index = fieldFromInstruction32(Insn, 7, 1);
				3377	if (fieldFromInstruction32(Insn, 6, 1))
				3378	inc = 2;
				3379	break;
				3380	}
				3381
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3382	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3383	return MCDisassembler::Fail;
				3384	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3385	return MCDisassembler::Fail;
				3386	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3387	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3388
				3389	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3390	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3391	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3392	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3393	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3394	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3395	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3396	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3397	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3398	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3399	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3400	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3401	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3402	}
				3403
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3404	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3405	return MCDisassembler::Fail;
				3406	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3407	return MCDisassembler::Fail;
				3408	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3409	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3410	Inst.addOperand(MCOperand::CreateImm(index));
				3411
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3412	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3413	}
				3414
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3415	static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3416	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3417	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3418
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3419	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3420	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3421	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3422	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3423	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3424
				3425	unsigned align = 0;
				3426	unsigned index = 0;
				3427	unsigned inc = 1;
				3428	switch (size) {
				3429	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3430	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3431	case 0:
				3432	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3433	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3434	index = fieldFromInstruction32(Insn, 5, 3);
				3435	break;
				3436	case 1:
				3437	if (fieldFromInstruction32(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3438	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3439	index = fieldFromInstruction32(Insn, 6, 2);
				3440	if (fieldFromInstruction32(Insn, 5, 1))
				3441	inc = 2;
				3442	break;
				3443	case 2:
				3444	if (fieldFromInstruction32(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3445	return MCDisassembler::Fail; // UNDEFINED
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3446	index = fieldFromInstruction32(Insn, 7, 1);
				3447	if (fieldFromInstruction32(Insn, 6, 1))
				3448	inc = 2;
				3449	break;
				3450	}
				3451
				3452	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3453	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3454	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3455	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3456	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3457	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3458	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3459	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3460	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3461	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3462	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3463	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3464	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3465	}
				3466
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3467	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3468	return MCDisassembler::Fail;
				3469	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3470	return MCDisassembler::Fail;
				3471	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3472	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3473	Inst.addOperand(MCOperand::CreateImm(index));
				3474
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3475	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3476	}
				3477
				3478
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3479	static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3480	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3481	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3482
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3483	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3484	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3485	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3486	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3487	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3488
				3489	unsigned align = 0;
				3490	unsigned index = 0;
				3491	unsigned inc = 1;
				3492	switch (size) {
				3493	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3494	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3495	case 0:
				3496	if (fieldFromInstruction32(Insn, 4, 1))
				3497	align = 4;
				3498	index = fieldFromInstruction32(Insn, 5, 3);
				3499	break;
				3500	case 1:
				3501	if (fieldFromInstruction32(Insn, 4, 1))
				3502	align = 8;
				3503	index = fieldFromInstruction32(Insn, 6, 2);
				3504	if (fieldFromInstruction32(Insn, 5, 1))
				3505	inc = 2;
				3506	break;
				3507	case 2:
				3508	if (fieldFromInstruction32(Insn, 4, 2))
				3509	align = 4 << fieldFromInstruction32(Insn, 4, 2);
				3510	index = fieldFromInstruction32(Insn, 7, 1);
				3511	if (fieldFromInstruction32(Insn, 6, 1))
				3512	inc = 2;
				3513	break;
				3514	}
				3515
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3516	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3517	return MCDisassembler::Fail;
				3518	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3519	return MCDisassembler::Fail;
				3520	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3521	return MCDisassembler::Fail;
				3522	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3523	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3524
				3525	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3526	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3527	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3528	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3529	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3530	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3531	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3532	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3533	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3534	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3535	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3536	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3537	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3538	}
				3539
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3540	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3541	return MCDisassembler::Fail;
				3542	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3543	return MCDisassembler::Fail;
				3544	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3545	return MCDisassembler::Fail;
				3546	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3547	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3548	Inst.addOperand(MCOperand::CreateImm(index));
				3549
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3550	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3551	}
				3552
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3553	static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3554	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3555	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3556
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3557	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3558	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3559	unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
				3560	Rd \|= fieldFromInstruction32(Insn, 22, 1) << 4;
				3561	unsigned size = fieldFromInstruction32(Insn, 10, 2);
				3562
				3563	unsigned align = 0;
				3564	unsigned index = 0;
				3565	unsigned inc = 1;
				3566	switch (size) {
				3567	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3568	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3569	case 0:
				3570	if (fieldFromInstruction32(Insn, 4, 1))
				3571	align = 4;
				3572	index = fieldFromInstruction32(Insn, 5, 3);
				3573	break;
				3574	case 1:
				3575	if (fieldFromInstruction32(Insn, 4, 1))
				3576	align = 8;
				3577	index = fieldFromInstruction32(Insn, 6, 2);
				3578	if (fieldFromInstruction32(Insn, 5, 1))
				3579	inc = 2;
				3580	break;
				3581	case 2:
				3582	if (fieldFromInstruction32(Insn, 4, 2))
				3583	align = 4 << fieldFromInstruction32(Insn, 4, 2);
				3584	index = fieldFromInstruction32(Insn, 7, 1);
				3585	if (fieldFromInstruction32(Insn, 6, 1))
				3586	inc = 2;
				3587	break;
				3588	}
				3589
				3590	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3591	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3592	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3593	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3594	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3595	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3596	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3597	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3598	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3599	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3600	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3601	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3602	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3603	}
				3604
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3605	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3606	return MCDisassembler::Fail;
				3607	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3608	return MCDisassembler::Fail;
				3609	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3610	return MCDisassembler::Fail;
				3611	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				3612	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3613	Inst.addOperand(MCOperand::CreateImm(index));
				3614
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3615	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3616	}
				3617
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3618	static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3619	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3620	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3621	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3622	unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
				3623	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3624	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3625	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				3626
				3627	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3628	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3629
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3630	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				3631	return MCDisassembler::Fail;
				3632	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				3633	return MCDisassembler::Fail;
				3634	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				3635	return MCDisassembler::Fail;
				3636	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				3637	return MCDisassembler::Fail;
				3638	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3639	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3640
				3641	return S;
				3642	}
				3643
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3644	static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3645	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3646	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3647	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3648	unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
				3649	unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
				3650	unsigned pred = fieldFromInstruction32(Insn, 28, 4);
				3651	Rm \|= fieldFromInstruction32(Insn, 5, 1) << 4;
				3652
				3653	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3654	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3655
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3656	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				3657	return MCDisassembler::Fail;
				3658	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				3659	return MCDisassembler::Fail;
				3660	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				3661	return MCDisassembler::Fail;
				3662	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				3663	return MCDisassembler::Fail;
				3664	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3665	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	3666
				3667	return S;
				3668	}
Owen Anderson	8e1e60b	2011-08-22 23:44:04 +0000	[diff] [blame]	3669
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3670	static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3671	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3672	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3673	unsigned pred = fieldFromInstruction16(Insn, 4, 4);
				3674	// The InstPrinter needs to have the low bit of the predicate in
				3675	// the mask operand to be able to print it properly.
				3676	unsigned mask = fieldFromInstruction16(Insn, 0, 5);
				3677
				3678	if (pred == 0xF) {
				3679	pred = 0xE;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3680	S = MCDisassembler::SoftFail;
Owen Anderson	e234d02	2011-08-24 17:21:43 +0000	[diff] [blame]	3681	}
				3682
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3683	if ((mask & 0xF) == 0) {
				3684	// Preserve the high bit of the mask, which is the low bit of
				3685	// the predicate.
				3686	mask &= 0x10;
				3687	mask \|= 0x8;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3688	S = MCDisassembler::SoftFail;
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	3689	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	3690
				3691	Inst.addOperand(MCOperand::CreateImm(pred));
				3692	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	3693	return S;
				3694	}
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	3695
				3696	static DecodeStatus
				3697	DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
				3698	uint64_t Address, const void *Decoder) {
				3699	DecodeStatus S = MCDisassembler::Success;
				3700
				3701	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3702	unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
				3703	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3704	unsigned addr = fieldFromInstruction32(Insn, 0, 8);
				3705	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				3706	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				3707	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				3708	bool writeback = (W == 1) \| (P == 0);
				3709
				3710	addr \|= (U << 8) \| (Rn << 9);
				3711
				3712	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				3713	Check(S, MCDisassembler::SoftFail);
				3714	if (Rt == Rt2)
				3715	Check(S, MCDisassembler::SoftFail);
				3716
				3717	// Rt
				3718	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3719	return MCDisassembler::Fail;
				3720	// Rt2
				3721	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				3722	return MCDisassembler::Fail;
				3723	// Writeback operand
				3724	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3725	return MCDisassembler::Fail;
				3726	// addr
				3727	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				3728	return MCDisassembler::Fail;
				3729
				3730	return S;
				3731	}
				3732
				3733	static DecodeStatus
				3734	DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
				3735	uint64_t Address, const void *Decoder) {
				3736	DecodeStatus S = MCDisassembler::Success;
				3737
				3738	unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
				3739	unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
				3740	unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
				3741	unsigned addr = fieldFromInstruction32(Insn, 0, 8);
				3742	unsigned W = fieldFromInstruction32(Insn, 21, 1);
				3743	unsigned U = fieldFromInstruction32(Insn, 23, 1);
				3744	unsigned P = fieldFromInstruction32(Insn, 24, 1);
				3745	bool writeback = (W == 1) \| (P == 0);
				3746
				3747	addr \|= (U << 8) \| (Rn << 9);
				3748
				3749	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				3750	Check(S, MCDisassembler::SoftFail);
				3751
				3752	// Writeback operand
				3753	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3754	return MCDisassembler::Fail;
				3755	// Rt
				3756	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3757	return MCDisassembler::Fail;
				3758	// Rt2
				3759	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				3760	return MCDisassembler::Fail;
				3761	// addr
				3762	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				3763	return MCDisassembler::Fail;
				3764
				3765	return S;
				3766	}
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	3767
				3768	static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
				3769	uint64_t Address, const void *Decoder) {
				3770	unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
				3771	unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
				3772	if (sign1 != sign2) return MCDisassembler::Fail;
				3773
				3774	unsigned Val = fieldFromInstruction32(Insn, 0, 8);
				3775	Val \|= fieldFromInstruction32(Insn, 12, 3) << 8;
				3776	Val \|= fieldFromInstruction32(Insn, 26, 1) << 11;
				3777	Val \|= sign1 << 12;
				3778	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				3779
				3780	return MCDisassembler::Success;
				3781	}
				3782