Blame - lib/Target/ARM/Disassembler/ARMDisassembler.cpp - platform/external/llvm

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Jia Liu	31d157a	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	12	#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	14	#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	15	#include "llvm/MC/EDInstInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	16	#include "llvm/MC/MCInst.h"
Benjamin Kramer	eea66f6	2011-11-11 12:39:41 +0000	[diff] [blame]	17	#include "llvm/MC/MCInstrDesc.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	18	#include "llvm/MC/MCExpr.h"
				19	#include "llvm/MC/MCContext.h"
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	20	#include "llvm/MC/MCDisassembler.h"
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	21	#include "llvm/MC/MCFixedLenDisassembler.h"
Dylan Noblesmith	75e3b7f	2012-04-03 15:48:14 +0000	[diff] [blame]	22	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	23	#include "llvm/Support/Debug.h"
				24	#include "llvm/Support/MemoryObject.h"
				25	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	26	#include "llvm/Support/LEB128.h"
Evan Cheng	3e74d6f	2011-08-24 18:08:43 +0000	[diff] [blame]	27	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	28	#include "llvm/Support/raw_ostream.h"
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	29	#include <vector>
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	30
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	31	using namespace llvm;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	32
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	33	typedef MCDisassembler::DecodeStatus DecodeStatus;
				34
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	35	namespace {
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	36	// Handles the condition code status of instructions in IT blocks
				37	class ITStatus
				38	{
				39	public:
				40	// Returns the condition code for instruction in IT block
				41	unsigned getITCC() {
				42	unsigned CC = ARMCC::AL;
				43	if (instrInITBlock())
				44	CC = ITStates.back();
				45	return CC;
				46	}
				47
				48	// Advances the IT block state to the next T or E
				49	void advanceITState() {
				50	ITStates.pop_back();
				51	}
				52
				53	// Returns true if the current instruction is in an IT block
				54	bool instrInITBlock() {
				55	return !ITStates.empty();
				56	}
				57
				58	// Returns true if current instruction is the last instruction in an IT block
				59	bool instrLastInITBlock() {
				60	return ITStates.size() == 1;
				61	}
				62
				63	// Called when decoding an IT instruction. Sets the IT state for the following
				64	// instructions that for the IT block. Firstcond and Mask correspond to the
				65	// fields in the IT instruction encoding.
				66	void setITState(char Firstcond, char Mask) {
				67	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	4d2f077	2012-04-27 08:42:59 +0000	[diff] [blame]	68	unsigned CondBit0 = Firstcond & 1;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	69	unsigned NumTZ = CountTrailingZeros_32(Mask);
				70	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				71	assert(NumTZ <= 3 && "Invalid IT mask!");
				72	// push condition codes onto the stack the correct order for the pops
				73	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				74	bool T = ((Mask >> Pos) & 1) == CondBit0;
				75	if (T)
				76	ITStates.push_back(CCBits);
				77	else
				78	ITStates.push_back(CCBits ^ 1);
				79	}
				80	ITStates.push_back(CCBits);
				81	}
				82
				83	private:
				84	std::vector<unsigned char> ITStates;
				85	};
				86	}
				87
				88	namespace {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	89	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				90	class ARMDisassembler : public MCDisassembler {
				91	public:
				92	/// Constructor - Initializes the disassembler.
				93	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	94	ARMDisassembler(const MCSubtargetInfo &STI) :
				95	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	96	}
				97
				98	~ARMDisassembler() {
				99	}
				100
				101	/// getInstruction - See MCDisassembler.
				102	DecodeStatus getInstruction(MCInst &instr,
				103	uint64_t &size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	104	const MemoryObject &region,
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	105	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	106	raw_ostream &vStream,
				107	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	108
				109	/// getEDInfo - See MCDisassembler.
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	110	const EDInstInfo *getEDInfo() const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	111	private:
				112	};
				113
				114	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				115	class ThumbDisassembler : public MCDisassembler {
				116	public:
				117	/// Constructor - Initializes the disassembler.
				118	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	119	ThumbDisassembler(const MCSubtargetInfo &STI) :
				120	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	121	}
				122
				123	~ThumbDisassembler() {
				124	}
				125
				126	/// getInstruction - See MCDisassembler.
				127	DecodeStatus getInstruction(MCInst &instr,
				128	uint64_t &size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	129	const MemoryObject &region,
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	130	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	131	raw_ostream &vStream,
				132	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	133
				134	/// getEDInfo - See MCDisassembler.
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	135	const EDInstInfo *getEDInfo() const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	136	private:
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	137	mutable ITStatus ITBlock;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	138	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	139	void UpdateThumbVFPPredicate(MCInst&) const;
				140	};
				141	}
				142
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	143	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	144	switch (In) {
				145	case MCDisassembler::Success:
				146	// Out stays the same.
				147	return true;
				148	case MCDisassembler::SoftFail:
				149	Out = In;
				150	return true;
				151	case MCDisassembler::Fail:
				152	Out = In;
				153	return false;
				154	}
David Blaikie	4d6ccb5	2012-01-20 21:51:11 +0000	[diff] [blame]	155	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	156	}
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	157
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	158
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	159	// Forward declare these because the autogenerated code will reference them.
				160	// Definitions are further down.
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	161	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	162	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	163	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	164	unsigned RegNo, uint64_t Address,
				165	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	168	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	169	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	173	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	174	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	175	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	176	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	177	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	178	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	179	unsigned RegNo,
				180	uint64_t Address,
				181	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	182	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	183	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	184	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	185	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	187	unsigned RegNo, uint64_t Address,
				188	const void *Decoder);
Johnny Chen	270159f	2010-08-12 01:40:54 +0000	[diff] [blame]	189
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	200	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	201	uint64_t Address, const void *Decoder);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	202
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	205	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	206	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	208	unsigned Insn,
				209	uint64_t Address,
				210	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	215	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	217	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	218	uint64_t Address, const void *Decoder);
				219
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	220	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	221	unsigned Insn,
				222	uint64_t Adddress,
				223	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	234	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	235	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	236	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	237	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	238	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	239	uint64_t Address, const void *Decoder);
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	240	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				241	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	242	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	243	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	244	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	245	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	246	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	247	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	248	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	249	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	250	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	251	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	280	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	282	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	284	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	285	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
				318
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	319
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	322	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	323	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	324	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	325	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	326	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	327	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	328	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	329	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	349	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	350	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	351	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	352	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	353	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	354	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	355	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	356	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	357	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	374	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	375	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	0afa009	2011-09-26 21:06:22 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
				382
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	383	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	384	uint64_t Address, const void *Decoder);
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	385	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				386	uint64_t Address, const void *Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	387	#include "ARMGenDisassemblerTables.inc"
Oscar Fuentes	38e1390	2010-09-28 11:48:19 +0000	[diff] [blame]	388	#include "ARMGenEDInfo.inc"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	389
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	390	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				391	return new ARMDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	392	}
				393
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	394	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				395	return new ThumbDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	396	}
				397
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	398	const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	399	return instInfoARM;
				400	}
				401
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	402	const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	403	return instInfoARM;
				404	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	405
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	406	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	407	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	408	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	409	raw_ostream &os,
				410	raw_ostream &cs) const {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	411	CommentStream = &cs;
				412
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	413	uint8_t bytes[4];
				414
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	415	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				416	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				417
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	418	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	419	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				420	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	421	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	422	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	423
				424	// Encoded as a small-endian 32-bit word in the stream.
				425	uint32_t insn = (bytes[3] << 24) \|
				426	(bytes[2] << 16) \|
				427	(bytes[1] << 8) \|
				428	(bytes[0] << 0);
				429
				430	// Calling the auto-generated decoder function.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	431	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				432	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	433	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	434	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	435	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	436	}
				437
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	438	// VFP and NEON instructions, similarly, are shared between ARM
				439	// and Thumb modes.
				440	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	441	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	442	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	443	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	444	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	445	}
				446
				447	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	448	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				449	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	450	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	451	Size = 4;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	452	// Add a fake predicate operand, because we share these instruction
				453	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	454	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				455	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	456	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	457	}
				458
				459	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	460	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				461	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	462	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	463	Size = 4;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	464	// Add a fake predicate operand, because we share these instruction
				465	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	466	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				467	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	468	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	469	}
				470
				471	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	472	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				473	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	474	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	475	Size = 4;
				476	// Add a fake predicate operand, because we share these instruction
				477	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	478	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				479	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	480	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	481	}
				482
				483	MI.clear();
				484
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	485	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	486	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	487	}
				488
				489	namespace llvm {
Benjamin Kramer	1a2f988	2011-10-22 16:50:00 +0000	[diff] [blame]	490	extern const MCInstrDesc ARMInsts[];
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	491	}
				492
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	493	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				494	/// immediate Value in the MCInst. The immediate Value has had any PC
				495	/// adjustment made by the caller. If the instruction is a branch instruction
				496	/// then isBranch is true, else false. If the getOpInfo() function was set as
				497	/// part of the setupForSymbolicDisassembly() call then that function is called
				498	/// to get any symbolic information at the Address for this instruction. If
				499	/// that returns non-zero then the symbolic information it returns is used to
				500	/// create an MCExpr and that is added as an operand to the MCInst. If
				501	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				502	/// Value is done and if a symbol is found an MCExpr is created with that, else
				503	/// an MCExpr with Value is created. This function returns true if it adds an
				504	/// operand to the MCInst and false otherwise.
				505	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				506	bool isBranch, uint64_t InstSize,
				507	MCInst &MI, const void *Decoder) {
				508	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				509	LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	510	struct LLVMOpInfo1 SymbolicOp;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	511	memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	512	SymbolicOp.Value = Value;
				513	void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	514
				515	if (!getOpInfo \|\|
				516	!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
				517	// Clear SymbolicOp.Value from above and also all other fields.
				518	memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
				519	LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
				520	if (!SymbolLookUp)
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	521	return false;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	522	uint64_t ReferenceType;
				523	if (isBranch)
				524	ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
				525	else
				526	ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
				527	const char *ReferenceName;
				528	const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
				529	&ReferenceName);
				530	if (Name) {
				531	SymbolicOp.AddSymbol.Name = Name;
				532	SymbolicOp.AddSymbol.Present = true;
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	533	}
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	534	// For branches always create an MCExpr so it gets printed as hex address.
				535	else if (isBranch) {
				536	SymbolicOp.Value = Value;
				537	}
				538	if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
				539	(*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
				540	if (!Name && !isBranch)
				541	return false;
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	542	}
				543
				544	MCContext *Ctx = Dis->getMCContext();
				545	const MCExpr *Add = NULL;
				546	if (SymbolicOp.AddSymbol.Present) {
				547	if (SymbolicOp.AddSymbol.Name) {
				548	StringRef Name(SymbolicOp.AddSymbol.Name);
				549	MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
				550	Add = MCSymbolRefExpr::Create(Sym, *Ctx);
				551	} else {
				552	Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
				553	}
				554	}
				555
				556	const MCExpr *Sub = NULL;
				557	if (SymbolicOp.SubtractSymbol.Present) {
				558	if (SymbolicOp.SubtractSymbol.Name) {
				559	StringRef Name(SymbolicOp.SubtractSymbol.Name);
				560	MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
				561	Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
				562	} else {
				563	Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
				564	}
				565	}
				566
				567	const MCExpr *Off = NULL;
				568	if (SymbolicOp.Value != 0)
				569	Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
				570
				571	const MCExpr *Expr;
				572	if (Sub) {
				573	const MCExpr *LHS;
				574	if (Add)
				575	LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
				576	else
				577	LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
				578	if (Off != 0)
				579	Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
				580	else
				581	Expr = LHS;
				582	} else if (Add) {
				583	if (Off != 0)
				584	Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
				585	else
				586	Expr = Add;
				587	} else {
				588	if (Off != 0)
				589	Expr = Off;
				590	else
				591	Expr = MCConstantExpr::Create(0, *Ctx);
				592	}
				593
				594	if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
				595	MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
				596	else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
				597	MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
				598	else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
				599	MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach	01817c3	2011-10-20 17:28:20 +0000	[diff] [blame]	600	else
Craig Topper	bc21981	2012-02-07 02:50:20 +0000	[diff] [blame]	601	llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	602
				603	return true;
				604	}
				605
				606	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				607	/// referenced by a load instruction with the base register that is the Pc.
				608	/// These can often be values in a literal pool near the Address of the
				609	/// instruction. The Address of the instruction and its immediate Value are
				610	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	c8e41c5	2012-07-23 08:51:15 +0000	[diff] [blame]	611	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	612	/// the referenced address is that of a symbol. Or it will return a pointer to
				613	/// a literal 'C' string if the referenced address of the literal pool's entry
				614	/// is an address into a section with 'C' string literals.
				615	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	616	const void *Decoder) {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	617	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				618	LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
				619	if (SymbolLookUp) {
				620	void *DisInfo = Dis->getDisInfoBlock();
				621	uint64_t ReferenceType;
				622	ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
				623	const char *ReferenceName;
				624	(void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
				625	if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr \|\|
				626	ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
				627	(*Dis->CommentStream) << "literal pool for: " << ReferenceName;
				628	}
				629	}
				630
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	631	// Thumb1 instructions don't have explicit S bits. Rather, they
				632	// implicitly set CPSR. Since it's not represented in the encoding, the
				633	// auto-generated decoder won't inject the CPSR operand. We need to fix
				634	// that as a post-pass.
				635	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				636	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	637	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	638	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	639	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				640	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	641	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	642	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	643	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				644	return;
				645	}
				646	}
				647
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	648	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	649	}
				650
				651	// Most Thumb instructions don't have explicit predicates in the
				652	// encoding, but rather get their predicates from IT context. We need
				653	// to fix up the predicate operands using this context information as a
				654	// post-pass.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	655	MCDisassembler::DecodeStatus
				656	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	657	MCDisassembler::DecodeStatus S = Success;
				658
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	659	// A few instructions actually have predicates encoded in them. Don't
				660	// try to overwrite it if we're seeing one of those.
				661	switch (MI.getOpcode()) {
				662	case ARM::tBcc:
				663	case ARM::t2Bcc:
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	664	case ARM::tCBZ:
				665	case ARM::tCBNZ:
Owen Anderson	9f666b5	2011-09-19 23:47:10 +0000	[diff] [blame]	666	case ARM::tCPS:
				667	case ARM::t2CPS3p:
				668	case ARM::t2CPS2p:
				669	case ARM::t2CPS1p:
Owen Anderson	d9346fb	2011-09-19 23:57:20 +0000	[diff] [blame]	670	case ARM::tMOVSr:
Owen Anderson	c18e940	2011-10-13 17:58:39 +0000	[diff] [blame]	671	case ARM::tSETEND:
Owen Anderson	441462f	2011-09-08 22:48:37 +0000	[diff] [blame]	672	// Some instructions (mostly conditional branches) are not
				673	// allowed in IT blocks.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	674	if (ITBlock.instrInITBlock())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	675	S = SoftFail;
				676	else
				677	return Success;
				678	break;
				679	case ARM::tB:
				680	case ARM::t2B:
Owen Anderson	04c7877	2011-09-19 22:34:23 +0000	[diff] [blame]	681	case ARM::t2TBB:
				682	case ARM::t2TBH:
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	683	// Some instructions (mostly unconditional branches) can
				684	// only appears at the end of, or outside of, an IT.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	685	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	686	S = SoftFail;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	687	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	688	default:
				689	break;
				690	}
				691
				692	// If we're in an IT block, base the predicate on that. Otherwise,
				693	// assume a predicate of AL.
				694	unsigned CC;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	695	CC = ITBlock.getITCC();
				696	if (CC == 0xF)
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	697	CC = ARMCC::AL;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	698	if (ITBlock.instrInITBlock())
				699	ITBlock.advanceITState();
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	700
				701	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	702	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	703	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	704	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				705	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	706	if (OpInfo[i].isPredicate()) {
				707	I = MI.insert(I, MCOperand::CreateImm(CC));
				708	++I;
				709	if (CC == ARMCC::AL)
				710	MI.insert(I, MCOperand::CreateReg(0));
				711	else
				712	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	713	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	714	}
				715	}
				716
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	717	I = MI.insert(I, MCOperand::CreateImm(CC));
				718	++I;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	719	if (CC == ARMCC::AL)
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	720	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	721	else
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	722	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	723
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	724	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	725	}
				726
				727	// Thumb VFP instructions are a special case. Because we share their
				728	// encodings between ARM and Thumb modes, and they are predicable in ARM
				729	// mode, the auto-generated decoder will give them an (incorrect)
				730	// predicate operand. We need to rewrite these operands based on the IT
				731	// context as a post-pass.
				732	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				733	unsigned CC;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	734	CC = ITBlock.getITCC();
				735	if (ITBlock.instrInITBlock())
				736	ITBlock.advanceITState();
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	737
				738	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				739	MCInst::iterator I = MI.begin();
Owen Anderson	12a1e3b	2011-08-24 21:35:46 +0000	[diff] [blame]	740	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				741	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	742	if (OpInfo[i].isPredicate() ) {
				743	I->setImm(CC);
				744	++I;
				745	if (CC == ARMCC::AL)
				746	I->setReg(0);
				747	else
				748	I->setReg(ARM::CPSR);
				749	return;
				750	}
				751	}
				752	}
				753
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	754	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	755	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	756	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	757	raw_ostream &os,
				758	raw_ostream &cs) const {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	759	CommentStream = &cs;
				760
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	761	uint8_t bytes[4];
				762
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	763	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				764	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				765
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	766	// We want to read exactly 2 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	767	if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
				768	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	769	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	770	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	771
				772	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	773	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				774	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	775	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	776	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	777	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	778	return result;
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	779	}
				780
				781	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	782	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				783	Address, this, STI);
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	784	if (result) {
				785	Size = 2;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	786	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	787	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	788	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	789	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	790	}
				791
				792	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	793	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				794	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	795	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	796	Size = 2;
Owen Anderson	7011eee	2011-10-06 23:33:11 +0000	[diff] [blame]	797
				798	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				799	// the Thumb predicate.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	800	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	7011eee	2011-10-06 23:33:11 +0000	[diff] [blame]	801	result = MCDisassembler::SoftFail;
				802
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	803	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	804
				805	// If we find an IT instruction, we need to parse its condition
				806	// code and mask operands so that we can apply them correctly
				807	// to the subsequent instructions.
				808	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	34626ac	2011-09-14 21:06:21 +0000	[diff] [blame]	809
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	810	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	811	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	812	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	813	}
				814
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	815	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	816	}
				817
				818	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	819	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				820	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	821	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	822	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	823
				824	uint32_t insn32 = (bytes[3] << 8) \|
				825	(bytes[2] << 0) \|
				826	(bytes[1] << 24) \|
				827	(bytes[0] << 16);
				828	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	829	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				830	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	831	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	832	Size = 4;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	833	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	834	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	835	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	836	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	837	}
				838
				839	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	840	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				841	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	842	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	843	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	844	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	845	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	846	}
				847
				848	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	849	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	850	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	851	Size = 4;
				852	UpdateThumbVFPPredicate(MI);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	853	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	854	}
				855
				856	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	857	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				858	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	859	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	860	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	861	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	862	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	863	}
				864
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	865	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	866	MI.clear();
				867	uint32_t NEONLdStInsn = insn32;
				868	NEONLdStInsn &= 0xF0FFFFFF;
				869	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	870	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				871	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	872	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	873	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	874	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	875	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	876	}
				877	}
				878
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	879	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	880	MI.clear();
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	881	uint32_t NEONDataInsn = insn32;
				882	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				883	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				884	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	885	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				886	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	887	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	888	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	889	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	890	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	891	}
				892	}
				893
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	894	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	895	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	896	}
				897
				898
				899	extern "C" void LLVMInitializeARMDisassembler() {
				900	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				901	createARMDisassembler);
				902	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				903	createThumbDisassembler);
				904	}
				905
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	906	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	907	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				908	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				909	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				910	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				911	};
				912
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	913	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	914	uint64_t Address, const void *Decoder) {
				915	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	916	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	917
				918	unsigned Register = GPRDecoderTable[RegNo];
				919	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	920	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	921	}
				922
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	923	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	924	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	925	uint64_t Address, const void *Decoder) {
Silviu Baranga	5c062ad	2012-03-20 15:54:56 +0000	[diff] [blame]	926	DecodeStatus S = MCDisassembler::Success;
				927
				928	if (RegNo == 15)
				929	S = MCDisassembler::SoftFail;
				930
				931	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				932
				933	return S;
Owen Anderson	51c9805	2011-08-09 22:48:45 +0000	[diff] [blame]	934	}
				935
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	936	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	937	uint64_t Address, const void *Decoder) {
				938	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	939	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	940	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				941	}
				942
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	943	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	944	uint64_t Address, const void *Decoder) {
				945	unsigned Register = 0;
				946	switch (RegNo) {
				947	case 0:
				948	Register = ARM::R0;
				949	break;
				950	case 1:
				951	Register = ARM::R1;
				952	break;
				953	case 2:
				954	Register = ARM::R2;
				955	break;
				956	case 3:
				957	Register = ARM::R3;
				958	break;
				959	case 9:
				960	Register = ARM::R9;
				961	break;
				962	case 12:
				963	Register = ARM::R12;
				964	break;
				965	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	966	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	967	}
				968
				969	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	970	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	971	}
				972
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	973	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	974	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	975	if (RegNo == 13 \|\| RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	976	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				977	}
				978
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	979	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	980	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				981	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				982	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				983	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				984	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				985	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				986	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				987	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				988	};
				989
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	990	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	991	uint64_t Address, const void *Decoder) {
				992	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	993	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	994
				995	unsigned Register = SPRDecoderTable[RegNo];
				996	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	997	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	998	}
				999
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1000	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1001	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1002	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1003	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1004	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1005	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1006	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1007	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1008	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1009	};
				1010
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1011	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1012	uint64_t Address, const void *Decoder) {
				1013	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1014	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1015
				1016	unsigned Register = DPRDecoderTable[RegNo];
				1017	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1018	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1019	}
				1020
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1021	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1022	uint64_t Address, const void *Decoder) {
				1023	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1024	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1025	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1026	}
				1027
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1028	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1029	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1030	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1031	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1032	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1033	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1034	}
				1035
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1036	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1037	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1038	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1039	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1040	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1041	};
				1042
				1043
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1044	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1045	uint64_t Address, const void *Decoder) {
				1046	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1047	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1048	RegNo >>= 1;
				1049
				1050	unsigned Register = QPRDecoderTable[RegNo];
				1051	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1052	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1053	}
				1054
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1055	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	1056	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1057	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1058	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1059	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1060	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1061	ARM::Q15
				1062	};
				1063
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1064	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	1065	uint64_t Address, const void *Decoder) {
				1066	if (RegNo > 30)
				1067	return MCDisassembler::Fail;
				1068
				1069	unsigned Register = DPairDecoderTable[RegNo];
				1070	Inst.addOperand(MCOperand::CreateReg(Register));
				1071	return MCDisassembler::Success;
				1072	}
				1073
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1074	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	1075	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1076	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1077	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1078	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1079	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1080	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1081	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1082	ARM::D28_D30, ARM::D29_D31
				1083	};
				1084
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1085	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	1086	unsigned RegNo,
				1087	uint64_t Address,
				1088	const void *Decoder) {
				1089	if (RegNo > 29)
				1090	return MCDisassembler::Fail;
				1091
				1092	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1093	Inst.addOperand(MCOperand::CreateReg(Register));
				1094	return MCDisassembler::Success;
				1095	}
				1096
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1097	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1098	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1099	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	bd9091c	2011-08-09 21:07:45 +0000	[diff] [blame]	1100	// AL predicate is not allowed on Thumb1 branches.
				1101	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1102	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1103	Inst.addOperand(MCOperand::CreateImm(Val));
				1104	if (Val == ARMCC::AL) {
				1105	Inst.addOperand(MCOperand::CreateReg(0));
				1106	} else
				1107	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1108	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1109	}
				1110
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1111	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1112	uint64_t Address, const void *Decoder) {
				1113	if (Val)
				1114	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1115	else
				1116	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1117	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1118	}
				1119
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1120	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1121	uint64_t Address, const void *Decoder) {
				1122	uint32_t imm = Val & 0xFF;
				1123	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	ecb830e	2011-10-13 23:36:06 +0000	[diff] [blame]	1124	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1125	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1126	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1127	}
				1128
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1129	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1130	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1131	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1132
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1133	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1134	unsigned type = fieldFromInstruction(Val, 5, 2);
				1135	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1136
				1137	// Register-immediate
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1138	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1139	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1140
				1141	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1142	switch (type) {
				1143	case 0:
				1144	Shift = ARM_AM::lsl;
				1145	break;
				1146	case 1:
				1147	Shift = ARM_AM::lsr;
				1148	break;
				1149	case 2:
				1150	Shift = ARM_AM::asr;
				1151	break;
				1152	case 3:
				1153	Shift = ARM_AM::ror;
				1154	break;
				1155	}
				1156
				1157	if (Shift == ARM_AM::ror && imm == 0)
				1158	Shift = ARM_AM::rrx;
				1159
				1160	unsigned Op = Shift \| (imm << 3);
				1161	Inst.addOperand(MCOperand::CreateImm(Op));
				1162
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1163	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1164	}
				1165
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1166	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1167	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1168	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1169
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1170	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1171	unsigned type = fieldFromInstruction(Val, 5, 2);
				1172	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1173
				1174	// Register-register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1175	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1176	return MCDisassembler::Fail;
				1177	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1178	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1179
				1180	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1181	switch (type) {
				1182	case 0:
				1183	Shift = ARM_AM::lsl;
				1184	break;
				1185	case 1:
				1186	Shift = ARM_AM::lsr;
				1187	break;
				1188	case 2:
				1189	Shift = ARM_AM::asr;
				1190	break;
				1191	case 3:
				1192	Shift = ARM_AM::ror;
				1193	break;
				1194	}
				1195
				1196	Inst.addOperand(MCOperand::CreateImm(Shift));
				1197
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1198	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1199	}
				1200
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1201	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1202	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1203	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1204
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	1205	bool writebackLoad = false;
				1206	unsigned writebackReg = 0;
				1207	switch (Inst.getOpcode()) {
				1208	default:
				1209	break;
				1210	case ARM::LDMIA_UPD:
				1211	case ARM::LDMDB_UPD:
				1212	case ARM::LDMIB_UPD:
				1213	case ARM::LDMDA_UPD:
				1214	case ARM::t2LDMIA_UPD:
				1215	case ARM::t2LDMDB_UPD:
				1216	writebackLoad = true;
				1217	writebackReg = Inst.getOperand(0).getReg();
				1218	break;
				1219	}
				1220
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	1221	// Empty register lists are not allowed.
Owen Anderson	244006d	2011-11-02 17:46:18 +0000	[diff] [blame]	1222	if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1223	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1224	if (Val & (1 << i)) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1225	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1226	return MCDisassembler::Fail;
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	1227	// Writeback not allowed if Rn is in the target list.
				1228	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				1229	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1230	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1231	}
				1232
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1233	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1234	}
				1235
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1236	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1237	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1238	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1239
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1240	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1241	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1242
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1243	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1244	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1245	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1246	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1247	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1248	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1249
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1250	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1251	}
				1252
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1253	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1254	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1255	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1256
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1257	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1258	unsigned regs = fieldFromInstruction(Val, 0, 8);
Silviu Baranga	b422d0b	2012-05-03 16:38:40 +0000	[diff] [blame]	1259
				1260	regs = regs >> 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1261
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1262	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1263	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1264	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1265	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1266	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1267	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1268
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1269	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1270	}
				1271
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1272	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1273	uint64_t Address, const void *Decoder) {
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1274	// This operand encodes a mask of contiguous zeros between a specified MSB
				1275	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1276	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1277	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1278	// create the final mask.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1279	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1280	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1281
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1282	DecodeStatus S = MCDisassembler::Success;
				1283	if (lsb > msb) Check(S, MCDisassembler::SoftFail);
				1284
Owen Anderson	8b22778	2011-09-16 23:04:48 +0000	[diff] [blame]	1285	uint32_t msb_mask = 0xFFFFFFFF;
				1286	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1287	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1288
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1289	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1290	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1291	}
				1292
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1293	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1294	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1295	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1296
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1297	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1298	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1299	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1300	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1301	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1302	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1303
				1304	switch (Inst.getOpcode()) {
				1305	case ARM::LDC_OFFSET:
				1306	case ARM::LDC_PRE:
				1307	case ARM::LDC_POST:
				1308	case ARM::LDC_OPTION:
				1309	case ARM::LDCL_OFFSET:
				1310	case ARM::LDCL_PRE:
				1311	case ARM::LDCL_POST:
				1312	case ARM::LDCL_OPTION:
				1313	case ARM::STC_OFFSET:
				1314	case ARM::STC_PRE:
				1315	case ARM::STC_POST:
				1316	case ARM::STC_OPTION:
				1317	case ARM::STCL_OFFSET:
				1318	case ARM::STCL_PRE:
				1319	case ARM::STCL_POST:
				1320	case ARM::STCL_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1321	case ARM::t2LDC_OFFSET:
				1322	case ARM::t2LDC_PRE:
				1323	case ARM::t2LDC_POST:
				1324	case ARM::t2LDC_OPTION:
				1325	case ARM::t2LDCL_OFFSET:
				1326	case ARM::t2LDCL_PRE:
				1327	case ARM::t2LDCL_POST:
				1328	case ARM::t2LDCL_OPTION:
				1329	case ARM::t2STC_OFFSET:
				1330	case ARM::t2STC_PRE:
				1331	case ARM::t2STC_POST:
				1332	case ARM::t2STC_OPTION:
				1333	case ARM::t2STCL_OFFSET:
				1334	case ARM::t2STCL_PRE:
				1335	case ARM::t2STCL_POST:
				1336	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1337	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1338	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1339	break;
				1340	default:
				1341	break;
				1342	}
				1343
				1344	Inst.addOperand(MCOperand::CreateImm(coproc));
				1345	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1346	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1347	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1348
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1349	switch (Inst.getOpcode()) {
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1350	case ARM::t2LDC2_OFFSET:
				1351	case ARM::t2LDC2L_OFFSET:
				1352	case ARM::t2LDC2_PRE:
				1353	case ARM::t2LDC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1354	case ARM::t2STC2_OFFSET:
				1355	case ARM::t2STC2L_OFFSET:
				1356	case ARM::t2STC2_PRE:
				1357	case ARM::t2STC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1358	case ARM::LDC2_OFFSET:
				1359	case ARM::LDC2L_OFFSET:
				1360	case ARM::LDC2_PRE:
				1361	case ARM::LDC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1362	case ARM::STC2_OFFSET:
				1363	case ARM::STC2L_OFFSET:
				1364	case ARM::STC2_PRE:
				1365	case ARM::STC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1366	case ARM::t2LDC_OFFSET:
				1367	case ARM::t2LDCL_OFFSET:
				1368	case ARM::t2LDC_PRE:
				1369	case ARM::t2LDCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1370	case ARM::t2STC_OFFSET:
				1371	case ARM::t2STCL_OFFSET:
				1372	case ARM::t2STC_PRE:
				1373	case ARM::t2STCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1374	case ARM::LDC_OFFSET:
				1375	case ARM::LDCL_OFFSET:
				1376	case ARM::LDC_PRE:
				1377	case ARM::LDCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1378	case ARM::STC_OFFSET:
				1379	case ARM::STCL_OFFSET:
				1380	case ARM::STC_PRE:
				1381	case ARM::STCL_PRE:
Jim Grosbach	81b2928	2011-10-12 21:59:02 +0000	[diff] [blame]	1382	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1383	Inst.addOperand(MCOperand::CreateImm(imm));
				1384	break;
				1385	case ARM::t2LDC2_POST:
				1386	case ARM::t2LDC2L_POST:
				1387	case ARM::t2STC2_POST:
				1388	case ARM::t2STC2L_POST:
				1389	case ARM::LDC2_POST:
				1390	case ARM::LDC2L_POST:
				1391	case ARM::STC2_POST:
				1392	case ARM::STC2L_POST:
				1393	case ARM::t2LDC_POST:
				1394	case ARM::t2LDCL_POST:
				1395	case ARM::t2STC_POST:
				1396	case ARM::t2STCL_POST:
				1397	case ARM::LDC_POST:
				1398	case ARM::LDCL_POST:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1399	case ARM::STC_POST:
				1400	case ARM::STCL_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1401	imm \|= U << 8;
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1402	// fall through.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1403	default:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1404	// The 'option' variant doesn't encode 'U' in the immediate since
				1405	// the immediate is unsigned [0,255].
				1406	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1407	break;
				1408	}
				1409
				1410	switch (Inst.getOpcode()) {
				1411	case ARM::LDC_OFFSET:
				1412	case ARM::LDC_PRE:
				1413	case ARM::LDC_POST:
				1414	case ARM::LDC_OPTION:
				1415	case ARM::LDCL_OFFSET:
				1416	case ARM::LDCL_PRE:
				1417	case ARM::LDCL_POST:
				1418	case ARM::LDCL_OPTION:
				1419	case ARM::STC_OFFSET:
				1420	case ARM::STC_PRE:
				1421	case ARM::STC_POST:
				1422	case ARM::STC_OPTION:
				1423	case ARM::STCL_OFFSET:
				1424	case ARM::STCL_PRE:
				1425	case ARM::STCL_POST:
				1426	case ARM::STCL_OPTION:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1427	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1428	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1429	break;
				1430	default:
				1431	break;
				1432	}
				1433
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1434	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1435	}
				1436
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1437	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1438	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1439	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1440	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1441
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1442	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1443	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1444	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1445	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1446	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1447	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1448	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1449	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1450
				1451	// On stores, the writeback operand precedes Rt.
				1452	switch (Inst.getOpcode()) {
				1453	case ARM::STR_POST_IMM:
				1454	case ARM::STR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1455	case ARM::STRB_POST_IMM:
				1456	case ARM::STRB_POST_REG:
Jim Grosbach	342ebd5	2011-08-11 22:18:00 +0000	[diff] [blame]	1457	case ARM::STRT_POST_REG:
				1458	case ARM::STRT_POST_IMM:
Jim Grosbach	10348e7	2011-08-11 20:04:56 +0000	[diff] [blame]	1459	case ARM::STRBT_POST_REG:
				1460	case ARM::STRBT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1461	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1462	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1463	break;
				1464	default:
				1465	break;
				1466	}
				1467
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1468	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1469	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1470
				1471	// On loads, the writeback operand comes after Rt.
				1472	switch (Inst.getOpcode()) {
				1473	case ARM::LDR_POST_IMM:
				1474	case ARM::LDR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1475	case ARM::LDRB_POST_IMM:
				1476	case ARM::LDRB_POST_REG:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1477	case ARM::LDRBT_POST_REG:
				1478	case ARM::LDRBT_POST_IMM:
Jim Grosbach	5999926	2011-08-10 23:43:54 +0000	[diff] [blame]	1479	case ARM::LDRT_POST_REG:
				1480	case ARM::LDRT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1481	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1482	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1483	break;
				1484	default:
				1485	break;
				1486	}
				1487
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1488	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1489	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1490
				1491	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1492	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1493	Op = ARM_AM::sub;
				1494
				1495	bool writeback = (P == 0) \|\| (W == 1);
				1496	unsigned idx_mode = 0;
				1497	if (P && writeback)
				1498	idx_mode = ARMII::IndexModePre;
				1499	else if (!P && writeback)
				1500	idx_mode = ARMII::IndexModePost;
				1501
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1502	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1503	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	71156a6	2011-08-11 19:00:18 +0000	[diff] [blame]	1504
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1505	if (reg) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1506	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1507	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1508	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1509	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1510	case 0:
				1511	Opc = ARM_AM::lsl;
				1512	break;
				1513	case 1:
				1514	Opc = ARM_AM::lsr;
				1515	break;
				1516	case 2:
				1517	Opc = ARM_AM::asr;
				1518	break;
				1519	case 3:
				1520	Opc = ARM_AM::ror;
				1521	break;
				1522	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1523	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1524	}
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1525	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1526	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1527
				1528	Inst.addOperand(MCOperand::CreateImm(imm));
				1529	} else {
				1530	Inst.addOperand(MCOperand::CreateReg(0));
				1531	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1532	Inst.addOperand(MCOperand::CreateImm(tmp));
				1533	}
				1534
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1535	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1536	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1537
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1538	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1539	}
				1540
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1541	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1542	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1543	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1544
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1545	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1546	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1547	unsigned type = fieldFromInstruction(Val, 5, 2);
				1548	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1549	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1550
Owen Anderson	51157d2	2011-08-09 21:38:14 +0000	[diff] [blame]	1551	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1552	switch (type) {
				1553	case 0:
				1554	ShOp = ARM_AM::lsl;
				1555	break;
				1556	case 1:
				1557	ShOp = ARM_AM::lsr;
				1558	break;
				1559	case 2:
				1560	ShOp = ARM_AM::asr;
				1561	break;
				1562	case 3:
				1563	ShOp = ARM_AM::ror;
				1564	break;
				1565	}
				1566
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1567	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1568	return MCDisassembler::Fail;
				1569	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1570	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1571	unsigned shift;
				1572	if (U)
				1573	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1574	else
				1575	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1576	Inst.addOperand(MCOperand::CreateImm(shift));
				1577
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1578	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1579	}
				1580
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1581	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1582	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1583	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1584	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1585
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1586	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1587	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1588	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1589	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1590	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1591	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1592	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1593	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1594	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1595	unsigned Rt2 = Rt + 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1596
				1597	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1598
				1599	// For {LD,ST}RD, Rt must be even, else undefined.
				1600	switch (Inst.getOpcode()) {
				1601	case ARM::STRD:
				1602	case ARM::STRD_PRE:
				1603	case ARM::STRD_POST:
				1604	case ARM::LDRD:
				1605	case ARM::LDRD_PRE:
				1606	case ARM::LDRD_POST:
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1607	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1608	break;
				1609	default:
				1610	break;
				1611	}
				1612	switch (Inst.getOpcode()) {
				1613	case ARM::STRD:
				1614	case ARM::STRD_PRE:
				1615	case ARM::STRD_POST:
				1616	if (P == 0 && W == 1)
				1617	S = MCDisassembler::SoftFail;
				1618
				1619	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1620	S = MCDisassembler::SoftFail;
				1621	if (type && Rm == 15)
				1622	S = MCDisassembler::SoftFail;
				1623	if (Rt2 == 15)
				1624	S = MCDisassembler::SoftFail;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1625	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1626	S = MCDisassembler::SoftFail;
				1627	break;
				1628	case ARM::STRH:
				1629	case ARM::STRH_PRE:
				1630	case ARM::STRH_POST:
				1631	if (Rt == 15)
				1632	S = MCDisassembler::SoftFail;
				1633	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1634	S = MCDisassembler::SoftFail;
				1635	if (!type && Rm == 15)
				1636	S = MCDisassembler::SoftFail;
				1637	break;
				1638	case ARM::LDRD:
				1639	case ARM::LDRD_PRE:
				1640	case ARM::LDRD_POST:
				1641	if (type && Rn == 15){
				1642	if (Rt2 == 15)
				1643	S = MCDisassembler::SoftFail;
				1644	break;
				1645	}
				1646	if (P == 0 && W == 1)
				1647	S = MCDisassembler::SoftFail;
				1648	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1649	S = MCDisassembler::SoftFail;
				1650	if (!type && writeback && Rn == 15)
				1651	S = MCDisassembler::SoftFail;
				1652	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1653	S = MCDisassembler::SoftFail;
				1654	break;
				1655	case ARM::LDRH:
				1656	case ARM::LDRH_PRE:
				1657	case ARM::LDRH_POST:
				1658	if (type && Rn == 15){
				1659	if (Rt == 15)
				1660	S = MCDisassembler::SoftFail;
				1661	break;
				1662	}
				1663	if (Rt == 15)
				1664	S = MCDisassembler::SoftFail;
				1665	if (!type && Rm == 15)
				1666	S = MCDisassembler::SoftFail;
				1667	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1668	S = MCDisassembler::SoftFail;
				1669	break;
				1670	case ARM::LDRSH:
				1671	case ARM::LDRSH_PRE:
				1672	case ARM::LDRSH_POST:
				1673	case ARM::LDRSB:
				1674	case ARM::LDRSB_PRE:
				1675	case ARM::LDRSB_POST:
				1676	if (type && Rn == 15){
				1677	if (Rt == 15)
				1678	S = MCDisassembler::SoftFail;
				1679	break;
				1680	}
				1681	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1682	S = MCDisassembler::SoftFail;
				1683	if (!type && (Rt == 15 \|\| Rm == 15))
				1684	S = MCDisassembler::SoftFail;
				1685	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1686	S = MCDisassembler::SoftFail;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1687	break;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1688	default:
				1689	break;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1690	}
				1691
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1692	if (writeback) { // Writeback
				1693	if (P)
				1694	U \|= ARMII::IndexModePre << 9;
				1695	else
				1696	U \|= ARMII::IndexModePost << 9;
				1697
				1698	// On stores, the writeback operand precedes Rt.
				1699	switch (Inst.getOpcode()) {
				1700	case ARM::STRD:
				1701	case ARM::STRD_PRE:
				1702	case ARM::STRD_POST:
Owen Anderson	79628e9	2011-08-12 20:02:50 +0000	[diff] [blame]	1703	case ARM::STRH:
				1704	case ARM::STRH_PRE:
				1705	case ARM::STRH_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1706	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1707	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1708	break;
				1709	default:
				1710	break;
				1711	}
				1712	}
				1713
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1714	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1715	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1716	switch (Inst.getOpcode()) {
				1717	case ARM::STRD:
				1718	case ARM::STRD_PRE:
				1719	case ARM::STRD_POST:
				1720	case ARM::LDRD:
				1721	case ARM::LDRD_PRE:
				1722	case ARM::LDRD_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1723	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1724	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1725	break;
				1726	default:
				1727	break;
				1728	}
				1729
				1730	if (writeback) {
				1731	// On loads, the writeback operand comes after Rt.
				1732	switch (Inst.getOpcode()) {
				1733	case ARM::LDRD:
				1734	case ARM::LDRD_PRE:
				1735	case ARM::LDRD_POST:
Owen Anderson	0d09499	2011-08-12 20:36:11 +0000	[diff] [blame]	1736	case ARM::LDRH:
				1737	case ARM::LDRH_PRE:
				1738	case ARM::LDRH_POST:
				1739	case ARM::LDRSH:
				1740	case ARM::LDRSH_PRE:
				1741	case ARM::LDRSH_POST:
				1742	case ARM::LDRSB:
				1743	case ARM::LDRSB_PRE:
				1744	case ARM::LDRSB_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1745	case ARM::LDRHTr:
				1746	case ARM::LDRSBTr:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1747	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1748	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1749	break;
				1750	default:
				1751	break;
				1752	}
				1753	}
				1754
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1755	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1756	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1757
				1758	if (type) {
				1759	Inst.addOperand(MCOperand::CreateReg(0));
				1760	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1761	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1762	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1763	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1764	Inst.addOperand(MCOperand::CreateImm(U));
				1765	}
				1766
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1767	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1768	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1769
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1770	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1771	}
				1772
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1773	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1774	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1775	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1776
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1777	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1778	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1779
				1780	switch (mode) {
				1781	case 0:
				1782	mode = ARM_AM::da;
				1783	break;
				1784	case 1:
				1785	mode = ARM_AM::ia;
				1786	break;
				1787	case 2:
				1788	mode = ARM_AM::db;
				1789	break;
				1790	case 3:
				1791	mode = ARM_AM::ib;
				1792	break;
				1793	}
				1794
				1795	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1796	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1797	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1798
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1799	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1800	}
				1801
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1802	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1803	unsigned Insn,
				1804	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1805	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1806
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1807	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1808	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1809	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1810
				1811	if (pred == 0xF) {
				1812	switch (Inst.getOpcode()) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1813	case ARM::LDMDA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1814	Inst.setOpcode(ARM::RFEDA);
				1815	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1816	case ARM::LDMDA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1817	Inst.setOpcode(ARM::RFEDA_UPD);
				1818	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1819	case ARM::LDMDB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1820	Inst.setOpcode(ARM::RFEDB);
				1821	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1822	case ARM::LDMDB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1823	Inst.setOpcode(ARM::RFEDB_UPD);
				1824	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1825	case ARM::LDMIA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1826	Inst.setOpcode(ARM::RFEIA);
				1827	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1828	case ARM::LDMIA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1829	Inst.setOpcode(ARM::RFEIA_UPD);
				1830	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1831	case ARM::LDMIB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1832	Inst.setOpcode(ARM::RFEIB);
				1833	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1834	case ARM::LDMIB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1835	Inst.setOpcode(ARM::RFEIB_UPD);
				1836	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1837	case ARM::STMDA:
				1838	Inst.setOpcode(ARM::SRSDA);
				1839	break;
				1840	case ARM::STMDA_UPD:
				1841	Inst.setOpcode(ARM::SRSDA_UPD);
				1842	break;
				1843	case ARM::STMDB:
				1844	Inst.setOpcode(ARM::SRSDB);
				1845	break;
				1846	case ARM::STMDB_UPD:
				1847	Inst.setOpcode(ARM::SRSDB_UPD);
				1848	break;
				1849	case ARM::STMIA:
				1850	Inst.setOpcode(ARM::SRSIA);
				1851	break;
				1852	case ARM::STMIA_UPD:
				1853	Inst.setOpcode(ARM::SRSIA_UPD);
				1854	break;
				1855	case ARM::STMIB:
				1856	Inst.setOpcode(ARM::SRSIB);
				1857	break;
				1858	case ARM::STMIB_UPD:
				1859	Inst.setOpcode(ARM::SRSIB_UPD);
				1860	break;
				1861	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1862	if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1863	}
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1864
				1865	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1866	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1867	Inst.addOperand(
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1868	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1869	return S;
				1870	}
				1871
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1872	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1873	}
				1874
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1875	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1876	return MCDisassembler::Fail;
				1877	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1878	return MCDisassembler::Fail; // Tied
				1879	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1880	return MCDisassembler::Fail;
				1881	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1882	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1883
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1884	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1885	}
				1886
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1887	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1888	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1889	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1890	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1891	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1892	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1893
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1894	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	1895
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1896	// imod == '01' --> UNPREDICTABLE
				1897	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1898	// return failure here. The '01' imod value is unprintable, so there's
				1899	// nothing useful we could do even if we returned UNPREDICTABLE.
				1900
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1901	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1902
				1903	if (imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1904	Inst.setOpcode(ARM::CPS3p);
				1905	Inst.addOperand(MCOperand::CreateImm(imod));
				1906	Inst.addOperand(MCOperand::CreateImm(iflags));
				1907	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1908	} else if (imod && !M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1909	Inst.setOpcode(ARM::CPS2p);
				1910	Inst.addOperand(MCOperand::CreateImm(imod));
				1911	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1912	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1913	} else if (!imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1914	Inst.setOpcode(ARM::CPS1p);
				1915	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1916	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1917	} else {
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1918	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1919	Inst.setOpcode(ARM::CPS1p);
				1920	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1921	S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1922	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1923
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1924	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1925	}
				1926
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1927	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1928	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1929	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1930	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1931	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				1932	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1933
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1934	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1935
				1936	// imod == '01' --> UNPREDICTABLE
				1937	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1938	// return failure here. The '01' imod value is unprintable, so there's
				1939	// nothing useful we could do even if we returned UNPREDICTABLE.
				1940
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1941	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1942
				1943	if (imod && M) {
				1944	Inst.setOpcode(ARM::t2CPS3p);
				1945	Inst.addOperand(MCOperand::CreateImm(imod));
				1946	Inst.addOperand(MCOperand::CreateImm(iflags));
				1947	Inst.addOperand(MCOperand::CreateImm(mode));
				1948	} else if (imod && !M) {
				1949	Inst.setOpcode(ARM::t2CPS2p);
				1950	Inst.addOperand(MCOperand::CreateImm(imod));
				1951	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1952	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1953	} else if (!imod && M) {
				1954	Inst.setOpcode(ARM::t2CPS1p);
				1955	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1956	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1957	} else {
				1958	// imod == '00' && M == '0' --> UNPREDICTABLE
				1959	Inst.setOpcode(ARM::t2CPS1p);
				1960	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1961	S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1962	}
				1963
				1964	return S;
				1965	}
				1966
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1967	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1968	uint64_t Address, const void *Decoder) {
				1969	DecodeStatus S = MCDisassembler::Success;
				1970
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1971	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1972	unsigned imm = 0;
				1973
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1974	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				1975	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				1976	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				1977	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1978
				1979	if (Inst.getOpcode() == ARM::t2MOVTi16)
				1980	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				1981	return MCDisassembler::Fail;
				1982	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				1983	return MCDisassembler::Fail;
				1984
				1985	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				1986	Inst.addOperand(MCOperand::CreateImm(imm));
				1987
				1988	return S;
				1989	}
				1990
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1991	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1992	uint64_t Address, const void *Decoder) {
				1993	DecodeStatus S = MCDisassembler::Success;
				1994
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1995	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1996	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1997	unsigned imm = 0;
				1998
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1999	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2000	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2001
				2002	if (Inst.getOpcode() == ARM::MOVTi16)
				2003	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2004	return MCDisassembler::Fail;
				2005	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2006	return MCDisassembler::Fail;
				2007
				2008	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2009	Inst.addOperand(MCOperand::CreateImm(imm));
				2010
				2011	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2012	return MCDisassembler::Fail;
				2013
				2014	return S;
				2015	}
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	2016
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2017	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2018	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2019	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2020
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2021	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2022	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2023	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2024	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2025	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2026
				2027	if (pred == 0xF)
				2028	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2029
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2030	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2031	return MCDisassembler::Fail;
				2032	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2033	return MCDisassembler::Fail;
				2034	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2035	return MCDisassembler::Fail;
				2036	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2037	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2038
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2039	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2040	return MCDisassembler::Fail;
Owen Anderson	1fb6673	2011-08-11 22:05:38 +0000	[diff] [blame]	2041
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2042	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2043	}
				2044
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2045	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2046	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2047	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2048
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2049	unsigned add = fieldFromInstruction(Val, 12, 1);
				2050	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2051	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2052
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2053	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2054	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2055
				2056	if (!add) imm *= -1;
				2057	if (imm == 0 && !add) imm = INT32_MIN;
				2058	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2059	if (Rn == 15)
				2060	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2061
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2062	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2063	}
				2064
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2065	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2066	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2067	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2068
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2069	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2070	unsigned U = fieldFromInstruction(Val, 8, 1);
				2071	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2072
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2073	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2074	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2075
				2076	if (U)
				2077	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2078	else
				2079	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2080
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2081	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2082	}
				2083
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2084	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2085	uint64_t Address, const void *Decoder) {
				2086	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2087	}
				2088
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2089	static DecodeStatus
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2090	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2091	uint64_t Address, const void *Decoder) {
				2092	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2093	unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) \|
				2094	(fieldFromInstruction(Insn, 11, 1) << 18) \|
				2095	(fieldFromInstruction(Insn, 13, 1) << 17) \|
				2096	(fieldFromInstruction(Insn, 16, 6) << 11) \|
				2097	(fieldFromInstruction(Insn, 26, 1) << 19);
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2098	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
				2099	true, 4, Inst, Decoder))
				2100	Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
				2101	return S;
				2102	}
				2103
				2104	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2105	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2106	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2107	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2108
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2109	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2110	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2111
				2112	if (pred == 0xF) {
				2113	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2114	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	2115	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2116	true, 4, Inst, Decoder))
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	2117	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2118	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2119	}
				2120
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	2121	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2122	true, 4, Inst, Decoder))
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2123	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2124	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2125	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2126
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2127	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2128	}
				2129
				2130
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2131	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2132	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2133	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2134
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2135	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2136	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2137
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2138	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2139	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2140	if (!align)
				2141	Inst.addOperand(MCOperand::CreateImm(0));
				2142	else
				2143	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2144
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2145	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2146	}
				2147
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2148	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2149	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2150	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2151
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2152	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2153	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2154	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2155	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2156	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2157	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2158
				2159	// First output register
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2160	switch (Inst.getOpcode()) {
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2161	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2162	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2163	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2164	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2165	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2166	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2167	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2168	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2169	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2170	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2171	return MCDisassembler::Fail;
				2172	break;
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	2173	case ARM::VLD2b16:
				2174	case ARM::VLD2b32:
				2175	case ARM::VLD2b8:
				2176	case ARM::VLD2b16wb_fixed:
				2177	case ARM::VLD2b16wb_register:
				2178	case ARM::VLD2b32wb_fixed:
				2179	case ARM::VLD2b32wb_register:
				2180	case ARM::VLD2b8wb_fixed:
				2181	case ARM::VLD2b8wb_register:
				2182	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2183	return MCDisassembler::Fail;
				2184	break;
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2185	default:
				2186	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2187	return MCDisassembler::Fail;
				2188	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2189
				2190	// Second output register
				2191	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2192	case ARM::VLD3d8:
				2193	case ARM::VLD3d16:
				2194	case ARM::VLD3d32:
				2195	case ARM::VLD3d8_UPD:
				2196	case ARM::VLD3d16_UPD:
				2197	case ARM::VLD3d32_UPD:
				2198	case ARM::VLD4d8:
				2199	case ARM::VLD4d16:
				2200	case ARM::VLD4d32:
				2201	case ARM::VLD4d8_UPD:
				2202	case ARM::VLD4d16_UPD:
				2203	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2204	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2205	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2206	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2207	case ARM::VLD3q8:
				2208	case ARM::VLD3q16:
				2209	case ARM::VLD3q32:
				2210	case ARM::VLD3q8_UPD:
				2211	case ARM::VLD3q16_UPD:
				2212	case ARM::VLD3q32_UPD:
				2213	case ARM::VLD4q8:
				2214	case ARM::VLD4q16:
				2215	case ARM::VLD4q32:
				2216	case ARM::VLD4q8_UPD:
				2217	case ARM::VLD4q16_UPD:
				2218	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2219	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2220	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2221	default:
				2222	break;
				2223	}
				2224
				2225	// Third output register
				2226	switch(Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2227	case ARM::VLD3d8:
				2228	case ARM::VLD3d16:
				2229	case ARM::VLD3d32:
				2230	case ARM::VLD3d8_UPD:
				2231	case ARM::VLD3d16_UPD:
				2232	case ARM::VLD3d32_UPD:
				2233	case ARM::VLD4d8:
				2234	case ARM::VLD4d16:
				2235	case ARM::VLD4d32:
				2236	case ARM::VLD4d8_UPD:
				2237	case ARM::VLD4d16_UPD:
				2238	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2239	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2240	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2241	break;
				2242	case ARM::VLD3q8:
				2243	case ARM::VLD3q16:
				2244	case ARM::VLD3q32:
				2245	case ARM::VLD3q8_UPD:
				2246	case ARM::VLD3q16_UPD:
				2247	case ARM::VLD3q32_UPD:
				2248	case ARM::VLD4q8:
				2249	case ARM::VLD4q16:
				2250	case ARM::VLD4q32:
				2251	case ARM::VLD4q8_UPD:
				2252	case ARM::VLD4q16_UPD:
				2253	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2254	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2255	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2256	break;
				2257	default:
				2258	break;
				2259	}
				2260
				2261	// Fourth output register
				2262	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2263	case ARM::VLD4d8:
				2264	case ARM::VLD4d16:
				2265	case ARM::VLD4d32:
				2266	case ARM::VLD4d8_UPD:
				2267	case ARM::VLD4d16_UPD:
				2268	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2269	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2270	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2271	break;
				2272	case ARM::VLD4q8:
				2273	case ARM::VLD4q16:
				2274	case ARM::VLD4q32:
				2275	case ARM::VLD4q8_UPD:
				2276	case ARM::VLD4q16_UPD:
				2277	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2278	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2279	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2280	break;
				2281	default:
				2282	break;
				2283	}
				2284
				2285	// Writeback operand
				2286	switch (Inst.getOpcode()) {
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2287	case ARM::VLD1d8wb_fixed:
				2288	case ARM::VLD1d16wb_fixed:
				2289	case ARM::VLD1d32wb_fixed:
				2290	case ARM::VLD1d64wb_fixed:
				2291	case ARM::VLD1d8wb_register:
				2292	case ARM::VLD1d16wb_register:
				2293	case ARM::VLD1d32wb_register:
				2294	case ARM::VLD1d64wb_register:
				2295	case ARM::VLD1q8wb_fixed:
				2296	case ARM::VLD1q16wb_fixed:
				2297	case ARM::VLD1q32wb_fixed:
				2298	case ARM::VLD1q64wb_fixed:
				2299	case ARM::VLD1q8wb_register:
				2300	case ARM::VLD1q16wb_register:
				2301	case ARM::VLD1q32wb_register:
				2302	case ARM::VLD1q64wb_register:
Jim Grosbach	5921675	2011-10-24 23:26:05 +0000	[diff] [blame]	2303	case ARM::VLD1d8Twb_fixed:
				2304	case ARM::VLD1d8Twb_register:
				2305	case ARM::VLD1d16Twb_fixed:
				2306	case ARM::VLD1d16Twb_register:
				2307	case ARM::VLD1d32Twb_fixed:
				2308	case ARM::VLD1d32Twb_register:
				2309	case ARM::VLD1d64Twb_fixed:
				2310	case ARM::VLD1d64Twb_register:
Jim Grosbach	399cdca	2011-10-25 00:14:01 +0000	[diff] [blame]	2311	case ARM::VLD1d8Qwb_fixed:
				2312	case ARM::VLD1d8Qwb_register:
				2313	case ARM::VLD1d16Qwb_fixed:
				2314	case ARM::VLD1d16Qwb_register:
				2315	case ARM::VLD1d32Qwb_fixed:
				2316	case ARM::VLD1d32Qwb_register:
				2317	case ARM::VLD1d64Qwb_fixed:
				2318	case ARM::VLD1d64Qwb_register:
Jim Grosbach	a4e3c7f	2011-12-09 21:28:25 +0000	[diff] [blame]	2319	case ARM::VLD2d8wb_fixed:
				2320	case ARM::VLD2d16wb_fixed:
				2321	case ARM::VLD2d32wb_fixed:
				2322	case ARM::VLD2q8wb_fixed:
				2323	case ARM::VLD2q16wb_fixed:
				2324	case ARM::VLD2q32wb_fixed:
				2325	case ARM::VLD2d8wb_register:
				2326	case ARM::VLD2d16wb_register:
				2327	case ARM::VLD2d32wb_register:
				2328	case ARM::VLD2q8wb_register:
				2329	case ARM::VLD2q16wb_register:
				2330	case ARM::VLD2q32wb_register:
				2331	case ARM::VLD2b8wb_fixed:
				2332	case ARM::VLD2b16wb_fixed:
				2333	case ARM::VLD2b32wb_fixed:
				2334	case ARM::VLD2b8wb_register:
				2335	case ARM::VLD2b16wb_register:
				2336	case ARM::VLD2b32wb_register:
Kevin Enderby	a69da35	2012-04-11 00:25:40 +0000	[diff] [blame]	2337	Inst.addOperand(MCOperand::CreateImm(0));
				2338	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2339	case ARM::VLD3d8_UPD:
				2340	case ARM::VLD3d16_UPD:
				2341	case ARM::VLD3d32_UPD:
				2342	case ARM::VLD3q8_UPD:
				2343	case ARM::VLD3q16_UPD:
				2344	case ARM::VLD3q32_UPD:
				2345	case ARM::VLD4d8_UPD:
				2346	case ARM::VLD4d16_UPD:
				2347	case ARM::VLD4d32_UPD:
				2348	case ARM::VLD4q8_UPD:
				2349	case ARM::VLD4q16_UPD:
				2350	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2351	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2352	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2353	break;
				2354	default:
				2355	break;
				2356	}
				2357
				2358	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2359	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2360	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2361
				2362	// AddrMode6 Offset (register)
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2363	switch (Inst.getOpcode()) {
				2364	default:
				2365	// The below have been updated to have explicit am6offset split
				2366	// between fixed and register offset. For those instructions not
				2367	// yet updated, we need to add an additional reg0 operand for the
				2368	// fixed variant.
				2369	//
				2370	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2371	if (Rm == 0xd) {
				2372	Inst.addOperand(MCOperand::CreateReg(0));
				2373	break;
				2374	}
				2375	// Fall through to handle the register offset variant.
				2376	case ARM::VLD1d8wb_fixed:
				2377	case ARM::VLD1d16wb_fixed:
				2378	case ARM::VLD1d32wb_fixed:
				2379	case ARM::VLD1d64wb_fixed:
Owen Anderson	04b12a4	2011-10-27 22:53:10 +0000	[diff] [blame]	2380	case ARM::VLD1d8Twb_fixed:
				2381	case ARM::VLD1d16Twb_fixed:
				2382	case ARM::VLD1d32Twb_fixed:
				2383	case ARM::VLD1d64Twb_fixed:
Owen Anderson	fb6ab2b	2011-10-31 17:17:32 +0000	[diff] [blame]	2384	case ARM::VLD1d8Qwb_fixed:
				2385	case ARM::VLD1d16Qwb_fixed:
				2386	case ARM::VLD1d32Qwb_fixed:
				2387	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2388	case ARM::VLD1d8wb_register:
				2389	case ARM::VLD1d16wb_register:
				2390	case ARM::VLD1d32wb_register:
				2391	case ARM::VLD1d64wb_register:
				2392	case ARM::VLD1q8wb_fixed:
				2393	case ARM::VLD1q16wb_fixed:
				2394	case ARM::VLD1q32wb_fixed:
				2395	case ARM::VLD1q64wb_fixed:
				2396	case ARM::VLD1q8wb_register:
				2397	case ARM::VLD1q16wb_register:
				2398	case ARM::VLD1q32wb_register:
				2399	case ARM::VLD1q64wb_register:
				2400	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2401	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2402	// increment and we need to add the register operand to the instruction.
				2403	if (Rm != 0xD && Rm != 0xF &&
				2404	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2405	return MCDisassembler::Fail;
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2406	break;
Kevin Enderby	a69da35	2012-04-11 00:25:40 +0000	[diff] [blame]	2407	case ARM::VLD2d8wb_fixed:
				2408	case ARM::VLD2d16wb_fixed:
				2409	case ARM::VLD2d32wb_fixed:
				2410	case ARM::VLD2b8wb_fixed:
				2411	case ARM::VLD2b16wb_fixed:
				2412	case ARM::VLD2b32wb_fixed:
				2413	case ARM::VLD2q8wb_fixed:
				2414	case ARM::VLD2q16wb_fixed:
				2415	case ARM::VLD2q32wb_fixed:
				2416	break;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2417	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2418
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2419	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2420	}
				2421
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2422	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2423	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2424	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2425
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2426	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2427	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2428	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2429	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2430	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2431	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2432
				2433	// Writeback Operand
				2434	switch (Inst.getOpcode()) {
Jim Grosbach	4334e03	2011-10-31 21:50:31 +0000	[diff] [blame]	2435	case ARM::VST1d8wb_fixed:
				2436	case ARM::VST1d16wb_fixed:
				2437	case ARM::VST1d32wb_fixed:
				2438	case ARM::VST1d64wb_fixed:
				2439	case ARM::VST1d8wb_register:
				2440	case ARM::VST1d16wb_register:
				2441	case ARM::VST1d32wb_register:
				2442	case ARM::VST1d64wb_register:
				2443	case ARM::VST1q8wb_fixed:
				2444	case ARM::VST1q16wb_fixed:
				2445	case ARM::VST1q32wb_fixed:
				2446	case ARM::VST1q64wb_fixed:
				2447	case ARM::VST1q8wb_register:
				2448	case ARM::VST1q16wb_register:
				2449	case ARM::VST1q32wb_register:
				2450	case ARM::VST1q64wb_register:
Jim Grosbach	d5ca201	2011-11-29 22:38:04 +0000	[diff] [blame]	2451	case ARM::VST1d8Twb_fixed:
				2452	case ARM::VST1d16Twb_fixed:
				2453	case ARM::VST1d32Twb_fixed:
				2454	case ARM::VST1d64Twb_fixed:
				2455	case ARM::VST1d8Twb_register:
				2456	case ARM::VST1d16Twb_register:
				2457	case ARM::VST1d32Twb_register:
				2458	case ARM::VST1d64Twb_register:
Jim Grosbach	4c7edb3	2011-11-29 22:58:48 +0000	[diff] [blame]	2459	case ARM::VST1d8Qwb_fixed:
				2460	case ARM::VST1d16Qwb_fixed:
				2461	case ARM::VST1d32Qwb_fixed:
				2462	case ARM::VST1d64Qwb_fixed:
				2463	case ARM::VST1d8Qwb_register:
				2464	case ARM::VST1d16Qwb_register:
				2465	case ARM::VST1d32Qwb_register:
				2466	case ARM::VST1d64Qwb_register:
Jim Grosbach	bb3a2e4	2011-12-14 21:32:11 +0000	[diff] [blame]	2467	case ARM::VST2d8wb_fixed:
				2468	case ARM::VST2d16wb_fixed:
				2469	case ARM::VST2d32wb_fixed:
				2470	case ARM::VST2d8wb_register:
				2471	case ARM::VST2d16wb_register:
				2472	case ARM::VST2d32wb_register:
				2473	case ARM::VST2q8wb_fixed:
				2474	case ARM::VST2q16wb_fixed:
				2475	case ARM::VST2q32wb_fixed:
				2476	case ARM::VST2q8wb_register:
				2477	case ARM::VST2q16wb_register:
				2478	case ARM::VST2q32wb_register:
				2479	case ARM::VST2b8wb_fixed:
				2480	case ARM::VST2b16wb_fixed:
				2481	case ARM::VST2b32wb_fixed:
				2482	case ARM::VST2b8wb_register:
				2483	case ARM::VST2b16wb_register:
				2484	case ARM::VST2b32wb_register:
Kevin Enderby	b318cc1	2012-04-11 22:40:17 +0000	[diff] [blame]	2485	if (Rm == 0xF)
				2486	return MCDisassembler::Fail;
Kevin Enderby	f0586f0	2012-03-21 20:54:32 +0000	[diff] [blame]	2487	Inst.addOperand(MCOperand::CreateImm(0));
				2488	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2489	case ARM::VST3d8_UPD:
				2490	case ARM::VST3d16_UPD:
				2491	case ARM::VST3d32_UPD:
				2492	case ARM::VST3q8_UPD:
				2493	case ARM::VST3q16_UPD:
				2494	case ARM::VST3q32_UPD:
				2495	case ARM::VST4d8_UPD:
				2496	case ARM::VST4d16_UPD:
				2497	case ARM::VST4d32_UPD:
				2498	case ARM::VST4q8_UPD:
				2499	case ARM::VST4q16_UPD:
				2500	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2501	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2502	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2503	break;
				2504	default:
				2505	break;
				2506	}
				2507
				2508	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2509	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2510	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2511
				2512	// AddrMode6 Offset (register)
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2513	switch (Inst.getOpcode()) {
				2514	default:
				2515	if (Rm == 0xD)
				2516	Inst.addOperand(MCOperand::CreateReg(0));
				2517	else if (Rm != 0xF) {
				2518	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2519	return MCDisassembler::Fail;
				2520	}
				2521	break;
				2522	case ARM::VST1d8wb_fixed:
				2523	case ARM::VST1d16wb_fixed:
				2524	case ARM::VST1d32wb_fixed:
				2525	case ARM::VST1d64wb_fixed:
				2526	case ARM::VST1q8wb_fixed:
				2527	case ARM::VST1q16wb_fixed:
				2528	case ARM::VST1q32wb_fixed:
				2529	case ARM::VST1q64wb_fixed:
Kevin Enderby	f0586f0	2012-03-21 20:54:32 +0000	[diff] [blame]	2530	case ARM::VST1d8Twb_fixed:
				2531	case ARM::VST1d16Twb_fixed:
				2532	case ARM::VST1d32Twb_fixed:
				2533	case ARM::VST1d64Twb_fixed:
				2534	case ARM::VST1d8Qwb_fixed:
				2535	case ARM::VST1d16Qwb_fixed:
				2536	case ARM::VST1d32Qwb_fixed:
				2537	case ARM::VST1d64Qwb_fixed:
				2538	case ARM::VST2d8wb_fixed:
				2539	case ARM::VST2d16wb_fixed:
				2540	case ARM::VST2d32wb_fixed:
				2541	case ARM::VST2q8wb_fixed:
				2542	case ARM::VST2q16wb_fixed:
				2543	case ARM::VST2q32wb_fixed:
				2544	case ARM::VST2b8wb_fixed:
				2545	case ARM::VST2b16wb_fixed:
				2546	case ARM::VST2b32wb_fixed:
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2547	break;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2548	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2549
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2550
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2551	// First input register
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2552	switch (Inst.getOpcode()) {
				2553	case ARM::VST1q16:
				2554	case ARM::VST1q32:
				2555	case ARM::VST1q64:
				2556	case ARM::VST1q8:
				2557	case ARM::VST1q16wb_fixed:
				2558	case ARM::VST1q16wb_register:
				2559	case ARM::VST1q32wb_fixed:
				2560	case ARM::VST1q32wb_register:
				2561	case ARM::VST1q64wb_fixed:
				2562	case ARM::VST1q64wb_register:
				2563	case ARM::VST1q8wb_fixed:
				2564	case ARM::VST1q8wb_register:
				2565	case ARM::VST2d16:
				2566	case ARM::VST2d32:
				2567	case ARM::VST2d8:
				2568	case ARM::VST2d16wb_fixed:
				2569	case ARM::VST2d16wb_register:
				2570	case ARM::VST2d32wb_fixed:
				2571	case ARM::VST2d32wb_register:
				2572	case ARM::VST2d8wb_fixed:
				2573	case ARM::VST2d8wb_register:
				2574	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2575	return MCDisassembler::Fail;
				2576	break;
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	2577	case ARM::VST2b16:
				2578	case ARM::VST2b32:
				2579	case ARM::VST2b8:
				2580	case ARM::VST2b16wb_fixed:
				2581	case ARM::VST2b16wb_register:
				2582	case ARM::VST2b32wb_fixed:
				2583	case ARM::VST2b32wb_register:
				2584	case ARM::VST2b8wb_fixed:
				2585	case ARM::VST2b8wb_register:
				2586	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2587	return MCDisassembler::Fail;
				2588	break;
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2589	default:
				2590	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2591	return MCDisassembler::Fail;
				2592	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2593
				2594	// Second input register
				2595	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2596	case ARM::VST3d8:
				2597	case ARM::VST3d16:
				2598	case ARM::VST3d32:
				2599	case ARM::VST3d8_UPD:
				2600	case ARM::VST3d16_UPD:
				2601	case ARM::VST3d32_UPD:
				2602	case ARM::VST4d8:
				2603	case ARM::VST4d16:
				2604	case ARM::VST4d32:
				2605	case ARM::VST4d8_UPD:
				2606	case ARM::VST4d16_UPD:
				2607	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2608	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2609	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2610	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2611	case ARM::VST3q8:
				2612	case ARM::VST3q16:
				2613	case ARM::VST3q32:
				2614	case ARM::VST3q8_UPD:
				2615	case ARM::VST3q16_UPD:
				2616	case ARM::VST3q32_UPD:
				2617	case ARM::VST4q8:
				2618	case ARM::VST4q16:
				2619	case ARM::VST4q32:
				2620	case ARM::VST4q8_UPD:
				2621	case ARM::VST4q16_UPD:
				2622	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2623	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2624	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2625	break;
				2626	default:
				2627	break;
				2628	}
				2629
				2630	// Third input register
				2631	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2632	case ARM::VST3d8:
				2633	case ARM::VST3d16:
				2634	case ARM::VST3d32:
				2635	case ARM::VST3d8_UPD:
				2636	case ARM::VST3d16_UPD:
				2637	case ARM::VST3d32_UPD:
				2638	case ARM::VST4d8:
				2639	case ARM::VST4d16:
				2640	case ARM::VST4d32:
				2641	case ARM::VST4d8_UPD:
				2642	case ARM::VST4d16_UPD:
				2643	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2644	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2645	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2646	break;
				2647	case ARM::VST3q8:
				2648	case ARM::VST3q16:
				2649	case ARM::VST3q32:
				2650	case ARM::VST3q8_UPD:
				2651	case ARM::VST3q16_UPD:
				2652	case ARM::VST3q32_UPD:
				2653	case ARM::VST4q8:
				2654	case ARM::VST4q16:
				2655	case ARM::VST4q32:
				2656	case ARM::VST4q8_UPD:
				2657	case ARM::VST4q16_UPD:
				2658	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2659	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2660	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2661	break;
				2662	default:
				2663	break;
				2664	}
				2665
				2666	// Fourth input register
				2667	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2668	case ARM::VST4d8:
				2669	case ARM::VST4d16:
				2670	case ARM::VST4d32:
				2671	case ARM::VST4d8_UPD:
				2672	case ARM::VST4d16_UPD:
				2673	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2674	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2675	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2676	break;
				2677	case ARM::VST4q8:
				2678	case ARM::VST4q16:
				2679	case ARM::VST4q32:
				2680	case ARM::VST4q8_UPD:
				2681	case ARM::VST4q16_UPD:
				2682	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2683	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2684	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2685	break;
				2686	default:
				2687	break;
				2688	}
				2689
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2690	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2691	}
				2692
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2693	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2694	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2695	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2696
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2697	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2698	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2699	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2700	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2701	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2702	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2703
Tim Northover	24b9f25	2012-09-06 15:27:12 +0000	[diff] [blame]	2704	if (size == 0 && align == 1)
				2705	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2706	align *= (1 << size);
				2707
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2708	switch (Inst.getOpcode()) {
				2709	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2710	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2711	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2712	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2713	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2714	return MCDisassembler::Fail;
				2715	break;
				2716	default:
				2717	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2718	return MCDisassembler::Fail;
				2719	break;
				2720	}
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2721	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2722	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2723	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2724	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2725
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2726	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2727	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2728	Inst.addOperand(MCOperand::CreateImm(align));
				2729
Jim Grosbach	096334e	2011-11-30 19:35:44 +0000	[diff] [blame]	2730	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2731	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2732	// increment and we need to add the register operand to the instruction.
				2733	if (Rm != 0xD && Rm != 0xF &&
				2734	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2735	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2736
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2737	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2738	}
				2739
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2740	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2741	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2742	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2743
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2744	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2745	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2746	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2747	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2748	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2749	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2750	align = 2size;
				2751
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2752	switch (Inst.getOpcode()) {
				2753	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2754	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2755	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2756	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2757	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2758	return MCDisassembler::Fail;
				2759	break;
Jim Grosbach	4d0983a	2012-03-06 23:10:38 +0000	[diff] [blame]	2760	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2761	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2762	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2763	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2764	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2765	return MCDisassembler::Fail;
				2766	break;
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2767	default:
				2768	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2769	return MCDisassembler::Fail;
				2770	break;
				2771	}
Kevin Enderby	158c8a4	2012-03-06 18:33:12 +0000	[diff] [blame]	2772
				2773	if (Rm != 0xF)
				2774	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2775
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2776	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2777	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2778	Inst.addOperand(MCOperand::CreateImm(align));
				2779
Kevin Enderby	c5a2a33	2012-04-17 00:49:27 +0000	[diff] [blame]	2780	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2781	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2782	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2783	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2784
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2785	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2786	}
				2787
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2788	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2789	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2790	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2791
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2792	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2793	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2794	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2795	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2796	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2797
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2798	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2799	return MCDisassembler::Fail;
				2800	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2801	return MCDisassembler::Fail;
				2802	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2803	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2804	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2805	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2806	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2807	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2808
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2809	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2810	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2811	Inst.addOperand(MCOperand::CreateImm(0));
				2812
				2813	if (Rm == 0xD)
				2814	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2815	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2816	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2817	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2818	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2819
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2820	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2821	}
				2822
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2823	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2824	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2825	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2826
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2827	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2828	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2829	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2830	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2831	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2832	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2833	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2834
				2835	if (size == 0x3) {
Tim Northover	24b9f25	2012-09-06 15:27:12 +0000	[diff] [blame]	2836	if (align == 0)
				2837	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2838	size = 4;
				2839	align = 16;
				2840	} else {
				2841	if (size == 2) {
				2842	size = 1 << size;
				2843	align *= 8;
				2844	} else {
				2845	size = 1 << size;
				2846	align = 4size;
				2847	}
				2848	}
				2849
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2850	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2851	return MCDisassembler::Fail;
				2852	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2853	return MCDisassembler::Fail;
				2854	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2855	return MCDisassembler::Fail;
				2856	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2857	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2858	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2859	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2860	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2861	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2862
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2863	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2864	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2865	Inst.addOperand(MCOperand::CreateImm(align));
				2866
				2867	if (Rm == 0xD)
				2868	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2869	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2870	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2871	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2872	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2873
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2874	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2875	}
				2876
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2877	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2878	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2879	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2880	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2881
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2882	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2883	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2884	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				2885	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				2886	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				2887	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				2888	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				2889	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2890
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2891	if (Q) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2892	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2893	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2894	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2895	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2896	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2897	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2898
				2899	Inst.addOperand(MCOperand::CreateImm(imm));
				2900
				2901	switch (Inst.getOpcode()) {
				2902	case ARM::VORRiv4i16:
				2903	case ARM::VORRiv2i32:
				2904	case ARM::VBICiv4i16:
				2905	case ARM::VBICiv2i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2906	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2907	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2908	break;
				2909	case ARM::VORRiv8i16:
				2910	case ARM::VORRiv4i32:
				2911	case ARM::VBICiv8i16:
				2912	case ARM::VBICiv4i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2913	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2914	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2915	break;
				2916	default:
				2917	break;
				2918	}
				2919
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2920	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2921	}
				2922
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2923	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2924	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2925	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2926
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2927	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2928	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2929	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2930	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				2931	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2932
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2933	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2934	return MCDisassembler::Fail;
				2935	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2936	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2937	Inst.addOperand(MCOperand::CreateImm(8 << size));
				2938
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2939	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2940	}
				2941
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2942	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2943	uint64_t Address, const void *Decoder) {
				2944	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2945	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2946	}
				2947
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2948	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2949	uint64_t Address, const void *Decoder) {
				2950	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2951	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2952	}
				2953
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2954	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2955	uint64_t Address, const void *Decoder) {
				2956	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2957	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2958	}
				2959
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2960	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2961	uint64_t Address, const void *Decoder) {
				2962	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2963	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2964	}
				2965
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2966	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2967	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2968	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2969
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2970	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2971	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2972	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2973	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				2974	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2975	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				2976	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2977
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2978	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2979	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2980	if (op) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2981	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2982	return MCDisassembler::Fail; // Writeback
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2983	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2984
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2985	switch (Inst.getOpcode()) {
				2986	case ARM::VTBL2:
				2987	case ARM::VTBX2:
				2988	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				2989	return MCDisassembler::Fail;
				2990	break;
				2991	default:
				2992	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				2993	return MCDisassembler::Fail;
				2994	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2995
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2996	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2997	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2998
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2999	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3000	}
				3001
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3002	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3003	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3004	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3005
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3006	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3007	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3008
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3009	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3010	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3011
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3012	switch(Inst.getOpcode()) {
Owen Anderson	1af7f72	2011-08-26 19:39:26 +0000	[diff] [blame]	3013	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3014	return MCDisassembler::Fail;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3015	case ARM::tADR:
Owen Anderson	9f7e831	2011-08-26 21:47:57 +0000	[diff] [blame]	3016	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3017	case ARM::tADDrSPi:
				3018	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3019	break;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3020	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3021
				3022	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3023	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3024	}
				3025
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3026	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3027	uint64_t Address, const void *Decoder) {
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3028	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3029	true, 2, Inst, Decoder))
				3030	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3031	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3032	}
				3033
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3034	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3035	uint64_t Address, const void *Decoder) {
Kevin Enderby	3610a15	2012-05-04 22:09:52 +0000	[diff] [blame]	3036	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3037	true, 4, Inst, Decoder))
				3038	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3039	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3040	}
				3041
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3042	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3043	uint64_t Address, const void *Decoder) {
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3044	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
				3045	true, 2, Inst, Decoder))
				3046	Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3047	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3048	}
				3049
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3050	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3051	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3052	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3053
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3054	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3055	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3056
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3057	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3058	return MCDisassembler::Fail;
				3059	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3060	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3061
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3062	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3063	}
				3064
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3065	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3066	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3067	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3068
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3069	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3070	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3071
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3072	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3073	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3074	Inst.addOperand(MCOperand::CreateImm(imm));
				3075
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3076	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3077	}
				3078
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3079	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3080	uint64_t Address, const void *Decoder) {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	3081	unsigned imm = Val << 2;
				3082
				3083	Inst.addOperand(MCOperand::CreateImm(imm));
				3084	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3085
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3086	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3087	}
				3088
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3089	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3090	uint64_t Address, const void *Decoder) {
				3091	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b113ec5	2011-08-22 17:56:58 +0000	[diff] [blame]	3092	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3093
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3094	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3095	}
				3096
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3097	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3098	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3099	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3100
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3101	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3102	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3103	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3104
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3105	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3106	return MCDisassembler::Fail;
				3107	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3108	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3109	Inst.addOperand(MCOperand::CreateImm(imm));
				3110
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3111	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3112	}
				3113
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3114	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3115	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3116	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3117
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	3118	switch (Inst.getOpcode()) {
				3119	case ARM::t2PLDs:
				3120	case ARM::t2PLDWs:
				3121	case ARM::t2PLIs:
				3122	break;
				3123	default: {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3124	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson	31d485e	2011-09-23 21:07:25 +0000	[diff] [blame]	3125	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3126	return MCDisassembler::Fail;
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	3127	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3128	}
				3129
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3130	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3131	if (Rn == 0xF) {
				3132	switch (Inst.getOpcode()) {
				3133	case ARM::t2LDRBs:
				3134	Inst.setOpcode(ARM::t2LDRBpci);
				3135	break;
				3136	case ARM::t2LDRHs:
				3137	Inst.setOpcode(ARM::t2LDRHpci);
				3138	break;
				3139	case ARM::t2LDRSHs:
				3140	Inst.setOpcode(ARM::t2LDRSHpci);
				3141	break;
				3142	case ARM::t2LDRSBs:
				3143	Inst.setOpcode(ARM::t2LDRSBpci);
				3144	break;
				3145	case ARM::t2PLDs:
				3146	Inst.setOpcode(ARM::t2PLDi12);
				3147	Inst.addOperand(MCOperand::CreateReg(ARM::PC));
				3148	break;
				3149	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3150	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3151	}
				3152
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3153	int imm = fieldFromInstruction(Insn, 0, 12);
				3154	if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3155	Inst.addOperand(MCOperand::CreateImm(imm));
				3156
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3157	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3158	}
				3159
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3160	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3161	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3162	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3163	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3164	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3165
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3166	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3167	}
				3168
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3169	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3170	uint64_t Address, const void *Decoder) {
Jiangning Liu	fd652df	2012-08-02 08:29:50 +0000	[diff] [blame]	3171	if (Val == 0)
				3172	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3173	else {
				3174	int imm = Val & 0xFF;
				3175
				3176	if (!(Val & 0x100)) imm *= -1;
Richard Smith	1144af3	2012-08-24 23:29:28 +0000	[diff] [blame]	3177	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	fd652df	2012-08-02 08:29:50 +0000	[diff] [blame]	3178	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3179
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3180	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3181	}
				3182
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3183	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3184	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3185	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3186
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3187	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3188	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3189
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3190	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3191	return MCDisassembler::Fail;
				3192	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3193	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3194
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3195	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3196	}
				3197
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3198	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	3199	uint64_t Address, const void *Decoder) {
				3200	DecodeStatus S = MCDisassembler::Success;
				3201
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3202	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3203	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	3204
				3205	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3206	return MCDisassembler::Fail;
				3207
				3208	Inst.addOperand(MCOperand::CreateImm(imm));
				3209
				3210	return S;
				3211	}
				3212
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3213	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3214	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3215	int imm = Val & 0xFF;
Owen Anderson	705b48f	2011-09-16 21:08:33 +0000	[diff] [blame]	3216	if (Val == 0)
				3217	imm = INT32_MIN;
				3218	else if (!(Val & 0x100))
				3219	imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3220	Inst.addOperand(MCOperand::CreateImm(imm));
				3221
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3222	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3223	}
				3224
				3225
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3226	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3227	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3228	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3229
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3230	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3231	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3232
				3233	// Some instructions always use an additive offset.
				3234	switch (Inst.getOpcode()) {
				3235	case ARM::t2LDRT:
				3236	case ARM::t2LDRBT:
				3237	case ARM::t2LDRHT:
				3238	case ARM::t2LDRSBT:
				3239	case ARM::t2LDRSHT:
Owen Anderson	ecd1c55	2011-09-19 18:07:10 +0000	[diff] [blame]	3240	case ARM::t2STRT:
				3241	case ARM::t2STRBT:
				3242	case ARM::t2STRHT:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3243	imm \|= 0x100;
				3244	break;
				3245	default:
				3246	break;
				3247	}
				3248
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3249	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3250	return MCDisassembler::Fail;
				3251	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3252	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3253
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3254	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3255	}
				3256
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3257	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3258	uint64_t Address, const void *Decoder) {
				3259	DecodeStatus S = MCDisassembler::Success;
				3260
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3261	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3262	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3263	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3264	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3265	addr \|= Rn << 9;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3266	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3267
				3268	if (!load) {
				3269	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3270	return MCDisassembler::Fail;
				3271	}
				3272
Owen Anderson	e4f2df9	2011-09-16 22:42:36 +0000	[diff] [blame]	3273	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3274	return MCDisassembler::Fail;
				3275
				3276	if (load) {
				3277	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3278	return MCDisassembler::Fail;
				3279	}
				3280
				3281	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3282	return MCDisassembler::Fail;
				3283
				3284	return S;
				3285	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3286
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3287	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3288	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3289	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3290
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3291	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3292	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3293
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3294	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3295	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3296	Inst.addOperand(MCOperand::CreateImm(imm));
				3297
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3298	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3299	}
				3300
				3301
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3302	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3303	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3304	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3305
				3306	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3307	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3308	Inst.addOperand(MCOperand::CreateImm(imm));
				3309
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3310	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3311	}
				3312
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3313	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3314	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3315	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3316
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3317	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3318	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3319	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3320
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3321	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3322	return MCDisassembler::Fail;
Jim Grosbach	bb32f1d	2012-04-27 23:51:33 +0000	[diff] [blame]	3323	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3324	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3325	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3326	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3327	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3328
				3329	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3330	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3331	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3332	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3333	}
				3334
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3335	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3336	}
				3337
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3338	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3339	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3340	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3341	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3342
				3343	Inst.addOperand(MCOperand::CreateImm(imod));
				3344	Inst.addOperand(MCOperand::CreateImm(flags));
				3345
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3346	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3347	}
				3348
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3349	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3350	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3351	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3352	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3353	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3354
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	3355	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3356	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3357	Inst.addOperand(MCOperand::CreateImm(add));
				3358
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3359	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3360	}
				3361
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3362	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3363	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3364	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3365	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3366	// the encoded instruction. So here change to I1 and I2 values via:
				3367	// I1 = NOT(J1 EOR S);
				3368	// I2 = NOT(J2 EOR S);
				3369	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3370	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3371	unsigned S = (Val >> 23) & 1;
				3372	unsigned J1 = (Val >> 22) & 1;
				3373	unsigned J2 = (Val >> 21) & 1;
				3374	unsigned I1 = !(J1 ^ S);
				3375	unsigned I2 = !(J2 ^ S);
				3376	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3377	int imm32 = SignExtend32<25>(tmp << 1);
				3378
Jim Grosbach	01817c3	2011-10-20 17:28:20 +0000	[diff] [blame]	3379	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3380	(Address & ~2u) + imm32 + 4,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	3381	true, 4, Inst, Decoder))
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3382	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3383	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3384	}
				3385
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3386	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3387	uint64_t Address, const void *Decoder) {
				3388	if (Val == 0xA \|\| Val == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3389	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3390
				3391	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3392	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3393	}
				3394
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3395	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3396	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	3397	uint64_t Address, const void *Decoder) {
				3398	DecodeStatus S = MCDisassembler::Success;
				3399
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3400	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3401	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	3402
				3403	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3404	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3405	return MCDisassembler::Fail;
				3406	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3407	return MCDisassembler::Fail;
				3408	return S;
				3409	}
				3410
				3411	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3412	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3413	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3414	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3415
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3416	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3417	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3418	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3419	switch (opc) {
				3420	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3421	return MCDisassembler::Fail;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3422	case 0xf3bf8f4:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3423	Inst.setOpcode(ARM::t2DSB);
				3424	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3425	case 0xf3bf8f5:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3426	Inst.setOpcode(ARM::t2DMB);
				3427	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3428	case 0xf3bf8f6:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3429	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	6de3c6f	2011-09-07 17:55:19 +0000	[diff] [blame]	3430	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3431	}
				3432
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3433	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3434	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3435	}
				3436
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3437	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3438	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3439	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3440	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3441	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3442
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3443	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3444	return MCDisassembler::Fail;
				3445	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3446	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3447
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3448	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3449	}
				3450
				3451	// Decode a shifted immediate operand. These basically consist
				3452	// of an 8-bit value, and a 4-bit directive that specifies either
				3453	// a splat operation or a rotation.
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3454	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3455	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3456	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3457	if (ctrl == 0) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3458	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3459	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3460	switch (byte) {
				3461	case 0:
				3462	Inst.addOperand(MCOperand::CreateImm(imm));
				3463	break;
				3464	case 1:
				3465	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3466	break;
				3467	case 2:
				3468	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3469	break;
				3470	case 3:
				3471	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3472	(imm << 8) \| imm));
				3473	break;
				3474	}
				3475	} else {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3476	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3477	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3478	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3479	Inst.addOperand(MCOperand::CreateImm(imm));
				3480	}
				3481
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3482	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3483	}
				3484
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3485	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3486	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3487	uint64_t Address, const void *Decoder){
Richard Barton	c8f2fcc	2012-06-06 09:12:53 +0000	[diff] [blame]	3488	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3489	true, 2, Inst, Decoder))
Richard Barton	c8f2fcc	2012-06-06 09:12:53 +0000	[diff] [blame]	3490	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3491	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3492	}
				3493
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3494	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3495	uint64_t Address, const void *Decoder){
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3496	// Val is passed in as S:J1:J2:imm10:imm11
				3497	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3498	// the encoded instruction. So here change to I1 and I2 values via:
				3499	// I1 = NOT(J1 EOR S);
				3500	// I2 = NOT(J2 EOR S);
				3501	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3502	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3503	unsigned S = (Val >> 23) & 1;
				3504	unsigned J1 = (Val >> 22) & 1;
				3505	unsigned J2 = (Val >> 21) & 1;
				3506	unsigned I1 = !(J1 ^ S);
				3507	unsigned I2 = !(J2 ^ S);
				3508	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3509	int imm32 = SignExtend32<25>(tmp << 1);
				3510
				3511	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	3512	true, 4, Inst, Decoder))
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3513	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3514	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3515	}
				3516
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3517	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3518	uint64_t Address, const void *Decoder) {
Jiangning Liu	c1b7ca5	2012-08-02 08:21:27 +0000	[diff] [blame]	3519	if (Val & ~0xf)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3520	return MCDisassembler::Fail;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3521
				3522	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3523	return MCDisassembler::Success;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3524	}
				3525
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3526	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3527	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3528	if (!Val) return MCDisassembler::Fail;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3529	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3530	return MCDisassembler::Success;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3531	}
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3532
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3533	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3534	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3535	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3536
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3537	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3538	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3539	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3540
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3541	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3542
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3543	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3544	return MCDisassembler::Fail;
				3545	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3546	return MCDisassembler::Fail;
				3547	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3548	return MCDisassembler::Fail;
				3549	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3550	return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3551
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3552	return S;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3553	}
				3554
				3555
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3556	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3557	uint64_t Address, const void *Decoder){
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3558	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3559
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3560	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3561	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				3562	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3563	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3564
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3565	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				3566	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3567
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3568	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
				3569	if (Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1) return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3570
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3571	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3572	return MCDisassembler::Fail;
				3573	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3574	return MCDisassembler::Fail;
				3575	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3576	return MCDisassembler::Fail;
				3577	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3578	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3579
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3580	return S;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3581	}
				3582
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3583	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3584	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3585	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3586
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3587	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3588	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3589	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3590	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3591	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3592	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3593
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3594	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3595
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3596	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3597	return MCDisassembler::Fail;
				3598	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3599	return MCDisassembler::Fail;
				3600	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3601	return MCDisassembler::Fail;
				3602	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3603	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3604
				3605	return S;
				3606	}
				3607
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3608	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3609	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3610	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3611
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3612	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3613	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3614	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3615	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3616	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3617	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				3618	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3619
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3620	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				3621	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3622
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3623	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3624	return MCDisassembler::Fail;
				3625	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3626	return MCDisassembler::Fail;
				3627	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3628	return MCDisassembler::Fail;
				3629	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3630	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3631
				3632	return S;
				3633	}
				3634
				3635
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3636	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3637	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3638	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3639
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3640	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3641	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3642	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3643	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3644	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3645	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3646
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3647	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3648
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3649	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3650	return MCDisassembler::Fail;
				3651	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3652	return MCDisassembler::Fail;
				3653	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3654	return MCDisassembler::Fail;
				3655	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3656	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3657
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3658	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3659	}
				3660
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3661	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3662	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3663	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3664
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3665	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3666	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3667	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3668	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3669	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3670	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3671
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3672	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3673
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3674	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3675	return MCDisassembler::Fail;
				3676	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3677	return MCDisassembler::Fail;
				3678	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3679	return MCDisassembler::Fail;
				3680	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3681	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3682
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3683	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3684	}
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3685
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3686	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3687	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3688	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3689
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3690	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3691	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3692	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3693	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3694	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3695
				3696	unsigned align = 0;
				3697	unsigned index = 0;
				3698	switch (size) {
				3699	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3700	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3701	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3702	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3703	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3704	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3705	break;
				3706	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3707	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3708	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3709	index = fieldFromInstruction(Insn, 6, 2);
				3710	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3711	align = 2;
				3712	break;
				3713	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3714	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3715	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3716	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	3717
				3718	switch (fieldFromInstruction(Insn, 4, 2)) {
				3719	case 0 :
				3720	align = 0; break;
				3721	case 3:
				3722	align = 4; break;
				3723	default:
				3724	return MCDisassembler::Fail;
				3725	}
				3726	break;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3727	}
				3728
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3729	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3730	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3731	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3732	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3733	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3734	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3735	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3736	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3737	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3738	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3739	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3740	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3741	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3742	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3743	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3744	}
				3745
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3746	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3747	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3748	Inst.addOperand(MCOperand::CreateImm(index));
				3749
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3750	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3751	}
				3752
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3753	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3754	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3755	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3756
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3757	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3758	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3759	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3760	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3761	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3762
				3763	unsigned align = 0;
				3764	unsigned index = 0;
				3765	switch (size) {
				3766	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3767	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3768	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3769	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3770	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3771	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3772	break;
				3773	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3774	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3775	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3776	index = fieldFromInstruction(Insn, 6, 2);
				3777	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3778	align = 2;
				3779	break;
				3780	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3781	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3782	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3783	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	3784
				3785	switch (fieldFromInstruction(Insn, 4, 2)) {
				3786	case 0:
				3787	align = 0; break;
				3788	case 3:
				3789	align = 4; break;
				3790	default:
				3791	return MCDisassembler::Fail;
				3792	}
				3793	break;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3794	}
				3795
				3796	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3797	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3798	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3799	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3800	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3801	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3802	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3803	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3804	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3805	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3806	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3807	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3808	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3809	}
				3810
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3811	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3812	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3813	Inst.addOperand(MCOperand::CreateImm(index));
				3814
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3815	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3816	}
				3817
				3818
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3819	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3820	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3821	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3822
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3823	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3824	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3825	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3826	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3827	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3828
				3829	unsigned align = 0;
				3830	unsigned index = 0;
				3831	unsigned inc = 1;
				3832	switch (size) {
				3833	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3834	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3835	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3836	index = fieldFromInstruction(Insn, 5, 3);
				3837	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3838	align = 2;
				3839	break;
				3840	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3841	index = fieldFromInstruction(Insn, 6, 2);
				3842	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3843	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3844	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3845	inc = 2;
				3846	break;
				3847	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3848	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3849	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3850	index = fieldFromInstruction(Insn, 7, 1);
				3851	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3852	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3853	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3854	inc = 2;
				3855	break;
				3856	}
				3857
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3858	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3859	return MCDisassembler::Fail;
				3860	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3861	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3862	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3863	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3864	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3865	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3866	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3867	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3868	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3869	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3870	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3871	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3872	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3873	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3874	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3875	}
				3876
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3877	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3878	return MCDisassembler::Fail;
				3879	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3880	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3881	Inst.addOperand(MCOperand::CreateImm(index));
				3882
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3883	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3884	}
				3885
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3886	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3887	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3888	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3889
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3890	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3891	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3892	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3893	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3894	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3895
				3896	unsigned align = 0;
				3897	unsigned index = 0;
				3898	unsigned inc = 1;
				3899	switch (size) {
				3900	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3901	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3902	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3903	index = fieldFromInstruction(Insn, 5, 3);
				3904	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3905	align = 2;
				3906	break;
				3907	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3908	index = fieldFromInstruction(Insn, 6, 2);
				3909	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3910	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3911	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3912	inc = 2;
				3913	break;
				3914	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3915	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3916	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3917	index = fieldFromInstruction(Insn, 7, 1);
				3918	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3919	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3920	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3921	inc = 2;
				3922	break;
				3923	}
				3924
				3925	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3926	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3927	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3928	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3929	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3930	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3931	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3932	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3933	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3934	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3935	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3936	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3937	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3938	}
				3939
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3940	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3941	return MCDisassembler::Fail;
				3942	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3943	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3944	Inst.addOperand(MCOperand::CreateImm(index));
				3945
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3946	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3947	}
				3948
				3949
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3950	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3951	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3952	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3953
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3954	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3955	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3956	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3957	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3958	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3959
				3960	unsigned align = 0;
				3961	unsigned index = 0;
				3962	unsigned inc = 1;
				3963	switch (size) {
				3964	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3965	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3966	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3967	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3968	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3969	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3970	break;
				3971	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3972	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3973	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3974	index = fieldFromInstruction(Insn, 6, 2);
				3975	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3976	inc = 2;
				3977	break;
				3978	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3979	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3980	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3981	index = fieldFromInstruction(Insn, 7, 1);
				3982	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3983	inc = 2;
				3984	break;
				3985	}
				3986
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3987	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3988	return MCDisassembler::Fail;
				3989	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3990	return MCDisassembler::Fail;
				3991	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3992	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3993
				3994	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3995	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3996	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3997	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3998	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3999	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4000	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4001	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4002	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4003	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4004	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4005	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4006	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4007	}
				4008
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4009	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4010	return MCDisassembler::Fail;
				4011	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4012	return MCDisassembler::Fail;
				4013	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4014	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4015	Inst.addOperand(MCOperand::CreateImm(index));
				4016
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4017	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4018	}
				4019
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4020	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4021	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4022	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4023
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4024	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4025	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4026	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4027	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4028	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4029
				4030	unsigned align = 0;
				4031	unsigned index = 0;
				4032	unsigned inc = 1;
				4033	switch (size) {
				4034	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4035	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4036	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4037	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4038	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4039	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4040	break;
				4041	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4042	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4043	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4044	index = fieldFromInstruction(Insn, 6, 2);
				4045	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4046	inc = 2;
				4047	break;
				4048	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4049	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4050	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4051	index = fieldFromInstruction(Insn, 7, 1);
				4052	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4053	inc = 2;
				4054	break;
				4055	}
				4056
				4057	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4058	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4059	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4060	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4061	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4062	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4063	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4064	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4065	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4066	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4067	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4068	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4069	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4070	}
				4071
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4072	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4073	return MCDisassembler::Fail;
				4074	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4075	return MCDisassembler::Fail;
				4076	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4077	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4078	Inst.addOperand(MCOperand::CreateImm(index));
				4079
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4080	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4081	}
				4082
				4083
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4084	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4085	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4086	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4087
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4088	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4089	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4090	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4091	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4092	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4093
				4094	unsigned align = 0;
				4095	unsigned index = 0;
				4096	unsigned inc = 1;
				4097	switch (size) {
				4098	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4099	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4100	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4101	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4102	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4103	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4104	break;
				4105	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4106	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4107	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4108	index = fieldFromInstruction(Insn, 6, 2);
				4109	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4110	inc = 2;
				4111	break;
				4112	case 2:
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	4113	switch (fieldFromInstruction(Insn, 4, 2)) {
				4114	case 0:
				4115	align = 0; break;
				4116	case 3:
				4117	return MCDisassembler::Fail;
				4118	default:
				4119	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4120	}
				4121
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4122	index = fieldFromInstruction(Insn, 7, 1);
				4123	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4124	inc = 2;
				4125	break;
				4126	}
				4127
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4128	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4129	return MCDisassembler::Fail;
				4130	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4131	return MCDisassembler::Fail;
				4132	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4133	return MCDisassembler::Fail;
				4134	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4135	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4136
				4137	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4138	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4139	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4140	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4141	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4142	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4143	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4144	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4145	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4146	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4147	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4148	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4149	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4150	}
				4151
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4152	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4153	return MCDisassembler::Fail;
				4154	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4155	return MCDisassembler::Fail;
				4156	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4157	return MCDisassembler::Fail;
				4158	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4159	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4160	Inst.addOperand(MCOperand::CreateImm(index));
				4161
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4162	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4163	}
				4164
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4165	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4166	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4167	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4168
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4169	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4170	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4171	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4172	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4173	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4174
				4175	unsigned align = 0;
				4176	unsigned index = 0;
				4177	unsigned inc = 1;
				4178	switch (size) {
				4179	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4180	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4181	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4182	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4183	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4184	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4185	break;
				4186	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4187	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4188	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4189	index = fieldFromInstruction(Insn, 6, 2);
				4190	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4191	inc = 2;
				4192	break;
				4193	case 2:
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	4194	switch (fieldFromInstruction(Insn, 4, 2)) {
				4195	case 0:
				4196	align = 0; break;
				4197	case 3:
				4198	return MCDisassembler::Fail;
				4199	default:
				4200	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4201	}
				4202
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4203	index = fieldFromInstruction(Insn, 7, 1);
				4204	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4205	inc = 2;
				4206	break;
				4207	}
				4208
				4209	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4210	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4211	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4212	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4213	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4214	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4215	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4216	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4217	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4218	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4219	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4220	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4221	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4222	}
				4223
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4224	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4225	return MCDisassembler::Fail;
				4226	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4227	return MCDisassembler::Fail;
				4228	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4229	return MCDisassembler::Fail;
				4230	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4231	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4232	Inst.addOperand(MCOperand::CreateImm(index));
				4233
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4234	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4235	}
				4236
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4237	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4238	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4239	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4240	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4241	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4242	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4243	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4244	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4245
				4246	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4247	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4248
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4249	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4250	return MCDisassembler::Fail;
				4251	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4252	return MCDisassembler::Fail;
				4253	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4254	return MCDisassembler::Fail;
				4255	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4256	return MCDisassembler::Fail;
				4257	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4258	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4259
				4260	return S;
				4261	}
				4262
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4263	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4264	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4265	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4266	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4267	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4268	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4269	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4270	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4271
				4272	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4273	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4274
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4275	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4276	return MCDisassembler::Fail;
				4277	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4278	return MCDisassembler::Fail;
				4279	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4280	return MCDisassembler::Fail;
				4281	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4282	return MCDisassembler::Fail;
				4283	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4284	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4285
				4286	return S;
				4287	}
Owen Anderson	8e1e60b	2011-08-22 23:44:04 +0000	[diff] [blame]	4288
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4289	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4290	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4291	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4292	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4293	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4294
				4295	if (pred == 0xF) {
				4296	pred = 0xE;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4297	S = MCDisassembler::SoftFail;
Owen Anderson	e234d02	2011-08-24 17:21:43 +0000	[diff] [blame]	4298	}
				4299
Richard Barton	4d2f077	2012-04-27 08:42:59 +0000	[diff] [blame]	4300	if (mask == 0x0) {
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4301	mask \|= 0x8;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4302	S = MCDisassembler::SoftFail;
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	4303	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4304
				4305	Inst.addOperand(MCOperand::CreateImm(pred));
				4306	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	4307	return S;
				4308	}
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4309
				4310	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4311	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4312	uint64_t Address, const void *Decoder) {
				4313	DecodeStatus S = MCDisassembler::Success;
				4314
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4315	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4316	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4317	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4318	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4319	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4320	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4321	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4322	bool writeback = (W == 1) \| (P == 0);
				4323
				4324	addr \|= (U << 8) \| (Rn << 9);
				4325
				4326	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4327	Check(S, MCDisassembler::SoftFail);
				4328	if (Rt == Rt2)
				4329	Check(S, MCDisassembler::SoftFail);
				4330
				4331	// Rt
				4332	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4333	return MCDisassembler::Fail;
				4334	// Rt2
				4335	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4336	return MCDisassembler::Fail;
				4337	// Writeback operand
				4338	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4339	return MCDisassembler::Fail;
				4340	// addr
				4341	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4342	return MCDisassembler::Fail;
				4343
				4344	return S;
				4345	}
				4346
				4347	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4348	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4349	uint64_t Address, const void *Decoder) {
				4350	DecodeStatus S = MCDisassembler::Success;
				4351
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4352	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4353	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4354	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4355	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4356	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4357	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4358	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4359	bool writeback = (W == 1) \| (P == 0);
				4360
				4361	addr \|= (U << 8) \| (Rn << 9);
				4362
				4363	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4364	Check(S, MCDisassembler::SoftFail);
				4365
				4366	// Writeback operand
				4367	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4368	return MCDisassembler::Fail;
				4369	// Rt
				4370	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4371	return MCDisassembler::Fail;
				4372	// Rt2
				4373	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4374	return MCDisassembler::Fail;
				4375	// addr
				4376	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4377	return MCDisassembler::Fail;
				4378
				4379	return S;
				4380	}
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4381
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4382	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4383	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4384	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4385	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4386	if (sign1 != sign2) return MCDisassembler::Fail;
				4387
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4388	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4389	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4390	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4391	Val \|= sign1 << 12;
				4392	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4393
				4394	return MCDisassembler::Success;
				4395	}
				4396
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4397	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	0afa009	2011-09-26 21:06:22 +0000	[diff] [blame]	4398	uint64_t Address,
				4399	const void *Decoder) {
				4400	DecodeStatus S = MCDisassembler::Success;
				4401
				4402	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4403	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4404	Inst.addOperand(MCOperand::CreateImm(Val));
				4405	return S;
				4406	}
				4407
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4408	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4409	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4410	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4411	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4412	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4413	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4414
				4415	if (pred == 0xF)
				4416	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4417
				4418	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	35ee7d2	2012-04-18 14:18:57 +0000	[diff] [blame]	4419
				4420	if (Rt == Rn \|\| Rn == Rt2)
				4421	S = MCDisassembler::SoftFail;
				4422
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4423	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4424	return MCDisassembler::Fail;
				4425	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4426	return MCDisassembler::Fail;
				4427	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4428	return MCDisassembler::Fail;
				4429	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4430	return MCDisassembler::Fail;
				4431
				4432	return S;
				4433	}
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4434
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4435	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4436	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4437	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4438	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4439	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4440	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4441	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4442	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4443
				4444	DecodeStatus S = MCDisassembler::Success;
				4445
				4446	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	22925d9	2011-11-15 20:30:41 +0000	[diff] [blame]	4447	if (!(imm & 0x38) && cmode == 0xF) {
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4448	Inst.setOpcode(ARM::VMOVv2f32);
				4449	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4450	}
				4451
				4452	if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
				4453
				4454	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4455	return MCDisassembler::Fail;
				4456	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4457	return MCDisassembler::Fail;
				4458	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4459
				4460	return S;
				4461	}
				4462
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4463	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4464	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4465	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4466	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4467	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4468	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4469	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4470	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4471
				4472	DecodeStatus S = MCDisassembler::Success;
				4473
				4474	// VMOVv4f32 is ambiguous with these decodings.
				4475	if (!(imm & 0x38) && cmode == 0xF) {
				4476	Inst.setOpcode(ARM::VMOVv4f32);
				4477	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4478	}
				4479
				4480	if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
				4481
				4482	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				4483	return MCDisassembler::Fail;
				4484	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				4485	return MCDisassembler::Fail;
				4486	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4487
				4488	return S;
				4489	}
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4490
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4491	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4492	uint64_t Address, const void *Decoder) {
				4493	DecodeStatus S = MCDisassembler::Success;
				4494
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4495	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				4496	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4497	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				4498	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				4499	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4500
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4501	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4502	S = MCDisassembler::SoftFail;
				4503
				4504	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4505	return MCDisassembler::Fail;
				4506	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4507	return MCDisassembler::Fail;
				4508	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				4509	return MCDisassembler::Fail;
				4510	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				4511	return MCDisassembler::Fail;
				4512	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				4513	return MCDisassembler::Fail;
				4514
				4515	return S;
				4516	}
				4517
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	4518	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				4519	uint64_t Address, const void *Decoder) {
				4520
				4521	DecodeStatus S = MCDisassembler::Success;
				4522
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4523	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				4524	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				4525	unsigned cop = fieldFromInstruction(Val, 8, 4);
				4526	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4527	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	4528
				4529	if ((cop & ~0x1) == 0xa)
				4530	return MCDisassembler::Fail;
				4531
				4532	if (Rt == Rt2)
				4533	S = MCDisassembler::SoftFail;
				4534
				4535	Inst.addOperand(MCOperand::CreateImm(cop));
				4536	Inst.addOperand(MCOperand::CreateImm(opc1));
				4537	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4538	return MCDisassembler::Fail;
				4539	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4540	return MCDisassembler::Fail;
				4541	Inst.addOperand(MCOperand::CreateImm(CRm));
				4542
				4543	return S;
				4544	}
				4545