Blame - lib/Target/ARM/Disassembler/ARMDisassembler.cpp - platform/external/llvm

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Jia Liu	31d157a	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	12	#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	14	#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	15	#include "llvm/MC/EDInstInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	16	#include "llvm/MC/MCInst.h"
Benjamin Kramer	eea66f6	2011-11-11 12:39:41 +0000	[diff] [blame]	17	#include "llvm/MC/MCInstrDesc.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	18	#include "llvm/MC/MCExpr.h"
				19	#include "llvm/MC/MCContext.h"
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	20	#include "llvm/MC/MCDisassembler.h"
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	21	#include "llvm/MC/MCFixedLenDisassembler.h"
Dylan Noblesmith	75e3b7f	2012-04-03 15:48:14 +0000	[diff] [blame]	22	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	23	#include "llvm/Support/Debug.h"
				24	#include "llvm/Support/MemoryObject.h"
				25	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	26	#include "llvm/Support/LEB128.h"
Evan Cheng	3e74d6f	2011-08-24 18:08:43 +0000	[diff] [blame]	27	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	28	#include "llvm/Support/raw_ostream.h"
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	29	#include <vector>
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	30
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	31	using namespace llvm;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	32
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	33	typedef MCDisassembler::DecodeStatus DecodeStatus;
				34
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	35	namespace {
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	36	// Handles the condition code status of instructions in IT blocks
				37	class ITStatus
				38	{
				39	public:
				40	// Returns the condition code for instruction in IT block
				41	unsigned getITCC() {
				42	unsigned CC = ARMCC::AL;
				43	if (instrInITBlock())
				44	CC = ITStates.back();
				45	return CC;
				46	}
				47
				48	// Advances the IT block state to the next T or E
				49	void advanceITState() {
				50	ITStates.pop_back();
				51	}
				52
				53	// Returns true if the current instruction is in an IT block
				54	bool instrInITBlock() {
				55	return !ITStates.empty();
				56	}
				57
				58	// Returns true if current instruction is the last instruction in an IT block
				59	bool instrLastInITBlock() {
				60	return ITStates.size() == 1;
				61	}
				62
				63	// Called when decoding an IT instruction. Sets the IT state for the following
				64	// instructions that for the IT block. Firstcond and Mask correspond to the
				65	// fields in the IT instruction encoding.
				66	void setITState(char Firstcond, char Mask) {
				67	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	4d2f077	2012-04-27 08:42:59 +0000	[diff] [blame]	68	unsigned CondBit0 = Firstcond & 1;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	69	unsigned NumTZ = CountTrailingZeros_32(Mask);
				70	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				71	assert(NumTZ <= 3 && "Invalid IT mask!");
				72	// push condition codes onto the stack the correct order for the pops
				73	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				74	bool T = ((Mask >> Pos) & 1) == CondBit0;
				75	if (T)
				76	ITStates.push_back(CCBits);
				77	else
				78	ITStates.push_back(CCBits ^ 1);
				79	}
				80	ITStates.push_back(CCBits);
				81	}
				82
				83	private:
				84	std::vector<unsigned char> ITStates;
				85	};
				86	}
				87
				88	namespace {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	89	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				90	class ARMDisassembler : public MCDisassembler {
				91	public:
				92	/// Constructor - Initializes the disassembler.
				93	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	94	ARMDisassembler(const MCSubtargetInfo &STI) :
				95	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	96	}
				97
				98	~ARMDisassembler() {
				99	}
				100
				101	/// getInstruction - See MCDisassembler.
				102	DecodeStatus getInstruction(MCInst &instr,
				103	uint64_t &size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	104	const MemoryObject &region,
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	105	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	106	raw_ostream &vStream,
				107	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	108
				109	/// getEDInfo - See MCDisassembler.
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	110	const EDInstInfo *getEDInfo() const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	111	private:
				112	};
				113
				114	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				115	class ThumbDisassembler : public MCDisassembler {
				116	public:
				117	/// Constructor - Initializes the disassembler.
				118	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	119	ThumbDisassembler(const MCSubtargetInfo &STI) :
				120	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	121	}
				122
				123	~ThumbDisassembler() {
				124	}
				125
				126	/// getInstruction - See MCDisassembler.
				127	DecodeStatus getInstruction(MCInst &instr,
				128	uint64_t &size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	129	const MemoryObject &region,
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	130	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	131	raw_ostream &vStream,
				132	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	133
				134	/// getEDInfo - See MCDisassembler.
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	135	const EDInstInfo *getEDInfo() const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	136	private:
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	137	mutable ITStatus ITBlock;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	138	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	139	void UpdateThumbVFPPredicate(MCInst&) const;
				140	};
				141	}
				142
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	143	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	144	switch (In) {
				145	case MCDisassembler::Success:
				146	// Out stays the same.
				147	return true;
				148	case MCDisassembler::SoftFail:
				149	Out = In;
				150	return true;
				151	case MCDisassembler::Fail:
				152	Out = In;
				153	return false;
				154	}
David Blaikie	4d6ccb5	2012-01-20 21:51:11 +0000	[diff] [blame]	155	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	156	}
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	157
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	158
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	159	// Forward declare these because the autogenerated code will reference them.
				160	// Definitions are further down.
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	161	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	162	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	163	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	164	unsigned RegNo, uint64_t Address,
				165	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	168	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	169	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	173	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	174	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	175	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	176	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	177	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	178	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	179	unsigned RegNo,
				180	uint64_t Address,
				181	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	182	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	183	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	184	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	185	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	187	unsigned RegNo, uint64_t Address,
				188	const void *Decoder);
Johnny Chen	270159f	2010-08-12 01:40:54 +0000	[diff] [blame]	189
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	200	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	201	uint64_t Address, const void *Decoder);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	202
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	205	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	206	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	208	unsigned Insn,
				209	uint64_t Address,
				210	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	215	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	217	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	218	uint64_t Address, const void *Decoder);
				219
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	220	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	221	unsigned Insn,
				222	uint64_t Adddress,
				223	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	234	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	235	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	236	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	237	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	238	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	239	uint64_t Address, const void *Decoder);
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	240	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				241	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	242	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	243	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	244	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	245	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	246	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	247	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	248	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	249	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	250	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	251	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	280	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	282	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	284	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	285	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
				318
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	319
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	322	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	323	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	324	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	325	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	326	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	327	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	328	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	329	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	349	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	350	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	351	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	352	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	353	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	354	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	355	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	356	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	357	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	374	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	375	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	0afa009	2011-09-26 21:06:22 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
				382
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	383	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	384	uint64_t Address, const void *Decoder);
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	385	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				386	uint64_t Address, const void *Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	387	#include "ARMGenDisassemblerTables.inc"
Oscar Fuentes	38e1390	2010-09-28 11:48:19 +0000	[diff] [blame]	388	#include "ARMGenEDInfo.inc"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	389
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	390	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				391	return new ARMDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	392	}
				393
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	394	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				395	return new ThumbDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	396	}
				397
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	398	const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	399	return instInfoARM;
				400	}
				401
Benjamin Kramer	88b6fc0	2012-02-11 14:51:07 +0000	[diff] [blame]	402	const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	403	return instInfoARM;
				404	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	405
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	406	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	407	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	408	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	409	raw_ostream &os,
				410	raw_ostream &cs) const {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	411	CommentStream = &cs;
				412
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	413	uint8_t bytes[4];
				414
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	415	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				416	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				417
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	418	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	419	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				420	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	421	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	422	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	423
				424	// Encoded as a small-endian 32-bit word in the stream.
				425	uint32_t insn = (bytes[3] << 24) \|
				426	(bytes[2] << 16) \|
				427	(bytes[1] << 8) \|
				428	(bytes[0] << 0);
				429
				430	// Calling the auto-generated decoder function.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	431	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				432	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	433	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	434	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	435	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	436	}
				437
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	438	// VFP and NEON instructions, similarly, are shared between ARM
				439	// and Thumb modes.
				440	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	441	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	442	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	443	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	444	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	445	}
				446
				447	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	448	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				449	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	450	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	451	Size = 4;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	452	// Add a fake predicate operand, because we share these instruction
				453	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	454	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				455	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	456	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	457	}
				458
				459	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	460	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				461	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	462	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	463	Size = 4;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	464	// Add a fake predicate operand, because we share these instruction
				465	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	466	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				467	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	468	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	469	}
				470
				471	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	472	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				473	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	474	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	475	Size = 4;
				476	// Add a fake predicate operand, because we share these instruction
				477	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	478	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				479	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	480	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	481	}
				482
				483	MI.clear();
				484
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	485	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	486	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	487	}
				488
				489	namespace llvm {
Benjamin Kramer	1a2f988	2011-10-22 16:50:00 +0000	[diff] [blame]	490	extern const MCInstrDesc ARMInsts[];
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	491	}
				492
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	493	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				494	/// immediate Value in the MCInst. The immediate Value has had any PC
				495	/// adjustment made by the caller. If the instruction is a branch instruction
				496	/// then isBranch is true, else false. If the getOpInfo() function was set as
				497	/// part of the setupForSymbolicDisassembly() call then that function is called
				498	/// to get any symbolic information at the Address for this instruction. If
				499	/// that returns non-zero then the symbolic information it returns is used to
				500	/// create an MCExpr and that is added as an operand to the MCInst. If
				501	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				502	/// Value is done and if a symbol is found an MCExpr is created with that, else
				503	/// an MCExpr with Value is created. This function returns true if it adds an
				504	/// operand to the MCInst and false otherwise.
				505	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				506	bool isBranch, uint64_t InstSize,
				507	MCInst &MI, const void *Decoder) {
				508	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				509	LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	510	struct LLVMOpInfo1 SymbolicOp;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	511	memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	512	SymbolicOp.Value = Value;
				513	void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	514
				515	if (!getOpInfo \|\|
				516	!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
				517	// Clear SymbolicOp.Value from above and also all other fields.
				518	memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
				519	LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
				520	if (!SymbolLookUp)
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	521	return false;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	522	uint64_t ReferenceType;
				523	if (isBranch)
				524	ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
				525	else
				526	ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
				527	const char *ReferenceName;
				528	const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
				529	&ReferenceName);
				530	if (Name) {
				531	SymbolicOp.AddSymbol.Name = Name;
				532	SymbolicOp.AddSymbol.Present = true;
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	533	}
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	534	// For branches always create an MCExpr so it gets printed as hex address.
				535	else if (isBranch) {
				536	SymbolicOp.Value = Value;
				537	}
				538	if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
				539	(*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
				540	if (!Name && !isBranch)
				541	return false;
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	542	}
				543
				544	MCContext *Ctx = Dis->getMCContext();
				545	const MCExpr *Add = NULL;
				546	if (SymbolicOp.AddSymbol.Present) {
				547	if (SymbolicOp.AddSymbol.Name) {
				548	StringRef Name(SymbolicOp.AddSymbol.Name);
				549	MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
				550	Add = MCSymbolRefExpr::Create(Sym, *Ctx);
				551	} else {
				552	Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
				553	}
				554	}
				555
				556	const MCExpr *Sub = NULL;
				557	if (SymbolicOp.SubtractSymbol.Present) {
				558	if (SymbolicOp.SubtractSymbol.Name) {
				559	StringRef Name(SymbolicOp.SubtractSymbol.Name);
				560	MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
				561	Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
				562	} else {
				563	Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
				564	}
				565	}
				566
				567	const MCExpr *Off = NULL;
				568	if (SymbolicOp.Value != 0)
				569	Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
				570
				571	const MCExpr *Expr;
				572	if (Sub) {
				573	const MCExpr *LHS;
				574	if (Add)
				575	LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
				576	else
				577	LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
				578	if (Off != 0)
				579	Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
				580	else
				581	Expr = LHS;
				582	} else if (Add) {
				583	if (Off != 0)
				584	Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
				585	else
				586	Expr = Add;
				587	} else {
				588	if (Off != 0)
				589	Expr = Off;
				590	else
				591	Expr = MCConstantExpr::Create(0, *Ctx);
				592	}
				593
				594	if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
				595	MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
				596	else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
				597	MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
				598	else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
				599	MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach	01817c3	2011-10-20 17:28:20 +0000	[diff] [blame]	600	else
Craig Topper	bc21981	2012-02-07 02:50:20 +0000	[diff] [blame]	601	llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	602
				603	return true;
				604	}
				605
				606	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				607	/// referenced by a load instruction with the base register that is the Pc.
				608	/// These can often be values in a literal pool near the Address of the
				609	/// instruction. The Address of the instruction and its immediate Value are
				610	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	c8e41c5	2012-07-23 08:51:15 +0000	[diff] [blame]	611	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	612	/// the referenced address is that of a symbol. Or it will return a pointer to
				613	/// a literal 'C' string if the referenced address of the literal pool's entry
				614	/// is an address into a section with 'C' string literals.
				615	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	616	const void *Decoder) {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	617	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				618	LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
				619	if (SymbolLookUp) {
				620	void *DisInfo = Dis->getDisInfoBlock();
				621	uint64_t ReferenceType;
				622	ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
				623	const char *ReferenceName;
				624	(void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
				625	if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr \|\|
				626	ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
				627	(*Dis->CommentStream) << "literal pool for: " << ReferenceName;
				628	}
				629	}
				630
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	631	// Thumb1 instructions don't have explicit S bits. Rather, they
				632	// implicitly set CPSR. Since it's not represented in the encoding, the
				633	// auto-generated decoder won't inject the CPSR operand. We need to fix
				634	// that as a post-pass.
				635	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				636	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	637	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	638	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	639	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				640	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	641	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	642	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	643	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				644	return;
				645	}
				646	}
				647
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	648	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	649	}
				650
				651	// Most Thumb instructions don't have explicit predicates in the
				652	// encoding, but rather get their predicates from IT context. We need
				653	// to fix up the predicate operands using this context information as a
				654	// post-pass.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	655	MCDisassembler::DecodeStatus
				656	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	657	MCDisassembler::DecodeStatus S = Success;
				658
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	659	// A few instructions actually have predicates encoded in them. Don't
				660	// try to overwrite it if we're seeing one of those.
				661	switch (MI.getOpcode()) {
				662	case ARM::tBcc:
				663	case ARM::t2Bcc:
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	664	case ARM::tCBZ:
				665	case ARM::tCBNZ:
Owen Anderson	9f666b5	2011-09-19 23:47:10 +0000	[diff] [blame]	666	case ARM::tCPS:
				667	case ARM::t2CPS3p:
				668	case ARM::t2CPS2p:
				669	case ARM::t2CPS1p:
Owen Anderson	d9346fb	2011-09-19 23:57:20 +0000	[diff] [blame]	670	case ARM::tMOVSr:
Owen Anderson	c18e940	2011-10-13 17:58:39 +0000	[diff] [blame]	671	case ARM::tSETEND:
Owen Anderson	441462f	2011-09-08 22:48:37 +0000	[diff] [blame]	672	// Some instructions (mostly conditional branches) are not
				673	// allowed in IT blocks.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	674	if (ITBlock.instrInITBlock())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	675	S = SoftFail;
				676	else
				677	return Success;
				678	break;
				679	case ARM::tB:
				680	case ARM::t2B:
Owen Anderson	04c7877	2011-09-19 22:34:23 +0000	[diff] [blame]	681	case ARM::t2TBB:
				682	case ARM::t2TBH:
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	683	// Some instructions (mostly unconditional branches) can
				684	// only appears at the end of, or outside of, an IT.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	685	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	686	S = SoftFail;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	687	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	688	default:
				689	break;
				690	}
				691
				692	// If we're in an IT block, base the predicate on that. Otherwise,
				693	// assume a predicate of AL.
				694	unsigned CC;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	695	CC = ITBlock.getITCC();
				696	if (CC == 0xF)
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	697	CC = ARMCC::AL;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	698	if (ITBlock.instrInITBlock())
				699	ITBlock.advanceITState();
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	700
				701	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	702	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	703	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	704	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				705	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	706	if (OpInfo[i].isPredicate()) {
				707	I = MI.insert(I, MCOperand::CreateImm(CC));
				708	++I;
				709	if (CC == ARMCC::AL)
				710	MI.insert(I, MCOperand::CreateReg(0));
				711	else
				712	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	713	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	714	}
				715	}
				716
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	717	I = MI.insert(I, MCOperand::CreateImm(CC));
				718	++I;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	719	if (CC == ARMCC::AL)
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	720	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	721	else
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	722	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	723
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	724	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	725	}
				726
				727	// Thumb VFP instructions are a special case. Because we share their
				728	// encodings between ARM and Thumb modes, and they are predicable in ARM
				729	// mode, the auto-generated decoder will give them an (incorrect)
				730	// predicate operand. We need to rewrite these operands based on the IT
				731	// context as a post-pass.
				732	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				733	unsigned CC;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	734	CC = ITBlock.getITCC();
				735	if (ITBlock.instrInITBlock())
				736	ITBlock.advanceITState();
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	737
				738	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				739	MCInst::iterator I = MI.begin();
Owen Anderson	12a1e3b	2011-08-24 21:35:46 +0000	[diff] [blame]	740	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				741	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	742	if (OpInfo[i].isPredicate() ) {
				743	I->setImm(CC);
				744	++I;
				745	if (CC == ARMCC::AL)
				746	I->setReg(0);
				747	else
				748	I->setReg(ARM::CPSR);
				749	return;
				750	}
				751	}
				752	}
				753
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	754	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	755	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	756	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	757	raw_ostream &os,
				758	raw_ostream &cs) const {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	759	CommentStream = &cs;
				760
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	761	uint8_t bytes[4];
				762
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	763	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				764	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				765
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	766	// We want to read exactly 2 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	767	if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
				768	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	769	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	770	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	771
				772	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	773	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				774	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	775	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	776	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	777	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	778	return result;
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	779	}
				780
				781	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	782	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				783	Address, this, STI);
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	784	if (result) {
				785	Size = 2;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	786	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	787	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	788	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	789	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	790	}
				791
				792	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	793	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				794	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	795	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	796	Size = 2;
Owen Anderson	7011eee	2011-10-06 23:33:11 +0000	[diff] [blame]	797
				798	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				799	// the Thumb predicate.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	800	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	7011eee	2011-10-06 23:33:11 +0000	[diff] [blame]	801	result = MCDisassembler::SoftFail;
				802
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	803	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	804
				805	// If we find an IT instruction, we need to parse its condition
				806	// code and mask operands so that we can apply them correctly
				807	// to the subsequent instructions.
				808	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	34626ac	2011-09-14 21:06:21 +0000	[diff] [blame]	809
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	810	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	811	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	812	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	813	}
				814
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	815	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	816	}
				817
				818	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	819	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				820	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	821	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	822	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	823
				824	uint32_t insn32 = (bytes[3] << 8) \|
				825	(bytes[2] << 0) \|
				826	(bytes[1] << 24) \|
				827	(bytes[0] << 16);
				828	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	829	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				830	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	831	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	832	Size = 4;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	833	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	834	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	835	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	836	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	837	}
				838
				839	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	840	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				841	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	842	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	843	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	844	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	845	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	846	}
				847
				848	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	849	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	850	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	851	Size = 4;
				852	UpdateThumbVFPPredicate(MI);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	853	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	854	}
				855
				856	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	857	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				858	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	859	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	860	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	861	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	862	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	863	}
				864
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	865	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	866	MI.clear();
				867	uint32_t NEONLdStInsn = insn32;
				868	NEONLdStInsn &= 0xF0FFFFFF;
				869	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	870	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				871	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	872	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	873	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	874	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	875	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	876	}
				877	}
				878
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	879	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	880	MI.clear();
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	881	uint32_t NEONDataInsn = insn32;
				882	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				883	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				884	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	885	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				886	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	887	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	888	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	889	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	890	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	891	}
				892	}
				893
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	894	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	895	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	896	}
				897
				898
				899	extern "C" void LLVMInitializeARMDisassembler() {
				900	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				901	createARMDisassembler);
				902	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				903	createThumbDisassembler);
				904	}
				905
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	906	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	907	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				908	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				909	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				910	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				911	};
				912
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	913	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	914	uint64_t Address, const void *Decoder) {
				915	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	916	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	917
				918	unsigned Register = GPRDecoderTable[RegNo];
				919	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	920	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	921	}
				922
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	923	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	924	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	925	uint64_t Address, const void *Decoder) {
Silviu Baranga	5c062ad	2012-03-20 15:54:56 +0000	[diff] [blame]	926	DecodeStatus S = MCDisassembler::Success;
				927
				928	if (RegNo == 15)
				929	S = MCDisassembler::SoftFail;
				930
				931	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				932
				933	return S;
Owen Anderson	51c9805	2011-08-09 22:48:45 +0000	[diff] [blame]	934	}
				935
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	936	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	937	uint64_t Address, const void *Decoder) {
				938	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	939	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	940	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				941	}
				942
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	943	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	944	uint64_t Address, const void *Decoder) {
				945	unsigned Register = 0;
				946	switch (RegNo) {
				947	case 0:
				948	Register = ARM::R0;
				949	break;
				950	case 1:
				951	Register = ARM::R1;
				952	break;
				953	case 2:
				954	Register = ARM::R2;
				955	break;
				956	case 3:
				957	Register = ARM::R3;
				958	break;
				959	case 9:
				960	Register = ARM::R9;
				961	break;
				962	case 12:
				963	Register = ARM::R12;
				964	break;
				965	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	966	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	967	}
				968
				969	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	970	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	971	}
				972
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	973	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	974	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	975	if (RegNo == 13 \|\| RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	976	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				977	}
				978
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	979	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	980	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				981	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				982	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				983	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				984	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				985	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				986	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				987	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				988	};
				989
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	990	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	991	uint64_t Address, const void *Decoder) {
				992	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	993	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	994
				995	unsigned Register = SPRDecoderTable[RegNo];
				996	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	997	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	998	}
				999
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1000	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1001	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1002	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1003	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1004	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1005	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1006	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1007	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1008	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1009	};
				1010
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1011	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1012	uint64_t Address, const void *Decoder) {
				1013	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1014	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1015
				1016	unsigned Register = DPRDecoderTable[RegNo];
				1017	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1018	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1019	}
				1020
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1021	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1022	uint64_t Address, const void *Decoder) {
				1023	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1024	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1025	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1026	}
				1027
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1028	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1029	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1030	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1031	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1032	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1033	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1034	}
				1035
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1036	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1037	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1038	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1039	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1040	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1041	};
				1042
				1043
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1044	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1045	uint64_t Address, const void *Decoder) {
				1046	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1047	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1048	RegNo >>= 1;
				1049
				1050	unsigned Register = QPRDecoderTable[RegNo];
				1051	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1052	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1053	}
				1054
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1055	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	1056	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1057	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1058	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1059	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1060	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1061	ARM::Q15
				1062	};
				1063
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1064	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	1065	uint64_t Address, const void *Decoder) {
				1066	if (RegNo > 30)
				1067	return MCDisassembler::Fail;
				1068
				1069	unsigned Register = DPairDecoderTable[RegNo];
				1070	Inst.addOperand(MCOperand::CreateReg(Register));
				1071	return MCDisassembler::Success;
				1072	}
				1073
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1074	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	1075	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1076	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1077	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1078	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1079	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1080	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1081	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1082	ARM::D28_D30, ARM::D29_D31
				1083	};
				1084
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1085	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	1086	unsigned RegNo,
				1087	uint64_t Address,
				1088	const void *Decoder) {
				1089	if (RegNo > 29)
				1090	return MCDisassembler::Fail;
				1091
				1092	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1093	Inst.addOperand(MCOperand::CreateReg(Register));
				1094	return MCDisassembler::Success;
				1095	}
				1096
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1097	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1098	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1099	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	bd9091c	2011-08-09 21:07:45 +0000	[diff] [blame]	1100	// AL predicate is not allowed on Thumb1 branches.
				1101	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1102	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1103	Inst.addOperand(MCOperand::CreateImm(Val));
				1104	if (Val == ARMCC::AL) {
				1105	Inst.addOperand(MCOperand::CreateReg(0));
				1106	} else
				1107	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1108	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1109	}
				1110
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1111	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1112	uint64_t Address, const void *Decoder) {
				1113	if (Val)
				1114	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1115	else
				1116	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1117	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1118	}
				1119
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1120	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1121	uint64_t Address, const void *Decoder) {
				1122	uint32_t imm = Val & 0xFF;
				1123	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	ecb830e	2011-10-13 23:36:06 +0000	[diff] [blame]	1124	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1125	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1126	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1127	}
				1128
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1129	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1130	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1131	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1132
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1133	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1134	unsigned type = fieldFromInstruction(Val, 5, 2);
				1135	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1136
				1137	// Register-immediate
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1138	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1139	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1140
				1141	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1142	switch (type) {
				1143	case 0:
				1144	Shift = ARM_AM::lsl;
				1145	break;
				1146	case 1:
				1147	Shift = ARM_AM::lsr;
				1148	break;
				1149	case 2:
				1150	Shift = ARM_AM::asr;
				1151	break;
				1152	case 3:
				1153	Shift = ARM_AM::ror;
				1154	break;
				1155	}
				1156
				1157	if (Shift == ARM_AM::ror && imm == 0)
				1158	Shift = ARM_AM::rrx;
				1159
				1160	unsigned Op = Shift \| (imm << 3);
				1161	Inst.addOperand(MCOperand::CreateImm(Op));
				1162
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1163	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1164	}
				1165
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1166	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1167	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1168	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1169
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1170	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1171	unsigned type = fieldFromInstruction(Val, 5, 2);
				1172	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1173
				1174	// Register-register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1175	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1176	return MCDisassembler::Fail;
				1177	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1178	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1179
				1180	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1181	switch (type) {
				1182	case 0:
				1183	Shift = ARM_AM::lsl;
				1184	break;
				1185	case 1:
				1186	Shift = ARM_AM::lsr;
				1187	break;
				1188	case 2:
				1189	Shift = ARM_AM::asr;
				1190	break;
				1191	case 3:
				1192	Shift = ARM_AM::ror;
				1193	break;
				1194	}
				1195
				1196	Inst.addOperand(MCOperand::CreateImm(Shift));
				1197
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1198	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1199	}
				1200
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1201	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1202	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1203	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1204
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	1205	bool writebackLoad = false;
				1206	unsigned writebackReg = 0;
				1207	switch (Inst.getOpcode()) {
				1208	default:
				1209	break;
				1210	case ARM::LDMIA_UPD:
				1211	case ARM::LDMDB_UPD:
				1212	case ARM::LDMIB_UPD:
				1213	case ARM::LDMDA_UPD:
				1214	case ARM::t2LDMIA_UPD:
				1215	case ARM::t2LDMDB_UPD:
				1216	writebackLoad = true;
				1217	writebackReg = Inst.getOperand(0).getReg();
				1218	break;
				1219	}
				1220
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	1221	// Empty register lists are not allowed.
Owen Anderson	244006d	2011-11-02 17:46:18 +0000	[diff] [blame]	1222	if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1223	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1224	if (Val & (1 << i)) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1225	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1226	return MCDisassembler::Fail;
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	1227	// Writeback not allowed if Rn is in the target list.
				1228	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				1229	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1230	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1231	}
				1232
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1233	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1234	}
				1235
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1236	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1237	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1238	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1239
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1240	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1241	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1242
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1243	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1244	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1245	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1246	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1247	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1248	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1249
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1250	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1251	}
				1252
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1253	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1254	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1255	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1256
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1257	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1258	unsigned regs = fieldFromInstruction(Val, 0, 8);
Silviu Baranga	b422d0b	2012-05-03 16:38:40 +0000	[diff] [blame]	1259
				1260	regs = regs >> 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1261
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1262	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1263	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1264	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1265	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1266	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1267	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1268
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1269	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1270	}
				1271
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1272	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1273	uint64_t Address, const void *Decoder) {
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1274	// This operand encodes a mask of contiguous zeros between a specified MSB
				1275	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1276	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1277	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1278	// create the final mask.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1279	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1280	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1281
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1282	DecodeStatus S = MCDisassembler::Success;
				1283	if (lsb > msb) Check(S, MCDisassembler::SoftFail);
				1284
Owen Anderson	8b22778	2011-09-16 23:04:48 +0000	[diff] [blame]	1285	uint32_t msb_mask = 0xFFFFFFFF;
				1286	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1287	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1288
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1289	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1290	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1291	}
				1292
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1293	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1294	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1295	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1296
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1297	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1298	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1299	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1300	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1301	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1302	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1303
				1304	switch (Inst.getOpcode()) {
				1305	case ARM::LDC_OFFSET:
				1306	case ARM::LDC_PRE:
				1307	case ARM::LDC_POST:
				1308	case ARM::LDC_OPTION:
				1309	case ARM::LDCL_OFFSET:
				1310	case ARM::LDCL_PRE:
				1311	case ARM::LDCL_POST:
				1312	case ARM::LDCL_OPTION:
				1313	case ARM::STC_OFFSET:
				1314	case ARM::STC_PRE:
				1315	case ARM::STC_POST:
				1316	case ARM::STC_OPTION:
				1317	case ARM::STCL_OFFSET:
				1318	case ARM::STCL_PRE:
				1319	case ARM::STCL_POST:
				1320	case ARM::STCL_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1321	case ARM::t2LDC_OFFSET:
				1322	case ARM::t2LDC_PRE:
				1323	case ARM::t2LDC_POST:
				1324	case ARM::t2LDC_OPTION:
				1325	case ARM::t2LDCL_OFFSET:
				1326	case ARM::t2LDCL_PRE:
				1327	case ARM::t2LDCL_POST:
				1328	case ARM::t2LDCL_OPTION:
				1329	case ARM::t2STC_OFFSET:
				1330	case ARM::t2STC_PRE:
				1331	case ARM::t2STC_POST:
				1332	case ARM::t2STC_OPTION:
				1333	case ARM::t2STCL_OFFSET:
				1334	case ARM::t2STCL_PRE:
				1335	case ARM::t2STCL_POST:
				1336	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1337	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1338	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1339	break;
				1340	default:
				1341	break;
				1342	}
				1343
				1344	Inst.addOperand(MCOperand::CreateImm(coproc));
				1345	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1346	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1347	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1348
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1349	switch (Inst.getOpcode()) {
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1350	case ARM::t2LDC2_OFFSET:
				1351	case ARM::t2LDC2L_OFFSET:
				1352	case ARM::t2LDC2_PRE:
				1353	case ARM::t2LDC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1354	case ARM::t2STC2_OFFSET:
				1355	case ARM::t2STC2L_OFFSET:
				1356	case ARM::t2STC2_PRE:
				1357	case ARM::t2STC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1358	case ARM::LDC2_OFFSET:
				1359	case ARM::LDC2L_OFFSET:
				1360	case ARM::LDC2_PRE:
				1361	case ARM::LDC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1362	case ARM::STC2_OFFSET:
				1363	case ARM::STC2L_OFFSET:
				1364	case ARM::STC2_PRE:
				1365	case ARM::STC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1366	case ARM::t2LDC_OFFSET:
				1367	case ARM::t2LDCL_OFFSET:
				1368	case ARM::t2LDC_PRE:
				1369	case ARM::t2LDCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1370	case ARM::t2STC_OFFSET:
				1371	case ARM::t2STCL_OFFSET:
				1372	case ARM::t2STC_PRE:
				1373	case ARM::t2STCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1374	case ARM::LDC_OFFSET:
				1375	case ARM::LDCL_OFFSET:
				1376	case ARM::LDC_PRE:
				1377	case ARM::LDCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1378	case ARM::STC_OFFSET:
				1379	case ARM::STCL_OFFSET:
				1380	case ARM::STC_PRE:
				1381	case ARM::STCL_PRE:
Jim Grosbach	81b2928	2011-10-12 21:59:02 +0000	[diff] [blame]	1382	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1383	Inst.addOperand(MCOperand::CreateImm(imm));
				1384	break;
				1385	case ARM::t2LDC2_POST:
				1386	case ARM::t2LDC2L_POST:
				1387	case ARM::t2STC2_POST:
				1388	case ARM::t2STC2L_POST:
				1389	case ARM::LDC2_POST:
				1390	case ARM::LDC2L_POST:
				1391	case ARM::STC2_POST:
				1392	case ARM::STC2L_POST:
				1393	case ARM::t2LDC_POST:
				1394	case ARM::t2LDCL_POST:
				1395	case ARM::t2STC_POST:
				1396	case ARM::t2STCL_POST:
				1397	case ARM::LDC_POST:
				1398	case ARM::LDCL_POST:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1399	case ARM::STC_POST:
				1400	case ARM::STCL_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1401	imm \|= U << 8;
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1402	// fall through.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1403	default:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1404	// The 'option' variant doesn't encode 'U' in the immediate since
				1405	// the immediate is unsigned [0,255].
				1406	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1407	break;
				1408	}
				1409
				1410	switch (Inst.getOpcode()) {
				1411	case ARM::LDC_OFFSET:
				1412	case ARM::LDC_PRE:
				1413	case ARM::LDC_POST:
				1414	case ARM::LDC_OPTION:
				1415	case ARM::LDCL_OFFSET:
				1416	case ARM::LDCL_PRE:
				1417	case ARM::LDCL_POST:
				1418	case ARM::LDCL_OPTION:
				1419	case ARM::STC_OFFSET:
				1420	case ARM::STC_PRE:
				1421	case ARM::STC_POST:
				1422	case ARM::STC_OPTION:
				1423	case ARM::STCL_OFFSET:
				1424	case ARM::STCL_PRE:
				1425	case ARM::STCL_POST:
				1426	case ARM::STCL_OPTION:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1427	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1428	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1429	break;
				1430	default:
				1431	break;
				1432	}
				1433
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1434	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1435	}
				1436
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1437	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1438	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1439	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1440	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1441
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1442	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1443	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1444	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1445	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1446	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1447	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1448	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1449	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1450
				1451	// On stores, the writeback operand precedes Rt.
				1452	switch (Inst.getOpcode()) {
				1453	case ARM::STR_POST_IMM:
				1454	case ARM::STR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1455	case ARM::STRB_POST_IMM:
				1456	case ARM::STRB_POST_REG:
Jim Grosbach	342ebd5	2011-08-11 22:18:00 +0000	[diff] [blame]	1457	case ARM::STRT_POST_REG:
				1458	case ARM::STRT_POST_IMM:
Jim Grosbach	10348e7	2011-08-11 20:04:56 +0000	[diff] [blame]	1459	case ARM::STRBT_POST_REG:
				1460	case ARM::STRBT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1461	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1462	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1463	break;
				1464	default:
				1465	break;
				1466	}
				1467
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1468	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1469	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1470
				1471	// On loads, the writeback operand comes after Rt.
				1472	switch (Inst.getOpcode()) {
				1473	case ARM::LDR_POST_IMM:
				1474	case ARM::LDR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1475	case ARM::LDRB_POST_IMM:
				1476	case ARM::LDRB_POST_REG:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1477	case ARM::LDRBT_POST_REG:
				1478	case ARM::LDRBT_POST_IMM:
Jim Grosbach	5999926	2011-08-10 23:43:54 +0000	[diff] [blame]	1479	case ARM::LDRT_POST_REG:
				1480	case ARM::LDRT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1481	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1482	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1483	break;
				1484	default:
				1485	break;
				1486	}
				1487
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1488	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1489	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1490
				1491	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1492	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1493	Op = ARM_AM::sub;
				1494
				1495	bool writeback = (P == 0) \|\| (W == 1);
				1496	unsigned idx_mode = 0;
				1497	if (P && writeback)
				1498	idx_mode = ARMII::IndexModePre;
				1499	else if (!P && writeback)
				1500	idx_mode = ARMII::IndexModePost;
				1501
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1502	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1503	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	71156a6	2011-08-11 19:00:18 +0000	[diff] [blame]	1504
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1505	if (reg) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1506	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1507	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1508	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1509	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1510	case 0:
				1511	Opc = ARM_AM::lsl;
				1512	break;
				1513	case 1:
				1514	Opc = ARM_AM::lsr;
				1515	break;
				1516	case 2:
				1517	Opc = ARM_AM::asr;
				1518	break;
				1519	case 3:
				1520	Opc = ARM_AM::ror;
				1521	break;
				1522	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1523	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1524	}
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1525	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	93c7c44	2012-09-22 11:18:12 +0000	[diff] [blame^]	1526	if (Opc == ARM_AM::ror && amt == 0)
				1527	Opc = ARM_AM::rrx;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1528	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1529
				1530	Inst.addOperand(MCOperand::CreateImm(imm));
				1531	} else {
				1532	Inst.addOperand(MCOperand::CreateReg(0));
				1533	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1534	Inst.addOperand(MCOperand::CreateImm(tmp));
				1535	}
				1536
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1537	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1538	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1539
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1540	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1541	}
				1542
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1543	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1544	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1545	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1546
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1547	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1548	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1549	unsigned type = fieldFromInstruction(Val, 5, 2);
				1550	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1551	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1552
Owen Anderson	51157d2	2011-08-09 21:38:14 +0000	[diff] [blame]	1553	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1554	switch (type) {
				1555	case 0:
				1556	ShOp = ARM_AM::lsl;
				1557	break;
				1558	case 1:
				1559	ShOp = ARM_AM::lsr;
				1560	break;
				1561	case 2:
				1562	ShOp = ARM_AM::asr;
				1563	break;
				1564	case 3:
				1565	ShOp = ARM_AM::ror;
				1566	break;
				1567	}
				1568
Tim Northover	93c7c44	2012-09-22 11:18:12 +0000	[diff] [blame^]	1569	if (ShOp == ARM_AM::ror && imm == 0)
				1570	ShOp = ARM_AM::rrx;
				1571
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1572	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1573	return MCDisassembler::Fail;
				1574	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1575	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1576	unsigned shift;
				1577	if (U)
				1578	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1579	else
				1580	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1581	Inst.addOperand(MCOperand::CreateImm(shift));
				1582
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1583	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1584	}
				1585
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1586	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1587	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1588	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1589	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1590
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1591	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1592	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1593	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1594	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1595	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1596	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1597	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1598	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1599	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1600	unsigned Rt2 = Rt + 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1601
				1602	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1603
				1604	// For {LD,ST}RD, Rt must be even, else undefined.
				1605	switch (Inst.getOpcode()) {
				1606	case ARM::STRD:
				1607	case ARM::STRD_PRE:
				1608	case ARM::STRD_POST:
				1609	case ARM::LDRD:
				1610	case ARM::LDRD_PRE:
				1611	case ARM::LDRD_POST:
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1612	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1613	break;
				1614	default:
				1615	break;
				1616	}
				1617	switch (Inst.getOpcode()) {
				1618	case ARM::STRD:
				1619	case ARM::STRD_PRE:
				1620	case ARM::STRD_POST:
				1621	if (P == 0 && W == 1)
				1622	S = MCDisassembler::SoftFail;
				1623
				1624	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1625	S = MCDisassembler::SoftFail;
				1626	if (type && Rm == 15)
				1627	S = MCDisassembler::SoftFail;
				1628	if (Rt2 == 15)
				1629	S = MCDisassembler::SoftFail;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1630	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1631	S = MCDisassembler::SoftFail;
				1632	break;
				1633	case ARM::STRH:
				1634	case ARM::STRH_PRE:
				1635	case ARM::STRH_POST:
				1636	if (Rt == 15)
				1637	S = MCDisassembler::SoftFail;
				1638	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1639	S = MCDisassembler::SoftFail;
				1640	if (!type && Rm == 15)
				1641	S = MCDisassembler::SoftFail;
				1642	break;
				1643	case ARM::LDRD:
				1644	case ARM::LDRD_PRE:
				1645	case ARM::LDRD_POST:
				1646	if (type && Rn == 15){
				1647	if (Rt2 == 15)
				1648	S = MCDisassembler::SoftFail;
				1649	break;
				1650	}
				1651	if (P == 0 && W == 1)
				1652	S = MCDisassembler::SoftFail;
				1653	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1654	S = MCDisassembler::SoftFail;
				1655	if (!type && writeback && Rn == 15)
				1656	S = MCDisassembler::SoftFail;
				1657	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1658	S = MCDisassembler::SoftFail;
				1659	break;
				1660	case ARM::LDRH:
				1661	case ARM::LDRH_PRE:
				1662	case ARM::LDRH_POST:
				1663	if (type && Rn == 15){
				1664	if (Rt == 15)
				1665	S = MCDisassembler::SoftFail;
				1666	break;
				1667	}
				1668	if (Rt == 15)
				1669	S = MCDisassembler::SoftFail;
				1670	if (!type && Rm == 15)
				1671	S = MCDisassembler::SoftFail;
				1672	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1673	S = MCDisassembler::SoftFail;
				1674	break;
				1675	case ARM::LDRSH:
				1676	case ARM::LDRSH_PRE:
				1677	case ARM::LDRSH_POST:
				1678	case ARM::LDRSB:
				1679	case ARM::LDRSB_PRE:
				1680	case ARM::LDRSB_POST:
				1681	if (type && Rn == 15){
				1682	if (Rt == 15)
				1683	S = MCDisassembler::SoftFail;
				1684	break;
				1685	}
				1686	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1687	S = MCDisassembler::SoftFail;
				1688	if (!type && (Rt == 15 \|\| Rm == 15))
				1689	S = MCDisassembler::SoftFail;
				1690	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1691	S = MCDisassembler::SoftFail;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1692	break;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1693	default:
				1694	break;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1695	}
				1696
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1697	if (writeback) { // Writeback
				1698	if (P)
				1699	U \|= ARMII::IndexModePre << 9;
				1700	else
				1701	U \|= ARMII::IndexModePost << 9;
				1702
				1703	// On stores, the writeback operand precedes Rt.
				1704	switch (Inst.getOpcode()) {
				1705	case ARM::STRD:
				1706	case ARM::STRD_PRE:
				1707	case ARM::STRD_POST:
Owen Anderson	79628e9	2011-08-12 20:02:50 +0000	[diff] [blame]	1708	case ARM::STRH:
				1709	case ARM::STRH_PRE:
				1710	case ARM::STRH_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1711	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1712	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1713	break;
				1714	default:
				1715	break;
				1716	}
				1717	}
				1718
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1719	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1720	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1721	switch (Inst.getOpcode()) {
				1722	case ARM::STRD:
				1723	case ARM::STRD_PRE:
				1724	case ARM::STRD_POST:
				1725	case ARM::LDRD:
				1726	case ARM::LDRD_PRE:
				1727	case ARM::LDRD_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1728	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1729	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1730	break;
				1731	default:
				1732	break;
				1733	}
				1734
				1735	if (writeback) {
				1736	// On loads, the writeback operand comes after Rt.
				1737	switch (Inst.getOpcode()) {
				1738	case ARM::LDRD:
				1739	case ARM::LDRD_PRE:
				1740	case ARM::LDRD_POST:
Owen Anderson	0d09499	2011-08-12 20:36:11 +0000	[diff] [blame]	1741	case ARM::LDRH:
				1742	case ARM::LDRH_PRE:
				1743	case ARM::LDRH_POST:
				1744	case ARM::LDRSH:
				1745	case ARM::LDRSH_PRE:
				1746	case ARM::LDRSH_POST:
				1747	case ARM::LDRSB:
				1748	case ARM::LDRSB_PRE:
				1749	case ARM::LDRSB_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1750	case ARM::LDRHTr:
				1751	case ARM::LDRSBTr:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1752	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1753	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1754	break;
				1755	default:
				1756	break;
				1757	}
				1758	}
				1759
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1760	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1761	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1762
				1763	if (type) {
				1764	Inst.addOperand(MCOperand::CreateReg(0));
				1765	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1766	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1767	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1768	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1769	Inst.addOperand(MCOperand::CreateImm(U));
				1770	}
				1771
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1772	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1773	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1774
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1775	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1776	}
				1777
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1778	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1779	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1780	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1781
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1782	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1783	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1784
				1785	switch (mode) {
				1786	case 0:
				1787	mode = ARM_AM::da;
				1788	break;
				1789	case 1:
				1790	mode = ARM_AM::ia;
				1791	break;
				1792	case 2:
				1793	mode = ARM_AM::db;
				1794	break;
				1795	case 3:
				1796	mode = ARM_AM::ib;
				1797	break;
				1798	}
				1799
				1800	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1801	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1802	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1803
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1804	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1805	}
				1806
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1807	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1808	unsigned Insn,
				1809	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1810	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1811
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1812	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1813	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1814	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1815
				1816	if (pred == 0xF) {
				1817	switch (Inst.getOpcode()) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1818	case ARM::LDMDA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1819	Inst.setOpcode(ARM::RFEDA);
				1820	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1821	case ARM::LDMDA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1822	Inst.setOpcode(ARM::RFEDA_UPD);
				1823	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1824	case ARM::LDMDB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1825	Inst.setOpcode(ARM::RFEDB);
				1826	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1827	case ARM::LDMDB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1828	Inst.setOpcode(ARM::RFEDB_UPD);
				1829	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1830	case ARM::LDMIA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1831	Inst.setOpcode(ARM::RFEIA);
				1832	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1833	case ARM::LDMIA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1834	Inst.setOpcode(ARM::RFEIA_UPD);
				1835	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1836	case ARM::LDMIB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1837	Inst.setOpcode(ARM::RFEIB);
				1838	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1839	case ARM::LDMIB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1840	Inst.setOpcode(ARM::RFEIB_UPD);
				1841	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1842	case ARM::STMDA:
				1843	Inst.setOpcode(ARM::SRSDA);
				1844	break;
				1845	case ARM::STMDA_UPD:
				1846	Inst.setOpcode(ARM::SRSDA_UPD);
				1847	break;
				1848	case ARM::STMDB:
				1849	Inst.setOpcode(ARM::SRSDB);
				1850	break;
				1851	case ARM::STMDB_UPD:
				1852	Inst.setOpcode(ARM::SRSDB_UPD);
				1853	break;
				1854	case ARM::STMIA:
				1855	Inst.setOpcode(ARM::SRSIA);
				1856	break;
				1857	case ARM::STMIA_UPD:
				1858	Inst.setOpcode(ARM::SRSIA_UPD);
				1859	break;
				1860	case ARM::STMIB:
				1861	Inst.setOpcode(ARM::SRSIB);
				1862	break;
				1863	case ARM::STMIB_UPD:
				1864	Inst.setOpcode(ARM::SRSIB_UPD);
				1865	break;
				1866	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1867	if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1868	}
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1869
				1870	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1871	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1872	Inst.addOperand(
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1873	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1874	return S;
				1875	}
				1876
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1877	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1878	}
				1879
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1880	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1881	return MCDisassembler::Fail;
				1882	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1883	return MCDisassembler::Fail; // Tied
				1884	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1885	return MCDisassembler::Fail;
				1886	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1887	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1888
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1889	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1890	}
				1891
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1892	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1893	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1894	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1895	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1896	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1897	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1898
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1899	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	1900
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1901	// imod == '01' --> UNPREDICTABLE
				1902	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1903	// return failure here. The '01' imod value is unprintable, so there's
				1904	// nothing useful we could do even if we returned UNPREDICTABLE.
				1905
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1906	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1907
				1908	if (imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1909	Inst.setOpcode(ARM::CPS3p);
				1910	Inst.addOperand(MCOperand::CreateImm(imod));
				1911	Inst.addOperand(MCOperand::CreateImm(iflags));
				1912	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1913	} else if (imod && !M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1914	Inst.setOpcode(ARM::CPS2p);
				1915	Inst.addOperand(MCOperand::CreateImm(imod));
				1916	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1917	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1918	} else if (!imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1919	Inst.setOpcode(ARM::CPS1p);
				1920	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1921	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1922	} else {
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1923	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1924	Inst.setOpcode(ARM::CPS1p);
				1925	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1926	S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1927	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1928
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1929	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1930	}
				1931
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1932	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1933	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1934	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1935	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1936	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				1937	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1938
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1939	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1940
				1941	// imod == '01' --> UNPREDICTABLE
				1942	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1943	// return failure here. The '01' imod value is unprintable, so there's
				1944	// nothing useful we could do even if we returned UNPREDICTABLE.
				1945
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1946	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1947
				1948	if (imod && M) {
				1949	Inst.setOpcode(ARM::t2CPS3p);
				1950	Inst.addOperand(MCOperand::CreateImm(imod));
				1951	Inst.addOperand(MCOperand::CreateImm(iflags));
				1952	Inst.addOperand(MCOperand::CreateImm(mode));
				1953	} else if (imod && !M) {
				1954	Inst.setOpcode(ARM::t2CPS2p);
				1955	Inst.addOperand(MCOperand::CreateImm(imod));
				1956	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1957	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1958	} else if (!imod && M) {
				1959	Inst.setOpcode(ARM::t2CPS1p);
				1960	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1961	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1962	} else {
				1963	// imod == '00' && M == '0' --> UNPREDICTABLE
				1964	Inst.setOpcode(ARM::t2CPS1p);
				1965	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1966	S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1967	}
				1968
				1969	return S;
				1970	}
				1971
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1972	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1973	uint64_t Address, const void *Decoder) {
				1974	DecodeStatus S = MCDisassembler::Success;
				1975
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1976	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1977	unsigned imm = 0;
				1978
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1979	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				1980	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				1981	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				1982	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1983
				1984	if (Inst.getOpcode() == ARM::t2MOVTi16)
				1985	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				1986	return MCDisassembler::Fail;
				1987	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				1988	return MCDisassembler::Fail;
				1989
				1990	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				1991	Inst.addOperand(MCOperand::CreateImm(imm));
				1992
				1993	return S;
				1994	}
				1995
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1996	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1997	uint64_t Address, const void *Decoder) {
				1998	DecodeStatus S = MCDisassembler::Success;
				1999
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2000	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2001	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2002	unsigned imm = 0;
				2003
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2004	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2005	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2006
				2007	if (Inst.getOpcode() == ARM::MOVTi16)
				2008	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2009	return MCDisassembler::Fail;
				2010	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2011	return MCDisassembler::Fail;
				2012
				2013	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2014	Inst.addOperand(MCOperand::CreateImm(imm));
				2015
				2016	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2017	return MCDisassembler::Fail;
				2018
				2019	return S;
				2020	}
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	2021
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2022	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2023	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2024	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2025
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2026	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2027	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2028	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2029	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2030	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2031
				2032	if (pred == 0xF)
				2033	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2034
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2035	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2036	return MCDisassembler::Fail;
				2037	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2038	return MCDisassembler::Fail;
				2039	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2040	return MCDisassembler::Fail;
				2041	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2042	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2043
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2044	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2045	return MCDisassembler::Fail;
Owen Anderson	1fb6673	2011-08-11 22:05:38 +0000	[diff] [blame]	2046
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2047	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2048	}
				2049
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2050	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2051	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2052	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2053
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2054	unsigned add = fieldFromInstruction(Val, 12, 1);
				2055	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2056	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2057
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2058	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2059	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2060
				2061	if (!add) imm *= -1;
				2062	if (imm == 0 && !add) imm = INT32_MIN;
				2063	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2064	if (Rn == 15)
				2065	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2066
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2067	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2068	}
				2069
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2070	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2071	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2072	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2073
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2074	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2075	unsigned U = fieldFromInstruction(Val, 8, 1);
				2076	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2077
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2078	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2079	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2080
				2081	if (U)
				2082	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2083	else
				2084	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2085
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2086	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2087	}
				2088
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2089	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2090	uint64_t Address, const void *Decoder) {
				2091	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2092	}
				2093
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2094	static DecodeStatus
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2095	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2096	uint64_t Address, const void *Decoder) {
				2097	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2098	unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) \|
				2099	(fieldFromInstruction(Insn, 11, 1) << 18) \|
				2100	(fieldFromInstruction(Insn, 13, 1) << 17) \|
				2101	(fieldFromInstruction(Insn, 16, 6) << 11) \|
				2102	(fieldFromInstruction(Insn, 26, 1) << 19);
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2103	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
				2104	true, 4, Inst, Decoder))
				2105	Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
				2106	return S;
				2107	}
				2108
				2109	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2110	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2111	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2112	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2113
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2114	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2115	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2116
				2117	if (pred == 0xF) {
				2118	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2119	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	2120	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2121	true, 4, Inst, Decoder))
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	2122	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2123	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2124	}
				2125
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	2126	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2127	true, 4, Inst, Decoder))
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2128	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2129	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2130	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2131
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2132	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2133	}
				2134
				2135
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2136	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2137	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2138	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2139
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2140	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2141	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2142
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2143	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2144	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2145	if (!align)
				2146	Inst.addOperand(MCOperand::CreateImm(0));
				2147	else
				2148	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2149
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2150	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2151	}
				2152
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2153	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2154	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2155	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2156
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2157	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2158	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2159	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2160	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2161	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2162	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2163
				2164	// First output register
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2165	switch (Inst.getOpcode()) {
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2166	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2167	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2168	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2169	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2170	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2171	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2172	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2173	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2174	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2175	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2176	return MCDisassembler::Fail;
				2177	break;
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	2178	case ARM::VLD2b16:
				2179	case ARM::VLD2b32:
				2180	case ARM::VLD2b8:
				2181	case ARM::VLD2b16wb_fixed:
				2182	case ARM::VLD2b16wb_register:
				2183	case ARM::VLD2b32wb_fixed:
				2184	case ARM::VLD2b32wb_register:
				2185	case ARM::VLD2b8wb_fixed:
				2186	case ARM::VLD2b8wb_register:
				2187	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2188	return MCDisassembler::Fail;
				2189	break;
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2190	default:
				2191	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2192	return MCDisassembler::Fail;
				2193	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2194
				2195	// Second output register
				2196	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2197	case ARM::VLD3d8:
				2198	case ARM::VLD3d16:
				2199	case ARM::VLD3d32:
				2200	case ARM::VLD3d8_UPD:
				2201	case ARM::VLD3d16_UPD:
				2202	case ARM::VLD3d32_UPD:
				2203	case ARM::VLD4d8:
				2204	case ARM::VLD4d16:
				2205	case ARM::VLD4d32:
				2206	case ARM::VLD4d8_UPD:
				2207	case ARM::VLD4d16_UPD:
				2208	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2209	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2210	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2211	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2212	case ARM::VLD3q8:
				2213	case ARM::VLD3q16:
				2214	case ARM::VLD3q32:
				2215	case ARM::VLD3q8_UPD:
				2216	case ARM::VLD3q16_UPD:
				2217	case ARM::VLD3q32_UPD:
				2218	case ARM::VLD4q8:
				2219	case ARM::VLD4q16:
				2220	case ARM::VLD4q32:
				2221	case ARM::VLD4q8_UPD:
				2222	case ARM::VLD4q16_UPD:
				2223	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2224	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2225	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2226	default:
				2227	break;
				2228	}
				2229
				2230	// Third output register
				2231	switch(Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2232	case ARM::VLD3d8:
				2233	case ARM::VLD3d16:
				2234	case ARM::VLD3d32:
				2235	case ARM::VLD3d8_UPD:
				2236	case ARM::VLD3d16_UPD:
				2237	case ARM::VLD3d32_UPD:
				2238	case ARM::VLD4d8:
				2239	case ARM::VLD4d16:
				2240	case ARM::VLD4d32:
				2241	case ARM::VLD4d8_UPD:
				2242	case ARM::VLD4d16_UPD:
				2243	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2244	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2245	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2246	break;
				2247	case ARM::VLD3q8:
				2248	case ARM::VLD3q16:
				2249	case ARM::VLD3q32:
				2250	case ARM::VLD3q8_UPD:
				2251	case ARM::VLD3q16_UPD:
				2252	case ARM::VLD3q32_UPD:
				2253	case ARM::VLD4q8:
				2254	case ARM::VLD4q16:
				2255	case ARM::VLD4q32:
				2256	case ARM::VLD4q8_UPD:
				2257	case ARM::VLD4q16_UPD:
				2258	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2259	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2260	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2261	break;
				2262	default:
				2263	break;
				2264	}
				2265
				2266	// Fourth output register
				2267	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2268	case ARM::VLD4d8:
				2269	case ARM::VLD4d16:
				2270	case ARM::VLD4d32:
				2271	case ARM::VLD4d8_UPD:
				2272	case ARM::VLD4d16_UPD:
				2273	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2274	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2275	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2276	break;
				2277	case ARM::VLD4q8:
				2278	case ARM::VLD4q16:
				2279	case ARM::VLD4q32:
				2280	case ARM::VLD4q8_UPD:
				2281	case ARM::VLD4q16_UPD:
				2282	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2283	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2284	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2285	break;
				2286	default:
				2287	break;
				2288	}
				2289
				2290	// Writeback operand
				2291	switch (Inst.getOpcode()) {
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2292	case ARM::VLD1d8wb_fixed:
				2293	case ARM::VLD1d16wb_fixed:
				2294	case ARM::VLD1d32wb_fixed:
				2295	case ARM::VLD1d64wb_fixed:
				2296	case ARM::VLD1d8wb_register:
				2297	case ARM::VLD1d16wb_register:
				2298	case ARM::VLD1d32wb_register:
				2299	case ARM::VLD1d64wb_register:
				2300	case ARM::VLD1q8wb_fixed:
				2301	case ARM::VLD1q16wb_fixed:
				2302	case ARM::VLD1q32wb_fixed:
				2303	case ARM::VLD1q64wb_fixed:
				2304	case ARM::VLD1q8wb_register:
				2305	case ARM::VLD1q16wb_register:
				2306	case ARM::VLD1q32wb_register:
				2307	case ARM::VLD1q64wb_register:
Jim Grosbach	5921675	2011-10-24 23:26:05 +0000	[diff] [blame]	2308	case ARM::VLD1d8Twb_fixed:
				2309	case ARM::VLD1d8Twb_register:
				2310	case ARM::VLD1d16Twb_fixed:
				2311	case ARM::VLD1d16Twb_register:
				2312	case ARM::VLD1d32Twb_fixed:
				2313	case ARM::VLD1d32Twb_register:
				2314	case ARM::VLD1d64Twb_fixed:
				2315	case ARM::VLD1d64Twb_register:
Jim Grosbach	399cdca	2011-10-25 00:14:01 +0000	[diff] [blame]	2316	case ARM::VLD1d8Qwb_fixed:
				2317	case ARM::VLD1d8Qwb_register:
				2318	case ARM::VLD1d16Qwb_fixed:
				2319	case ARM::VLD1d16Qwb_register:
				2320	case ARM::VLD1d32Qwb_fixed:
				2321	case ARM::VLD1d32Qwb_register:
				2322	case ARM::VLD1d64Qwb_fixed:
				2323	case ARM::VLD1d64Qwb_register:
Jim Grosbach	a4e3c7f	2011-12-09 21:28:25 +0000	[diff] [blame]	2324	case ARM::VLD2d8wb_fixed:
				2325	case ARM::VLD2d16wb_fixed:
				2326	case ARM::VLD2d32wb_fixed:
				2327	case ARM::VLD2q8wb_fixed:
				2328	case ARM::VLD2q16wb_fixed:
				2329	case ARM::VLD2q32wb_fixed:
				2330	case ARM::VLD2d8wb_register:
				2331	case ARM::VLD2d16wb_register:
				2332	case ARM::VLD2d32wb_register:
				2333	case ARM::VLD2q8wb_register:
				2334	case ARM::VLD2q16wb_register:
				2335	case ARM::VLD2q32wb_register:
				2336	case ARM::VLD2b8wb_fixed:
				2337	case ARM::VLD2b16wb_fixed:
				2338	case ARM::VLD2b32wb_fixed:
				2339	case ARM::VLD2b8wb_register:
				2340	case ARM::VLD2b16wb_register:
				2341	case ARM::VLD2b32wb_register:
Kevin Enderby	a69da35	2012-04-11 00:25:40 +0000	[diff] [blame]	2342	Inst.addOperand(MCOperand::CreateImm(0));
				2343	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2344	case ARM::VLD3d8_UPD:
				2345	case ARM::VLD3d16_UPD:
				2346	case ARM::VLD3d32_UPD:
				2347	case ARM::VLD3q8_UPD:
				2348	case ARM::VLD3q16_UPD:
				2349	case ARM::VLD3q32_UPD:
				2350	case ARM::VLD4d8_UPD:
				2351	case ARM::VLD4d16_UPD:
				2352	case ARM::VLD4d32_UPD:
				2353	case ARM::VLD4q8_UPD:
				2354	case ARM::VLD4q16_UPD:
				2355	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2356	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2357	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2358	break;
				2359	default:
				2360	break;
				2361	}
				2362
				2363	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2364	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2365	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2366
				2367	// AddrMode6 Offset (register)
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2368	switch (Inst.getOpcode()) {
				2369	default:
				2370	// The below have been updated to have explicit am6offset split
				2371	// between fixed and register offset. For those instructions not
				2372	// yet updated, we need to add an additional reg0 operand for the
				2373	// fixed variant.
				2374	//
				2375	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2376	if (Rm == 0xd) {
				2377	Inst.addOperand(MCOperand::CreateReg(0));
				2378	break;
				2379	}
				2380	// Fall through to handle the register offset variant.
				2381	case ARM::VLD1d8wb_fixed:
				2382	case ARM::VLD1d16wb_fixed:
				2383	case ARM::VLD1d32wb_fixed:
				2384	case ARM::VLD1d64wb_fixed:
Owen Anderson	04b12a4	2011-10-27 22:53:10 +0000	[diff] [blame]	2385	case ARM::VLD1d8Twb_fixed:
				2386	case ARM::VLD1d16Twb_fixed:
				2387	case ARM::VLD1d32Twb_fixed:
				2388	case ARM::VLD1d64Twb_fixed:
Owen Anderson	fb6ab2b	2011-10-31 17:17:32 +0000	[diff] [blame]	2389	case ARM::VLD1d8Qwb_fixed:
				2390	case ARM::VLD1d16Qwb_fixed:
				2391	case ARM::VLD1d32Qwb_fixed:
				2392	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2393	case ARM::VLD1d8wb_register:
				2394	case ARM::VLD1d16wb_register:
				2395	case ARM::VLD1d32wb_register:
				2396	case ARM::VLD1d64wb_register:
				2397	case ARM::VLD1q8wb_fixed:
				2398	case ARM::VLD1q16wb_fixed:
				2399	case ARM::VLD1q32wb_fixed:
				2400	case ARM::VLD1q64wb_fixed:
				2401	case ARM::VLD1q8wb_register:
				2402	case ARM::VLD1q16wb_register:
				2403	case ARM::VLD1q32wb_register:
				2404	case ARM::VLD1q64wb_register:
				2405	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2406	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2407	// increment and we need to add the register operand to the instruction.
				2408	if (Rm != 0xD && Rm != 0xF &&
				2409	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2410	return MCDisassembler::Fail;
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2411	break;
Kevin Enderby	a69da35	2012-04-11 00:25:40 +0000	[diff] [blame]	2412	case ARM::VLD2d8wb_fixed:
				2413	case ARM::VLD2d16wb_fixed:
				2414	case ARM::VLD2d32wb_fixed:
				2415	case ARM::VLD2b8wb_fixed:
				2416	case ARM::VLD2b16wb_fixed:
				2417	case ARM::VLD2b32wb_fixed:
				2418	case ARM::VLD2q8wb_fixed:
				2419	case ARM::VLD2q16wb_fixed:
				2420	case ARM::VLD2q32wb_fixed:
				2421	break;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2422	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2423
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2424	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2425	}
				2426
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2427	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2428	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2429	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2430
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2431	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2432	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2433	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2434	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2435	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2436	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2437
				2438	// Writeback Operand
				2439	switch (Inst.getOpcode()) {
Jim Grosbach	4334e03	2011-10-31 21:50:31 +0000	[diff] [blame]	2440	case ARM::VST1d8wb_fixed:
				2441	case ARM::VST1d16wb_fixed:
				2442	case ARM::VST1d32wb_fixed:
				2443	case ARM::VST1d64wb_fixed:
				2444	case ARM::VST1d8wb_register:
				2445	case ARM::VST1d16wb_register:
				2446	case ARM::VST1d32wb_register:
				2447	case ARM::VST1d64wb_register:
				2448	case ARM::VST1q8wb_fixed:
				2449	case ARM::VST1q16wb_fixed:
				2450	case ARM::VST1q32wb_fixed:
				2451	case ARM::VST1q64wb_fixed:
				2452	case ARM::VST1q8wb_register:
				2453	case ARM::VST1q16wb_register:
				2454	case ARM::VST1q32wb_register:
				2455	case ARM::VST1q64wb_register:
Jim Grosbach	d5ca201	2011-11-29 22:38:04 +0000	[diff] [blame]	2456	case ARM::VST1d8Twb_fixed:
				2457	case ARM::VST1d16Twb_fixed:
				2458	case ARM::VST1d32Twb_fixed:
				2459	case ARM::VST1d64Twb_fixed:
				2460	case ARM::VST1d8Twb_register:
				2461	case ARM::VST1d16Twb_register:
				2462	case ARM::VST1d32Twb_register:
				2463	case ARM::VST1d64Twb_register:
Jim Grosbach	4c7edb3	2011-11-29 22:58:48 +0000	[diff] [blame]	2464	case ARM::VST1d8Qwb_fixed:
				2465	case ARM::VST1d16Qwb_fixed:
				2466	case ARM::VST1d32Qwb_fixed:
				2467	case ARM::VST1d64Qwb_fixed:
				2468	case ARM::VST1d8Qwb_register:
				2469	case ARM::VST1d16Qwb_register:
				2470	case ARM::VST1d32Qwb_register:
				2471	case ARM::VST1d64Qwb_register:
Jim Grosbach	bb3a2e4	2011-12-14 21:32:11 +0000	[diff] [blame]	2472	case ARM::VST2d8wb_fixed:
				2473	case ARM::VST2d16wb_fixed:
				2474	case ARM::VST2d32wb_fixed:
				2475	case ARM::VST2d8wb_register:
				2476	case ARM::VST2d16wb_register:
				2477	case ARM::VST2d32wb_register:
				2478	case ARM::VST2q8wb_fixed:
				2479	case ARM::VST2q16wb_fixed:
				2480	case ARM::VST2q32wb_fixed:
				2481	case ARM::VST2q8wb_register:
				2482	case ARM::VST2q16wb_register:
				2483	case ARM::VST2q32wb_register:
				2484	case ARM::VST2b8wb_fixed:
				2485	case ARM::VST2b16wb_fixed:
				2486	case ARM::VST2b32wb_fixed:
				2487	case ARM::VST2b8wb_register:
				2488	case ARM::VST2b16wb_register:
				2489	case ARM::VST2b32wb_register:
Kevin Enderby	b318cc1	2012-04-11 22:40:17 +0000	[diff] [blame]	2490	if (Rm == 0xF)
				2491	return MCDisassembler::Fail;
Kevin Enderby	f0586f0	2012-03-21 20:54:32 +0000	[diff] [blame]	2492	Inst.addOperand(MCOperand::CreateImm(0));
				2493	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2494	case ARM::VST3d8_UPD:
				2495	case ARM::VST3d16_UPD:
				2496	case ARM::VST3d32_UPD:
				2497	case ARM::VST3q8_UPD:
				2498	case ARM::VST3q16_UPD:
				2499	case ARM::VST3q32_UPD:
				2500	case ARM::VST4d8_UPD:
				2501	case ARM::VST4d16_UPD:
				2502	case ARM::VST4d32_UPD:
				2503	case ARM::VST4q8_UPD:
				2504	case ARM::VST4q16_UPD:
				2505	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2506	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2507	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2508	break;
				2509	default:
				2510	break;
				2511	}
				2512
				2513	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2514	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2515	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2516
				2517	// AddrMode6 Offset (register)
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2518	switch (Inst.getOpcode()) {
				2519	default:
				2520	if (Rm == 0xD)
				2521	Inst.addOperand(MCOperand::CreateReg(0));
				2522	else if (Rm != 0xF) {
				2523	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2524	return MCDisassembler::Fail;
				2525	}
				2526	break;
				2527	case ARM::VST1d8wb_fixed:
				2528	case ARM::VST1d16wb_fixed:
				2529	case ARM::VST1d32wb_fixed:
				2530	case ARM::VST1d64wb_fixed:
				2531	case ARM::VST1q8wb_fixed:
				2532	case ARM::VST1q16wb_fixed:
				2533	case ARM::VST1q32wb_fixed:
				2534	case ARM::VST1q64wb_fixed:
Kevin Enderby	f0586f0	2012-03-21 20:54:32 +0000	[diff] [blame]	2535	case ARM::VST1d8Twb_fixed:
				2536	case ARM::VST1d16Twb_fixed:
				2537	case ARM::VST1d32Twb_fixed:
				2538	case ARM::VST1d64Twb_fixed:
				2539	case ARM::VST1d8Qwb_fixed:
				2540	case ARM::VST1d16Qwb_fixed:
				2541	case ARM::VST1d32Qwb_fixed:
				2542	case ARM::VST1d64Qwb_fixed:
				2543	case ARM::VST2d8wb_fixed:
				2544	case ARM::VST2d16wb_fixed:
				2545	case ARM::VST2d32wb_fixed:
				2546	case ARM::VST2q8wb_fixed:
				2547	case ARM::VST2q16wb_fixed:
				2548	case ARM::VST2q32wb_fixed:
				2549	case ARM::VST2b8wb_fixed:
				2550	case ARM::VST2b16wb_fixed:
				2551	case ARM::VST2b32wb_fixed:
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2552	break;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2553	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2554
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2555
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2556	// First input register
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2557	switch (Inst.getOpcode()) {
				2558	case ARM::VST1q16:
				2559	case ARM::VST1q32:
				2560	case ARM::VST1q64:
				2561	case ARM::VST1q8:
				2562	case ARM::VST1q16wb_fixed:
				2563	case ARM::VST1q16wb_register:
				2564	case ARM::VST1q32wb_fixed:
				2565	case ARM::VST1q32wb_register:
				2566	case ARM::VST1q64wb_fixed:
				2567	case ARM::VST1q64wb_register:
				2568	case ARM::VST1q8wb_fixed:
				2569	case ARM::VST1q8wb_register:
				2570	case ARM::VST2d16:
				2571	case ARM::VST2d32:
				2572	case ARM::VST2d8:
				2573	case ARM::VST2d16wb_fixed:
				2574	case ARM::VST2d16wb_register:
				2575	case ARM::VST2d32wb_fixed:
				2576	case ARM::VST2d32wb_register:
				2577	case ARM::VST2d8wb_fixed:
				2578	case ARM::VST2d8wb_register:
				2579	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2580	return MCDisassembler::Fail;
				2581	break;
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	2582	case ARM::VST2b16:
				2583	case ARM::VST2b32:
				2584	case ARM::VST2b8:
				2585	case ARM::VST2b16wb_fixed:
				2586	case ARM::VST2b16wb_register:
				2587	case ARM::VST2b32wb_fixed:
				2588	case ARM::VST2b32wb_register:
				2589	case ARM::VST2b8wb_fixed:
				2590	case ARM::VST2b8wb_register:
				2591	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2592	return MCDisassembler::Fail;
				2593	break;
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2594	default:
				2595	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2596	return MCDisassembler::Fail;
				2597	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2598
				2599	// Second input register
				2600	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2601	case ARM::VST3d8:
				2602	case ARM::VST3d16:
				2603	case ARM::VST3d32:
				2604	case ARM::VST3d8_UPD:
				2605	case ARM::VST3d16_UPD:
				2606	case ARM::VST3d32_UPD:
				2607	case ARM::VST4d8:
				2608	case ARM::VST4d16:
				2609	case ARM::VST4d32:
				2610	case ARM::VST4d8_UPD:
				2611	case ARM::VST4d16_UPD:
				2612	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2613	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2614	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2615	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2616	case ARM::VST3q8:
				2617	case ARM::VST3q16:
				2618	case ARM::VST3q32:
				2619	case ARM::VST3q8_UPD:
				2620	case ARM::VST3q16_UPD:
				2621	case ARM::VST3q32_UPD:
				2622	case ARM::VST4q8:
				2623	case ARM::VST4q16:
				2624	case ARM::VST4q32:
				2625	case ARM::VST4q8_UPD:
				2626	case ARM::VST4q16_UPD:
				2627	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2628	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2629	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2630	break;
				2631	default:
				2632	break;
				2633	}
				2634
				2635	// Third input register
				2636	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2637	case ARM::VST3d8:
				2638	case ARM::VST3d16:
				2639	case ARM::VST3d32:
				2640	case ARM::VST3d8_UPD:
				2641	case ARM::VST3d16_UPD:
				2642	case ARM::VST3d32_UPD:
				2643	case ARM::VST4d8:
				2644	case ARM::VST4d16:
				2645	case ARM::VST4d32:
				2646	case ARM::VST4d8_UPD:
				2647	case ARM::VST4d16_UPD:
				2648	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2649	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2650	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2651	break;
				2652	case ARM::VST3q8:
				2653	case ARM::VST3q16:
				2654	case ARM::VST3q32:
				2655	case ARM::VST3q8_UPD:
				2656	case ARM::VST3q16_UPD:
				2657	case ARM::VST3q32_UPD:
				2658	case ARM::VST4q8:
				2659	case ARM::VST4q16:
				2660	case ARM::VST4q32:
				2661	case ARM::VST4q8_UPD:
				2662	case ARM::VST4q16_UPD:
				2663	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2664	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2665	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2666	break;
				2667	default:
				2668	break;
				2669	}
				2670
				2671	// Fourth input register
				2672	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2673	case ARM::VST4d8:
				2674	case ARM::VST4d16:
				2675	case ARM::VST4d32:
				2676	case ARM::VST4d8_UPD:
				2677	case ARM::VST4d16_UPD:
				2678	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2679	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2680	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2681	break;
				2682	case ARM::VST4q8:
				2683	case ARM::VST4q16:
				2684	case ARM::VST4q32:
				2685	case ARM::VST4q8_UPD:
				2686	case ARM::VST4q16_UPD:
				2687	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2688	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2689	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2690	break;
				2691	default:
				2692	break;
				2693	}
				2694
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2695	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2696	}
				2697
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2698	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2699	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2700	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2701
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2702	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2703	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2704	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2705	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2706	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2707	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2708
Tim Northover	24b9f25	2012-09-06 15:27:12 +0000	[diff] [blame]	2709	if (size == 0 && align == 1)
				2710	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2711	align *= (1 << size);
				2712
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2713	switch (Inst.getOpcode()) {
				2714	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2715	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2716	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2717	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2718	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2719	return MCDisassembler::Fail;
				2720	break;
				2721	default:
				2722	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2723	return MCDisassembler::Fail;
				2724	break;
				2725	}
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2726	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2727	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2728	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2729	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2730
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2731	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2732	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2733	Inst.addOperand(MCOperand::CreateImm(align));
				2734
Jim Grosbach	096334e	2011-11-30 19:35:44 +0000	[diff] [blame]	2735	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2736	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2737	// increment and we need to add the register operand to the instruction.
				2738	if (Rm != 0xD && Rm != 0xF &&
				2739	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2740	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2741
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2742	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2743	}
				2744
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2745	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2746	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2747	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2748
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2749	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2750	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2751	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2752	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2753	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2754	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2755	align = 2size;
				2756
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2757	switch (Inst.getOpcode()) {
				2758	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2759	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2760	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2761	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2762	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2763	return MCDisassembler::Fail;
				2764	break;
Jim Grosbach	4d0983a	2012-03-06 23:10:38 +0000	[diff] [blame]	2765	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2766	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2767	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2768	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2769	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2770	return MCDisassembler::Fail;
				2771	break;
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2772	default:
				2773	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2774	return MCDisassembler::Fail;
				2775	break;
				2776	}
Kevin Enderby	158c8a4	2012-03-06 18:33:12 +0000	[diff] [blame]	2777
				2778	if (Rm != 0xF)
				2779	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2780
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2781	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2782	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2783	Inst.addOperand(MCOperand::CreateImm(align));
				2784
Kevin Enderby	c5a2a33	2012-04-17 00:49:27 +0000	[diff] [blame]	2785	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2786	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2787	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2788	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2789
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2790	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2791	}
				2792
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2793	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2794	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2795	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2796
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2797	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2798	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2799	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2800	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2801	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2802
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2803	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2804	return MCDisassembler::Fail;
				2805	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2806	return MCDisassembler::Fail;
				2807	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2808	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2809	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2810	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2811	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2812	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2813
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2814	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2815	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2816	Inst.addOperand(MCOperand::CreateImm(0));
				2817
				2818	if (Rm == 0xD)
				2819	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2820	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2821	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2822	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2823	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2824
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2825	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2826	}
				2827
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2828	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2829	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2830	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2831
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2832	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2833	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2834	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2835	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2836	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2837	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2838	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2839
				2840	if (size == 0x3) {
Tim Northover	24b9f25	2012-09-06 15:27:12 +0000	[diff] [blame]	2841	if (align == 0)
				2842	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2843	size = 4;
				2844	align = 16;
				2845	} else {
				2846	if (size == 2) {
				2847	size = 1 << size;
				2848	align *= 8;
				2849	} else {
				2850	size = 1 << size;
				2851	align = 4size;
				2852	}
				2853	}
				2854
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2855	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2856	return MCDisassembler::Fail;
				2857	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2858	return MCDisassembler::Fail;
				2859	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2860	return MCDisassembler::Fail;
				2861	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2862	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2863	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2864	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2865	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2866	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2867
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2868	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2869	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2870	Inst.addOperand(MCOperand::CreateImm(align));
				2871
				2872	if (Rm == 0xD)
				2873	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2874	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2875	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2876	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2877	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2878
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2879	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2880	}
				2881
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2882	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2883	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2884	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2885	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2886
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2887	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2888	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2889	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				2890	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				2891	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				2892	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				2893	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				2894	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2895
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2896	if (Q) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2897	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2898	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2899	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2900	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2901	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2902	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2903
				2904	Inst.addOperand(MCOperand::CreateImm(imm));
				2905
				2906	switch (Inst.getOpcode()) {
				2907	case ARM::VORRiv4i16:
				2908	case ARM::VORRiv2i32:
				2909	case ARM::VBICiv4i16:
				2910	case ARM::VBICiv2i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2911	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2912	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2913	break;
				2914	case ARM::VORRiv8i16:
				2915	case ARM::VORRiv4i32:
				2916	case ARM::VBICiv8i16:
				2917	case ARM::VBICiv4i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2918	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2919	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2920	break;
				2921	default:
				2922	break;
				2923	}
				2924
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2925	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2926	}
				2927
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2928	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2929	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2930	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2931
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2932	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2933	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2934	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2935	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				2936	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2937
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2938	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2939	return MCDisassembler::Fail;
				2940	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				2941	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2942	Inst.addOperand(MCOperand::CreateImm(8 << size));
				2943
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2944	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2945	}
				2946
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2947	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2948	uint64_t Address, const void *Decoder) {
				2949	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2950	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2951	}
				2952
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2953	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2954	uint64_t Address, const void *Decoder) {
				2955	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2956	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2957	}
				2958
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2959	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2960	uint64_t Address, const void *Decoder) {
				2961	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2962	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2963	}
				2964
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2965	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2966	uint64_t Address, const void *Decoder) {
				2967	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	2968	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2969	}
				2970
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2971	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2972	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2973	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2974
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2975	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2976	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2977	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2978	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				2979	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2980	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				2981	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2982
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2983	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2984	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2985	if (op) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2986	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2987	return MCDisassembler::Fail; // Writeback
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2988	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2989
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2990	switch (Inst.getOpcode()) {
				2991	case ARM::VTBL2:
				2992	case ARM::VTBX2:
				2993	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				2994	return MCDisassembler::Fail;
				2995	break;
				2996	default:
				2997	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				2998	return MCDisassembler::Fail;
				2999	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3000
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3001	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3002	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3003
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3004	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3005	}
				3006
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3007	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3008	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3009	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3010
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3011	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3012	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3013
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3014	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3015	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3016
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3017	switch(Inst.getOpcode()) {
Owen Anderson	1af7f72	2011-08-26 19:39:26 +0000	[diff] [blame]	3018	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3019	return MCDisassembler::Fail;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3020	case ARM::tADR:
Owen Anderson	9f7e831	2011-08-26 21:47:57 +0000	[diff] [blame]	3021	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3022	case ARM::tADDrSPi:
				3023	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3024	break;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3025	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3026
				3027	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3028	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3029	}
				3030
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3031	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3032	uint64_t Address, const void *Decoder) {
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3033	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3034	true, 2, Inst, Decoder))
				3035	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3036	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3037	}
				3038
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3039	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3040	uint64_t Address, const void *Decoder) {
Kevin Enderby	3610a15	2012-05-04 22:09:52 +0000	[diff] [blame]	3041	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3042	true, 4, Inst, Decoder))
				3043	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3044	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3045	}
				3046
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3047	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3048	uint64_t Address, const void *Decoder) {
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3049	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
				3050	true, 2, Inst, Decoder))
				3051	Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3052	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3053	}
				3054
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3055	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3056	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3057	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3058
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3059	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3060	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3061
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3062	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3063	return MCDisassembler::Fail;
				3064	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3065	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3066
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3067	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3068	}
				3069
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3070	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3071	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3072	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3073
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3074	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3075	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3076
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3077	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3078	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3079	Inst.addOperand(MCOperand::CreateImm(imm));
				3080
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3081	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3082	}
				3083
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3084	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3085	uint64_t Address, const void *Decoder) {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	3086	unsigned imm = Val << 2;
				3087
				3088	Inst.addOperand(MCOperand::CreateImm(imm));
				3089	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3090
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3091	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3092	}
				3093
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3094	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3095	uint64_t Address, const void *Decoder) {
				3096	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b113ec5	2011-08-22 17:56:58 +0000	[diff] [blame]	3097	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3098
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3099	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3100	}
				3101
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3102	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3103	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3104	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3105
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3106	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3107	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3108	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3109
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3110	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3111	return MCDisassembler::Fail;
				3112	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3113	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3114	Inst.addOperand(MCOperand::CreateImm(imm));
				3115
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3116	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3117	}
				3118
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3119	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3120	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3121	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3122
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	3123	switch (Inst.getOpcode()) {
				3124	case ARM::t2PLDs:
				3125	case ARM::t2PLDWs:
				3126	case ARM::t2PLIs:
				3127	break;
				3128	default: {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3129	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson	31d485e	2011-09-23 21:07:25 +0000	[diff] [blame]	3130	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3131	return MCDisassembler::Fail;
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	3132	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3133	}
				3134
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3135	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3136	if (Rn == 0xF) {
				3137	switch (Inst.getOpcode()) {
				3138	case ARM::t2LDRBs:
				3139	Inst.setOpcode(ARM::t2LDRBpci);
				3140	break;
				3141	case ARM::t2LDRHs:
				3142	Inst.setOpcode(ARM::t2LDRHpci);
				3143	break;
				3144	case ARM::t2LDRSHs:
				3145	Inst.setOpcode(ARM::t2LDRSHpci);
				3146	break;
				3147	case ARM::t2LDRSBs:
				3148	Inst.setOpcode(ARM::t2LDRSBpci);
				3149	break;
				3150	case ARM::t2PLDs:
				3151	Inst.setOpcode(ARM::t2PLDi12);
				3152	Inst.addOperand(MCOperand::CreateReg(ARM::PC));
				3153	break;
				3154	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3155	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3156	}
				3157
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3158	int imm = fieldFromInstruction(Insn, 0, 12);
				3159	if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3160	Inst.addOperand(MCOperand::CreateImm(imm));
				3161
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3162	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3163	}
				3164
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3165	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3166	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3167	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3168	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3169	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3170
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3171	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3172	}
				3173
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3174	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3175	uint64_t Address, const void *Decoder) {
Jiangning Liu	fd652df	2012-08-02 08:29:50 +0000	[diff] [blame]	3176	if (Val == 0)
				3177	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3178	else {
				3179	int imm = Val & 0xFF;
				3180
				3181	if (!(Val & 0x100)) imm *= -1;
Richard Smith	1144af3	2012-08-24 23:29:28 +0000	[diff] [blame]	3182	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	fd652df	2012-08-02 08:29:50 +0000	[diff] [blame]	3183	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3184
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3185	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3186	}
				3187
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3188	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3189	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3190	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3191
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3192	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3193	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3194
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3195	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3196	return MCDisassembler::Fail;
				3197	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3198	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3199
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3200	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3201	}
				3202
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3203	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	3204	uint64_t Address, const void *Decoder) {
				3205	DecodeStatus S = MCDisassembler::Success;
				3206
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3207	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3208	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	3209
				3210	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3211	return MCDisassembler::Fail;
				3212
				3213	Inst.addOperand(MCOperand::CreateImm(imm));
				3214
				3215	return S;
				3216	}
				3217
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3218	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3219	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3220	int imm = Val & 0xFF;
Owen Anderson	705b48f	2011-09-16 21:08:33 +0000	[diff] [blame]	3221	if (Val == 0)
				3222	imm = INT32_MIN;
				3223	else if (!(Val & 0x100))
				3224	imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3225	Inst.addOperand(MCOperand::CreateImm(imm));
				3226
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3227	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3228	}
				3229
				3230
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3231	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3232	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3233	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3234
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3235	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3236	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3237
				3238	// Some instructions always use an additive offset.
				3239	switch (Inst.getOpcode()) {
				3240	case ARM::t2LDRT:
				3241	case ARM::t2LDRBT:
				3242	case ARM::t2LDRHT:
				3243	case ARM::t2LDRSBT:
				3244	case ARM::t2LDRSHT:
Owen Anderson	ecd1c55	2011-09-19 18:07:10 +0000	[diff] [blame]	3245	case ARM::t2STRT:
				3246	case ARM::t2STRBT:
				3247	case ARM::t2STRHT:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3248	imm \|= 0x100;
				3249	break;
				3250	default:
				3251	break;
				3252	}
				3253
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3254	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3255	return MCDisassembler::Fail;
				3256	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3257	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3258
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3259	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3260	}
				3261
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3262	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3263	uint64_t Address, const void *Decoder) {
				3264	DecodeStatus S = MCDisassembler::Success;
				3265
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3266	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3267	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3268	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3269	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3270	addr \|= Rn << 9;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3271	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3272
				3273	if (!load) {
				3274	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3275	return MCDisassembler::Fail;
				3276	}
				3277
Owen Anderson	e4f2df9	2011-09-16 22:42:36 +0000	[diff] [blame]	3278	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3279	return MCDisassembler::Fail;
				3280
				3281	if (load) {
				3282	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3283	return MCDisassembler::Fail;
				3284	}
				3285
				3286	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3287	return MCDisassembler::Fail;
				3288
				3289	return S;
				3290	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3291
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3292	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3293	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3294	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3295
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3296	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3297	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3298
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3299	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3300	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3301	Inst.addOperand(MCOperand::CreateImm(imm));
				3302
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3303	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3304	}
				3305
				3306
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3307	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3308	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3309	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3310
				3311	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3312	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3313	Inst.addOperand(MCOperand::CreateImm(imm));
				3314
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3315	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3316	}
				3317
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3318	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3319	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3320	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3321
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3322	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3323	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3324	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3325
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3326	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3327	return MCDisassembler::Fail;
Jim Grosbach	bb32f1d	2012-04-27 23:51:33 +0000	[diff] [blame]	3328	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3329	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3330	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3331	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3332	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3333
				3334	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3335	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3336	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3337	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3338	}
				3339
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3340	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3341	}
				3342
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3343	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3344	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3345	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3346	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3347
				3348	Inst.addOperand(MCOperand::CreateImm(imod));
				3349	Inst.addOperand(MCOperand::CreateImm(flags));
				3350
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3351	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3352	}
				3353
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3354	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3355	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3356	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3357	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3358	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3359
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	3360	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3361	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3362	Inst.addOperand(MCOperand::CreateImm(add));
				3363
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3364	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3365	}
				3366
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3367	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3368	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3369	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3370	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3371	// the encoded instruction. So here change to I1 and I2 values via:
				3372	// I1 = NOT(J1 EOR S);
				3373	// I2 = NOT(J2 EOR S);
				3374	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3375	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3376	unsigned S = (Val >> 23) & 1;
				3377	unsigned J1 = (Val >> 22) & 1;
				3378	unsigned J2 = (Val >> 21) & 1;
				3379	unsigned I1 = !(J1 ^ S);
				3380	unsigned I2 = !(J2 ^ S);
				3381	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3382	int imm32 = SignExtend32<25>(tmp << 1);
				3383
Jim Grosbach	01817c3	2011-10-20 17:28:20 +0000	[diff] [blame]	3384	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3385	(Address & ~2u) + imm32 + 4,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	3386	true, 4, Inst, Decoder))
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3387	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3388	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3389	}
				3390
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3391	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3392	uint64_t Address, const void *Decoder) {
				3393	if (Val == 0xA \|\| Val == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3394	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3395
				3396	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3397	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3398	}
				3399
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3400	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3401	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	3402	uint64_t Address, const void *Decoder) {
				3403	DecodeStatus S = MCDisassembler::Success;
				3404
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3405	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3406	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	3407
				3408	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3409	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3410	return MCDisassembler::Fail;
				3411	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3412	return MCDisassembler::Fail;
				3413	return S;
				3414	}
				3415
				3416	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3417	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3418	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3419	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3420
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3421	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3422	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3423	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3424	switch (opc) {
				3425	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3426	return MCDisassembler::Fail;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3427	case 0xf3bf8f4:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3428	Inst.setOpcode(ARM::t2DSB);
				3429	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3430	case 0xf3bf8f5:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3431	Inst.setOpcode(ARM::t2DMB);
				3432	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3433	case 0xf3bf8f6:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3434	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	6de3c6f	2011-09-07 17:55:19 +0000	[diff] [blame]	3435	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3436	}
				3437
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3438	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3439	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3440	}
				3441
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3442	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3443	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3444	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3445	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3446	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3447
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3448	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3449	return MCDisassembler::Fail;
				3450	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3451	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3452
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3453	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3454	}
				3455
				3456	// Decode a shifted immediate operand. These basically consist
				3457	// of an 8-bit value, and a 4-bit directive that specifies either
				3458	// a splat operation or a rotation.
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3459	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3460	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3461	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3462	if (ctrl == 0) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3463	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3464	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3465	switch (byte) {
				3466	case 0:
				3467	Inst.addOperand(MCOperand::CreateImm(imm));
				3468	break;
				3469	case 1:
				3470	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3471	break;
				3472	case 2:
				3473	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3474	break;
				3475	case 3:
				3476	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3477	(imm << 8) \| imm));
				3478	break;
				3479	}
				3480	} else {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3481	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3482	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3483	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3484	Inst.addOperand(MCOperand::CreateImm(imm));
				3485	}
				3486
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3487	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3488	}
				3489
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3490	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3491	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3492	uint64_t Address, const void *Decoder){
Richard Barton	c8f2fcc	2012-06-06 09:12:53 +0000	[diff] [blame]	3493	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3494	true, 2, Inst, Decoder))
Richard Barton	c8f2fcc	2012-06-06 09:12:53 +0000	[diff] [blame]	3495	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3496	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3497	}
				3498
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3499	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3500	uint64_t Address, const void *Decoder){
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3501	// Val is passed in as S:J1:J2:imm10:imm11
				3502	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3503	// the encoded instruction. So here change to I1 and I2 values via:
				3504	// I1 = NOT(J1 EOR S);
				3505	// I2 = NOT(J2 EOR S);
				3506	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3507	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3508	unsigned S = (Val >> 23) & 1;
				3509	unsigned J1 = (Val >> 22) & 1;
				3510	unsigned J2 = (Val >> 21) & 1;
				3511	unsigned I1 = !(J1 ^ S);
				3512	unsigned I2 = !(J2 ^ S);
				3513	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3514	int imm32 = SignExtend32<25>(tmp << 1);
				3515
				3516	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	3517	true, 4, Inst, Decoder))
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3518	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3519	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3520	}
				3521
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3522	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3523	uint64_t Address, const void *Decoder) {
Jiangning Liu	c1b7ca5	2012-08-02 08:21:27 +0000	[diff] [blame]	3524	if (Val & ~0xf)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3525	return MCDisassembler::Fail;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3526
				3527	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3528	return MCDisassembler::Success;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3529	}
				3530
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3531	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3532	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3533	if (!Val) return MCDisassembler::Fail;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3534	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3535	return MCDisassembler::Success;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3536	}
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3537
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3538	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3539	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3540	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3541
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3542	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3543	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3544	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3545
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3546	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3547
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3548	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3549	return MCDisassembler::Fail;
				3550	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3551	return MCDisassembler::Fail;
				3552	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3553	return MCDisassembler::Fail;
				3554	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3555	return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3556
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3557	return S;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3558	}
				3559
				3560
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3561	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3562	uint64_t Address, const void *Decoder){
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3563	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3564
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3565	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3566	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				3567	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3568	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3569
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3570	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				3571	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3572
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3573	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
				3574	if (Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1) return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3575
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3576	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3577	return MCDisassembler::Fail;
				3578	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3579	return MCDisassembler::Fail;
				3580	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3581	return MCDisassembler::Fail;
				3582	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3583	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3584
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3585	return S;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3586	}
				3587
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3588	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3589	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3590	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3591
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3592	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3593	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3594	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3595	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3596	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3597	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3598
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3599	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3600
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3601	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3602	return MCDisassembler::Fail;
				3603	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3604	return MCDisassembler::Fail;
				3605	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3606	return MCDisassembler::Fail;
				3607	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3608	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3609
				3610	return S;
				3611	}
				3612
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3613	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3614	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3615	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3616
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3617	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3618	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3619	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3620	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3621	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3622	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				3623	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3624
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3625	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				3626	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3627
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3628	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3629	return MCDisassembler::Fail;
				3630	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3631	return MCDisassembler::Fail;
				3632	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3633	return MCDisassembler::Fail;
				3634	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3635	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3636
				3637	return S;
				3638	}
				3639
				3640
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3641	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3642	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3643	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3644
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3645	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3646	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3647	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3648	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3649	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3650	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3651
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3652	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3653
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3654	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3655	return MCDisassembler::Fail;
				3656	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3657	return MCDisassembler::Fail;
				3658	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3659	return MCDisassembler::Fail;
				3660	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3661	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3662
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3663	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3664	}
				3665
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3666	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3667	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3668	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3669
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3670	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3671	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3672	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3673	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3674	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3675	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3676
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3677	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3678
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3679	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3680	return MCDisassembler::Fail;
				3681	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3682	return MCDisassembler::Fail;
				3683	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3684	return MCDisassembler::Fail;
				3685	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3686	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3687
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3688	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3689	}
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3690
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3691	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3692	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3693	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3694
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3695	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3696	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3697	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3698	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3699	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3700
				3701	unsigned align = 0;
				3702	unsigned index = 0;
				3703	switch (size) {
				3704	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3705	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3706	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3707	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3708	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3709	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3710	break;
				3711	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3712	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3713	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3714	index = fieldFromInstruction(Insn, 6, 2);
				3715	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3716	align = 2;
				3717	break;
				3718	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3719	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3720	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3721	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	3722
				3723	switch (fieldFromInstruction(Insn, 4, 2)) {
				3724	case 0 :
				3725	align = 0; break;
				3726	case 3:
				3727	align = 4; break;
				3728	default:
				3729	return MCDisassembler::Fail;
				3730	}
				3731	break;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3732	}
				3733
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3734	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3735	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3736	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3737	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3738	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3739	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3740	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3741	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3742	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3743	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3744	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3745	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3746	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3747	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3748	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3749	}
				3750
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3751	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3752	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3753	Inst.addOperand(MCOperand::CreateImm(index));
				3754
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3755	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3756	}
				3757
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3758	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3759	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3760	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3761
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3762	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3763	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3764	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3765	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3766	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3767
				3768	unsigned align = 0;
				3769	unsigned index = 0;
				3770	switch (size) {
				3771	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3772	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3773	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3774	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3775	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3776	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3777	break;
				3778	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3779	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3780	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3781	index = fieldFromInstruction(Insn, 6, 2);
				3782	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3783	align = 2;
				3784	break;
				3785	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3786	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3787	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3788	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	3789
				3790	switch (fieldFromInstruction(Insn, 4, 2)) {
				3791	case 0:
				3792	align = 0; break;
				3793	case 3:
				3794	align = 4; break;
				3795	default:
				3796	return MCDisassembler::Fail;
				3797	}
				3798	break;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3799	}
				3800
				3801	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3802	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3803	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3804	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3805	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3806	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3807	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3808	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3809	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3810	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3811	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3812	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3813	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3814	}
				3815
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3816	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3817	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3818	Inst.addOperand(MCOperand::CreateImm(index));
				3819
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3820	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3821	}
				3822
				3823
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3824	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3825	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3826	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3827
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3828	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3829	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3830	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3831	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3832	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3833
				3834	unsigned align = 0;
				3835	unsigned index = 0;
				3836	unsigned inc = 1;
				3837	switch (size) {
				3838	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3839	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3840	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3841	index = fieldFromInstruction(Insn, 5, 3);
				3842	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3843	align = 2;
				3844	break;
				3845	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3846	index = fieldFromInstruction(Insn, 6, 2);
				3847	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3848	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3849	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3850	inc = 2;
				3851	break;
				3852	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3853	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3854	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3855	index = fieldFromInstruction(Insn, 7, 1);
				3856	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3857	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3858	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3859	inc = 2;
				3860	break;
				3861	}
				3862
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3863	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3864	return MCDisassembler::Fail;
				3865	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3866	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3867	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3868	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3869	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3870	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3871	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3872	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3873	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3874	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3875	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3876	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3877	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3878	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3879	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3880	}
				3881
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3882	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3883	return MCDisassembler::Fail;
				3884	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3885	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3886	Inst.addOperand(MCOperand::CreateImm(index));
				3887
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3888	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3889	}
				3890
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3891	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3892	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3893	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3894
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3895	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3896	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3897	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3898	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3899	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3900
				3901	unsigned align = 0;
				3902	unsigned index = 0;
				3903	unsigned inc = 1;
				3904	switch (size) {
				3905	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3906	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3907	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3908	index = fieldFromInstruction(Insn, 5, 3);
				3909	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3910	align = 2;
				3911	break;
				3912	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3913	index = fieldFromInstruction(Insn, 6, 2);
				3914	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3915	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3916	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3917	inc = 2;
				3918	break;
				3919	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3920	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3921	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3922	index = fieldFromInstruction(Insn, 7, 1);
				3923	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3924	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3925	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3926	inc = 2;
				3927	break;
				3928	}
				3929
				3930	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3931	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3932	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3933	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3934	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3935	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3936	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3937	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3938	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3939	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3940	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3941	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3942	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3943	}
				3944
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3945	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3946	return MCDisassembler::Fail;
				3947	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3948	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3949	Inst.addOperand(MCOperand::CreateImm(index));
				3950
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3951	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3952	}
				3953
				3954
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3955	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3956	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3957	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3958
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3959	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3960	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3961	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3962	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3963	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3964
				3965	unsigned align = 0;
				3966	unsigned index = 0;
				3967	unsigned inc = 1;
				3968	switch (size) {
				3969	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3970	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3971	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3972	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3973	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3974	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3975	break;
				3976	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3977	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3978	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3979	index = fieldFromInstruction(Insn, 6, 2);
				3980	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3981	inc = 2;
				3982	break;
				3983	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3984	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3985	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3986	index = fieldFromInstruction(Insn, 7, 1);
				3987	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3988	inc = 2;
				3989	break;
				3990	}
				3991
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3992	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3993	return MCDisassembler::Fail;
				3994	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3995	return MCDisassembler::Fail;
				3996	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				3997	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3998
				3999	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4000	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4001	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4002	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4003	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4004	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4005	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4006	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4007	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4008	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4009	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4010	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4011	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4012	}
				4013
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4014	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4015	return MCDisassembler::Fail;
				4016	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4017	return MCDisassembler::Fail;
				4018	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4019	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4020	Inst.addOperand(MCOperand::CreateImm(index));
				4021
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4022	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4023	}
				4024
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4025	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4026	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4027	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4028
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4029	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4030	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4031	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4032	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4033	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4034
				4035	unsigned align = 0;
				4036	unsigned index = 0;
				4037	unsigned inc = 1;
				4038	switch (size) {
				4039	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4040	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4041	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4042	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4043	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4044	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4045	break;
				4046	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4047	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4048	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4049	index = fieldFromInstruction(Insn, 6, 2);
				4050	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4051	inc = 2;
				4052	break;
				4053	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4054	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4055	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4056	index = fieldFromInstruction(Insn, 7, 1);
				4057	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4058	inc = 2;
				4059	break;
				4060	}
				4061
				4062	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4063	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4064	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4065	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4066	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4067	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4068	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4069	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4070	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4071	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4072	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4073	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4074	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4075	}
				4076
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4077	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4078	return MCDisassembler::Fail;
				4079	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4080	return MCDisassembler::Fail;
				4081	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4082	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4083	Inst.addOperand(MCOperand::CreateImm(index));
				4084
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4085	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4086	}
				4087
				4088
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4089	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4090	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4091	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4092
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4093	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4094	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4095	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4096	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4097	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4098
				4099	unsigned align = 0;
				4100	unsigned index = 0;
				4101	unsigned inc = 1;
				4102	switch (size) {
				4103	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4104	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4105	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4106	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4107	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4108	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4109	break;
				4110	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4111	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4112	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4113	index = fieldFromInstruction(Insn, 6, 2);
				4114	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4115	inc = 2;
				4116	break;
				4117	case 2:
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	4118	switch (fieldFromInstruction(Insn, 4, 2)) {
				4119	case 0:
				4120	align = 0; break;
				4121	case 3:
				4122	return MCDisassembler::Fail;
				4123	default:
				4124	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4125	}
				4126
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4127	index = fieldFromInstruction(Insn, 7, 1);
				4128	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4129	inc = 2;
				4130	break;
				4131	}
				4132
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4133	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4134	return MCDisassembler::Fail;
				4135	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4136	return MCDisassembler::Fail;
				4137	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4138	return MCDisassembler::Fail;
				4139	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4140	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4141
				4142	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4143	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4144	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4145	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4146	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4147	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4148	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4149	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4150	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4151	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4152	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4153	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4154	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4155	}
				4156
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4157	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4158	return MCDisassembler::Fail;
				4159	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4160	return MCDisassembler::Fail;
				4161	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4162	return MCDisassembler::Fail;
				4163	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4164	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4165	Inst.addOperand(MCOperand::CreateImm(index));
				4166
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4167	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4168	}
				4169
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4170	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4171	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4172	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4173
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4174	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4175	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4176	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4177	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4178	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4179
				4180	unsigned align = 0;
				4181	unsigned index = 0;
				4182	unsigned inc = 1;
				4183	switch (size) {
				4184	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4185	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4186	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4187	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4188	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4189	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4190	break;
				4191	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4192	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4193	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4194	index = fieldFromInstruction(Insn, 6, 2);
				4195	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4196	inc = 2;
				4197	break;
				4198	case 2:
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	4199	switch (fieldFromInstruction(Insn, 4, 2)) {
				4200	case 0:
				4201	align = 0; break;
				4202	case 3:
				4203	return MCDisassembler::Fail;
				4204	default:
				4205	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4206	}
				4207
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4208	index = fieldFromInstruction(Insn, 7, 1);
				4209	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4210	inc = 2;
				4211	break;
				4212	}
				4213
				4214	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4215	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4216	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4217	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4218	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4219	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4220	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4221	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4222	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4223	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4224	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4225	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4226	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4227	}
				4228
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4229	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4230	return MCDisassembler::Fail;
				4231	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4232	return MCDisassembler::Fail;
				4233	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4234	return MCDisassembler::Fail;
				4235	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4236	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4237	Inst.addOperand(MCOperand::CreateImm(index));
				4238
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4239	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4240	}
				4241
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4242	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4243	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4244	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4245	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4246	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4247	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4248	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4249	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4250
				4251	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4252	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4253
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4254	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4255	return MCDisassembler::Fail;
				4256	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4257	return MCDisassembler::Fail;
				4258	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4259	return MCDisassembler::Fail;
				4260	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4261	return MCDisassembler::Fail;
				4262	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4263	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4264
				4265	return S;
				4266	}
				4267
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4268	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4269	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4270	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4271	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4272	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4273	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4274	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4275	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4276
				4277	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4278	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4279
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4280	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4281	return MCDisassembler::Fail;
				4282	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4283	return MCDisassembler::Fail;
				4284	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4285	return MCDisassembler::Fail;
				4286	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4287	return MCDisassembler::Fail;
				4288	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4289	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4290
				4291	return S;
				4292	}
Owen Anderson	8e1e60b	2011-08-22 23:44:04 +0000	[diff] [blame]	4293
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4294	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4295	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4296	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4297	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4298	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4299
				4300	if (pred == 0xF) {
				4301	pred = 0xE;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4302	S = MCDisassembler::SoftFail;
Owen Anderson	e234d02	2011-08-24 17:21:43 +0000	[diff] [blame]	4303	}
				4304
Richard Barton	4d2f077	2012-04-27 08:42:59 +0000	[diff] [blame]	4305	if (mask == 0x0) {
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4306	mask \|= 0x8;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4307	S = MCDisassembler::SoftFail;
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	4308	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4309
				4310	Inst.addOperand(MCOperand::CreateImm(pred));
				4311	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	4312	return S;
				4313	}
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4314
				4315	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4316	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4317	uint64_t Address, const void *Decoder) {
				4318	DecodeStatus S = MCDisassembler::Success;
				4319
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4320	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4321	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4322	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4323	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4324	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4325	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4326	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4327	bool writeback = (W == 1) \| (P == 0);
				4328
				4329	addr \|= (U << 8) \| (Rn << 9);
				4330
				4331	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4332	Check(S, MCDisassembler::SoftFail);
				4333	if (Rt == Rt2)
				4334	Check(S, MCDisassembler::SoftFail);
				4335
				4336	// Rt
				4337	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4338	return MCDisassembler::Fail;
				4339	// Rt2
				4340	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4341	return MCDisassembler::Fail;
				4342	// Writeback operand
				4343	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4344	return MCDisassembler::Fail;
				4345	// addr
				4346	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4347	return MCDisassembler::Fail;
				4348
				4349	return S;
				4350	}
				4351
				4352	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4353	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4354	uint64_t Address, const void *Decoder) {
				4355	DecodeStatus S = MCDisassembler::Success;
				4356
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4357	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4358	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4359	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4360	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4361	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4362	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4363	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4364	bool writeback = (W == 1) \| (P == 0);
				4365
				4366	addr \|= (U << 8) \| (Rn << 9);
				4367
				4368	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4369	Check(S, MCDisassembler::SoftFail);
				4370
				4371	// Writeback operand
				4372	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4373	return MCDisassembler::Fail;
				4374	// Rt
				4375	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4376	return MCDisassembler::Fail;
				4377	// Rt2
				4378	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4379	return MCDisassembler::Fail;
				4380	// addr
				4381	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4382	return MCDisassembler::Fail;
				4383
				4384	return S;
				4385	}
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4386
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4387	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4388	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4389	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4390	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4391	if (sign1 != sign2) return MCDisassembler::Fail;
				4392
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4393	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4394	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4395	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4396	Val \|= sign1 << 12;
				4397	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4398
				4399	return MCDisassembler::Success;
				4400	}
				4401
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4402	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	0afa009	2011-09-26 21:06:22 +0000	[diff] [blame]	4403	uint64_t Address,
				4404	const void *Decoder) {
				4405	DecodeStatus S = MCDisassembler::Success;
				4406
				4407	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4408	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4409	Inst.addOperand(MCOperand::CreateImm(Val));
				4410	return S;
				4411	}
				4412
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4413	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4414	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4415	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4416	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4417	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4418	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4419
				4420	if (pred == 0xF)
				4421	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4422
				4423	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	35ee7d2	2012-04-18 14:18:57 +0000	[diff] [blame]	4424
				4425	if (Rt == Rn \|\| Rn == Rt2)
				4426	S = MCDisassembler::SoftFail;
				4427
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4428	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4429	return MCDisassembler::Fail;
				4430	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4431	return MCDisassembler::Fail;
				4432	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4433	return MCDisassembler::Fail;
				4434	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4435	return MCDisassembler::Fail;
				4436
				4437	return S;
				4438	}
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4439
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4440	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4441	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4442	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4443	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4444	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4445	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4446	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4447	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4448
				4449	DecodeStatus S = MCDisassembler::Success;
				4450
				4451	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	22925d9	2011-11-15 20:30:41 +0000	[diff] [blame]	4452	if (!(imm & 0x38) && cmode == 0xF) {
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4453	Inst.setOpcode(ARM::VMOVv2f32);
				4454	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4455	}
				4456
				4457	if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
				4458
				4459	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4460	return MCDisassembler::Fail;
				4461	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4462	return MCDisassembler::Fail;
				4463	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4464
				4465	return S;
				4466	}
				4467
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4468	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4469	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4470	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4471	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4472	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4473	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4474	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4475	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4476
				4477	DecodeStatus S = MCDisassembler::Success;
				4478
				4479	// VMOVv4f32 is ambiguous with these decodings.
				4480	if (!(imm & 0x38) && cmode == 0xF) {
				4481	Inst.setOpcode(ARM::VMOVv4f32);
				4482	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4483	}
				4484
				4485	if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
				4486
				4487	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				4488	return MCDisassembler::Fail;
				4489	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				4490	return MCDisassembler::Fail;
				4491	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4492
				4493	return S;
				4494	}
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4495
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4496	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4497	uint64_t Address, const void *Decoder) {
				4498	DecodeStatus S = MCDisassembler::Success;
				4499
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4500	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				4501	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4502	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				4503	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				4504	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4505
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4506	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4507	S = MCDisassembler::SoftFail;
				4508
				4509	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4510	return MCDisassembler::Fail;
				4511	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4512	return MCDisassembler::Fail;
				4513	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				4514	return MCDisassembler::Fail;
				4515	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				4516	return MCDisassembler::Fail;
				4517	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				4518	return MCDisassembler::Fail;
				4519
				4520	return S;
				4521	}
				4522
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	4523	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				4524	uint64_t Address, const void *Decoder) {
				4525
				4526	DecodeStatus S = MCDisassembler::Success;
				4527
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4528	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				4529	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				4530	unsigned cop = fieldFromInstruction(Val, 8, 4);
				4531	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4532	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	4533
				4534	if ((cop & ~0x1) == 0xa)
				4535	return MCDisassembler::Fail;
				4536
				4537	if (Rt == Rt2)
				4538	S = MCDisassembler::SoftFail;
				4539
				4540	Inst.addOperand(MCOperand::CreateImm(cop));
				4541	Inst.addOperand(MCOperand::CreateImm(opc1));
				4542	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4543	return MCDisassembler::Fail;
				4544	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4545	return MCDisassembler::Fail;
				4546	Inst.addOperand(MCOperand::CreateImm(CRm));
				4547
				4548	return S;
				4549	}
				4550