Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / llvm / 71280b55a3406c7dd4215449bf4a3ab216e78ffd / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 6b86e41c45231909d067a4405d3e7a93d81c6579 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
50 raw_ostream &vStream) const;
51
52 /// getEDInfo - See MCDisassembler.
53 EDInstInfo *getEDInfo() const;
54private:
55};
56
57/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
58class ThumbDisassembler : public MCDisassembler {
59public:
60 /// Constructor - Initializes the disassembler.
61 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]62 ThumbDisassembler(const MCSubtargetInfo &STI) :
63 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]64 }
65
66 ~ThumbDisassembler() {
67 }
68
69 /// getInstruction - See MCDisassembler.
70 DecodeStatus getInstruction(MCInst &instr,
71 uint64_t &size,
72 const MemoryObject &region,
73 uint64_t address,
74 raw_ostream &vStream) const;
75
76 /// getEDInfo - See MCDisassembler.
77 EDInstInfo *getEDInfo() const;
78private:
79 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]80 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]81 void UpdateThumbVFPPredicate(MCInst&) const;
82};
83}
84
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]85static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]86 switch (In) {
87 case MCDisassembler::Success:
88 // Out stays the same.
89 return true;
90 case MCDisassembler::SoftFail:
91 Out = In;
92 return true;
93 case MCDisassembler::Fail:
94 Out = In;
95 return false;
96 }
97 return false;
98}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]99
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]100
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]101// Forward declare these because the autogenerated code will reference them.
102// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]103static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]106 unsigned RegNo, uint64_t Address,
107 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]109 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]121 unsigned RegNo,
122 uint64_t Address,
123 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]124static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]125 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]126
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]139
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]145 unsigned Insn,
146 uint64_t Address,
147 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]148static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]149 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
156
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 unsigned Insn,
159 uint64_t Adddress,
160 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]161static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
273 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]274static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]290static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]298static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
299 uint64_t Address, const void *Decoder);
300static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
301 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]302static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
303 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]304static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
306
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]307
308#include "ARMGenDisassemblerTables.inc"
309#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]310#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]311
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]312static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
313 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]314}
315
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]316static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
317 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]318}
319
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]320EDInstInfo *ARMDisassembler::getEDInfo() const {
321 return instInfoARM;
322}
323
324EDInstInfo *ThumbDisassembler::getEDInfo() const {
325 return instInfoARM;
326}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]328DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]329 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]330 uint64_t Address,
331 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]332 uint8_t bytes[4];
333
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]334 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
335 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
336
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]338 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
339 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]340 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]341 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]342
343 // Encoded as a small-endian 32-bit word in the stream.
344 uint32_t insn = (bytes[3] << 24) |
345 (bytes[2] << 16) |
346 (bytes[1] << 8) |
347 (bytes[0] << 0);
348
349 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]350 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]351 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]352 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]353 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]354 }
355
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]356 // VFP and NEON instructions, similarly, are shared between ARM
357 // and Thumb modes.
358 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]359 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]360 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]361 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]362 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]363 }
364
365 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]366 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]367 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]368 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 // Add a fake predicate operand, because we share these instruction
370 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]371 if (!DecodePredicateOperand(MI, 0xE, Address, this))
372 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]373 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]374 }
375
376 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]377 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]378 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]379 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]380 // Add a fake predicate operand, because we share these instruction
381 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]382 if (!DecodePredicateOperand(MI, 0xE, Address, this))
383 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]384 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]385 }
386
387 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]388 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]389 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]390 Size = 4;
391 // Add a fake predicate operand, because we share these instruction
392 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]393 if (!DecodePredicateOperand(MI, 0xE, Address, this))
394 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]395 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]396 }
397
398 MI.clear();
399
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]400 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]401 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]402}
403
404namespace llvm {
405extern MCInstrDesc ARMInsts[];
406}
407
408// Thumb1 instructions don't have explicit S bits. Rather, they
409// implicitly set CPSR. Since it's not represented in the encoding, the
410// auto-generated decoder won't inject the CPSR operand. We need to fix
411// that as a post-pass.
412static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
413 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]414 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]416 for (unsigned i = 0; i < NumOps; ++i, ++I) {
417 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]418 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]419 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]420 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
421 return;
422 }
423 }
424
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]425 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]426}
427
428// Most Thumb instructions don't have explicit predicates in the
429// encoding, but rather get their predicates from IT context. We need
430// to fix up the predicate operands using this context information as a
431// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]432MCDisassembler::DecodeStatus
433ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]434 MCDisassembler::DecodeStatus S = Success;
435
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]436 // A few instructions actually have predicates encoded in them. Don't
437 // try to overwrite it if we're seeing one of those.
438 switch (MI.getOpcode()) {
439 case ARM::tBcc:
440 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]441 case ARM::tCBZ:
442 case ARM::tCBNZ:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]443 // Some instructions (mostly conditional branches) are not
444 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]445 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]446 S = SoftFail;
447 else
448 return Success;
449 break;
450 case ARM::tB:
451 case ARM::t2B:
452 // Some instructions (mostly unconditional branches) can
453 // only appears at the end of, or outside of, an IT.
454 if (ITBlock.size() > 1)
455 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]456 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]457 default:
458 break;
459 }
460
461 // If we're in an IT block, base the predicate on that. Otherwise,
462 // assume a predicate of AL.
463 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]464 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]465 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]466 if (CC == 0xF)
467 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]468 ITBlock.pop_back();
469 } else
470 CC = ARMCC::AL;
471
472 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]473 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]474 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]475 for (unsigned i = 0; i < NumOps; ++i, ++I) {
476 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]477 if (OpInfo[i].isPredicate()) {
478 I = MI.insert(I, MCOperand::CreateImm(CC));
479 ++I;
480 if (CC == ARMCC::AL)
481 MI.insert(I, MCOperand::CreateReg(0));
482 else
483 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]484 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]485 }
486 }
487
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]488 I = MI.insert(I, MCOperand::CreateImm(CC));
489 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]490 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]491 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]492 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]493 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]494
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]495 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]496}
497
498// Thumb VFP instructions are a special case. Because we share their
499// encodings between ARM and Thumb modes, and they are predicable in ARM
500// mode, the auto-generated decoder will give them an (incorrect)
501// predicate operand. We need to rewrite these operands based on the IT
502// context as a post-pass.
503void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
504 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]505 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]506 CC = ITBlock.back();
507 ITBlock.pop_back();
508 } else
509 CC = ARMCC::AL;
510
511 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
512 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]513 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
514 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]515 if (OpInfo[i].isPredicate() ) {
516 I->setImm(CC);
517 ++I;
518 if (CC == ARMCC::AL)
519 I->setReg(0);
520 else
521 I->setReg(ARM::CPSR);
522 return;
523 }
524 }
525}
526
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]527DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]528 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]529 uint64_t Address,
530 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]531 uint8_t bytes[4];
532
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]533 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
534 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
535
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]536 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]537 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
538 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]539 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]540 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]541
542 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]543 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]544 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]545 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]546 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]547 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]548 }
549
550 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]551 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]552 if (result) {
553 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]554 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]555 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]556 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]557 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]558 }
559
560 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]561 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]562 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]563 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]564 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]565
566 // If we find an IT instruction, we need to parse its condition
567 // code and mask operands so that we can apply them correctly
568 // to the subsequent instructions.
569 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]570 // Nested IT blocks are UNPREDICTABLE.
571 if (!ITBlock.empty())
572 return MCDisassembler::SoftFail;
573
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]574 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]575 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]576 unsigned Mask = MI.getOperand(1).getImm();
577 unsigned CondBit0 = Mask >> 4 & 1;
578 unsigned NumTZ = CountTrailingZeros_32(Mask);
579 assert(NumTZ <= 3 && "Invalid IT mask!");
580 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
581 bool T = ((Mask >> Pos) & 1) == CondBit0;
582 if (T)
583 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]584 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]585 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]586 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]587
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]588 ITBlock.push_back(firstcond);
589 }
590
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]591 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]592 }
593
594 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]595 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
596 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]597 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]598 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]599
600 uint32_t insn32 = (bytes[3] << 8) |
601 (bytes[2] << 0) |
602 (bytes[1] << 24) |
603 (bytes[0] << 16);
604 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]605 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]606 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]607 Size = 4;
608 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]609 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]610 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]611 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]612 }
613
614 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]615 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]616 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]617 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]618 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]619 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]620 }
621
622 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]623 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]624 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]625 Size = 4;
626 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]627 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]628 }
629
630 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]631 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]632 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]633 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]634 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]635 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]636 }
637
638 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
639 MI.clear();
640 uint32_t NEONLdStInsn = insn32;
641 NEONLdStInsn &= 0xF0FFFFFF;
642 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]643 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]644 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]645 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]646 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]647 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]648 }
649 }
650
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]651 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]652 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]653 uint32_t NEONDataInsn = insn32;
654 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
655 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
656 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]657 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]658 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]659 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]660 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]661 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]662 }
663 }
664
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]665 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]666 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]667}
668
669
670extern "C" void LLVMInitializeARMDisassembler() {
671 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
672 createARMDisassembler);
673 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
674 createThumbDisassembler);
675}
676
677static const unsigned GPRDecoderTable[] = {
678 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
679 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
680 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
681 ARM::R12, ARM::SP, ARM::LR, ARM::PC
682};
683
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]684static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]685 uint64_t Address, const void *Decoder) {
686 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]687 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]688
689 unsigned Register = GPRDecoderTable[RegNo];
690 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]691 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]692}
693
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]694static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]695DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
696 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]697 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]698 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
699}
700
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]701static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]702 uint64_t Address, const void *Decoder) {
703 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]704 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]705 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
706}
707
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]708static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]709 uint64_t Address, const void *Decoder) {
710 unsigned Register = 0;
711 switch (RegNo) {
712 case 0:
713 Register = ARM::R0;
714 break;
715 case 1:
716 Register = ARM::R1;
717 break;
718 case 2:
719 Register = ARM::R2;
720 break;
721 case 3:
722 Register = ARM::R3;
723 break;
724 case 9:
725 Register = ARM::R9;
726 break;
727 case 12:
728 Register = ARM::R12;
729 break;
730 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]731 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]732 }
733
734 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]735 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]736}
737
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]738static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]739 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]740 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]741 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
742}
743
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]744static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]745 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
746 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
747 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
748 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
749 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
750 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
751 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
752 ARM::S28, ARM::S29, ARM::S30, ARM::S31
753};
754
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]755static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]756 uint64_t Address, const void *Decoder) {
757 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]758 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]759
760 unsigned Register = SPRDecoderTable[RegNo];
761 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]762 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]763}
764
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]765static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]766 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
767 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
768 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
769 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
770 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
771 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
772 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
773 ARM::D28, ARM::D29, ARM::D30, ARM::D31
774};
775
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]776static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777 uint64_t Address, const void *Decoder) {
778 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]779 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]780
781 unsigned Register = DPRDecoderTable[RegNo];
782 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]783 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]784}
785
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]786static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]787 uint64_t Address, const void *Decoder) {
788 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]789 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]790 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
791}
792
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]793static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]794DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
795 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]796 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]797 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]798 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
799}
800
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]801static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]802 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
803 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
804 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
805 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
806};
807
808
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]809static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]810 uint64_t Address, const void *Decoder) {
811 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]812 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]813 RegNo >>= 1;
814
815 unsigned Register = QPRDecoderTable[RegNo];
816 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]817 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]818}
819
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]820static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]821 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]822 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]823 // AL predicate is not allowed on Thumb1 branches.
824 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]825 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]826 Inst.addOperand(MCOperand::CreateImm(Val));
827 if (Val == ARMCC::AL) {
828 Inst.addOperand(MCOperand::CreateReg(0));
829 } else
830 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]831 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]832}
833
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]834static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]835 uint64_t Address, const void *Decoder) {
836 if (Val)
837 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
838 else
839 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]840 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]841}
842
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]843static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]844 uint64_t Address, const void *Decoder) {
845 uint32_t imm = Val & 0xFF;
846 uint32_t rot = (Val & 0xF00) >> 7;
847 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
848 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]849 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]850}
851
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]852static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]853 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]854 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]855
856 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
857 unsigned type = fieldFromInstruction32(Val, 5, 2);
858 unsigned imm = fieldFromInstruction32(Val, 7, 5);
859
860 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
862 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]863
864 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
865 switch (type) {
866 case 0:
867 Shift = ARM_AM::lsl;
868 break;
869 case 1:
870 Shift = ARM_AM::lsr;
871 break;
872 case 2:
873 Shift = ARM_AM::asr;
874 break;
875 case 3:
876 Shift = ARM_AM::ror;
877 break;
878 }
879
880 if (Shift == ARM_AM::ror && imm == 0)
881 Shift = ARM_AM::rrx;
882
883 unsigned Op = Shift | (imm << 3);
884 Inst.addOperand(MCOperand::CreateImm(Op));
885
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]886 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]887}
888
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]889static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]890 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]891 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]892
893 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
894 unsigned type = fieldFromInstruction32(Val, 5, 2);
895 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
896
897 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]898 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
899 return MCDisassembler::Fail;
900 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
901 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]902
903 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
904 switch (type) {
905 case 0:
906 Shift = ARM_AM::lsl;
907 break;
908 case 1:
909 Shift = ARM_AM::lsr;
910 break;
911 case 2:
912 Shift = ARM_AM::asr;
913 break;
914 case 3:
915 Shift = ARM_AM::ror;
916 break;
917 }
918
919 Inst.addOperand(MCOperand::CreateImm(Shift));
920
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]921 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]922}
923
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]924static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]926 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]927
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]928 bool writebackLoad = false;
929 unsigned writebackReg = 0;
930 switch (Inst.getOpcode()) {
931 default:
932 break;
933 case ARM::LDMIA_UPD:
934 case ARM::LDMDB_UPD:
935 case ARM::LDMIB_UPD:
936 case ARM::LDMDA_UPD:
937 case ARM::t2LDMIA_UPD:
938 case ARM::t2LDMDB_UPD:
939 writebackLoad = true;
940 writebackReg = Inst.getOperand(0).getReg();
941 break;
942 }
943
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]944 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]945 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]947 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]948 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
949 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]950 // Writeback not allowed if Rn is in the target list.
951 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
952 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]953 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]954 }
955
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]956 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]957}
958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]959static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]960 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]961 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]962
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
964 unsigned regs = Val & 0xFF;
965
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]966 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
967 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]968 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]969 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
970 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]971 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]972
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]973 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]974}
975
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]976static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]977 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]978 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]979
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]980 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
981 unsigned regs = (Val & 0xFF) / 2;
982
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]983 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
984 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]985 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]986 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
987 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]988 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]989
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]990 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]991}
992
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]993static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]994 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]995 // This operand encodes a mask of contiguous zeros between a specified MSB
996 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
997 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]998 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]999 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1000 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1001 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1002 uint32_t msb_mask = (1 << (msb+1)) - 1;
1003 uint32_t lsb_mask = (1 << lsb) - 1;
1004 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1005 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1006}
1007
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1008static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1009 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1010 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1011
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1012 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1013 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1014 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1015 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1016 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1017 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1018
1019 switch (Inst.getOpcode()) {
1020 case ARM::LDC_OFFSET:
1021 case ARM::LDC_PRE:
1022 case ARM::LDC_POST:
1023 case ARM::LDC_OPTION:
1024 case ARM::LDCL_OFFSET:
1025 case ARM::LDCL_PRE:
1026 case ARM::LDCL_POST:
1027 case ARM::LDCL_OPTION:
1028 case ARM::STC_OFFSET:
1029 case ARM::STC_PRE:
1030 case ARM::STC_POST:
1031 case ARM::STC_OPTION:
1032 case ARM::STCL_OFFSET:
1033 case ARM::STCL_PRE:
1034 case ARM::STCL_POST:
1035 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1036 case ARM::t2LDC_OFFSET:
1037 case ARM::t2LDC_PRE:
1038 case ARM::t2LDC_POST:
1039 case ARM::t2LDC_OPTION:
1040 case ARM::t2LDCL_OFFSET:
1041 case ARM::t2LDCL_PRE:
1042 case ARM::t2LDCL_POST:
1043 case ARM::t2LDCL_OPTION:
1044 case ARM::t2STC_OFFSET:
1045 case ARM::t2STC_PRE:
1046 case ARM::t2STC_POST:
1047 case ARM::t2STC_OPTION:
1048 case ARM::t2STCL_OFFSET:
1049 case ARM::t2STCL_PRE:
1050 case ARM::t2STCL_POST:
1051 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1052 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1053 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1054 break;
1055 default:
1056 break;
1057 }
1058
1059 Inst.addOperand(MCOperand::CreateImm(coproc));
1060 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1062 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1063 switch (Inst.getOpcode()) {
1064 case ARM::LDC_OPTION:
1065 case ARM::LDCL_OPTION:
1066 case ARM::LDC2_OPTION:
1067 case ARM::LDC2L_OPTION:
1068 case ARM::STC_OPTION:
1069 case ARM::STCL_OPTION:
1070 case ARM::STC2_OPTION:
1071 case ARM::STC2L_OPTION:
1072 case ARM::LDCL_POST:
1073 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1074 case ARM::LDC2L_POST:
1075 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1076 case ARM::t2LDC_OPTION:
1077 case ARM::t2LDCL_OPTION:
1078 case ARM::t2STC_OPTION:
1079 case ARM::t2STCL_OPTION:
1080 case ARM::t2LDCL_POST:
1081 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1082 break;
1083 default:
1084 Inst.addOperand(MCOperand::CreateReg(0));
1085 break;
1086 }
1087
1088 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1089 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1090
1091 bool writeback = (P == 0) || (W == 1);
1092 unsigned idx_mode = 0;
1093 if (P && writeback)
1094 idx_mode = ARMII::IndexModePre;
1095 else if (!P && writeback)
1096 idx_mode = ARMII::IndexModePost;
1097
1098 switch (Inst.getOpcode()) {
1099 case ARM::LDCL_POST:
1100 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1101 case ARM::t2LDCL_POST:
1102 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1103 case ARM::LDC2L_POST:
1104 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1105 imm |= U << 8;
1106 case ARM::LDC_OPTION:
1107 case ARM::LDCL_OPTION:
1108 case ARM::LDC2_OPTION:
1109 case ARM::LDC2L_OPTION:
1110 case ARM::STC_OPTION:
1111 case ARM::STCL_OPTION:
1112 case ARM::STC2_OPTION:
1113 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1114 case ARM::t2LDC_OPTION:
1115 case ARM::t2LDCL_OPTION:
1116 case ARM::t2STC_OPTION:
1117 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1118 Inst.addOperand(MCOperand::CreateImm(imm));
1119 break;
1120 default:
1121 if (U)
1122 Inst.addOperand(MCOperand::CreateImm(
1123 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1124 else
1125 Inst.addOperand(MCOperand::CreateImm(
1126 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1127 break;
1128 }
1129
1130 switch (Inst.getOpcode()) {
1131 case ARM::LDC_OFFSET:
1132 case ARM::LDC_PRE:
1133 case ARM::LDC_POST:
1134 case ARM::LDC_OPTION:
1135 case ARM::LDCL_OFFSET:
1136 case ARM::LDCL_PRE:
1137 case ARM::LDCL_POST:
1138 case ARM::LDCL_OPTION:
1139 case ARM::STC_OFFSET:
1140 case ARM::STC_PRE:
1141 case ARM::STC_POST:
1142 case ARM::STC_OPTION:
1143 case ARM::STCL_OFFSET:
1144 case ARM::STCL_PRE:
1145 case ARM::STCL_POST:
1146 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1147 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1148 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1149 break;
1150 default:
1151 break;
1152 }
1153
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1154 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1155}
1156
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1157static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1158DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1159 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1160 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1161
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1162 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1163 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1164 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1165 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1166 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1167 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1168 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1169 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1170
1171 // On stores, the writeback operand precedes Rt.
1172 switch (Inst.getOpcode()) {
1173 case ARM::STR_POST_IMM:
1174 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1175 case ARM::STRB_POST_IMM:
1176 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1177 case ARM::STRT_POST_REG:
1178 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1179 case ARM::STRBT_POST_REG:
1180 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1182 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1183 break;
1184 default:
1185 break;
1186 }
1187
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1189 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1190
1191 // On loads, the writeback operand comes after Rt.
1192 switch (Inst.getOpcode()) {
1193 case ARM::LDR_POST_IMM:
1194 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1195 case ARM::LDRB_POST_IMM:
1196 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1197 case ARM::LDRBT_POST_REG:
1198 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1199 case ARM::LDRT_POST_REG:
1200 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1202 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1203 break;
1204 default:
1205 break;
1206 }
1207
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1209 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1210
1211 ARM_AM::AddrOpc Op = ARM_AM::add;
1212 if (!fieldFromInstruction32(Insn, 23, 1))
1213 Op = ARM_AM::sub;
1214
1215 bool writeback = (P == 0) || (W == 1);
1216 unsigned idx_mode = 0;
1217 if (P && writeback)
1218 idx_mode = ARMII::IndexModePre;
1219 else if (!P && writeback)
1220 idx_mode = ARMII::IndexModePost;
1221
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1222 if (writeback && (Rn == 15 || Rn == Rt))
1223 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1224
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1225 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1227 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1228 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1229 switch( fieldFromInstruction32(Insn, 5, 2)) {
1230 case 0:
1231 Opc = ARM_AM::lsl;
1232 break;
1233 case 1:
1234 Opc = ARM_AM::lsr;
1235 break;
1236 case 2:
1237 Opc = ARM_AM::asr;
1238 break;
1239 case 3:
1240 Opc = ARM_AM::ror;
1241 break;
1242 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1243 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1244 }
1245 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1246 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1247
1248 Inst.addOperand(MCOperand::CreateImm(imm));
1249 } else {
1250 Inst.addOperand(MCOperand::CreateReg(0));
1251 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1252 Inst.addOperand(MCOperand::CreateImm(tmp));
1253 }
1254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1255 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1256 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1257
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1258 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1259}
1260
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1261static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1262 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1263 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1264
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1265 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1266 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1267 unsigned type = fieldFromInstruction32(Val, 5, 2);
1268 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1269 unsigned U = fieldFromInstruction32(Val, 12, 1);
1270
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1271 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1272 switch (type) {
1273 case 0:
1274 ShOp = ARM_AM::lsl;
1275 break;
1276 case 1:
1277 ShOp = ARM_AM::lsr;
1278 break;
1279 case 2:
1280 ShOp = ARM_AM::asr;
1281 break;
1282 case 3:
1283 ShOp = ARM_AM::ror;
1284 break;
1285 }
1286
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1288 return MCDisassembler::Fail;
1289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1290 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1291 unsigned shift;
1292 if (U)
1293 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1294 else
1295 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1296 Inst.addOperand(MCOperand::CreateImm(shift));
1297
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1298 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1299}
1300
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1301static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1302DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1303 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1304 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1305
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1306 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1307 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1308 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1309 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1310 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1311 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1312 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1313 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1314 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1315
1316 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1317
1318 // For {LD,ST}RD, Rt must be even, else undefined.
1319 switch (Inst.getOpcode()) {
1320 case ARM::STRD:
1321 case ARM::STRD_PRE:
1322 case ARM::STRD_POST:
1323 case ARM::LDRD:
1324 case ARM::LDRD_PRE:
1325 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1326 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1327 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1328 default:
1329 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1330 }
1331
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1332 if (writeback) { // Writeback
1333 if (P)
1334 U |= ARMII::IndexModePre << 9;
1335 else
1336 U |= ARMII::IndexModePost << 9;
1337
1338 // On stores, the writeback operand precedes Rt.
1339 switch (Inst.getOpcode()) {
1340 case ARM::STRD:
1341 case ARM::STRD_PRE:
1342 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1343 case ARM::STRH:
1344 case ARM::STRH_PRE:
1345 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1347 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1348 break;
1349 default:
1350 break;
1351 }
1352 }
1353
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1355 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1356 switch (Inst.getOpcode()) {
1357 case ARM::STRD:
1358 case ARM::STRD_PRE:
1359 case ARM::STRD_POST:
1360 case ARM::LDRD:
1361 case ARM::LDRD_PRE:
1362 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1364 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1365 break;
1366 default:
1367 break;
1368 }
1369
1370 if (writeback) {
1371 // On loads, the writeback operand comes after Rt.
1372 switch (Inst.getOpcode()) {
1373 case ARM::LDRD:
1374 case ARM::LDRD_PRE:
1375 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1376 case ARM::LDRH:
1377 case ARM::LDRH_PRE:
1378 case ARM::LDRH_POST:
1379 case ARM::LDRSH:
1380 case ARM::LDRSH_PRE:
1381 case ARM::LDRSH_POST:
1382 case ARM::LDRSB:
1383 case ARM::LDRSB_PRE:
1384 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1385 case ARM::LDRHTr:
1386 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1388 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1389 break;
1390 default:
1391 break;
1392 }
1393 }
1394
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1396 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1397
1398 if (type) {
1399 Inst.addOperand(MCOperand::CreateReg(0));
1400 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1401 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1402 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1403 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1404 Inst.addOperand(MCOperand::CreateImm(U));
1405 }
1406
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1407 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1408 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1409
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1410 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1411}
1412
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1413static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1414 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1415 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1416
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1417 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1418 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1419
1420 switch (mode) {
1421 case 0:
1422 mode = ARM_AM::da;
1423 break;
1424 case 1:
1425 mode = ARM_AM::ia;
1426 break;
1427 case 2:
1428 mode = ARM_AM::db;
1429 break;
1430 case 3:
1431 mode = ARM_AM::ib;
1432 break;
1433 }
1434
1435 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1437 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1438
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1439 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1440}
1441
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1442static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1443 unsigned Insn,
1444 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1445 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1446
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1447 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1448 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1449 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1450
1451 if (pred == 0xF) {
1452 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1453 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1454 Inst.setOpcode(ARM::RFEDA);
1455 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1456 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1457 Inst.setOpcode(ARM::RFEDA_UPD);
1458 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1459 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1460 Inst.setOpcode(ARM::RFEDB);
1461 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1462 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1463 Inst.setOpcode(ARM::RFEDB_UPD);
1464 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1465 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1466 Inst.setOpcode(ARM::RFEIA);
1467 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1468 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1469 Inst.setOpcode(ARM::RFEIA_UPD);
1470 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1471 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1472 Inst.setOpcode(ARM::RFEIB);
1473 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1474 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1475 Inst.setOpcode(ARM::RFEIB_UPD);
1476 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1477 case ARM::STMDA:
1478 Inst.setOpcode(ARM::SRSDA);
1479 break;
1480 case ARM::STMDA_UPD:
1481 Inst.setOpcode(ARM::SRSDA_UPD);
1482 break;
1483 case ARM::STMDB:
1484 Inst.setOpcode(ARM::SRSDB);
1485 break;
1486 case ARM::STMDB_UPD:
1487 Inst.setOpcode(ARM::SRSDB_UPD);
1488 break;
1489 case ARM::STMIA:
1490 Inst.setOpcode(ARM::SRSIA);
1491 break;
1492 case ARM::STMIA_UPD:
1493 Inst.setOpcode(ARM::SRSIA_UPD);
1494 break;
1495 case ARM::STMIB:
1496 Inst.setOpcode(ARM::SRSIB);
1497 break;
1498 case ARM::STMIB_UPD:
1499 Inst.setOpcode(ARM::SRSIB_UPD);
1500 break;
1501 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1502 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1503 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1504
1505 // For stores (which become SRS's, the only operand is the mode.
1506 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1507 Inst.addOperand(
1508 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1509 return S;
1510 }
1511
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1512 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1513 }
1514
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1516 return MCDisassembler::Fail;
1517 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1518 return MCDisassembler::Fail; // Tied
1519 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1520 return MCDisassembler::Fail;
1521 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1522 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1523
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1524 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1525}
1526
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1527static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1528 uint64_t Address, const void *Decoder) {
1529 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1530 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1531 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1532 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1533
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1534 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1535
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1536 // imod == '01' --> UNPREDICTABLE
1537 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1538 // return failure here. The '01' imod value is unprintable, so there's
1539 // nothing useful we could do even if we returned UNPREDICTABLE.
1540
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1541 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1542
1543 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1544 Inst.setOpcode(ARM::CPS3p);
1545 Inst.addOperand(MCOperand::CreateImm(imod));
1546 Inst.addOperand(MCOperand::CreateImm(iflags));
1547 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1548 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1549 Inst.setOpcode(ARM::CPS2p);
1550 Inst.addOperand(MCOperand::CreateImm(imod));
1551 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1552 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1553 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1554 Inst.setOpcode(ARM::CPS1p);
1555 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1556 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1557 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1558 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1559 Inst.setOpcode(ARM::CPS1p);
1560 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1561 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1562 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1563
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1564 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1565}
1566
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1567static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1568 uint64_t Address, const void *Decoder) {
1569 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1570 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1571 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1572 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1573
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1574 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1575
1576 // imod == '01' --> UNPREDICTABLE
1577 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1578 // return failure here. The '01' imod value is unprintable, so there's
1579 // nothing useful we could do even if we returned UNPREDICTABLE.
1580
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1581 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1582
1583 if (imod && M) {
1584 Inst.setOpcode(ARM::t2CPS3p);
1585 Inst.addOperand(MCOperand::CreateImm(imod));
1586 Inst.addOperand(MCOperand::CreateImm(iflags));
1587 Inst.addOperand(MCOperand::CreateImm(mode));
1588 } else if (imod && !M) {
1589 Inst.setOpcode(ARM::t2CPS2p);
1590 Inst.addOperand(MCOperand::CreateImm(imod));
1591 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1592 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1593 } else if (!imod && M) {
1594 Inst.setOpcode(ARM::t2CPS1p);
1595 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1596 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1597 } else {
1598 // imod == '00' && M == '0' --> UNPREDICTABLE
1599 Inst.setOpcode(ARM::t2CPS1p);
1600 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1601 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1602 }
1603
1604 return S;
1605}
1606
1607
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1608static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1609 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1610 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1611
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1612 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1613 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1614 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1615 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1616 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1617
1618 if (pred == 0xF)
1619 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1620
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1621 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1622 return MCDisassembler::Fail;
1623 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1624 return MCDisassembler::Fail;
1625 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1626 return MCDisassembler::Fail;
1627 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1628 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1629
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1630 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1631 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1632
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1633 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1634}
1635
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1636static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1638 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1639
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1640 unsigned add = fieldFromInstruction32(Val, 12, 1);
1641 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1642 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1643
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1645 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1646
1647 if (!add) imm *= -1;
1648 if (imm == 0 && !add) imm = INT32_MIN;
1649 Inst.addOperand(MCOperand::CreateImm(imm));
1650
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1651 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1652}
1653
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1654static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1655 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1656 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1657
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1658 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1659 unsigned U = fieldFromInstruction32(Val, 8, 1);
1660 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1661
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1663 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1664
1665 if (U)
1666 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1667 else
1668 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1669
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1670 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1671}
1672
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1673static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1674 uint64_t Address, const void *Decoder) {
1675 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1676}
1677
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1678static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1679DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1680 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1681 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1682
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1683 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1684 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1685
1686 if (pred == 0xF) {
1687 Inst.setOpcode(ARM::BLXi);
1688 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1689 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1690 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1691 }
1692
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1693 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1694 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1695 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1696
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1697 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1698}
1699
1700
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1701static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1702 uint64_t Address, const void *Decoder) {
1703 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1704 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1705}
1706
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1707static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1708 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1709 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1710
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1711 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1712 unsigned align = fieldFromInstruction32(Val, 4, 2);
1713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1715 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1716 if (!align)
1717 Inst.addOperand(MCOperand::CreateImm(0));
1718 else
1719 Inst.addOperand(MCOperand::CreateImm(4 << align));
1720
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1721 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1722}
1723
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1724static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1725 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1726 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1727
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1728 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1729 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1730 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1731 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1732 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1733 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1734
1735 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1736 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1737 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1738
1739 // Second output register
1740 switch (Inst.getOpcode()) {
1741 case ARM::VLD1q8:
1742 case ARM::VLD1q16:
1743 case ARM::VLD1q32:
1744 case ARM::VLD1q64:
1745 case ARM::VLD1q8_UPD:
1746 case ARM::VLD1q16_UPD:
1747 case ARM::VLD1q32_UPD:
1748 case ARM::VLD1q64_UPD:
1749 case ARM::VLD1d8T:
1750 case ARM::VLD1d16T:
1751 case ARM::VLD1d32T:
1752 case ARM::VLD1d64T:
1753 case ARM::VLD1d8T_UPD:
1754 case ARM::VLD1d16T_UPD:
1755 case ARM::VLD1d32T_UPD:
1756 case ARM::VLD1d64T_UPD:
1757 case ARM::VLD1d8Q:
1758 case ARM::VLD1d16Q:
1759 case ARM::VLD1d32Q:
1760 case ARM::VLD1d64Q:
1761 case ARM::VLD1d8Q_UPD:
1762 case ARM::VLD1d16Q_UPD:
1763 case ARM::VLD1d32Q_UPD:
1764 case ARM::VLD1d64Q_UPD:
1765 case ARM::VLD2d8:
1766 case ARM::VLD2d16:
1767 case ARM::VLD2d32:
1768 case ARM::VLD2d8_UPD:
1769 case ARM::VLD2d16_UPD:
1770 case ARM::VLD2d32_UPD:
1771 case ARM::VLD2q8:
1772 case ARM::VLD2q16:
1773 case ARM::VLD2q32:
1774 case ARM::VLD2q8_UPD:
1775 case ARM::VLD2q16_UPD:
1776 case ARM::VLD2q32_UPD:
1777 case ARM::VLD3d8:
1778 case ARM::VLD3d16:
1779 case ARM::VLD3d32:
1780 case ARM::VLD3d8_UPD:
1781 case ARM::VLD3d16_UPD:
1782 case ARM::VLD3d32_UPD:
1783 case ARM::VLD4d8:
1784 case ARM::VLD4d16:
1785 case ARM::VLD4d32:
1786 case ARM::VLD4d8_UPD:
1787 case ARM::VLD4d16_UPD:
1788 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1789 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1790 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1791 break;
1792 case ARM::VLD2b8:
1793 case ARM::VLD2b16:
1794 case ARM::VLD2b32:
1795 case ARM::VLD2b8_UPD:
1796 case ARM::VLD2b16_UPD:
1797 case ARM::VLD2b32_UPD:
1798 case ARM::VLD3q8:
1799 case ARM::VLD3q16:
1800 case ARM::VLD3q32:
1801 case ARM::VLD3q8_UPD:
1802 case ARM::VLD3q16_UPD:
1803 case ARM::VLD3q32_UPD:
1804 case ARM::VLD4q8:
1805 case ARM::VLD4q16:
1806 case ARM::VLD4q32:
1807 case ARM::VLD4q8_UPD:
1808 case ARM::VLD4q16_UPD:
1809 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1810 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1811 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1812 default:
1813 break;
1814 }
1815
1816 // Third output register
1817 switch(Inst.getOpcode()) {
1818 case ARM::VLD1d8T:
1819 case ARM::VLD1d16T:
1820 case ARM::VLD1d32T:
1821 case ARM::VLD1d64T:
1822 case ARM::VLD1d8T_UPD:
1823 case ARM::VLD1d16T_UPD:
1824 case ARM::VLD1d32T_UPD:
1825 case ARM::VLD1d64T_UPD:
1826 case ARM::VLD1d8Q:
1827 case ARM::VLD1d16Q:
1828 case ARM::VLD1d32Q:
1829 case ARM::VLD1d64Q:
1830 case ARM::VLD1d8Q_UPD:
1831 case ARM::VLD1d16Q_UPD:
1832 case ARM::VLD1d32Q_UPD:
1833 case ARM::VLD1d64Q_UPD:
1834 case ARM::VLD2q8:
1835 case ARM::VLD2q16:
1836 case ARM::VLD2q32:
1837 case ARM::VLD2q8_UPD:
1838 case ARM::VLD2q16_UPD:
1839 case ARM::VLD2q32_UPD:
1840 case ARM::VLD3d8:
1841 case ARM::VLD3d16:
1842 case ARM::VLD3d32:
1843 case ARM::VLD3d8_UPD:
1844 case ARM::VLD3d16_UPD:
1845 case ARM::VLD3d32_UPD:
1846 case ARM::VLD4d8:
1847 case ARM::VLD4d16:
1848 case ARM::VLD4d32:
1849 case ARM::VLD4d8_UPD:
1850 case ARM::VLD4d16_UPD:
1851 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1852 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1853 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1854 break;
1855 case ARM::VLD3q8:
1856 case ARM::VLD3q16:
1857 case ARM::VLD3q32:
1858 case ARM::VLD3q8_UPD:
1859 case ARM::VLD3q16_UPD:
1860 case ARM::VLD3q32_UPD:
1861 case ARM::VLD4q8:
1862 case ARM::VLD4q16:
1863 case ARM::VLD4q32:
1864 case ARM::VLD4q8_UPD:
1865 case ARM::VLD4q16_UPD:
1866 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1867 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1868 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1869 break;
1870 default:
1871 break;
1872 }
1873
1874 // Fourth output register
1875 switch (Inst.getOpcode()) {
1876 case ARM::VLD1d8Q:
1877 case ARM::VLD1d16Q:
1878 case ARM::VLD1d32Q:
1879 case ARM::VLD1d64Q:
1880 case ARM::VLD1d8Q_UPD:
1881 case ARM::VLD1d16Q_UPD:
1882 case ARM::VLD1d32Q_UPD:
1883 case ARM::VLD1d64Q_UPD:
1884 case ARM::VLD2q8:
1885 case ARM::VLD2q16:
1886 case ARM::VLD2q32:
1887 case ARM::VLD2q8_UPD:
1888 case ARM::VLD2q16_UPD:
1889 case ARM::VLD2q32_UPD:
1890 case ARM::VLD4d8:
1891 case ARM::VLD4d16:
1892 case ARM::VLD4d32:
1893 case ARM::VLD4d8_UPD:
1894 case ARM::VLD4d16_UPD:
1895 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1896 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1897 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1898 break;
1899 case ARM::VLD4q8:
1900 case ARM::VLD4q16:
1901 case ARM::VLD4q32:
1902 case ARM::VLD4q8_UPD:
1903 case ARM::VLD4q16_UPD:
1904 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1905 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1906 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1907 break;
1908 default:
1909 break;
1910 }
1911
1912 // Writeback operand
1913 switch (Inst.getOpcode()) {
1914 case ARM::VLD1d8_UPD:
1915 case ARM::VLD1d16_UPD:
1916 case ARM::VLD1d32_UPD:
1917 case ARM::VLD1d64_UPD:
1918 case ARM::VLD1q8_UPD:
1919 case ARM::VLD1q16_UPD:
1920 case ARM::VLD1q32_UPD:
1921 case ARM::VLD1q64_UPD:
1922 case ARM::VLD1d8T_UPD:
1923 case ARM::VLD1d16T_UPD:
1924 case ARM::VLD1d32T_UPD:
1925 case ARM::VLD1d64T_UPD:
1926 case ARM::VLD1d8Q_UPD:
1927 case ARM::VLD1d16Q_UPD:
1928 case ARM::VLD1d32Q_UPD:
1929 case ARM::VLD1d64Q_UPD:
1930 case ARM::VLD2d8_UPD:
1931 case ARM::VLD2d16_UPD:
1932 case ARM::VLD2d32_UPD:
1933 case ARM::VLD2q8_UPD:
1934 case ARM::VLD2q16_UPD:
1935 case ARM::VLD2q32_UPD:
1936 case ARM::VLD2b8_UPD:
1937 case ARM::VLD2b16_UPD:
1938 case ARM::VLD2b32_UPD:
1939 case ARM::VLD3d8_UPD:
1940 case ARM::VLD3d16_UPD:
1941 case ARM::VLD3d32_UPD:
1942 case ARM::VLD3q8_UPD:
1943 case ARM::VLD3q16_UPD:
1944 case ARM::VLD3q32_UPD:
1945 case ARM::VLD4d8_UPD:
1946 case ARM::VLD4d16_UPD:
1947 case ARM::VLD4d32_UPD:
1948 case ARM::VLD4q8_UPD:
1949 case ARM::VLD4q16_UPD:
1950 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1951 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1952 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1953 break;
1954 default:
1955 break;
1956 }
1957
1958 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1959 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1960 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1961
1962 // AddrMode6 Offset (register)
1963 if (Rm == 0xD)
1964 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1965 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1967 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1968 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1969
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1970 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1971}
1972
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1973static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1974 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1975 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1976
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1977 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1978 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1979 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1980 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1981 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1982 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1983
1984 // Writeback Operand
1985 switch (Inst.getOpcode()) {
1986 case ARM::VST1d8_UPD:
1987 case ARM::VST1d16_UPD:
1988 case ARM::VST1d32_UPD:
1989 case ARM::VST1d64_UPD:
1990 case ARM::VST1q8_UPD:
1991 case ARM::VST1q16_UPD:
1992 case ARM::VST1q32_UPD:
1993 case ARM::VST1q64_UPD:
1994 case ARM::VST1d8T_UPD:
1995 case ARM::VST1d16T_UPD:
1996 case ARM::VST1d32T_UPD:
1997 case ARM::VST1d64T_UPD:
1998 case ARM::VST1d8Q_UPD:
1999 case ARM::VST1d16Q_UPD:
2000 case ARM::VST1d32Q_UPD:
2001 case ARM::VST1d64Q_UPD:
2002 case ARM::VST2d8_UPD:
2003 case ARM::VST2d16_UPD:
2004 case ARM::VST2d32_UPD:
2005 case ARM::VST2q8_UPD:
2006 case ARM::VST2q16_UPD:
2007 case ARM::VST2q32_UPD:
2008 case ARM::VST2b8_UPD:
2009 case ARM::VST2b16_UPD:
2010 case ARM::VST2b32_UPD:
2011 case ARM::VST3d8_UPD:
2012 case ARM::VST3d16_UPD:
2013 case ARM::VST3d32_UPD:
2014 case ARM::VST3q8_UPD:
2015 case ARM::VST3q16_UPD:
2016 case ARM::VST3q32_UPD:
2017 case ARM::VST4d8_UPD:
2018 case ARM::VST4d16_UPD:
2019 case ARM::VST4d32_UPD:
2020 case ARM::VST4q8_UPD:
2021 case ARM::VST4q16_UPD:
2022 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2023 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2024 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2025 break;
2026 default:
2027 break;
2028 }
2029
2030 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2031 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2032 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2033
2034 // AddrMode6 Offset (register)
2035 if (Rm == 0xD)
2036 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2037 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2039 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2040 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2041
2042 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2043 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2044 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2045
2046 // Second input register
2047 switch (Inst.getOpcode()) {
2048 case ARM::VST1q8:
2049 case ARM::VST1q16:
2050 case ARM::VST1q32:
2051 case ARM::VST1q64:
2052 case ARM::VST1q8_UPD:
2053 case ARM::VST1q16_UPD:
2054 case ARM::VST1q32_UPD:
2055 case ARM::VST1q64_UPD:
2056 case ARM::VST1d8T:
2057 case ARM::VST1d16T:
2058 case ARM::VST1d32T:
2059 case ARM::VST1d64T:
2060 case ARM::VST1d8T_UPD:
2061 case ARM::VST1d16T_UPD:
2062 case ARM::VST1d32T_UPD:
2063 case ARM::VST1d64T_UPD:
2064 case ARM::VST1d8Q:
2065 case ARM::VST1d16Q:
2066 case ARM::VST1d32Q:
2067 case ARM::VST1d64Q:
2068 case ARM::VST1d8Q_UPD:
2069 case ARM::VST1d16Q_UPD:
2070 case ARM::VST1d32Q_UPD:
2071 case ARM::VST1d64Q_UPD:
2072 case ARM::VST2d8:
2073 case ARM::VST2d16:
2074 case ARM::VST2d32:
2075 case ARM::VST2d8_UPD:
2076 case ARM::VST2d16_UPD:
2077 case ARM::VST2d32_UPD:
2078 case ARM::VST2q8:
2079 case ARM::VST2q16:
2080 case ARM::VST2q32:
2081 case ARM::VST2q8_UPD:
2082 case ARM::VST2q16_UPD:
2083 case ARM::VST2q32_UPD:
2084 case ARM::VST3d8:
2085 case ARM::VST3d16:
2086 case ARM::VST3d32:
2087 case ARM::VST3d8_UPD:
2088 case ARM::VST3d16_UPD:
2089 case ARM::VST3d32_UPD:
2090 case ARM::VST4d8:
2091 case ARM::VST4d16:
2092 case ARM::VST4d32:
2093 case ARM::VST4d8_UPD:
2094 case ARM::VST4d16_UPD:
2095 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2096 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2097 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2098 break;
2099 case ARM::VST2b8:
2100 case ARM::VST2b16:
2101 case ARM::VST2b32:
2102 case ARM::VST2b8_UPD:
2103 case ARM::VST2b16_UPD:
2104 case ARM::VST2b32_UPD:
2105 case ARM::VST3q8:
2106 case ARM::VST3q16:
2107 case ARM::VST3q32:
2108 case ARM::VST3q8_UPD:
2109 case ARM::VST3q16_UPD:
2110 case ARM::VST3q32_UPD:
2111 case ARM::VST4q8:
2112 case ARM::VST4q16:
2113 case ARM::VST4q32:
2114 case ARM::VST4q8_UPD:
2115 case ARM::VST4q16_UPD:
2116 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2117 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2118 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2119 break;
2120 default:
2121 break;
2122 }
2123
2124 // Third input register
2125 switch (Inst.getOpcode()) {
2126 case ARM::VST1d8T:
2127 case ARM::VST1d16T:
2128 case ARM::VST1d32T:
2129 case ARM::VST1d64T:
2130 case ARM::VST1d8T_UPD:
2131 case ARM::VST1d16T_UPD:
2132 case ARM::VST1d32T_UPD:
2133 case ARM::VST1d64T_UPD:
2134 case ARM::VST1d8Q:
2135 case ARM::VST1d16Q:
2136 case ARM::VST1d32Q:
2137 case ARM::VST1d64Q:
2138 case ARM::VST1d8Q_UPD:
2139 case ARM::VST1d16Q_UPD:
2140 case ARM::VST1d32Q_UPD:
2141 case ARM::VST1d64Q_UPD:
2142 case ARM::VST2q8:
2143 case ARM::VST2q16:
2144 case ARM::VST2q32:
2145 case ARM::VST2q8_UPD:
2146 case ARM::VST2q16_UPD:
2147 case ARM::VST2q32_UPD:
2148 case ARM::VST3d8:
2149 case ARM::VST3d16:
2150 case ARM::VST3d32:
2151 case ARM::VST3d8_UPD:
2152 case ARM::VST3d16_UPD:
2153 case ARM::VST3d32_UPD:
2154 case ARM::VST4d8:
2155 case ARM::VST4d16:
2156 case ARM::VST4d32:
2157 case ARM::VST4d8_UPD:
2158 case ARM::VST4d16_UPD:
2159 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2160 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2161 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2162 break;
2163 case ARM::VST3q8:
2164 case ARM::VST3q16:
2165 case ARM::VST3q32:
2166 case ARM::VST3q8_UPD:
2167 case ARM::VST3q16_UPD:
2168 case ARM::VST3q32_UPD:
2169 case ARM::VST4q8:
2170 case ARM::VST4q16:
2171 case ARM::VST4q32:
2172 case ARM::VST4q8_UPD:
2173 case ARM::VST4q16_UPD:
2174 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2175 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2176 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2177 break;
2178 default:
2179 break;
2180 }
2181
2182 // Fourth input register
2183 switch (Inst.getOpcode()) {
2184 case ARM::VST1d8Q:
2185 case ARM::VST1d16Q:
2186 case ARM::VST1d32Q:
2187 case ARM::VST1d64Q:
2188 case ARM::VST1d8Q_UPD:
2189 case ARM::VST1d16Q_UPD:
2190 case ARM::VST1d32Q_UPD:
2191 case ARM::VST1d64Q_UPD:
2192 case ARM::VST2q8:
2193 case ARM::VST2q16:
2194 case ARM::VST2q32:
2195 case ARM::VST2q8_UPD:
2196 case ARM::VST2q16_UPD:
2197 case ARM::VST2q32_UPD:
2198 case ARM::VST4d8:
2199 case ARM::VST4d16:
2200 case ARM::VST4d32:
2201 case ARM::VST4d8_UPD:
2202 case ARM::VST4d16_UPD:
2203 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2204 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2205 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2206 break;
2207 case ARM::VST4q8:
2208 case ARM::VST4q16:
2209 case ARM::VST4q32:
2210 case ARM::VST4q8_UPD:
2211 case ARM::VST4q16_UPD:
2212 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2213 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2214 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2215 break;
2216 default:
2217 break;
2218 }
2219
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2220 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2221}
2222
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2223static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2224 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2225 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2226
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2227 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2228 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2229 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2230 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2231 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2232 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2233 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2234
2235 align *= (1 << size);
2236
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2238 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2239 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2240 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2241 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2242 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2243 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2245 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2246 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2249 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2250 Inst.addOperand(MCOperand::CreateImm(align));
2251
2252 if (Rm == 0xD)
2253 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2254 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2256 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2257 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2258
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2259 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2260}
2261
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2262static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2263 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2264 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2265
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2266 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2267 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2268 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2269 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2270 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2271 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2272 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2273 align *= 2*size;
2274
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2275 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2276 return MCDisassembler::Fail;
2277 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2278 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2279 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2281 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2282 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2283
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2285 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2286 Inst.addOperand(MCOperand::CreateImm(align));
2287
2288 if (Rm == 0xD)
2289 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2290 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2292 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2293 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2294
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2295 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2296}
2297
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2298static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2299 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2300 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2301
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2302 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2303 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2304 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2305 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2306 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2307
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2309 return MCDisassembler::Fail;
2310 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2311 return MCDisassembler::Fail;
2312 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2313 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2314 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2316 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2317 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2318
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2320 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2321 Inst.addOperand(MCOperand::CreateImm(0));
2322
2323 if (Rm == 0xD)
2324 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2325 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2327 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2328 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2329
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2330 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2331}
2332
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2333static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2334 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2335 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2336
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2337 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2338 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2339 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2340 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2341 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2342 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2343 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2344
2345 if (size == 0x3) {
2346 size = 4;
2347 align = 16;
2348 } else {
2349 if (size == 2) {
2350 size = 1 << size;
2351 align *= 8;
2352 } else {
2353 size = 1 << size;
2354 align *= 4*size;
2355 }
2356 }
2357
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2358 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2359 return MCDisassembler::Fail;
2360 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2361 return MCDisassembler::Fail;
2362 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2363 return MCDisassembler::Fail;
2364 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2365 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2366 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2368 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2369 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2370
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2372 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2373 Inst.addOperand(MCOperand::CreateImm(align));
2374
2375 if (Rm == 0xD)
2376 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2377 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2379 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2380 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2381
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2382 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2383}
2384
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2385static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2386DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2387 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2388 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2389
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2390 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2391 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2392 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2393 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2394 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2395 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2396 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2397 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2398
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2399 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2400 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2401 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2402 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2403 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2404 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2405 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2406
2407 Inst.addOperand(MCOperand::CreateImm(imm));
2408
2409 switch (Inst.getOpcode()) {
2410 case ARM::VORRiv4i16:
2411 case ARM::VORRiv2i32:
2412 case ARM::VBICiv4i16:
2413 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2414 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2415 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2416 break;
2417 case ARM::VORRiv8i16:
2418 case ARM::VORRiv4i32:
2419 case ARM::VBICiv8i16:
2420 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2421 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2422 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2423 break;
2424 default:
2425 break;
2426 }
2427
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2428 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2429}
2430
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2431static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2432 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2433 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2434
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2435 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2436 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2437 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2438 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2439 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2440
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2441 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2442 return MCDisassembler::Fail;
2443 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2444 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2445 Inst.addOperand(MCOperand::CreateImm(8 << size));
2446
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2447 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2448}
2449
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2450static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2451 uint64_t Address, const void *Decoder) {
2452 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2453 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2454}
2455
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2456static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2457 uint64_t Address, const void *Decoder) {
2458 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2459 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2460}
2461
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2462static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2463 uint64_t Address, const void *Decoder) {
2464 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2465 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2466}
2467
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2468static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2469 uint64_t Address, const void *Decoder) {
2470 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2471 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2472}
2473
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2474static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2475 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2476 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2477
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2478 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2479 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2480 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2481 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2482 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2483 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2484 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2485 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2486
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2487 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2488 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2489 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2490 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2491 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2492 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2493
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2494 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2495 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2496 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2497 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2498
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2500 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2501
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2502 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2503}
2504
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2505static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2506 uint64_t Address, const void *Decoder) {
2507 // The immediate needs to be a fully instantiated float. However, the
2508 // auto-generated decoder is only able to fill in some of the bits
2509 // necessary. For instance, the 'b' bit is replicated multiple times,
2510 // and is even present in inverted form in one bit. We do a little
2511 // binary parsing here to fill in those missing bits, and then
2512 // reinterpret it all as a float.
2513 union {
2514 uint32_t integer;
2515 float fp;
2516 } fp_conv;
2517
2518 fp_conv.integer = Val;
2519 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2520 fp_conv.integer |= b << 26;
2521 fp_conv.integer |= b << 27;
2522 fp_conv.integer |= b << 28;
2523 fp_conv.integer |= b << 29;
2524 fp_conv.integer |= (~b & 0x1) << 30;
2525
2526 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2527 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2528}
2529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2530static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2531 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2532 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2533
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2534 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2535 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2536
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2537 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2538 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2539
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2540 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2541 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2542 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2543 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2544 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2545 case ARM::tADDrSPi:
2546 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2547 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2548 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2549
2550 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2551 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2552}
2553
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2554static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2555 uint64_t Address, const void *Decoder) {
2556 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2557 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2558}
2559
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2560static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2561 uint64_t Address, const void *Decoder) {
2562 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2563 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2564}
2565
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2566static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2567 uint64_t Address, const void *Decoder) {
2568 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2569 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2570}
2571
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2572static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2573 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2574 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2575
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2576 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2577 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2578
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2579 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2580 return MCDisassembler::Fail;
2581 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2582 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2583
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2584 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2585}
2586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2587static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2588 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2589 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2590
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2591 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2592 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2593
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2594 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2595 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2596 Inst.addOperand(MCOperand::CreateImm(imm));
2597
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2598 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2599}
2600
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2601static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2602 uint64_t Address, const void *Decoder) {
2603 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2604
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2605 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606}
2607
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2608static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2609 uint64_t Address, const void *Decoder) {
2610 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2611 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2612
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2613 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2614}
2615
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2616static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2617 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2618 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2619
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2620 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2621 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2622 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2623
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2625 return MCDisassembler::Fail;
2626 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2627 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2628 Inst.addOperand(MCOperand::CreateImm(imm));
2629
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2630 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2631}
2632
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2633static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2634 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2635 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2636
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2637 switch (Inst.getOpcode()) {
2638 case ARM::t2PLDs:
2639 case ARM::t2PLDWs:
2640 case ARM::t2PLIs:
2641 break;
2642 default: {
2643 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2645 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2646 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2647 }
2648
2649 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2650 if (Rn == 0xF) {
2651 switch (Inst.getOpcode()) {
2652 case ARM::t2LDRBs:
2653 Inst.setOpcode(ARM::t2LDRBpci);
2654 break;
2655 case ARM::t2LDRHs:
2656 Inst.setOpcode(ARM::t2LDRHpci);
2657 break;
2658 case ARM::t2LDRSHs:
2659 Inst.setOpcode(ARM::t2LDRSHpci);
2660 break;
2661 case ARM::t2LDRSBs:
2662 Inst.setOpcode(ARM::t2LDRSBpci);
2663 break;
2664 case ARM::t2PLDs:
2665 Inst.setOpcode(ARM::t2PLDi12);
2666 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2667 break;
2668 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2669 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670 }
2671
2672 int imm = fieldFromInstruction32(Insn, 0, 12);
2673 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2674 Inst.addOperand(MCOperand::CreateImm(imm));
2675
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2676 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2677 }
2678
2679 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2680 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2681 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2682 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2683 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2685 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2686}
2687
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2688static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2689 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2690 int imm = Val & 0xFF;
2691 if (!(Val & 0x100)) imm *= -1;
2692 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2693
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2694 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2695}
2696
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2697static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2698 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2699 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2700
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2701 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2702 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2703
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2705 return MCDisassembler::Fail;
2706 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2707 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2708
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2709 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2710}
2711
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2712static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2713 uint64_t Address, const void *Decoder) {
2714 DecodeStatus S = MCDisassembler::Success;
2715
2716 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2717 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2718
2719 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2720 return MCDisassembler::Fail;
2721
2722 Inst.addOperand(MCOperand::CreateImm(imm));
2723
2724 return S;
2725}
2726
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2727static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2728 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2729 int imm = Val & 0xFF;
2730 if (!(Val & 0x100)) imm *= -1;
2731 Inst.addOperand(MCOperand::CreateImm(imm));
2732
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2733 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2734}
2735
2736
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2737static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2738 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2739 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2740
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2741 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2742 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2743
2744 // Some instructions always use an additive offset.
2745 switch (Inst.getOpcode()) {
2746 case ARM::t2LDRT:
2747 case ARM::t2LDRBT:
2748 case ARM::t2LDRHT:
2749 case ARM::t2LDRSBT:
2750 case ARM::t2LDRSHT:
2751 imm |= 0x100;
2752 break;
2753 default:
2754 break;
2755 }
2756
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2758 return MCDisassembler::Fail;
2759 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2760 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2761
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2762 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2763}
2764
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2765static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2766 uint64_t Address, const void *Decoder) {
2767 DecodeStatus S = MCDisassembler::Success;
2768
2769 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2770 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2771 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2772 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2773 addr |= Rn << 9;
2774 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2775
2776 if (!load) {
2777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2778 return MCDisassembler::Fail;
2779 }
2780
2781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2782 return MCDisassembler::Fail;
2783
2784 if (load) {
2785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2786 return MCDisassembler::Fail;
2787 }
2788
2789 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2790 return MCDisassembler::Fail;
2791
2792 return S;
2793}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2794
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2795static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2796 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2797 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2798
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2799 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2800 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2801
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2803 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804 Inst.addOperand(MCOperand::CreateImm(imm));
2805
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2806 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2807}
2808
2809
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2810static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2811 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2813
2814 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2815 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2816 Inst.addOperand(MCOperand::CreateImm(imm));
2817
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2818 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2819}
2820
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2821static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2822 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2823 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2824
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2825 if (Inst.getOpcode() == ARM::tADDrSP) {
2826 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2827 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2828
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2830 return MCDisassembler::Fail;
2831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2832 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2833 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2834 } else if (Inst.getOpcode() == ARM::tADDspr) {
2835 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2836
2837 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2838 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2840 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2841 }
2842
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2843 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2844}
2845
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2846static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2847 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2848 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2849 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2850
2851 Inst.addOperand(MCOperand::CreateImm(imod));
2852 Inst.addOperand(MCOperand::CreateImm(flags));
2853
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2854 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2855}
2856
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2857static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2858 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2859 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2860 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2861 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2862
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2864 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2865 Inst.addOperand(MCOperand::CreateImm(add));
2866
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2867 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2868}
2869
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2870static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2871 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2872 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2873 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2874}
2875
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2876static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2877 uint64_t Address, const void *Decoder) {
2878 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2879 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2880
2881 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2882 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2883}
2884
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2885static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2886DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2887 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2888 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2889
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2890 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2891 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2892 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893 switch (opc) {
2894 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2895 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2896 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2897 Inst.setOpcode(ARM::t2DSB);
2898 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2899 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900 Inst.setOpcode(ARM::t2DMB);
2901 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2902 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2903 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2904 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2905 }
2906
2907 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2908 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2909 }
2910
2911 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2912 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2913 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2914 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2915 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2916
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2917 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2918 return MCDisassembler::Fail;
2919 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2920 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2921
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2922 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2923}
2924
2925// Decode a shifted immediate operand. These basically consist
2926// of an 8-bit value, and a 4-bit directive that specifies either
2927// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2928static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2929 uint64_t Address, const void *Decoder) {
2930 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2931 if (ctrl == 0) {
2932 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2933 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2934 switch (byte) {
2935 case 0:
2936 Inst.addOperand(MCOperand::CreateImm(imm));
2937 break;
2938 case 1:
2939 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2940 break;
2941 case 2:
2942 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2943 break;
2944 case 3:
2945 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2946 (imm << 8) | imm));
2947 break;
2948 }
2949 } else {
2950 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2951 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2952 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2953 Inst.addOperand(MCOperand::CreateImm(imm));
2954 }
2955
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2956 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2957}
2958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2959static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2960DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2961 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2962 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2963 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2964}
2965
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2966static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2967 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2968 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2969 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2970}
2971
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2972static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2973 uint64_t Address, const void *Decoder) {
2974 switch (Val) {
2975 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2976 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2977 case 0xF: // SY
2978 case 0xE: // ST
2979 case 0xB: // ISH
2980 case 0xA: // ISHST
2981 case 0x7: // NSH
2982 case 0x6: // NSHST
2983 case 0x3: // OSH
2984 case 0x2: // OSHST
2985 break;
2986 }
2987
2988 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2989 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2990}
2991
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2992static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2993 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2994 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2995 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2996 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2997}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2998
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2999static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3000 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3001 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3002
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3003 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3004 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3005 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3006
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3007 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3008
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3010 return MCDisassembler::Fail;
3011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3012 return MCDisassembler::Fail;
3013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3014 return MCDisassembler::Fail;
3015 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3016 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3017
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3018 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3019}
3020
3021
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3022static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3023 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3024 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3025
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3026 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3027 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3028 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3029 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3030
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3031 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3032 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3033
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3034 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3035 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3036
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3038 return MCDisassembler::Fail;
3039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3040 return MCDisassembler::Fail;
3041 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3042 return MCDisassembler::Fail;
3043 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3044 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3045
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3046 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3047}
3048
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3049static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3050 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3051 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3052
3053 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3054 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3055 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3056 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3057 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3058 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3059
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3060 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3061
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3063 return MCDisassembler::Fail;
3064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3065 return MCDisassembler::Fail;
3066 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3067 return MCDisassembler::Fail;
3068 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3069 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3070
3071 return S;
3072}
3073
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3074static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3075 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3076 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3077
3078 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3079 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3080 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3081 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3082 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3083 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3084 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3085
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3086 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3087 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3088
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3089 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3090 return MCDisassembler::Fail;
3091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3092 return MCDisassembler::Fail;
3093 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3094 return MCDisassembler::Fail;
3095 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3096 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3097
3098 return S;
3099}
3100
3101
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3102static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3103 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3104 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3105
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3106 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3107 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3108 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3109 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3110 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3111 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3112
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3113 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3114
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3115 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3116 return MCDisassembler::Fail;
3117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3118 return MCDisassembler::Fail;
3119 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3120 return MCDisassembler::Fail;
3121 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3122 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3123
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3124 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3125}
3126
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3127static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3128 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3129 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3130
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3131 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3132 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3133 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3134 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3135 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3136 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3137
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3138 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3139
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3141 return MCDisassembler::Fail;
3142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3143 return MCDisassembler::Fail;
3144 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3145 return MCDisassembler::Fail;
3146 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3147 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3148
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3149 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3150}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3151
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3152static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3153 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3154 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3155
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3156 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3157 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3158 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3159 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3160 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3161
3162 unsigned align = 0;
3163 unsigned index = 0;
3164 switch (size) {
3165 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3166 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3167 case 0:
3168 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3169 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3170 index = fieldFromInstruction32(Insn, 5, 3);
3171 break;
3172 case 1:
3173 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3174 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3175 index = fieldFromInstruction32(Insn, 6, 2);
3176 if (fieldFromInstruction32(Insn, 4, 1))
3177 align = 2;
3178 break;
3179 case 2:
3180 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3181 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3182 index = fieldFromInstruction32(Insn, 7, 1);
3183 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3184 align = 4;
3185 }
3186
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3188 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3189 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3190 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3191 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3192 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3193 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3194 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3195 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3196 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3197 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3199 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3200 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3201 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3202 }
3203
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3205 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3206 Inst.addOperand(MCOperand::CreateImm(index));
3207
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3208 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3209}
3210
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3211static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3212 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3213 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3214
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3215 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3216 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3217 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3218 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3219 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3220
3221 unsigned align = 0;
3222 unsigned index = 0;
3223 switch (size) {
3224 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3225 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3226 case 0:
3227 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3228 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3229 index = fieldFromInstruction32(Insn, 5, 3);
3230 break;
3231 case 1:
3232 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3233 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3234 index = fieldFromInstruction32(Insn, 6, 2);
3235 if (fieldFromInstruction32(Insn, 4, 1))
3236 align = 2;
3237 break;
3238 case 2:
3239 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3240 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3241 index = fieldFromInstruction32(Insn, 7, 1);
3242 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3243 align = 4;
3244 }
3245
3246 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3248 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3249 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3251 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3252 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3253 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3254 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3256 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3257 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3258 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3259 }
3260
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3261 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3262 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3263 Inst.addOperand(MCOperand::CreateImm(index));
3264
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3265 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3266}
3267
3268
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3269static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3270 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3271 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3272
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3273 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3274 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3275 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3276 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3277 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3278
3279 unsigned align = 0;
3280 unsigned index = 0;
3281 unsigned inc = 1;
3282 switch (size) {
3283 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3284 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3285 case 0:
3286 index = fieldFromInstruction32(Insn, 5, 3);
3287 if (fieldFromInstruction32(Insn, 4, 1))
3288 align = 2;
3289 break;
3290 case 1:
3291 index = fieldFromInstruction32(Insn, 6, 2);
3292 if (fieldFromInstruction32(Insn, 4, 1))
3293 align = 4;
3294 if (fieldFromInstruction32(Insn, 5, 1))
3295 inc = 2;
3296 break;
3297 case 2:
3298 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3299 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3300 index = fieldFromInstruction32(Insn, 7, 1);
3301 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3302 align = 8;
3303 if (fieldFromInstruction32(Insn, 6, 1))
3304 inc = 2;
3305 break;
3306 }
3307
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3309 return MCDisassembler::Fail;
3310 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3311 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3312 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3314 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3315 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3317 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3318 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3319 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3320 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3321 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3322 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3323 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3324 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3325 }
3326
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3327 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3328 return MCDisassembler::Fail;
3329 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3330 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3331 Inst.addOperand(MCOperand::CreateImm(index));
3332
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3333 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3334}
3335
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3336static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3337 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3338 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3339
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3340 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3341 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3342 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3343 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3344 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3345
3346 unsigned align = 0;
3347 unsigned index = 0;
3348 unsigned inc = 1;
3349 switch (size) {
3350 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3351 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3352 case 0:
3353 index = fieldFromInstruction32(Insn, 5, 3);
3354 if (fieldFromInstruction32(Insn, 4, 1))
3355 align = 2;
3356 break;
3357 case 1:
3358 index = fieldFromInstruction32(Insn, 6, 2);
3359 if (fieldFromInstruction32(Insn, 4, 1))
3360 align = 4;
3361 if (fieldFromInstruction32(Insn, 5, 1))
3362 inc = 2;
3363 break;
3364 case 2:
3365 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3366 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3367 index = fieldFromInstruction32(Insn, 7, 1);
3368 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3369 align = 8;
3370 if (fieldFromInstruction32(Insn, 6, 1))
3371 inc = 2;
3372 break;
3373 }
3374
3375 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3377 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3378 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3380 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3381 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3382 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3383 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3385 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3386 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3387 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3388 }
3389
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3390 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3391 return MCDisassembler::Fail;
3392 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3393 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3394 Inst.addOperand(MCOperand::CreateImm(index));
3395
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3396 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3397}
3398
3399
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3400static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3401 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3402 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3403
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3404 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3405 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3406 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3407 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3408 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3409
3410 unsigned align = 0;
3411 unsigned index = 0;
3412 unsigned inc = 1;
3413 switch (size) {
3414 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3415 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3416 case 0:
3417 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3418 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3419 index = fieldFromInstruction32(Insn, 5, 3);
3420 break;
3421 case 1:
3422 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3423 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3424 index = fieldFromInstruction32(Insn, 6, 2);
3425 if (fieldFromInstruction32(Insn, 5, 1))
3426 inc = 2;
3427 break;
3428 case 2:
3429 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3430 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3431 index = fieldFromInstruction32(Insn, 7, 1);
3432 if (fieldFromInstruction32(Insn, 6, 1))
3433 inc = 2;
3434 break;
3435 }
3436
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3438 return MCDisassembler::Fail;
3439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3440 return MCDisassembler::Fail;
3441 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3442 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3443
3444 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3446 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3447 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3449 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3450 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3451 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3452 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3454 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3455 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3456 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3457 }
3458
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3460 return MCDisassembler::Fail;
3461 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3462 return MCDisassembler::Fail;
3463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3464 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3465 Inst.addOperand(MCOperand::CreateImm(index));
3466
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3467 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3468}
3469
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3470static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3471 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3472 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3473
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3474 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3475 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3476 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3477 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3478 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3479
3480 unsigned align = 0;
3481 unsigned index = 0;
3482 unsigned inc = 1;
3483 switch (size) {
3484 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3485 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3486 case 0:
3487 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3488 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3489 index = fieldFromInstruction32(Insn, 5, 3);
3490 break;
3491 case 1:
3492 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3493 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3494 index = fieldFromInstruction32(Insn, 6, 2);
3495 if (fieldFromInstruction32(Insn, 5, 1))
3496 inc = 2;
3497 break;
3498 case 2:
3499 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3500 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3501 index = fieldFromInstruction32(Insn, 7, 1);
3502 if (fieldFromInstruction32(Insn, 6, 1))
3503 inc = 2;
3504 break;
3505 }
3506
3507 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3509 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3510 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3512 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3513 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3514 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3515 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3517 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3518 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3519 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3520 }
3521
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3523 return MCDisassembler::Fail;
3524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3525 return MCDisassembler::Fail;
3526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3527 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3528 Inst.addOperand(MCOperand::CreateImm(index));
3529
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3530 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3531}
3532
3533
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3534static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3535 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3536 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3537
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3538 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3539 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3540 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3541 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3542 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3543
3544 unsigned align = 0;
3545 unsigned index = 0;
3546 unsigned inc = 1;
3547 switch (size) {
3548 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3549 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3550 case 0:
3551 if (fieldFromInstruction32(Insn, 4, 1))
3552 align = 4;
3553 index = fieldFromInstruction32(Insn, 5, 3);
3554 break;
3555 case 1:
3556 if (fieldFromInstruction32(Insn, 4, 1))
3557 align = 8;
3558 index = fieldFromInstruction32(Insn, 6, 2);
3559 if (fieldFromInstruction32(Insn, 5, 1))
3560 inc = 2;
3561 break;
3562 case 2:
3563 if (fieldFromInstruction32(Insn, 4, 2))
3564 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3565 index = fieldFromInstruction32(Insn, 7, 1);
3566 if (fieldFromInstruction32(Insn, 6, 1))
3567 inc = 2;
3568 break;
3569 }
3570
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3572 return MCDisassembler::Fail;
3573 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3574 return MCDisassembler::Fail;
3575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3576 return MCDisassembler::Fail;
3577 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3578 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3579
3580 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3582 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3583 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3585 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3586 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3587 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3588 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3589 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3590 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3591 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3592 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3593 }
3594
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3598 return MCDisassembler::Fail;
3599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3600 return MCDisassembler::Fail;
3601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3602 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3603 Inst.addOperand(MCOperand::CreateImm(index));
3604
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3605 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3606}
3607
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3608static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3609 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3610 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3611
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3612 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3613 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3614 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3615 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3616 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3617
3618 unsigned align = 0;
3619 unsigned index = 0;
3620 unsigned inc = 1;
3621 switch (size) {
3622 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3623 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3624 case 0:
3625 if (fieldFromInstruction32(Insn, 4, 1))
3626 align = 4;
3627 index = fieldFromInstruction32(Insn, 5, 3);
3628 break;
3629 case 1:
3630 if (fieldFromInstruction32(Insn, 4, 1))
3631 align = 8;
3632 index = fieldFromInstruction32(Insn, 6, 2);
3633 if (fieldFromInstruction32(Insn, 5, 1))
3634 inc = 2;
3635 break;
3636 case 2:
3637 if (fieldFromInstruction32(Insn, 4, 2))
3638 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3639 index = fieldFromInstruction32(Insn, 7, 1);
3640 if (fieldFromInstruction32(Insn, 6, 1))
3641 inc = 2;
3642 break;
3643 }
3644
3645 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3647 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3648 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3650 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3651 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3652 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3653 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3655 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3656 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3657 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3658 }
3659
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3661 return MCDisassembler::Fail;
3662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3663 return MCDisassembler::Fail;
3664 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3665 return MCDisassembler::Fail;
3666 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3667 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3668 Inst.addOperand(MCOperand::CreateImm(index));
3669
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3670 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3671}
3672
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3673static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3674 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3675 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3676 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3677 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3678 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3679 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3680 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3681
3682 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3683 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3684
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3685 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3686 return MCDisassembler::Fail;
3687 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3688 return MCDisassembler::Fail;
3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3690 return MCDisassembler::Fail;
3691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3692 return MCDisassembler::Fail;
3693 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3694 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3695
3696 return S;
3697}
3698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3699static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3700 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3701 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3702 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3703 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3704 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3705 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3706 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3707
3708 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3709 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3710
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3712 return MCDisassembler::Fail;
3713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3714 return MCDisassembler::Fail;
3715 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3716 return MCDisassembler::Fail;
3717 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3718 return MCDisassembler::Fail;
3719 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3720 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3721
3722 return S;
3723}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3724
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3725static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3726 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3727 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3728 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3729 // The InstPrinter needs to have the low bit of the predicate in
3730 // the mask operand to be able to print it properly.
3731 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3732
3733 if (pred == 0xF) {
3734 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3735 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3736 }
3737
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3738 if ((mask & 0xF) == 0) {
3739 // Preserve the high bit of the mask, which is the low bit of
3740 // the predicate.
3741 mask &= 0x10;
3742 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3743 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3744 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3745
3746 Inst.addOperand(MCOperand::CreateImm(pred));
3747 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3748 return S;
3749}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3750
3751static DecodeStatus
3752DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3753 uint64_t Address, const void *Decoder) {
3754 DecodeStatus S = MCDisassembler::Success;
3755
3756 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3757 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3758 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3759 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3760 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3761 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3762 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3763 bool writeback = (W == 1) | (P == 0);
3764
3765 addr |= (U << 8) | (Rn << 9);
3766
3767 if (writeback && (Rn == Rt || Rn == Rt2))
3768 Check(S, MCDisassembler::SoftFail);
3769 if (Rt == Rt2)
3770 Check(S, MCDisassembler::SoftFail);
3771
3772 // Rt
3773 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3774 return MCDisassembler::Fail;
3775 // Rt2
3776 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3777 return MCDisassembler::Fail;
3778 // Writeback operand
3779 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3780 return MCDisassembler::Fail;
3781 // addr
3782 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3783 return MCDisassembler::Fail;
3784
3785 return S;
3786}
3787
3788static DecodeStatus
3789DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3790 uint64_t Address, const void *Decoder) {
3791 DecodeStatus S = MCDisassembler::Success;
3792
3793 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3794 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3795 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3796 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3797 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3798 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3799 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3800 bool writeback = (W == 1) | (P == 0);
3801
3802 addr |= (U << 8) | (Rn << 9);
3803
3804 if (writeback && (Rn == Rt || Rn == Rt2))
3805 Check(S, MCDisassembler::SoftFail);
3806
3807 // Writeback operand
3808 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3809 return MCDisassembler::Fail;
3810 // Rt
3811 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3812 return MCDisassembler::Fail;
3813 // Rt2
3814 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3815 return MCDisassembler::Fail;
3816 // addr
3817 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3818 return MCDisassembler::Fail;
3819
3820 return S;
3821}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]3822
3823static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3824 uint64_t Address, const void *Decoder) {
3825 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3826 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3827 if (sign1 != sign2) return MCDisassembler::Fail;
3828
3829 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3830 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3831 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3832 Val |= sign1 << 12;
3833 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3834
3835 return MCDisassembler::Success;
3836}
3837