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gerrit-public.fairphone.software / platform / external / llvm / 9ead2c0609104d6feecdba3b70f0c6bb1ffe3094 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 6e4bb8c64cbf476f5a6cbec1bfd5712ba94bb26d [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]50 raw_ostream &vStream,
51 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]52
53 /// getEDInfo - See MCDisassembler.
54 EDInstInfo *getEDInfo() const;
55private:
56};
57
58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59class ThumbDisassembler : public MCDisassembler {
60public:
61 /// Constructor - Initializes the disassembler.
62 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]65 }
66
67 ~ThumbDisassembler() {
68 }
69
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
72 uint64_t &size,
73 const MemoryObject &region,
74 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]75 raw_ostream &vStream,
76 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]77
78 /// getEDInfo - See MCDisassembler.
79 EDInstInfo *getEDInfo() const;
80private:
81 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]82 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]83 void UpdateThumbVFPPredicate(MCInst&) const;
84};
85}
86
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]87static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]88 switch (In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
91 return true;
92 case MCDisassembler::SoftFail:
93 Out = In;
94 return true;
95 case MCDisassembler::Fail:
96 Out = In;
97 return false;
98 }
99 return false;
100}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]101
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]102
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103// Forward declare these because the autogenerated code will reference them.
104// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]106 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]107static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]122static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]126static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]128
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]139static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]140 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]146static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]147 unsigned Insn,
148 uint64_t Address,
149 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]156static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
158
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]159static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 unsigned Insn,
161 uint64_t Adddress,
162 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]247static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]248 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]272static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]274static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]290static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]296static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]298static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]300static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]302static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
303 uint64_t Address, const void *Decoder);
304static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
305 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]306static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]308static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
309 uint64_t Address, const void *Decoder);
310
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]311
312#include "ARMGenDisassemblerTables.inc"
313#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]314#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]315
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]316static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
317 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]318}
319
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]320static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
321 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]322}
323
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]324EDInstInfo *ARMDisassembler::getEDInfo() const {
325 return instInfoARM;
326}
327
328EDInstInfo *ThumbDisassembler::getEDInfo() const {
329 return instInfoARM;
330}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]332DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]333 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]334 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]335 raw_ostream &os,
336 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 uint8_t bytes[4];
338
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]339 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
340 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
341
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]342 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]343 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
344 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]345 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]346 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347
348 // Encoded as a small-endian 32-bit word in the stream.
349 uint32_t insn = (bytes[3] << 24) |
350 (bytes[2] << 16) |
351 (bytes[1] << 8) |
352 (bytes[0] << 0);
353
354 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]355 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]356 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]358 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]359 }
360
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]361 // VFP and NEON instructions, similarly, are shared between ARM
362 // and Thumb modes.
363 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]364 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]365 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]366 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]367 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]368 }
369
370 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]371 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]372 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]373 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 // Add a fake predicate operand, because we share these instruction
375 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]376 if (!DecodePredicateOperand(MI, 0xE, Address, this))
377 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]378 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]379 }
380
381 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]382 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]383 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]384 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]385 // Add a fake predicate operand, because we share these instruction
386 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]387 if (!DecodePredicateOperand(MI, 0xE, Address, this))
388 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]389 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]390 }
391
392 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]393 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]394 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]395 Size = 4;
396 // Add a fake predicate operand, because we share these instruction
397 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]398 if (!DecodePredicateOperand(MI, 0xE, Address, this))
399 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]400 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]401 }
402
403 MI.clear();
404
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]405 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]406 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]407}
408
409namespace llvm {
410extern MCInstrDesc ARMInsts[];
411}
412
413// Thumb1 instructions don't have explicit S bits. Rather, they
414// implicitly set CPSR. Since it's not represented in the encoding, the
415// auto-generated decoder won't inject the CPSR operand. We need to fix
416// that as a post-pass.
417static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
418 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]419 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]420 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]421 for (unsigned i = 0; i < NumOps; ++i, ++I) {
422 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]423 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]424 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]425 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
426 return;
427 }
428 }
429
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]430 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]431}
432
433// Most Thumb instructions don't have explicit predicates in the
434// encoding, but rather get their predicates from IT context. We need
435// to fix up the predicate operands using this context information as a
436// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]437MCDisassembler::DecodeStatus
438ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]439 MCDisassembler::DecodeStatus S = Success;
440
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]441 // A few instructions actually have predicates encoded in them. Don't
442 // try to overwrite it if we're seeing one of those.
443 switch (MI.getOpcode()) {
444 case ARM::tBcc:
445 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]446 case ARM::tCBZ:
447 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]448 case ARM::tCPS:
449 case ARM::t2CPS3p:
450 case ARM::t2CPS2p:
451 case ARM::t2CPS1p:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]452 // Some instructions (mostly conditional branches) are not
453 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]454 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]455 S = SoftFail;
456 else
457 return Success;
458 break;
459 case ARM::tB:
460 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]461 case ARM::t2TBB:
462 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]463 // Some instructions (mostly unconditional branches) can
464 // only appears at the end of, or outside of, an IT.
465 if (ITBlock.size() > 1)
466 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]467 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]468 default:
469 break;
470 }
471
472 // If we're in an IT block, base the predicate on that. Otherwise,
473 // assume a predicate of AL.
474 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]475 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]476 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]477 if (CC == 0xF)
478 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]479 ITBlock.pop_back();
480 } else
481 CC = ARMCC::AL;
482
483 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]484 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]485 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]486 for (unsigned i = 0; i < NumOps; ++i, ++I) {
487 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]488 if (OpInfo[i].isPredicate()) {
489 I = MI.insert(I, MCOperand::CreateImm(CC));
490 ++I;
491 if (CC == ARMCC::AL)
492 MI.insert(I, MCOperand::CreateReg(0));
493 else
494 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]495 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]496 }
497 }
498
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]499 I = MI.insert(I, MCOperand::CreateImm(CC));
500 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]501 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]502 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]503 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]504 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]505
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]506 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]507}
508
509// Thumb VFP instructions are a special case. Because we share their
510// encodings between ARM and Thumb modes, and they are predicable in ARM
511// mode, the auto-generated decoder will give them an (incorrect)
512// predicate operand. We need to rewrite these operands based on the IT
513// context as a post-pass.
514void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
515 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]516 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]517 CC = ITBlock.back();
518 ITBlock.pop_back();
519 } else
520 CC = ARMCC::AL;
521
522 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
523 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]524 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
525 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]526 if (OpInfo[i].isPredicate() ) {
527 I->setImm(CC);
528 ++I;
529 if (CC == ARMCC::AL)
530 I->setReg(0);
531 else
532 I->setReg(ARM::CPSR);
533 return;
534 }
535 }
536}
537
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]538DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]539 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]540 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]541 raw_ostream &os,
542 raw_ostream &cs) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]543 uint8_t bytes[4];
544
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]545 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
546 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
547
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]548 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]549 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
550 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]551 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]552 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]553
554 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]555 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]556 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]557 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]558 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]559 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]560 }
561
562 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]563 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]564 if (result) {
565 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]566 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]567 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]568 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]569 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]570 }
571
572 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]573 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]574 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]575 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]576 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]577
578 // If we find an IT instruction, we need to parse its condition
579 // code and mask operands so that we can apply them correctly
580 // to the subsequent instructions.
581 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]582 // Nested IT blocks are UNPREDICTABLE.
583 if (!ITBlock.empty())
584 return MCDisassembler::SoftFail;
585
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]586 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]587 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]588 unsigned Mask = MI.getOperand(1).getImm();
589 unsigned CondBit0 = Mask >> 4 & 1;
590 unsigned NumTZ = CountTrailingZeros_32(Mask);
591 assert(NumTZ <= 3 && "Invalid IT mask!");
592 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
593 bool T = ((Mask >> Pos) & 1) == CondBit0;
594 if (T)
595 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]596 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]597 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]598 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]599
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]600 ITBlock.push_back(firstcond);
601 }
602
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]603 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]604 }
605
606 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]607 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
608 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]609 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]610 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]611
612 uint32_t insn32 = (bytes[3] << 8) |
613 (bytes[2] << 0) |
614 (bytes[1] << 24) |
615 (bytes[0] << 16);
616 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]617 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]618 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]619 Size = 4;
620 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]621 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]622 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]623 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]624 }
625
626 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]627 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]628 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]629 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]630 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]631 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]632 }
633
634 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]635 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]636 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 Size = 4;
638 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]639 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]640 }
641
642 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]643 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]644 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]645 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]646 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]647 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]648 }
649
650 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
651 MI.clear();
652 uint32_t NEONLdStInsn = insn32;
653 NEONLdStInsn &= 0xF0FFFFFF;
654 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]655 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]656 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]657 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]658 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]659 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]660 }
661 }
662
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]663 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]664 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]665 uint32_t NEONDataInsn = insn32;
666 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
667 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
668 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]669 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]670 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]671 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]672 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]673 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]674 }
675 }
676
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]677 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]678 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]679}
680
681
682extern "C" void LLVMInitializeARMDisassembler() {
683 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
684 createARMDisassembler);
685 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
686 createThumbDisassembler);
687}
688
689static const unsigned GPRDecoderTable[] = {
690 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
691 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
692 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
693 ARM::R12, ARM::SP, ARM::LR, ARM::PC
694};
695
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]696static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]697 uint64_t Address, const void *Decoder) {
698 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]699 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]700
701 unsigned Register = GPRDecoderTable[RegNo];
702 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]703 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704}
705
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]706static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]707DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
708 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]709 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]710 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
711}
712
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]713static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]714 uint64_t Address, const void *Decoder) {
715 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]716 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]717 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
718}
719
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]720static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]721 uint64_t Address, const void *Decoder) {
722 unsigned Register = 0;
723 switch (RegNo) {
724 case 0:
725 Register = ARM::R0;
726 break;
727 case 1:
728 Register = ARM::R1;
729 break;
730 case 2:
731 Register = ARM::R2;
732 break;
733 case 3:
734 Register = ARM::R3;
735 break;
736 case 9:
737 Register = ARM::R9;
738 break;
739 case 12:
740 Register = ARM::R12;
741 break;
742 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]743 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]744 }
745
746 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]747 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]748}
749
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]750static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]751 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]752 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
754}
755
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]756static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]757 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
758 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
759 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
760 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
761 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
762 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
763 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
764 ARM::S28, ARM::S29, ARM::S30, ARM::S31
765};
766
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]767static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]768 uint64_t Address, const void *Decoder) {
769 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]770 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]771
772 unsigned Register = SPRDecoderTable[RegNo];
773 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]774 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]775}
776
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]777static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]778 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
779 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
780 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
781 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
782 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
783 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
784 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
785 ARM::D28, ARM::D29, ARM::D30, ARM::D31
786};
787
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]788static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]789 uint64_t Address, const void *Decoder) {
790 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]791 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]792
793 unsigned Register = DPRDecoderTable[RegNo];
794 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]795 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]796}
797
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]798static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]799 uint64_t Address, const void *Decoder) {
800 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]801 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]802 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
803}
804
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]805static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]806DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
807 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]808 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]809 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]810 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
811}
812
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]813static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]814 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
815 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
816 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
817 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
818};
819
820
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]821static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]822 uint64_t Address, const void *Decoder) {
823 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]824 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]825 RegNo >>= 1;
826
827 unsigned Register = QPRDecoderTable[RegNo];
828 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]829 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]830}
831
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]832static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]833 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]834 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]835 // AL predicate is not allowed on Thumb1 branches.
836 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]837 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]838 Inst.addOperand(MCOperand::CreateImm(Val));
839 if (Val == ARMCC::AL) {
840 Inst.addOperand(MCOperand::CreateReg(0));
841 } else
842 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]843 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]844}
845
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]846static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]847 uint64_t Address, const void *Decoder) {
848 if (Val)
849 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
850 else
851 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]852 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]853}
854
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]855static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]856 uint64_t Address, const void *Decoder) {
857 uint32_t imm = Val & 0xFF;
858 uint32_t rot = (Val & 0xF00) >> 7;
859 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
860 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]861 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]862}
863
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]864static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]865 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]866 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]867
868 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
869 unsigned type = fieldFromInstruction32(Val, 5, 2);
870 unsigned imm = fieldFromInstruction32(Val, 7, 5);
871
872 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
874 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]875
876 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
877 switch (type) {
878 case 0:
879 Shift = ARM_AM::lsl;
880 break;
881 case 1:
882 Shift = ARM_AM::lsr;
883 break;
884 case 2:
885 Shift = ARM_AM::asr;
886 break;
887 case 3:
888 Shift = ARM_AM::ror;
889 break;
890 }
891
892 if (Shift == ARM_AM::ror && imm == 0)
893 Shift = ARM_AM::rrx;
894
895 unsigned Op = Shift | (imm << 3);
896 Inst.addOperand(MCOperand::CreateImm(Op));
897
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]898 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]899}
900
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]901static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]902 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]903 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]904
905 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
906 unsigned type = fieldFromInstruction32(Val, 5, 2);
907 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
908
909 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]910 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
911 return MCDisassembler::Fail;
912 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
913 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]914
915 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
916 switch (type) {
917 case 0:
918 Shift = ARM_AM::lsl;
919 break;
920 case 1:
921 Shift = ARM_AM::lsr;
922 break;
923 case 2:
924 Shift = ARM_AM::asr;
925 break;
926 case 3:
927 Shift = ARM_AM::ror;
928 break;
929 }
930
931 Inst.addOperand(MCOperand::CreateImm(Shift));
932
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]933 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]934}
935
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]936static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]937 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]938 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]939
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]940 bool writebackLoad = false;
941 unsigned writebackReg = 0;
942 switch (Inst.getOpcode()) {
943 default:
944 break;
945 case ARM::LDMIA_UPD:
946 case ARM::LDMDB_UPD:
947 case ARM::LDMIB_UPD:
948 case ARM::LDMDA_UPD:
949 case ARM::t2LDMIA_UPD:
950 case ARM::t2LDMDB_UPD:
951 writebackLoad = true;
952 writebackReg = Inst.getOperand(0).getReg();
953 break;
954 }
955
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]956 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]957 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]959 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]960 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
961 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]962 // Writeback not allowed if Rn is in the target list.
963 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
964 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]965 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]966 }
967
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]968 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]969}
970
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]971static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]972 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]973 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]974
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]975 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
976 unsigned regs = Val & 0xFF;
977
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]978 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
979 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]980 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]981 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
982 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]983 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]984
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]985 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]986}
987
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]988static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]989 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]990 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]991
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]992 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
993 unsigned regs = (Val & 0xFF) / 2;
994
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]995 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
996 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]997 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]998 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
999 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1000 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1001
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1002 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1003}
1004
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1005static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1006 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1007 // This operand encodes a mask of contiguous zeros between a specified MSB
1008 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1009 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1010 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1011 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1012 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1013 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1014
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1015 DecodeStatus S = MCDisassembler::Success;
1016 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1017
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1018 uint32_t msb_mask = 0xFFFFFFFF;
1019 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1020 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1021
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1022 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1023 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1024}
1025
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1026static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1027 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1028 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1029
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1030 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1031 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1032 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1033 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1034 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1035 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1036
1037 switch (Inst.getOpcode()) {
1038 case ARM::LDC_OFFSET:
1039 case ARM::LDC_PRE:
1040 case ARM::LDC_POST:
1041 case ARM::LDC_OPTION:
1042 case ARM::LDCL_OFFSET:
1043 case ARM::LDCL_PRE:
1044 case ARM::LDCL_POST:
1045 case ARM::LDCL_OPTION:
1046 case ARM::STC_OFFSET:
1047 case ARM::STC_PRE:
1048 case ARM::STC_POST:
1049 case ARM::STC_OPTION:
1050 case ARM::STCL_OFFSET:
1051 case ARM::STCL_PRE:
1052 case ARM::STCL_POST:
1053 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1054 case ARM::t2LDC_OFFSET:
1055 case ARM::t2LDC_PRE:
1056 case ARM::t2LDC_POST:
1057 case ARM::t2LDC_OPTION:
1058 case ARM::t2LDCL_OFFSET:
1059 case ARM::t2LDCL_PRE:
1060 case ARM::t2LDCL_POST:
1061 case ARM::t2LDCL_OPTION:
1062 case ARM::t2STC_OFFSET:
1063 case ARM::t2STC_PRE:
1064 case ARM::t2STC_POST:
1065 case ARM::t2STC_OPTION:
1066 case ARM::t2STCL_OFFSET:
1067 case ARM::t2STCL_PRE:
1068 case ARM::t2STCL_POST:
1069 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1070 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1071 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1072 break;
1073 default:
1074 break;
1075 }
1076
1077 Inst.addOperand(MCOperand::CreateImm(coproc));
1078 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1080 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1081 switch (Inst.getOpcode()) {
1082 case ARM::LDC_OPTION:
1083 case ARM::LDCL_OPTION:
1084 case ARM::LDC2_OPTION:
1085 case ARM::LDC2L_OPTION:
1086 case ARM::STC_OPTION:
1087 case ARM::STCL_OPTION:
1088 case ARM::STC2_OPTION:
1089 case ARM::STC2L_OPTION:
1090 case ARM::LDCL_POST:
1091 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1092 case ARM::LDC2L_POST:
1093 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1094 case ARM::t2LDC_OPTION:
1095 case ARM::t2LDCL_OPTION:
1096 case ARM::t2STC_OPTION:
1097 case ARM::t2STCL_OPTION:
1098 case ARM::t2LDCL_POST:
1099 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1100 break;
1101 default:
1102 Inst.addOperand(MCOperand::CreateReg(0));
1103 break;
1104 }
1105
1106 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1107 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1108
1109 bool writeback = (P == 0) || (W == 1);
1110 unsigned idx_mode = 0;
1111 if (P && writeback)
1112 idx_mode = ARMII::IndexModePre;
1113 else if (!P && writeback)
1114 idx_mode = ARMII::IndexModePost;
1115
1116 switch (Inst.getOpcode()) {
1117 case ARM::LDCL_POST:
1118 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1119 case ARM::t2LDCL_POST:
1120 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1121 case ARM::LDC2L_POST:
1122 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1123 imm |= U << 8;
1124 case ARM::LDC_OPTION:
1125 case ARM::LDCL_OPTION:
1126 case ARM::LDC2_OPTION:
1127 case ARM::LDC2L_OPTION:
1128 case ARM::STC_OPTION:
1129 case ARM::STCL_OPTION:
1130 case ARM::STC2_OPTION:
1131 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1132 case ARM::t2LDC_OPTION:
1133 case ARM::t2LDCL_OPTION:
1134 case ARM::t2STC_OPTION:
1135 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1136 Inst.addOperand(MCOperand::CreateImm(imm));
1137 break;
1138 default:
1139 if (U)
1140 Inst.addOperand(MCOperand::CreateImm(
1141 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1142 else
1143 Inst.addOperand(MCOperand::CreateImm(
1144 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1145 break;
1146 }
1147
1148 switch (Inst.getOpcode()) {
1149 case ARM::LDC_OFFSET:
1150 case ARM::LDC_PRE:
1151 case ARM::LDC_POST:
1152 case ARM::LDC_OPTION:
1153 case ARM::LDCL_OFFSET:
1154 case ARM::LDCL_PRE:
1155 case ARM::LDCL_POST:
1156 case ARM::LDCL_OPTION:
1157 case ARM::STC_OFFSET:
1158 case ARM::STC_PRE:
1159 case ARM::STC_POST:
1160 case ARM::STC_OPTION:
1161 case ARM::STCL_OFFSET:
1162 case ARM::STCL_PRE:
1163 case ARM::STCL_POST:
1164 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1165 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1166 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1167 break;
1168 default:
1169 break;
1170 }
1171
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1172 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1173}
1174
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1175static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1176DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1177 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1178 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1179
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1180 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1181 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1182 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1183 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1184 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1185 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1186 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1187 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1188
1189 // On stores, the writeback operand precedes Rt.
1190 switch (Inst.getOpcode()) {
1191 case ARM::STR_POST_IMM:
1192 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1193 case ARM::STRB_POST_IMM:
1194 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1195 case ARM::STRT_POST_REG:
1196 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1197 case ARM::STRBT_POST_REG:
1198 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1199 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1200 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1201 break;
1202 default:
1203 break;
1204 }
1205
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1207 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1208
1209 // On loads, the writeback operand comes after Rt.
1210 switch (Inst.getOpcode()) {
1211 case ARM::LDR_POST_IMM:
1212 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1213 case ARM::LDRB_POST_IMM:
1214 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1215 case ARM::LDRBT_POST_REG:
1216 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1217 case ARM::LDRT_POST_REG:
1218 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1220 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1221 break;
1222 default:
1223 break;
1224 }
1225
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1227 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1228
1229 ARM_AM::AddrOpc Op = ARM_AM::add;
1230 if (!fieldFromInstruction32(Insn, 23, 1))
1231 Op = ARM_AM::sub;
1232
1233 bool writeback = (P == 0) || (W == 1);
1234 unsigned idx_mode = 0;
1235 if (P && writeback)
1236 idx_mode = ARMII::IndexModePre;
1237 else if (!P && writeback)
1238 idx_mode = ARMII::IndexModePost;
1239
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1240 if (writeback && (Rn == 15 || Rn == Rt))
1241 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1242
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1243 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1244 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1245 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1246 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1247 switch( fieldFromInstruction32(Insn, 5, 2)) {
1248 case 0:
1249 Opc = ARM_AM::lsl;
1250 break;
1251 case 1:
1252 Opc = ARM_AM::lsr;
1253 break;
1254 case 2:
1255 Opc = ARM_AM::asr;
1256 break;
1257 case 3:
1258 Opc = ARM_AM::ror;
1259 break;
1260 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1261 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1262 }
1263 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1264 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1265
1266 Inst.addOperand(MCOperand::CreateImm(imm));
1267 } else {
1268 Inst.addOperand(MCOperand::CreateReg(0));
1269 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1270 Inst.addOperand(MCOperand::CreateImm(tmp));
1271 }
1272
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1273 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1274 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1275
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1276 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1277}
1278
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1279static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1280 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1281 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1282
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1283 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1284 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1285 unsigned type = fieldFromInstruction32(Val, 5, 2);
1286 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1287 unsigned U = fieldFromInstruction32(Val, 12, 1);
1288
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1289 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1290 switch (type) {
1291 case 0:
1292 ShOp = ARM_AM::lsl;
1293 break;
1294 case 1:
1295 ShOp = ARM_AM::lsr;
1296 break;
1297 case 2:
1298 ShOp = ARM_AM::asr;
1299 break;
1300 case 3:
1301 ShOp = ARM_AM::ror;
1302 break;
1303 }
1304
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1306 return MCDisassembler::Fail;
1307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1308 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1309 unsigned shift;
1310 if (U)
1311 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1312 else
1313 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1314 Inst.addOperand(MCOperand::CreateImm(shift));
1315
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1316 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1317}
1318
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1319static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1320DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1321 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1322 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1323
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1324 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1325 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1326 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1327 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1328 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1329 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1330 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1331 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1332 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1333
1334 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1335
1336 // For {LD,ST}RD, Rt must be even, else undefined.
1337 switch (Inst.getOpcode()) {
1338 case ARM::STRD:
1339 case ARM::STRD_PRE:
1340 case ARM::STRD_POST:
1341 case ARM::LDRD:
1342 case ARM::LDRD_PRE:
1343 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1344 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1345 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1346 default:
1347 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1348 }
1349
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1350 if (writeback) { // Writeback
1351 if (P)
1352 U |= ARMII::IndexModePre << 9;
1353 else
1354 U |= ARMII::IndexModePost << 9;
1355
1356 // On stores, the writeback operand precedes Rt.
1357 switch (Inst.getOpcode()) {
1358 case ARM::STRD:
1359 case ARM::STRD_PRE:
1360 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1361 case ARM::STRH:
1362 case ARM::STRH_PRE:
1363 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1365 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1366 break;
1367 default:
1368 break;
1369 }
1370 }
1371
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1373 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1374 switch (Inst.getOpcode()) {
1375 case ARM::STRD:
1376 case ARM::STRD_PRE:
1377 case ARM::STRD_POST:
1378 case ARM::LDRD:
1379 case ARM::LDRD_PRE:
1380 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1382 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1383 break;
1384 default:
1385 break;
1386 }
1387
1388 if (writeback) {
1389 // On loads, the writeback operand comes after Rt.
1390 switch (Inst.getOpcode()) {
1391 case ARM::LDRD:
1392 case ARM::LDRD_PRE:
1393 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1394 case ARM::LDRH:
1395 case ARM::LDRH_PRE:
1396 case ARM::LDRH_POST:
1397 case ARM::LDRSH:
1398 case ARM::LDRSH_PRE:
1399 case ARM::LDRSH_POST:
1400 case ARM::LDRSB:
1401 case ARM::LDRSB_PRE:
1402 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1403 case ARM::LDRHTr:
1404 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1406 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1407 break;
1408 default:
1409 break;
1410 }
1411 }
1412
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1414 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1415
1416 if (type) {
1417 Inst.addOperand(MCOperand::CreateReg(0));
1418 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1419 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1421 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1422 Inst.addOperand(MCOperand::CreateImm(U));
1423 }
1424
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1425 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1426 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1427
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1428 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1429}
1430
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1431static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1432 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1433 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1434
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1435 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1436 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1437
1438 switch (mode) {
1439 case 0:
1440 mode = ARM_AM::da;
1441 break;
1442 case 1:
1443 mode = ARM_AM::ia;
1444 break;
1445 case 2:
1446 mode = ARM_AM::db;
1447 break;
1448 case 3:
1449 mode = ARM_AM::ib;
1450 break;
1451 }
1452
1453 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1455 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1456
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1457 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1458}
1459
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1460static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1461 unsigned Insn,
1462 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1463 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1464
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1465 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1466 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1467 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1468
1469 if (pred == 0xF) {
1470 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1471 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1472 Inst.setOpcode(ARM::RFEDA);
1473 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1474 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1475 Inst.setOpcode(ARM::RFEDA_UPD);
1476 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1477 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1478 Inst.setOpcode(ARM::RFEDB);
1479 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1480 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1481 Inst.setOpcode(ARM::RFEDB_UPD);
1482 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1483 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1484 Inst.setOpcode(ARM::RFEIA);
1485 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1486 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1487 Inst.setOpcode(ARM::RFEIA_UPD);
1488 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1489 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1490 Inst.setOpcode(ARM::RFEIB);
1491 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1492 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1493 Inst.setOpcode(ARM::RFEIB_UPD);
1494 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1495 case ARM::STMDA:
1496 Inst.setOpcode(ARM::SRSDA);
1497 break;
1498 case ARM::STMDA_UPD:
1499 Inst.setOpcode(ARM::SRSDA_UPD);
1500 break;
1501 case ARM::STMDB:
1502 Inst.setOpcode(ARM::SRSDB);
1503 break;
1504 case ARM::STMDB_UPD:
1505 Inst.setOpcode(ARM::SRSDB_UPD);
1506 break;
1507 case ARM::STMIA:
1508 Inst.setOpcode(ARM::SRSIA);
1509 break;
1510 case ARM::STMIA_UPD:
1511 Inst.setOpcode(ARM::SRSIA_UPD);
1512 break;
1513 case ARM::STMIB:
1514 Inst.setOpcode(ARM::SRSIB);
1515 break;
1516 case ARM::STMIB_UPD:
1517 Inst.setOpcode(ARM::SRSIB_UPD);
1518 break;
1519 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1520 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1521 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1522
1523 // For stores (which become SRS's, the only operand is the mode.
1524 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1525 Inst.addOperand(
1526 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1527 return S;
1528 }
1529
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1530 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1531 }
1532
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1534 return MCDisassembler::Fail;
1535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1536 return MCDisassembler::Fail; // Tied
1537 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1538 return MCDisassembler::Fail;
1539 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1540 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1541
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1542 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1543}
1544
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1545static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1546 uint64_t Address, const void *Decoder) {
1547 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1548 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1549 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1550 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1551
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1552 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1553
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1554 // imod == '01' --> UNPREDICTABLE
1555 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1556 // return failure here. The '01' imod value is unprintable, so there's
1557 // nothing useful we could do even if we returned UNPREDICTABLE.
1558
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1559 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1560
1561 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1562 Inst.setOpcode(ARM::CPS3p);
1563 Inst.addOperand(MCOperand::CreateImm(imod));
1564 Inst.addOperand(MCOperand::CreateImm(iflags));
1565 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1566 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1567 Inst.setOpcode(ARM::CPS2p);
1568 Inst.addOperand(MCOperand::CreateImm(imod));
1569 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1570 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1571 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1572 Inst.setOpcode(ARM::CPS1p);
1573 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1574 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1575 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1576 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1577 Inst.setOpcode(ARM::CPS1p);
1578 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1579 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1580 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1581
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1582 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1583}
1584
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1585static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1586 uint64_t Address, const void *Decoder) {
1587 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1588 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1589 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1590 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1591
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1592 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1593
1594 // imod == '01' --> UNPREDICTABLE
1595 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1596 // return failure here. The '01' imod value is unprintable, so there's
1597 // nothing useful we could do even if we returned UNPREDICTABLE.
1598
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1599 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1600
1601 if (imod && M) {
1602 Inst.setOpcode(ARM::t2CPS3p);
1603 Inst.addOperand(MCOperand::CreateImm(imod));
1604 Inst.addOperand(MCOperand::CreateImm(iflags));
1605 Inst.addOperand(MCOperand::CreateImm(mode));
1606 } else if (imod && !M) {
1607 Inst.setOpcode(ARM::t2CPS2p);
1608 Inst.addOperand(MCOperand::CreateImm(imod));
1609 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1610 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1611 } else if (!imod && M) {
1612 Inst.setOpcode(ARM::t2CPS1p);
1613 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1614 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1615 } else {
1616 // imod == '00' && M == '0' --> UNPREDICTABLE
1617 Inst.setOpcode(ARM::t2CPS1p);
1618 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1619 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1620 }
1621
1622 return S;
1623}
1624
1625
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1626static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1627 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1628 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1629
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1630 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1631 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1632 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1633 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1634 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1635
1636 if (pred == 0xF)
1637 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1638
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1639 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1640 return MCDisassembler::Fail;
1641 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1642 return MCDisassembler::Fail;
1643 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1644 return MCDisassembler::Fail;
1645 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1646 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1647
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1648 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1649 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1650
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1651 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1652}
1653
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1654static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1655 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1656 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1657
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1658 unsigned add = fieldFromInstruction32(Val, 12, 1);
1659 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1660 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1661
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1663 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1664
1665 if (!add) imm *= -1;
1666 if (imm == 0 && !add) imm = INT32_MIN;
1667 Inst.addOperand(MCOperand::CreateImm(imm));
1668
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1669 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1670}
1671
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1672static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1673 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1674 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1675
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1676 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1677 unsigned U = fieldFromInstruction32(Val, 8, 1);
1678 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1679
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1681 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1682
1683 if (U)
1684 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1685 else
1686 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1687
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1688 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1689}
1690
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1691static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1692 uint64_t Address, const void *Decoder) {
1693 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1694}
1695
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1696static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1697DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1698 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1699 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1700
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1701 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1702 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1703
1704 if (pred == 0xF) {
1705 Inst.setOpcode(ARM::BLXi);
1706 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1707 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1708 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1709 }
1710
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1711 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1712 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1713 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1714
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1715 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1716}
1717
1718
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1719static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1720 uint64_t Address, const void *Decoder) {
1721 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1722 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1723}
1724
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1725static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1726 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1727 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1728
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1729 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1730 unsigned align = fieldFromInstruction32(Val, 4, 2);
1731
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1733 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1734 if (!align)
1735 Inst.addOperand(MCOperand::CreateImm(0));
1736 else
1737 Inst.addOperand(MCOperand::CreateImm(4 << align));
1738
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1739 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1740}
1741
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1742static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1743 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1744 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1745
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1746 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1747 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1748 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1749 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1750 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1751 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1752
1753 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1754 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1755 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1756
1757 // Second output register
1758 switch (Inst.getOpcode()) {
1759 case ARM::VLD1q8:
1760 case ARM::VLD1q16:
1761 case ARM::VLD1q32:
1762 case ARM::VLD1q64:
1763 case ARM::VLD1q8_UPD:
1764 case ARM::VLD1q16_UPD:
1765 case ARM::VLD1q32_UPD:
1766 case ARM::VLD1q64_UPD:
1767 case ARM::VLD1d8T:
1768 case ARM::VLD1d16T:
1769 case ARM::VLD1d32T:
1770 case ARM::VLD1d64T:
1771 case ARM::VLD1d8T_UPD:
1772 case ARM::VLD1d16T_UPD:
1773 case ARM::VLD1d32T_UPD:
1774 case ARM::VLD1d64T_UPD:
1775 case ARM::VLD1d8Q:
1776 case ARM::VLD1d16Q:
1777 case ARM::VLD1d32Q:
1778 case ARM::VLD1d64Q:
1779 case ARM::VLD1d8Q_UPD:
1780 case ARM::VLD1d16Q_UPD:
1781 case ARM::VLD1d32Q_UPD:
1782 case ARM::VLD1d64Q_UPD:
1783 case ARM::VLD2d8:
1784 case ARM::VLD2d16:
1785 case ARM::VLD2d32:
1786 case ARM::VLD2d8_UPD:
1787 case ARM::VLD2d16_UPD:
1788 case ARM::VLD2d32_UPD:
1789 case ARM::VLD2q8:
1790 case ARM::VLD2q16:
1791 case ARM::VLD2q32:
1792 case ARM::VLD2q8_UPD:
1793 case ARM::VLD2q16_UPD:
1794 case ARM::VLD2q32_UPD:
1795 case ARM::VLD3d8:
1796 case ARM::VLD3d16:
1797 case ARM::VLD3d32:
1798 case ARM::VLD3d8_UPD:
1799 case ARM::VLD3d16_UPD:
1800 case ARM::VLD3d32_UPD:
1801 case ARM::VLD4d8:
1802 case ARM::VLD4d16:
1803 case ARM::VLD4d32:
1804 case ARM::VLD4d8_UPD:
1805 case ARM::VLD4d16_UPD:
1806 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1807 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1808 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1809 break;
1810 case ARM::VLD2b8:
1811 case ARM::VLD2b16:
1812 case ARM::VLD2b32:
1813 case ARM::VLD2b8_UPD:
1814 case ARM::VLD2b16_UPD:
1815 case ARM::VLD2b32_UPD:
1816 case ARM::VLD3q8:
1817 case ARM::VLD3q16:
1818 case ARM::VLD3q32:
1819 case ARM::VLD3q8_UPD:
1820 case ARM::VLD3q16_UPD:
1821 case ARM::VLD3q32_UPD:
1822 case ARM::VLD4q8:
1823 case ARM::VLD4q16:
1824 case ARM::VLD4q32:
1825 case ARM::VLD4q8_UPD:
1826 case ARM::VLD4q16_UPD:
1827 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1828 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1829 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1830 default:
1831 break;
1832 }
1833
1834 // Third output register
1835 switch(Inst.getOpcode()) {
1836 case ARM::VLD1d8T:
1837 case ARM::VLD1d16T:
1838 case ARM::VLD1d32T:
1839 case ARM::VLD1d64T:
1840 case ARM::VLD1d8T_UPD:
1841 case ARM::VLD1d16T_UPD:
1842 case ARM::VLD1d32T_UPD:
1843 case ARM::VLD1d64T_UPD:
1844 case ARM::VLD1d8Q:
1845 case ARM::VLD1d16Q:
1846 case ARM::VLD1d32Q:
1847 case ARM::VLD1d64Q:
1848 case ARM::VLD1d8Q_UPD:
1849 case ARM::VLD1d16Q_UPD:
1850 case ARM::VLD1d32Q_UPD:
1851 case ARM::VLD1d64Q_UPD:
1852 case ARM::VLD2q8:
1853 case ARM::VLD2q16:
1854 case ARM::VLD2q32:
1855 case ARM::VLD2q8_UPD:
1856 case ARM::VLD2q16_UPD:
1857 case ARM::VLD2q32_UPD:
1858 case ARM::VLD3d8:
1859 case ARM::VLD3d16:
1860 case ARM::VLD3d32:
1861 case ARM::VLD3d8_UPD:
1862 case ARM::VLD3d16_UPD:
1863 case ARM::VLD3d32_UPD:
1864 case ARM::VLD4d8:
1865 case ARM::VLD4d16:
1866 case ARM::VLD4d32:
1867 case ARM::VLD4d8_UPD:
1868 case ARM::VLD4d16_UPD:
1869 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1870 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1871 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1872 break;
1873 case ARM::VLD3q8:
1874 case ARM::VLD3q16:
1875 case ARM::VLD3q32:
1876 case ARM::VLD3q8_UPD:
1877 case ARM::VLD3q16_UPD:
1878 case ARM::VLD3q32_UPD:
1879 case ARM::VLD4q8:
1880 case ARM::VLD4q16:
1881 case ARM::VLD4q32:
1882 case ARM::VLD4q8_UPD:
1883 case ARM::VLD4q16_UPD:
1884 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1885 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1886 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1887 break;
1888 default:
1889 break;
1890 }
1891
1892 // Fourth output register
1893 switch (Inst.getOpcode()) {
1894 case ARM::VLD1d8Q:
1895 case ARM::VLD1d16Q:
1896 case ARM::VLD1d32Q:
1897 case ARM::VLD1d64Q:
1898 case ARM::VLD1d8Q_UPD:
1899 case ARM::VLD1d16Q_UPD:
1900 case ARM::VLD1d32Q_UPD:
1901 case ARM::VLD1d64Q_UPD:
1902 case ARM::VLD2q8:
1903 case ARM::VLD2q16:
1904 case ARM::VLD2q32:
1905 case ARM::VLD2q8_UPD:
1906 case ARM::VLD2q16_UPD:
1907 case ARM::VLD2q32_UPD:
1908 case ARM::VLD4d8:
1909 case ARM::VLD4d16:
1910 case ARM::VLD4d32:
1911 case ARM::VLD4d8_UPD:
1912 case ARM::VLD4d16_UPD:
1913 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1914 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1915 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1916 break;
1917 case ARM::VLD4q8:
1918 case ARM::VLD4q16:
1919 case ARM::VLD4q32:
1920 case ARM::VLD4q8_UPD:
1921 case ARM::VLD4q16_UPD:
1922 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1923 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1924 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1925 break;
1926 default:
1927 break;
1928 }
1929
1930 // Writeback operand
1931 switch (Inst.getOpcode()) {
1932 case ARM::VLD1d8_UPD:
1933 case ARM::VLD1d16_UPD:
1934 case ARM::VLD1d32_UPD:
1935 case ARM::VLD1d64_UPD:
1936 case ARM::VLD1q8_UPD:
1937 case ARM::VLD1q16_UPD:
1938 case ARM::VLD1q32_UPD:
1939 case ARM::VLD1q64_UPD:
1940 case ARM::VLD1d8T_UPD:
1941 case ARM::VLD1d16T_UPD:
1942 case ARM::VLD1d32T_UPD:
1943 case ARM::VLD1d64T_UPD:
1944 case ARM::VLD1d8Q_UPD:
1945 case ARM::VLD1d16Q_UPD:
1946 case ARM::VLD1d32Q_UPD:
1947 case ARM::VLD1d64Q_UPD:
1948 case ARM::VLD2d8_UPD:
1949 case ARM::VLD2d16_UPD:
1950 case ARM::VLD2d32_UPD:
1951 case ARM::VLD2q8_UPD:
1952 case ARM::VLD2q16_UPD:
1953 case ARM::VLD2q32_UPD:
1954 case ARM::VLD2b8_UPD:
1955 case ARM::VLD2b16_UPD:
1956 case ARM::VLD2b32_UPD:
1957 case ARM::VLD3d8_UPD:
1958 case ARM::VLD3d16_UPD:
1959 case ARM::VLD3d32_UPD:
1960 case ARM::VLD3q8_UPD:
1961 case ARM::VLD3q16_UPD:
1962 case ARM::VLD3q32_UPD:
1963 case ARM::VLD4d8_UPD:
1964 case ARM::VLD4d16_UPD:
1965 case ARM::VLD4d32_UPD:
1966 case ARM::VLD4q8_UPD:
1967 case ARM::VLD4q16_UPD:
1968 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1969 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1970 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1971 break;
1972 default:
1973 break;
1974 }
1975
1976 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1977 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1978 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1979
1980 // AddrMode6 Offset (register)
1981 if (Rm == 0xD)
1982 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1983 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1984 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1985 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1986 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1987
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1988 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1989}
1990
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1991static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1992 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1993 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1994
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1995 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1996 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1997 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1998 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1999 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2000 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2001
2002 // Writeback Operand
2003 switch (Inst.getOpcode()) {
2004 case ARM::VST1d8_UPD:
2005 case ARM::VST1d16_UPD:
2006 case ARM::VST1d32_UPD:
2007 case ARM::VST1d64_UPD:
2008 case ARM::VST1q8_UPD:
2009 case ARM::VST1q16_UPD:
2010 case ARM::VST1q32_UPD:
2011 case ARM::VST1q64_UPD:
2012 case ARM::VST1d8T_UPD:
2013 case ARM::VST1d16T_UPD:
2014 case ARM::VST1d32T_UPD:
2015 case ARM::VST1d64T_UPD:
2016 case ARM::VST1d8Q_UPD:
2017 case ARM::VST1d16Q_UPD:
2018 case ARM::VST1d32Q_UPD:
2019 case ARM::VST1d64Q_UPD:
2020 case ARM::VST2d8_UPD:
2021 case ARM::VST2d16_UPD:
2022 case ARM::VST2d32_UPD:
2023 case ARM::VST2q8_UPD:
2024 case ARM::VST2q16_UPD:
2025 case ARM::VST2q32_UPD:
2026 case ARM::VST2b8_UPD:
2027 case ARM::VST2b16_UPD:
2028 case ARM::VST2b32_UPD:
2029 case ARM::VST3d8_UPD:
2030 case ARM::VST3d16_UPD:
2031 case ARM::VST3d32_UPD:
2032 case ARM::VST3q8_UPD:
2033 case ARM::VST3q16_UPD:
2034 case ARM::VST3q32_UPD:
2035 case ARM::VST4d8_UPD:
2036 case ARM::VST4d16_UPD:
2037 case ARM::VST4d32_UPD:
2038 case ARM::VST4q8_UPD:
2039 case ARM::VST4q16_UPD:
2040 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2041 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2042 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2043 break;
2044 default:
2045 break;
2046 }
2047
2048 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2049 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2050 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2051
2052 // AddrMode6 Offset (register)
2053 if (Rm == 0xD)
2054 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2055 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2057 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2058 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2059
2060 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2061 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2062 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2063
2064 // Second input register
2065 switch (Inst.getOpcode()) {
2066 case ARM::VST1q8:
2067 case ARM::VST1q16:
2068 case ARM::VST1q32:
2069 case ARM::VST1q64:
2070 case ARM::VST1q8_UPD:
2071 case ARM::VST1q16_UPD:
2072 case ARM::VST1q32_UPD:
2073 case ARM::VST1q64_UPD:
2074 case ARM::VST1d8T:
2075 case ARM::VST1d16T:
2076 case ARM::VST1d32T:
2077 case ARM::VST1d64T:
2078 case ARM::VST1d8T_UPD:
2079 case ARM::VST1d16T_UPD:
2080 case ARM::VST1d32T_UPD:
2081 case ARM::VST1d64T_UPD:
2082 case ARM::VST1d8Q:
2083 case ARM::VST1d16Q:
2084 case ARM::VST1d32Q:
2085 case ARM::VST1d64Q:
2086 case ARM::VST1d8Q_UPD:
2087 case ARM::VST1d16Q_UPD:
2088 case ARM::VST1d32Q_UPD:
2089 case ARM::VST1d64Q_UPD:
2090 case ARM::VST2d8:
2091 case ARM::VST2d16:
2092 case ARM::VST2d32:
2093 case ARM::VST2d8_UPD:
2094 case ARM::VST2d16_UPD:
2095 case ARM::VST2d32_UPD:
2096 case ARM::VST2q8:
2097 case ARM::VST2q16:
2098 case ARM::VST2q32:
2099 case ARM::VST2q8_UPD:
2100 case ARM::VST2q16_UPD:
2101 case ARM::VST2q32_UPD:
2102 case ARM::VST3d8:
2103 case ARM::VST3d16:
2104 case ARM::VST3d32:
2105 case ARM::VST3d8_UPD:
2106 case ARM::VST3d16_UPD:
2107 case ARM::VST3d32_UPD:
2108 case ARM::VST4d8:
2109 case ARM::VST4d16:
2110 case ARM::VST4d32:
2111 case ARM::VST4d8_UPD:
2112 case ARM::VST4d16_UPD:
2113 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2114 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2115 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2116 break;
2117 case ARM::VST2b8:
2118 case ARM::VST2b16:
2119 case ARM::VST2b32:
2120 case ARM::VST2b8_UPD:
2121 case ARM::VST2b16_UPD:
2122 case ARM::VST2b32_UPD:
2123 case ARM::VST3q8:
2124 case ARM::VST3q16:
2125 case ARM::VST3q32:
2126 case ARM::VST3q8_UPD:
2127 case ARM::VST3q16_UPD:
2128 case ARM::VST3q32_UPD:
2129 case ARM::VST4q8:
2130 case ARM::VST4q16:
2131 case ARM::VST4q32:
2132 case ARM::VST4q8_UPD:
2133 case ARM::VST4q16_UPD:
2134 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2135 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2136 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2137 break;
2138 default:
2139 break;
2140 }
2141
2142 // Third input register
2143 switch (Inst.getOpcode()) {
2144 case ARM::VST1d8T:
2145 case ARM::VST1d16T:
2146 case ARM::VST1d32T:
2147 case ARM::VST1d64T:
2148 case ARM::VST1d8T_UPD:
2149 case ARM::VST1d16T_UPD:
2150 case ARM::VST1d32T_UPD:
2151 case ARM::VST1d64T_UPD:
2152 case ARM::VST1d8Q:
2153 case ARM::VST1d16Q:
2154 case ARM::VST1d32Q:
2155 case ARM::VST1d64Q:
2156 case ARM::VST1d8Q_UPD:
2157 case ARM::VST1d16Q_UPD:
2158 case ARM::VST1d32Q_UPD:
2159 case ARM::VST1d64Q_UPD:
2160 case ARM::VST2q8:
2161 case ARM::VST2q16:
2162 case ARM::VST2q32:
2163 case ARM::VST2q8_UPD:
2164 case ARM::VST2q16_UPD:
2165 case ARM::VST2q32_UPD:
2166 case ARM::VST3d8:
2167 case ARM::VST3d16:
2168 case ARM::VST3d32:
2169 case ARM::VST3d8_UPD:
2170 case ARM::VST3d16_UPD:
2171 case ARM::VST3d32_UPD:
2172 case ARM::VST4d8:
2173 case ARM::VST4d16:
2174 case ARM::VST4d32:
2175 case ARM::VST4d8_UPD:
2176 case ARM::VST4d16_UPD:
2177 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2178 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2179 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2180 break;
2181 case ARM::VST3q8:
2182 case ARM::VST3q16:
2183 case ARM::VST3q32:
2184 case ARM::VST3q8_UPD:
2185 case ARM::VST3q16_UPD:
2186 case ARM::VST3q32_UPD:
2187 case ARM::VST4q8:
2188 case ARM::VST4q16:
2189 case ARM::VST4q32:
2190 case ARM::VST4q8_UPD:
2191 case ARM::VST4q16_UPD:
2192 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2193 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2194 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2195 break;
2196 default:
2197 break;
2198 }
2199
2200 // Fourth input register
2201 switch (Inst.getOpcode()) {
2202 case ARM::VST1d8Q:
2203 case ARM::VST1d16Q:
2204 case ARM::VST1d32Q:
2205 case ARM::VST1d64Q:
2206 case ARM::VST1d8Q_UPD:
2207 case ARM::VST1d16Q_UPD:
2208 case ARM::VST1d32Q_UPD:
2209 case ARM::VST1d64Q_UPD:
2210 case ARM::VST2q8:
2211 case ARM::VST2q16:
2212 case ARM::VST2q32:
2213 case ARM::VST2q8_UPD:
2214 case ARM::VST2q16_UPD:
2215 case ARM::VST2q32_UPD:
2216 case ARM::VST4d8:
2217 case ARM::VST4d16:
2218 case ARM::VST4d32:
2219 case ARM::VST4d8_UPD:
2220 case ARM::VST4d16_UPD:
2221 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2222 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2223 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2224 break;
2225 case ARM::VST4q8:
2226 case ARM::VST4q16:
2227 case ARM::VST4q32:
2228 case ARM::VST4q8_UPD:
2229 case ARM::VST4q16_UPD:
2230 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2231 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2232 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2233 break;
2234 default:
2235 break;
2236 }
2237
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2238 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2239}
2240
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2241static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2242 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2243 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2244
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2245 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2246 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2247 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2248 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2249 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2250 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2251 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2252
2253 align *= (1 << size);
2254
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2255 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2256 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2257 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2258 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2259 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2260 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2261 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2263 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2264 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2265
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2267 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2268 Inst.addOperand(MCOperand::CreateImm(align));
2269
2270 if (Rm == 0xD)
2271 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2272 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2274 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2275 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2276
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2277 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2278}
2279
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2280static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2281 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2282 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2283
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2284 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2285 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2286 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2287 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2288 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2289 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2290 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2291 align *= 2*size;
2292
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2293 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2294 return MCDisassembler::Fail;
2295 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2296 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2297 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2299 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2300 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2301
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2303 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2304 Inst.addOperand(MCOperand::CreateImm(align));
2305
2306 if (Rm == 0xD)
2307 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2308 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2310 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2311 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2312
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2313 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2314}
2315
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2316static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2317 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2318 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2319
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2320 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2321 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2322 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2323 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2324 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2325
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2326 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2327 return MCDisassembler::Fail;
2328 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2329 return MCDisassembler::Fail;
2330 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2331 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2332 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2334 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2335 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2336
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2338 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2339 Inst.addOperand(MCOperand::CreateImm(0));
2340
2341 if (Rm == 0xD)
2342 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2343 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2345 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2346 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2347
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2348 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2349}
2350
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2351static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2352 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2353 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2354
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2355 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2356 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2357 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2358 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2359 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2360 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2361 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2362
2363 if (size == 0x3) {
2364 size = 4;
2365 align = 16;
2366 } else {
2367 if (size == 2) {
2368 size = 1 << size;
2369 align *= 8;
2370 } else {
2371 size = 1 << size;
2372 align *= 4*size;
2373 }
2374 }
2375
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2376 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2377 return MCDisassembler::Fail;
2378 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2379 return MCDisassembler::Fail;
2380 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2381 return MCDisassembler::Fail;
2382 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2383 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2384 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2386 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2387 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2388
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2390 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2391 Inst.addOperand(MCOperand::CreateImm(align));
2392
2393 if (Rm == 0xD)
2394 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2395 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2397 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2398 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2399
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2400 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2401}
2402
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2403static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2404DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2405 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2406 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2407
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2408 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2409 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2410 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2411 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2412 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2413 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2414 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2415 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2416
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2417 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2418 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2419 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2420 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2421 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2422 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2423 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2424
2425 Inst.addOperand(MCOperand::CreateImm(imm));
2426
2427 switch (Inst.getOpcode()) {
2428 case ARM::VORRiv4i16:
2429 case ARM::VORRiv2i32:
2430 case ARM::VBICiv4i16:
2431 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2432 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2433 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2434 break;
2435 case ARM::VORRiv8i16:
2436 case ARM::VORRiv4i32:
2437 case ARM::VBICiv8i16:
2438 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2439 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2440 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2441 break;
2442 default:
2443 break;
2444 }
2445
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2446 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2447}
2448
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2449static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2450 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2451 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2452
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2453 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2454 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2455 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2456 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2457 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2458
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2459 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2460 return MCDisassembler::Fail;
2461 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2462 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2463 Inst.addOperand(MCOperand::CreateImm(8 << size));
2464
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2465 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2466}
2467
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2468static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2469 uint64_t Address, const void *Decoder) {
2470 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2471 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2472}
2473
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2474static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2475 uint64_t Address, const void *Decoder) {
2476 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2477 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2478}
2479
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2480static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2481 uint64_t Address, const void *Decoder) {
2482 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2483 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2484}
2485
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2486static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2487 uint64_t Address, const void *Decoder) {
2488 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2489 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2490}
2491
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2492static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2493 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2494 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2495
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2496 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2497 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2498 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2499 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2500 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2501 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2502 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2503 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2504
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2506 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2507 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2508 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2509 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2510 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2511
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2512 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2513 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2514 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2515 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2516
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2518 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2519
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2520 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521}
2522
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2523static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524 uint64_t Address, const void *Decoder) {
2525 // The immediate needs to be a fully instantiated float. However, the
2526 // auto-generated decoder is only able to fill in some of the bits
2527 // necessary. For instance, the 'b' bit is replicated multiple times,
2528 // and is even present in inverted form in one bit. We do a little
2529 // binary parsing here to fill in those missing bits, and then
2530 // reinterpret it all as a float.
2531 union {
2532 uint32_t integer;
2533 float fp;
2534 } fp_conv;
2535
2536 fp_conv.integer = Val;
2537 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2538 fp_conv.integer |= b << 26;
2539 fp_conv.integer |= b << 27;
2540 fp_conv.integer |= b << 28;
2541 fp_conv.integer |= b << 29;
2542 fp_conv.integer |= (~b & 0x1) << 30;
2543
2544 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2545 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2546}
2547
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2548static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2549 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2550 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2551
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2552 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2553 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2554
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2555 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2556 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2557
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2558 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2559 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2560 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2561 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2562 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2563 case ARM::tADDrSPi:
2564 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2565 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2566 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2567
2568 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2569 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2570}
2571
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2572static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2573 uint64_t Address, const void *Decoder) {
2574 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2575 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2576}
2577
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2578static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2579 uint64_t Address, const void *Decoder) {
2580 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2581 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2582}
2583
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2584static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2585 uint64_t Address, const void *Decoder) {
2586 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2587 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2588}
2589
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2590static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2591 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2592 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2593
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2594 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2595 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2596
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2597 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2598 return MCDisassembler::Fail;
2599 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2600 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2601
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2602 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2603}
2604
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2605static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2607 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2608
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2609 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2610 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2611
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2612 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2613 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2614 Inst.addOperand(MCOperand::CreateImm(imm));
2615
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2616 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2617}
2618
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2619static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2620 uint64_t Address, const void *Decoder) {
2621 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2622
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2623 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2624}
2625
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2626static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2627 uint64_t Address, const void *Decoder) {
2628 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2629 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2630
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2631 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2632}
2633
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2634static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2635 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2636 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2637
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2638 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2639 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2640 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2641
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2643 return MCDisassembler::Fail;
2644 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2645 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2646 Inst.addOperand(MCOperand::CreateImm(imm));
2647
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2648 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2649}
2650
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2651static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2652 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2653 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2654
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2655 switch (Inst.getOpcode()) {
2656 case ARM::t2PLDs:
2657 case ARM::t2PLDWs:
2658 case ARM::t2PLIs:
2659 break;
2660 default: {
2661 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2663 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2664 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2665 }
2666
2667 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2668 if (Rn == 0xF) {
2669 switch (Inst.getOpcode()) {
2670 case ARM::t2LDRBs:
2671 Inst.setOpcode(ARM::t2LDRBpci);
2672 break;
2673 case ARM::t2LDRHs:
2674 Inst.setOpcode(ARM::t2LDRHpci);
2675 break;
2676 case ARM::t2LDRSHs:
2677 Inst.setOpcode(ARM::t2LDRSHpci);
2678 break;
2679 case ARM::t2LDRSBs:
2680 Inst.setOpcode(ARM::t2LDRSBpci);
2681 break;
2682 case ARM::t2PLDs:
2683 Inst.setOpcode(ARM::t2PLDi12);
2684 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2685 break;
2686 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2687 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2688 }
2689
2690 int imm = fieldFromInstruction32(Insn, 0, 12);
2691 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2692 Inst.addOperand(MCOperand::CreateImm(imm));
2693
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2694 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2695 }
2696
2697 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2698 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2699 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2700 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2701 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2702
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2703 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2704}
2705
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2706static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2707 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2708 int imm = Val & 0xFF;
2709 if (!(Val & 0x100)) imm *= -1;
2710 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2711
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2712 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2713}
2714
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2715static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2716 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2717 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2718
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2719 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2720 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2721
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2723 return MCDisassembler::Fail;
2724 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2725 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2726
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2727 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2728}
2729
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2730static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2731 uint64_t Address, const void *Decoder) {
2732 DecodeStatus S = MCDisassembler::Success;
2733
2734 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2735 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2736
2737 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2738 return MCDisassembler::Fail;
2739
2740 Inst.addOperand(MCOperand::CreateImm(imm));
2741
2742 return S;
2743}
2744
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2745static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2746 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2747 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2748 if (Val == 0)
2749 imm = INT32_MIN;
2750 else if (!(Val & 0x100))
2751 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2752 Inst.addOperand(MCOperand::CreateImm(imm));
2753
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2754 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2755}
2756
2757
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2758static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2759 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2760 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2761
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2762 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2763 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2764
2765 // Some instructions always use an additive offset.
2766 switch (Inst.getOpcode()) {
2767 case ARM::t2LDRT:
2768 case ARM::t2LDRBT:
2769 case ARM::t2LDRHT:
2770 case ARM::t2LDRSBT:
2771 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2772 case ARM::t2STRT:
2773 case ARM::t2STRBT:
2774 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2775 imm |= 0x100;
2776 break;
2777 default:
2778 break;
2779 }
2780
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2782 return MCDisassembler::Fail;
2783 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2784 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2785
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2786 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2787}
2788
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2789static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2790 uint64_t Address, const void *Decoder) {
2791 DecodeStatus S = MCDisassembler::Success;
2792
2793 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2794 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2795 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2796 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2797 addr |= Rn << 9;
2798 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2799
2800 if (!load) {
2801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2802 return MCDisassembler::Fail;
2803 }
2804
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2805 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2806 return MCDisassembler::Fail;
2807
2808 if (load) {
2809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2810 return MCDisassembler::Fail;
2811 }
2812
2813 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2814 return MCDisassembler::Fail;
2815
2816 return S;
2817}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2818
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2819static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2820 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2821 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2822
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2823 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2824 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2825
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2827 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2828 Inst.addOperand(MCOperand::CreateImm(imm));
2829
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2830 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2831}
2832
2833
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2834static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2835 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2836 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2837
2838 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2839 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2840 Inst.addOperand(MCOperand::CreateImm(imm));
2841
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2842 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2843}
2844
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2845static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2846 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2847 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2848
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2849 if (Inst.getOpcode() == ARM::tADDrSP) {
2850 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2851 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2852
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2854 return MCDisassembler::Fail;
2855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2856 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2857 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2858 } else if (Inst.getOpcode() == ARM::tADDspr) {
2859 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2860
2861 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2862 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2864 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2865 }
2866
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2867 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2868}
2869
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2870static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2871 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2872 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2873 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2874
2875 Inst.addOperand(MCOperand::CreateImm(imod));
2876 Inst.addOperand(MCOperand::CreateImm(flags));
2877
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2878 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2879}
2880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2881static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2882 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2883 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2884 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2885 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2886
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2888 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2889 Inst.addOperand(MCOperand::CreateImm(add));
2890
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2891 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2892}
2893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2894static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2895 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2896 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2897 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2898}
2899
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2900static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2901 uint64_t Address, const void *Decoder) {
2902 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2903 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2904
2905 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2906 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907}
2908
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2909static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]2910DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
2911 uint64_t Address, const void *Decoder) {
2912 DecodeStatus S = MCDisassembler::Success;
2913
2914 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2915 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2916
2917 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
2918 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2919 return MCDisassembler::Fail;
2920 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2921 return MCDisassembler::Fail;
2922 return S;
2923}
2924
2925static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2926DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2927 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2928 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2929
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2930 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2931 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2932 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2933 switch (opc) {
2934 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2935 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2936 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2937 Inst.setOpcode(ARM::t2DSB);
2938 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2939 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2940 Inst.setOpcode(ARM::t2DMB);
2941 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2942 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2943 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2944 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2945 }
2946
2947 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2948 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2949 }
2950
2951 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2952 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2953 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2954 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2955 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2956
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2957 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2958 return MCDisassembler::Fail;
2959 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2960 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2961
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2962 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2963}
2964
2965// Decode a shifted immediate operand. These basically consist
2966// of an 8-bit value, and a 4-bit directive that specifies either
2967// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2968static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2969 uint64_t Address, const void *Decoder) {
2970 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2971 if (ctrl == 0) {
2972 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2973 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2974 switch (byte) {
2975 case 0:
2976 Inst.addOperand(MCOperand::CreateImm(imm));
2977 break;
2978 case 1:
2979 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2980 break;
2981 case 2:
2982 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2983 break;
2984 case 3:
2985 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2986 (imm << 8) | imm));
2987 break;
2988 }
2989 } else {
2990 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2991 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2992 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2993 Inst.addOperand(MCOperand::CreateImm(imm));
2994 }
2995
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2996 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2997}
2998
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2999static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3000DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3001 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3002 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3003 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3004}
3005
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3006static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3007 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3008 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3009 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3010}
3011
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3012static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3013 uint64_t Address, const void *Decoder) {
3014 switch (Val) {
3015 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3016 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3017 case 0xF: // SY
3018 case 0xE: // ST
3019 case 0xB: // ISH
3020 case 0xA: // ISHST
3021 case 0x7: // NSH
3022 case 0x6: // NSHST
3023 case 0x3: // OSH
3024 case 0x2: // OSHST
3025 break;
3026 }
3027
3028 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3029 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3030}
3031
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3032static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3033 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3034 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3035 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3036 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3037}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3038
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3039static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3040 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3041 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3042
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3043 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3044 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3045 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3046
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3047 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3048
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3049 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3050 return MCDisassembler::Fail;
3051 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3052 return MCDisassembler::Fail;
3053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3054 return MCDisassembler::Fail;
3055 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3056 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3057
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3058 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3059}
3060
3061
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3062static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3063 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3064 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3065
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3066 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3067 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3068 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3069 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3070
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3071 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3072 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3073
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3074 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3075 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3076
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3078 return MCDisassembler::Fail;
3079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3080 return MCDisassembler::Fail;
3081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3082 return MCDisassembler::Fail;
3083 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3084 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3085
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3086 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3087}
3088
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3089static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3090 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3091 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3092
3093 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3094 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3095 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3096 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3097 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3098 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3099
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3100 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3101
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3103 return MCDisassembler::Fail;
3104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3105 return MCDisassembler::Fail;
3106 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3107 return MCDisassembler::Fail;
3108 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3109 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3110
3111 return S;
3112}
3113
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3114static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3115 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3116 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3117
3118 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3119 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3120 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3121 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3122 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3123 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3124 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3125
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3126 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3127 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3128
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3130 return MCDisassembler::Fail;
3131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3132 return MCDisassembler::Fail;
3133 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3134 return MCDisassembler::Fail;
3135 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3136 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3137
3138 return S;
3139}
3140
3141
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3142static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3143 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3144 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3145
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3146 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3147 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3148 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3149 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3150 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3151 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3152
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3153 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3154
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3156 return MCDisassembler::Fail;
3157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3158 return MCDisassembler::Fail;
3159 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3160 return MCDisassembler::Fail;
3161 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3162 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3163
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3164 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3165}
3166
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3167static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3168 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3169 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3170
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3171 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3172 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3173 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3174 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3175 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3176 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3177
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3178 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3179
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3181 return MCDisassembler::Fail;
3182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3183 return MCDisassembler::Fail;
3184 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3185 return MCDisassembler::Fail;
3186 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3187 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3188
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3189 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3190}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3191
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3192static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3193 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3194 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3195
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3196 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3197 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3198 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3199 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3200 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3201
3202 unsigned align = 0;
3203 unsigned index = 0;
3204 switch (size) {
3205 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3206 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3207 case 0:
3208 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3209 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3210 index = fieldFromInstruction32(Insn, 5, 3);
3211 break;
3212 case 1:
3213 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3214 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3215 index = fieldFromInstruction32(Insn, 6, 2);
3216 if (fieldFromInstruction32(Insn, 4, 1))
3217 align = 2;
3218 break;
3219 case 2:
3220 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3221 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3222 index = fieldFromInstruction32(Insn, 7, 1);
3223 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3224 align = 4;
3225 }
3226
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3227 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3228 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3229 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3231 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3232 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3234 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3235 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3236 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3237 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3239 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3240 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3241 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3242 }
3243
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3245 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3246 Inst.addOperand(MCOperand::CreateImm(index));
3247
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3248 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3249}
3250
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3251static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3252 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3253 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3254
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3255 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3256 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3257 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3258 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3259 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3260
3261 unsigned align = 0;
3262 unsigned index = 0;
3263 switch (size) {
3264 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3265 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3266 case 0:
3267 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3268 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3269 index = fieldFromInstruction32(Insn, 5, 3);
3270 break;
3271 case 1:
3272 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3273 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3274 index = fieldFromInstruction32(Insn, 6, 2);
3275 if (fieldFromInstruction32(Insn, 4, 1))
3276 align = 2;
3277 break;
3278 case 2:
3279 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3280 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3281 index = fieldFromInstruction32(Insn, 7, 1);
3282 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3283 align = 4;
3284 }
3285
3286 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3288 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3289 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3291 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3292 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3293 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3294 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3296 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3297 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3298 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3299 }
3300
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3301 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3302 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3303 Inst.addOperand(MCOperand::CreateImm(index));
3304
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3305 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3306}
3307
3308
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3309static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3310 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3311 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3312
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3313 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3314 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3315 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3316 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3317 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3318
3319 unsigned align = 0;
3320 unsigned index = 0;
3321 unsigned inc = 1;
3322 switch (size) {
3323 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3324 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3325 case 0:
3326 index = fieldFromInstruction32(Insn, 5, 3);
3327 if (fieldFromInstruction32(Insn, 4, 1))
3328 align = 2;
3329 break;
3330 case 1:
3331 index = fieldFromInstruction32(Insn, 6, 2);
3332 if (fieldFromInstruction32(Insn, 4, 1))
3333 align = 4;
3334 if (fieldFromInstruction32(Insn, 5, 1))
3335 inc = 2;
3336 break;
3337 case 2:
3338 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3339 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3340 index = fieldFromInstruction32(Insn, 7, 1);
3341 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3342 align = 8;
3343 if (fieldFromInstruction32(Insn, 6, 1))
3344 inc = 2;
3345 break;
3346 }
3347
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3348 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3349 return MCDisassembler::Fail;
3350 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3351 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3352 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3354 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3355 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3357 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3358 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3359 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3360 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3362 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3363 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3364 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3365 }
3366
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3367 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3368 return MCDisassembler::Fail;
3369 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3370 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3371 Inst.addOperand(MCOperand::CreateImm(index));
3372
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3373 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3374}
3375
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3376static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3377 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3378 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3379
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3380 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3381 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3382 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3383 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3384 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3385
3386 unsigned align = 0;
3387 unsigned index = 0;
3388 unsigned inc = 1;
3389 switch (size) {
3390 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3391 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3392 case 0:
3393 index = fieldFromInstruction32(Insn, 5, 3);
3394 if (fieldFromInstruction32(Insn, 4, 1))
3395 align = 2;
3396 break;
3397 case 1:
3398 index = fieldFromInstruction32(Insn, 6, 2);
3399 if (fieldFromInstruction32(Insn, 4, 1))
3400 align = 4;
3401 if (fieldFromInstruction32(Insn, 5, 1))
3402 inc = 2;
3403 break;
3404 case 2:
3405 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3406 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3407 index = fieldFromInstruction32(Insn, 7, 1);
3408 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3409 align = 8;
3410 if (fieldFromInstruction32(Insn, 6, 1))
3411 inc = 2;
3412 break;
3413 }
3414
3415 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3416 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3417 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3418 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3420 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3421 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3422 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3423 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3425 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3426 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3427 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3428 }
3429
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3430 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3431 return MCDisassembler::Fail;
3432 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3433 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3434 Inst.addOperand(MCOperand::CreateImm(index));
3435
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3436 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3437}
3438
3439
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3440static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3441 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3442 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3443
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3444 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3445 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3446 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3447 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3448 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3449
3450 unsigned align = 0;
3451 unsigned index = 0;
3452 unsigned inc = 1;
3453 switch (size) {
3454 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3455 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3456 case 0:
3457 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3458 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3459 index = fieldFromInstruction32(Insn, 5, 3);
3460 break;
3461 case 1:
3462 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3463 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3464 index = fieldFromInstruction32(Insn, 6, 2);
3465 if (fieldFromInstruction32(Insn, 5, 1))
3466 inc = 2;
3467 break;
3468 case 2:
3469 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3470 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3471 index = fieldFromInstruction32(Insn, 7, 1);
3472 if (fieldFromInstruction32(Insn, 6, 1))
3473 inc = 2;
3474 break;
3475 }
3476
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3477 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3478 return MCDisassembler::Fail;
3479 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3480 return MCDisassembler::Fail;
3481 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3482 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3483
3484 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3486 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3487 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3489 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3490 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3491 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3492 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3493 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3494 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3495 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3496 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3497 }
3498
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3500 return MCDisassembler::Fail;
3501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3502 return MCDisassembler::Fail;
3503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3504 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3505 Inst.addOperand(MCOperand::CreateImm(index));
3506
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3507 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3508}
3509
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3510static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3511 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3512 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3513
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3514 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3515 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3516 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3517 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3518 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3519
3520 unsigned align = 0;
3521 unsigned index = 0;
3522 unsigned inc = 1;
3523 switch (size) {
3524 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3525 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3526 case 0:
3527 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3528 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3529 index = fieldFromInstruction32(Insn, 5, 3);
3530 break;
3531 case 1:
3532 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3533 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3534 index = fieldFromInstruction32(Insn, 6, 2);
3535 if (fieldFromInstruction32(Insn, 5, 1))
3536 inc = 2;
3537 break;
3538 case 2:
3539 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3540 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3541 index = fieldFromInstruction32(Insn, 7, 1);
3542 if (fieldFromInstruction32(Insn, 6, 1))
3543 inc = 2;
3544 break;
3545 }
3546
3547 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3549 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3550 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3552 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3553 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3554 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3555 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3557 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3558 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3559 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3560 }
3561
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3562 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3563 return MCDisassembler::Fail;
3564 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3565 return MCDisassembler::Fail;
3566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3567 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3568 Inst.addOperand(MCOperand::CreateImm(index));
3569
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3570 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3571}
3572
3573
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3574static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3575 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3576 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3577
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3578 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3579 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3580 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3581 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3582 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3583
3584 unsigned align = 0;
3585 unsigned index = 0;
3586 unsigned inc = 1;
3587 switch (size) {
3588 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3589 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3590 case 0:
3591 if (fieldFromInstruction32(Insn, 4, 1))
3592 align = 4;
3593 index = fieldFromInstruction32(Insn, 5, 3);
3594 break;
3595 case 1:
3596 if (fieldFromInstruction32(Insn, 4, 1))
3597 align = 8;
3598 index = fieldFromInstruction32(Insn, 6, 2);
3599 if (fieldFromInstruction32(Insn, 5, 1))
3600 inc = 2;
3601 break;
3602 case 2:
3603 if (fieldFromInstruction32(Insn, 4, 2))
3604 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3605 index = fieldFromInstruction32(Insn, 7, 1);
3606 if (fieldFromInstruction32(Insn, 6, 1))
3607 inc = 2;
3608 break;
3609 }
3610
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3611 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3612 return MCDisassembler::Fail;
3613 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3614 return MCDisassembler::Fail;
3615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3616 return MCDisassembler::Fail;
3617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3618 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3619
3620 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3621 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3622 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3623 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3625 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3626 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3627 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3628 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3630 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3631 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3632 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3633 }
3634
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3636 return MCDisassembler::Fail;
3637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3638 return MCDisassembler::Fail;
3639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3640 return MCDisassembler::Fail;
3641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3642 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3643 Inst.addOperand(MCOperand::CreateImm(index));
3644
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3645 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3646}
3647
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3648static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3649 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3650 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3651
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3652 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3653 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3654 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3655 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3656 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3657
3658 unsigned align = 0;
3659 unsigned index = 0;
3660 unsigned inc = 1;
3661 switch (size) {
3662 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3663 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3664 case 0:
3665 if (fieldFromInstruction32(Insn, 4, 1))
3666 align = 4;
3667 index = fieldFromInstruction32(Insn, 5, 3);
3668 break;
3669 case 1:
3670 if (fieldFromInstruction32(Insn, 4, 1))
3671 align = 8;
3672 index = fieldFromInstruction32(Insn, 6, 2);
3673 if (fieldFromInstruction32(Insn, 5, 1))
3674 inc = 2;
3675 break;
3676 case 2:
3677 if (fieldFromInstruction32(Insn, 4, 2))
3678 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3679 index = fieldFromInstruction32(Insn, 7, 1);
3680 if (fieldFromInstruction32(Insn, 6, 1))
3681 inc = 2;
3682 break;
3683 }
3684
3685 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3687 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3688 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3690 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3691 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3692 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3693 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3695 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3696 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3697 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3698 }
3699
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3701 return MCDisassembler::Fail;
3702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3703 return MCDisassembler::Fail;
3704 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3705 return MCDisassembler::Fail;
3706 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3707 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3708 Inst.addOperand(MCOperand::CreateImm(index));
3709
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3710 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3711}
3712
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3713static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3714 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3715 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3716 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3717 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3718 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3719 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3720 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3721
3722 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3723 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3724
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3725 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3726 return MCDisassembler::Fail;
3727 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3728 return MCDisassembler::Fail;
3729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3730 return MCDisassembler::Fail;
3731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3732 return MCDisassembler::Fail;
3733 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3734 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3735
3736 return S;
3737}
3738
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3739static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3740 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3741 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3742 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3743 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3744 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3745 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3746 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3747
3748 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3749 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3750
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3752 return MCDisassembler::Fail;
3753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3754 return MCDisassembler::Fail;
3755 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3756 return MCDisassembler::Fail;
3757 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3758 return MCDisassembler::Fail;
3759 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3760 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3761
3762 return S;
3763}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3764
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3765static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3766 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3767 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3768 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3769 // The InstPrinter needs to have the low bit of the predicate in
3770 // the mask operand to be able to print it properly.
3771 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3772
3773 if (pred == 0xF) {
3774 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3775 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3776 }
3777
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3778 if ((mask & 0xF) == 0) {
3779 // Preserve the high bit of the mask, which is the low bit of
3780 // the predicate.
3781 mask &= 0x10;
3782 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3783 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3784 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3785
3786 Inst.addOperand(MCOperand::CreateImm(pred));
3787 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3788 return S;
3789}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3790
3791static DecodeStatus
3792DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3793 uint64_t Address, const void *Decoder) {
3794 DecodeStatus S = MCDisassembler::Success;
3795
3796 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3797 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3798 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3799 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3800 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3801 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3802 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3803 bool writeback = (W == 1) | (P == 0);
3804
3805 addr |= (U << 8) | (Rn << 9);
3806
3807 if (writeback && (Rn == Rt || Rn == Rt2))
3808 Check(S, MCDisassembler::SoftFail);
3809 if (Rt == Rt2)
3810 Check(S, MCDisassembler::SoftFail);
3811
3812 // Rt
3813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3814 return MCDisassembler::Fail;
3815 // Rt2
3816 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3817 return MCDisassembler::Fail;
3818 // Writeback operand
3819 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3820 return MCDisassembler::Fail;
3821 // addr
3822 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3823 return MCDisassembler::Fail;
3824
3825 return S;
3826}
3827
3828static DecodeStatus
3829DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3830 uint64_t Address, const void *Decoder) {
3831 DecodeStatus S = MCDisassembler::Success;
3832
3833 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3834 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3835 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3836 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3837 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3838 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3839 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3840 bool writeback = (W == 1) | (P == 0);
3841
3842 addr |= (U << 8) | (Rn << 9);
3843
3844 if (writeback && (Rn == Rt || Rn == Rt2))
3845 Check(S, MCDisassembler::SoftFail);
3846
3847 // Writeback operand
3848 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3849 return MCDisassembler::Fail;
3850 // Rt
3851 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3852 return MCDisassembler::Fail;
3853 // Rt2
3854 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3855 return MCDisassembler::Fail;
3856 // addr
3857 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3858 return MCDisassembler::Fail;
3859
3860 return S;
3861}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]3862
3863static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3864 uint64_t Address, const void *Decoder) {
3865 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3866 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3867 if (sign1 != sign2) return MCDisassembler::Fail;
3868
3869 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3870 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3871 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3872 Val |= sign1 << 12;
3873 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3874
3875 return MCDisassembler::Success;
3876}
3877