Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / llvm / 7ec8fb8830108574b58c85c740d1857ccd2b0aba / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 66e64d3ffcb1987f76412800c2923c4a84203757 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
50 raw_ostream &vStream) const;
51
52 /// getEDInfo - See MCDisassembler.
53 EDInstInfo *getEDInfo() const;
54private:
55};
56
57/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
58class ThumbDisassembler : public MCDisassembler {
59public:
60 /// Constructor - Initializes the disassembler.
61 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]62 ThumbDisassembler(const MCSubtargetInfo &STI) :
63 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]64 }
65
66 ~ThumbDisassembler() {
67 }
68
69 /// getInstruction - See MCDisassembler.
70 DecodeStatus getInstruction(MCInst &instr,
71 uint64_t &size,
72 const MemoryObject &region,
73 uint64_t address,
74 raw_ostream &vStream) const;
75
76 /// getEDInfo - See MCDisassembler.
77 EDInstInfo *getEDInfo() const;
78private:
79 mutable std::vector<unsigned> ITBlock;
80 void AddThumbPredicate(MCInst&) const;
81 void UpdateThumbVFPPredicate(MCInst&) const;
82};
83}
84
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]85static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]86 switch (In) {
87 case MCDisassembler::Success:
88 // Out stays the same.
89 return true;
90 case MCDisassembler::SoftFail:
91 Out = In;
92 return true;
93 case MCDisassembler::Fail:
94 Out = In;
95 return false;
96 }
97 return false;
98}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]99
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]100
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]101// Forward declare these because the autogenerated code will reference them.
102// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]103static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]105static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]106 unsigned RegNo, uint64_t Address,
107 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]109 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]110static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]112static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]114static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]116static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]118static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]120static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]121 unsigned RegNo,
122 uint64_t Address,
123 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]124static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]125 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]126
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]129static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]130 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]131static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]132 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]133static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]139
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]142static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]144static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]145 unsigned Insn,
146 uint64_t Address,
147 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]148static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]149 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]153 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]154static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
156
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 unsigned Insn,
159 uint64_t Adddress,
160 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]161static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]163static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]164 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]166 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]167static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]168 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]169static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]170 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]171static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]252static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]254static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]256static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]258static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]260static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]264static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]266static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]268static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]270static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]272static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]274static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]276static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]278static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]280static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]282static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]284static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]286static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]288static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]290static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]292static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]294static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]296
297#include "ARMGenDisassemblerTables.inc"
298#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]299#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]300
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]301static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
302 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]303}
304
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]305static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
306 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]307}
308
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]309EDInstInfo *ARMDisassembler::getEDInfo() const {
310 return instInfoARM;
311}
312
313EDInstInfo *ThumbDisassembler::getEDInfo() const {
314 return instInfoARM;
315}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]316
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]317DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]318 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]319 uint64_t Address,
320 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]321 uint8_t bytes[4];
322
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]323 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
324 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
325
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]326 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]327 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
328 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]329 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]330 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331
332 // Encoded as a small-endian 32-bit word in the stream.
333 uint32_t insn = (bytes[3] << 24) |
334 (bytes[2] << 16) |
335 (bytes[1] << 8) |
336 (bytes[0] << 0);
337
338 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]339 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]340 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]341 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]342 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]343 }
344
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 // VFP and NEON instructions, similarly, are shared between ARM
346 // and Thumb modes.
347 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]348 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]349 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]350 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]351 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]352 }
353
354 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]355 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]356 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]357 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]358 // Add a fake predicate operand, because we share these instruction
359 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]360 if (!DecodePredicateOperand(MI, 0xE, Address, this))
361 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]362 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]363 }
364
365 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]366 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]367 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]368 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]369 // Add a fake predicate operand, because we share these instruction
370 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]371 if (!DecodePredicateOperand(MI, 0xE, Address, this))
372 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]373 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]374 }
375
376 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]377 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]378 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]379 Size = 4;
380 // Add a fake predicate operand, because we share these instruction
381 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]382 if (!DecodePredicateOperand(MI, 0xE, Address, this))
383 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]384 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]385 }
386
387 MI.clear();
388
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]389 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]390 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]391}
392
393namespace llvm {
394extern MCInstrDesc ARMInsts[];
395}
396
397// Thumb1 instructions don't have explicit S bits. Rather, they
398// implicitly set CPSR. Since it's not represented in the encoding, the
399// auto-generated decoder won't inject the CPSR operand. We need to fix
400// that as a post-pass.
401static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
402 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]403 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]404 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]405 for (unsigned i = 0; i < NumOps; ++i, ++I) {
406 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]407 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]408 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]409 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
410 return;
411 }
412 }
413
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]414 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415}
416
417// Most Thumb instructions don't have explicit predicates in the
418// encoding, but rather get their predicates from IT context. We need
419// to fix up the predicate operands using this context information as a
420// post-pass.
421void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
422 // A few instructions actually have predicates encoded in them. Don't
423 // try to overwrite it if we're seeing one of those.
424 switch (MI.getOpcode()) {
425 case ARM::tBcc:
426 case ARM::t2Bcc:
427 return;
428 default:
429 break;
430 }
431
432 // If we're in an IT block, base the predicate on that. Otherwise,
433 // assume a predicate of AL.
434 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]435 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]436 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]437 if (CC == 0xF)
438 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]439 ITBlock.pop_back();
440 } else
441 CC = ARMCC::AL;
442
443 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]444 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]445 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]446 for (unsigned i = 0; i < NumOps; ++i, ++I) {
447 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]448 if (OpInfo[i].isPredicate()) {
449 I = MI.insert(I, MCOperand::CreateImm(CC));
450 ++I;
451 if (CC == ARMCC::AL)
452 MI.insert(I, MCOperand::CreateReg(0));
453 else
454 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
455 return;
456 }
457 }
458
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]459 I = MI.insert(I, MCOperand::CreateImm(CC));
460 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]461 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]462 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]463 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]464 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]465}
466
467// Thumb VFP instructions are a special case. Because we share their
468// encodings between ARM and Thumb modes, and they are predicable in ARM
469// mode, the auto-generated decoder will give them an (incorrect)
470// predicate operand. We need to rewrite these operands based on the IT
471// context as a post-pass.
472void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
473 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]474 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]475 CC = ITBlock.back();
476 ITBlock.pop_back();
477 } else
478 CC = ARMCC::AL;
479
480 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
481 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]482 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
483 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]484 if (OpInfo[i].isPredicate() ) {
485 I->setImm(CC);
486 ++I;
487 if (CC == ARMCC::AL)
488 I->setReg(0);
489 else
490 I->setReg(ARM::CPSR);
491 return;
492 }
493 }
494}
495
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]496DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]497 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]498 uint64_t Address,
499 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]500 uint8_t bytes[4];
501
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]502 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
503 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
504
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]505 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]506 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
507 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]508 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]509 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]510
511 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]512 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]513 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]514 Size = 2;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]515 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]516 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]517 }
518
519 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]520 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]521 if (result) {
522 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]523 bool InITBlock = !ITBlock.empty();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]524 AddThumbPredicate(MI);
525 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]526 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]527 }
528
529 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]530 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]531 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]532 Size = 2;
533 AddThumbPredicate(MI);
534
535 // If we find an IT instruction, we need to parse its condition
536 // code and mask operands so that we can apply them correctly
537 // to the subsequent instructions.
538 if (MI.getOpcode() == ARM::t2IT) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]539 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]540 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]541 unsigned Mask = MI.getOperand(1).getImm();
542 unsigned CondBit0 = Mask >> 4 & 1;
543 unsigned NumTZ = CountTrailingZeros_32(Mask);
544 assert(NumTZ <= 3 && "Invalid IT mask!");
545 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
546 bool T = ((Mask >> Pos) & 1) == CondBit0;
547 if (T)
548 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]549 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]550 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]551 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]552
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]553 ITBlock.push_back(firstcond);
554 }
555
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]556 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]557 }
558
559 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]560 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
561 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]562 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]563 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]564
565 uint32_t insn32 = (bytes[3] << 8) |
566 (bytes[2] << 0) |
567 (bytes[1] << 24) |
568 (bytes[0] << 16);
569 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]570 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]571 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]572 Size = 4;
573 bool InITBlock = ITBlock.size();
574 AddThumbPredicate(MI);
575 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]576 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]577 }
578
579 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]580 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]581 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]582 Size = 4;
583 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]584 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]585 }
586
587 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]588 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]589 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]590 Size = 4;
591 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]592 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]593 }
594
595 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]596 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]597 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]598 Size = 4;
599 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]600 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]601 }
602
603 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
604 MI.clear();
605 uint32_t NEONLdStInsn = insn32;
606 NEONLdStInsn &= 0xF0FFFFFF;
607 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]608 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]609 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]610 Size = 4;
611 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]612 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]613 }
614 }
615
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]616 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]617 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]618 uint32_t NEONDataInsn = insn32;
619 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
620 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
621 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]622 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]623 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]624 Size = 4;
625 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]626 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]627 }
628 }
629
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]630 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]631 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]632}
633
634
635extern "C" void LLVMInitializeARMDisassembler() {
636 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
637 createARMDisassembler);
638 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
639 createThumbDisassembler);
640}
641
642static const unsigned GPRDecoderTable[] = {
643 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
644 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
645 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
646 ARM::R12, ARM::SP, ARM::LR, ARM::PC
647};
648
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]649static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]650 uint64_t Address, const void *Decoder) {
651 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]652 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]653
654 unsigned Register = GPRDecoderTable[RegNo];
655 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]656 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]657}
658
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]659static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]660DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
661 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]662 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]663 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
664}
665
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]666static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]667 uint64_t Address, const void *Decoder) {
668 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]669 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]670 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
671}
672
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]673static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]674 uint64_t Address, const void *Decoder) {
675 unsigned Register = 0;
676 switch (RegNo) {
677 case 0:
678 Register = ARM::R0;
679 break;
680 case 1:
681 Register = ARM::R1;
682 break;
683 case 2:
684 Register = ARM::R2;
685 break;
686 case 3:
687 Register = ARM::R3;
688 break;
689 case 9:
690 Register = ARM::R9;
691 break;
692 case 12:
693 Register = ARM::R12;
694 break;
695 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]696 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]697 }
698
699 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]700 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]701}
702
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]703static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]704 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]705 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]706 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
707}
708
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]709static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]710 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
711 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
712 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
713 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
714 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
715 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
716 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
717 ARM::S28, ARM::S29, ARM::S30, ARM::S31
718};
719
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]720static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]721 uint64_t Address, const void *Decoder) {
722 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]723 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]724
725 unsigned Register = SPRDecoderTable[RegNo];
726 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]727 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]728}
729
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]730static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]731 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
732 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
733 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
734 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
735 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
736 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
737 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
738 ARM::D28, ARM::D29, ARM::D30, ARM::D31
739};
740
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]741static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]742 uint64_t Address, const void *Decoder) {
743 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]744 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]745
746 unsigned Register = DPRDecoderTable[RegNo];
747 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]748 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]749}
750
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]751static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]752 uint64_t Address, const void *Decoder) {
753 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]754 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]755 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
756}
757
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]758static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]759DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
760 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]761 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]762 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]763 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
764}
765
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]766static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]767 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
768 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
769 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
770 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
771};
772
773
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]774static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]775 uint64_t Address, const void *Decoder) {
776 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]777 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]778 RegNo >>= 1;
779
780 unsigned Register = QPRDecoderTable[RegNo];
781 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]782 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]783}
784
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]785static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]787 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]788 // AL predicate is not allowed on Thumb1 branches.
789 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]790 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 Inst.addOperand(MCOperand::CreateImm(Val));
792 if (Val == ARMCC::AL) {
793 Inst.addOperand(MCOperand::CreateReg(0));
794 } else
795 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]796 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]797}
798
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]799static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]800 uint64_t Address, const void *Decoder) {
801 if (Val)
802 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
803 else
804 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]805 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]806}
807
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]808static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]809 uint64_t Address, const void *Decoder) {
810 uint32_t imm = Val & 0xFF;
811 uint32_t rot = (Val & 0xF00) >> 7;
812 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
813 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]814 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]815}
816
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]817static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]818 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]819 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]820
821 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
822 unsigned type = fieldFromInstruction32(Val, 5, 2);
823 unsigned imm = fieldFromInstruction32(Val, 7, 5);
824
825 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
827 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]828
829 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
830 switch (type) {
831 case 0:
832 Shift = ARM_AM::lsl;
833 break;
834 case 1:
835 Shift = ARM_AM::lsr;
836 break;
837 case 2:
838 Shift = ARM_AM::asr;
839 break;
840 case 3:
841 Shift = ARM_AM::ror;
842 break;
843 }
844
845 if (Shift == ARM_AM::ror && imm == 0)
846 Shift = ARM_AM::rrx;
847
848 unsigned Op = Shift | (imm << 3);
849 Inst.addOperand(MCOperand::CreateImm(Op));
850
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]851 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]852}
853
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]854static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]855 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]856 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]857
858 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
859 unsigned type = fieldFromInstruction32(Val, 5, 2);
860 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
861
862 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]863 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
864 return MCDisassembler::Fail;
865 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
866 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]867
868 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
869 switch (type) {
870 case 0:
871 Shift = ARM_AM::lsl;
872 break;
873 case 1:
874 Shift = ARM_AM::lsr;
875 break;
876 case 2:
877 Shift = ARM_AM::asr;
878 break;
879 case 3:
880 Shift = ARM_AM::ror;
881 break;
882 }
883
884 Inst.addOperand(MCOperand::CreateImm(Shift));
885
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]886 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]887}
888
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]889static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]890 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]891 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]892
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]893 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]894 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]895 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]896 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]897 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
898 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]899 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]900 }
901
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]902 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]903}
904
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]905static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]906 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]907 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]908
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]909 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
910 unsigned regs = Val & 0xFF;
911
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]912 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
913 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]914 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]915 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
916 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]917 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]918
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]919 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]920}
921
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]922static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]923 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]924 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]925
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]926 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
927 unsigned regs = (Val & 0xFF) / 2;
928
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]929 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
930 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]931 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]932 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
933 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]934 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]935
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]936 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]937}
938
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]939static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]940 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]941 // This operand encodes a mask of contiguous zeros between a specified MSB
942 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
943 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]944 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]945 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946 unsigned msb = fieldFromInstruction32(Val, 5, 5);
947 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
948 uint32_t msb_mask = (1 << (msb+1)) - 1;
949 uint32_t lsb_mask = (1 << lsb) - 1;
950 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]951 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]952}
953
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]954static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]955 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]956 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]957
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
959 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
960 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
961 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
962 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
963 unsigned U = fieldFromInstruction32(Insn, 23, 1);
964
965 switch (Inst.getOpcode()) {
966 case ARM::LDC_OFFSET:
967 case ARM::LDC_PRE:
968 case ARM::LDC_POST:
969 case ARM::LDC_OPTION:
970 case ARM::LDCL_OFFSET:
971 case ARM::LDCL_PRE:
972 case ARM::LDCL_POST:
973 case ARM::LDCL_OPTION:
974 case ARM::STC_OFFSET:
975 case ARM::STC_PRE:
976 case ARM::STC_POST:
977 case ARM::STC_OPTION:
978 case ARM::STCL_OFFSET:
979 case ARM::STCL_PRE:
980 case ARM::STCL_POST:
981 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]982 case ARM::t2LDC_OFFSET:
983 case ARM::t2LDC_PRE:
984 case ARM::t2LDC_POST:
985 case ARM::t2LDC_OPTION:
986 case ARM::t2LDCL_OFFSET:
987 case ARM::t2LDCL_PRE:
988 case ARM::t2LDCL_POST:
989 case ARM::t2LDCL_OPTION:
990 case ARM::t2STC_OFFSET:
991 case ARM::t2STC_PRE:
992 case ARM::t2STC_POST:
993 case ARM::t2STC_OPTION:
994 case ARM::t2STCL_OFFSET:
995 case ARM::t2STCL_PRE:
996 case ARM::t2STCL_POST:
997 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]998 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]999 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1000 break;
1001 default:
1002 break;
1003 }
1004
1005 Inst.addOperand(MCOperand::CreateImm(coproc));
1006 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1008 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1009 switch (Inst.getOpcode()) {
1010 case ARM::LDC_OPTION:
1011 case ARM::LDCL_OPTION:
1012 case ARM::LDC2_OPTION:
1013 case ARM::LDC2L_OPTION:
1014 case ARM::STC_OPTION:
1015 case ARM::STCL_OPTION:
1016 case ARM::STC2_OPTION:
1017 case ARM::STC2L_OPTION:
1018 case ARM::LDCL_POST:
1019 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1020 case ARM::LDC2L_POST:
1021 case ARM::STC2L_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1022 case ARM::t2LDC_OPTION:
1023 case ARM::t2LDCL_OPTION:
1024 case ARM::t2STC_OPTION:
1025 case ARM::t2STCL_OPTION:
1026 case ARM::t2LDCL_POST:
1027 case ARM::t2STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1028 break;
1029 default:
1030 Inst.addOperand(MCOperand::CreateReg(0));
1031 break;
1032 }
1033
1034 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1035 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1036
1037 bool writeback = (P == 0) || (W == 1);
1038 unsigned idx_mode = 0;
1039 if (P && writeback)
1040 idx_mode = ARMII::IndexModePre;
1041 else if (!P && writeback)
1042 idx_mode = ARMII::IndexModePost;
1043
1044 switch (Inst.getOpcode()) {
1045 case ARM::LDCL_POST:
1046 case ARM::STCL_POST:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1047 case ARM::t2LDCL_POST:
1048 case ARM::t2STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1049 case ARM::LDC2L_POST:
1050 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1051 imm |= U << 8;
1052 case ARM::LDC_OPTION:
1053 case ARM::LDCL_OPTION:
1054 case ARM::LDC2_OPTION:
1055 case ARM::LDC2L_OPTION:
1056 case ARM::STC_OPTION:
1057 case ARM::STCL_OPTION:
1058 case ARM::STC2_OPTION:
1059 case ARM::STC2L_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1060 case ARM::t2LDC_OPTION:
1061 case ARM::t2LDCL_OPTION:
1062 case ARM::t2STC_OPTION:
1063 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1064 Inst.addOperand(MCOperand::CreateImm(imm));
1065 break;
1066 default:
1067 if (U)
1068 Inst.addOperand(MCOperand::CreateImm(
1069 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1070 else
1071 Inst.addOperand(MCOperand::CreateImm(
1072 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1073 break;
1074 }
1075
1076 switch (Inst.getOpcode()) {
1077 case ARM::LDC_OFFSET:
1078 case ARM::LDC_PRE:
1079 case ARM::LDC_POST:
1080 case ARM::LDC_OPTION:
1081 case ARM::LDCL_OFFSET:
1082 case ARM::LDCL_PRE:
1083 case ARM::LDCL_POST:
1084 case ARM::LDCL_OPTION:
1085 case ARM::STC_OFFSET:
1086 case ARM::STC_PRE:
1087 case ARM::STC_POST:
1088 case ARM::STC_OPTION:
1089 case ARM::STCL_OFFSET:
1090 case ARM::STCL_PRE:
1091 case ARM::STCL_POST:
1092 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1093 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1094 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1095 break;
1096 default:
1097 break;
1098 }
1099
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1100 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1101}
1102
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1103static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1104DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1105 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1106 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1107
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1108 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1109 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1110 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1111 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1112 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1113 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1114 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1115 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1116
1117 // On stores, the writeback operand precedes Rt.
1118 switch (Inst.getOpcode()) {
1119 case ARM::STR_POST_IMM:
1120 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1121 case ARM::STRB_POST_IMM:
1122 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1123 case ARM::STRT_POST_REG:
1124 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1125 case ARM::STRBT_POST_REG:
1126 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1128 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1129 break;
1130 default:
1131 break;
1132 }
1133
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1135 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1136
1137 // On loads, the writeback operand comes after Rt.
1138 switch (Inst.getOpcode()) {
1139 case ARM::LDR_POST_IMM:
1140 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1141 case ARM::LDRB_POST_IMM:
1142 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1143 case ARM::LDRBT_POST_REG:
1144 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1145 case ARM::LDRT_POST_REG:
1146 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1147 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1148 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1149 break;
1150 default:
1151 break;
1152 }
1153
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1155 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1156
1157 ARM_AM::AddrOpc Op = ARM_AM::add;
1158 if (!fieldFromInstruction32(Insn, 23, 1))
1159 Op = ARM_AM::sub;
1160
1161 bool writeback = (P == 0) || (W == 1);
1162 unsigned idx_mode = 0;
1163 if (P && writeback)
1164 idx_mode = ARMII::IndexModePre;
1165 else if (!P && writeback)
1166 idx_mode = ARMII::IndexModePost;
1167
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1168 if (writeback && (Rn == 15 || Rn == Rt))
1169 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1170
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1171 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1172 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1173 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1174 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1175 switch( fieldFromInstruction32(Insn, 5, 2)) {
1176 case 0:
1177 Opc = ARM_AM::lsl;
1178 break;
1179 case 1:
1180 Opc = ARM_AM::lsr;
1181 break;
1182 case 2:
1183 Opc = ARM_AM::asr;
1184 break;
1185 case 3:
1186 Opc = ARM_AM::ror;
1187 break;
1188 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1189 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1190 }
1191 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1192 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1193
1194 Inst.addOperand(MCOperand::CreateImm(imm));
1195 } else {
1196 Inst.addOperand(MCOperand::CreateReg(0));
1197 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1198 Inst.addOperand(MCOperand::CreateImm(tmp));
1199 }
1200
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1201 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1202 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1203
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1204 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1205}
1206
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1207static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1208 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1209 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1210
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1211 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1212 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1213 unsigned type = fieldFromInstruction32(Val, 5, 2);
1214 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1215 unsigned U = fieldFromInstruction32(Val, 12, 1);
1216
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1217 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1218 switch (type) {
1219 case 0:
1220 ShOp = ARM_AM::lsl;
1221 break;
1222 case 1:
1223 ShOp = ARM_AM::lsr;
1224 break;
1225 case 2:
1226 ShOp = ARM_AM::asr;
1227 break;
1228 case 3:
1229 ShOp = ARM_AM::ror;
1230 break;
1231 }
1232
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1234 return MCDisassembler::Fail;
1235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1236 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1237 unsigned shift;
1238 if (U)
1239 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1240 else
1241 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1242 Inst.addOperand(MCOperand::CreateImm(shift));
1243
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1244 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1245}
1246
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1247static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1248DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1249 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1250 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1251
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1252 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1253 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1254 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1255 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1256 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1257 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1258 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1259 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1260 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1261
1262 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1263
1264 // For {LD,ST}RD, Rt must be even, else undefined.
1265 switch (Inst.getOpcode()) {
1266 case ARM::STRD:
1267 case ARM::STRD_PRE:
1268 case ARM::STRD_POST:
1269 case ARM::LDRD:
1270 case ARM::LDRD_PRE:
1271 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1272 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1273 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1274 default:
1275 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1276 }
1277
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1278 if (writeback) { // Writeback
1279 if (P)
1280 U |= ARMII::IndexModePre << 9;
1281 else
1282 U |= ARMII::IndexModePost << 9;
1283
1284 // On stores, the writeback operand precedes Rt.
1285 switch (Inst.getOpcode()) {
1286 case ARM::STRD:
1287 case ARM::STRD_PRE:
1288 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1289 case ARM::STRH:
1290 case ARM::STRH_PRE:
1291 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1293 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1294 break;
1295 default:
1296 break;
1297 }
1298 }
1299
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1301 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1302 switch (Inst.getOpcode()) {
1303 case ARM::STRD:
1304 case ARM::STRD_PRE:
1305 case ARM::STRD_POST:
1306 case ARM::LDRD:
1307 case ARM::LDRD_PRE:
1308 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1310 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1311 break;
1312 default:
1313 break;
1314 }
1315
1316 if (writeback) {
1317 // On loads, the writeback operand comes after Rt.
1318 switch (Inst.getOpcode()) {
1319 case ARM::LDRD:
1320 case ARM::LDRD_PRE:
1321 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1322 case ARM::LDRH:
1323 case ARM::LDRH_PRE:
1324 case ARM::LDRH_POST:
1325 case ARM::LDRSH:
1326 case ARM::LDRSH_PRE:
1327 case ARM::LDRSH_POST:
1328 case ARM::LDRSB:
1329 case ARM::LDRSB_PRE:
1330 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1331 case ARM::LDRHTr:
1332 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1334 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1335 break;
1336 default:
1337 break;
1338 }
1339 }
1340
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1342 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1343
1344 if (type) {
1345 Inst.addOperand(MCOperand::CreateReg(0));
1346 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1347 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1349 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1350 Inst.addOperand(MCOperand::CreateImm(U));
1351 }
1352
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1353 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1354 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1355
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1356 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1357}
1358
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1359static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1360 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1361 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1362
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1363 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1364 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1365
1366 switch (mode) {
1367 case 0:
1368 mode = ARM_AM::da;
1369 break;
1370 case 1:
1371 mode = ARM_AM::ia;
1372 break;
1373 case 2:
1374 mode = ARM_AM::db;
1375 break;
1376 case 3:
1377 mode = ARM_AM::ib;
1378 break;
1379 }
1380
1381 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1383 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1384
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1385 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1386}
1387
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1388static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1389 unsigned Insn,
1390 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1391 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1392
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1393 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1394 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1395 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1396
1397 if (pred == 0xF) {
1398 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1399 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1400 Inst.setOpcode(ARM::RFEDA);
1401 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1402 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1403 Inst.setOpcode(ARM::RFEDA_UPD);
1404 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1405 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1406 Inst.setOpcode(ARM::RFEDB);
1407 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1408 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1409 Inst.setOpcode(ARM::RFEDB_UPD);
1410 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1411 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1412 Inst.setOpcode(ARM::RFEIA);
1413 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1414 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1415 Inst.setOpcode(ARM::RFEIA_UPD);
1416 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1417 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1418 Inst.setOpcode(ARM::RFEIB);
1419 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1420 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1421 Inst.setOpcode(ARM::RFEIB_UPD);
1422 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1423 case ARM::STMDA:
1424 Inst.setOpcode(ARM::SRSDA);
1425 break;
1426 case ARM::STMDA_UPD:
1427 Inst.setOpcode(ARM::SRSDA_UPD);
1428 break;
1429 case ARM::STMDB:
1430 Inst.setOpcode(ARM::SRSDB);
1431 break;
1432 case ARM::STMDB_UPD:
1433 Inst.setOpcode(ARM::SRSDB_UPD);
1434 break;
1435 case ARM::STMIA:
1436 Inst.setOpcode(ARM::SRSIA);
1437 break;
1438 case ARM::STMIA_UPD:
1439 Inst.setOpcode(ARM::SRSIA_UPD);
1440 break;
1441 case ARM::STMIB:
1442 Inst.setOpcode(ARM::SRSIB);
1443 break;
1444 case ARM::STMIB_UPD:
1445 Inst.setOpcode(ARM::SRSIB_UPD);
1446 break;
1447 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1448 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1449 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1450
1451 // For stores (which become SRS's, the only operand is the mode.
1452 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1453 Inst.addOperand(
1454 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1455 return S;
1456 }
1457
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1458 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1459 }
1460
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1462 return MCDisassembler::Fail;
1463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1464 return MCDisassembler::Fail; // Tied
1465 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1466 return MCDisassembler::Fail;
1467 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1468 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1469
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1470 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1471}
1472
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1473static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1474 uint64_t Address, const void *Decoder) {
1475 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1476 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1477 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1478 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1479
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1480 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1481
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1482 // imod == '01' --> UNPREDICTABLE
1483 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1484 // return failure here. The '01' imod value is unprintable, so there's
1485 // nothing useful we could do even if we returned UNPREDICTABLE.
1486
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1487 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1488
1489 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1490 Inst.setOpcode(ARM::CPS3p);
1491 Inst.addOperand(MCOperand::CreateImm(imod));
1492 Inst.addOperand(MCOperand::CreateImm(iflags));
1493 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1494 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1495 Inst.setOpcode(ARM::CPS2p);
1496 Inst.addOperand(MCOperand::CreateImm(imod));
1497 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1498 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1499 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1500 Inst.setOpcode(ARM::CPS1p);
1501 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1502 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1503 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1504 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1505 Inst.setOpcode(ARM::CPS1p);
1506 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1507 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1508 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1509
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1510 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1511}
1512
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1513static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1514 uint64_t Address, const void *Decoder) {
1515 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1516 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1517 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1518 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1519
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1520 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1521
1522 // imod == '01' --> UNPREDICTABLE
1523 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1524 // return failure here. The '01' imod value is unprintable, so there's
1525 // nothing useful we could do even if we returned UNPREDICTABLE.
1526
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1527 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1528
1529 if (imod && M) {
1530 Inst.setOpcode(ARM::t2CPS3p);
1531 Inst.addOperand(MCOperand::CreateImm(imod));
1532 Inst.addOperand(MCOperand::CreateImm(iflags));
1533 Inst.addOperand(MCOperand::CreateImm(mode));
1534 } else if (imod && !M) {
1535 Inst.setOpcode(ARM::t2CPS2p);
1536 Inst.addOperand(MCOperand::CreateImm(imod));
1537 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1538 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1539 } else if (!imod && M) {
1540 Inst.setOpcode(ARM::t2CPS1p);
1541 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1542 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1543 } else {
1544 // imod == '00' && M == '0' --> UNPREDICTABLE
1545 Inst.setOpcode(ARM::t2CPS1p);
1546 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1547 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1548 }
1549
1550 return S;
1551}
1552
1553
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1554static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1555 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1556 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1557
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1558 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1559 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1560 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1561 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1562 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1563
1564 if (pred == 0xF)
1565 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1566
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1567 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1568 return MCDisassembler::Fail;
1569 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1570 return MCDisassembler::Fail;
1571 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1572 return MCDisassembler::Fail;
1573 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1574 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1575
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1576 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1577 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1578
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1579 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1580}
1581
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1582static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1583 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1584 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1585
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1586 unsigned add = fieldFromInstruction32(Val, 12, 1);
1587 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1588 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1589
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1591 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1592
1593 if (!add) imm *= -1;
1594 if (imm == 0 && !add) imm = INT32_MIN;
1595 Inst.addOperand(MCOperand::CreateImm(imm));
1596
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1597 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1598}
1599
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1600static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1601 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1602 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1603
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1604 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1605 unsigned U = fieldFromInstruction32(Val, 8, 1);
1606 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1607
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1609 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1610
1611 if (U)
1612 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1613 else
1614 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1615
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1616 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1617}
1618
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1619static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1620 uint64_t Address, const void *Decoder) {
1621 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1622}
1623
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1624static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1625DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1626 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1627 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1628
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1629 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1630 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1631
1632 if (pred == 0xF) {
1633 Inst.setOpcode(ARM::BLXi);
1634 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1635 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1636 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 }
1638
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1639 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1640 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1641 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1642
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1643 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1644}
1645
1646
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1647static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1648 uint64_t Address, const void *Decoder) {
1649 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1650 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1651}
1652
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1653static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1654 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1655 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1656
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1657 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1658 unsigned align = fieldFromInstruction32(Val, 4, 2);
1659
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1661 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1662 if (!align)
1663 Inst.addOperand(MCOperand::CreateImm(0));
1664 else
1665 Inst.addOperand(MCOperand::CreateImm(4 << align));
1666
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1667 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1668}
1669
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1670static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1671 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1672 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1673
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1674 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1675 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1676 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1677 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1678 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1679 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1680
1681 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1682 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1683 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1684
1685 // Second output register
1686 switch (Inst.getOpcode()) {
1687 case ARM::VLD1q8:
1688 case ARM::VLD1q16:
1689 case ARM::VLD1q32:
1690 case ARM::VLD1q64:
1691 case ARM::VLD1q8_UPD:
1692 case ARM::VLD1q16_UPD:
1693 case ARM::VLD1q32_UPD:
1694 case ARM::VLD1q64_UPD:
1695 case ARM::VLD1d8T:
1696 case ARM::VLD1d16T:
1697 case ARM::VLD1d32T:
1698 case ARM::VLD1d64T:
1699 case ARM::VLD1d8T_UPD:
1700 case ARM::VLD1d16T_UPD:
1701 case ARM::VLD1d32T_UPD:
1702 case ARM::VLD1d64T_UPD:
1703 case ARM::VLD1d8Q:
1704 case ARM::VLD1d16Q:
1705 case ARM::VLD1d32Q:
1706 case ARM::VLD1d64Q:
1707 case ARM::VLD1d8Q_UPD:
1708 case ARM::VLD1d16Q_UPD:
1709 case ARM::VLD1d32Q_UPD:
1710 case ARM::VLD1d64Q_UPD:
1711 case ARM::VLD2d8:
1712 case ARM::VLD2d16:
1713 case ARM::VLD2d32:
1714 case ARM::VLD2d8_UPD:
1715 case ARM::VLD2d16_UPD:
1716 case ARM::VLD2d32_UPD:
1717 case ARM::VLD2q8:
1718 case ARM::VLD2q16:
1719 case ARM::VLD2q32:
1720 case ARM::VLD2q8_UPD:
1721 case ARM::VLD2q16_UPD:
1722 case ARM::VLD2q32_UPD:
1723 case ARM::VLD3d8:
1724 case ARM::VLD3d16:
1725 case ARM::VLD3d32:
1726 case ARM::VLD3d8_UPD:
1727 case ARM::VLD3d16_UPD:
1728 case ARM::VLD3d32_UPD:
1729 case ARM::VLD4d8:
1730 case ARM::VLD4d16:
1731 case ARM::VLD4d32:
1732 case ARM::VLD4d8_UPD:
1733 case ARM::VLD4d16_UPD:
1734 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1735 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1736 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1737 break;
1738 case ARM::VLD2b8:
1739 case ARM::VLD2b16:
1740 case ARM::VLD2b32:
1741 case ARM::VLD2b8_UPD:
1742 case ARM::VLD2b16_UPD:
1743 case ARM::VLD2b32_UPD:
1744 case ARM::VLD3q8:
1745 case ARM::VLD3q16:
1746 case ARM::VLD3q32:
1747 case ARM::VLD3q8_UPD:
1748 case ARM::VLD3q16_UPD:
1749 case ARM::VLD3q32_UPD:
1750 case ARM::VLD4q8:
1751 case ARM::VLD4q16:
1752 case ARM::VLD4q32:
1753 case ARM::VLD4q8_UPD:
1754 case ARM::VLD4q16_UPD:
1755 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1756 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1757 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1758 default:
1759 break;
1760 }
1761
1762 // Third output register
1763 switch(Inst.getOpcode()) {
1764 case ARM::VLD1d8T:
1765 case ARM::VLD1d16T:
1766 case ARM::VLD1d32T:
1767 case ARM::VLD1d64T:
1768 case ARM::VLD1d8T_UPD:
1769 case ARM::VLD1d16T_UPD:
1770 case ARM::VLD1d32T_UPD:
1771 case ARM::VLD1d64T_UPD:
1772 case ARM::VLD1d8Q:
1773 case ARM::VLD1d16Q:
1774 case ARM::VLD1d32Q:
1775 case ARM::VLD1d64Q:
1776 case ARM::VLD1d8Q_UPD:
1777 case ARM::VLD1d16Q_UPD:
1778 case ARM::VLD1d32Q_UPD:
1779 case ARM::VLD1d64Q_UPD:
1780 case ARM::VLD2q8:
1781 case ARM::VLD2q16:
1782 case ARM::VLD2q32:
1783 case ARM::VLD2q8_UPD:
1784 case ARM::VLD2q16_UPD:
1785 case ARM::VLD2q32_UPD:
1786 case ARM::VLD3d8:
1787 case ARM::VLD3d16:
1788 case ARM::VLD3d32:
1789 case ARM::VLD3d8_UPD:
1790 case ARM::VLD3d16_UPD:
1791 case ARM::VLD3d32_UPD:
1792 case ARM::VLD4d8:
1793 case ARM::VLD4d16:
1794 case ARM::VLD4d32:
1795 case ARM::VLD4d8_UPD:
1796 case ARM::VLD4d16_UPD:
1797 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1798 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1799 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1800 break;
1801 case ARM::VLD3q8:
1802 case ARM::VLD3q16:
1803 case ARM::VLD3q32:
1804 case ARM::VLD3q8_UPD:
1805 case ARM::VLD3q16_UPD:
1806 case ARM::VLD3q32_UPD:
1807 case ARM::VLD4q8:
1808 case ARM::VLD4q16:
1809 case ARM::VLD4q32:
1810 case ARM::VLD4q8_UPD:
1811 case ARM::VLD4q16_UPD:
1812 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1813 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1814 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1815 break;
1816 default:
1817 break;
1818 }
1819
1820 // Fourth output register
1821 switch (Inst.getOpcode()) {
1822 case ARM::VLD1d8Q:
1823 case ARM::VLD1d16Q:
1824 case ARM::VLD1d32Q:
1825 case ARM::VLD1d64Q:
1826 case ARM::VLD1d8Q_UPD:
1827 case ARM::VLD1d16Q_UPD:
1828 case ARM::VLD1d32Q_UPD:
1829 case ARM::VLD1d64Q_UPD:
1830 case ARM::VLD2q8:
1831 case ARM::VLD2q16:
1832 case ARM::VLD2q32:
1833 case ARM::VLD2q8_UPD:
1834 case ARM::VLD2q16_UPD:
1835 case ARM::VLD2q32_UPD:
1836 case ARM::VLD4d8:
1837 case ARM::VLD4d16:
1838 case ARM::VLD4d32:
1839 case ARM::VLD4d8_UPD:
1840 case ARM::VLD4d16_UPD:
1841 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1842 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1843 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1844 break;
1845 case ARM::VLD4q8:
1846 case ARM::VLD4q16:
1847 case ARM::VLD4q32:
1848 case ARM::VLD4q8_UPD:
1849 case ARM::VLD4q16_UPD:
1850 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1851 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1852 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1853 break;
1854 default:
1855 break;
1856 }
1857
1858 // Writeback operand
1859 switch (Inst.getOpcode()) {
1860 case ARM::VLD1d8_UPD:
1861 case ARM::VLD1d16_UPD:
1862 case ARM::VLD1d32_UPD:
1863 case ARM::VLD1d64_UPD:
1864 case ARM::VLD1q8_UPD:
1865 case ARM::VLD1q16_UPD:
1866 case ARM::VLD1q32_UPD:
1867 case ARM::VLD1q64_UPD:
1868 case ARM::VLD1d8T_UPD:
1869 case ARM::VLD1d16T_UPD:
1870 case ARM::VLD1d32T_UPD:
1871 case ARM::VLD1d64T_UPD:
1872 case ARM::VLD1d8Q_UPD:
1873 case ARM::VLD1d16Q_UPD:
1874 case ARM::VLD1d32Q_UPD:
1875 case ARM::VLD1d64Q_UPD:
1876 case ARM::VLD2d8_UPD:
1877 case ARM::VLD2d16_UPD:
1878 case ARM::VLD2d32_UPD:
1879 case ARM::VLD2q8_UPD:
1880 case ARM::VLD2q16_UPD:
1881 case ARM::VLD2q32_UPD:
1882 case ARM::VLD2b8_UPD:
1883 case ARM::VLD2b16_UPD:
1884 case ARM::VLD2b32_UPD:
1885 case ARM::VLD3d8_UPD:
1886 case ARM::VLD3d16_UPD:
1887 case ARM::VLD3d32_UPD:
1888 case ARM::VLD3q8_UPD:
1889 case ARM::VLD3q16_UPD:
1890 case ARM::VLD3q32_UPD:
1891 case ARM::VLD4d8_UPD:
1892 case ARM::VLD4d16_UPD:
1893 case ARM::VLD4d32_UPD:
1894 case ARM::VLD4q8_UPD:
1895 case ARM::VLD4q16_UPD:
1896 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1897 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1898 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1899 break;
1900 default:
1901 break;
1902 }
1903
1904 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1905 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1906 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1907
1908 // AddrMode6 Offset (register)
1909 if (Rm == 0xD)
1910 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1911 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1912 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1913 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1914 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1915
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1916 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1917}
1918
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1919static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1920 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1921 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1922
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1923 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1924 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1925 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1926 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1927 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1928 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1929
1930 // Writeback Operand
1931 switch (Inst.getOpcode()) {
1932 case ARM::VST1d8_UPD:
1933 case ARM::VST1d16_UPD:
1934 case ARM::VST1d32_UPD:
1935 case ARM::VST1d64_UPD:
1936 case ARM::VST1q8_UPD:
1937 case ARM::VST1q16_UPD:
1938 case ARM::VST1q32_UPD:
1939 case ARM::VST1q64_UPD:
1940 case ARM::VST1d8T_UPD:
1941 case ARM::VST1d16T_UPD:
1942 case ARM::VST1d32T_UPD:
1943 case ARM::VST1d64T_UPD:
1944 case ARM::VST1d8Q_UPD:
1945 case ARM::VST1d16Q_UPD:
1946 case ARM::VST1d32Q_UPD:
1947 case ARM::VST1d64Q_UPD:
1948 case ARM::VST2d8_UPD:
1949 case ARM::VST2d16_UPD:
1950 case ARM::VST2d32_UPD:
1951 case ARM::VST2q8_UPD:
1952 case ARM::VST2q16_UPD:
1953 case ARM::VST2q32_UPD:
1954 case ARM::VST2b8_UPD:
1955 case ARM::VST2b16_UPD:
1956 case ARM::VST2b32_UPD:
1957 case ARM::VST3d8_UPD:
1958 case ARM::VST3d16_UPD:
1959 case ARM::VST3d32_UPD:
1960 case ARM::VST3q8_UPD:
1961 case ARM::VST3q16_UPD:
1962 case ARM::VST3q32_UPD:
1963 case ARM::VST4d8_UPD:
1964 case ARM::VST4d16_UPD:
1965 case ARM::VST4d32_UPD:
1966 case ARM::VST4q8_UPD:
1967 case ARM::VST4q16_UPD:
1968 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1969 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1970 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1971 break;
1972 default:
1973 break;
1974 }
1975
1976 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1977 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1978 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1979
1980 // AddrMode6 Offset (register)
1981 if (Rm == 0xD)
1982 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1983 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1984 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1985 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1986 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1987
1988 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1989 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1990 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1991
1992 // Second input register
1993 switch (Inst.getOpcode()) {
1994 case ARM::VST1q8:
1995 case ARM::VST1q16:
1996 case ARM::VST1q32:
1997 case ARM::VST1q64:
1998 case ARM::VST1q8_UPD:
1999 case ARM::VST1q16_UPD:
2000 case ARM::VST1q32_UPD:
2001 case ARM::VST1q64_UPD:
2002 case ARM::VST1d8T:
2003 case ARM::VST1d16T:
2004 case ARM::VST1d32T:
2005 case ARM::VST1d64T:
2006 case ARM::VST1d8T_UPD:
2007 case ARM::VST1d16T_UPD:
2008 case ARM::VST1d32T_UPD:
2009 case ARM::VST1d64T_UPD:
2010 case ARM::VST1d8Q:
2011 case ARM::VST1d16Q:
2012 case ARM::VST1d32Q:
2013 case ARM::VST1d64Q:
2014 case ARM::VST1d8Q_UPD:
2015 case ARM::VST1d16Q_UPD:
2016 case ARM::VST1d32Q_UPD:
2017 case ARM::VST1d64Q_UPD:
2018 case ARM::VST2d8:
2019 case ARM::VST2d16:
2020 case ARM::VST2d32:
2021 case ARM::VST2d8_UPD:
2022 case ARM::VST2d16_UPD:
2023 case ARM::VST2d32_UPD:
2024 case ARM::VST2q8:
2025 case ARM::VST2q16:
2026 case ARM::VST2q32:
2027 case ARM::VST2q8_UPD:
2028 case ARM::VST2q16_UPD:
2029 case ARM::VST2q32_UPD:
2030 case ARM::VST3d8:
2031 case ARM::VST3d16:
2032 case ARM::VST3d32:
2033 case ARM::VST3d8_UPD:
2034 case ARM::VST3d16_UPD:
2035 case ARM::VST3d32_UPD:
2036 case ARM::VST4d8:
2037 case ARM::VST4d16:
2038 case ARM::VST4d32:
2039 case ARM::VST4d8_UPD:
2040 case ARM::VST4d16_UPD:
2041 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2042 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2043 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2044 break;
2045 case ARM::VST2b8:
2046 case ARM::VST2b16:
2047 case ARM::VST2b32:
2048 case ARM::VST2b8_UPD:
2049 case ARM::VST2b16_UPD:
2050 case ARM::VST2b32_UPD:
2051 case ARM::VST3q8:
2052 case ARM::VST3q16:
2053 case ARM::VST3q32:
2054 case ARM::VST3q8_UPD:
2055 case ARM::VST3q16_UPD:
2056 case ARM::VST3q32_UPD:
2057 case ARM::VST4q8:
2058 case ARM::VST4q16:
2059 case ARM::VST4q32:
2060 case ARM::VST4q8_UPD:
2061 case ARM::VST4q16_UPD:
2062 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2063 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2064 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2065 break;
2066 default:
2067 break;
2068 }
2069
2070 // Third input register
2071 switch (Inst.getOpcode()) {
2072 case ARM::VST1d8T:
2073 case ARM::VST1d16T:
2074 case ARM::VST1d32T:
2075 case ARM::VST1d64T:
2076 case ARM::VST1d8T_UPD:
2077 case ARM::VST1d16T_UPD:
2078 case ARM::VST1d32T_UPD:
2079 case ARM::VST1d64T_UPD:
2080 case ARM::VST1d8Q:
2081 case ARM::VST1d16Q:
2082 case ARM::VST1d32Q:
2083 case ARM::VST1d64Q:
2084 case ARM::VST1d8Q_UPD:
2085 case ARM::VST1d16Q_UPD:
2086 case ARM::VST1d32Q_UPD:
2087 case ARM::VST1d64Q_UPD:
2088 case ARM::VST2q8:
2089 case ARM::VST2q16:
2090 case ARM::VST2q32:
2091 case ARM::VST2q8_UPD:
2092 case ARM::VST2q16_UPD:
2093 case ARM::VST2q32_UPD:
2094 case ARM::VST3d8:
2095 case ARM::VST3d16:
2096 case ARM::VST3d32:
2097 case ARM::VST3d8_UPD:
2098 case ARM::VST3d16_UPD:
2099 case ARM::VST3d32_UPD:
2100 case ARM::VST4d8:
2101 case ARM::VST4d16:
2102 case ARM::VST4d32:
2103 case ARM::VST4d8_UPD:
2104 case ARM::VST4d16_UPD:
2105 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2106 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2107 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2108 break;
2109 case ARM::VST3q8:
2110 case ARM::VST3q16:
2111 case ARM::VST3q32:
2112 case ARM::VST3q8_UPD:
2113 case ARM::VST3q16_UPD:
2114 case ARM::VST3q32_UPD:
2115 case ARM::VST4q8:
2116 case ARM::VST4q16:
2117 case ARM::VST4q32:
2118 case ARM::VST4q8_UPD:
2119 case ARM::VST4q16_UPD:
2120 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2121 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2122 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2123 break;
2124 default:
2125 break;
2126 }
2127
2128 // Fourth input register
2129 switch (Inst.getOpcode()) {
2130 case ARM::VST1d8Q:
2131 case ARM::VST1d16Q:
2132 case ARM::VST1d32Q:
2133 case ARM::VST1d64Q:
2134 case ARM::VST1d8Q_UPD:
2135 case ARM::VST1d16Q_UPD:
2136 case ARM::VST1d32Q_UPD:
2137 case ARM::VST1d64Q_UPD:
2138 case ARM::VST2q8:
2139 case ARM::VST2q16:
2140 case ARM::VST2q32:
2141 case ARM::VST2q8_UPD:
2142 case ARM::VST2q16_UPD:
2143 case ARM::VST2q32_UPD:
2144 case ARM::VST4d8:
2145 case ARM::VST4d16:
2146 case ARM::VST4d32:
2147 case ARM::VST4d8_UPD:
2148 case ARM::VST4d16_UPD:
2149 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2150 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2151 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2152 break;
2153 case ARM::VST4q8:
2154 case ARM::VST4q16:
2155 case ARM::VST4q32:
2156 case ARM::VST4q8_UPD:
2157 case ARM::VST4q16_UPD:
2158 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2159 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2160 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2161 break;
2162 default:
2163 break;
2164 }
2165
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2166 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2167}
2168
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2169static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2170 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2171 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2172
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2173 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2174 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2175 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2176 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2177 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2178 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2179 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2180
2181 align *= (1 << size);
2182
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2184 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2185 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2186 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2187 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2188 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2189 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2190 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2191 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2192 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2193
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2194 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2195 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2196 Inst.addOperand(MCOperand::CreateImm(align));
2197
2198 if (Rm == 0xD)
2199 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2200 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2202 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2203 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2204
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2205 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2206}
2207
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2208static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2209 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2210 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2211
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2212 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2213 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2214 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2215 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2216 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2217 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2218 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2219 align *= 2*size;
2220
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2222 return MCDisassembler::Fail;
2223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2224 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2225 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2227 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2228 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2231 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2232 Inst.addOperand(MCOperand::CreateImm(align));
2233
2234 if (Rm == 0xD)
2235 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2236 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2238 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2239 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2240
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2241 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2242}
2243
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2244static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2245 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2246 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2247
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2248 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2249 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2250 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2251 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2252 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2253
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2255 return MCDisassembler::Fail;
2256 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2257 return MCDisassembler::Fail;
2258 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2259 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2260 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2262 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2263 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2264
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2266 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2267 Inst.addOperand(MCOperand::CreateImm(0));
2268
2269 if (Rm == 0xD)
2270 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2271 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2273 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2274 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2275
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2276 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2277}
2278
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2279static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2280 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2281 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2282
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2283 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2284 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2285 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2286 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2287 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2288 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2289 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2290
2291 if (size == 0x3) {
2292 size = 4;
2293 align = 16;
2294 } else {
2295 if (size == 2) {
2296 size = 1 << size;
2297 align *= 8;
2298 } else {
2299 size = 1 << size;
2300 align *= 4*size;
2301 }
2302 }
2303
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2305 return MCDisassembler::Fail;
2306 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2307 return MCDisassembler::Fail;
2308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2309 return MCDisassembler::Fail;
2310 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2311 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2312 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2314 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2315 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2316
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2318 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2319 Inst.addOperand(MCOperand::CreateImm(align));
2320
2321 if (Rm == 0xD)
2322 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2323 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2325 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2326 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2327
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2328 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2329}
2330
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2331static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2332DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2333 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2334 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2335
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2336 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2337 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2338 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2339 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2340 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2341 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2342 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2343 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2344
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2345 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2346 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2347 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2348 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2349 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2350 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2351 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2352
2353 Inst.addOperand(MCOperand::CreateImm(imm));
2354
2355 switch (Inst.getOpcode()) {
2356 case ARM::VORRiv4i16:
2357 case ARM::VORRiv2i32:
2358 case ARM::VBICiv4i16:
2359 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2360 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2361 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2362 break;
2363 case ARM::VORRiv8i16:
2364 case ARM::VORRiv4i32:
2365 case ARM::VBICiv8i16:
2366 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2367 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2368 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2369 break;
2370 default:
2371 break;
2372 }
2373
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2374 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2375}
2376
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2377static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2378 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2379 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2380
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2381 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2382 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2383 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2384 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2385 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2386
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2387 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2388 return MCDisassembler::Fail;
2389 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2390 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2391 Inst.addOperand(MCOperand::CreateImm(8 << size));
2392
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2393 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2394}
2395
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2396static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2397 uint64_t Address, const void *Decoder) {
2398 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2399 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2400}
2401
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2402static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2403 uint64_t Address, const void *Decoder) {
2404 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2405 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2406}
2407
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2408static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2409 uint64_t Address, const void *Decoder) {
2410 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2411 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2412}
2413
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2414static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2415 uint64_t Address, const void *Decoder) {
2416 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2417 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2418}
2419
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2420static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2421 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2422 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2423
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2424 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2425 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2426 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2427 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2428 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2429 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2430 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2431 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2432
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2434 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2435 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2437 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2438 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2439
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2440 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2441 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2442 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2443 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2444
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2445 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2446 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2447
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2448 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2449}
2450
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2451static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2452 uint64_t Address, const void *Decoder) {
2453 // The immediate needs to be a fully instantiated float. However, the
2454 // auto-generated decoder is only able to fill in some of the bits
2455 // necessary. For instance, the 'b' bit is replicated multiple times,
2456 // and is even present in inverted form in one bit. We do a little
2457 // binary parsing here to fill in those missing bits, and then
2458 // reinterpret it all as a float.
2459 union {
2460 uint32_t integer;
2461 float fp;
2462 } fp_conv;
2463
2464 fp_conv.integer = Val;
2465 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2466 fp_conv.integer |= b << 26;
2467 fp_conv.integer |= b << 27;
2468 fp_conv.integer |= b << 28;
2469 fp_conv.integer |= b << 29;
2470 fp_conv.integer |= (~b & 0x1) << 30;
2471
2472 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2473 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2474}
2475
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2476static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2477 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2478 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2479
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2480 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2481 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2482
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2483 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2484 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2485
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2486 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2487 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2488 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2489 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2490 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2491 case ARM::tADDrSPi:
2492 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2493 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2494 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2495
2496 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2497 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2498}
2499
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2500static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2501 uint64_t Address, const void *Decoder) {
2502 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2503 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2504}
2505
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2506static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2507 uint64_t Address, const void *Decoder) {
2508 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2509 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2510}
2511
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2512static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2513 uint64_t Address, const void *Decoder) {
2514 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2515 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2516}
2517
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2518static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2519 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2520 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2521
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2522 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2523 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2524
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2525 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2526 return MCDisassembler::Fail;
2527 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2528 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2529
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2530 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2531}
2532
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2533static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2534 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2535 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2536
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2537 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2538 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2539
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2540 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2541 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2542 Inst.addOperand(MCOperand::CreateImm(imm));
2543
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2544 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2545}
2546
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2547static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2548 uint64_t Address, const void *Decoder) {
2549 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2550
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2551 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2552}
2553
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2554static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2555 uint64_t Address, const void *Decoder) {
2556 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2557 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2558
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2559 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2560}
2561
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2562static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2563 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2564 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2565
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2566 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2567 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2568 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2569
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2571 return MCDisassembler::Fail;
2572 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2573 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2574 Inst.addOperand(MCOperand::CreateImm(imm));
2575
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2576 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2577}
2578
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2579static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2580 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2581 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2582
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2583 switch (Inst.getOpcode()) {
2584 case ARM::t2PLDs:
2585 case ARM::t2PLDWs:
2586 case ARM::t2PLIs:
2587 break;
2588 default: {
2589 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2591 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2592 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2593 }
2594
2595 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2596 if (Rn == 0xF) {
2597 switch (Inst.getOpcode()) {
2598 case ARM::t2LDRBs:
2599 Inst.setOpcode(ARM::t2LDRBpci);
2600 break;
2601 case ARM::t2LDRHs:
2602 Inst.setOpcode(ARM::t2LDRHpci);
2603 break;
2604 case ARM::t2LDRSHs:
2605 Inst.setOpcode(ARM::t2LDRSHpci);
2606 break;
2607 case ARM::t2LDRSBs:
2608 Inst.setOpcode(ARM::t2LDRSBpci);
2609 break;
2610 case ARM::t2PLDs:
2611 Inst.setOpcode(ARM::t2PLDi12);
2612 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2613 break;
2614 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2615 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2616 }
2617
2618 int imm = fieldFromInstruction32(Insn, 0, 12);
2619 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2620 Inst.addOperand(MCOperand::CreateImm(imm));
2621
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2622 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2623 }
2624
2625 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2626 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2627 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2628 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2629 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2630
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2631 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2632}
2633
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2634static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2635 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2636 int imm = Val & 0xFF;
2637 if (!(Val & 0x100)) imm *= -1;
2638 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2639
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2640 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2641}
2642
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2643static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2644 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2645 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2646
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2647 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2648 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2649
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2651 return MCDisassembler::Fail;
2652 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2653 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2654
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2655 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2656}
2657
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2658static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2659 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2660 int imm = Val & 0xFF;
2661 if (!(Val & 0x100)) imm *= -1;
2662 Inst.addOperand(MCOperand::CreateImm(imm));
2663
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2664 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2665}
2666
2667
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2668static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2669 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2670 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2671
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2672 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2673 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2674
2675 // Some instructions always use an additive offset.
2676 switch (Inst.getOpcode()) {
2677 case ARM::t2LDRT:
2678 case ARM::t2LDRBT:
2679 case ARM::t2LDRHT:
2680 case ARM::t2LDRSBT:
2681 case ARM::t2LDRSHT:
2682 imm |= 0x100;
2683 break;
2684 default:
2685 break;
2686 }
2687
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2689 return MCDisassembler::Fail;
2690 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2691 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2692
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2693 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694}
2695
2696
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2697static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2698 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2699 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2700
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2701 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2702 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2703
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2705 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2706 Inst.addOperand(MCOperand::CreateImm(imm));
2707
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2708 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2709}
2710
2711
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2712static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2713 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2714 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2715
2716 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2717 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2718 Inst.addOperand(MCOperand::CreateImm(imm));
2719
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2720 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2721}
2722
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2723static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2724 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2725 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2726
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2727 if (Inst.getOpcode() == ARM::tADDrSP) {
2728 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2729 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2730
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2732 return MCDisassembler::Fail;
2733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2734 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2735 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2736 } else if (Inst.getOpcode() == ARM::tADDspr) {
2737 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2738
2739 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2740 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2742 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2743 }
2744
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2745 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2746}
2747
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2748static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2749 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2750 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2751 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2752
2753 Inst.addOperand(MCOperand::CreateImm(imod));
2754 Inst.addOperand(MCOperand::CreateImm(flags));
2755
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2756 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757}
2758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2759static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2760 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2761 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2762 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2763 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2764
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2766 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2767 Inst.addOperand(MCOperand::CreateImm(add));
2768
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2769 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2770}
2771
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2772static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2773 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2774 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2775 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2776}
2777
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2778static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2779 uint64_t Address, const void *Decoder) {
2780 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2781 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2782
2783 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2784 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2785}
2786
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2787static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2788DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2789 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2790 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2791
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2792 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2793 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2794 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2795 switch (opc) {
2796 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2797 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2798 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2799 Inst.setOpcode(ARM::t2DSB);
2800 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2801 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2802 Inst.setOpcode(ARM::t2DMB);
2803 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2804 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2805 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]2806 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2807 }
2808
2809 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2810 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2811 }
2812
2813 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2814 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2815 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2816 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2817 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2818
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2819 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2820 return MCDisassembler::Fail;
2821 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2822 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2823
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2824 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2825}
2826
2827// Decode a shifted immediate operand. These basically consist
2828// of an 8-bit value, and a 4-bit directive that specifies either
2829// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2830static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2831 uint64_t Address, const void *Decoder) {
2832 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2833 if (ctrl == 0) {
2834 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2835 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2836 switch (byte) {
2837 case 0:
2838 Inst.addOperand(MCOperand::CreateImm(imm));
2839 break;
2840 case 1:
2841 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2842 break;
2843 case 2:
2844 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2845 break;
2846 case 3:
2847 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2848 (imm << 8) | imm));
2849 break;
2850 }
2851 } else {
2852 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2853 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2854 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2855 Inst.addOperand(MCOperand::CreateImm(imm));
2856 }
2857
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2858 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2859}
2860
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2861static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2862DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2863 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2864 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2865 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2866}
2867
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2868static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2869 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2870 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2871 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2872}
2873
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2874static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2875 uint64_t Address, const void *Decoder) {
2876 switch (Val) {
2877 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2878 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2879 case 0xF: // SY
2880 case 0xE: // ST
2881 case 0xB: // ISH
2882 case 0xA: // ISHST
2883 case 0x7: // NSH
2884 case 0x6: // NSHST
2885 case 0x3: // OSH
2886 case 0x2: // OSHST
2887 break;
2888 }
2889
2890 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2891 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2892}
2893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2894static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2895 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2896 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2897 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2898 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2899}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2900
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2901static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2902 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2903 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2904
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2905 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2906 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2907 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2908
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2909 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2910
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2912 return MCDisassembler::Fail;
2913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2914 return MCDisassembler::Fail;
2915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2916 return MCDisassembler::Fail;
2917 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2918 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2919
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2920 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2921}
2922
2923
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2924static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2925 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2926 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2927
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2928 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2929 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2930 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]2931 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2932
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2933 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2934 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2935
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2936 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
2937 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2938
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2940 return MCDisassembler::Fail;
2941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2942 return MCDisassembler::Fail;
2943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2944 return MCDisassembler::Fail;
2945 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2946 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2947
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2948 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2949}
2950
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2951static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2952 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2953 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2954
2955 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2956 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2957 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2958 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2959 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2960 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2961
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2962 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2963
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2964 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2965 return MCDisassembler::Fail;
2966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2967 return MCDisassembler::Fail;
2968 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
2969 return MCDisassembler::Fail;
2970 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2971 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2972
2973 return S;
2974}
2975
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2976static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2977 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2978 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2979
2980 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2981 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2982 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2983 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2984 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2985 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2986 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2987
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2988 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
2989 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2990
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2992 return MCDisassembler::Fail;
2993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2994 return MCDisassembler::Fail;
2995 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
2996 return MCDisassembler::Fail;
2997 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2998 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2999
3000 return S;
3001}
3002
3003
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3004static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3005 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3006 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3007
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3008 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3009 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3010 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3011 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3012 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3013 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3014
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3015 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3016
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3017 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3018 return MCDisassembler::Fail;
3019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3020 return MCDisassembler::Fail;
3021 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3022 return MCDisassembler::Fail;
3023 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3024 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3025
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3026 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3027}
3028
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3029static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3030 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3031 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3032
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3033 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3034 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3035 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3036 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3037 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3038 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3039
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3040 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3041
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3043 return MCDisassembler::Fail;
3044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3045 return MCDisassembler::Fail;
3046 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3047 return MCDisassembler::Fail;
3048 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3049 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3050
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3051 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3052}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3053
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3054static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3055 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3056 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3057
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3058 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3059 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3060 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3061 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3062 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3063
3064 unsigned align = 0;
3065 unsigned index = 0;
3066 switch (size) {
3067 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3068 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3069 case 0:
3070 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3071 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3072 index = fieldFromInstruction32(Insn, 5, 3);
3073 break;
3074 case 1:
3075 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3076 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3077 index = fieldFromInstruction32(Insn, 6, 2);
3078 if (fieldFromInstruction32(Insn, 4, 1))
3079 align = 2;
3080 break;
3081 case 2:
3082 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3083 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3084 index = fieldFromInstruction32(Insn, 7, 1);
3085 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3086 align = 4;
3087 }
3088
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3089 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3090 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3091 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3093 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3094 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3096 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3097 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3098 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3099 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3101 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3102 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3103 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3104 }
3105
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3107 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3108 Inst.addOperand(MCOperand::CreateImm(index));
3109
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3110 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3111}
3112
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3113static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3114 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3115 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3116
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3117 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3118 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3119 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3120 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3121 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3122
3123 unsigned align = 0;
3124 unsigned index = 0;
3125 switch (size) {
3126 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3127 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3128 case 0:
3129 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3130 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3131 index = fieldFromInstruction32(Insn, 5, 3);
3132 break;
3133 case 1:
3134 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3135 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3136 index = fieldFromInstruction32(Insn, 6, 2);
3137 if (fieldFromInstruction32(Insn, 4, 1))
3138 align = 2;
3139 break;
3140 case 2:
3141 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3142 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3143 index = fieldFromInstruction32(Insn, 7, 1);
3144 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3145 align = 4;
3146 }
3147
3148 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3150 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3151 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3153 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3154 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3155 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3156 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3158 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3159 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3160 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3161 }
3162
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3163 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3164 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3165 Inst.addOperand(MCOperand::CreateImm(index));
3166
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3167 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3168}
3169
3170
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3171static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3172 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3173 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3174
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3175 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3176 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3177 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3178 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3179 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3180
3181 unsigned align = 0;
3182 unsigned index = 0;
3183 unsigned inc = 1;
3184 switch (size) {
3185 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3186 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3187 case 0:
3188 index = fieldFromInstruction32(Insn, 5, 3);
3189 if (fieldFromInstruction32(Insn, 4, 1))
3190 align = 2;
3191 break;
3192 case 1:
3193 index = fieldFromInstruction32(Insn, 6, 2);
3194 if (fieldFromInstruction32(Insn, 4, 1))
3195 align = 4;
3196 if (fieldFromInstruction32(Insn, 5, 1))
3197 inc = 2;
3198 break;
3199 case 2:
3200 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3201 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3202 index = fieldFromInstruction32(Insn, 7, 1);
3203 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3204 align = 8;
3205 if (fieldFromInstruction32(Insn, 6, 1))
3206 inc = 2;
3207 break;
3208 }
3209
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3211 return MCDisassembler::Fail;
3212 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3213 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3214 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3216 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3217 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3218 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3219 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3220 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3221 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3222 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3224 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3225 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3226 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3227 }
3228
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3229 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3230 return MCDisassembler::Fail;
3231 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3232 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3233 Inst.addOperand(MCOperand::CreateImm(index));
3234
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3235 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3236}
3237
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3238static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3239 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3240 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3241
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3242 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3243 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3244 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3245 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3246 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3247
3248 unsigned align = 0;
3249 unsigned index = 0;
3250 unsigned inc = 1;
3251 switch (size) {
3252 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3253 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3254 case 0:
3255 index = fieldFromInstruction32(Insn, 5, 3);
3256 if (fieldFromInstruction32(Insn, 4, 1))
3257 align = 2;
3258 break;
3259 case 1:
3260 index = fieldFromInstruction32(Insn, 6, 2);
3261 if (fieldFromInstruction32(Insn, 4, 1))
3262 align = 4;
3263 if (fieldFromInstruction32(Insn, 5, 1))
3264 inc = 2;
3265 break;
3266 case 2:
3267 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3268 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3269 index = fieldFromInstruction32(Insn, 7, 1);
3270 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3271 align = 8;
3272 if (fieldFromInstruction32(Insn, 6, 1))
3273 inc = 2;
3274 break;
3275 }
3276
3277 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3278 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3279 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3280 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3282 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3283 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3284 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3285 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3287 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3288 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3289 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3290 }
3291
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3292 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3293 return MCDisassembler::Fail;
3294 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3295 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3296 Inst.addOperand(MCOperand::CreateImm(index));
3297
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3298 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3299}
3300
3301
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3302static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3303 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3304 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3305
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3306 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3307 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3308 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3309 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3310 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3311
3312 unsigned align = 0;
3313 unsigned index = 0;
3314 unsigned inc = 1;
3315 switch (size) {
3316 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3317 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3318 case 0:
3319 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3320 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3321 index = fieldFromInstruction32(Insn, 5, 3);
3322 break;
3323 case 1:
3324 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3325 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3326 index = fieldFromInstruction32(Insn, 6, 2);
3327 if (fieldFromInstruction32(Insn, 5, 1))
3328 inc = 2;
3329 break;
3330 case 2:
3331 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3332 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3333 index = fieldFromInstruction32(Insn, 7, 1);
3334 if (fieldFromInstruction32(Insn, 6, 1))
3335 inc = 2;
3336 break;
3337 }
3338
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3339 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3340 return MCDisassembler::Fail;
3341 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3342 return MCDisassembler::Fail;
3343 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3344 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3345
3346 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3348 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3349 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3351 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3352 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3353 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3354 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3356 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3357 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3358 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3359 }
3360
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3361 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3362 return MCDisassembler::Fail;
3363 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3364 return MCDisassembler::Fail;
3365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3366 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3367 Inst.addOperand(MCOperand::CreateImm(index));
3368
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3369 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3370}
3371
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3372static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3373 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3374 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3375
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3376 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3377 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3378 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3379 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3380 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3381
3382 unsigned align = 0;
3383 unsigned index = 0;
3384 unsigned inc = 1;
3385 switch (size) {
3386 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3387 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3388 case 0:
3389 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3390 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3391 index = fieldFromInstruction32(Insn, 5, 3);
3392 break;
3393 case 1:
3394 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3395 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3396 index = fieldFromInstruction32(Insn, 6, 2);
3397 if (fieldFromInstruction32(Insn, 5, 1))
3398 inc = 2;
3399 break;
3400 case 2:
3401 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3402 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3403 index = fieldFromInstruction32(Insn, 7, 1);
3404 if (fieldFromInstruction32(Insn, 6, 1))
3405 inc = 2;
3406 break;
3407 }
3408
3409 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3411 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3412 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3414 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3415 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3416 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3417 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3419 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3420 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3421 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3422 }
3423
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3425 return MCDisassembler::Fail;
3426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3427 return MCDisassembler::Fail;
3428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3429 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3430 Inst.addOperand(MCOperand::CreateImm(index));
3431
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3432 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3433}
3434
3435
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3436static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3437 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3438 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3439
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3440 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3441 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3442 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3443 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3444 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3445
3446 unsigned align = 0;
3447 unsigned index = 0;
3448 unsigned inc = 1;
3449 switch (size) {
3450 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3451 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3452 case 0:
3453 if (fieldFromInstruction32(Insn, 4, 1))
3454 align = 4;
3455 index = fieldFromInstruction32(Insn, 5, 3);
3456 break;
3457 case 1:
3458 if (fieldFromInstruction32(Insn, 4, 1))
3459 align = 8;
3460 index = fieldFromInstruction32(Insn, 6, 2);
3461 if (fieldFromInstruction32(Insn, 5, 1))
3462 inc = 2;
3463 break;
3464 case 2:
3465 if (fieldFromInstruction32(Insn, 4, 2))
3466 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3467 index = fieldFromInstruction32(Insn, 7, 1);
3468 if (fieldFromInstruction32(Insn, 6, 1))
3469 inc = 2;
3470 break;
3471 }
3472
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3473 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3474 return MCDisassembler::Fail;
3475 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3476 return MCDisassembler::Fail;
3477 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3478 return MCDisassembler::Fail;
3479 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3480 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3481
3482 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3484 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3485 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3487 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3488 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3489 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3490 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3492 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3493 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3494 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3495 }
3496
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3497 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3498 return MCDisassembler::Fail;
3499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3500 return MCDisassembler::Fail;
3501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3502 return MCDisassembler::Fail;
3503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3504 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3505 Inst.addOperand(MCOperand::CreateImm(index));
3506
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3507 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3508}
3509
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3510static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3511 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3512 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3513
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3514 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3515 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3516 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3517 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3518 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3519
3520 unsigned align = 0;
3521 unsigned index = 0;
3522 unsigned inc = 1;
3523 switch (size) {
3524 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3525 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3526 case 0:
3527 if (fieldFromInstruction32(Insn, 4, 1))
3528 align = 4;
3529 index = fieldFromInstruction32(Insn, 5, 3);
3530 break;
3531 case 1:
3532 if (fieldFromInstruction32(Insn, 4, 1))
3533 align = 8;
3534 index = fieldFromInstruction32(Insn, 6, 2);
3535 if (fieldFromInstruction32(Insn, 5, 1))
3536 inc = 2;
3537 break;
3538 case 2:
3539 if (fieldFromInstruction32(Insn, 4, 2))
3540 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3541 index = fieldFromInstruction32(Insn, 7, 1);
3542 if (fieldFromInstruction32(Insn, 6, 1))
3543 inc = 2;
3544 break;
3545 }
3546
3547 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3549 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3550 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3552 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3553 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3554 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3555 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3557 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3558 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3559 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3560 }
3561
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3562 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3563 return MCDisassembler::Fail;
3564 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3565 return MCDisassembler::Fail;
3566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3567 return MCDisassembler::Fail;
3568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3569 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3570 Inst.addOperand(MCOperand::CreateImm(index));
3571
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3572 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3573}
3574
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3575static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3576 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3577 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3578 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3579 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3580 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3581 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3582 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3583
3584 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3585 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3586
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3587 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3588 return MCDisassembler::Fail;
3589 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3590 return MCDisassembler::Fail;
3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3592 return MCDisassembler::Fail;
3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3596 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3597
3598 return S;
3599}
3600
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3601static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3602 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3603 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3604 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3605 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3606 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3607 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3608 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3609
3610 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3611 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3612
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3614 return MCDisassembler::Fail;
3615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3616 return MCDisassembler::Fail;
3617 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3618 return MCDisassembler::Fail;
3619 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3620 return MCDisassembler::Fail;
3621 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3622 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3623
3624 return S;
3625}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3626
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3627static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3628 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3629 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3630 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3631 // The InstPrinter needs to have the low bit of the predicate in
3632 // the mask operand to be able to print it properly.
3633 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3634
3635 if (pred == 0xF) {
3636 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3637 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3638 }
3639
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3640 if ((mask & 0xF) == 0) {
3641 // Preserve the high bit of the mask, which is the low bit of
3642 // the predicate.
3643 mask &= 0x10;
3644 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3645 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3646 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3647
3648 Inst.addOperand(MCOperand::CreateImm(pred));
3649 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3650 return S;
3651}