Blame - lib/CodeGen/SelectionDAG/TargetLowering.cpp - platform/external/llvm

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Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	1	//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukman	f976c85	2005-04-21 22:55:34 +0000	[diff] [blame]	2	//
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	3	// The LLVM Compiler Infrastructure
				4	//
Chris Lattner	4ee451d	2007-12-29 20:36:04 +0000	[diff] [blame]	5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
Misha Brukman	f976c85	2005-04-21 22:55:34 +0000	[diff] [blame]	7	//
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	8	//===----------------------------------------------------------------------===//
				9	//
				10	// This implements the TargetLowering class.
				11	//
				12	//===----------------------------------------------------------------------===//
				13
				14	#include "llvm/Target/TargetLowering.h"
Chris Lattner	af76e59	2009-08-22 20:48:53 +0000	[diff] [blame]	15	#include "llvm/MC/MCAsmInfo.h"
Chris Lattner	beeb93e	2010-01-26 05:58:28 +0000	[diff] [blame]	16	#include "llvm/MC/MCExpr.h"
Owen Anderson	07000c6	2006-05-12 06:33:49 +0000	[diff] [blame]	17	#include "llvm/Target/TargetData.h"
Chris Lattner	f014412	2009-07-28 03:13:23 +0000	[diff] [blame]	18	#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	19	#include "llvm/Target/TargetMachine.h"
Dan Gohman	6f0d024	2008-02-10 18:45:23 +0000	[diff] [blame]	20	#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman	707e018	2008-04-12 04:36:06 +0000	[diff] [blame]	21	#include "llvm/GlobalVariable.h"
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	22	#include "llvm/DerivedTypes.h"
Dan Gohman	84023e0	2010-07-10 09:00:22 +0000	[diff] [blame]	23	#include "llvm/CodeGen/Analysis.h"
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	24	#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner	071c62f	2010-01-25 23:26:13 +0000	[diff] [blame]	25	#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner	589c6f6	2010-01-26 06:28:43 +0000	[diff] [blame]	26	#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	27	#include "llvm/CodeGen/SelectionDAG.h"
Jakob Stoklund Olesen	e3ee49f	2012-05-04 02:19:22 +0000	[diff] [blame]	28	#include "llvm/ADT/BitVector.h"
Owen Anderson	718cb66	2007-09-07 04:06:50 +0000	[diff] [blame]	29	#include "llvm/ADT/STLExtras.h"
Nadav Rotem	b6fbec3	2011-06-01 12:51:46 +0000	[diff] [blame]	30	#include "llvm/Support/CommandLine.h"
Torok Edwin	c25e758	2009-07-11 20:10:48 +0000	[diff] [blame]	31	#include "llvm/Support/ErrorHandling.h"
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	32	#include "llvm/Support/MathExtras.h"
Nick Lewycky	476b242	2010-12-19 20:43:38 +0000	[diff] [blame]	33	#include <cctype>
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	34	using namespace llvm;
				35
Nadav Rotem	b6fbec3	2011-06-01 12:51:46 +0000	[diff] [blame]	36	/// We are in the process of implementing a new TypeLegalization action
				37	/// - the promotion of vector elements. This feature is disabled by default
				38	/// and only enabled using this flag.
				39	static cl::opt<bool>
Nadav Rotem	8fb06b3	2011-10-16 20:31:33 +0000	[diff] [blame]	40	AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true),
Nadav Rotem	b6fbec3	2011-06-01 12:51:46 +0000	[diff] [blame]	41	cl::desc("Allow promotion of integer vector element types"));
				42
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	43	/// InitLibcallNames - Set default libcall names.
				44	///
Evan Cheng	79cca50	2007-01-12 22:51:10 +0000	[diff] [blame]	45	static void InitLibcallNames(const char **Names) {
Anton Korobeynikov	c31642f	2009-05-03 13:14:08 +0000	[diff] [blame]	46	Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	47	Names[RTLIB::SHL_I32] = "__ashlsi3";
				48	Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sands	dddc629	2008-07-11 16:52:29 +0000	[diff] [blame]	49	Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikov	c31642f	2009-05-03 13:14:08 +0000	[diff] [blame]	50	Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	51	Names[RTLIB::SRL_I32] = "__lshrsi3";
				52	Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sands	dddc629	2008-07-11 16:52:29 +0000	[diff] [blame]	53	Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikov	c31642f	2009-05-03 13:14:08 +0000	[diff] [blame]	54	Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	55	Names[RTLIB::SRA_I32] = "__ashrsi3";
				56	Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sands	dddc629	2008-07-11 16:52:29 +0000	[diff] [blame]	57	Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	58	Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikov	c31642f	2009-05-03 13:14:08 +0000	[diff] [blame]	59	Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	60	Names[RTLIB::MUL_I32] = "__mulsi3";
				61	Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	62	Names[RTLIB::MUL_I128] = "__multi3";
Eric Christopher	362fee9	2011-06-17 20:41:29 +0000	[diff] [blame]	63	Names[RTLIB::MULO_I32] = "__mulosi4";
				64	Names[RTLIB::MULO_I64] = "__mulodi4";
				65	Names[RTLIB::MULO_I128] = "__muloti4";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	66	Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov	813090c	2009-05-03 13:18:16 +0000	[diff] [blame]	67	Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	68	Names[RTLIB::SDIV_I32] = "__divsi3";
				69	Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	70	Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	71	Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikov	fb3f84f	2009-05-08 18:50:54 +0000	[diff] [blame]	72	Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	73	Names[RTLIB::UDIV_I32] = "__udivsi3";
				74	Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	75	Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	76	Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov	813090c	2009-05-03 13:18:16 +0000	[diff] [blame]	77	Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	78	Names[RTLIB::SREM_I32] = "__modsi3";
				79	Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	80	Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	81	Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov	9fe9c8e	2009-05-03 13:19:57 +0000	[diff] [blame]	82	Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	83	Names[RTLIB::UREM_I32] = "__umodsi3";
				84	Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	85	Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng	8e23e81	2011-04-01 00:42:02 +0000	[diff] [blame]	86
				87	// These are generally not available.
				88	Names[RTLIB::SDIVREM_I8] = 0;
				89	Names[RTLIB::SDIVREM_I16] = 0;
				90	Names[RTLIB::SDIVREM_I32] = 0;
				91	Names[RTLIB::SDIVREM_I64] = 0;
				92	Names[RTLIB::SDIVREM_I128] = 0;
				93	Names[RTLIB::UDIVREM_I8] = 0;
				94	Names[RTLIB::UDIVREM_I16] = 0;
				95	Names[RTLIB::UDIVREM_I32] = 0;
				96	Names[RTLIB::UDIVREM_I64] = 0;
				97	Names[RTLIB::UDIVREM_I128] = 0;
				98
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	99	Names[RTLIB::NEG_I32] = "__negsi2";
				100	Names[RTLIB::NEG_I64] = "__negdi2";
				101	Names[RTLIB::ADD_F32] = "__addsf3";
				102	Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	103	Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	104	Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	105	Names[RTLIB::SUB_F32] = "__subsf3";
				106	Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	107	Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	108	Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	109	Names[RTLIB::MUL_F32] = "__mulsf3";
				110	Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	111	Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	112	Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	113	Names[RTLIB::DIV_F32] = "__divsf3";
				114	Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	115	Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	116	Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	117	Names[RTLIB::REM_F32] = "fmodf";
				118	Names[RTLIB::REM_F64] = "fmod";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	119	Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	120	Names[RTLIB::REM_PPCF128] = "fmodl";
Cameron Zwarich	3339084	2011-07-08 21:39:21 +0000	[diff] [blame]	121	Names[RTLIB::FMA_F32] = "fmaf";
				122	Names[RTLIB::FMA_F64] = "fma";
				123	Names[RTLIB::FMA_F80] = "fmal";
				124	Names[RTLIB::FMA_PPCF128] = "fmal";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	125	Names[RTLIB::POWI_F32] = "__powisf2";
				126	Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	127	Names[RTLIB::POWI_F80] = "__powixf2";
				128	Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	129	Names[RTLIB::SQRT_F32] = "sqrtf";
				130	Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	131	Names[RTLIB::SQRT_F80] = "sqrtl";
				132	Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen	7794f2a	2008-09-04 00:47:13 +0000	[diff] [blame]	133	Names[RTLIB::LOG_F32] = "logf";
				134	Names[RTLIB::LOG_F64] = "log";
				135	Names[RTLIB::LOG_F80] = "logl";
				136	Names[RTLIB::LOG_PPCF128] = "logl";
				137	Names[RTLIB::LOG2_F32] = "log2f";
				138	Names[RTLIB::LOG2_F64] = "log2";
				139	Names[RTLIB::LOG2_F80] = "log2l";
				140	Names[RTLIB::LOG2_PPCF128] = "log2l";
				141	Names[RTLIB::LOG10_F32] = "log10f";
				142	Names[RTLIB::LOG10_F64] = "log10";
				143	Names[RTLIB::LOG10_F80] = "log10l";
				144	Names[RTLIB::LOG10_PPCF128] = "log10l";
				145	Names[RTLIB::EXP_F32] = "expf";
				146	Names[RTLIB::EXP_F64] = "exp";
				147	Names[RTLIB::EXP_F80] = "expl";
				148	Names[RTLIB::EXP_PPCF128] = "expl";
				149	Names[RTLIB::EXP2_F32] = "exp2f";
				150	Names[RTLIB::EXP2_F64] = "exp2";
				151	Names[RTLIB::EXP2_F80] = "exp2l";
				152	Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	153	Names[RTLIB::SIN_F32] = "sinf";
				154	Names[RTLIB::SIN_F64] = "sin";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	155	Names[RTLIB::SIN_F80] = "sinl";
				156	Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	157	Names[RTLIB::COS_F32] = "cosf";
				158	Names[RTLIB::COS_F64] = "cos";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	159	Names[RTLIB::COS_F80] = "cosl";
				160	Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohman	e54be10	2007-10-11 23:09:10 +0000	[diff] [blame]	161	Names[RTLIB::POW_F32] = "powf";
				162	Names[RTLIB::POW_F64] = "pow";
				163	Names[RTLIB::POW_F80] = "powl";
				164	Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman	2bb1e3e	2008-08-21 18:38:14 +0000	[diff] [blame]	165	Names[RTLIB::CEIL_F32] = "ceilf";
				166	Names[RTLIB::CEIL_F64] = "ceil";
				167	Names[RTLIB::CEIL_F80] = "ceill";
				168	Names[RTLIB::CEIL_PPCF128] = "ceill";
				169	Names[RTLIB::TRUNC_F32] = "truncf";
				170	Names[RTLIB::TRUNC_F64] = "trunc";
				171	Names[RTLIB::TRUNC_F80] = "truncl";
				172	Names[RTLIB::TRUNC_PPCF128] = "truncl";
				173	Names[RTLIB::RINT_F32] = "rintf";
				174	Names[RTLIB::RINT_F64] = "rint";
				175	Names[RTLIB::RINT_F80] = "rintl";
				176	Names[RTLIB::RINT_PPCF128] = "rintl";
				177	Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
				178	Names[RTLIB::NEARBYINT_F64] = "nearbyint";
				179	Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
				180	Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
				181	Names[RTLIB::FLOOR_F32] = "floorf";
				182	Names[RTLIB::FLOOR_F64] = "floor";
				183	Names[RTLIB::FLOOR_F80] = "floorl";
				184	Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sands	d2c817e	2010-03-14 21:08:40 +0000	[diff] [blame]	185	Names[RTLIB::COPYSIGN_F32] = "copysignf";
				186	Names[RTLIB::COPYSIGN_F64] = "copysign";
				187	Names[RTLIB::COPYSIGN_F80] = "copysignl";
				188	Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	189	Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov	927411b	2010-03-14 18:42:24 +0000	[diff] [blame]	190	Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
				191	Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	192	Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	193	Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
				194	Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
				195	Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
				196	Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	197	Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
				198	Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	199	Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
				200	Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	201	Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	202	Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
				203	Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	204	Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
				205	Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	206	Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sands	be1ad4d	2008-07-10 15:33:02 +0000	[diff] [blame]	207	Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	208	Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	209	Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands	041cde2	2008-06-25 20:24:48 +0000	[diff] [blame]	210	Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	211	Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	212	Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	213	Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
				214	Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	215	Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
				216	Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	217	Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	218	Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
				219	Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	220	Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
				221	Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	222	Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	223	Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
				224	Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	225	Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands	041cde2	2008-06-25 20:24:48 +0000	[diff] [blame]	226	Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	227	Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	228	Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	229	Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
				230	Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands	9bed0f5	2008-07-11 16:57:02 +0000	[diff] [blame]	231	Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
				232	Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	233	Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
				234	Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	235	Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
				236	Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohman	d91446d	2008-03-05 01:08:17 +0000	[diff] [blame]	237	Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
				238	Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
				239	Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
				240	Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	241	Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
				242	Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sands	ac6cece	2008-07-11 17:00:14 +0000	[diff] [blame]	243	Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
				244	Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	245	Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
				246	Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sands	ac6cece	2008-07-11 17:00:14 +0000	[diff] [blame]	247	Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
				248	Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
				249	Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
				250	Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
				251	Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
				252	Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	253	Names[RTLIB::OEQ_F32] = "__eqsf2";
				254	Names[RTLIB::OEQ_F64] = "__eqdf2";
				255	Names[RTLIB::UNE_F32] = "__nesf2";
				256	Names[RTLIB::UNE_F64] = "__nedf2";
				257	Names[RTLIB::OGE_F32] = "__gesf2";
				258	Names[RTLIB::OGE_F64] = "__gedf2";
				259	Names[RTLIB::OLT_F32] = "__ltsf2";
				260	Names[RTLIB::OLT_F64] = "__ltdf2";
				261	Names[RTLIB::OLE_F32] = "__lesf2";
				262	Names[RTLIB::OLE_F64] = "__ledf2";
				263	Names[RTLIB::OGT_F32] = "__gtsf2";
				264	Names[RTLIB::OGT_F64] = "__gtdf2";
				265	Names[RTLIB::UO_F32] = "__unordsf2";
				266	Names[RTLIB::UO_F64] = "__unorddf2";
Evan Cheng	d385fd6	2007-01-31 09:29:11 +0000	[diff] [blame]	267	Names[RTLIB::O_F32] = "__unordsf2";
				268	Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Gupta	a114baa	2009-07-30 09:12:56 +0000	[diff] [blame]	269	Names[RTLIB::MEMCPY] = "memcpy";
				270	Names[RTLIB::MEMMOVE] = "memmove";
				271	Names[RTLIB::MEMSET] = "memset";
Duncan Sands	b0f1e17	2009-05-22 20:36:31 +0000	[diff] [blame]	272	Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbach	e03262f	2010-06-18 21:43:38 +0000	[diff] [blame]	273	Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
				274	Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
				275	Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
				276	Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbach	ef6eb9c	2010-06-18 23:03:10 +0000	[diff] [blame]	277	Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
				278	Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
				279	Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
				280	Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbach	e03262f	2010-06-18 21:43:38 +0000	[diff] [blame]	281	Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
				282	Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
				283	Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
				284	Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
				285	Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
				286	Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
				287	Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
				288	Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
				289	Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
				290	Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
				291	Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
				292	Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
				293	Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
				294	Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
				295	Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
				296	Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
				297	Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
				298	Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
Jim Grosbach	312b7c9	2011-10-14 15:53:48 +0000	[diff] [blame]	299	Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
Jim Grosbach	e03262f	2010-06-18 21:43:38 +0000	[diff] [blame]	300	Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
				301	Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
				302	Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
				303	Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
				304	Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Cheng	d385fd6	2007-01-31 09:29:11 +0000	[diff] [blame]	305	}
				306
Anton Korobeynikov	72977a4	2009-08-14 20:10:52 +0000	[diff] [blame]	307	/// InitLibcallCallingConvs - Set default libcall CallingConvs.
				308	///
				309	static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
				310	for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
				311	CCs[i] = CallingConv::C;
				312	}
				313	}
				314
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	315	/// getFPEXT - Return the FPEXT__ value for the given types, or
				316	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	317	RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	318	if (OpVT == MVT::f32) {
				319	if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	320	return FPEXT_F32_F64;
				321	}
Anton Korobeynikov	927411b	2010-03-14 18:42:24 +0000	[diff] [blame]	322
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	323	return UNKNOWN_LIBCALL;
				324	}
				325
				326	/// getFPROUND - Return the FPROUND__ value for the given types, or
				327	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	328	RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	329	if (RetVT == MVT::f32) {
				330	if (OpVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	331	return FPROUND_F64_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	332	if (OpVT == MVT::f80)
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	333	return FPROUND_F80_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	334	if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	335	return FPROUND_PPCF128_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	336	} else if (RetVT == MVT::f64) {
				337	if (OpVT == MVT::f80)
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	338	return FPROUND_F80_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	339	if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	340	return FPROUND_PPCF128_F64;
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	341	}
Anton Korobeynikov	927411b	2010-03-14 18:42:24 +0000	[diff] [blame]	342
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	343	return UNKNOWN_LIBCALL;
				344	}
				345
				346	/// getFPTOSINT - Return the FPTOSINT__ value for the given types, or
				347	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	348	RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	349	if (OpVT == MVT::f32) {
				350	if (RetVT == MVT::i8)
Sanjiv Gupta	8aa207e	2009-06-16 09:03:58 +0000	[diff] [blame]	351	return FPTOSINT_F32_I8;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	352	if (RetVT == MVT::i16)
Sanjiv Gupta	8aa207e	2009-06-16 09:03:58 +0000	[diff] [blame]	353	return FPTOSINT_F32_I16;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	354	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	355	return FPTOSINT_F32_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	356	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	357	return FPTOSINT_F32_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	358	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	359	return FPTOSINT_F32_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	360	} else if (OpVT == MVT::f64) {
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	361	if (RetVT == MVT::i8)
				362	return FPTOSINT_F64_I8;
				363	if (RetVT == MVT::i16)
				364	return FPTOSINT_F64_I16;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	365	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	366	return FPTOSINT_F64_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	367	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	368	return FPTOSINT_F64_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	369	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	370	return FPTOSINT_F64_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	371	} else if (OpVT == MVT::f80) {
				372	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	373	return FPTOSINT_F80_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	374	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	375	return FPTOSINT_F80_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	376	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	377	return FPTOSINT_F80_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	378	} else if (OpVT == MVT::ppcf128) {
				379	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	380	return FPTOSINT_PPCF128_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	381	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	382	return FPTOSINT_PPCF128_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	383	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	384	return FPTOSINT_PPCF128_I128;
				385	}
				386	return UNKNOWN_LIBCALL;
				387	}
				388
				389	/// getFPTOUINT - Return the FPTOUINT__ value for the given types, or
				390	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	391	RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	392	if (OpVT == MVT::f32) {
				393	if (RetVT == MVT::i8)
Sanjiv Gupta	8aa207e	2009-06-16 09:03:58 +0000	[diff] [blame]	394	return FPTOUINT_F32_I8;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	395	if (RetVT == MVT::i16)
Sanjiv Gupta	8aa207e	2009-06-16 09:03:58 +0000	[diff] [blame]	396	return FPTOUINT_F32_I16;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	397	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	398	return FPTOUINT_F32_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	399	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	400	return FPTOUINT_F32_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	401	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	402	return FPTOUINT_F32_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	403	} else if (OpVT == MVT::f64) {
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	404	if (RetVT == MVT::i8)
				405	return FPTOUINT_F64_I8;
				406	if (RetVT == MVT::i16)
				407	return FPTOUINT_F64_I16;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	408	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	409	return FPTOUINT_F64_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	410	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	411	return FPTOUINT_F64_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	412	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	413	return FPTOUINT_F64_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	414	} else if (OpVT == MVT::f80) {
				415	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	416	return FPTOUINT_F80_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	417	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	418	return FPTOUINT_F80_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	419	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	420	return FPTOUINT_F80_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	421	} else if (OpVT == MVT::ppcf128) {
				422	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	423	return FPTOUINT_PPCF128_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	424	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	425	return FPTOUINT_PPCF128_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	426	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	427	return FPTOUINT_PPCF128_I128;
				428	}
				429	return UNKNOWN_LIBCALL;
				430	}
				431
				432	/// getSINTTOFP - Return the SINTTOFP__ value for the given types, or
				433	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	434	RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	435	if (OpVT == MVT::i32) {
				436	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	437	return SINTTOFP_I32_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	438	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	439	return SINTTOFP_I32_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	440	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	441	return SINTTOFP_I32_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	442	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	443	return SINTTOFP_I32_PPCF128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	444	} else if (OpVT == MVT::i64) {
				445	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	446	return SINTTOFP_I64_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	447	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	448	return SINTTOFP_I64_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	449	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	450	return SINTTOFP_I64_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	451	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	452	return SINTTOFP_I64_PPCF128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	453	} else if (OpVT == MVT::i128) {
				454	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	455	return SINTTOFP_I128_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	456	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	457	return SINTTOFP_I128_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	458	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	459	return SINTTOFP_I128_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	460	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	461	return SINTTOFP_I128_PPCF128;
				462	}
				463	return UNKNOWN_LIBCALL;
				464	}
				465
				466	/// getUINTTOFP - Return the UINTTOFP__ value for the given types, or
				467	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	468	RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	469	if (OpVT == MVT::i32) {
				470	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	471	return UINTTOFP_I32_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	472	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	473	return UINTTOFP_I32_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	474	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	475	return UINTTOFP_I32_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	476	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	477	return UINTTOFP_I32_PPCF128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	478	} else if (OpVT == MVT::i64) {
				479	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	480	return UINTTOFP_I64_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	481	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	482	return UINTTOFP_I64_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	483	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	484	return UINTTOFP_I64_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	485	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	486	return UINTTOFP_I64_PPCF128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	487	} else if (OpVT == MVT::i128) {
				488	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	489	return UINTTOFP_I128_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	490	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	491	return UINTTOFP_I128_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	492	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	493	return UINTTOFP_I128_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	494	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	495	return UINTTOFP_I128_PPCF128;
				496	}
				497	return UNKNOWN_LIBCALL;
				498	}
				499
Evan Cheng	d385fd6	2007-01-31 09:29:11 +0000	[diff] [blame]	500	/// InitCmpLibcallCCs - Set default comparison libcall CC.
				501	///
				502	static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
				503	memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
				504	CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
				505	CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
				506	CCs[RTLIB::UNE_F32] = ISD::SETNE;
				507	CCs[RTLIB::UNE_F64] = ISD::SETNE;
				508	CCs[RTLIB::OGE_F32] = ISD::SETGE;
				509	CCs[RTLIB::OGE_F64] = ISD::SETGE;
				510	CCs[RTLIB::OLT_F32] = ISD::SETLT;
				511	CCs[RTLIB::OLT_F64] = ISD::SETLT;
				512	CCs[RTLIB::OLE_F32] = ISD::SETLE;
				513	CCs[RTLIB::OLE_F64] = ISD::SETLE;
				514	CCs[RTLIB::OGT_F32] = ISD::SETGT;
				515	CCs[RTLIB::OGT_F64] = ISD::SETGT;
				516	CCs[RTLIB::UO_F32] = ISD::SETNE;
				517	CCs[RTLIB::UO_F64] = ISD::SETNE;
				518	CCs[RTLIB::O_F32] = ISD::SETEQ;
				519	CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	520	}
				521
Chris Lattner	f014412	2009-07-28 03:13:23 +0000	[diff] [blame]	522	/// NOTE: The constructor takes ownership of TLOF.
Dan Gohman	f0757b0	2010-04-21 01:34:56 +0000	[diff] [blame]	523	TargetLowering::TargetLowering(const TargetMachine &tm,
				524	const TargetLoweringObjectFile *tlof)
Nadav Rotem	b6fbec3	2011-06-01 12:51:46 +0000	[diff] [blame]	525	: TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
				526	mayPromoteElements(AllowPromoteIntElem) {
Chris Lattner	cba82f9	2005-01-16 07:28:11 +0000	[diff] [blame]	527	// All operations default to being supported.
				528	memset(OpActions, 0, sizeof(OpActions));
Evan Cheng	0329466	2008-10-14 21:26:46 +0000	[diff] [blame]	529	memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattner	ddf8956	2008-01-17 19:59:44 +0000	[diff] [blame]	530	memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattner	c9133f9	2008-01-18 19:36:20 +0000	[diff] [blame]	531	memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng	7f04268	2008-10-15 02:05:31 +0000	[diff] [blame]	532	memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman	93f81e2	2007-07-09 20:49:44 +0000	[diff] [blame]	533
Chris Lattner	1a3048b	2007-12-22 20:47:56 +0000	[diff] [blame]	534	// Set default actions for various operations.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	535	for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner	1a3048b	2007-12-22 20:47:56 +0000	[diff] [blame]	536	// Default all indexed load / store to expand.
Evan Cheng	5ff839f	2006-11-09 18:56:43 +0000	[diff] [blame]	537	for (unsigned IM = (unsigned)ISD::PRE_INC;
				538	IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	539	setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
				540	setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng	5ff839f	2006-11-09 18:56:43 +0000	[diff] [blame]	541	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	542
Chris Lattner	1a3048b	2007-12-22 20:47:56 +0000	[diff] [blame]	543	// These operations default to expand.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	544	setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
				545	setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng	5ff839f	2006-11-09 18:56:43 +0000	[diff] [blame]	546	}
Evan Cheng	d2cde68	2008-03-10 19:38:10 +0000	[diff] [blame]	547
				548	// Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	549	setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	550
				551	// ConstantFP nodes default to expand. Targets can either change this to
Evan Cheng	eb2f969	2009-10-27 19:56:55 +0000	[diff] [blame]	552	// Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begeman	e179584	2008-02-14 08:57:00 +0000	[diff] [blame]	553	// to optimize expansions for certain constants.
Dan Gohman	e3376ec	2011-12-20 00:02:33 +0000	[diff] [blame]	554	setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	555	setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
				556	setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
				557	setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	558
Dale Johannesen	0bb4160	2008-09-22 21:57:32 +0000	[diff] [blame]	559	// These library functions default to expand.
Dan Gohman	e3376ec	2011-12-20 00:02:33 +0000	[diff] [blame]	560	setOperationAction(ISD::FLOG , MVT::f16, Expand);
				561	setOperationAction(ISD::FLOG2, MVT::f16, Expand);
				562	setOperationAction(ISD::FLOG10, MVT::f16, Expand);
				563	setOperationAction(ISD::FEXP , MVT::f16, Expand);
				564	setOperationAction(ISD::FEXP2, MVT::f16, Expand);
				565	setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
				566	setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
				567	setOperationAction(ISD::FCEIL, MVT::f16, Expand);
				568	setOperationAction(ISD::FRINT, MVT::f16, Expand);
				569	setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Owen Anderson	4a4fdf3	2011-12-08 19:32:14 +0000	[diff] [blame]	570	setOperationAction(ISD::FLOG , MVT::f32, Expand);
				571	setOperationAction(ISD::FLOG2, MVT::f32, Expand);
				572	setOperationAction(ISD::FLOG10, MVT::f32, Expand);
				573	setOperationAction(ISD::FEXP , MVT::f32, Expand);
				574	setOperationAction(ISD::FEXP2, MVT::f32, Expand);
				575	setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
				576	setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
				577	setOperationAction(ISD::FCEIL, MVT::f32, Expand);
				578	setOperationAction(ISD::FRINT, MVT::f32, Expand);
				579	setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Dan Gohman	e3376ec	2011-12-20 00:02:33 +0000	[diff] [blame]	580	setOperationAction(ISD::FLOG , MVT::f64, Expand);
				581	setOperationAction(ISD::FLOG2, MVT::f64, Expand);
				582	setOperationAction(ISD::FLOG10, MVT::f64, Expand);
				583	setOperationAction(ISD::FEXP , MVT::f64, Expand);
				584	setOperationAction(ISD::FEXP2, MVT::f64, Expand);
				585	setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
				586	setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
				587	setOperationAction(ISD::FCEIL, MVT::f64, Expand);
				588	setOperationAction(ISD::FRINT, MVT::f64, Expand);
				589	setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Dale Johannesen	0bb4160	2008-09-22 21:57:32 +0000	[diff] [blame]	590
Chris Lattner	41bab0b	2008-01-15 21:58:08 +0000	[diff] [blame]	591	// Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	592	setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	593
Owen Anderson	a69571c	2006-05-03 01:29:57 +0000	[diff] [blame]	594	IsLittleEndian = TD->isLittleEndian();
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	595	PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	596	memset(RegClassForVT, 0,MVT::LAST_VALUETYPEsizeof(TargetRegisterClass));
Owen Anderson	718cb66	2007-09-07 04:06:50 +0000	[diff] [blame]	597	memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Cheng	a03a5dc	2006-02-14 08:38:30 +0000	[diff] [blame]	598	maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng	0521928	2011-01-06 06:52:41 +0000	[diff] [blame]	599	maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
				600	= maxStoresPerMemmoveOptSize = 4;
Evan Cheng	6ebf7bc	2009-05-13 21:42:09 +0000	[diff] [blame]	601	benefitFromCodePlacementOpt = false;
Anton Korobeynikov	d27a258	2006-12-10 23:12:42 +0000	[diff] [blame]	602	UseUnderscoreSetJmp = false;
				603	UseUnderscoreLongJmp = false;
Chris Lattner	6618039	2007-02-25 01:28:05 +0000	[diff] [blame]	604	SelectIsExpensive = false;
Nate Begeman	405e3ec	2005-10-21 00:02:42 +0000	[diff] [blame]	605	IntDivIsCheap = false;
				606	Pow2DivIsCheap = false;
Chris Lattner	de189be	2010-11-30 18:12:52 +0000	[diff] [blame]	607	JumpIsExpensive = false;
Benjamin Kramer	aaf723d	2012-05-05 12:49:14 +0000	[diff] [blame^]	608	predictableSelectIsExpensive = false;
Chris Lattner	ee4a765	2006-01-25 18:57:15 +0000	[diff] [blame]	609	StackPointerRegisterToSaveRestore = 0;
Jim Laskey	9bb3c93	2007-02-22 18:04:49 +0000	[diff] [blame]	610	ExceptionPointerRegister = 0;
				611	ExceptionSelectorRegister = 0;
Duncan Sands	0322808	2008-11-23 15:47:28 +0000	[diff] [blame]	612	BooleanContents = UndefinedBooleanContent;
Duncan Sands	28b77e9	2011-09-06 19:07:46 +0000	[diff] [blame]	613	BooleanVectorContents = UndefinedBooleanContent;
Dan Gohman	8c2d270	2011-10-24 17:45:02 +0000	[diff] [blame]	614	SchedPreferenceInfo = Sched::ILP;
Chris Lattner	7acf5f3	2006-09-05 17:39:15 +0000	[diff] [blame]	615	JumpBufSize = 0;
Duraid Madina	0c9e0ff	2006-09-04 07:44:11 +0000	[diff] [blame]	616	JumpBufAlignment = 0;
Eli Friedman	fc5d305	2011-05-06 20:34:06 +0000	[diff] [blame]	617	MinFunctionAlignment = 0;
				618	PrefFunctionAlignment = 0;
Evan Cheng	fb8075d	2008-02-28 00:43:03 +0000	[diff] [blame]	619	PrefLoopAlignment = 0;
Rafael Espindola	cbeeae2	2010-07-11 04:01:49 +0000	[diff] [blame]	620	MinStackArgumentAlignment = 1;
Jim Grosbach	9a52649	2010-06-23 16:07:42 +0000	[diff] [blame]	621	ShouldFoldAtomicFences = false;
Eli Friedman	26689ac	2011-08-03 21:06:02 +0000	[diff] [blame]	622	InsertFencesForAtomic = false;
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	623
				624	InitLibcallNames(LibcallRoutineNames);
Evan Cheng	d385fd6	2007-01-31 09:29:11 +0000	[diff] [blame]	625	InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov	72977a4	2009-08-14 20:10:52 +0000	[diff] [blame]	626	InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	627	}
				628
Chris Lattner	f014412	2009-07-28 03:13:23 +0000	[diff] [blame]	629	TargetLowering::~TargetLowering() {
				630	delete &TLOF;
				631	}
Chris Lattner	cba82f9	2005-01-16 07:28:11 +0000	[diff] [blame]	632
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	633	MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
				634	return MVT::getIntegerVT(8*TD->getPointerSize());
				635	}
				636
Mon P Wang	f7ea6c3	2010-02-10 23:37:45 +0000	[diff] [blame]	637	/// canOpTrap - Returns true if the operation can trap for the value type.
				638	/// VT must be a legal type.
				639	bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
				640	assert(isTypeLegal(VT));
				641	switch (Op) {
				642	default:
				643	return false;
				644	case ISD::FDIV:
				645	case ISD::FREM:
				646	case ISD::SDIV:
				647	case ISD::UDIV:
				648	case ISD::SREM:
				649	case ISD::UREM:
				650	return true;
				651	}
				652	}
				653
				654
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	655	static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner	598751e	2010-07-05 05:36:21 +0000	[diff] [blame]	656	unsigned &NumIntermediates,
				657	EVT &RegisterVT,
				658	TargetLowering *TLI) {
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	659	// Figure out the right, legal destination reg to copy into.
				660	unsigned NumElts = VT.getVectorNumElements();
				661	MVT EltTy = VT.getVectorElementType();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	662
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	663	unsigned NumVectorRegs = 1;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	664
				665	// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	666	// could break down into LHS/RHS like LegalizeDAG does.
				667	if (!isPowerOf2_32(NumElts)) {
				668	NumVectorRegs = NumElts;
				669	NumElts = 1;
				670	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	671
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	672	// Divide the input until we get to a supported size. This will always
				673	// end with a scalar if the target doesn't support vectors.
				674	while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
				675	NumElts >>= 1;
				676	NumVectorRegs <<= 1;
				677	}
				678
				679	NumIntermediates = NumVectorRegs;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	680
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	681	MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
				682	if (!TLI->isTypeLegal(NewVT))
				683	NewVT = EltTy;
				684	IntermediateVT = NewVT;
				685
Nadav Rotem	0c3e678	2011-06-12 14:56:55 +0000	[diff] [blame]	686	unsigned NewVTSize = NewVT.getSizeInBits();
				687
				688	// Convert sizes such as i33 to i64.
				689	if (!isPowerOf2_32(NewVTSize))
				690	NewVTSize = NextPowerOf2(NewVTSize);
				691
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	692	EVT DestVT = TLI->getRegisterType(NewVT);
				693	RegisterVT = DestVT;
Chris Lattner	32b4b5a	2010-07-05 05:53:14 +0000	[diff] [blame]	694	if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem	0c3e678	2011-06-12 14:56:55 +0000	[diff] [blame]	695	return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	696
Chris Lattner	32b4b5a	2010-07-05 05:53:14 +0000	[diff] [blame]	697	// Otherwise, promotion or legal types use the same number of registers as
				698	// the vector decimated to the appropriate level.
				699	return NumVectorRegs;
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	700	}
				701
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	702	/// isLegalRC - Return true if the value types that can be represented by the
				703	/// specified register class are all legal.
				704	bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
				705	for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
				706	I != E; ++I) {
				707	if (isTypeLegal(*I))
				708	return true;
				709	}
				710	return false;
				711	}
				712
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	713	/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng	4f6b467	2010-07-21 06:09:07 +0000	[diff] [blame]	714	/// of the register class for the specified type and its associated "cost".
				715	std::pair<const TargetRegisterClass*, uint8_t>
				716	TargetLowering::findRepresentativeClass(EVT VT) const {
Jakob Stoklund Olesen	e3ee49f	2012-05-04 02:19:22 +0000	[diff] [blame]	717	const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
Evan Cheng	4f6b467	2010-07-21 06:09:07 +0000	[diff] [blame]	718	const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
				719	if (!RC)
				720	return std::make_pair(RC, 0);
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	721
Jakob Stoklund Olesen	e3ee49f	2012-05-04 02:19:22 +0000	[diff] [blame]	722	// Compute the set of all super-register classes.
Jakob Stoklund Olesen	e3ee49f	2012-05-04 02:19:22 +0000	[diff] [blame]	723	BitVector SuperRegRC(TRI->getNumRegClasses());
Jakob Stoklund Olesen	7fc4d9c	2012-05-04 22:53:28 +0000	[diff] [blame]	724	for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
Jakob Stoklund Olesen	e3ee49f	2012-05-04 02:19:22 +0000	[diff] [blame]	725	SuperRegRC.setBitsInMask(RCI.getMask());
				726
Jakob Stoklund Olesen	7fc4d9c	2012-05-04 22:53:28 +0000	[diff] [blame]	727	// Find the first legal register class with the largest spill size.
				728	const TargetRegisterClass *BestRC = RC;
Jakob Stoklund Olesen	e3ee49f	2012-05-04 02:19:22 +0000	[diff] [blame]	729	for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
				730	const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
Jakob Stoklund Olesen	7fc4d9c	2012-05-04 22:53:28 +0000	[diff] [blame]	731	// We want the largest possible spill size.
				732	if (SuperRC->getSize() <= BestRC->getSize())
				733	continue;
				734	if (!isLegalRC(SuperRC))
				735	continue;
				736	BestRC = SuperRC;
Jakob Stoklund Olesen	e3ee49f	2012-05-04 02:19:22 +0000	[diff] [blame]	737	}
Jakob Stoklund Olesen	7fc4d9c	2012-05-04 22:53:28 +0000	[diff] [blame]	738	return std::make_pair(BestRC, 1);
Jakob Stoklund Olesen	e3ee49f	2012-05-04 02:19:22 +0000	[diff] [blame]	739	}
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	740
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	741	/// computeRegisterProperties - Once all of the register classes are added,
				742	/// this allows us to compute derived properties we expose.
				743	void TargetLowering::computeRegisterProperties() {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	744	assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattner	bb97d81	2005-01-16 01:10:58 +0000	[diff] [blame]	745	"Too many value types for ValueTypeActions to hold!");
				746
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	747	// Everything defaults to needing one register.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	748	for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohman	b9f1019	2007-06-21 14:42:22 +0000	[diff] [blame]	749	NumRegistersForVT[i] = 1;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	750	RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	751	}
				752	// ...except isVoid, which doesn't need any registers.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	753	NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukman	f976c85	2005-04-21 22:55:34 +0000	[diff] [blame]	754
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	755	// Find the largest integer register class.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	756	unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	757	for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	758	assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	759
				760	// Every integer value type larger than this largest register takes twice as
				761	// many registers to represent as the previous ValueType.
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	762	for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman	8a55ce4	2009-09-23 21:02:20 +0000	[diff] [blame]	763	EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
				764	if (!ExpandedVT.isInteger())
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	765	break;
Dan Gohman	b9f1019	2007-06-21 14:42:22 +0000	[diff] [blame]	766	NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	767	RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
				768	TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	769	ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
Evan Cheng	1a8f1fe	2006-12-09 02:42:38 +0000	[diff] [blame]	770	}
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	771
				772	// Inspect all of the ValueType's smaller than the largest integer
				773	// register to see which ones need promotion.
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	774	unsigned LegalIntReg = LargestIntReg;
				775	for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	776	IntReg >= (unsigned)MVT::i1; --IntReg) {
				777	EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	778	if (isTypeLegal(IVT)) {
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	779	LegalIntReg = IntReg;
				780	} else {
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	781	RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	782	(MVT::SimpleValueType)LegalIntReg;
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	783	ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	784	}
				785	}
				786
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	787	// ppcf128 type is really two f64's.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	788	if (!isTypeLegal(MVT::ppcf128)) {
				789	NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
				790	RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
				791	TransformToType[MVT::ppcf128] = MVT::f64;
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	792	ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	793	}
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	794
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	795	// Decide how to handle f64. If the target does not have native f64 support,
				796	// expand it to i64 and we will be generating soft float library calls.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	797	if (!isTypeLegal(MVT::f64)) {
				798	NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
				799	RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
				800	TransformToType[MVT::f64] = MVT::i64;
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	801	ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	802	}
				803
				804	// Decide how to handle f32. If the target does not have native support for
				805	// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	806	if (!isTypeLegal(MVT::f32)) {
				807	if (isTypeLegal(MVT::f64)) {
				808	NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
				809	RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
				810	TransformToType[MVT::f32] = MVT::f64;
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	811	ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	812	} else {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	813	NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
				814	RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
				815	TransformToType[MVT::f32] = MVT::i32;
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	816	ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	817	}
Evan Cheng	1a8f1fe	2006-12-09 02:42:38 +0000	[diff] [blame]	818	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	819
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	820	// Loop over all of the vector value types to see which need transformations.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	821	for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
				822	i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	823	MVT VT = (MVT::SimpleValueType)i;
Chris Lattner	598751e	2010-07-05 05:36:21 +0000	[diff] [blame]	824	if (isTypeLegal(VT)) continue;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	825
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	826	// Determine if there is a legal wider type. If so, we should promote to
				827	// that wider vector type.
				828	EVT EltVT = VT.getVectorElementType();
				829	unsigned NElts = VT.getVectorNumElements();
				830	if (NElts != 1) {
				831	bool IsLegalWiderType = false;
Nadav Rotem	f1c025d	2011-06-04 20:32:01 +0000	[diff] [blame]	832	// If we allow the promotion of vector elements using a flag,
				833	// then return TypePromoteInteger on vector elements.
				834	// First try to promote the elements of integer vectors. If no legal
				835	// promotion was found, fallback to the widen-vector method.
				836	if (mayPromoteElements)
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	837	for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
				838	EVT SVT = (MVT::SimpleValueType)nVT;
Nadav Rotem	f1c025d	2011-06-04 20:32:01 +0000	[diff] [blame]	839	// Promote vectors of integers to vectors with the same number
				840	// of elements, with a wider element type.
				841	if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
				842	&& SVT.getVectorNumElements() == NElts &&
				843	isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
				844	TransformToType[i] = SVT;
				845	RegisterTypeForVT[i] = SVT;
				846	NumRegistersForVT[i] = 1;
				847	ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
				848	IsLegalWiderType = true;
				849	break;
Nadav Rotem	b6fbec3	2011-06-01 12:51:46 +0000	[diff] [blame]	850	}
Nadav Rotem	f1c025d	2011-06-04 20:32:01 +0000	[diff] [blame]	851	}
Nadav Rotem	b6fbec3	2011-06-01 12:51:46 +0000	[diff] [blame]	852
Nadav Rotem	f1c025d	2011-06-04 20:32:01 +0000	[diff] [blame]	853	if (IsLegalWiderType) continue;
				854
				855	// Try to widen the vector.
				856	for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
				857	EVT SVT = (MVT::SimpleValueType)nVT;
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	858	if (SVT.getVectorElementType() == EltVT &&
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	859	SVT.getVectorNumElements() > NElts &&
Dale Johannesen	e93d99c	2010-10-20 21:32:10 +0000	[diff] [blame]	860	isTypeLegal(SVT)) {
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	861	TransformToType[i] = SVT;
				862	RegisterTypeForVT[i] = SVT;
				863	NumRegistersForVT[i] = 1;
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	864	ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	865	IsLegalWiderType = true;
				866	break;
				867	}
				868	}
				869	if (IsLegalWiderType) continue;
				870	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	871
Chris Lattner	598751e	2010-07-05 05:36:21 +0000	[diff] [blame]	872	MVT IntermediateVT;
				873	EVT RegisterVT;
				874	unsigned NumIntermediates;
				875	NumRegistersForVT[i] =
				876	getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
				877	RegisterVT, this);
				878	RegisterTypeForVT[i] = RegisterVT;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	879
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	880	EVT NVT = VT.getPow2VectorType();
				881	if (NVT == VT) {
				882	// Type is already a power of 2. The default action is to split.
				883	TransformToType[i] = MVT::Other;
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	884	unsigned NumElts = VT.getVectorNumElements();
				885	ValueTypeActions.setTypeAction(VT,
				886	NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	887	} else {
				888	TransformToType[i] = NVT;
Nadav Rotem	b6aacae	2011-05-28 17:57:14 +0000	[diff] [blame]	889	ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Dan Gohman	7f32156	2007-06-25 16:23:39 +0000	[diff] [blame]	890	}
Chris Lattner	3a593584	2006-03-16 19:50:01 +0000	[diff] [blame]	891	}
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	892
				893	// Determine the 'representative' register class for each value type.
				894	// An representative register class is the largest (meaning one which is
				895	// not a sub-register class / subreg register class) legal register class for
				896	// a group of value types. For example, on i386, i8, i16, and i32
				897	// representative would be GR32; while on x86_64 it's GR64.
Evan Cheng	d70f57b	2010-07-19 22:15:08 +0000	[diff] [blame]	898	for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng	4f6b467	2010-07-21 06:09:07 +0000	[diff] [blame]	899	const TargetRegisterClass* RRC;
				900	uint8_t Cost;
				901	tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
				902	RepRegClassForVT[i] = RRC;
				903	RepRegClassCostForVT[i] = Cost;
Evan Cheng	d70f57b	2010-07-19 22:15:08 +0000	[diff] [blame]	904	}
Chris Lattner	bb97d81	2005-01-16 01:10:58 +0000	[diff] [blame]	905	}
Chris Lattner	cba82f9	2005-01-16 07:28:11 +0000	[diff] [blame]	906
Evan Cheng	7226158	2005-12-20 06:22:03 +0000	[diff] [blame]	907	const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
				908	return NULL;
				909	}
Evan Cheng	3a03ebb	2005-12-21 23:05:39 +0000	[diff] [blame]	910
Scott Michel	5b8f82e	2008-03-10 15:42:14 +0000	[diff] [blame]	911
Duncan Sands	28b77e9	2011-09-06 19:07:46 +0000	[diff] [blame]	912	EVT TargetLowering::getSetCCResultType(EVT VT) const {
				913	assert(!VT.isVector() && "No default SetCC type for vectors!");
Owen Anderson	1d0be15	2009-08-13 21:58:54 +0000	[diff] [blame]	914	return PointerTy.SimpleTy;
Scott Michel	5b8f82e	2008-03-10 15:42:14 +0000	[diff] [blame]	915	}
				916
Sanjiv Gupta	8f17a36	2009-12-28 02:40:33 +0000	[diff] [blame]	917	MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
				918	return MVT::i32; // return the default value
				919	}
				920
Dan Gohman	7f32156	2007-06-25 16:23:39 +0000	[diff] [blame]	921	/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	922	/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
				923	/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
				924	/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	925	///
Dan Gohman	7f32156	2007-06-25 16:23:39 +0000	[diff] [blame]	926	/// This method returns the number of registers needed, and the VT for each
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	927	/// register. It also returns the VT and quantity of the intermediate values
				928	/// before they are promoted/expanded.
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	929	///
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	930	unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	931	EVT &IntermediateVT,
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	932	unsigned &NumIntermediates,
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	933	EVT &RegisterVT) const {
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	934	unsigned NumElts = VT.getVectorNumElements();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	935
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	936	// If there is a wider vector type with the same element type as this one,
Nadav Rotem	db34616	2012-04-21 20:08:32 +0000	[diff] [blame]	937	// or a promoted vector type that has the same number of elements which
				938	// are wider, then we should convert to that legal vector type.
				939	// This handles things like <2 x float> -> <4 x float> and
				940	// <4 x i1> -> <4 x i32>.
				941	LegalizeTypeAction TA = getTypeAction(Context, VT);
				942	if (NumElts != 1 && (TA == TypeWidenVector \|\| TA == TypePromoteInteger)) {
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	943	RegisterVT = getTypeToTransformTo(Context, VT);
				944	if (isTypeLegal(RegisterVT)) {
				945	IntermediateVT = RegisterVT;
				946	NumIntermediates = 1;
				947	return 1;
				948	}
				949	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	950
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	951	// Figure out the right, legal destination reg to copy into.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	952	EVT EltTy = VT.getVectorElementType();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	953
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	954	unsigned NumVectorRegs = 1;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	955
				956	// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begeman	d73ab88	2007-11-27 19:28:48 +0000	[diff] [blame]	957	// could break down into LHS/RHS like LegalizeDAG does.
				958	if (!isPowerOf2_32(NumElts)) {
				959	NumVectorRegs = NumElts;
				960	NumElts = 1;
				961	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	962
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	963	// Divide the input until we get to a supported size. This will always
				964	// end with a scalar if the target doesn't support vectors.
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	965	while (NumElts > 1 && !isTypeLegal(
				966	EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	967	NumElts >>= 1;
				968	NumVectorRegs <<= 1;
				969	}
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	970
				971	NumIntermediates = NumVectorRegs;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	972
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	973	EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman	7f32156	2007-06-25 16:23:39 +0000	[diff] [blame]	974	if (!isTypeLegal(NewVT))
				975	NewVT = EltTy;
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	976	IntermediateVT = NewVT;
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	977
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	978	EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	979	RegisterVT = DestVT;
Nadav Rotem	0c3e678	2011-06-12 14:56:55 +0000	[diff] [blame]	980	unsigned NewVTSize = NewVT.getSizeInBits();
				981
				982	// Convert sizes such as i33 to i64.
				983	if (!isPowerOf2_32(NewVTSize))
				984	NewVTSize = NextPowerOf2(NewVTSize);
				985
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	986	if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem	0c3e678	2011-06-12 14:56:55 +0000	[diff] [blame]	987	return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	988
Chris Lattner	e6f7c26	2010-08-25 22:49:25 +0000	[diff] [blame]	989	// Otherwise, promotion or legal types use the same number of registers as
				990	// the vector decimated to the appropriate level.
				991	return NumVectorRegs;
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	992	}
				993
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	994	/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman	84023e0	2010-07-10 09:00:22 +0000	[diff] [blame]	995	/// type of the given function. This does not require a DAG or a return value,
				996	/// and is suitable for use before any DAGs for the function are constructed.
				997	/// TODO: Move this out of TargetLowering.cpp.
Chris Lattner	db125cf	2011-07-18 04:54:35 +0000	[diff] [blame]	998	void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
Dan Gohman	84023e0	2010-07-10 09:00:22 +0000	[diff] [blame]	999	SmallVectorImpl<ISD::OutputArg> &Outs,
				1000	const TargetLowering &TLI,
				1001	SmallVectorImpl<uint64_t> *Offsets) {
				1002	SmallVector<EVT, 4> ValueVTs;
				1003	ComputeValueVTs(TLI, ReturnType, ValueVTs);
				1004	unsigned NumValues = ValueVTs.size();
				1005	if (NumValues == 0) return;
				1006	unsigned Offset = 0;
				1007
				1008	for (unsigned j = 0, f = NumValues; j != f; ++j) {
				1009	EVT VT = ValueVTs[j];
				1010	ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
				1011
				1012	if (attr & Attribute::SExt)
				1013	ExtendKind = ISD::SIGN_EXTEND;
				1014	else if (attr & Attribute::ZExt)
				1015	ExtendKind = ISD::ZERO_EXTEND;
				1016
				1017	// FIXME: C calling convention requires the return type to be promoted to
				1018	// at least 32-bit. But this is not necessary for non-C calling
				1019	// conventions. The frontend should mark functions whose return values
				1020	// require promoting with signext or zeroext attributes.
				1021	if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
				1022	EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
				1023	if (VT.bitsLT(MinVT))
				1024	VT = MinVT;
				1025	}
				1026
				1027	unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
				1028	EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
				1029	unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
				1030	PartVT.getTypeForEVT(ReturnType->getContext()));
				1031
				1032	// 'inreg' on function refers to return value
				1033	ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
				1034	if (attr & Attribute::InReg)
				1035	Flags.setInReg();
				1036
				1037	// Propagate extension type if any
				1038	if (attr & Attribute::SExt)
				1039	Flags.setSExt();
				1040	else if (attr & Attribute::ZExt)
				1041	Flags.setZExt();
				1042
				1043	for (unsigned i = 0; i < NumParts; ++i) {
				1044	Outs.push_back(ISD::OutputArg(Flags, PartVT, /isFixed=/true));
				1045	if (Offsets) {
				1046	Offsets->push_back(Offset);
				1047	Offset += PartSize;
				1048	}
				1049	}
				1050	}
				1051	}
				1052
Evan Cheng	3ae0543	2008-01-24 00:22:01 +0000	[diff] [blame]	1053	/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen	28d08fd	2008-02-28 22:31:51 +0000	[diff] [blame]	1054	/// function arguments in the caller parameter area. This is the actual
				1055	/// alignment, not its logarithm.
Chris Lattner	db125cf	2011-07-18 04:54:35 +0000	[diff] [blame]	1056	unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesen	28d08fd	2008-02-28 22:31:51 +0000	[diff] [blame]	1057	return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng	3ae0543	2008-01-24 00:22:01 +0000	[diff] [blame]	1058	}
				1059
Chris Lattner	071c62f	2010-01-25 23:26:13 +0000	[diff] [blame]	1060	/// getJumpTableEncoding - Return the entry encoding for a jump table in the
				1061	/// current function. The returned value is a member of the
				1062	/// MachineJumpTableInfo::JTEntryKind enum.
				1063	unsigned TargetLowering::getJumpTableEncoding() const {
				1064	// In non-pic modes, just use the address of a block.
				1065	if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
				1066	return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1067
Chris Lattner	071c62f	2010-01-25 23:26:13 +0000	[diff] [blame]	1068	// In PIC mode, if the target supports a GPRel32 directive, use it.
				1069	if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
				1070	return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1071
Chris Lattner	071c62f	2010-01-25 23:26:13 +0000	[diff] [blame]	1072	// Otherwise, use a label difference.
				1073	return MachineJumpTableInfo::EK_LabelDifference32;
				1074	}
				1075
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1076	SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
				1077	SelectionDAG &DAG) const {
Chris Lattner	f1214cb	2010-01-26 06:53:37 +0000	[diff] [blame]	1078	// If our PIC model is GP relative, use the global offset table as the base.
Akira Hatanaka	787c3fd	2012-04-09 20:32:12 +0000	[diff] [blame]	1079	unsigned JTEncoding = getJumpTableEncoding();
				1080
				1081	if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) \|\|
				1082	(JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
Dale Johannesen	b300d2a	2009-02-07 00:55:49 +0000	[diff] [blame]	1083	return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Akira Hatanaka	787c3fd	2012-04-09 20:32:12 +0000	[diff] [blame]	1084
Evan Cheng	cc41586	2007-11-09 01:32:10 +0000	[diff] [blame]	1085	return Table;
				1086	}
				1087
Chris Lattner	13e97a2	2010-01-26 05:30:30 +0000	[diff] [blame]	1088	/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
				1089	/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
				1090	/// MCExpr.
				1091	const MCExpr *
Chris Lattner	589c6f6	2010-01-26 06:28:43 +0000	[diff] [blame]	1092	TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
				1093	unsigned JTI,MCContext &Ctx) const{
Chris Lattner	beeb93e	2010-01-26 05:58:28 +0000	[diff] [blame]	1094	// The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner	589c6f6	2010-01-26 06:28:43 +0000	[diff] [blame]	1095	return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner	13e97a2	2010-01-26 05:30:30 +0000	[diff] [blame]	1096	}
				1097
Dan Gohman	6520e20	2008-10-18 02:06:02 +0000	[diff] [blame]	1098	bool
				1099	TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
				1100	// Assume that everything is safe in static mode.
				1101	if (getTargetMachine().getRelocationModel() == Reloc::Static)
				1102	return true;
				1103
				1104	// In dynamic-no-pic mode, assume that known defined values are safe.
				1105	if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
				1106	GA &&
				1107	!GA->getGlobal()->isDeclaration() &&
Duncan Sands	667d4b8	2009-03-07 15:45:40 +0000	[diff] [blame]	1108	!GA->getGlobal()->isWeakForLinker())
Dan Gohman	6520e20	2008-10-18 02:06:02 +0000	[diff] [blame]	1109	return true;
				1110
				1111	// Otherwise assume nothing is safe.
				1112	return false;
				1113	}
				1114
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	1115	//===----------------------------------------------------------------------===//
				1116	// Optimization Methods
				1117	//===----------------------------------------------------------------------===//
				1118
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1119	/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1120	/// specified instruction is a constant integer. If so, check to see if there
				1121	/// are any bits set in the constant that are not demanded. If so, shrink the
				1122	/// constant and return true.
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1123	bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1124	const APInt &Demanded) {
Dale Johannesen	de06470	2009-02-06 21:50:26 +0000	[diff] [blame]	1125	DebugLoc dl = Op.getDebugLoc();
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1126
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1127	// FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1128	switch (Op.getOpcode()) {
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1129	default: break;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1130	case ISD::XOR:
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1131	case ISD::AND:
				1132	case ISD::OR: {
				1133	ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
				1134	if (!C) return false;
				1135
				1136	if (Op.getOpcode() == ISD::XOR &&
				1137	(C->getAPIntValue() \| (~Demanded)).isAllOnesValue())
				1138	return false;
				1139
				1140	// if we can expand it to have all bits set, do it
				1141	if (C->getAPIntValue().intersects(~Demanded)) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1142	EVT VT = Op.getValueType();
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1143	SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
				1144	DAG.getConstant(Demanded &
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1145	C->getAPIntValue(),
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1146	VT));
				1147	return CombineTo(Op, New);
				1148	}
				1149
Nate Begeman	de99629	2006-02-03 22:24:05 +0000	[diff] [blame]	1150	break;
				1151	}
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1152	}
				1153
Nate Begeman	de99629	2006-02-03 22:24:05 +0000	[diff] [blame]	1154	return false;
				1155	}
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1156
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1157	/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
				1158	/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
				1159	/// cast, but it could be generalized for targets with other types of
				1160	/// implicit widening casts.
				1161	bool
				1162	TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
				1163	unsigned BitWidth,
				1164	const APInt &Demanded,
				1165	DebugLoc dl) {
				1166	assert(Op.getNumOperands() == 2 &&
				1167	"ShrinkDemandedOp only supports binary operators!");
				1168	assert(Op.getNode()->getNumValues() == 1 &&
				1169	"ShrinkDemandedOp only supports nodes with one result!");
				1170
				1171	// Don't do this if the node has another user, which may require the
				1172	// full value.
				1173	if (!Op.getNode()->hasOneUse())
				1174	return false;
				1175
				1176	// Search for the smallest integer type with free casts to and from
				1177	// Op's type. For expedience, just check power-of-2 integer types.
				1178	const TargetLowering &TLI = DAG.getTargetLoweringInfo();
				1179	unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
				1180	if (!isPowerOf2_32(SmallVTBits))
				1181	SmallVTBits = NextPowerOf2(SmallVTBits);
				1182	for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	1183	EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1184	if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
				1185	TLI.isZExtFree(SmallVT, Op.getValueType())) {
				1186	// We found a type with free casts.
				1187	SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
				1188	DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
				1189	Op.getNode()->getOperand(0)),
				1190	DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
				1191	Op.getNode()->getOperand(1)));
				1192	SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
				1193	return CombineTo(Op, Z);
				1194	}
				1195	}
				1196	return false;
				1197	}
				1198
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1199	/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Chad Rosier	8c1ec5a	2011-06-11 02:27:46 +0000	[diff] [blame]	1200	/// DemandedMask bits of the result of Op are ever used downstream. If we can
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1201	/// use this information to simplify Op, create a new simplified DAG node and
				1202	/// return true, returning the original and new nodes in Old and New. Otherwise,
				1203	/// analyze the expression and return a mask of KnownOne and KnownZero bits for
				1204	/// the expression (used to simplify the caller). The KnownZero/One bits may
				1205	/// only be accurate for those bits in the DemandedMask.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1206	bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1207	const APInt &DemandedMask,
				1208	APInt &KnownZero,
				1209	APInt &KnownOne,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1210	TargetLoweringOpt &TLO,
				1211	unsigned Depth) const {
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1212	unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman	87862e7	2009-12-11 21:31:27 +0000	[diff] [blame]	1213	assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1214	"Mask size mismatches value type size!");
				1215	APInt NewMask = DemandedMask;
Dale Johannesen	6f38cb6	2009-02-07 19:59:05 +0000	[diff] [blame]	1216	DebugLoc dl = Op.getDebugLoc();
Chris Lattner	3fc5b01	2007-05-17 18:19:23 +0000	[diff] [blame]	1217
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1218	// Don't know anything.
				1219	KnownZero = KnownOne = APInt(BitWidth, 0);
				1220
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1221	// Other users may use these bits.
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1222	if (!Op.getNode()->hasOneUse()) {
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1223	if (Depth != 0) {
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1224	// If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1225	// simplify things downstream.
Rafael Espindola	26c8dcc	2012-04-04 12:51:34 +0000	[diff] [blame]	1226	TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1227	return false;
				1228	}
				1229	// If this is the root being simplified, allow it to have multiple uses,
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1230	// just set the NewMask to all bits.
				1231	NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1232	} else if (DemandedMask == 0) {
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1233	// Not demanding any bits from Op.
				1234	if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesen	e8d7230	2009-02-06 23:05:02 +0000	[diff] [blame]	1235	return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1236	return false;
				1237	} else if (Depth == 6) { // Limit search depth.
				1238	return false;
				1239	}
				1240
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1241	APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1242	switch (Op.getOpcode()) {
				1243	case ISD::Constant:
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1244	// We know all of the bits for a constant!
Rafael Espindola	26c8dcc	2012-04-04 12:51:34 +0000	[diff] [blame]	1245	KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
				1246	KnownZero = ~KnownOne;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1247	return false; // Don't fall through, will infinitely loop.
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1248	case ISD::AND:
Chris Lattner	81cd355	2006-02-27 00:36:27 +0000	[diff] [blame]	1249	// If the RHS is a constant, check to see if the LHS would be zero without
				1250	// using the bits from the RHS. Below, we use knowledge about the RHS to
				1251	// simplify the LHS, here we're using information from the LHS to simplify
				1252	// the RHS.
				1253	if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1254	APInt LHSZero, LHSOne;
Dale Johannesen	97fd9a5	2011-01-10 21:53:07 +0000	[diff] [blame]	1255	// Do not increment Depth here; that can cause an infinite loop.
Rafael Espindola	26c8dcc	2012-04-04 12:51:34 +0000	[diff] [blame]	1256	TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
Chris Lattner	81cd355	2006-02-27 00:36:27 +0000	[diff] [blame]	1257	// If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1258	if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner	81cd355	2006-02-27 00:36:27 +0000	[diff] [blame]	1259	return TLO.CombineTo(Op, Op.getOperand(0));
				1260	// If any of the set bits in the RHS are known zero on the LHS, shrink
				1261	// the constant.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1262	if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner	81cd355	2006-02-27 00:36:27 +0000	[diff] [blame]	1263	return true;
				1264	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1265
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1266	if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1267	KnownOne, TLO, Depth+1))
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1268	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1269	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1270	if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1271	KnownZero2, KnownOne2, TLO, Depth+1))
				1272	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1273	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1274
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1275	// If all of the demanded bits are known one on one side, return the other.
				1276	// These bits cannot contribute to the result of the 'and'.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1277	if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1278	return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1279	if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1280	return TLO.CombineTo(Op, Op.getOperand(1));
				1281	// If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1282	if ((NewMask & (KnownZero\|KnownZero2)) == NewMask)
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1283	return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
				1284	// If the RHS is a constant, see if we can simplify it.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1285	if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1286	return true;
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1287	// If the operation can be done in a smaller type, do so.
Dan Gohman	4e39e9d	2010-06-24 14:30:44 +0000	[diff] [blame]	1288	if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1289	return true;
				1290
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1291	// Output known-1 bits are only known if set in both the LHS & RHS.
				1292	KnownOne &= KnownOne2;
				1293	// Output known-0 are known to be clear if zero in either the LHS \| RHS.
				1294	KnownZero \|= KnownZero2;
				1295	break;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1296	case ISD::OR:
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1297	if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1298	KnownOne, TLO, Depth+1))
				1299	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1300	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1301	if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1302	KnownZero2, KnownOne2, TLO, Depth+1))
				1303	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1304	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1305
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1306	// If all of the demanded bits are known zero on one side, return the other.
				1307	// These bits cannot contribute to the result of the 'or'.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1308	if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1309	return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1310	if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1311	return TLO.CombineTo(Op, Op.getOperand(1));
				1312	// If all of the potentially set bits on one side are known to be set on
				1313	// the other side, just use the 'other' side.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1314	if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1315	return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1316	if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1317	return TLO.CombineTo(Op, Op.getOperand(1));
				1318	// If the RHS is a constant, see if we can simplify it.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1319	if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1320	return true;
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1321	// If the operation can be done in a smaller type, do so.
Dan Gohman	4e39e9d	2010-06-24 14:30:44 +0000	[diff] [blame]	1322	if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1323	return true;
				1324
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1325	// Output known-0 bits are only known if clear in both the LHS & RHS.
				1326	KnownZero &= KnownZero2;
				1327	// Output known-1 are known to be set if set in either the LHS \| RHS.
				1328	KnownOne \|= KnownOne2;
				1329	break;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1330	case ISD::XOR:
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1331	if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1332	KnownOne, TLO, Depth+1))
				1333	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1334	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1335	if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1336	KnownOne2, TLO, Depth+1))
				1337	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1338	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1339
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1340	// If all of the demanded bits are known zero on one side, return the other.
				1341	// These bits cannot contribute to the result of the 'xor'.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1342	if ((KnownZero & NewMask) == NewMask)
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1343	return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1344	if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1345	return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1346	// If the operation can be done in a smaller type, do so.
Dan Gohman	4e39e9d	2010-06-24 14:30:44 +0000	[diff] [blame]	1347	if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1348	return true;
				1349
Chris Lattner	3687c1a	2006-11-27 21:50:02 +0000	[diff] [blame]	1350	// If all of the unknown bits are known to be zero on one side or the other
				1351	// (but not both) turn this into an inclusive or.
				1352	// e.g. (A & C1)^(B & C2) -> (A & C1)\|(B & C2) iff C1&C2 == 0
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1353	if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesen	de06470	2009-02-06 21:50:26 +0000	[diff] [blame]	1354	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner	3687c1a	2006-11-27 21:50:02 +0000	[diff] [blame]	1355	Op.getOperand(0),
				1356	Op.getOperand(1)));
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1357
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1358	// Output known-0 bits are known if clear or set in both the LHS & RHS.
				1359	KnownZeroOut = (KnownZero & KnownZero2) \| (KnownOne & KnownOne2);
				1360	// Output known-1 are known to be set if set in only one of the LHS, RHS.
				1361	KnownOneOut = (KnownZero & KnownOne2) \| (KnownOne & KnownZero2);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1362
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1363	// If all of the demanded bits on one side are known, and all of the set
				1364	// bits on that side are also known to be set on the other side, turn this
				1365	// into an AND, as we know the bits will be cleared.
				1366	// e.g. (X \| C1) ^ C2 --> (X \| C1) & ~C2 iff (C1&C2) == C2
Joel Jones	d16ce17	2012-04-17 22:23:10 +0000	[diff] [blame]	1367	// NB: it is okay if more bits are known than are requested
				1368	if ((NewMask & (KnownZero\|KnownOne)) == NewMask) { // all known on one side
				1369	if (KnownOne == KnownOne2) { // set bits are the same on both sides
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1370	EVT VT = Op.getValueType();
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1371	SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1372	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1373	Op.getOperand(0), ANDC));
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1374	}
				1375	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1376
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1377	// If the RHS is a constant, see if we can simplify it.
Torok Edwin	4fea2e9	2008-04-06 21:23:02 +0000	[diff] [blame]	1378	// for XOR, we prefer to force bits to 1 if they will make a -1.
				1379	// if we can't force bits, try to shrink constant
				1380	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
				1381	APInt Expanded = C->getAPIntValue() \| (~NewMask);
				1382	// if we can expand it to have all bits set, do it
				1383	if (Expanded.isAllOnesValue()) {
				1384	if (Expanded != C->getAPIntValue()) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1385	EVT VT = Op.getValueType();
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1386	SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin	4fea2e9	2008-04-06 21:23:02 +0000	[diff] [blame]	1387	TLO.DAG.getConstant(Expanded, VT));
				1388	return TLO.CombineTo(Op, New);
				1389	}
				1390	// if it already has all the bits set, nothing to change
				1391	// but don't shrink either!
				1392	} else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
				1393	return true;
				1394	}
				1395	}
				1396
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1397	KnownZero = KnownZeroOut;
				1398	KnownOne = KnownOneOut;
				1399	break;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1400	case ISD::SELECT:
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1401	if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1402	KnownOne, TLO, Depth+1))
				1403	return true;
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1404	if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1405	KnownOne2, TLO, Depth+1))
				1406	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1407	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
				1408	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1409
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1410	// If the operands are constants, see if we can simplify them.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1411	if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1412	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1413
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1414	// Only known if known in both the LHS and RHS.
				1415	KnownOne &= KnownOne2;
				1416	KnownZero &= KnownZero2;
				1417	break;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1418	case ISD::SELECT_CC:
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1419	if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1420	KnownOne, TLO, Depth+1))
				1421	return true;
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1422	if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1423	KnownOne2, TLO, Depth+1))
				1424	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1425	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
				1426	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1427
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1428	// If the operands are constants, see if we can simplify them.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1429	if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1430	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1431
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1432	// Only known if known in both the LHS and RHS.
				1433	KnownOne &= KnownOne2;
				1434	KnownZero &= KnownZero2;
				1435	break;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1436	case ISD::SHL:
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1437	if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1438	unsigned ShAmt = SA->getZExtValue();
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1439	SDValue InOp = Op.getOperand(0);
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1440
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1441	// If the shift count is an invalid immediate, don't do anything.
				1442	if (ShAmt >= BitWidth)
				1443	break;
				1444
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1445	// If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
				1446	// single shift. We can do this if the bottom bits (which are shifted
				1447	// out) are never demanded.
				1448	if (InOp.getOpcode() == ISD::SRL &&
				1449	isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1450	if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1451	unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1452	unsigned Opc = ISD::SHL;
				1453	int Diff = ShAmt-C1;
				1454	if (Diff < 0) {
				1455	Diff = -Diff;
				1456	Opc = ISD::SRL;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1457	}
				1458
				1459	SDValue NewSA =
Chris Lattner	4e7e6cd	2007-05-30 16:30:06 +0000	[diff] [blame]	1460	TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1461	EVT VT = Op.getValueType();
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1462	return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1463	InOp.getOperand(0), NewSA));
				1464	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1465	}
				1466
Dan Gohman	a4f4d69	2010-07-23 18:03:30 +0000	[diff] [blame]	1467	if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1468	KnownZero, KnownOne, TLO, Depth+1))
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1469	return true;
Dan Gohman	a4f4d69	2010-07-23 18:03:30 +0000	[diff] [blame]	1470
				1471	// Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
				1472	// are not demanded. This will likely allow the anyext to be folded away.
				1473	if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
				1474	SDValue InnerOp = InOp.getNode()->getOperand(0);
				1475	EVT InnerVT = InnerOp.getValueType();
Eli Friedman	2dd0353	2011-12-09 01:16:26 +0000	[diff] [blame]	1476	unsigned InnerBits = InnerVT.getSizeInBits();
				1477	if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
Dan Gohman	a4f4d69	2010-07-23 18:03:30 +0000	[diff] [blame]	1478	isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	1479	EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohman	cd20c6f	2010-07-23 21:08:12 +0000	[diff] [blame]	1480	if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
				1481	ShTy = InnerVT;
Dan Gohman	a4f4d69	2010-07-23 18:03:30 +0000	[diff] [blame]	1482	SDValue NarrowShl =
				1483	TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohman	cd20c6f	2010-07-23 21:08:12 +0000	[diff] [blame]	1484	TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohman	a4f4d69	2010-07-23 18:03:30 +0000	[diff] [blame]	1485	return
				1486	TLO.CombineTo(Op,
				1487	TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
				1488	NarrowShl));
				1489	}
				1490	}
				1491
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1492	KnownZero <<= SA->getZExtValue();
				1493	KnownOne <<= SA->getZExtValue();
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1494	// low bits known zero.
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1495	KnownZero \|= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1496	}
				1497	break;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1498	case ISD::SRL:
				1499	if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1500	EVT VT = Op.getValueType();
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1501	unsigned ShAmt = SA->getZExtValue();
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	1502	unsigned VTSize = VT.getSizeInBits();
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1503	SDValue InOp = Op.getOperand(0);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1504
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1505	// If the shift count is an invalid immediate, don't do anything.
				1506	if (ShAmt >= BitWidth)
				1507	break;
				1508
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1509	// If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
				1510	// single shift. We can do this if the top bits (which are shifted out)
				1511	// are never demanded.
				1512	if (InOp.getOpcode() == ISD::SHL &&
				1513	isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1514	if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1515	unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1516	unsigned Opc = ISD::SRL;
				1517	int Diff = ShAmt-C1;
				1518	if (Diff < 0) {
				1519	Diff = -Diff;
				1520	Opc = ISD::SHL;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1521	}
				1522
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1523	SDValue NewSA =
Chris Lattner	8c7d2d5	2007-04-17 22:53:02 +0000	[diff] [blame]	1524	TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1525	return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1526	InOp.getOperand(0), NewSA));
				1527	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1528	}
				1529
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1530	// Compute the new bits that are at the top now.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1531	if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1532	KnownZero, KnownOne, TLO, Depth+1))
				1533	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1534	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1535	KnownZero = KnownZero.lshr(ShAmt);
				1536	KnownOne = KnownOne.lshr(ShAmt);
Chris Lattner	c4fa603	2006-06-13 16:52:37 +0000	[diff] [blame]	1537
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1538	APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattner	c4fa603	2006-06-13 16:52:37 +0000	[diff] [blame]	1539	KnownZero \|= HighBits; // High bits known zero.
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1540	}
				1541	break;
				1542	case ISD::SRA:
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1543	// If this is an arithmetic shift right and only the low-bit is set, we can
				1544	// always convert this into a logical shr, even if the shift amount is
				1545	// variable. The low bit of the shift cannot be an input sign bit unless
				1546	// the shift amount is >= the size of the datatype, which is undefined.
Eli Friedman	2dd0353	2011-12-09 01:16:26 +0000	[diff] [blame]	1547	if (NewMask == 1)
Evan Cheng	e5b51ac	2010-04-17 06:13:15 +0000	[diff] [blame]	1548	return TLO.CombineTo(Op,
				1549	TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
				1550	Op.getOperand(0), Op.getOperand(1)));
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1551
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1552	if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1553	EVT VT = Op.getValueType();
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1554	unsigned ShAmt = SA->getZExtValue();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1555
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1556	// If the shift count is an invalid immediate, don't do anything.
				1557	if (ShAmt >= BitWidth)
				1558	break;
				1559
				1560	APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner	1b73713	2006-05-08 17:22:53 +0000	[diff] [blame]	1561
				1562	// If any of the demanded bits are produced by the sign extension, we also
				1563	// demand the input sign bit.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1564	APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
				1565	if (HighBits.intersects(NewMask))
Dan Gohman	87862e7	2009-12-11 21:31:27 +0000	[diff] [blame]	1566	InDemandedMask \|= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1567
Chris Lattner	1b73713	2006-05-08 17:22:53 +0000	[diff] [blame]	1568	if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1569	KnownZero, KnownOne, TLO, Depth+1))
				1570	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1571	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1572	KnownZero = KnownZero.lshr(ShAmt);
				1573	KnownOne = KnownOne.lshr(ShAmt);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1574
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1575	// Handle the sign bit, adjusted to where it is now in the mask.
				1576	APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1577
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1578	// If the input sign bit is known to be zero, or if none of the top bits
				1579	// are demanded, turn this into an unsigned shift right.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1580	if (KnownZero.intersects(SignBit) \|\| (HighBits & ~NewMask) == HighBits) {
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1581	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1582	Op.getOperand(0),
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1583	Op.getOperand(1)));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1584	} else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1585	KnownOne \|= HighBits;
				1586	}
				1587	}
				1588	break;
				1589	case ISD::SIGN_EXTEND_INREG: {
Nadav Rotem	cc61656	2012-01-15 19:27:55 +0000	[diff] [blame]	1590	EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
				1591
				1592	APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
				1593	// If we only care about the highest bit, don't bother shifting right.
Eli Friedman	d49db36	2012-01-31 01:08:03 +0000	[diff] [blame]	1594	if (MsbMask == DemandedMask) {
Nadav Rotem	cc61656	2012-01-15 19:27:55 +0000	[diff] [blame]	1595	unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
				1596	SDValue InOp = Op.getOperand(0);
Eli Friedman	d49db36	2012-01-31 01:08:03 +0000	[diff] [blame]	1597
				1598	// Compute the correct shift amount type, which must be getShiftAmountTy
				1599	// for scalar types after legalization.
				1600	EVT ShiftAmtTy = Op.getValueType();
				1601	if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
				1602	ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
				1603
				1604	SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
Nadav Rotem	cc61656	2012-01-15 19:27:55 +0000	[diff] [blame]	1605	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
				1606	Op.getValueType(), InOp, ShiftAmt));
				1607	}
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1608
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1609	// Sign extension. Compute the demanded bits in the result that are not
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1610	// present in the input.
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1611	APInt NewBits =
				1612	APInt::getHighBitsSet(BitWidth,
Nadav Rotem	cc61656	2012-01-15 19:27:55 +0000	[diff] [blame]	1613	BitWidth - ExVT.getScalarType().getSizeInBits());
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1614
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1615	// If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman	1d17d19	2010-08-02 04:42:25 +0000	[diff] [blame]	1616	if ((NewBits & NewMask) == 0)
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1617	return TLO.CombineTo(Op, Op.getOperand(0));
				1618
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1619	APInt InSignBit =
Nadav Rotem	cc61656	2012-01-15 19:27:55 +0000	[diff] [blame]	1620	APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1621	APInt InputDemandedBits =
				1622	APInt::getLowBitsSet(BitWidth,
Nadav Rotem	cc61656	2012-01-15 19:27:55 +0000	[diff] [blame]	1623	ExVT.getScalarType().getSizeInBits()) &
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1624	NewMask;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1625
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1626	// Since the sign extended bits are demanded, we know that the sign
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1627	// bit is demanded.
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1628	InputDemandedBits \|= InSignBit;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1629
				1630	if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
				1631	KnownZero, KnownOne, TLO, Depth+1))
				1632	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1633	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1634
				1635	// If the sign bit of the input is known set or clear, then we know the
				1636	// top bits of the result.
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1637
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1638	// If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1639	if (KnownZero.intersects(InSignBit))
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1640	return TLO.CombineTo(Op,
Nadav Rotem	cc61656	2012-01-15 19:27:55 +0000	[diff] [blame]	1641	TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1642
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1643	if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1644	KnownOne \|= NewBits;
				1645	KnownZero &= ~NewBits;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1646	} else { // Input sign bit unknown
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1647	KnownZero &= ~NewBits;
				1648	KnownOne &= ~NewBits;
				1649	}
				1650	break;
				1651	}
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1652	case ISD::ZERO_EXTEND: {
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1653	unsigned OperandBitWidth =
				1654	Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1655	APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1656
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1657	// If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1658	APInt NewBits =
				1659	APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
				1660	if (!NewBits.intersects(NewMask))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1661	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1662	Op.getValueType(),
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1663	Op.getOperand(0)));
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1664
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1665	if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1666	KnownZero, KnownOne, TLO, Depth+1))
				1667	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1668	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1669	KnownZero = KnownZero.zext(BitWidth);
				1670	KnownOne = KnownOne.zext(BitWidth);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1671	KnownZero \|= NewBits;
				1672	break;
				1673	}
				1674	case ISD::SIGN_EXTEND: {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1675	EVT InVT = Op.getOperand(0).getValueType();
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1676	unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1677	APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman	9736028	2008-03-11 21:29:43 +0000	[diff] [blame]	1678	APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1679	APInt NewBits = ~InMask & NewMask;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1680
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1681	// If none of the top bits are demanded, convert this into an any_extend.
				1682	if (NewBits == 0)
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1683	return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
				1684	Op.getValueType(),
				1685	Op.getOperand(0)));
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1686
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1687	// Since some of the sign extended bits are demanded, we know that the sign
				1688	// bit is demanded.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1689	APInt InDemandedBits = InMask & NewMask;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1690	InDemandedBits \|= InSignBit;
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1691	InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1692
				1693	if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1694	KnownOne, TLO, Depth+1))
				1695	return true;
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1696	KnownZero = KnownZero.zext(BitWidth);
				1697	KnownOne = KnownOne.zext(BitWidth);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1698
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1699	// If the sign bit is known zero, convert this to a zero extend.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1700	if (KnownZero.intersects(InSignBit))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1701	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1702	Op.getValueType(),
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1703	Op.getOperand(0)));
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1704
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1705	// If the sign bit is known one, the top bits match.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1706	if (KnownOne.intersects(InSignBit)) {
Rafael Espindola	26c8dcc	2012-04-04 12:51:34 +0000	[diff] [blame]	1707	KnownOne \|= NewBits;
				1708	assert((KnownZero & NewBits) == 0);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1709	} else { // Otherwise, top bits aren't known.
Rafael Espindola	26c8dcc	2012-04-04 12:51:34 +0000	[diff] [blame]	1710	assert((KnownOne & NewBits) == 0);
				1711	assert((KnownZero & NewBits) == 0);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1712	}
				1713	break;
				1714	}
				1715	case ISD::ANY_EXTEND: {
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1716	unsigned OperandBitWidth =
				1717	Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1718	APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1719	if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1720	KnownZero, KnownOne, TLO, Depth+1))
				1721	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1722	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1723	KnownZero = KnownZero.zext(BitWidth);
				1724	KnownOne = KnownOne.zext(BitWidth);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1725	break;
				1726	}
Chris Lattner	fe8babf	2006-05-05 22:32:12 +0000	[diff] [blame]	1727	case ISD::TRUNCATE: {
Chris Lattner	c93dfda	2006-05-06 00:11:52 +0000	[diff] [blame]	1728	// Simplify the input, using demanded bit information, and compute the known
				1729	// zero/one bits live out.
Dan Gohman	042919c	2010-03-01 17:59:21 +0000	[diff] [blame]	1730	unsigned OperandBitWidth =
				1731	Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1732	APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1733	if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattner	fe8babf	2006-05-05 22:32:12 +0000	[diff] [blame]	1734	KnownZero, KnownOne, TLO, Depth+1))
				1735	return true;
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1736	KnownZero = KnownZero.trunc(BitWidth);
				1737	KnownOne = KnownOne.trunc(BitWidth);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1738
Chris Lattner	c93dfda	2006-05-06 00:11:52 +0000	[diff] [blame]	1739	// If the input is only used by this truncate, see if we can shrink it based
				1740	// on the known demanded bits.
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	1741	if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1742	SDValue In = Op.getOperand(0);
Chris Lattner	c93dfda	2006-05-06 00:11:52 +0000	[diff] [blame]	1743	switch (In.getOpcode()) {
				1744	default: break;
				1745	case ISD::SRL:
				1746	// Shrink SRL by a constant if none of the high bits shifted in are
				1747	// demanded.
Evan Cheng	e5b51ac	2010-04-17 06:13:15 +0000	[diff] [blame]	1748	if (TLO.LegalTypes() &&
				1749	!isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
				1750	// Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
				1751	// undesirable.
				1752	break;
				1753	ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
				1754	if (!ShAmt)
				1755	break;
Owen Anderson	7adf862	2011-04-13 23:22:23 +0000	[diff] [blame]	1756	SDValue Shift = In.getOperand(1);
				1757	if (TLO.LegalTypes()) {
				1758	uint64_t ShVal = ShAmt->getZExtValue();
				1759	Shift =
				1760	TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
				1761	}
				1762
Evan Cheng	e5b51ac	2010-04-17 06:13:15 +0000	[diff] [blame]	1763	APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
				1764	OperandBitWidth - BitWidth);
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	1765	HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Cheng	e5b51ac	2010-04-17 06:13:15 +0000	[diff] [blame]	1766
				1767	if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
				1768	// None of the shifted in bits are needed. Add a truncate of the
				1769	// shift input, then shift it.
				1770	SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1771	Op.getValueType(),
Evan Cheng	e5b51ac	2010-04-17 06:13:15 +0000	[diff] [blame]	1772	In.getOperand(0));
				1773	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
				1774	Op.getValueType(),
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1775	NewTrunc,
Owen Anderson	7adf862	2011-04-13 23:22:23 +0000	[diff] [blame]	1776	Shift));
Chris Lattner	c93dfda	2006-05-06 00:11:52 +0000	[diff] [blame]	1777	}
				1778	break;
				1779	}
				1780	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1781
				1782	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattner	fe8babf	2006-05-05 22:32:12 +0000	[diff] [blame]	1783	break;
				1784	}
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1785	case ISD::AssertZext: {
Owen Anderson	7ab15f6	2011-09-03 00:26:49 +0000	[diff] [blame]	1786	// AssertZext demands all of the high bits, plus any of the low bits
				1787	// demanded by its users.
				1788	EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
				1789	APInt InMask = APInt::getLowBitsSet(BitWidth,
				1790	VT.getSizeInBits());
				1791	if (SimplifyDemandedBits(Op.getOperand(0), ~InMask \| NewMask,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1792	KnownZero, KnownOne, TLO, Depth+1))
				1793	return true;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1794	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	400f75c	2010-06-03 20:21:33 +0000	[diff] [blame]	1795
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1796	KnownZero \|= ~InMask & NewMask;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1797	break;
				1798	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1799	case ISD::BITCAST:
Stuart Hastings	57f1fde	2011-06-06 16:44:31 +0000	[diff] [blame]	1800	// If this is an FP->Int bitcast and if the sign bit is the only
				1801	// thing demanded, turn this into a FGETSIGN.
Eli Friedman	ca072a3	2011-12-15 02:07:20 +0000	[diff] [blame]	1802	if (!TLO.LegalOperations() &&
				1803	!Op.getValueType().isVector() &&
Eli Friedman	0948f0a	2011-11-09 22:25:12 +0000	[diff] [blame]	1804	!Op.getOperand(0).getValueType().isVector() &&
Nadav Rotem	0c3e678	2011-06-12 14:56:55 +0000	[diff] [blame]	1805	NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
				1806	Op.getOperand(0).getValueType().isFloatingPoint()) {
Stuart Hastings	57f1fde	2011-06-06 16:44:31 +0000	[diff] [blame]	1807	bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
				1808	bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
				1809	if ((OpVTLegal \|\| i32Legal) && Op.getValueType().isSimple()) {
				1810	EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
Chris Lattner	2ceb2cf	2007-12-22 21:35:38 +0000	[diff] [blame]	1811	// Make a FGETSIGN + SHL to move the sign bit into the appropriate
				1812	// place. We expect the SHL to be eliminated by other optimizations.
Stuart Hastings	090bf19	2011-06-01 18:32:25 +0000	[diff] [blame]	1813	SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Stuart Hastings	57f1fde	2011-06-06 16:44:31 +0000	[diff] [blame]	1814	unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
				1815	if (!OpVTLegal && OpVTSizeInBits > 32)
Stuart Hastings	090bf19	2011-06-01 18:32:25 +0000	[diff] [blame]	1816	Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	1817	unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Stuart Hastings	bdce372	2011-06-01 14:04:17 +0000	[diff] [blame]	1818	SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Stuart Hastings	3dfc4b12	2011-05-19 18:48:20 +0000	[diff] [blame]	1819	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
				1820	Op.getValueType(),
Chris Lattner	2ceb2cf	2007-12-22 21:35:38 +0000	[diff] [blame]	1821	Sign, ShAmt));
				1822	}
				1823	}
Chris Lattner	2ceb2cf	2007-12-22 21:35:38 +0000	[diff] [blame]	1824	break;
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1825	case ISD::ADD:
				1826	case ISD::MUL:
				1827	case ISD::SUB: {
				1828	// Add, Sub, and Mul don't demand any bits in positions beyond that
				1829	// of the highest bit demanded of them.
				1830	APInt LoMask = APInt::getLowBitsSet(BitWidth,
				1831	BitWidth - NewMask.countLeadingZeros());
				1832	if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
				1833	KnownOne2, TLO, Depth+1))
				1834	return true;
				1835	if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
				1836	KnownOne2, TLO, Depth+1))
				1837	return true;
				1838	// See if the operation should be performed at a smaller bit width.
Dan Gohman	4e39e9d	2010-06-24 14:30:44 +0000	[diff] [blame]	1839	if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1840	return true;
				1841	}
				1842	// FALL THROUGH
Dan Gohman	54eed37	2008-05-06 00:53:29 +0000	[diff] [blame]	1843	default:
Chris Lattner	1482b5f	2006-04-02 06:15:09 +0000	[diff] [blame]	1844	// Just use ComputeMaskedBits to compute output bits.
Rafael Espindola	26c8dcc	2012-04-04 12:51:34 +0000	[diff] [blame]	1845	TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Chris Lattner	a6bc5a4	2006-02-27 01:00:42 +0000	[diff] [blame]	1846	break;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1847	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1848
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1849	// If we know the value of all of the demanded bits, return this as a
				1850	// constant.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1851	if ((NewMask & (KnownZero\|KnownOne)) == NewMask)
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1852	return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1853
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1854	return false;
				1855	}
				1856
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1857	/// computeMaskedBitsForTargetNode - Determine which of the bits specified
				1858	/// in Mask are known to be either zero or one and return them in the
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1859	/// KnownZero/KnownOne bitsets.
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1860	void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1861	APInt &KnownZero,
Dan Gohman	fd29e0e	2008-02-13 00:35:47 +0000	[diff] [blame]	1862	APInt &KnownOne,
Dan Gohman	ea859be	2007-06-22 14:59:07 +0000	[diff] [blame]	1863	const SelectionDAG &DAG,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1864	unsigned Depth) const {
Chris Lattner	1b5232a	2006-04-02 06:19:46 +0000	[diff] [blame]	1865	assert((Op.getOpcode() >= ISD::BUILTIN_OP_END \|\|
				1866	Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN \|\|
				1867	Op.getOpcode() == ISD::INTRINSIC_W_CHAIN \|\|
				1868	Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1869	"Should use MaskedValueIsZero if you don't know whether Op"
				1870	" is a target node!");
Rafael Espindola	26c8dcc	2012-04-04 12:51:34 +0000	[diff] [blame]	1871	KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
Evan Cheng	3a03ebb	2005-12-21 23:05:39 +0000	[diff] [blame]	1872	}
Chris Lattner	4ccb070	2006-01-26 20:37:03 +0000	[diff] [blame]	1873
Chris Lattner	5c3e21d	2006-05-06 09:27:13 +0000	[diff] [blame]	1874	/// ComputeNumSignBitsForTargetNode - This method can be implemented by
				1875	/// targets that want to expose additional information about sign bits to the
				1876	/// DAG Combiner.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1877	unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner	5c3e21d	2006-05-06 09:27:13 +0000	[diff] [blame]	1878	unsigned Depth) const {
				1879	assert((Op.getOpcode() >= ISD::BUILTIN_OP_END \|\|
				1880	Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN \|\|
				1881	Op.getOpcode() == ISD::INTRINSIC_W_CHAIN \|\|
				1882	Op.getOpcode() == ISD::INTRINSIC_VOID) &&
				1883	"Should use ComputeNumSignBits if you don't know whether Op"
				1884	" is a target node!");
				1885	return 1;
				1886	}
				1887
Dan Gohman	97d1163	2009-02-15 23:59:32 +0000	[diff] [blame]	1888	/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
				1889	/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
				1890	/// determine which bit is set.
				1891	///
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	1892	static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman	97d1163	2009-02-15 23:59:32 +0000	[diff] [blame]	1893	// A left-shift of a constant one will have exactly one bit set, because
				1894	// shifting the bit off the end is undefined.
				1895	if (Val.getOpcode() == ISD::SHL)
				1896	if (ConstantSDNode *C =
				1897	dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
				1898	if (C->getAPIntValue() == 1)
				1899	return true;
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1900
Dan Gohman	97d1163	2009-02-15 23:59:32 +0000	[diff] [blame]	1901	// Similarly, a right-shift of a constant sign-bit will have exactly
				1902	// one bit set.
				1903	if (Val.getOpcode() == ISD::SRL)
				1904	if (ConstantSDNode *C =
				1905	dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
				1906	if (C->getAPIntValue().isSignBit())
				1907	return true;
				1908
				1909	// More could be done here, though the above checks are enough
				1910	// to handle some common cases.
				1911
				1912	// Fall back to ComputeMaskedBits to catch other known cases.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1913	EVT OpVT = Val.getValueType();
Dan Gohman	5b870af	2010-03-02 02:14:38 +0000	[diff] [blame]	1914	unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1915	APInt KnownZero, KnownOne;
Rafael Espindola	26c8dcc	2012-04-04 12:51:34 +0000	[diff] [blame]	1916	DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	1917	return (KnownZero.countPopulation() == BitWidth - 1) &&
				1918	(KnownOne.countPopulation() == 1);
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1919	}
Chris Lattner	5c3e21d	2006-05-06 09:27:13 +0000	[diff] [blame]	1920
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	1921	/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1922	/// and cc. If it is unable to simplify it, return a null SDValue.
				1923	SDValue
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1924	TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1925	ISD::CondCode Cond, bool foldBooleans,
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1926	DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1927	SelectionDAG &DAG = DCI.DAG;
				1928
				1929	// These setcc operations always fold.
				1930	switch (Cond) {
				1931	default: break;
				1932	case ISD::SETFALSE:
				1933	case ISD::SETFALSE2: return DAG.getConstant(0, VT);
				1934	case ISD::SETTRUE:
				1935	case ISD::SETTRUE2: return DAG.getConstant(1, VT);
				1936	}
				1937
Chris Lattner	7a2bdde	2011-04-15 05:18:47 +0000	[diff] [blame]	1938	// Ensure that the constant occurs on the RHS, and fold constant
				1939	// comparisons.
				1940	if (isa<ConstantSDNode>(N0.getNode()))
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1941	return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Eric Christopher	362fee9	2011-06-17 20:41:29 +0000	[diff] [blame]	1942
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	1943	if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman	6c6cd1c	2008-03-03 22:22:56 +0000	[diff] [blame]	1944	const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen	89217a6	2008-11-07 01:28:02 +0000	[diff] [blame]	1945
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1946	// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
				1947	// equality comparison, then we're just comparing whether X itself is
				1948	// zero.
				1949	if (N0.getOpcode() == ISD::SRL && (C1 == 0 \|\| C1 == 1) &&
				1950	N0.getOperand(0).getOpcode() == ISD::CTLZ &&
				1951	N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1952	const APInt &ShAmt
				1953	= cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1954	if ((Cond == ISD::SETEQ \|\| Cond == ISD::SETNE) &&
				1955	ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
				1956	if ((C1 == 0) == (Cond == ISD::SETEQ)) {
				1957	// (srl (ctlz x), 5) == 0 -> X != 0
				1958	// (srl (ctlz x), 5) != 1 -> X != 0
				1959	Cond = ISD::SETNE;
				1960	} else {
				1961	// (srl (ctlz x), 5) != 0 -> X == 0
				1962	// (srl (ctlz x), 5) == 1 -> X == 0
				1963	Cond = ISD::SETEQ;
				1964	}
				1965	SDValue Zero = DAG.getConstant(0, N0.getValueType());
				1966	return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
				1967	Zero, Cond);
				1968	}
				1969	}
				1970
Benjamin Kramer	d822892	2011-01-17 12:04:57 +0000	[diff] [blame]	1971	SDValue CTPOP = N0;
				1972	// Look through truncs that don't change the value of a ctpop.
				1973	if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
				1974	CTPOP = N0.getOperand(0);
				1975
				1976	if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramer	c9b6a3e	2011-01-17 18:00:28 +0000	[diff] [blame]	1977	(N0 == CTPOP \|\| N0.getValueType().getSizeInBits() >
Benjamin Kramer	d822892	2011-01-17 12:04:57 +0000	[diff] [blame]	1978	Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
				1979	EVT CTVT = CTPOP.getValueType();
				1980	SDValue CTOp = CTPOP.getOperand(0);
				1981
				1982	// (ctpop x) u< 2 -> (x & x-1) == 0
				1983	// (ctpop x) u> 1 -> (x & x-1) != 0
				1984	if ((Cond == ISD::SETULT && C1 == 2) \|\| (Cond == ISD::SETUGT && C1 == 1)){
				1985	SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
				1986	DAG.getConstant(1, CTVT));
				1987	SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
				1988	ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
				1989	return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
				1990	}
				1991
				1992	// TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
				1993	}
				1994
Benjamin Kramer	e7cf062	2011-04-22 18:47:44 +0000	[diff] [blame]	1995	// (zext x) == C --> x == (trunc C)
				1996	if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
				1997	(Cond == ISD::SETEQ \|\| Cond == ISD::SETNE)) {
				1998	unsigned MinBits = N0.getValueSizeInBits();
				1999	SDValue PreZExt;
				2000	if (N0->getOpcode() == ISD::ZERO_EXTEND) {
				2001	// ZExt
				2002	MinBits = N0->getOperand(0).getValueSizeInBits();
				2003	PreZExt = N0->getOperand(0);
				2004	} else if (N0->getOpcode() == ISD::AND) {
				2005	// DAGCombine turns costly ZExts into ANDs
				2006	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
				2007	if ((C->getAPIntValue()+1).isPowerOf2()) {
				2008	MinBits = C->getAPIntValue().countTrailingOnes();
				2009	PreZExt = N0->getOperand(0);
				2010	}
				2011	} else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
				2012	// ZEXTLOAD
				2013	if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
				2014	MinBits = LN0->getMemoryVT().getSizeInBits();
				2015	PreZExt = N0;
				2016	}
				2017	}
				2018
				2019	// Make sure we're not loosing bits from the constant.
				2020	if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
				2021	EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
				2022	if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
				2023	// Will get folded away.
				2024	SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
				2025	SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
				2026	return DAG.getSetCC(dl, VT, Trunc, C, Cond);
				2027	}
				2028	}
				2029	}
				2030
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2031	// If the LHS is '(and load, const)', the RHS is 0,
				2032	// the test is for equality or unsigned, and all 1 bits of the const are
				2033	// in the same partial word, see if we can shorten the load.
				2034	if (DCI.isBeforeLegalize() &&
				2035	N0.getOpcode() == ISD::AND && C1 == 0 &&
				2036	N0.getNode()->hasOneUse() &&
				2037	isa<LoadSDNode>(N0.getOperand(0)) &&
				2038	N0.getOperand(0).getNode()->hasOneUse() &&
				2039	isa<ConstantSDNode>(N0.getOperand(1))) {
				2040	LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2041	APInt bestMask;
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2042	unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2043	if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2044	unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2045	unsigned maskWidth = origWidth;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2046	// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2047	// 8 bits, but have to be careful...
				2048	if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
				2049	origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2050	const APInt &Mask =
				2051	cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2052	for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2053	APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2054	for (unsigned offset=0; offset<origWidth/width; offset++) {
				2055	if ((newMask & Mask) == Mask) {
				2056	if (!TD->isLittleEndian())
				2057	bestOffset = (origWidth/width - offset - 1) * (width/8);
				2058	else
				2059	bestOffset = (uint64_t)offset * (width/8);
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2060	bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2061	bestWidth = width;
				2062	break;
Dale Johannesen	89217a6	2008-11-07 01:28:02 +0000	[diff] [blame]	2063	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2064	newMask = newMask << width;
Dale Johannesen	89217a6	2008-11-07 01:28:02 +0000	[diff] [blame]	2065	}
				2066	}
				2067	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2068	if (bestWidth) {
Chris Lattner	c0c7fca	2011-04-14 04:12:47 +0000	[diff] [blame]	2069	EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2070	if (newVT.isRound()) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2071	EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2072	SDValue Ptr = Lod->getBasePtr();
				2073	if (bestOffset != 0)
				2074	Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
				2075	DAG.getConstant(bestOffset, PtrType));
				2076	unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
				2077	SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattner	ecf42c4	2010-09-21 16:36:31 +0000	[diff] [blame]	2078	Lod->getPointerInfo().getWithOffset(bestOffset),
Pete Cooper	d752e0f	2011-11-08 18:42:53 +0000	[diff] [blame]	2079	false, false, false, NewAlign);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2080	return DAG.getSetCC(dl, VT,
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2081	DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2082	DAG.getConstant(bestMask.trunc(bestWidth),
				2083	newVT)),
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2084	DAG.getConstant(0LL, newVT), Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2085	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2086	}
				2087	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2088
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2089	// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
				2090	if (N0.getOpcode() == ISD::ZERO_EXTEND) {
				2091	unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
				2092
				2093	// If the comparison constant has bits in the upper part, the
				2094	// zero-extended value could never match.
				2095	if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
				2096	C1.getBitWidth() - InSize))) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2097	switch (Cond) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2098	case ISD::SETUGT:
				2099	case ISD::SETUGE:
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2100	case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2101	case ISD::SETULT:
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2102	case ISD::SETULE:
				2103	case ISD::SETNE: return DAG.getConstant(1, VT);
				2104	case ISD::SETGT:
				2105	case ISD::SETGE:
				2106	// True if the sign bit of C1 is set.
				2107	return DAG.getConstant(C1.isNegative(), VT);
				2108	case ISD::SETLT:
				2109	case ISD::SETLE:
				2110	// True if the sign bit of C1 isn't set.
				2111	return DAG.getConstant(C1.isNonNegative(), VT);
				2112	default:
Jakob Stoklund Olesen	78d1264	2009-07-24 18:22:59 +0000	[diff] [blame]	2113	break;
				2114	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2115	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2116
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2117	// Otherwise, we can perform the comparison with the low bits.
				2118	switch (Cond) {
				2119	case ISD::SETEQ:
				2120	case ISD::SETNE:
				2121	case ISD::SETUGT:
				2122	case ISD::SETUGE:
				2123	case ISD::SETULT:
				2124	case ISD::SETULE: {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2125	EVT newVT = N0.getOperand(0).getValueType();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2126	if (DCI.isBeforeLegalizeOps() \|\|
				2127	(isOperationLegal(ISD::SETCC, newVT) &&
				2128	getCondCodeAction(Cond, newVT)==Legal))
				2129	return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad	40f8f62	2010-12-07 08:25:19 +0000	[diff] [blame]	2130	DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2131	Cond);
				2132	break;
				2133	}
				2134	default:
				2135	break; // todo, be more careful with signed comparisons
				2136	}
				2137	} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2138	(Cond == ISD::SETEQ \|\| Cond == ISD::SETNE)) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2139	EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2140	unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2141	EVT ExtDstTy = N0.getValueType();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2142	unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
				2143
Eli Friedman	ad78a88	2010-07-30 06:44:31 +0000	[diff] [blame]	2144	// If the constant doesn't fit into the number of bits for the source of
				2145	// the sign extension, it is impossible for both sides to be equal.
				2146	if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2147	return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2148
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2149	SDValue ZextOp;
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2150	EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2151	if (Op0Ty == ExtSrcTy) {
				2152	ZextOp = N0.getOperand(0);
				2153	} else {
				2154	APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
				2155	ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
				2156	DAG.getConstant(Imm, Op0Ty));
				2157	}
				2158	if (!DCI.isCalledByLegalizer())
				2159	DCI.AddToWorklist(ZextOp.getNode());
				2160	// Otherwise, make this a use of a zext.
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2161	return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2162	DAG.getConstant(C1 & APInt::getLowBitsSet(
				2163	ExtDstTyBits,
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2164	ExtSrcTyBits),
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2165	ExtDstTy),
				2166	Cond);
				2167	} else if ((N1C->isNullValue() \|\| N1C->getAPIntValue() == 1) &&
				2168	(Cond == ISD::SETEQ \|\| Cond == ISD::SETNE)) {
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2169	// SETCC (SETCC), [0\|1], [EQ\|NE] -> SETCC
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2170	if (N0.getOpcode() == ISD::SETCC &&
				2171	isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2172	bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2173	if (TrueWhenTrue)
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2174	return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2175	// Invert the condition.
				2176	ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2177	CC = ISD::getSetCCInverse(CC,
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2178	N0.getOperand(0).getValueType().isInteger());
				2179	return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2180	}
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2181
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2182	if ((N0.getOpcode() == ISD::XOR \|\|
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2183	(N0.getOpcode() == ISD::AND &&
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2184	N0.getOperand(0).getOpcode() == ISD::XOR &&
				2185	N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
				2186	isa<ConstantSDNode>(N0.getOperand(1)) &&
				2187	cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
				2188	// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
				2189	// can only do this if the top bits are known zero.
				2190	unsigned BitWidth = N0.getValueSizeInBits();
				2191	if (DAG.MaskedValueIsZero(N0,
				2192	APInt::getHighBitsSet(BitWidth,
				2193	BitWidth-1))) {
				2194	// Okay, get the un-inverted input value.
				2195	SDValue Val;
				2196	if (N0.getOpcode() == ISD::XOR)
				2197	Val = N0.getOperand(0);
				2198	else {
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2199	assert(N0.getOpcode() == ISD::AND &&
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2200	N0.getOperand(0).getOpcode() == ISD::XOR);
				2201	// ((X^1)&1)^1 -> X & 1
				2202	Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
				2203	N0.getOperand(0).getOperand(0),
				2204	N0.getOperand(1));
				2205	}
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2206
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2207	return DAG.getSetCC(dl, VT, Val, N1,
				2208	Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
				2209	}
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2210	} else if (N1C->getAPIntValue() == 1 &&
				2211	(VT == MVT::i1 \|\|
Duncan Sands	28b77e9	2011-09-06 19:07:46 +0000	[diff] [blame]	2212	getBooleanContents(false) == ZeroOrOneBooleanContent)) {
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2213	SDValue Op0 = N0;
				2214	if (Op0.getOpcode() == ISD::TRUNCATE)
				2215	Op0 = Op0.getOperand(0);
				2216
				2217	if ((Op0.getOpcode() == ISD::XOR) &&
				2218	Op0.getOperand(0).getOpcode() == ISD::SETCC &&
				2219	Op0.getOperand(1).getOpcode() == ISD::SETCC) {
				2220	// (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
				2221	Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
				2222	return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
				2223	Cond);
				2224	} else if (Op0.getOpcode() == ISD::AND &&
				2225	isa<ConstantSDNode>(Op0.getOperand(1)) &&
				2226	cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
				2227	// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov	17458a7	2010-05-01 12:52:34 +0000	[diff] [blame]	2228	if (Op0.getValueType().bitsGT(VT))
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2229	Op0 = DAG.getNode(ISD::AND, dl, VT,
				2230	DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
				2231	DAG.getConstant(1, VT));
Anton Korobeynikov	17458a7	2010-05-01 12:52:34 +0000	[diff] [blame]	2232	else if (Op0.getValueType().bitsLT(VT))
				2233	Op0 = DAG.getNode(ISD::AND, dl, VT,
				2234	DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
				2235	DAG.getConstant(1, VT));
				2236
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2237	return DAG.getSetCC(dl, VT, Op0,
				2238	DAG.getConstant(0, Op0.getValueType()),
				2239	Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
				2240	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2241	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2242	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2243
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2244	APInt MinVal, MaxVal;
				2245	unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
				2246	if (ISD::isSignedIntSetCC(Cond)) {
				2247	MinVal = APInt::getSignedMinValue(OperandBitSize);
				2248	MaxVal = APInt::getSignedMaxValue(OperandBitSize);
				2249	} else {
				2250	MinVal = APInt::getMinValue(OperandBitSize);
				2251	MaxVal = APInt::getMaxValue(OperandBitSize);
				2252	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2253
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2254	// Canonicalize GE/LE comparisons to use GT/LT comparisons.
				2255	if (Cond == ISD::SETGE \|\| Cond == ISD::SETUGE) {
				2256	if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
				2257	// X >= C0 --> X > (C0-1)
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2258	return DAG.getSetCC(dl, VT, N0,
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2259	DAG.getConstant(C1-1, N1.getValueType()),
				2260	(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
				2261	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2262
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2263	if (Cond == ISD::SETLE \|\| Cond == ISD::SETULE) {
				2264	if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
				2265	// X <= C0 --> X < (C0+1)
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2266	return DAG.getSetCC(dl, VT, N0,
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2267	DAG.getConstant(C1+1, N1.getValueType()),
				2268	(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
				2269	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2270
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2271	if ((Cond == ISD::SETLT \|\| Cond == ISD::SETULT) && C1 == MinVal)
				2272	return DAG.getConstant(0, VT); // X < MIN --> false
				2273	if ((Cond == ISD::SETGE \|\| Cond == ISD::SETUGE) && C1 == MinVal)
				2274	return DAG.getConstant(1, VT); // X >= MIN --> true
				2275	if ((Cond == ISD::SETGT \|\| Cond == ISD::SETUGT) && C1 == MaxVal)
				2276	return DAG.getConstant(0, VT); // X > MAX --> false
				2277	if ((Cond == ISD::SETLE \|\| Cond == ISD::SETULE) && C1 == MaxVal)
				2278	return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2279
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2280	// Canonicalize setgt X, Min --> setne X, Min
				2281	if ((Cond == ISD::SETGT \|\| Cond == ISD::SETUGT) && C1 == MinVal)
				2282	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
				2283	// Canonicalize setlt X, Max --> setne X, Max
				2284	if ((Cond == ISD::SETLT \|\| Cond == ISD::SETULT) && C1 == MaxVal)
				2285	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2286
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2287	// If we have setult X, 1, turn it into seteq X, 0
				2288	if ((Cond == ISD::SETLT \|\| Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2289	return DAG.getSetCC(dl, VT, N0,
				2290	DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2291	ISD::SETEQ);
				2292	// If we have setugt X, Max-1, turn it into seteq X, Max
				2293	else if ((Cond == ISD::SETGT \|\| Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2294	return DAG.getSetCC(dl, VT, N0,
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2295	DAG.getConstant(MaxVal, N0.getValueType()),
				2296	ISD::SETEQ);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2297
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2298	// If we have "setcc X, C0", check to see if we can shrink the immediate
				2299	// by changing cc.
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2300
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2301	// SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2302	if (Cond == ISD::SETUGT &&
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2303	C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2304	return DAG.getSetCC(dl, VT, N0,
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2305	DAG.getConstant(0, N1.getValueType()),
				2306	ISD::SETLT);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2307
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2308	// SETULT X, SINTMIN -> SETGT X, -1
				2309	if (Cond == ISD::SETULT &&
				2310	C1 == APInt::getSignedMinValue(OperandBitSize)) {
				2311	SDValue ConstMinusOne =
				2312	DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
				2313	N1.getValueType());
				2314	return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
				2315	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2316
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2317	// Fold bit comparisons when we can.
				2318	if ((Cond == ISD::SETEQ \|\| Cond == ISD::SETNE) &&
Evan Cheng	d40d03e	2010-01-06 19:38:29 +0000	[diff] [blame]	2319	(VT == N0.getValueType() \|\|
				2320	(isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
				2321	N0.getOpcode() == ISD::AND)
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2322	if (ConstantSDNode *AndRHS =
				2323	dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2324	EVT ShiftTy = DCI.isBeforeLegalize() ?
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	2325	getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2326	if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
				2327	// Perform the xform if the AND RHS is a single bit.
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2328	if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Cheng	d40d03e	2010-01-06 19:38:29 +0000	[diff] [blame]	2329	return DAG.getNode(ISD::TRUNCATE, dl, VT,
				2330	DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2331	DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2332	}
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2333	} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2334	// (X & 8) == 8 --> (X & 8) >> 3
				2335	// Perform the xform if C1 is a single bit.
				2336	if (C1.isPowerOf2()) {
Evan Cheng	d40d03e	2010-01-06 19:38:29 +0000	[diff] [blame]	2337	return DAG.getNode(ISD::TRUNCATE, dl, VT,
				2338	DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
				2339	DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2340	}
				2341	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2342	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2343	}
				2344
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2345	if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2346	// Constant fold or commute setcc.
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2347	SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2348	if (O.getNode()) return O;
				2349	} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner	63079f0	2007-12-29 08:37:08 +0000	[diff] [blame]	2350	// If the RHS of an FP comparison is a constant, simplify it away in
				2351	// some cases.
				2352	if (CFP->getValueAPF().isNaN()) {
				2353	// If an operand is known to be a nan, we can fold it.
				2354	switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwin	c23197a	2009-07-14 16:55:14 +0000	[diff] [blame]	2355	default: llvm_unreachable("Unknown flavor!");
Chris Lattner	63079f0	2007-12-29 08:37:08 +0000	[diff] [blame]	2356	case 0: // Known false.
				2357	return DAG.getConstant(0, VT);
				2358	case 1: // Known true.
				2359	return DAG.getConstant(1, VT);
Chris Lattner	1c3e1e2	2007-12-30 21:21:10 +0000	[diff] [blame]	2360	case 2: // Undefined.
Dale Johannesen	e8d7230	2009-02-06 23:05:02 +0000	[diff] [blame]	2361	return DAG.getUNDEF(VT);
Chris Lattner	63079f0	2007-12-29 08:37:08 +0000	[diff] [blame]	2362	}
				2363	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2364
Chris Lattner	63079f0	2007-12-29 08:37:08 +0000	[diff] [blame]	2365	// Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
				2366	// constant if knowing that the operand is non-nan is enough. We prefer to
				2367	// have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
				2368	// materialize 0.0.
				2369	if (Cond == ISD::SETO \|\| Cond == ISD::SETUO)
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2370	return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman	11eab02	2009-09-26 15:24:17 +0000	[diff] [blame]	2371
				2372	// If the condition is not legal, see if we can find an equivalent one
				2373	// which is legal.
				2374	if (!isCondCodeLegal(Cond, N0.getValueType())) {
				2375	// If the comparison was an awkward floating-point == or != and one of
				2376	// the comparison operands is infinity or negative infinity, convert the
				2377	// condition to a less-awkward <= or >=.
				2378	if (CFP->getValueAPF().isInfinity()) {
				2379	if (CFP->getValueAPF().isNegative()) {
				2380	if (Cond == ISD::SETOEQ &&
				2381	isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
				2382	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
				2383	if (Cond == ISD::SETUEQ &&
				2384	isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
				2385	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
				2386	if (Cond == ISD::SETUNE &&
				2387	isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
				2388	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
				2389	if (Cond == ISD::SETONE &&
				2390	isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
				2391	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
				2392	} else {
				2393	if (Cond == ISD::SETOEQ &&
				2394	isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
				2395	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
				2396	if (Cond == ISD::SETUEQ &&
				2397	isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
				2398	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
				2399	if (Cond == ISD::SETUNE &&
				2400	isCondCodeLegal(ISD::SETULT, N0.getValueType()))
				2401	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
				2402	if (Cond == ISD::SETONE &&
				2403	isCondCodeLegal(ISD::SETULT, N0.getValueType()))
				2404	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
				2405	}
				2406	}
				2407	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2408	}
				2409
				2410	if (N0 == N1) {
				2411	// We can always fold X == X for integer setcc's.
Chad Rosier	9dbb018	2012-04-03 20:11:24 +0000	[diff] [blame]	2412	if (N0.getValueType().isInteger()) {
				2413	switch (getBooleanContents(N0.getValueType().isVector())) {
Chad Rosier	9dbb018	2012-04-03 20:11:24 +0000	[diff] [blame]	2414	case UndefinedBooleanContent:
				2415	case ZeroOrOneBooleanContent:
				2416	return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
				2417	case ZeroOrNegativeOneBooleanContent:
				2418	return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
				2419	}
				2420	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2421	unsigned UOF = ISD::getUnorderedFlavor(Cond);
				2422	if (UOF == 2) // FP operators that are undefined on NaNs.
				2423	return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
				2424	if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
				2425	return DAG.getConstant(UOF, VT);
				2426	// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
				2427	// if it is not already.
				2428	ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
				2429	if (NewCond != Cond)
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2430	return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2431	}
				2432
				2433	if ((Cond == ISD::SETEQ \|\| Cond == ISD::SETNE) &&
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	2434	N0.getValueType().isInteger()) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2435	if (N0.getOpcode() == ISD::ADD \|\| N0.getOpcode() == ISD::SUB \|\|
				2436	N0.getOpcode() == ISD::XOR) {
				2437	// Simplify (X+Y) == (X+Z) --> Y == Z
				2438	if (N0.getOpcode() == N1.getOpcode()) {
				2439	if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2440	return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2441	if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2442	return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2443	if (DAG.isCommutativeBinOp(N0.getOpcode())) {
				2444	// If X op Y == Y op X, try other combinations.
				2445	if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2446	return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2447	Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2448	if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2449	return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2450	Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2451	}
				2452	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2453
Jakob Stoklund Olesen	740cd65	2012-04-05 20:30:20 +0000	[diff] [blame]	2454	// If RHS is a legal immediate value for a compare instruction, we need
				2455	// to be careful about increasing register pressure needlessly.
				2456	bool LegalRHSImm = false;
				2457
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2458	if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
				2459	if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
				2460	// Turn (X+C1) == C2 --> X == C2-C1
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2461	if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2462	return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	2463	DAG.getConstant(RHSC->getAPIntValue()-
				2464	LHSR->getAPIntValue(),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2465	N0.getValueType()), Cond);
				2466	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2467
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2468	// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
				2469	if (N0.getOpcode() == ISD::XOR)
				2470	// If we know that all of the inverted bits are zero, don't bother
				2471	// performing the inversion.
Dan Gohman	2e68b6f	2008-02-25 21:11:39 +0000	[diff] [blame]	2472	if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
				2473	return
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2474	DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman	2e68b6f	2008-02-25 21:11:39 +0000	[diff] [blame]	2475	DAG.getConstant(LHSR->getAPIntValue() ^
				2476	RHSC->getAPIntValue(),
				2477	N0.getValueType()),
				2478	Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2479	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2480
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2481	// Turn (C1-X) == C2 --> X == C1-C2
				2482	if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2483	if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman	2e68b6f	2008-02-25 21:11:39 +0000	[diff] [blame]	2484	return
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2485	DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman	2e68b6f	2008-02-25 21:11:39 +0000	[diff] [blame]	2486	DAG.getConstant(SUBC->getAPIntValue() -
				2487	RHSC->getAPIntValue(),
				2488	N0.getValueType()),
				2489	Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2490	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2491	}
Jakob Stoklund Olesen	740cd65	2012-04-05 20:30:20 +0000	[diff] [blame]	2492
				2493	// Could RHSC fold directly into a compare?
				2494	if (RHSC->getValueType(0).getSizeInBits() <= 64)
				2495	LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2496	}
				2497
				2498	// Simplify (X+Z) == X --> Z == 0
Jakob Stoklund Olesen	740cd65	2012-04-05 20:30:20 +0000	[diff] [blame]	2499	// Don't do this if X is an immediate that can fold into a cmp
				2500	// instruction and X+Z has other uses. It could be an induction variable
				2501	// chain, and the transform would increase register pressure.
				2502	if (!LegalRHSImm \|\| N0.getNode()->hasOneUse()) {
				2503	if (N0.getOperand(0) == N1)
				2504	return DAG.getSetCC(dl, VT, N0.getOperand(1),
				2505	DAG.getConstant(0, N0.getValueType()), Cond);
				2506	if (N0.getOperand(1) == N1) {
				2507	if (DAG.isCommutativeBinOp(N0.getOpcode()))
				2508	return DAG.getSetCC(dl, VT, N0.getOperand(0),
				2509	DAG.getConstant(0, N0.getValueType()), Cond);
				2510	else if (N0.getNode()->hasOneUse()) {
				2511	assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
				2512	// (Z-X) == X --> Z == X<<1
				2513	SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	2514	DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Jakob Stoklund Olesen	740cd65	2012-04-05 20:30:20 +0000	[diff] [blame]	2515	if (!DCI.isCalledByLegalizer())
				2516	DCI.AddToWorklist(SH.getNode());
				2517	return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
				2518	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2519	}
				2520	}
				2521	}
				2522
				2523	if (N1.getOpcode() == ISD::ADD \|\| N1.getOpcode() == ISD::SUB \|\|
				2524	N1.getOpcode() == ISD::XOR) {
				2525	// Simplify X == (X+Z) --> Z == 0
				2526	if (N1.getOperand(0) == N0) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2527	return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2528	DAG.getConstant(0, N1.getValueType()), Cond);
				2529	} else if (N1.getOperand(1) == N0) {
				2530	if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2531	return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2532	DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2533	} else if (N1.getNode()->hasOneUse()) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2534	assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
				2535	// X == (Z-X) --> X<<1 == Z
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2536	SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	2537	DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2538	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2539	DCI.AddToWorklist(SH.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2540	return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2541	}
				2542	}
				2543	}
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2544
Dan Gohman	2c65c3d	2009-01-29 16:18:12 +0000	[diff] [blame]	2545	// Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	2546	// Note that where y is variable and is known to have at most
				2547	// one bit set (for example, if it is z&1) we cannot do this;
				2548	// the expressions are not equivalent when y==0.
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2549	if (N0.getOpcode() == ISD::AND)
				2550	if (N0.getOperand(0) == N1 \|\| N0.getOperand(1) == N1) {
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	2551	if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2552	Cond = ISD::getSetCCInverse(Cond, /isInteger=/true);
				2553	SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2554	return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2555	}
				2556	}
				2557	if (N1.getOpcode() == ISD::AND)
				2558	if (N1.getOperand(0) == N0 \|\| N1.getOperand(1) == N0) {
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	2559	if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2560	Cond = ISD::getSetCCInverse(Cond, /isInteger=/true);
				2561	SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2562	return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2563	}
				2564	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2565	}
				2566
				2567	// Fold away ALL boolean setcc's.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2568	SDValue Temp;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2569	if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2570	switch (Cond) {
Torok Edwin	c23197a	2009-07-14 16:55:14 +0000	[diff] [blame]	2571	default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2572	case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2573	Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
				2574	N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2575	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2576	DCI.AddToWorklist(Temp.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2577	break;
				2578	case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2579	N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2580	break;
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2581	case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
				2582	case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2583	Temp = DAG.getNOT(dl, N0, MVT::i1);
				2584	N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2585	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2586	DCI.AddToWorklist(Temp.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2587	break;
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2588	case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
				2589	case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2590	Temp = DAG.getNOT(dl, N1, MVT::i1);
				2591	N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2592	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2593	DCI.AddToWorklist(Temp.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2594	break;
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2595	case ISD::SETULE: // X <=u Y --> X == 0 \| Y == 1 --> ~X \| Y
				2596	case ISD::SETGE: // X >=s Y --> X == 0 \| Y == 1 --> ~X \| Y
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2597	Temp = DAG.getNOT(dl, N0, MVT::i1);
				2598	N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2599	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2600	DCI.AddToWorklist(Temp.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2601	break;
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2602	case ISD::SETUGE: // X >=u Y --> X == 1 \| Y == 0 --> ~Y \| X
				2603	case ISD::SETLE: // X <=s Y --> X == 1 \| Y == 0 --> ~Y \| X
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2604	Temp = DAG.getNOT(dl, N1, MVT::i1);
				2605	N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2606	break;
				2607	}
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2608	if (VT != MVT::i1) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2609	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2610	DCI.AddToWorklist(N0.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2611	// FIXME: If running after legalize, we probably can't do this.
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2612	N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2613	}
				2614	return N0;
				2615	}
				2616
				2617	// Could not fold it.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2618	return SDValue();
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2619	}
				2620
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2621	/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
				2622	/// node is a GlobalAddress + offset.
Chris Lattner	0a9481f	2011-02-13 22:25:43 +0000	[diff] [blame]	2623	bool TargetLowering::isGAPlusOffset(SDNode N, const GlobalValue &GA,
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2624	int64_t &Offset) const {
				2625	if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman	9ea3f56	2008-06-09 22:05:52 +0000	[diff] [blame]	2626	GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
				2627	GA = GASD->getGlobal();
				2628	Offset += GASD->getOffset();
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2629	return true;
				2630	}
				2631
				2632	if (N->getOpcode() == ISD::ADD) {
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2633	SDValue N1 = N->getOperand(0);
				2634	SDValue N2 = N->getOperand(1);
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2635	if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2636	ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
				2637	if (V) {
Dan Gohman	7810bfe	2008-09-26 21:54:37 +0000	[diff] [blame]	2638	Offset += V->getSExtValue();
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2639	return true;
				2640	}
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2641	} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2642	ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
				2643	if (V) {
Dan Gohman	7810bfe	2008-09-26 21:54:37 +0000	[diff] [blame]	2644	Offset += V->getSExtValue();
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2645	return true;
				2646	}
				2647	}
				2648	}
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	2649
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2650	return false;
				2651	}
				2652
				2653
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2654	SDValue TargetLowering::
Chris Lattner	00ffed0	2006-03-01 04:52:55 +0000	[diff] [blame]	2655	PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
				2656	// Default implementation: no optimization.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2657	return SDValue();
Chris Lattner	00ffed0	2006-03-01 04:52:55 +0000	[diff] [blame]	2658	}
				2659
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2660	//===----------------------------------------------------------------------===//
				2661	// Inline Assembler Implementation Methods
				2662	//===----------------------------------------------------------------------===//
				2663
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2664
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2665	TargetLowering::ConstraintType
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2666	TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2667	if (Constraint.size() == 1) {
				2668	switch (Constraint[0]) {
				2669	default: break;
				2670	case 'r': return C_RegisterClass;
				2671	case 'm': // memory
				2672	case 'o': // offsetable
				2673	case 'V': // not offsetable
				2674	return C_Memory;
				2675	case 'i': // Simple Integer or Relocatable Constant
				2676	case 'n': // Simple Integer
John Thompson	67aff16	2010-09-21 22:04:54 +0000	[diff] [blame]	2677	case 'E': // Floating Point Constant
				2678	case 'F': // Floating Point Constant
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2679	case 's': // Relocatable Constant
John Thompson	67aff16	2010-09-21 22:04:54 +0000	[diff] [blame]	2680	case 'p': // Address.
Chris Lattner	c13dd1c	2007-03-25 04:35:41 +0000	[diff] [blame]	2681	case 'X': // Allow ANY value.
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2682	case 'I': // Target registers.
				2683	case 'J':
				2684	case 'K':
				2685	case 'L':
				2686	case 'M':
				2687	case 'N':
				2688	case 'O':
				2689	case 'P':
John Thompson	67aff16	2010-09-21 22:04:54 +0000	[diff] [blame]	2690	case '<':
				2691	case '>':
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2692	return C_Other;
				2693	}
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2694	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2695
				2696	if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner	065421f	2007-03-25 02:18:14 +0000	[diff] [blame]	2697	Constraint[Constraint.size()-1] == '}')
				2698	return C_Register;
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2699	return C_Unknown;
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2700	}
				2701
Dale Johannesen	ba2a0b9	2008-01-29 02:21:21 +0000	[diff] [blame]	2702	/// LowerXConstraint - try to replace an X constraint, which matches anything,
				2703	/// with another that has more specific requirements based on the type of the
				2704	/// corresponding operand.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2705	const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	2706	if (ConstraintVT.isInteger())
Chris Lattner	5e76423	2008-04-26 23:02:14 +0000	[diff] [blame]	2707	return "r";
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	2708	if (ConstraintVT.isFloatingPoint())
Chris Lattner	5e76423	2008-04-26 23:02:14 +0000	[diff] [blame]	2709	return "f"; // works for many targets
				2710	return 0;
Dale Johannesen	ba2a0b9	2008-01-29 02:21:21 +0000	[diff] [blame]	2711	}
				2712
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2713	/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
				2714	/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2715	void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher	100c833	2011-06-02 23:16:42 +0000	[diff] [blame]	2716	std::string &Constraint,
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2717	std::vector<SDValue> &Ops,
Chris Lattner	5e76423	2008-04-26 23:02:14 +0000	[diff] [blame]	2718	SelectionDAG &DAG) const {
Eric Christopher	362fee9	2011-06-17 20:41:29 +0000	[diff] [blame]	2719
Eric Christopher	100c833	2011-06-02 23:16:42 +0000	[diff] [blame]	2720	if (Constraint.length() > 1) return;
Eric Christopher	362fee9	2011-06-17 20:41:29 +0000	[diff] [blame]	2721
Eric Christopher	100c833	2011-06-02 23:16:42 +0000	[diff] [blame]	2722	char ConstraintLetter = Constraint[0];
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2723	switch (ConstraintLetter) {
Chris Lattner	9ff6ee8	2007-02-17 06:00:35 +0000	[diff] [blame]	2724	default: break;
Dale Johannesen	eb57ea7	2007-11-05 21:20:28 +0000	[diff] [blame]	2725	case 'X': // Allows any operand; labels (basic block) use this.
				2726	if (Op.getOpcode() == ISD::BasicBlock) {
				2727	Ops.push_back(Op);
				2728	return;
				2729	}
				2730	// fall through
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2731	case 'i': // Simple Integer or Relocatable Constant
				2732	case 'n': // Simple Integer
Dale Johannesen	eb57ea7	2007-11-05 21:20:28 +0000	[diff] [blame]	2733	case 's': { // Relocatable Constant
Chris Lattner	75c7d2b	2007-05-03 16:54:34 +0000	[diff] [blame]	2734	// These operands are interested in values of the form (GV+C), where C may
				2735	// be folded in as an offset of GV, or it may be explicitly added. Also, it
				2736	// is possible and fine if either GV or C are missing.
				2737	ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
				2738	GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2739
Chris Lattner	75c7d2b	2007-05-03 16:54:34 +0000	[diff] [blame]	2740	// If we have "(add GV, C)", pull out GV/C
				2741	if (Op.getOpcode() == ISD::ADD) {
				2742	C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
				2743	GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
				2744	if (C == 0 \|\| GA == 0) {
				2745	C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
				2746	GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
				2747	}
				2748	if (C == 0 \|\| GA == 0)
				2749	C = 0, GA = 0;
				2750	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2751
Chris Lattner	75c7d2b	2007-05-03 16:54:34 +0000	[diff] [blame]	2752	// If we find a valid operand, map to the TargetXXX version so that the
				2753	// value itself doesn't get selected.
				2754	if (GA) { // Either &GV or &GV+C
				2755	if (ConstraintLetter != 'n') {
				2756	int64_t Offs = GA->getOffset();
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	2757	if (C) Offs += C->getZExtValue();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2758	Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel	07538ad	2010-07-15 18:45:27 +0000	[diff] [blame]	2759	C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2760	Op.getValueType(), Offs));
				2761	return;
Chris Lattner	75c7d2b	2007-05-03 16:54:34 +0000	[diff] [blame]	2762	}
				2763	}
				2764	if (C) { // just C, no GV.
Chris Lattner	9ff6ee8	2007-02-17 06:00:35 +0000	[diff] [blame]	2765	// Simple constants are not allowed for 's'.
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2766	if (ConstraintLetter != 's') {
Dale Johannesen	78e3e52	2009-02-12 20:58:09 +0000	[diff] [blame]	2767	// gcc prints these as sign extended. Sign extend value to 64 bits
				2768	// now; without this it would get ZExt'd later in
				2769	// ScheduleDAGSDNodes::EmitNode, which is very generic.
				2770	Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2771	MVT::i64));
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2772	return;
				2773	}
Chris Lattner	9ff6ee8	2007-02-17 06:00:35 +0000	[diff] [blame]	2774	}
Chris Lattner	9ff6ee8	2007-02-17 06:00:35 +0000	[diff] [blame]	2775	break;
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2776	}
Chris Lattner	75c7d2b	2007-05-03 16:54:34 +0000	[diff] [blame]	2777	}
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2778	}
				2779
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2780	std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner	4217ca8dc	2006-02-21 23:11:00 +0000	[diff] [blame]	2781	getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2782	EVT VT) const {
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2783	if (Constraint[0] != '{')
Douglas Gregor	7d9663c	2010-05-11 06:17:44 +0000	[diff] [blame]	2784	return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattner	a55079a	2006-02-01 01:29:47 +0000	[diff] [blame]	2785	assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
				2786
				2787	// Remove the braces from around the name.
Benjamin Kramer	05872ea	2009-11-12 20:36:59 +0000	[diff] [blame]	2788	StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2789
				2790	// Figure out which register class contains this reg.
Dan Gohman	6f0d024	2008-02-10 18:45:23 +0000	[diff] [blame]	2791	const TargetRegisterInfo *RI = TM.getRegisterInfo();
				2792	for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2793	E = RI->regclass_end(); RCI != E; ++RCI) {
				2794	const TargetRegisterClass RC = RCI;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2795
				2796	// If none of the value types for this register class are valid, we
Chris Lattner	b3befd4	2006-02-22 23:00:51 +0000	[diff] [blame]	2797	// can't use it. For example, 64-bit reg classes on 32-bit targets.
Jakob Stoklund Olesen	22e8a36	2011-10-12 01:24:51 +0000	[diff] [blame]	2798	if (!isLegalRC(RC))
				2799	continue;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2800
				2801	for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2802	I != E; ++I) {
Benjamin Kramer	05872ea	2009-11-12 20:36:59 +0000	[diff] [blame]	2803	if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2804	return std::make_pair(*I, RC);
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2805	}
Chris Lattner	4ccb070	2006-01-26 20:37:03 +0000	[diff] [blame]	2806	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2807
Douglas Gregor	7d9663c	2010-05-11 06:17:44 +0000	[diff] [blame]	2808	return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner	4ccb070	2006-01-26 20:37:03 +0000	[diff] [blame]	2809	}
Evan Cheng	30b37b5	2006-03-13 23:18:16 +0000	[diff] [blame]	2810
				2811	//===----------------------------------------------------------------------===//
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2812	// Constraint Selection.
				2813
Chris Lattner	6bdcda3	2008-10-17 16:47:46 +0000	[diff] [blame]	2814	/// isMatchingInputConstraint - Return true of this is an input operand that is
				2815	/// a matching constraint like "4".
				2816	bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner	58f15c4	2008-10-17 16:21:11 +0000	[diff] [blame]	2817	assert(!ConstraintCode.empty() && "No known constraint!");
				2818	return isdigit(ConstraintCode[0]);
				2819	}
				2820
				2821	/// getMatchedOperand - If this is an input matching constraint, this method
				2822	/// returns the output operand it matches.
				2823	unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
				2824	assert(!ConstraintCode.empty() && "No known constraint!");
				2825	return atoi(ConstraintCode.c_str());
				2826	}
				2827
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2828
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2829	/// ParseConstraints - Split up the constraint string from the inline
				2830	/// assembly value into the specific constraints and their prefixes,
				2831	/// and also tie in the associated operand values.
				2832	/// If this returns an empty vector, and if the constraint string itself
				2833	/// isn't empty, there was an error parsing.
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2834	TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2835	ImmutableCallSite CS) const {
				2836	/// ConstraintOperands - Information about all of the constraints.
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2837	AsmOperandInfoVector ConstraintOperands;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2838	const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson	67aff16	2010-09-21 22:04:54 +0000	[diff] [blame]	2839	unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2840
				2841	// Do a prepass over the constraints, canonicalizing them, and building up the
				2842	// ConstraintOperands list.
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2843	InlineAsm::ConstraintInfoVector
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2844	ConstraintInfos = IA->ParseConstraints();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2845
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2846	unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
				2847	unsigned ResNo = 0; // ResNo - The result number of the next output.
				2848
				2849	for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
				2850	ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
				2851	AsmOperandInfo &OpInfo = ConstraintOperands.back();
				2852
John Thompson	67aff16	2010-09-21 22:04:54 +0000	[diff] [blame]	2853	// Update multiple alternative constraint count.
				2854	if (OpInfo.multipleAlternatives.size() > maCount)
				2855	maCount = OpInfo.multipleAlternatives.size();
				2856
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2857	OpInfo.ConstraintVT = MVT::Other;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2858
				2859	// Compute the value type for each operand.
				2860	switch (OpInfo.Type) {
				2861	case InlineAsm::isOutput:
				2862	// Indirect outputs just consume an argument.
				2863	if (OpInfo.isIndirect) {
				2864	OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
				2865	break;
				2866	}
				2867
				2868	// The return value of the call is this value. As such, there is no
				2869	// corresponding argument.
				2870	assert(!CS.getType()->isVoidTy() &&
				2871	"Bad inline asm!");
Chris Lattner	db125cf	2011-07-18 04:54:35 +0000	[diff] [blame]	2872	if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2873	OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2874	} else {
				2875	assert(ResNo == 0 && "Asm only has one result!");
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2876	OpInfo.ConstraintVT = getValueType(CS.getType());
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2877	}
				2878	++ResNo;
				2879	break;
				2880	case InlineAsm::isInput:
				2881	OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
				2882	break;
				2883	case InlineAsm::isClobber:
				2884	// Nothing to do.
				2885	break;
				2886	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2887
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2888	if (OpInfo.CallOperandVal) {
Chris Lattner	db125cf	2011-07-18 04:54:35 +0000	[diff] [blame]	2889	llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2890	if (OpInfo.isIndirect) {
Chris Lattner	db125cf	2011-07-18 04:54:35 +0000	[diff] [blame]	2891	llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2892	if (!PtrTy)
				2893	report_fatal_error("Indirect operand for inline asm not a pointer!");
				2894	OpTy = PtrTy->getElementType();
				2895	}
Eric Christopher	362fee9	2011-06-17 20:41:29 +0000	[diff] [blame]	2896
Eric Christopher	cef81b7	2011-05-09 20:04:43 +0000	[diff] [blame]	2897	// Look for vector wrapped in a struct. e.g. { <16 x i8> }.
Chris Lattner	db125cf	2011-07-18 04:54:35 +0000	[diff] [blame]	2898	if (StructType *STy = dyn_cast<StructType>(OpTy))
Eric Christopher	cef81b7	2011-05-09 20:04:43 +0000	[diff] [blame]	2899	if (STy->getNumElements() == 1)
				2900	OpTy = STy->getElementType(0);
				2901
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2902	// If OpTy is not a single value, it may be a struct/union that we
				2903	// can tile with integers.
				2904	if (!OpTy->isSingleValueType() && OpTy->isSized()) {
				2905	unsigned BitSize = TD->getTypeSizeInBits(OpTy);
				2906	switch (BitSize) {
				2907	default: break;
				2908	case 1:
				2909	case 8:
				2910	case 16:
				2911	case 32:
				2912	case 64:
				2913	case 128:
Dale Johannesen	71365d3	2010-11-09 01:15:07 +0000	[diff] [blame]	2914	OpInfo.ConstraintVT =
				2915	EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2916	break;
				2917	}
				2918	} else if (dyn_cast<PointerType>(OpTy)) {
				2919	OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
				2920	} else {
				2921	OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
				2922	}
				2923	}
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2924	}
				2925
				2926	// If we have multiple alternative constraints, select the best alternative.
				2927	if (ConstraintInfos.size()) {
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2928	if (maCount) {
				2929	unsigned bestMAIndex = 0;
				2930	int bestWeight = -1;
				2931	// weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
				2932	int weight = -1;
				2933	unsigned maIndex;
				2934	// Compute the sums of the weights for each alternative, keeping track
				2935	// of the best (highest weight) one so far.
				2936	for (maIndex = 0; maIndex < maCount; ++maIndex) {
				2937	int weightSum = 0;
				2938	for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
				2939	cIndex != eIndex; ++cIndex) {
				2940	AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
				2941	if (OpInfo.Type == InlineAsm::isClobber)
				2942	continue;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2943
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2944	// If this is an output operand with a matching input operand,
				2945	// look up the matching input. If their types mismatch, e.g. one
				2946	// is an integer, the other is floating point, or their sizes are
				2947	// different, flag it as an maCantMatch.
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2948	if (OpInfo.hasMatchingInput()) {
				2949	AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2950	if (OpInfo.ConstraintVT != Input.ConstraintVT) {
				2951	if ((OpInfo.ConstraintVT.isInteger() !=
				2952	Input.ConstraintVT.isInteger()) \|\|
				2953	(OpInfo.ConstraintVT.getSizeInBits() !=
				2954	Input.ConstraintVT.getSizeInBits())) {
				2955	weightSum = -1; // Can't match.
				2956	break;
				2957	}
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2958	}
				2959	}
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2960	weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
				2961	if (weight == -1) {
				2962	weightSum = -1;
				2963	break;
				2964	}
				2965	weightSum += weight;
				2966	}
				2967	// Update best.
				2968	if (weightSum > bestWeight) {
				2969	bestWeight = weightSum;
				2970	bestMAIndex = maIndex;
				2971	}
				2972	}
				2973
				2974	// Now select chosen alternative in each constraint.
				2975	for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
				2976	cIndex != eIndex; ++cIndex) {
				2977	AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
				2978	if (cInfo.Type == InlineAsm::isClobber)
				2979	continue;
				2980	cInfo.selectAlternative(bestMAIndex);
				2981	}
				2982	}
				2983	}
				2984
				2985	// Check and hook up tied operands, choose constraint code to use.
				2986	for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
				2987	cIndex != eIndex; ++cIndex) {
				2988	AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	2989
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2990	// If this is an output operand with a matching input operand, look up the
				2991	// matching input. If their types mismatch, e.g. one is an integer, the
				2992	// other is floating point, or their sizes are different, flag it as an
				2993	// error.
				2994	if (OpInfo.hasMatchingInput()) {
				2995	AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	2996
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	2997	if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Eric Christopher	5427ede	2011-07-14 20:13:52 +0000	[diff] [blame]	2998	std::pair<unsigned, const TargetRegisterClass*> MatchRC =
				2999	getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
				3000	std::pair<unsigned, const TargetRegisterClass*> InputRC =
				3001	getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3002	if ((OpInfo.ConstraintVT.isInteger() !=
				3003	Input.ConstraintVT.isInteger()) \|\|
Eric Christopher	5427ede	2011-07-14 20:13:52 +0000	[diff] [blame]	3004	(MatchRC.second != InputRC.second)) {
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3005	report_fatal_error("Unsupported asm: input constraint"
				3006	" with a matching output constraint of"
				3007	" incompatible type!");
				3008	}
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3009	}
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3010
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3011	}
				3012	}
				3013
				3014	return ConstraintOperands;
				3015	}
				3016
Chris Lattner	58f15c4	2008-10-17 16:21:11 +0000	[diff] [blame]	3017
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3018	/// getConstraintGenerality - Return an integer indicating how general CT
				3019	/// is.
				3020	static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
				3021	switch (CT) {
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3022	case TargetLowering::C_Other:
				3023	case TargetLowering::C_Unknown:
				3024	return 0;
				3025	case TargetLowering::C_Register:
				3026	return 1;
				3027	case TargetLowering::C_RegisterClass:
				3028	return 2;
				3029	case TargetLowering::C_Memory:
				3030	return 3;
				3031	}
Chandler Carruth	732f05c	2012-01-10 18:08:01 +0000	[diff] [blame]	3032	llvm_unreachable("Invalid constraint type");
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3033	}
				3034
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3035	/// Examine constraint type and operand type and determine a weight value.
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3036	/// This object must already have been set up with the operand type
				3037	/// and the current alternative constraint selected.
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3038	TargetLowering::ConstraintWeight
				3039	TargetLowering::getMultipleConstraintMatchWeight(
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3040	AsmOperandInfo &info, int maIndex) const {
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3041	InlineAsm::ConstraintCodeVector *rCodes;
John Thompson	67aff16	2010-09-21 22:04:54 +0000	[diff] [blame]	3042	if (maIndex >= (int)info.multipleAlternatives.size())
				3043	rCodes = &info.Codes;
				3044	else
				3045	rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3046	ConstraintWeight BestWeight = CW_Invalid;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3047
				3048	// Loop over the options, keeping track of the most general one.
John Thompson	67aff16	2010-09-21 22:04:54 +0000	[diff] [blame]	3049	for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3050	ConstraintWeight weight =
				3051	getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3052	if (weight > BestWeight)
				3053	BestWeight = weight;
				3054	}
				3055
				3056	return BestWeight;
				3057	}
				3058
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3059	/// Examine constraint type and operand type and determine a weight value.
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3060	/// This object must already have been set up with the operand type
				3061	/// and the current alternative constraint selected.
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3062	TargetLowering::ConstraintWeight
				3063	TargetLowering::getSingleConstraintMatchWeight(
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3064	AsmOperandInfo &info, const char *constraint) const {
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3065	ConstraintWeight weight = CW_Invalid;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3066	Value *CallOperandVal = info.CallOperandVal;
				3067	// If we don't have a value, we can't do a match,
				3068	// but allow it at the lowest weight.
				3069	if (CallOperandVal == NULL)
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3070	return CW_Default;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3071	// Look at the constraint type.
				3072	switch (*constraint) {
				3073	case 'i': // immediate integer.
				3074	case 'n': // immediate integer with a known value.
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3075	if (isa<ConstantInt>(CallOperandVal))
				3076	weight = CW_Constant;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3077	break;
				3078	case 's': // non-explicit intregal immediate.
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3079	if (isa<GlobalValue>(CallOperandVal))
				3080	weight = CW_Constant;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3081	break;
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3082	case 'E': // immediate float if host format.
				3083	case 'F': // immediate float.
				3084	if (isa<ConstantFP>(CallOperandVal))
				3085	weight = CW_Constant;
				3086	break;
				3087	case '<': // memory operand with autodecrement.
				3088	case '>': // memory operand with autoincrement.
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3089	case 'm': // memory operand.
				3090	case 'o': // offsettable memory operand
				3091	case 'V': // non-offsettable memory operand
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3092	weight = CW_Memory;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3093	break;
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3094	case 'r': // general register.
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3095	case 'g': // general register, memory operand or immediate integer.
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3096	// note: Clang converts "g" to "imr".
				3097	if (CallOperandVal->getType()->isIntegerTy())
				3098	weight = CW_Register;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3099	break;
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3100	case 'X': // any operand.
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3101	default:
John Thompson	44ab89e	2010-10-29 17:29:13 +0000	[diff] [blame]	3102	weight = CW_Default;
John Thompson	eac6e1d	2010-09-13 18:15:37 +0000	[diff] [blame]	3103	break;
				3104	}
				3105	return weight;
				3106	}
				3107
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3108	/// ChooseConstraint - If there are multiple different constraints that we
				3109	/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner	24e1a9d	2008-04-27 01:49:46 +0000	[diff] [blame]	3110	/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3111	/// Other -> immediates and magic values
				3112	/// Register -> one specific register
				3113	/// RegisterClass -> a group of regs
				3114	/// Memory -> memory
				3115	/// Ideally, we would pick the most specific constraint possible: if we have
				3116	/// something that fits into a register, we would pick it. The problem here
				3117	/// is that if we have something that could either be in a register or in
				3118	/// memory that use of the register could cause selection of other
				3119	/// operands to fail: they might only succeed if we pick memory. Because of
				3120	/// this the heuristic we use is:
				3121	///
				3122	/// 1) If there is an 'other' constraint, and if the operand is valid for
				3123	/// that constraint, use it. This makes us take advantage of 'i'
				3124	/// constraints when available.
				3125	/// 2) Otherwise, pick the most general constraint present. This prefers
				3126	/// 'm' over 'r', for example.
				3127	///
				3128	static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen	1784d16	2010-06-25 21:55:36 +0000	[diff] [blame]	3129	const TargetLowering &TLI,
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	3130	SDValue Op, SelectionDAG *DAG) {
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3131	assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
				3132	unsigned BestIdx = 0;
				3133	TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
				3134	int BestGenerality = -1;
Dale Johannesen	a5989f8	2010-06-28 22:09:45 +0000	[diff] [blame]	3135
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3136	// Loop over the options, keeping track of the most general one.
				3137	for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
				3138	TargetLowering::ConstraintType CType =
				3139	TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesen	a5989f8	2010-06-28 22:09:45 +0000	[diff] [blame]	3140
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	3141	// If this is an 'other' constraint, see if the operand is valid for it.
				3142	// For example, on X86 we might have an 'rI' constraint. If the operand
				3143	// is an integer in the range [0..31] we want to use I (saving a load
				3144	// of a register), otherwise we must use 'r'.
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3145	if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	3146	assert(OpInfo.Codes[i].size() == 1 &&
				3147	"Unhandled multi-letter 'other' constraint");
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	3148	std::vector<SDValue> ResultOps;
Eric Christopher	100c833	2011-06-02 23:16:42 +0000	[diff] [blame]	3149	TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	3150	ResultOps, *DAG);
				3151	if (!ResultOps.empty()) {
				3152	BestType = CType;
				3153	BestIdx = i;
				3154	break;
				3155	}
				3156	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3157
Dale Johannesen	a5989f8	2010-06-28 22:09:45 +0000	[diff] [blame]	3158	// Things with matching constraints can only be registers, per gcc
				3159	// documentation. This mainly affects "g" constraints.
				3160	if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
				3161	continue;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3162
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3163	// This constraint letter is more general than the previous one, use it.
				3164	int Generality = getConstraintGenerality(CType);
				3165	if (Generality > BestGenerality) {
				3166	BestType = CType;
				3167	BestIdx = i;
				3168	BestGenerality = Generality;
				3169	}
				3170	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3171
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3172	OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
				3173	OpInfo.ConstraintType = BestType;
				3174	}
				3175
				3176	/// ComputeConstraintToUse - Determines the constraint code and constraint
				3177	/// type to use for the specific AsmOperandInfo, setting
				3178	/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	3179	void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3180	SDValue Op,
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	3181	SelectionDAG *DAG) const {
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3182	assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3183
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3184	// Single-letter constraints ('r') are very common.
				3185	if (OpInfo.Codes.size() == 1) {
				3186	OpInfo.ConstraintCode = OpInfo.Codes[0];
				3187	OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
				3188	} else {
Dale Johannesen	1784d16	2010-06-25 21:55:36 +0000	[diff] [blame]	3189	ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3190	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3191
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3192	// 'X' matches anything.
				3193	if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
				3194	// Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen	8ea5ec6	2009-07-07 23:26:33 +0000	[diff] [blame]	3195	// that matches labels). For Functions, the type here is the type of
Dale Johannesen	5339c55	2009-07-20 23:27:39 +0000	[diff] [blame]	3196	// the result, which is not what we want to look at; leave them alone.
				3197	Value *v = OpInfo.CallOperandVal;
Dale Johannesen	8ea5ec6	2009-07-07 23:26:33 +0000	[diff] [blame]	3198	if (isa<BasicBlock>(v) \|\| isa<ConstantInt>(v) \|\| isa<Function>(v)) {
				3199	OpInfo.CallOperandVal = v;
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3200	return;
Dale Johannesen	8ea5ec6	2009-07-07 23:26:33 +0000	[diff] [blame]	3201	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3202
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	3203	// Otherwise, try to resolve it to something we know about by looking at
				3204	// the actual operand type.
				3205	if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
				3206	OpInfo.ConstraintCode = Repl;
				3207	OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
				3208	}
				3209	}
				3210	}
				3211
				3212	//===----------------------------------------------------------------------===//
Evan Cheng	30b37b5	2006-03-13 23:18:16 +0000	[diff] [blame]	3213	// Loop Strength Reduction hooks
				3214	//===----------------------------------------------------------------------===//
				3215
Chris Lattner	1436bb6	2007-03-30 23:14:50 +0000	[diff] [blame]	3216	/// isLegalAddressingMode - Return true if the addressing mode represented
				3217	/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3218	bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattner	db125cf	2011-07-18 04:54:35 +0000	[diff] [blame]	3219	Type *Ty) const {
Chris Lattner	1436bb6	2007-03-30 23:14:50 +0000	[diff] [blame]	3220	// The default implementation of this implements a conservative RISCy, r+r and
				3221	// r+i addr mode.
				3222
				3223	// Allows a sign-extended 16-bit immediate field.
				3224	if (AM.BaseOffs <= -(1LL << 16) \|\| AM.BaseOffs >= (1LL << 16)-1)
				3225	return false;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3226
Chris Lattner	1436bb6	2007-03-30 23:14:50 +0000	[diff] [blame]	3227	// No global is ever allowed as a base.
				3228	if (AM.BaseGV)
				3229	return false;
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3230
				3231	// Only support r+r,
Chris Lattner	1436bb6	2007-03-30 23:14:50 +0000	[diff] [blame]	3232	switch (AM.Scale) {
				3233	case 0: // "r+i" or just "i", depending on HasBaseReg.
				3234	break;
				3235	case 1:
				3236	if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
				3237	return false;
				3238	// Otherwise we have r+r or r+i.
				3239	break;
				3240	case 2:
				3241	if (AM.HasBaseReg \|\| AM.BaseOffs) // 2r+r or 2r+i is not allowed.
				3242	return false;
				3243	// Allow 2*r as r+r.
				3244	break;
				3245	}
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3246
Chris Lattner	1436bb6	2007-03-30 23:14:50 +0000	[diff] [blame]	3247	return true;
				3248	}
				3249
Benjamin Kramer	9c64030	2011-07-08 10:31:30 +0000	[diff] [blame]	3250	/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
				3251	/// with the multiplicative inverse of the constant.
				3252	SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
				3253	SelectionDAG &DAG) const {
				3254	ConstantSDNode *C = cast<ConstantSDNode>(Op2);
				3255	APInt d = C->getAPIntValue();
				3256	assert(d != 0 && "Division by zero!");
				3257
				3258	// Shift the value upfront if it is even, so the LSB is one.
				3259	unsigned ShAmt = d.countTrailingZeros();
				3260	if (ShAmt) {
				3261	// TODO: For UDIV use SRL instead of SRA.
				3262	SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
				3263	Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
				3264	d = d.ashr(ShAmt);
				3265	}
				3266
				3267	// Calculate the multiplicative inverse, using Newton's method.
				3268	APInt t, xn = d;
				3269	while ((t = d*xn) != 1)
				3270	xn *= APInt(d.getBitWidth(), 2) - t;
				3271
				3272	Op2 = DAG.getConstant(xn, Op1.getValueType());
				3273	return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
				3274	}
				3275
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3276	/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
				3277	/// return a DAG expression to select that will generate the same value by
				3278	/// multiplying by a magic number. See:
				3279	/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne	19a4daf	2011-11-07 17:09:05 +0000	[diff] [blame]	3280	SDValue TargetLowering::
				3281	BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
				3282	std::vector<SDNode> Created) const {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	3283	EVT VT = N->getValueType(0);
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3284	DebugLoc dl= N->getDebugLoc();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3285
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3286	// Check to see if we can do this.
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	3287	// FIXME: We should be more aggressive here.
				3288	if (!isTypeLegal(VT))
				3289	return SDValue();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3290
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	3291	APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad	4e5ea55	2009-04-30 10:15:35 +0000	[diff] [blame]	3292	APInt::ms magics = d.magic();
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3293
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3294	// Multiply the numerator (operand 0) by the magic value
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	3295	// FIXME: We should support doing a MUL in a wider type
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	3296	SDValue Q;
Richard Osborne	19a4daf	2011-11-07 17:09:05 +0000	[diff] [blame]	3297	if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
				3298	isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3299	Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	3300	DAG.getConstant(magics.m, VT));
Richard Osborne	19a4daf	2011-11-07 17:09:05 +0000	[diff] [blame]	3301	else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
				3302	isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3303	Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	3304	N->getOperand(0),
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3305	DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	3306	else
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	3307	return SDValue(); // No mulhs or equvialent
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3308	// If d > 0 and m < 0, add the numerator
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3309	if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3310	Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3311	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3312	Created->push_back(Q.getNode());
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3313	}
				3314	// If d < 0 and m > 0, subtract the numerator.
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	3315	if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3316	Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3317	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3318	Created->push_back(Q.getNode());
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3319	}
				3320	// Shift right algebraic if shift value is nonzero
				3321	if (magics.s > 0) {
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3322	Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	3323	DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3324	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3325	Created->push_back(Q.getNode());
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3326	}
				3327	// Extract the sign bit and add it to the quotient
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	3328	SDValue T =
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3329	DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	3330	getShiftAmountTy(Q.getValueType())));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3331	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3332	Created->push_back(T.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3333	return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3334	}
				3335
				3336	/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
				3337	/// return a DAG expression to select that will generate the same value by
				3338	/// multiplying by a magic number. See:
				3339	/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne	19a4daf	2011-11-07 17:09:05 +0000	[diff] [blame]	3340	SDValue TargetLowering::
				3341	BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
				3342	std::vector<SDNode> Created) const {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	3343	EVT VT = N->getValueType(0);
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3344	DebugLoc dl = N->getDebugLoc();
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	3345
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3346	// Check to see if we can do this.
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	3347	// FIXME: We should be more aggressive here.
				3348	if (!isTypeLegal(VT))
				3349	return SDValue();
				3350
				3351	// FIXME: We should use a narrower constant when the upper
				3352	// bits are known to be zero.
Benjamin Kramer	1c10b8d	2011-03-17 20:39:14 +0000	[diff] [blame]	3353	const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
				3354	APInt::mu magics = N1C.magicu();
				3355
				3356	SDValue Q = N->getOperand(0);
				3357
				3358	// If the divisor is even, we can avoid using the expensive fixup by shifting
				3359	// the divided value upfront.
				3360	if (magics.a != 0 && !N1C[0]) {
				3361	unsigned Shift = N1C.countTrailingZeros();
				3362	Q = DAG.getNode(ISD::SRL, dl, VT, Q,
				3363	DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
				3364	if (Created)
				3365	Created->push_back(Q.getNode());
				3366
				3367	// Get magic number for the shifted divisor.
				3368	magics = N1C.lshr(Shift).magicu(Shift);
				3369	assert(magics.a == 0 && "Should use cheap fixup now");
				3370	}
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	3371
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3372	// Multiply the numerator (operand 0) by the magic value
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	3373	// FIXME: We should support doing a MUL in a wider type
Richard Osborne	19a4daf	2011-11-07 17:09:05 +0000	[diff] [blame]	3374	if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
				3375	isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer	1c10b8d	2011-03-17 20:39:14 +0000	[diff] [blame]	3376	Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Richard Osborne	19a4daf	2011-11-07 17:09:05 +0000	[diff] [blame]	3377	else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
				3378	isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer	1c10b8d	2011-03-17 20:39:14 +0000	[diff] [blame]	3379	Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
				3380	DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	3381	else
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	3382	return SDValue(); // No mulhu or equvialent
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3383	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3384	Created->push_back(Q.getNode());
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3385
				3386	if (magics.a == 0) {
Benjamin Kramer	1c10b8d	2011-03-17 20:39:14 +0000	[diff] [blame]	3387	assert(magics.s < N1C.getBitWidth() &&
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	3388	"We shouldn't generate an undefined shift!");
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3389	return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	3390	DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3391	} else {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3392	SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3393	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3394	Created->push_back(NPQ.getNode());
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3395	NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	3396	DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3397	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3398	Created->push_back(NPQ.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	3399	NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3400	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	3401	Created->push_back(NPQ.getNode());
Wesley Peck	bf17cfa	2010-11-23 03:31:01 +0000	[diff] [blame]	3402	return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson	95771af	2011-02-25 21:41:48 +0000	[diff] [blame]	3403	DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	3404	}
				3405	}