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gerrit-public.fairphone.software / platform / external / llvm / b318cc16c9e959adb96294b3aa4940e74f68dde3 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 05e3cedbdf5dd365df9fbca2d9d60619b6ab3d9c [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]13#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]14#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]15#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]16#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]17#include "llvm/MC/MCInstrDesc.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]20#include "llvm/MC/MCDisassembler.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]21#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]48 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]49 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]50 raw_ostream &vStream,
51 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]52
53 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]54 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]55private:
56};
57
58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59class ThumbDisassembler : public MCDisassembler {
60public:
61 /// Constructor - Initializes the disassembler.
62 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]65 }
66
67 ~ThumbDisassembler() {
68 }
69
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
72 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]73 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]74 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]75 raw_ostream &vStream,
76 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]77
78 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]79 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]80private:
81 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]82 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]83 void UpdateThumbVFPPredicate(MCInst&) const;
84};
85}
86
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]87static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]88 switch (In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
91 return true;
92 case MCDisassembler::SoftFail:
93 Out = In;
94 return true;
95 case MCDisassembler::Fail:
96 Out = In;
97 return false;
98 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]99 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]100}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]101
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]102
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103// Forward declare these because the autogenerated code will reference them.
104// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]105static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]106 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]107static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]110static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]111 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]112static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]113 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]114static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]115 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]116static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]118static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]120static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]122static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]123 unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]126static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]128static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]129 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]130static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]131 unsigned RegNo, uint64_t Address,
132 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]133
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]134static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]136static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]138static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]140static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]142static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]143 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]144static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]145 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]146
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]147static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]148 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]149static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]150 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]151static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]152 unsigned Insn,
153 uint64_t Address,
154 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]155static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]157static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]159static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]160 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]161static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]162 uint64_t Address, const void *Decoder);
163
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]164static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]165 unsigned Insn,
166 uint64_t Adddress,
167 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]168static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]170static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]172static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]174static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]176static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]178static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]180static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]182static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]184static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]186static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]188static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]190static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]192static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]194static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]198static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]200static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]202static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]204static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]210static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]212static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]214static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]216static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]218static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]220static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]222static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]224static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]226static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]228static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]230static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]232static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]234static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]236static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]238static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]240static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]242static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]244static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]246static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]248static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]250static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]252static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]254static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]256static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]258static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
260
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]262static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]264static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]266static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]268static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]270static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]272static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]274static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]276static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]278static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]280static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]282static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]284static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]286static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]288static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]290static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]292static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]294static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]296static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]298static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]300static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]302static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]303 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]304static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]305 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]306static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]307 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]308static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]309 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]310static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]311 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]312static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]313 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]314static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]315 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]316static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]317 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]318static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]319 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]320static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]321 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]322static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]323 uint64_t Address, const void *Decoder);
324
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]325static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]326 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327#include "ARMGenDisassemblerTables.inc"
328#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]329#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]330
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]331static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
332 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]333}
334
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]335static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
336 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]337}
338
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]339const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]340 return instInfoARM;
341}
342
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]343const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]344 return instInfoARM;
345}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]346
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]347DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]348 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]349 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]350 raw_ostream &os,
351 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]352 CommentStream = &cs;
353
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]354 uint8_t bytes[4];
355
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]356 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
357 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
358
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]359 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]360 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
361 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]362 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]363 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]364
365 // Encoded as a small-endian 32-bit word in the stream.
366 uint32_t insn = (bytes[3] << 24) |
367 (bytes[2] << 16) |
368 (bytes[1] << 8) |
369 (bytes[0] << 0);
370
371 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]372 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]375 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 }
377
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]378 // VFP and NEON instructions, similarly, are shared between ARM
379 // and Thumb modes.
380 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]381 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]382 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]383 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]384 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]385 }
386
387 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]388 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]389 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]390 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]391 // Add a fake predicate operand, because we share these instruction
392 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]393 if (!DecodePredicateOperand(MI, 0xE, Address, this))
394 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]395 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]396 }
397
398 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]399 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]400 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]401 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]402 // Add a fake predicate operand, because we share these instruction
403 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]404 if (!DecodePredicateOperand(MI, 0xE, Address, this))
405 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]406 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]407 }
408
409 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]410 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]411 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]412 Size = 4;
413 // Add a fake predicate operand, because we share these instruction
414 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]415 if (!DecodePredicateOperand(MI, 0xE, Address, this))
416 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]417 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]418 }
419
420 MI.clear();
421
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]422 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]423 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]424}
425
426namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]427extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]428}
429
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]430/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
431/// immediate Value in the MCInst. The immediate Value has had any PC
432/// adjustment made by the caller. If the instruction is a branch instruction
433/// then isBranch is true, else false. If the getOpInfo() function was set as
434/// part of the setupForSymbolicDisassembly() call then that function is called
435/// to get any symbolic information at the Address for this instruction. If
436/// that returns non-zero then the symbolic information it returns is used to
437/// create an MCExpr and that is added as an operand to the MCInst. If
438/// getOpInfo() returns zero and isBranch is true then a symbol look up for
439/// Value is done and if a symbol is found an MCExpr is created with that, else
440/// an MCExpr with Value is created. This function returns true if it adds an
441/// operand to the MCInst and false otherwise.
442static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
443 bool isBranch, uint64_t InstSize,
444 MCInst &MI, const void *Decoder) {
445 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
446 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]447 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]448 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]449 SymbolicOp.Value = Value;
450 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]451
452 if (!getOpInfo ||
453 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
454 // Clear SymbolicOp.Value from above and also all other fields.
455 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
456 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
457 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]458 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]459 uint64_t ReferenceType;
460 if (isBranch)
461 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
462 else
463 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
464 const char *ReferenceName;
465 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
466 &ReferenceName);
467 if (Name) {
468 SymbolicOp.AddSymbol.Name = Name;
469 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]470 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]471 // For branches always create an MCExpr so it gets printed as hex address.
472 else if (isBranch) {
473 SymbolicOp.Value = Value;
474 }
475 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
476 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
477 if (!Name && !isBranch)
478 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]479 }
480
481 MCContext *Ctx = Dis->getMCContext();
482 const MCExpr *Add = NULL;
483 if (SymbolicOp.AddSymbol.Present) {
484 if (SymbolicOp.AddSymbol.Name) {
485 StringRef Name(SymbolicOp.AddSymbol.Name);
486 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
487 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
488 } else {
489 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
490 }
491 }
492
493 const MCExpr *Sub = NULL;
494 if (SymbolicOp.SubtractSymbol.Present) {
495 if (SymbolicOp.SubtractSymbol.Name) {
496 StringRef Name(SymbolicOp.SubtractSymbol.Name);
497 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
498 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
499 } else {
500 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
501 }
502 }
503
504 const MCExpr *Off = NULL;
505 if (SymbolicOp.Value != 0)
506 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
507
508 const MCExpr *Expr;
509 if (Sub) {
510 const MCExpr *LHS;
511 if (Add)
512 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
513 else
514 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
515 if (Off != 0)
516 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
517 else
518 Expr = LHS;
519 } else if (Add) {
520 if (Off != 0)
521 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
522 else
523 Expr = Add;
524 } else {
525 if (Off != 0)
526 Expr = Off;
527 else
528 Expr = MCConstantExpr::Create(0, *Ctx);
529 }
530
531 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
532 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
533 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
534 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
535 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
536 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]537 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]538 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]539
540 return true;
541}
542
543/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
544/// referenced by a load instruction with the base register that is the Pc.
545/// These can often be values in a literal pool near the Address of the
546/// instruction. The Address of the instruction and its immediate Value are
547/// used as a possible literal pool entry. The SymbolLookUp call back will
548/// return the name of a symbol referenced by the the literal pool's entry if
549/// the referenced address is that of a symbol. Or it will return a pointer to
550/// a literal 'C' string if the referenced address of the literal pool's entry
551/// is an address into a section with 'C' string literals.
552static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]553 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]554 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
555 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
556 if (SymbolLookUp) {
557 void *DisInfo = Dis->getDisInfoBlock();
558 uint64_t ReferenceType;
559 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
560 const char *ReferenceName;
561 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
562 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
563 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
564 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
565 }
566}
567
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]568// Thumb1 instructions don't have explicit S bits. Rather, they
569// implicitly set CPSR. Since it's not represented in the encoding, the
570// auto-generated decoder won't inject the CPSR operand. We need to fix
571// that as a post-pass.
572static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
573 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]574 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]575 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]576 for (unsigned i = 0; i < NumOps; ++i, ++I) {
577 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]578 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]579 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]580 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
581 return;
582 }
583 }
584
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]585 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]586}
587
588// Most Thumb instructions don't have explicit predicates in the
589// encoding, but rather get their predicates from IT context. We need
590// to fix up the predicate operands using this context information as a
591// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]592MCDisassembler::DecodeStatus
593ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]594 MCDisassembler::DecodeStatus S = Success;
595
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]596 // A few instructions actually have predicates encoded in them. Don't
597 // try to overwrite it if we're seeing one of those.
598 switch (MI.getOpcode()) {
599 case ARM::tBcc:
600 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]601 case ARM::tCBZ:
602 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]603 case ARM::tCPS:
604 case ARM::t2CPS3p:
605 case ARM::t2CPS2p:
606 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]607 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]608 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]609 // Some instructions (mostly conditional branches) are not
610 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]611 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]612 S = SoftFail;
613 else
614 return Success;
615 break;
616 case ARM::tB:
617 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]618 case ARM::t2TBB:
619 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]620 // Some instructions (mostly unconditional branches) can
621 // only appears at the end of, or outside of, an IT.
622 if (ITBlock.size() > 1)
623 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]624 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]625 default:
626 break;
627 }
628
629 // If we're in an IT block, base the predicate on that. Otherwise,
630 // assume a predicate of AL.
631 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]632 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]633 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]634 if (CC == 0xF)
635 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]636 ITBlock.pop_back();
637 } else
638 CC = ARMCC::AL;
639
640 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]641 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]642 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]643 for (unsigned i = 0; i < NumOps; ++i, ++I) {
644 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]645 if (OpInfo[i].isPredicate()) {
646 I = MI.insert(I, MCOperand::CreateImm(CC));
647 ++I;
648 if (CC == ARMCC::AL)
649 MI.insert(I, MCOperand::CreateReg(0));
650 else
651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]652 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]653 }
654 }
655
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]656 I = MI.insert(I, MCOperand::CreateImm(CC));
657 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]658 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]659 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]660 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]661 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]662
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]663 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]664}
665
666// Thumb VFP instructions are a special case. Because we share their
667// encodings between ARM and Thumb modes, and they are predicable in ARM
668// mode, the auto-generated decoder will give them an (incorrect)
669// predicate operand. We need to rewrite these operands based on the IT
670// context as a post-pass.
671void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
672 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]673 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]674 CC = ITBlock.back();
675 ITBlock.pop_back();
676 } else
677 CC = ARMCC::AL;
678
679 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
680 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]681 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
682 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]683 if (OpInfo[i].isPredicate() ) {
684 I->setImm(CC);
685 ++I;
686 if (CC == ARMCC::AL)
687 I->setReg(0);
688 else
689 I->setReg(ARM::CPSR);
690 return;
691 }
692 }
693}
694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]695DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]696 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]697 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]698 raw_ostream &os,
699 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]700 CommentStream = &cs;
701
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]702 uint8_t bytes[4];
703
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]704 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
705 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
706
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]707 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]708 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
709 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]710 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]711 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]712
713 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]714 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]715 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]716 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]717 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]718 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]719 }
720
721 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]722 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]723 if (result) {
724 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]725 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]726 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]727 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]728 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]729 }
730
731 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]732 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]733 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]734 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]735
736 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
737 // the Thumb predicate.
738 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
739 result = MCDisassembler::SoftFail;
740
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]741 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]742
743 // If we find an IT instruction, we need to parse its condition
744 // code and mask operands so that we can apply them correctly
745 // to the subsequent instructions.
746 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]747
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]748 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]749 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]750 unsigned Mask = MI.getOperand(1).getImm();
751 unsigned CondBit0 = Mask >> 4 & 1;
752 unsigned NumTZ = CountTrailingZeros_32(Mask);
753 assert(NumTZ <= 3 && "Invalid IT mask!");
754 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
755 bool T = ((Mask >> Pos) & 1) == CondBit0;
756 if (T)
757 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]758 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]759 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]760 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]761
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]762 ITBlock.push_back(firstcond);
763 }
764
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]765 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]766 }
767
768 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]769 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
770 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]771 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]772 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]773
774 uint32_t insn32 = (bytes[3] << 8) |
775 (bytes[2] << 0) |
776 (bytes[1] << 24) |
777 (bytes[0] << 16);
778 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]779 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]780 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]781 Size = 4;
782 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]783 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]784 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]785 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 }
787
788 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]789 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]790 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]792 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]793 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794 }
795
796 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]797 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]798 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]799 Size = 4;
800 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]801 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]802 }
803
804 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]805 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]806 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]807 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]808 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]809 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]810 }
811
812 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
813 MI.clear();
814 uint32_t NEONLdStInsn = insn32;
815 NEONLdStInsn &= 0xF0FFFFFF;
816 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]817 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]818 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]819 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]820 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]821 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]822 }
823 }
824
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]825 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]826 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]827 uint32_t NEONDataInsn = insn32;
828 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
829 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
830 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]831 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]832 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]833 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]834 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]835 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]836 }
837 }
838
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]839 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]840 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]841}
842
843
844extern "C" void LLVMInitializeARMDisassembler() {
845 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
846 createARMDisassembler);
847 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
848 createThumbDisassembler);
849}
850
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]851static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]852 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
853 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
854 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
855 ARM::R12, ARM::SP, ARM::LR, ARM::PC
856};
857
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]858static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]859 uint64_t Address, const void *Decoder) {
860 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]861 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]862
863 unsigned Register = GPRDecoderTable[RegNo];
864 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]865 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]866}
867
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]868static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]869DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]870 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]871 DecodeStatus S = MCDisassembler::Success;
872
873 if (RegNo == 15)
874 S = MCDisassembler::SoftFail;
875
876 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
877
878 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]879}
880
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]881static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]882 uint64_t Address, const void *Decoder) {
883 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]884 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]885 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
886}
887
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]888static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]889 uint64_t Address, const void *Decoder) {
890 unsigned Register = 0;
891 switch (RegNo) {
892 case 0:
893 Register = ARM::R0;
894 break;
895 case 1:
896 Register = ARM::R1;
897 break;
898 case 2:
899 Register = ARM::R2;
900 break;
901 case 3:
902 Register = ARM::R3;
903 break;
904 case 9:
905 Register = ARM::R9;
906 break;
907 case 12:
908 Register = ARM::R12;
909 break;
910 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]911 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]912 }
913
914 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]915 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]916}
917
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]918static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]919 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]920 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]921 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
922}
923
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]924static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
926 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
927 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
928 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
929 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
930 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
931 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
932 ARM::S28, ARM::S29, ARM::S30, ARM::S31
933};
934
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]935static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]936 uint64_t Address, const void *Decoder) {
937 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]938 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]939
940 unsigned Register = SPRDecoderTable[RegNo];
941 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]942 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]943}
944
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]945static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
947 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
948 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
949 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
950 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
951 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
952 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
953 ARM::D28, ARM::D29, ARM::D30, ARM::D31
954};
955
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]956static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]957 uint64_t Address, const void *Decoder) {
958 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]959 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]960
961 unsigned Register = DPRDecoderTable[RegNo];
962 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]963 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]964}
965
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]966static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]967 uint64_t Address, const void *Decoder) {
968 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]969 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]970 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
971}
972
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]973static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]974DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]975 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]976 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]977 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]978 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
979}
980
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]981static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]982 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
983 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
984 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
985 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
986};
987
988
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]989static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]990 uint64_t Address, const void *Decoder) {
991 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]992 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]993 RegNo >>= 1;
994
995 unsigned Register = QPRDecoderTable[RegNo];
996 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]997 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]998}
999
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1000static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1001 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1002 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1003 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1004 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1005 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1006 ARM::Q15
1007};
1008
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1009static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1010 uint64_t Address, const void *Decoder) {
1011 if (RegNo > 30)
1012 return MCDisassembler::Fail;
1013
1014 unsigned Register = DPairDecoderTable[RegNo];
1015 Inst.addOperand(MCOperand::CreateReg(Register));
1016 return MCDisassembler::Success;
1017}
1018
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1019static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1020 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1021 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1022 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1023 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1024 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1025 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1026 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1027 ARM::D28_D30, ARM::D29_D31
1028};
1029
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1030static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1031 unsigned RegNo,
1032 uint64_t Address,
1033 const void *Decoder) {
1034 if (RegNo > 29)
1035 return MCDisassembler::Fail;
1036
1037 unsigned Register = DPairSpacedDecoderTable[RegNo];
1038 Inst.addOperand(MCOperand::CreateReg(Register));
1039 return MCDisassembler::Success;
1040}
1041
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1042static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1043 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1044 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1045 // AL predicate is not allowed on Thumb1 branches.
1046 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1047 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1048 Inst.addOperand(MCOperand::CreateImm(Val));
1049 if (Val == ARMCC::AL) {
1050 Inst.addOperand(MCOperand::CreateReg(0));
1051 } else
1052 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1053 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1054}
1055
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1056static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1057 uint64_t Address, const void *Decoder) {
1058 if (Val)
1059 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1060 else
1061 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1062 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1063}
1064
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1065static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1066 uint64_t Address, const void *Decoder) {
1067 uint32_t imm = Val & 0xFF;
1068 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1069 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1070 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1071 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1072}
1073
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1074static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1075 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1076 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1077
1078 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1079 unsigned type = fieldFromInstruction32(Val, 5, 2);
1080 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1081
1082 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1084 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1085
1086 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1087 switch (type) {
1088 case 0:
1089 Shift = ARM_AM::lsl;
1090 break;
1091 case 1:
1092 Shift = ARM_AM::lsr;
1093 break;
1094 case 2:
1095 Shift = ARM_AM::asr;
1096 break;
1097 case 3:
1098 Shift = ARM_AM::ror;
1099 break;
1100 }
1101
1102 if (Shift == ARM_AM::ror && imm == 0)
1103 Shift = ARM_AM::rrx;
1104
1105 unsigned Op = Shift | (imm << 3);
1106 Inst.addOperand(MCOperand::CreateImm(Op));
1107
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1108 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1109}
1110
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1111static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1113 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1114
1115 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1116 unsigned type = fieldFromInstruction32(Val, 5, 2);
1117 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1118
1119 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1120 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1121 return MCDisassembler::Fail;
1122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1123 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1124
1125 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1126 switch (type) {
1127 case 0:
1128 Shift = ARM_AM::lsl;
1129 break;
1130 case 1:
1131 Shift = ARM_AM::lsr;
1132 break;
1133 case 2:
1134 Shift = ARM_AM::asr;
1135 break;
1136 case 3:
1137 Shift = ARM_AM::ror;
1138 break;
1139 }
1140
1141 Inst.addOperand(MCOperand::CreateImm(Shift));
1142
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1143 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1144}
1145
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1146static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1147 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1148 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1149
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1150 bool writebackLoad = false;
1151 unsigned writebackReg = 0;
1152 switch (Inst.getOpcode()) {
1153 default:
1154 break;
1155 case ARM::LDMIA_UPD:
1156 case ARM::LDMDB_UPD:
1157 case ARM::LDMIB_UPD:
1158 case ARM::LDMDA_UPD:
1159 case ARM::t2LDMIA_UPD:
1160 case ARM::t2LDMDB_UPD:
1161 writebackLoad = true;
1162 writebackReg = Inst.getOperand(0).getReg();
1163 break;
1164 }
1165
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1166 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1167 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1168 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1169 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1170 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1171 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1172 // Writeback not allowed if Rn is in the target list.
1173 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1174 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1175 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1176 }
1177
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1178 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1179}
1180
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1181static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1182 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1183 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1184
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1185 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1186 unsigned regs = Val & 0xFF;
1187
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1188 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1189 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1190 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1191 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1192 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1193 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1194
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1195 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1196}
1197
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1198static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1199 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1200 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1201
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1202 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1203 unsigned regs = (Val & 0xFF) / 2;
1204
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1205 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1206 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1207 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1208 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1209 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1210 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1211
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1212 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1213}
1214
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1215static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1216 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1217 // This operand encodes a mask of contiguous zeros between a specified MSB
1218 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1219 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1220 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1221 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1222 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1223 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1224
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1225 DecodeStatus S = MCDisassembler::Success;
1226 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1227
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1228 uint32_t msb_mask = 0xFFFFFFFF;
1229 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1230 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1231
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1232 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1233 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1234}
1235
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1236static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1237 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1238 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1239
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1240 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1241 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1242 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1243 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1244 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1245 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1246
1247 switch (Inst.getOpcode()) {
1248 case ARM::LDC_OFFSET:
1249 case ARM::LDC_PRE:
1250 case ARM::LDC_POST:
1251 case ARM::LDC_OPTION:
1252 case ARM::LDCL_OFFSET:
1253 case ARM::LDCL_PRE:
1254 case ARM::LDCL_POST:
1255 case ARM::LDCL_OPTION:
1256 case ARM::STC_OFFSET:
1257 case ARM::STC_PRE:
1258 case ARM::STC_POST:
1259 case ARM::STC_OPTION:
1260 case ARM::STCL_OFFSET:
1261 case ARM::STCL_PRE:
1262 case ARM::STCL_POST:
1263 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1264 case ARM::t2LDC_OFFSET:
1265 case ARM::t2LDC_PRE:
1266 case ARM::t2LDC_POST:
1267 case ARM::t2LDC_OPTION:
1268 case ARM::t2LDCL_OFFSET:
1269 case ARM::t2LDCL_PRE:
1270 case ARM::t2LDCL_POST:
1271 case ARM::t2LDCL_OPTION:
1272 case ARM::t2STC_OFFSET:
1273 case ARM::t2STC_PRE:
1274 case ARM::t2STC_POST:
1275 case ARM::t2STC_OPTION:
1276 case ARM::t2STCL_OFFSET:
1277 case ARM::t2STCL_PRE:
1278 case ARM::t2STCL_POST:
1279 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1280 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1281 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1282 break;
1283 default:
1284 break;
1285 }
1286
1287 Inst.addOperand(MCOperand::CreateImm(coproc));
1288 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1290 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1291
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1292 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1293 case ARM::t2LDC2_OFFSET:
1294 case ARM::t2LDC2L_OFFSET:
1295 case ARM::t2LDC2_PRE:
1296 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1297 case ARM::t2STC2_OFFSET:
1298 case ARM::t2STC2L_OFFSET:
1299 case ARM::t2STC2_PRE:
1300 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1301 case ARM::LDC2_OFFSET:
1302 case ARM::LDC2L_OFFSET:
1303 case ARM::LDC2_PRE:
1304 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1305 case ARM::STC2_OFFSET:
1306 case ARM::STC2L_OFFSET:
1307 case ARM::STC2_PRE:
1308 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1309 case ARM::t2LDC_OFFSET:
1310 case ARM::t2LDCL_OFFSET:
1311 case ARM::t2LDC_PRE:
1312 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1313 case ARM::t2STC_OFFSET:
1314 case ARM::t2STCL_OFFSET:
1315 case ARM::t2STC_PRE:
1316 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1317 case ARM::LDC_OFFSET:
1318 case ARM::LDCL_OFFSET:
1319 case ARM::LDC_PRE:
1320 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1321 case ARM::STC_OFFSET:
1322 case ARM::STCL_OFFSET:
1323 case ARM::STC_PRE:
1324 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1325 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1326 Inst.addOperand(MCOperand::CreateImm(imm));
1327 break;
1328 case ARM::t2LDC2_POST:
1329 case ARM::t2LDC2L_POST:
1330 case ARM::t2STC2_POST:
1331 case ARM::t2STC2L_POST:
1332 case ARM::LDC2_POST:
1333 case ARM::LDC2L_POST:
1334 case ARM::STC2_POST:
1335 case ARM::STC2L_POST:
1336 case ARM::t2LDC_POST:
1337 case ARM::t2LDCL_POST:
1338 case ARM::t2STC_POST:
1339 case ARM::t2STCL_POST:
1340 case ARM::LDC_POST:
1341 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1342 case ARM::STC_POST:
1343 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1344 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1345 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1346 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1347 // The 'option' variant doesn't encode 'U' in the immediate since
1348 // the immediate is unsigned [0,255].
1349 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1350 break;
1351 }
1352
1353 switch (Inst.getOpcode()) {
1354 case ARM::LDC_OFFSET:
1355 case ARM::LDC_PRE:
1356 case ARM::LDC_POST:
1357 case ARM::LDC_OPTION:
1358 case ARM::LDCL_OFFSET:
1359 case ARM::LDCL_PRE:
1360 case ARM::LDCL_POST:
1361 case ARM::LDCL_OPTION:
1362 case ARM::STC_OFFSET:
1363 case ARM::STC_PRE:
1364 case ARM::STC_POST:
1365 case ARM::STC_OPTION:
1366 case ARM::STCL_OFFSET:
1367 case ARM::STCL_PRE:
1368 case ARM::STCL_POST:
1369 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1370 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1371 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1372 break;
1373 default:
1374 break;
1375 }
1376
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1377 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1378}
1379
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1380static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1381DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1382 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1383 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1384
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1385 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1386 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1387 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1388 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1389 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1390 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1391 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1392 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1393
1394 // On stores, the writeback operand precedes Rt.
1395 switch (Inst.getOpcode()) {
1396 case ARM::STR_POST_IMM:
1397 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1398 case ARM::STRB_POST_IMM:
1399 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1400 case ARM::STRT_POST_REG:
1401 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1402 case ARM::STRBT_POST_REG:
1403 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1405 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1406 break;
1407 default:
1408 break;
1409 }
1410
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1412 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1413
1414 // On loads, the writeback operand comes after Rt.
1415 switch (Inst.getOpcode()) {
1416 case ARM::LDR_POST_IMM:
1417 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1418 case ARM::LDRB_POST_IMM:
1419 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1420 case ARM::LDRBT_POST_REG:
1421 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1422 case ARM::LDRT_POST_REG:
1423 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1425 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1426 break;
1427 default:
1428 break;
1429 }
1430
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1432 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1433
1434 ARM_AM::AddrOpc Op = ARM_AM::add;
1435 if (!fieldFromInstruction32(Insn, 23, 1))
1436 Op = ARM_AM::sub;
1437
1438 bool writeback = (P == 0) || (W == 1);
1439 unsigned idx_mode = 0;
1440 if (P && writeback)
1441 idx_mode = ARMII::IndexModePre;
1442 else if (!P && writeback)
1443 idx_mode = ARMII::IndexModePost;
1444
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1445 if (writeback && (Rn == 15 || Rn == Rt))
1446 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1447
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1448 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1449 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1450 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1451 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1452 switch( fieldFromInstruction32(Insn, 5, 2)) {
1453 case 0:
1454 Opc = ARM_AM::lsl;
1455 break;
1456 case 1:
1457 Opc = ARM_AM::lsr;
1458 break;
1459 case 2:
1460 Opc = ARM_AM::asr;
1461 break;
1462 case 3:
1463 Opc = ARM_AM::ror;
1464 break;
1465 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1466 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1467 }
1468 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1469 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1470
1471 Inst.addOperand(MCOperand::CreateImm(imm));
1472 } else {
1473 Inst.addOperand(MCOperand::CreateReg(0));
1474 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1475 Inst.addOperand(MCOperand::CreateImm(tmp));
1476 }
1477
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1478 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1479 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1480
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1481 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1482}
1483
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1484static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1485 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1486 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1487
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1488 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1489 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1490 unsigned type = fieldFromInstruction32(Val, 5, 2);
1491 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1492 unsigned U = fieldFromInstruction32(Val, 12, 1);
1493
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1494 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1495 switch (type) {
1496 case 0:
1497 ShOp = ARM_AM::lsl;
1498 break;
1499 case 1:
1500 ShOp = ARM_AM::lsr;
1501 break;
1502 case 2:
1503 ShOp = ARM_AM::asr;
1504 break;
1505 case 3:
1506 ShOp = ARM_AM::ror;
1507 break;
1508 }
1509
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1511 return MCDisassembler::Fail;
1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1513 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1514 unsigned shift;
1515 if (U)
1516 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1517 else
1518 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1519 Inst.addOperand(MCOperand::CreateImm(shift));
1520
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1521 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1522}
1523
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1524static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1525DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1526 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1527 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1528
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1529 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1530 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1531 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1532 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1533 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1534 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1535 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1536 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1537 unsigned P = fieldFromInstruction32(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1538 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1539
1540 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1541
1542 // For {LD,ST}RD, Rt must be even, else undefined.
1543 switch (Inst.getOpcode()) {
1544 case ARM::STRD:
1545 case ARM::STRD_PRE:
1546 case ARM::STRD_POST:
1547 case ARM::LDRD:
1548 case ARM::LDRD_PRE:
1549 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1550 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1551 break;
1552 default:
1553 break;
1554 }
1555 switch (Inst.getOpcode()) {
1556 case ARM::STRD:
1557 case ARM::STRD_PRE:
1558 case ARM::STRD_POST:
1559 if (P == 0 && W == 1)
1560 S = MCDisassembler::SoftFail;
1561
1562 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1563 S = MCDisassembler::SoftFail;
1564 if (type && Rm == 15)
1565 S = MCDisassembler::SoftFail;
1566 if (Rt2 == 15)
1567 S = MCDisassembler::SoftFail;
1568 if (!type && fieldFromInstruction32(Insn, 8, 4))
1569 S = MCDisassembler::SoftFail;
1570 break;
1571 case ARM::STRH:
1572 case ARM::STRH_PRE:
1573 case ARM::STRH_POST:
1574 if (Rt == 15)
1575 S = MCDisassembler::SoftFail;
1576 if (writeback && (Rn == 15 || Rn == Rt))
1577 S = MCDisassembler::SoftFail;
1578 if (!type && Rm == 15)
1579 S = MCDisassembler::SoftFail;
1580 break;
1581 case ARM::LDRD:
1582 case ARM::LDRD_PRE:
1583 case ARM::LDRD_POST:
1584 if (type && Rn == 15){
1585 if (Rt2 == 15)
1586 S = MCDisassembler::SoftFail;
1587 break;
1588 }
1589 if (P == 0 && W == 1)
1590 S = MCDisassembler::SoftFail;
1591 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1592 S = MCDisassembler::SoftFail;
1593 if (!type && writeback && Rn == 15)
1594 S = MCDisassembler::SoftFail;
1595 if (writeback && (Rn == Rt || Rn == Rt2))
1596 S = MCDisassembler::SoftFail;
1597 break;
1598 case ARM::LDRH:
1599 case ARM::LDRH_PRE:
1600 case ARM::LDRH_POST:
1601 if (type && Rn == 15){
1602 if (Rt == 15)
1603 S = MCDisassembler::SoftFail;
1604 break;
1605 }
1606 if (Rt == 15)
1607 S = MCDisassembler::SoftFail;
1608 if (!type && Rm == 15)
1609 S = MCDisassembler::SoftFail;
1610 if (!type && writeback && (Rn == 15 || Rn == Rt))
1611 S = MCDisassembler::SoftFail;
1612 break;
1613 case ARM::LDRSH:
1614 case ARM::LDRSH_PRE:
1615 case ARM::LDRSH_POST:
1616 case ARM::LDRSB:
1617 case ARM::LDRSB_PRE:
1618 case ARM::LDRSB_POST:
1619 if (type && Rn == 15){
1620 if (Rt == 15)
1621 S = MCDisassembler::SoftFail;
1622 break;
1623 }
1624 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1625 S = MCDisassembler::SoftFail;
1626 if (!type && (Rt == 15 || Rm == 15))
1627 S = MCDisassembler::SoftFail;
1628 if (!type && writeback && (Rn == 15 || Rn == Rt))
1629 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1630 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1631 default:
1632 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1633 }
1634
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1635 if (writeback) { // Writeback
1636 if (P)
1637 U |= ARMII::IndexModePre << 9;
1638 else
1639 U |= ARMII::IndexModePost << 9;
1640
1641 // On stores, the writeback operand precedes Rt.
1642 switch (Inst.getOpcode()) {
1643 case ARM::STRD:
1644 case ARM::STRD_PRE:
1645 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1646 case ARM::STRH:
1647 case ARM::STRH_PRE:
1648 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1650 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1651 break;
1652 default:
1653 break;
1654 }
1655 }
1656
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1658 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1659 switch (Inst.getOpcode()) {
1660 case ARM::STRD:
1661 case ARM::STRD_PRE:
1662 case ARM::STRD_POST:
1663 case ARM::LDRD:
1664 case ARM::LDRD_PRE:
1665 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1667 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1668 break;
1669 default:
1670 break;
1671 }
1672
1673 if (writeback) {
1674 // On loads, the writeback operand comes after Rt.
1675 switch (Inst.getOpcode()) {
1676 case ARM::LDRD:
1677 case ARM::LDRD_PRE:
1678 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1679 case ARM::LDRH:
1680 case ARM::LDRH_PRE:
1681 case ARM::LDRH_POST:
1682 case ARM::LDRSH:
1683 case ARM::LDRSH_PRE:
1684 case ARM::LDRSH_POST:
1685 case ARM::LDRSB:
1686 case ARM::LDRSB_PRE:
1687 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1688 case ARM::LDRHTr:
1689 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1691 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1692 break;
1693 default:
1694 break;
1695 }
1696 }
1697
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1699 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1700
1701 if (type) {
1702 Inst.addOperand(MCOperand::CreateReg(0));
1703 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1704 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1706 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1707 Inst.addOperand(MCOperand::CreateImm(U));
1708 }
1709
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1710 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1711 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1712
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1713 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1714}
1715
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1716static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1717 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1718 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1719
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1720 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1721 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1722
1723 switch (mode) {
1724 case 0:
1725 mode = ARM_AM::da;
1726 break;
1727 case 1:
1728 mode = ARM_AM::ia;
1729 break;
1730 case 2:
1731 mode = ARM_AM::db;
1732 break;
1733 case 3:
1734 mode = ARM_AM::ib;
1735 break;
1736 }
1737
1738 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1740 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1741
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1742 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1743}
1744
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1745static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1746 unsigned Insn,
1747 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1748 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1749
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1750 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1751 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1752 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1753
1754 if (pred == 0xF) {
1755 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1756 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1757 Inst.setOpcode(ARM::RFEDA);
1758 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1759 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1760 Inst.setOpcode(ARM::RFEDA_UPD);
1761 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1762 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1763 Inst.setOpcode(ARM::RFEDB);
1764 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1765 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1766 Inst.setOpcode(ARM::RFEDB_UPD);
1767 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1768 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1769 Inst.setOpcode(ARM::RFEIA);
1770 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1771 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1772 Inst.setOpcode(ARM::RFEIA_UPD);
1773 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1774 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1775 Inst.setOpcode(ARM::RFEIB);
1776 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1777 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1778 Inst.setOpcode(ARM::RFEIB_UPD);
1779 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1780 case ARM::STMDA:
1781 Inst.setOpcode(ARM::SRSDA);
1782 break;
1783 case ARM::STMDA_UPD:
1784 Inst.setOpcode(ARM::SRSDA_UPD);
1785 break;
1786 case ARM::STMDB:
1787 Inst.setOpcode(ARM::SRSDB);
1788 break;
1789 case ARM::STMDB_UPD:
1790 Inst.setOpcode(ARM::SRSDB_UPD);
1791 break;
1792 case ARM::STMIA:
1793 Inst.setOpcode(ARM::SRSIA);
1794 break;
1795 case ARM::STMIA_UPD:
1796 Inst.setOpcode(ARM::SRSIA_UPD);
1797 break;
1798 case ARM::STMIB:
1799 Inst.setOpcode(ARM::SRSIB);
1800 break;
1801 case ARM::STMIB_UPD:
1802 Inst.setOpcode(ARM::SRSIB_UPD);
1803 break;
1804 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1805 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1806 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1807
1808 // For stores (which become SRS's, the only operand is the mode.
1809 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1810 Inst.addOperand(
1811 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1812 return S;
1813 }
1814
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1815 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1816 }
1817
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1819 return MCDisassembler::Fail;
1820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1821 return MCDisassembler::Fail; // Tied
1822 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1823 return MCDisassembler::Fail;
1824 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1825 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1826
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1827 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1828}
1829
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1830static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1831 uint64_t Address, const void *Decoder) {
1832 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1833 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1834 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1835 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1836
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1837 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1838
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1839 // imod == '01' --> UNPREDICTABLE
1840 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1841 // return failure here. The '01' imod value is unprintable, so there's
1842 // nothing useful we could do even if we returned UNPREDICTABLE.
1843
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1844 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1845
1846 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1847 Inst.setOpcode(ARM::CPS3p);
1848 Inst.addOperand(MCOperand::CreateImm(imod));
1849 Inst.addOperand(MCOperand::CreateImm(iflags));
1850 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1851 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1852 Inst.setOpcode(ARM::CPS2p);
1853 Inst.addOperand(MCOperand::CreateImm(imod));
1854 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1855 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1856 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1857 Inst.setOpcode(ARM::CPS1p);
1858 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1859 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1860 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1861 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1862 Inst.setOpcode(ARM::CPS1p);
1863 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1864 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1865 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1866
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1867 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1868}
1869
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1870static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1871 uint64_t Address, const void *Decoder) {
1872 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1873 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1874 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1875 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1876
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1877 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1878
1879 // imod == '01' --> UNPREDICTABLE
1880 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1881 // return failure here. The '01' imod value is unprintable, so there's
1882 // nothing useful we could do even if we returned UNPREDICTABLE.
1883
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1884 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1885
1886 if (imod && M) {
1887 Inst.setOpcode(ARM::t2CPS3p);
1888 Inst.addOperand(MCOperand::CreateImm(imod));
1889 Inst.addOperand(MCOperand::CreateImm(iflags));
1890 Inst.addOperand(MCOperand::CreateImm(mode));
1891 } else if (imod && !M) {
1892 Inst.setOpcode(ARM::t2CPS2p);
1893 Inst.addOperand(MCOperand::CreateImm(imod));
1894 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1895 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1896 } else if (!imod && M) {
1897 Inst.setOpcode(ARM::t2CPS1p);
1898 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1899 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1900 } else {
1901 // imod == '00' && M == '0' --> UNPREDICTABLE
1902 Inst.setOpcode(ARM::t2CPS1p);
1903 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1904 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1905 }
1906
1907 return S;
1908}
1909
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1910static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1911 uint64_t Address, const void *Decoder) {
1912 DecodeStatus S = MCDisassembler::Success;
1913
1914 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1915 unsigned imm = 0;
1916
1917 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1918 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1919 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1920 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1921
1922 if (Inst.getOpcode() == ARM::t2MOVTi16)
1923 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1924 return MCDisassembler::Fail;
1925 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1926 return MCDisassembler::Fail;
1927
1928 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1929 Inst.addOperand(MCOperand::CreateImm(imm));
1930
1931 return S;
1932}
1933
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1934static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1935 uint64_t Address, const void *Decoder) {
1936 DecodeStatus S = MCDisassembler::Success;
1937
1938 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1939 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1940 unsigned imm = 0;
1941
1942 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1943 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1944
1945 if (Inst.getOpcode() == ARM::MOVTi16)
1946 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1947 return MCDisassembler::Fail;
1948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1949 return MCDisassembler::Fail;
1950
1951 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1952 Inst.addOperand(MCOperand::CreateImm(imm));
1953
1954 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1955 return MCDisassembler::Fail;
1956
1957 return S;
1958}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1959
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1960static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1961 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1962 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1963
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1964 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1965 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1966 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1967 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1968 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1969
1970 if (pred == 0xF)
1971 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1972
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1973 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1974 return MCDisassembler::Fail;
1975 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1976 return MCDisassembler::Fail;
1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1978 return MCDisassembler::Fail;
1979 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1980 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1981
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1982 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1983 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1984
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1985 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1986}
1987
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1988static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1989 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1990 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1991
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1992 unsigned add = fieldFromInstruction32(Val, 12, 1);
1993 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1994 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1995
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1997 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1998
1999 if (!add) imm *= -1;
2000 if (imm == 0 && !add) imm = INT32_MIN;
2001 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2002 if (Rn == 15)
2003 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2004
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2005 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2006}
2007
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2008static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2009 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2010 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2011
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2012 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2013 unsigned U = fieldFromInstruction32(Val, 8, 1);
2014 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2015
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2017 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2018
2019 if (U)
2020 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2021 else
2022 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2023
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2024 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2025}
2026
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2027static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2028 uint64_t Address, const void *Decoder) {
2029 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2030}
2031
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2032static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2033DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2034 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2035 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2036
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2037 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2038 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2039
2040 if (pred == 0xF) {
2041 Inst.setOpcode(ARM::BLXi);
2042 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2043 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2044 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2045 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2046 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2047 }
2048
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2049 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2050 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2051 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2052 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2053 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2054
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2055 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2056}
2057
2058
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2059static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2060 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2061 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2062
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2063 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2064 unsigned align = fieldFromInstruction32(Val, 4, 2);
2065
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2067 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2068 if (!align)
2069 Inst.addOperand(MCOperand::CreateImm(0));
2070 else
2071 Inst.addOperand(MCOperand::CreateImm(4 << align));
2072
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2073 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2074}
2075
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2076static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2077 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2078 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2079
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2080 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2081 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2082 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2083 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2084 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2085 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2086
2087 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2088 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2089 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2090 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2091 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2092 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2093 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2094 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2095 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2096 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2097 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2098 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2099 return MCDisassembler::Fail;
2100 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2101 case ARM::VLD2b16:
2102 case ARM::VLD2b32:
2103 case ARM::VLD2b8:
2104 case ARM::VLD2b16wb_fixed:
2105 case ARM::VLD2b16wb_register:
2106 case ARM::VLD2b32wb_fixed:
2107 case ARM::VLD2b32wb_register:
2108 case ARM::VLD2b8wb_fixed:
2109 case ARM::VLD2b8wb_register:
2110 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2111 return MCDisassembler::Fail;
2112 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2113 default:
2114 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2115 return MCDisassembler::Fail;
2116 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2117
2118 // Second output register
2119 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2120 case ARM::VLD3d8:
2121 case ARM::VLD3d16:
2122 case ARM::VLD3d32:
2123 case ARM::VLD3d8_UPD:
2124 case ARM::VLD3d16_UPD:
2125 case ARM::VLD3d32_UPD:
2126 case ARM::VLD4d8:
2127 case ARM::VLD4d16:
2128 case ARM::VLD4d32:
2129 case ARM::VLD4d8_UPD:
2130 case ARM::VLD4d16_UPD:
2131 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2132 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2133 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2134 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2135 case ARM::VLD3q8:
2136 case ARM::VLD3q16:
2137 case ARM::VLD3q32:
2138 case ARM::VLD3q8_UPD:
2139 case ARM::VLD3q16_UPD:
2140 case ARM::VLD3q32_UPD:
2141 case ARM::VLD4q8:
2142 case ARM::VLD4q16:
2143 case ARM::VLD4q32:
2144 case ARM::VLD4q8_UPD:
2145 case ARM::VLD4q16_UPD:
2146 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2147 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2148 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2149 default:
2150 break;
2151 }
2152
2153 // Third output register
2154 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2155 case ARM::VLD3d8:
2156 case ARM::VLD3d16:
2157 case ARM::VLD3d32:
2158 case ARM::VLD3d8_UPD:
2159 case ARM::VLD3d16_UPD:
2160 case ARM::VLD3d32_UPD:
2161 case ARM::VLD4d8:
2162 case ARM::VLD4d16:
2163 case ARM::VLD4d32:
2164 case ARM::VLD4d8_UPD:
2165 case ARM::VLD4d16_UPD:
2166 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2167 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2168 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2169 break;
2170 case ARM::VLD3q8:
2171 case ARM::VLD3q16:
2172 case ARM::VLD3q32:
2173 case ARM::VLD3q8_UPD:
2174 case ARM::VLD3q16_UPD:
2175 case ARM::VLD3q32_UPD:
2176 case ARM::VLD4q8:
2177 case ARM::VLD4q16:
2178 case ARM::VLD4q32:
2179 case ARM::VLD4q8_UPD:
2180 case ARM::VLD4q16_UPD:
2181 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2182 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2183 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2184 break;
2185 default:
2186 break;
2187 }
2188
2189 // Fourth output register
2190 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2191 case ARM::VLD4d8:
2192 case ARM::VLD4d16:
2193 case ARM::VLD4d32:
2194 case ARM::VLD4d8_UPD:
2195 case ARM::VLD4d16_UPD:
2196 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2197 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2198 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2199 break;
2200 case ARM::VLD4q8:
2201 case ARM::VLD4q16:
2202 case ARM::VLD4q32:
2203 case ARM::VLD4q8_UPD:
2204 case ARM::VLD4q16_UPD:
2205 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2207 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2208 break;
2209 default:
2210 break;
2211 }
2212
2213 // Writeback operand
2214 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2215 case ARM::VLD1d8wb_fixed:
2216 case ARM::VLD1d16wb_fixed:
2217 case ARM::VLD1d32wb_fixed:
2218 case ARM::VLD1d64wb_fixed:
2219 case ARM::VLD1d8wb_register:
2220 case ARM::VLD1d16wb_register:
2221 case ARM::VLD1d32wb_register:
2222 case ARM::VLD1d64wb_register:
2223 case ARM::VLD1q8wb_fixed:
2224 case ARM::VLD1q16wb_fixed:
2225 case ARM::VLD1q32wb_fixed:
2226 case ARM::VLD1q64wb_fixed:
2227 case ARM::VLD1q8wb_register:
2228 case ARM::VLD1q16wb_register:
2229 case ARM::VLD1q32wb_register:
2230 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2231 case ARM::VLD1d8Twb_fixed:
2232 case ARM::VLD1d8Twb_register:
2233 case ARM::VLD1d16Twb_fixed:
2234 case ARM::VLD1d16Twb_register:
2235 case ARM::VLD1d32Twb_fixed:
2236 case ARM::VLD1d32Twb_register:
2237 case ARM::VLD1d64Twb_fixed:
2238 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2239 case ARM::VLD1d8Qwb_fixed:
2240 case ARM::VLD1d8Qwb_register:
2241 case ARM::VLD1d16Qwb_fixed:
2242 case ARM::VLD1d16Qwb_register:
2243 case ARM::VLD1d32Qwb_fixed:
2244 case ARM::VLD1d32Qwb_register:
2245 case ARM::VLD1d64Qwb_fixed:
2246 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2247 case ARM::VLD2d8wb_fixed:
2248 case ARM::VLD2d16wb_fixed:
2249 case ARM::VLD2d32wb_fixed:
2250 case ARM::VLD2q8wb_fixed:
2251 case ARM::VLD2q16wb_fixed:
2252 case ARM::VLD2q32wb_fixed:
2253 case ARM::VLD2d8wb_register:
2254 case ARM::VLD2d16wb_register:
2255 case ARM::VLD2d32wb_register:
2256 case ARM::VLD2q8wb_register:
2257 case ARM::VLD2q16wb_register:
2258 case ARM::VLD2q32wb_register:
2259 case ARM::VLD2b8wb_fixed:
2260 case ARM::VLD2b16wb_fixed:
2261 case ARM::VLD2b32wb_fixed:
2262 case ARM::VLD2b8wb_register:
2263 case ARM::VLD2b16wb_register:
2264 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2265 Inst.addOperand(MCOperand::CreateImm(0));
2266 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2267 case ARM::VLD3d8_UPD:
2268 case ARM::VLD3d16_UPD:
2269 case ARM::VLD3d32_UPD:
2270 case ARM::VLD3q8_UPD:
2271 case ARM::VLD3q16_UPD:
2272 case ARM::VLD3q32_UPD:
2273 case ARM::VLD4d8_UPD:
2274 case ARM::VLD4d16_UPD:
2275 case ARM::VLD4d32_UPD:
2276 case ARM::VLD4q8_UPD:
2277 case ARM::VLD4q16_UPD:
2278 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2279 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2280 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2281 break;
2282 default:
2283 break;
2284 }
2285
2286 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2287 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2288 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2289
2290 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2291 switch (Inst.getOpcode()) {
2292 default:
2293 // The below have been updated to have explicit am6offset split
2294 // between fixed and register offset. For those instructions not
2295 // yet updated, we need to add an additional reg0 operand for the
2296 // fixed variant.
2297 //
2298 // The fixed offset encodes as Rm == 0xd, so we check for that.
2299 if (Rm == 0xd) {
2300 Inst.addOperand(MCOperand::CreateReg(0));
2301 break;
2302 }
2303 // Fall through to handle the register offset variant.
2304 case ARM::VLD1d8wb_fixed:
2305 case ARM::VLD1d16wb_fixed:
2306 case ARM::VLD1d32wb_fixed:
2307 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2308 case ARM::VLD1d8Twb_fixed:
2309 case ARM::VLD1d16Twb_fixed:
2310 case ARM::VLD1d32Twb_fixed:
2311 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2312 case ARM::VLD1d8Qwb_fixed:
2313 case ARM::VLD1d16Qwb_fixed:
2314 case ARM::VLD1d32Qwb_fixed:
2315 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2316 case ARM::VLD1d8wb_register:
2317 case ARM::VLD1d16wb_register:
2318 case ARM::VLD1d32wb_register:
2319 case ARM::VLD1d64wb_register:
2320 case ARM::VLD1q8wb_fixed:
2321 case ARM::VLD1q16wb_fixed:
2322 case ARM::VLD1q32wb_fixed:
2323 case ARM::VLD1q64wb_fixed:
2324 case ARM::VLD1q8wb_register:
2325 case ARM::VLD1q16wb_register:
2326 case ARM::VLD1q32wb_register:
2327 case ARM::VLD1q64wb_register:
2328 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2329 // variant encodes Rm == 0xf. Anything else is a register offset post-
2330 // increment and we need to add the register operand to the instruction.
2331 if (Rm != 0xD && Rm != 0xF &&
2332 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2333 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2334 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2335 case ARM::VLD2d8wb_fixed:
2336 case ARM::VLD2d16wb_fixed:
2337 case ARM::VLD2d32wb_fixed:
2338 case ARM::VLD2b8wb_fixed:
2339 case ARM::VLD2b16wb_fixed:
2340 case ARM::VLD2b32wb_fixed:
2341 case ARM::VLD2q8wb_fixed:
2342 case ARM::VLD2q16wb_fixed:
2343 case ARM::VLD2q32wb_fixed:
2344 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2345 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2346
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2347 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2348}
2349
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2350static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2351 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2352 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2353
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2354 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2355 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2356 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2357 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2358 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2359 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2360
2361 // Writeback Operand
2362 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2363 case ARM::VST1d8wb_fixed:
2364 case ARM::VST1d16wb_fixed:
2365 case ARM::VST1d32wb_fixed:
2366 case ARM::VST1d64wb_fixed:
2367 case ARM::VST1d8wb_register:
2368 case ARM::VST1d16wb_register:
2369 case ARM::VST1d32wb_register:
2370 case ARM::VST1d64wb_register:
2371 case ARM::VST1q8wb_fixed:
2372 case ARM::VST1q16wb_fixed:
2373 case ARM::VST1q32wb_fixed:
2374 case ARM::VST1q64wb_fixed:
2375 case ARM::VST1q8wb_register:
2376 case ARM::VST1q16wb_register:
2377 case ARM::VST1q32wb_register:
2378 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2379 case ARM::VST1d8Twb_fixed:
2380 case ARM::VST1d16Twb_fixed:
2381 case ARM::VST1d32Twb_fixed:
2382 case ARM::VST1d64Twb_fixed:
2383 case ARM::VST1d8Twb_register:
2384 case ARM::VST1d16Twb_register:
2385 case ARM::VST1d32Twb_register:
2386 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2387 case ARM::VST1d8Qwb_fixed:
2388 case ARM::VST1d16Qwb_fixed:
2389 case ARM::VST1d32Qwb_fixed:
2390 case ARM::VST1d64Qwb_fixed:
2391 case ARM::VST1d8Qwb_register:
2392 case ARM::VST1d16Qwb_register:
2393 case ARM::VST1d32Qwb_register:
2394 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2395 case ARM::VST2d8wb_fixed:
2396 case ARM::VST2d16wb_fixed:
2397 case ARM::VST2d32wb_fixed:
2398 case ARM::VST2d8wb_register:
2399 case ARM::VST2d16wb_register:
2400 case ARM::VST2d32wb_register:
2401 case ARM::VST2q8wb_fixed:
2402 case ARM::VST2q16wb_fixed:
2403 case ARM::VST2q32wb_fixed:
2404 case ARM::VST2q8wb_register:
2405 case ARM::VST2q16wb_register:
2406 case ARM::VST2q32wb_register:
2407 case ARM::VST2b8wb_fixed:
2408 case ARM::VST2b16wb_fixed:
2409 case ARM::VST2b32wb_fixed:
2410 case ARM::VST2b8wb_register:
2411 case ARM::VST2b16wb_register:
2412 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame^]2413 if (Rm == 0xF)
2414 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2415 Inst.addOperand(MCOperand::CreateImm(0));
2416 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2417 case ARM::VST3d8_UPD:
2418 case ARM::VST3d16_UPD:
2419 case ARM::VST3d32_UPD:
2420 case ARM::VST3q8_UPD:
2421 case ARM::VST3q16_UPD:
2422 case ARM::VST3q32_UPD:
2423 case ARM::VST4d8_UPD:
2424 case ARM::VST4d16_UPD:
2425 case ARM::VST4d32_UPD:
2426 case ARM::VST4q8_UPD:
2427 case ARM::VST4q16_UPD:
2428 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2429 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2430 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2431 break;
2432 default:
2433 break;
2434 }
2435
2436 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2437 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2438 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2439
2440 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2441 switch (Inst.getOpcode()) {
2442 default:
2443 if (Rm == 0xD)
2444 Inst.addOperand(MCOperand::CreateReg(0));
2445 else if (Rm != 0xF) {
2446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2447 return MCDisassembler::Fail;
2448 }
2449 break;
2450 case ARM::VST1d8wb_fixed:
2451 case ARM::VST1d16wb_fixed:
2452 case ARM::VST1d32wb_fixed:
2453 case ARM::VST1d64wb_fixed:
2454 case ARM::VST1q8wb_fixed:
2455 case ARM::VST1q16wb_fixed:
2456 case ARM::VST1q32wb_fixed:
2457 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2458 case ARM::VST1d8Twb_fixed:
2459 case ARM::VST1d16Twb_fixed:
2460 case ARM::VST1d32Twb_fixed:
2461 case ARM::VST1d64Twb_fixed:
2462 case ARM::VST1d8Qwb_fixed:
2463 case ARM::VST1d16Qwb_fixed:
2464 case ARM::VST1d32Qwb_fixed:
2465 case ARM::VST1d64Qwb_fixed:
2466 case ARM::VST2d8wb_fixed:
2467 case ARM::VST2d16wb_fixed:
2468 case ARM::VST2d32wb_fixed:
2469 case ARM::VST2q8wb_fixed:
2470 case ARM::VST2q16wb_fixed:
2471 case ARM::VST2q32wb_fixed:
2472 case ARM::VST2b8wb_fixed:
2473 case ARM::VST2b16wb_fixed:
2474 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2475 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2476 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2477
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2478
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2479 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2480 switch (Inst.getOpcode()) {
2481 case ARM::VST1q16:
2482 case ARM::VST1q32:
2483 case ARM::VST1q64:
2484 case ARM::VST1q8:
2485 case ARM::VST1q16wb_fixed:
2486 case ARM::VST1q16wb_register:
2487 case ARM::VST1q32wb_fixed:
2488 case ARM::VST1q32wb_register:
2489 case ARM::VST1q64wb_fixed:
2490 case ARM::VST1q64wb_register:
2491 case ARM::VST1q8wb_fixed:
2492 case ARM::VST1q8wb_register:
2493 case ARM::VST2d16:
2494 case ARM::VST2d32:
2495 case ARM::VST2d8:
2496 case ARM::VST2d16wb_fixed:
2497 case ARM::VST2d16wb_register:
2498 case ARM::VST2d32wb_fixed:
2499 case ARM::VST2d32wb_register:
2500 case ARM::VST2d8wb_fixed:
2501 case ARM::VST2d8wb_register:
2502 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2503 return MCDisassembler::Fail;
2504 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2505 case ARM::VST2b16:
2506 case ARM::VST2b32:
2507 case ARM::VST2b8:
2508 case ARM::VST2b16wb_fixed:
2509 case ARM::VST2b16wb_register:
2510 case ARM::VST2b32wb_fixed:
2511 case ARM::VST2b32wb_register:
2512 case ARM::VST2b8wb_fixed:
2513 case ARM::VST2b8wb_register:
2514 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2515 return MCDisassembler::Fail;
2516 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2517 default:
2518 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2519 return MCDisassembler::Fail;
2520 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2521
2522 // Second input register
2523 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2524 case ARM::VST3d8:
2525 case ARM::VST3d16:
2526 case ARM::VST3d32:
2527 case ARM::VST3d8_UPD:
2528 case ARM::VST3d16_UPD:
2529 case ARM::VST3d32_UPD:
2530 case ARM::VST4d8:
2531 case ARM::VST4d16:
2532 case ARM::VST4d32:
2533 case ARM::VST4d8_UPD:
2534 case ARM::VST4d16_UPD:
2535 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2536 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2537 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2538 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2539 case ARM::VST3q8:
2540 case ARM::VST3q16:
2541 case ARM::VST3q32:
2542 case ARM::VST3q8_UPD:
2543 case ARM::VST3q16_UPD:
2544 case ARM::VST3q32_UPD:
2545 case ARM::VST4q8:
2546 case ARM::VST4q16:
2547 case ARM::VST4q32:
2548 case ARM::VST4q8_UPD:
2549 case ARM::VST4q16_UPD:
2550 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2551 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2552 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2553 break;
2554 default:
2555 break;
2556 }
2557
2558 // Third input register
2559 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2560 case ARM::VST3d8:
2561 case ARM::VST3d16:
2562 case ARM::VST3d32:
2563 case ARM::VST3d8_UPD:
2564 case ARM::VST3d16_UPD:
2565 case ARM::VST3d32_UPD:
2566 case ARM::VST4d8:
2567 case ARM::VST4d16:
2568 case ARM::VST4d32:
2569 case ARM::VST4d8_UPD:
2570 case ARM::VST4d16_UPD:
2571 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2572 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2573 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2574 break;
2575 case ARM::VST3q8:
2576 case ARM::VST3q16:
2577 case ARM::VST3q32:
2578 case ARM::VST3q8_UPD:
2579 case ARM::VST3q16_UPD:
2580 case ARM::VST3q32_UPD:
2581 case ARM::VST4q8:
2582 case ARM::VST4q16:
2583 case ARM::VST4q32:
2584 case ARM::VST4q8_UPD:
2585 case ARM::VST4q16_UPD:
2586 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2587 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2588 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2589 break;
2590 default:
2591 break;
2592 }
2593
2594 // Fourth input register
2595 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2596 case ARM::VST4d8:
2597 case ARM::VST4d16:
2598 case ARM::VST4d32:
2599 case ARM::VST4d8_UPD:
2600 case ARM::VST4d16_UPD:
2601 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2602 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2603 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2604 break;
2605 case ARM::VST4q8:
2606 case ARM::VST4q16:
2607 case ARM::VST4q32:
2608 case ARM::VST4q8_UPD:
2609 case ARM::VST4q16_UPD:
2610 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2611 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2612 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2613 break;
2614 default:
2615 break;
2616 }
2617
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2618 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2619}
2620
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2621static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2622 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2623 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2624
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2625 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2626 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2627 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2628 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2629 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2630 unsigned size = fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2631
2632 align *= (1 << size);
2633
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2634 switch (Inst.getOpcode()) {
2635 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2636 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2637 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2638 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2639 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2640 return MCDisassembler::Fail;
2641 break;
2642 default:
2643 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2644 return MCDisassembler::Fail;
2645 break;
2646 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2647 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2649 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2650 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2651
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2653 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2654 Inst.addOperand(MCOperand::CreateImm(align));
2655
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2656 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2657 // variant encodes Rm == 0xf. Anything else is a register offset post-
2658 // increment and we need to add the register operand to the instruction.
2659 if (Rm != 0xD && Rm != 0xF &&
2660 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2661 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2662
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2663 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2664}
2665
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2666static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2667 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2668 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2669
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2671 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2672 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2673 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2674 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2675 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2676 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2677 align *= 2*size;
2678
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2679 switch (Inst.getOpcode()) {
2680 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2681 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2682 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2683 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2684 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2685 return MCDisassembler::Fail;
2686 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2687 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2688 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2689 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2690 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2691 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2692 return MCDisassembler::Fail;
2693 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2694 default:
2695 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2696 return MCDisassembler::Fail;
2697 break;
2698 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2699
2700 if (Rm != 0xF)
2701 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2702
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2704 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2705 Inst.addOperand(MCOperand::CreateImm(align));
2706
2707 if (Rm == 0xD)
2708 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2709 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2711 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2712 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2713
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2714 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2715 return MCDisassembler::Fail;
2716
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2717 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2718}
2719
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2720static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2721 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2722 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2723
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2724 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2725 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2726 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2727 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2728 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2729
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2731 return MCDisassembler::Fail;
2732 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2733 return MCDisassembler::Fail;
2734 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2735 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2736 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2738 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2739 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2740
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2742 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2743 Inst.addOperand(MCOperand::CreateImm(0));
2744
2745 if (Rm == 0xD)
2746 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2747 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2749 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2750 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2751
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2752 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2753}
2754
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2755static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2756 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2757 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2758
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2759 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2760 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2761 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2762 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2763 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2764 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2765 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2766
2767 if (size == 0x3) {
2768 size = 4;
2769 align = 16;
2770 } else {
2771 if (size == 2) {
2772 size = 1 << size;
2773 align *= 8;
2774 } else {
2775 size = 1 << size;
2776 align *= 4*size;
2777 }
2778 }
2779
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2781 return MCDisassembler::Fail;
2782 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2783 return MCDisassembler::Fail;
2784 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2785 return MCDisassembler::Fail;
2786 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2787 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2788 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2790 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2791 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2792
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2794 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2795 Inst.addOperand(MCOperand::CreateImm(align));
2796
2797 if (Rm == 0xD)
2798 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2799 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2801 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2802 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2803
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2804 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2805}
2806
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2807static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2808DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2809 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2810 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2811
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2812 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2813 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2814 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2815 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2816 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2817 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2818 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2819 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2820
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2821 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2822 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2823 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2824 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2825 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2826 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2827 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2828
2829 Inst.addOperand(MCOperand::CreateImm(imm));
2830
2831 switch (Inst.getOpcode()) {
2832 case ARM::VORRiv4i16:
2833 case ARM::VORRiv2i32:
2834 case ARM::VBICiv4i16:
2835 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2836 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2837 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2838 break;
2839 case ARM::VORRiv8i16:
2840 case ARM::VORRiv4i32:
2841 case ARM::VBICiv8i16:
2842 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2843 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2844 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2845 break;
2846 default:
2847 break;
2848 }
2849
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2850 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2851}
2852
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2853static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2854 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2855 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2856
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2857 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2858 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2859 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2860 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2861 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2862
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2863 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2864 return MCDisassembler::Fail;
2865 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2866 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2867 Inst.addOperand(MCOperand::CreateImm(8 << size));
2868
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2869 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2870}
2871
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2872static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2873 uint64_t Address, const void *Decoder) {
2874 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2875 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2876}
2877
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2878static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2879 uint64_t Address, const void *Decoder) {
2880 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2881 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2882}
2883
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2884static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2885 uint64_t Address, const void *Decoder) {
2886 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2887 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2888}
2889
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2890static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2891 uint64_t Address, const void *Decoder) {
2892 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2893 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2894}
2895
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2896static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2897 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2898 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2899
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2901 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2902 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2903 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2904 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2905 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2906 unsigned op = fieldFromInstruction32(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2909 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2910 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2911 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2912 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2913 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2914
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2915 switch (Inst.getOpcode()) {
2916 case ARM::VTBL2:
2917 case ARM::VTBX2:
2918 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2919 return MCDisassembler::Fail;
2920 break;
2921 default:
2922 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2923 return MCDisassembler::Fail;
2924 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2925
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2926 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2927 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2928
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2929 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2930}
2931
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2932static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2933 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2934 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2935
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2936 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2937 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2938
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2939 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2940 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2941
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2942 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2943 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2944 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2945 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2946 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2947 case ARM::tADDrSPi:
2948 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2949 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2950 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2951
2952 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2953 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2954}
2955
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2956static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2957 uint64_t Address, const void *Decoder) {
2958 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2959 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2960}
2961
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2962static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2963 uint64_t Address, const void *Decoder) {
2964 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2965 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2966}
2967
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2968static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2969 uint64_t Address, const void *Decoder) {
2970 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2971 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2972}
2973
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2974static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2975 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2976 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2977
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2978 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2979 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2980
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2981 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2982 return MCDisassembler::Fail;
2983 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2984 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2985
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2986 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2987}
2988
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2989static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2990 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2991 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2992
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2993 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2994 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2995
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2996 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2997 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2998 Inst.addOperand(MCOperand::CreateImm(imm));
2999
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3000 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3001}
3002
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3003static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3004 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3005 unsigned imm = Val << 2;
3006
3007 Inst.addOperand(MCOperand::CreateImm(imm));
3008 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3009
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3010 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3011}
3012
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3013static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3014 uint64_t Address, const void *Decoder) {
3015 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3016 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3017
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3018 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3019}
3020
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3021static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3022 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3023 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3024
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3025 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3026 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3027 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3028
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3030 return MCDisassembler::Fail;
3031 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3032 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3033 Inst.addOperand(MCOperand::CreateImm(imm));
3034
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3035 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3036}
3037
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3038static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3039 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3040 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3041
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3042 switch (Inst.getOpcode()) {
3043 case ARM::t2PLDs:
3044 case ARM::t2PLDWs:
3045 case ARM::t2PLIs:
3046 break;
3047 default: {
3048 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3049 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3050 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3051 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3052 }
3053
3054 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3055 if (Rn == 0xF) {
3056 switch (Inst.getOpcode()) {
3057 case ARM::t2LDRBs:
3058 Inst.setOpcode(ARM::t2LDRBpci);
3059 break;
3060 case ARM::t2LDRHs:
3061 Inst.setOpcode(ARM::t2LDRHpci);
3062 break;
3063 case ARM::t2LDRSHs:
3064 Inst.setOpcode(ARM::t2LDRSHpci);
3065 break;
3066 case ARM::t2LDRSBs:
3067 Inst.setOpcode(ARM::t2LDRSBpci);
3068 break;
3069 case ARM::t2PLDs:
3070 Inst.setOpcode(ARM::t2PLDi12);
3071 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3072 break;
3073 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3074 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3075 }
3076
3077 int imm = fieldFromInstruction32(Insn, 0, 12);
3078 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3079 Inst.addOperand(MCOperand::CreateImm(imm));
3080
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3081 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3082 }
3083
3084 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3085 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3086 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3087 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3088 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3089
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3090 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3091}
3092
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3093static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3094 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3095 int imm = Val & 0xFF;
3096 if (!(Val & 0x100)) imm *= -1;
3097 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3098
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3099 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3100}
3101
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3102static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3103 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3104 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3105
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3106 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3107 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3108
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3110 return MCDisassembler::Fail;
3111 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3112 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3113
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3114 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3115}
3116
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3117static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3118 uint64_t Address, const void *Decoder) {
3119 DecodeStatus S = MCDisassembler::Success;
3120
3121 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3122 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3123
3124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3125 return MCDisassembler::Fail;
3126
3127 Inst.addOperand(MCOperand::CreateImm(imm));
3128
3129 return S;
3130}
3131
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3132static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3133 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3134 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3135 if (Val == 0)
3136 imm = INT32_MIN;
3137 else if (!(Val & 0x100))
3138 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3139 Inst.addOperand(MCOperand::CreateImm(imm));
3140
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3141 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3142}
3143
3144
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3145static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3146 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3147 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3148
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3149 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3150 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3151
3152 // Some instructions always use an additive offset.
3153 switch (Inst.getOpcode()) {
3154 case ARM::t2LDRT:
3155 case ARM::t2LDRBT:
3156 case ARM::t2LDRHT:
3157 case ARM::t2LDRSBT:
3158 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3159 case ARM::t2STRT:
3160 case ARM::t2STRBT:
3161 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3162 imm |= 0x100;
3163 break;
3164 default:
3165 break;
3166 }
3167
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3169 return MCDisassembler::Fail;
3170 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3171 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3172
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3173 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3174}
3175
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3176static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3177 uint64_t Address, const void *Decoder) {
3178 DecodeStatus S = MCDisassembler::Success;
3179
3180 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3181 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3182 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3183 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3184 addr |= Rn << 9;
3185 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3186
3187 if (!load) {
3188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3189 return MCDisassembler::Fail;
3190 }
3191
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]3192 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3193 return MCDisassembler::Fail;
3194
3195 if (load) {
3196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3197 return MCDisassembler::Fail;
3198 }
3199
3200 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3201 return MCDisassembler::Fail;
3202
3203 return S;
3204}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3205
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3206static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3207 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3208 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3209
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3210 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3211 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3212
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3214 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3215 Inst.addOperand(MCOperand::CreateImm(imm));
3216
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3217 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3218}
3219
3220
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3221static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3222 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3223 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3224
3225 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3226 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3227 Inst.addOperand(MCOperand::CreateImm(imm));
3228
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3229 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3230}
3231
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3232static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3233 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3234 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3235
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3236 if (Inst.getOpcode() == ARM::tADDrSP) {
3237 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3238 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3239
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3241 return MCDisassembler::Fail;
3242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3243 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3244 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3245 } else if (Inst.getOpcode() == ARM::tADDspr) {
3246 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3247
3248 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3249 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3251 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3252 }
3253
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3254 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3255}
3256
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3257static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3258 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3259 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3260 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3261
3262 Inst.addOperand(MCOperand::CreateImm(imod));
3263 Inst.addOperand(MCOperand::CreateImm(flags));
3264
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3265 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3266}
3267
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3268static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3269 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3270 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3271 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3272 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3273
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3274 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3275 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3276 Inst.addOperand(MCOperand::CreateImm(add));
3277
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3278 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3279}
3280
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3281static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3282 uint64_t Address, const void *Decoder) {
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3283 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3284 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3285 true, 4, Inst, Decoder))
3286 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3287 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3288}
3289
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3290static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3291 uint64_t Address, const void *Decoder) {
3292 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3293 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3294
3295 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3296 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3297}
3298
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3299static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3300DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3301 uint64_t Address, const void *Decoder) {
3302 DecodeStatus S = MCDisassembler::Success;
3303
3304 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3305 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3306
3307 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3309 return MCDisassembler::Fail;
3310 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3311 return MCDisassembler::Fail;
3312 return S;
3313}
3314
3315static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3316DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3317 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3318 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3319
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3320 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3321 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3322 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3323 switch (opc) {
3324 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3325 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3326 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3327 Inst.setOpcode(ARM::t2DSB);
3328 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3329 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3330 Inst.setOpcode(ARM::t2DMB);
3331 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3332 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3333 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3334 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3335 }
3336
3337 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3338 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3339 }
3340
3341 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3342 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3343 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3344 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3345 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3346
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3347 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3348 return MCDisassembler::Fail;
3349 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3350 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3351
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3352 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3353}
3354
3355// Decode a shifted immediate operand. These basically consist
3356// of an 8-bit value, and a 4-bit directive that specifies either
3357// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3358static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3359 uint64_t Address, const void *Decoder) {
3360 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3361 if (ctrl == 0) {
3362 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3363 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3364 switch (byte) {
3365 case 0:
3366 Inst.addOperand(MCOperand::CreateImm(imm));
3367 break;
3368 case 1:
3369 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3370 break;
3371 case 2:
3372 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3373 break;
3374 case 3:
3375 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3376 (imm << 8) | imm));
3377 break;
3378 }
3379 } else {
3380 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3381 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3382 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3383 Inst.addOperand(MCOperand::CreateImm(imm));
3384 }
3385
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3386 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3387}
3388
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3389static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3390DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3391 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3392 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3393 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3394}
3395
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3396static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3397 uint64_t Address, const void *Decoder){
Kevin Enderby09433032012-02-27 18:15:15 +0000[diff] [blame]3398 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3399 true, 4, Inst, Decoder))
3400 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3401 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3402}
3403
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3404static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3405 uint64_t Address, const void *Decoder) {
3406 switch (Val) {
3407 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3408 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3409 case 0xF: // SY
3410 case 0xE: // ST
3411 case 0xB: // ISH
3412 case 0xA: // ISHST
3413 case 0x7: // NSH
3414 case 0x6: // NSHST
3415 case 0x3: // OSH
3416 case 0x2: // OSHST
3417 break;
3418 }
3419
3420 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3421 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3422}
3423
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3424static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3425 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3426 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3427 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3428 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3429}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3430
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3431static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3432 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3433 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3434
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3435 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3436 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3437 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3438
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3439 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3440
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3442 return MCDisassembler::Fail;
3443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3444 return MCDisassembler::Fail;
3445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3446 return MCDisassembler::Fail;
3447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3448 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3449
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3450 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3451}
3452
3453
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3454static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3455 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3456 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3457
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3458 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3459 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3460 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3461 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3462
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3463 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3464 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3465
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3466 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3467 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3468
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3470 return MCDisassembler::Fail;
3471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3472 return MCDisassembler::Fail;
3473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3474 return MCDisassembler::Fail;
3475 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3476 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3477
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3478 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3479}
3480
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3481static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3482 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3483 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3484
3485 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3486 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3487 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3488 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3489 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3490 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3491
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3492 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3493
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3495 return MCDisassembler::Fail;
3496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3497 return MCDisassembler::Fail;
3498 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3499 return MCDisassembler::Fail;
3500 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3501 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3502
3503 return S;
3504}
3505
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3506static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3507 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3508 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3509
3510 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3511 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3512 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3513 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3514 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3515 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3516 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3517
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3518 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3519 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3520
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3522 return MCDisassembler::Fail;
3523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3524 return MCDisassembler::Fail;
3525 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3526 return MCDisassembler::Fail;
3527 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3528 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3529
3530 return S;
3531}
3532
3533
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3534static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3535 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3536 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3537
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3538 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3539 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3540 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3541 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3542 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3543 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3544
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3545 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3546
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3548 return MCDisassembler::Fail;
3549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3550 return MCDisassembler::Fail;
3551 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3552 return MCDisassembler::Fail;
3553 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3554 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3555
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3556 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3557}
3558
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3559static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3560 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3561 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3562
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3563 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3564 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3565 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3566 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3567 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3568 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3569
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3570 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3571
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3573 return MCDisassembler::Fail;
3574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3575 return MCDisassembler::Fail;
3576 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3577 return MCDisassembler::Fail;
3578 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3579 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3580
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3581 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3582}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3583
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3584static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3585 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3586 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3587
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3588 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3589 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3590 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3591 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3592 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3593
3594 unsigned align = 0;
3595 unsigned index = 0;
3596 switch (size) {
3597 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3598 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3599 case 0:
3600 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3601 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3602 index = fieldFromInstruction32(Insn, 5, 3);
3603 break;
3604 case 1:
3605 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3606 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3607 index = fieldFromInstruction32(Insn, 6, 2);
3608 if (fieldFromInstruction32(Insn, 4, 1))
3609 align = 2;
3610 break;
3611 case 2:
3612 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3613 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3614 index = fieldFromInstruction32(Insn, 7, 1);
3615 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3616 align = 4;
3617 }
3618
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3619 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3620 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3621 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3623 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3624 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3626 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3627 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3628 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3629 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3631 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3632 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3633 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3634 }
3635
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3636 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3637 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3638 Inst.addOperand(MCOperand::CreateImm(index));
3639
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3640 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3641}
3642
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3643static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3644 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3645 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3646
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3647 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3648 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3649 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3650 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3651 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3652
3653 unsigned align = 0;
3654 unsigned index = 0;
3655 switch (size) {
3656 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3657 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3658 case 0:
3659 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3660 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3661 index = fieldFromInstruction32(Insn, 5, 3);
3662 break;
3663 case 1:
3664 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3665 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3666 index = fieldFromInstruction32(Insn, 6, 2);
3667 if (fieldFromInstruction32(Insn, 4, 1))
3668 align = 2;
3669 break;
3670 case 2:
3671 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3672 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3673 index = fieldFromInstruction32(Insn, 7, 1);
3674 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3675 align = 4;
3676 }
3677
3678 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3680 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3681 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3683 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3684 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3685 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3686 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3688 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3689 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3690 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3691 }
3692
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3693 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3694 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3695 Inst.addOperand(MCOperand::CreateImm(index));
3696
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3697 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3698}
3699
3700
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3701static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3702 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3703 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3704
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3705 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3706 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3707 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3708 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3709 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3710
3711 unsigned align = 0;
3712 unsigned index = 0;
3713 unsigned inc = 1;
3714 switch (size) {
3715 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3716 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3717 case 0:
3718 index = fieldFromInstruction32(Insn, 5, 3);
3719 if (fieldFromInstruction32(Insn, 4, 1))
3720 align = 2;
3721 break;
3722 case 1:
3723 index = fieldFromInstruction32(Insn, 6, 2);
3724 if (fieldFromInstruction32(Insn, 4, 1))
3725 align = 4;
3726 if (fieldFromInstruction32(Insn, 5, 1))
3727 inc = 2;
3728 break;
3729 case 2:
3730 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3731 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3732 index = fieldFromInstruction32(Insn, 7, 1);
3733 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3734 align = 8;
3735 if (fieldFromInstruction32(Insn, 6, 1))
3736 inc = 2;
3737 break;
3738 }
3739
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3741 return MCDisassembler::Fail;
3742 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3743 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3744 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3746 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3747 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3749 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3750 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3751 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3752 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3754 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3755 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3756 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3757 }
3758
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3760 return MCDisassembler::Fail;
3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3762 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3763 Inst.addOperand(MCOperand::CreateImm(index));
3764
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3765 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3766}
3767
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3768static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3769 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3770 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3771
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3772 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3773 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3774 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3775 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3776 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3777
3778 unsigned align = 0;
3779 unsigned index = 0;
3780 unsigned inc = 1;
3781 switch (size) {
3782 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3783 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3784 case 0:
3785 index = fieldFromInstruction32(Insn, 5, 3);
3786 if (fieldFromInstruction32(Insn, 4, 1))
3787 align = 2;
3788 break;
3789 case 1:
3790 index = fieldFromInstruction32(Insn, 6, 2);
3791 if (fieldFromInstruction32(Insn, 4, 1))
3792 align = 4;
3793 if (fieldFromInstruction32(Insn, 5, 1))
3794 inc = 2;
3795 break;
3796 case 2:
3797 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3798 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3799 index = fieldFromInstruction32(Insn, 7, 1);
3800 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3801 align = 8;
3802 if (fieldFromInstruction32(Insn, 6, 1))
3803 inc = 2;
3804 break;
3805 }
3806
3807 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3809 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3810 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3812 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3813 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3814 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3815 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3817 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3818 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3819 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3820 }
3821
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3823 return MCDisassembler::Fail;
3824 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3825 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3826 Inst.addOperand(MCOperand::CreateImm(index));
3827
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3828 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3829}
3830
3831
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3832static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3833 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3834 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3835
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3836 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3837 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3838 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3839 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3840 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3841
3842 unsigned align = 0;
3843 unsigned index = 0;
3844 unsigned inc = 1;
3845 switch (size) {
3846 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3847 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3848 case 0:
3849 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3850 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3851 index = fieldFromInstruction32(Insn, 5, 3);
3852 break;
3853 case 1:
3854 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3855 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3856 index = fieldFromInstruction32(Insn, 6, 2);
3857 if (fieldFromInstruction32(Insn, 5, 1))
3858 inc = 2;
3859 break;
3860 case 2:
3861 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3862 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3863 index = fieldFromInstruction32(Insn, 7, 1);
3864 if (fieldFromInstruction32(Insn, 6, 1))
3865 inc = 2;
3866 break;
3867 }
3868
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3870 return MCDisassembler::Fail;
3871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3872 return MCDisassembler::Fail;
3873 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3874 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3875
3876 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3878 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3879 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3881 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3882 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3883 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3884 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3885 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3886 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3887 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3888 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3889 }
3890
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3892 return MCDisassembler::Fail;
3893 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3894 return MCDisassembler::Fail;
3895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3896 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3897 Inst.addOperand(MCOperand::CreateImm(index));
3898
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3899 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3900}
3901
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3902static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3903 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3904 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3905
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3906 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3907 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3908 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3909 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3910 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3911
3912 unsigned align = 0;
3913 unsigned index = 0;
3914 unsigned inc = 1;
3915 switch (size) {
3916 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3917 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3918 case 0:
3919 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3920 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3921 index = fieldFromInstruction32(Insn, 5, 3);
3922 break;
3923 case 1:
3924 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3925 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3926 index = fieldFromInstruction32(Insn, 6, 2);
3927 if (fieldFromInstruction32(Insn, 5, 1))
3928 inc = 2;
3929 break;
3930 case 2:
3931 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3932 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3933 index = fieldFromInstruction32(Insn, 7, 1);
3934 if (fieldFromInstruction32(Insn, 6, 1))
3935 inc = 2;
3936 break;
3937 }
3938
3939 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3941 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3942 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3944 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3945 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3946 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3947 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3949 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3950 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3951 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3952 }
3953
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3954 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3955 return MCDisassembler::Fail;
3956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3957 return MCDisassembler::Fail;
3958 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3959 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3960 Inst.addOperand(MCOperand::CreateImm(index));
3961
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3962 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3963}
3964
3965
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3966static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3967 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3968 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3969
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3970 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3971 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3972 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3973 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3974 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3975
3976 unsigned align = 0;
3977 unsigned index = 0;
3978 unsigned inc = 1;
3979 switch (size) {
3980 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3981 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3982 case 0:
3983 if (fieldFromInstruction32(Insn, 4, 1))
3984 align = 4;
3985 index = fieldFromInstruction32(Insn, 5, 3);
3986 break;
3987 case 1:
3988 if (fieldFromInstruction32(Insn, 4, 1))
3989 align = 8;
3990 index = fieldFromInstruction32(Insn, 6, 2);
3991 if (fieldFromInstruction32(Insn, 5, 1))
3992 inc = 2;
3993 break;
3994 case 2:
3995 if (fieldFromInstruction32(Insn, 4, 2))
3996 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3997 index = fieldFromInstruction32(Insn, 7, 1);
3998 if (fieldFromInstruction32(Insn, 6, 1))
3999 inc = 2;
4000 break;
4001 }
4002
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4004 return MCDisassembler::Fail;
4005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4006 return MCDisassembler::Fail;
4007 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4008 return MCDisassembler::Fail;
4009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4010 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4011
4012 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4014 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4015 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4017 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4018 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4019 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4020 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4022 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4023 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4024 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4025 }
4026
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4027 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4028 return MCDisassembler::Fail;
4029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4030 return MCDisassembler::Fail;
4031 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4032 return MCDisassembler::Fail;
4033 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4034 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4035 Inst.addOperand(MCOperand::CreateImm(index));
4036
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4037 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4038}
4039
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4040static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4041 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4042 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4043
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4044 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4045 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4046 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4047 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4048 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4049
4050 unsigned align = 0;
4051 unsigned index = 0;
4052 unsigned inc = 1;
4053 switch (size) {
4054 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4055 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4056 case 0:
4057 if (fieldFromInstruction32(Insn, 4, 1))
4058 align = 4;
4059 index = fieldFromInstruction32(Insn, 5, 3);
4060 break;
4061 case 1:
4062 if (fieldFromInstruction32(Insn, 4, 1))
4063 align = 8;
4064 index = fieldFromInstruction32(Insn, 6, 2);
4065 if (fieldFromInstruction32(Insn, 5, 1))
4066 inc = 2;
4067 break;
4068 case 2:
4069 if (fieldFromInstruction32(Insn, 4, 2))
4070 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4071 index = fieldFromInstruction32(Insn, 7, 1);
4072 if (fieldFromInstruction32(Insn, 6, 1))
4073 inc = 2;
4074 break;
4075 }
4076
4077 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4079 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4080 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4082 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4083 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4084 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4085 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4087 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4088 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4089 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4090 }
4091
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4093 return MCDisassembler::Fail;
4094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4095 return MCDisassembler::Fail;
4096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4097 return MCDisassembler::Fail;
4098 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4099 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4100 Inst.addOperand(MCOperand::CreateImm(index));
4101
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4102 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4103}
4104
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4105static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4106 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4107 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4108 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4109 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4110 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4111 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4112 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4113
4114 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4115 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4116
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4117 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4118 return MCDisassembler::Fail;
4119 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4120 return MCDisassembler::Fail;
4121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4122 return MCDisassembler::Fail;
4123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4124 return MCDisassembler::Fail;
4125 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4126 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4127
4128 return S;
4129}
4130
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4131static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4132 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4133 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4134 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4135 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4136 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4137 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4138 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4139
4140 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4141 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4144 return MCDisassembler::Fail;
4145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4146 return MCDisassembler::Fail;
4147 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4148 return MCDisassembler::Fail;
4149 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4150 return MCDisassembler::Fail;
4151 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4152 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4153
4154 return S;
4155}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4156
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4157static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4158 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4159 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4160 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4161 // The InstPrinter needs to have the low bit of the predicate in
4162 // the mask operand to be able to print it properly.
4163 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4164
4165 if (pred == 0xF) {
4166 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4167 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4168 }
4169
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4170 if ((mask & 0xF) == 0) {
4171 // Preserve the high bit of the mask, which is the low bit of
4172 // the predicate.
4173 mask &= 0x10;
4174 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4175 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4176 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4177
4178 Inst.addOperand(MCOperand::CreateImm(pred));
4179 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4180 return S;
4181}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4182
4183static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4184DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4185 uint64_t Address, const void *Decoder) {
4186 DecodeStatus S = MCDisassembler::Success;
4187
4188 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4189 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4190 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4191 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4192 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4193 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4194 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4195 bool writeback = (W == 1) | (P == 0);
4196
4197 addr |= (U << 8) | (Rn << 9);
4198
4199 if (writeback && (Rn == Rt || Rn == Rt2))
4200 Check(S, MCDisassembler::SoftFail);
4201 if (Rt == Rt2)
4202 Check(S, MCDisassembler::SoftFail);
4203
4204 // Rt
4205 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4206 return MCDisassembler::Fail;
4207 // Rt2
4208 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 // Writeback operand
4211 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4212 return MCDisassembler::Fail;
4213 // addr
4214 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4215 return MCDisassembler::Fail;
4216
4217 return S;
4218}
4219
4220static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4221DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4222 uint64_t Address, const void *Decoder) {
4223 DecodeStatus S = MCDisassembler::Success;
4224
4225 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4226 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4227 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4228 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4229 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4230 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4231 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4232 bool writeback = (W == 1) | (P == 0);
4233
4234 addr |= (U << 8) | (Rn << 9);
4235
4236 if (writeback && (Rn == Rt || Rn == Rt2))
4237 Check(S, MCDisassembler::SoftFail);
4238
4239 // Writeback operand
4240 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4241 return MCDisassembler::Fail;
4242 // Rt
4243 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4244 return MCDisassembler::Fail;
4245 // Rt2
4246 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4247 return MCDisassembler::Fail;
4248 // addr
4249 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4250 return MCDisassembler::Fail;
4251
4252 return S;
4253}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4254
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4255static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4256 uint64_t Address, const void *Decoder) {
4257 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4258 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4259 if (sign1 != sign2) return MCDisassembler::Fail;
4260
4261 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4262 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4263 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4264 Val |= sign1 << 12;
4265 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4266
4267 return MCDisassembler::Success;
4268}
4269
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4270static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4271 uint64_t Address,
4272 const void *Decoder) {
4273 DecodeStatus S = MCDisassembler::Success;
4274
4275 // Shift of "asr #32" is not allowed in Thumb2 mode.
4276 if (Val == 0x20) S = MCDisassembler::SoftFail;
4277 Inst.addOperand(MCOperand::CreateImm(Val));
4278 return S;
4279}
4280
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4281static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4282 uint64_t Address, const void *Decoder) {
4283 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4284 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4285 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4286 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4287
4288 if (pred == 0xF)
4289 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4290
4291 DecodeStatus S = MCDisassembler::Success;
4292 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4293 return MCDisassembler::Fail;
4294 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4295 return MCDisassembler::Fail;
4296 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4297 return MCDisassembler::Fail;
4298 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4299 return MCDisassembler::Fail;
4300
4301 return S;
4302}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4303
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4304static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4305 uint64_t Address, const void *Decoder) {
4306 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4307 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4308 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4309 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4310 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4311 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4312
4313 DecodeStatus S = MCDisassembler::Success;
4314
4315 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4316 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4317 Inst.setOpcode(ARM::VMOVv2f32);
4318 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4319 }
4320
4321 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4322
4323 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4324 return MCDisassembler::Fail;
4325 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4326 return MCDisassembler::Fail;
4327 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4328
4329 return S;
4330}
4331
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4332static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4333 uint64_t Address, const void *Decoder) {
4334 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4335 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4336 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4337 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4338 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4339 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4340
4341 DecodeStatus S = MCDisassembler::Success;
4342
4343 // VMOVv4f32 is ambiguous with these decodings.
4344 if (!(imm & 0x38) && cmode == 0xF) {
4345 Inst.setOpcode(ARM::VMOVv4f32);
4346 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4347 }
4348
4349 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4350
4351 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4352 return MCDisassembler::Fail;
4353 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4354 return MCDisassembler::Fail;
4355 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4356
4357 return S;
4358}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4359
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4360static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4361 uint64_t Address, const void *Decoder) {
4362 DecodeStatus S = MCDisassembler::Success;
4363
4364 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4365 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4366 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4367 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4368 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4369
4370 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4371 S = MCDisassembler::SoftFail;
4372
4373 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4374 return MCDisassembler::Fail;
4375 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4376 return MCDisassembler::Fail;
4377 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4378 return MCDisassembler::Fail;
4379 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4380 return MCDisassembler::Fail;
4381 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4382 return MCDisassembler::Fail;
4383
4384 return S;
4385}
4386