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Chris Lattner035dfbe2002-08-09 20:08:06 +00001//===-- InstrSelectionSupport.cpp -----------------------------------------===//
John Criswellb576c942003-10-20 19:43:21 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Chris Lattner035dfbe2002-08-09 20:08:06 +00009//
10// Target-independent instruction selection code. See SparcInstrSelection.cpp
11// for usage.
Vikram S. Advea1d14f32001-10-10 20:50:43 +000012//
Chris Lattner035dfbe2002-08-09 20:08:06 +000013//===----------------------------------------------------------------------===//
Vikram S. Advea1d14f32001-10-10 20:50:43 +000014
15#include "llvm/CodeGen/InstrSelectionSupport.h"
16#include "llvm/CodeGen/InstrSelection.h"
Vikram S. Adve36f0a9e2002-05-19 15:34:29 +000017#include "llvm/CodeGen/MachineInstrAnnot.h"
Chris Lattnerfb3b1ec2002-02-03 07:39:06 +000018#include "llvm/CodeGen/MachineCodeForInstruction.h"
Chris Lattnerfb3b1ec2002-02-03 07:39:06 +000019#include "llvm/CodeGen/InstrForest.h"
Vikram S. Advea1d14f32001-10-10 20:50:43 +000020#include "llvm/Target/TargetMachine.h"
Chris Lattnerd0f166a2002-12-29 03:13:05 +000021#include "llvm/Target/TargetRegInfo.h"
Chris Lattner3501fea2003-01-14 22:00:31 +000022#include "llvm/Target/TargetInstrInfo.h"
Chris Lattner31bcdb82002-04-28 19:55:58 +000023#include "llvm/Constants.h"
Chris Lattner795ba6c2003-01-15 21:36:50 +000024#include "llvm/BasicBlock.h"
Chris Lattnerc5b8b1a2002-10-28 23:54:47 +000025#include "llvm/DerivedTypes.h"
Chris Lattner18153832003-07-23 14:55:59 +000026#include "../../Target/Sparc/SparcInstrSelectionSupport.h" // FIXME!
Vikram S. Advea1d14f32001-10-10 20:50:43 +000027
Vikram S. Advea1d14f32001-10-10 20:50:43 +000028
Vikram S. Adve36f0a9e2002-05-19 15:34:29 +000029// Generate code to load the constant into a TmpInstruction (virtual reg) and
30// returns the virtual register.
31//
Vikram S. Adve6d353262001-10-17 23:57:50 +000032static TmpInstruction*
Chris Lattner2fbfdcf2002-04-07 20:49:59 +000033InsertCodeToLoadConstant(Function *F,
Vikram S. Adve42f63202002-03-18 03:33:43 +000034 Value* opValue,
Vikram S. Adve6d353262001-10-17 23:57:50 +000035 Instruction* vmInstr,
Chris Lattner18153832003-07-23 14:55:59 +000036 std::vector<MachineInstr*>& loadConstVec,
Vikram S. Adve6d353262001-10-17 23:57:50 +000037 TargetMachine& target)
Vikram S. Advea1d14f32001-10-10 20:50:43 +000038{
Vikram S. Adve6d353262001-10-17 23:57:50 +000039 // Create a tmp virtual register to hold the constant.
Vikram S. Adve36f0a9e2002-05-19 15:34:29 +000040 MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
Vikram S. Advef3d3ca12003-05-31 07:41:24 +000041 TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
Vikram S. Advea1d14f32001-10-10 20:50:43 +000042
Vikram S. Adve36f0a9e2002-05-19 15:34:29 +000043 target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
44 loadConstVec, mcfi);
Vikram S. Adve6d353262001-10-17 23:57:50 +000045
46 // Record the mapping from the tmp VM instruction to machine instruction.
47 // Do this for all machine instructions that were not mapped to any
48 // other temp values created by
49 // tmpReg->addMachineInstruction(loadConstVec.back());
50
51 return tmpReg;
Vikram S. Advea1d14f32001-10-10 20:50:43 +000052}
53
54
Vikram S. Advea1d14f32001-10-10 20:50:43 +000055MachineOperand::MachineOperandType
Vikram S. Advefd0ec802002-09-16 15:15:57 +000056ChooseRegOrImmed(int64_t intValue,
57 bool isSigned,
58 MachineOpCode opCode,
59 const TargetMachine& target,
60 bool canUseImmed,
61 unsigned int& getMachineRegNum,
62 int64_t& getImmedValue)
63{
64 MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
65 getMachineRegNum = 0;
66 getImmedValue = 0;
67
68 if (canUseImmed &&
Chris Lattner795ba6c2003-01-15 21:36:50 +000069 target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
Vikram S. Advefd0ec802002-09-16 15:15:57 +000070 {
71 opType = isSigned? MachineOperand::MO_SignExtendedImmed
72 : MachineOperand::MO_UnextendedImmed;
73 getImmedValue = intValue;
74 }
75 else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
76 {
77 opType = MachineOperand::MO_MachineRegister;
78 getMachineRegNum = target.getRegInfo().getZeroRegNum();
79 }
80
81 return opType;
82}
83
84
85MachineOperand::MachineOperandType
Vikram S. Advea1d14f32001-10-10 20:50:43 +000086ChooseRegOrImmed(Value* val,
87 MachineOpCode opCode,
88 const TargetMachine& target,
89 bool canUseImmed,
90 unsigned int& getMachineRegNum,
91 int64_t& getImmedValue)
92{
Vikram S. Advea1d14f32001-10-10 20:50:43 +000093 getMachineRegNum = 0;
94 getImmedValue = 0;
Vikram S. Advefd0ec802002-09-16 15:15:57 +000095
96 // To use reg or immed, constant needs to be integer, bool, or a NULL pointer
Vikram S. Adveb5161b62003-07-29 19:50:12 +000097 // TargetInstrInfo::ConvertConstantToIntType() does the right conversions:
98 bool isValidConstant;
99 uint64_t valueToUse =
100 target.getInstrInfo().ConvertConstantToIntType(target, val, val->getType(),
101 isValidConstant);
102 if (! isValidConstant)
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000103 return MachineOperand::MO_VirtualRegister;
Vikram S. Advea1d14f32001-10-10 20:50:43 +0000104
Vikram S. Adveb5161b62003-07-29 19:50:12 +0000105 // Now check if the constant value fits in the IMMED field.
Vikram S. Advea1d14f32001-10-10 20:50:43 +0000106 //
Vikram S. Adveb5161b62003-07-29 19:50:12 +0000107 return ChooseRegOrImmed((int64_t) valueToUse, val->getType()->isSigned(),
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000108 opCode, target, canUseImmed,
109 getMachineRegNum, getImmedValue);
Vikram S. Advea1d14f32001-10-10 20:50:43 +0000110}
111
Vikram S. Adve6d353262001-10-17 23:57:50 +0000112//---------------------------------------------------------------------------
113// Function: FixConstantOperandsForInstr
114//
115// Purpose:
116// Special handling for constant operands of a machine instruction
117// -- if the constant is 0, use the hardwired 0 register, if any;
118// -- if the constant fits in the IMMEDIATE field, use that field;
119// -- else create instructions to put the constant into a register, either
120// directly or by loading explicitly from the constant pool.
121//
122// In the first 2 cases, the operand of `minstr' is modified in place.
123// Returns a vector of machine instructions generated for operands that
124// fall under case 3; these must be inserted before `minstr'.
125//---------------------------------------------------------------------------
126
Chris Lattner18153832003-07-23 14:55:59 +0000127std::vector<MachineInstr*>
Vikram S. Adve6d353262001-10-17 23:57:50 +0000128FixConstantOperandsForInstr(Instruction* vmInstr,
129 MachineInstr* minstr,
130 TargetMachine& target)
131{
Chris Lattner18153832003-07-23 14:55:59 +0000132 std::vector<MachineInstr*> MVec;
Vikram S. Adve6d353262001-10-17 23:57:50 +0000133
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000134 MachineOpCode opCode = minstr->getOpCode();
Chris Lattner3501fea2003-01-14 22:00:31 +0000135 const TargetInstrInfo& instrInfo = target.getInstrInfo();
Chris Lattner8f780272002-10-29 17:25:41 +0000136 int resultPos = instrInfo.getResultPos(opCode);
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000137 int immedPos = instrInfo.getImmedConstantPos(opCode);
138
Chris Lattner2fbfdcf2002-04-07 20:49:59 +0000139 Function *F = vmInstr->getParent()->getParent();
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000140
Vikram S. Adve6d353262001-10-17 23:57:50 +0000141 for (unsigned op=0; op < minstr->getNumOperands(); op++)
142 {
143 const MachineOperand& mop = minstr->getOperand(op);
144
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000145 // Skip the result position, preallocated machine registers, or operands
146 // that cannot be constants (CC regs or PC-relative displacements)
Chris Lattner8f780272002-10-29 17:25:41 +0000147 if (resultPos == (int)op ||
Chris Lattner133f0792002-10-28 04:45:29 +0000148 mop.getType() == MachineOperand::MO_MachineRegister ||
149 mop.getType() == MachineOperand::MO_CCRegister ||
150 mop.getType() == MachineOperand::MO_PCRelativeDisp)
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000151 continue;
152
Vikram S. Adve6d353262001-10-17 23:57:50 +0000153 bool constantThatMustBeLoaded = false;
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000154 unsigned int machineRegNum = 0;
155 int64_t immedValue = 0;
156 Value* opValue = NULL;
157 MachineOperand::MachineOperandType opType =
158 MachineOperand::MO_VirtualRegister;
159
160 // Operand may be a virtual register or a compile-time constant
Chris Lattner133f0792002-10-28 04:45:29 +0000161 if (mop.getType() == MachineOperand::MO_VirtualRegister)
Vikram S. Adve42f63202002-03-18 03:33:43 +0000162 {
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000163 assert(mop.getVRegValue() != NULL);
Chris Lattnerc7c7b7a2003-01-15 20:32:15 +0000164 opValue = mop.getVRegValue();
165 if (Constant *opConst = dyn_cast<Constant>(opValue)) {
Chris Lattner04120772003-01-15 19:47:53 +0000166 opType = ChooseRegOrImmed(opConst, opCode, target,
167 (immedPos == (int)op), machineRegNum,
168 immedValue);
169 if (opType == MachineOperand::MO_VirtualRegister)
170 constantThatMustBeLoaded = true;
171 }
Vikram S. Adve94e40ef2001-10-28 21:46:23 +0000172 }
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000173 else
174 {
Chris Lattner04120772003-01-15 19:47:53 +0000175 assert(mop.isImmediate());
176 bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000177
178 // Bit-selection flags indicate an instruction that is extracting
179 // bits from its operand so ignore this even if it is a big constant.
180 if (mop.opHiBits32() || mop.opLoBits32() ||
181 mop.opHiBits64() || mop.opLoBits64())
182 continue;
183
184 opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
185 opCode, target, (immedPos == (int)op),
186 machineRegNum, immedValue);
187
Misha Brukman6fe69052003-06-07 02:34:43 +0000188 if (opType == MachineOperand::MO_SignExtendedImmed ||
189 opType == MachineOperand::MO_UnextendedImmed) {
Misha Brukmand15cd272003-06-04 04:54:06 +0000190 // The optype is an immediate value
191 // This means we need to change the opcode, e.g. ADDr -> ADDi
192 unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
193 minstr->setOpcode(newOpcode);
194 }
195
Chris Lattner133f0792002-10-28 04:45:29 +0000196 if (opType == mop.getType())
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000197 continue; // no change: this is the most common case
198
199 if (opType == MachineOperand::MO_VirtualRegister)
200 {
201 constantThatMustBeLoaded = true;
202 opValue = isSigned
Chris Lattner82f05d82002-09-17 17:23:09 +0000203 ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
204 : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000205 }
206 }
207
208 if (opType == MachineOperand::MO_MachineRegister)
209 minstr->SetMachineOperandReg(op, machineRegNum);
210 else if (opType == MachineOperand::MO_SignExtendedImmed ||
Misha Brukmanc740aae2003-06-03 03:18:20 +0000211 opType == MachineOperand::MO_UnextendedImmed) {
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000212 minstr->SetMachineOperandConst(op, opType, immedValue);
Misha Brukman6fe69052003-06-07 02:34:43 +0000213 // The optype is or has become an immediate
214 // This means we need to change the opcode, e.g. ADDr -> ADDi
215 unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
216 minstr->setOpcode(newOpcode);
Misha Brukmanc740aae2003-06-03 03:18:20 +0000217 } else if (constantThatMustBeLoaded ||
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000218 (opValue && isa<GlobalValue>(opValue)))
219 { // opValue is a constant that must be explicitly loaded into a reg
220 assert(opValue);
221 TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
Chris Lattner04120772003-01-15 19:47:53 +0000222 MVec, target);
Vikram S. Adve42f63202002-03-18 03:33:43 +0000223 minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
224 tmpReg);
Vikram S. Adve6d353262001-10-17 23:57:50 +0000225 }
226 }
227
Vikram S. Adve36f0a9e2002-05-19 15:34:29 +0000228 // Also, check for implicit operands used by the machine instruction
229 // (no need to check those defined since they cannot be constants).
230 // These include:
Vikram S. Adve6d353262001-10-17 23:57:50 +0000231 // -- arguments to a Call
232 // -- return value of a Return
233 // Any such operand that is a constant value needs to be fixed also.
234 // The current instructions with implicit refs (viz., Call and Return)
235 // have no immediate fields, so the constant always needs to be loaded
236 // into a register.
237 //
Vikram S. Advefd0ec802002-09-16 15:15:57 +0000238 bool isCall = instrInfo.isCall(opCode);
Vikram S. Adve36f0a9e2002-05-19 15:34:29 +0000239 unsigned lastCallArgNum = 0; // unused if not a call
240 CallArgsDescriptor* argDesc = NULL; // unused if not a call
241 if (isCall)
242 argDesc = CallArgsDescriptor::get(minstr);
243
Vikram S. Adve6d353262001-10-17 23:57:50 +0000244 for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
Chris Lattnere9bb2df2001-12-03 22:26:30 +0000245 if (isa<Constant>(minstr->getImplicitRef(i)) ||
Vikram S. Adve6d353262001-10-17 23:57:50 +0000246 isa<GlobalValue>(minstr->getImplicitRef(i)))
247 {
Vikram S. Adve94e40ef2001-10-28 21:46:23 +0000248 Value* oldVal = minstr->getImplicitRef(i);
Vikram S. Adve6d353262001-10-17 23:57:50 +0000249 TmpInstruction* tmpReg =
Chris Lattner04120772003-01-15 19:47:53 +0000250 InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
Vikram S. Adve6d353262001-10-17 23:57:50 +0000251 minstr->setImplicitRef(i, tmpReg);
Vikram S. Adve36f0a9e2002-05-19 15:34:29 +0000252
253 if (isCall)
254 { // find and replace the argument in the CallArgsDescriptor
255 unsigned i=lastCallArgNum;
256 while (argDesc->getArgInfo(i).getArgVal() != oldVal)
257 ++i;
258 assert(i < argDesc->getNumArgs() &&
259 "Constant operands to a call *must* be in the arg list");
260 lastCallArgNum = i;
261 argDesc->getArgInfo(i).replaceArgVal(tmpReg);
262 }
Vikram S. Adve6d353262001-10-17 23:57:50 +0000263 }
264
Chris Lattner04120772003-01-15 19:47:53 +0000265 return MVec;
Vikram S. Adve6d353262001-10-17 23:57:50 +0000266}