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gerrit-public.fairphone.software / platform / external / llvm / b72d53d8efb51f7d8a22ff8753a8286071dc5f06 / . / test / CodeGen / X86 / atomic_op.ll
blob: 677941bc6022aa9f9a0589e4a7c37595e49e4d7a [file] [log] [blame]
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]1; RUN: llc < %s -march=x86 | FileCheck %s
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]2
3target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
4
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]5define void @main(i32 %argc, i8** %argv) nounwind {
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]6entry:
7 %argc.addr = alloca i32 ; <i32*> [#uses=1]
8 %argv.addr = alloca i8** ; <i8***> [#uses=1]
9 %val1 = alloca i32 ; <i32*> [#uses=2]
10 %val2 = alloca i32 ; <i32*> [#uses=15]
11 %andt = alloca i32 ; <i32*> [#uses=2]
12 %ort = alloca i32 ; <i32*> [#uses=2]
13 %xort = alloca i32 ; <i32*> [#uses=2]
14 %old = alloca i32 ; <i32*> [#uses=18]
15 %temp = alloca i32 ; <i32*> [#uses=2]
16 store i32 %argc, i32* %argc.addr
17 store i8** %argv, i8*** %argv.addr
18 store i32 0, i32* %val1
19 store i32 31, i32* %val2
20 store i32 3855, i32* %andt
21 store i32 3855, i32* %ort
22 store i32 3855, i32* %xort
23 store i32 4, i32* %temp
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]24 %tmp = load i32* %temp
25 ; CHECK: lock
26 ; CHECK: xaddl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]27 call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp ) ; <i32>:0 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]28 store i32 %0, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]29 ; CHECK: lock
30 ; CHECK: xaddl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]31 call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 ) ; <i32>:1 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]32 store i32 %1, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]33 ; CHECK: lock
34 ; CHECK: xaddl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]35 call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:2 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]36 store i32 %2, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]37 ; CHECK: lock
38 ; CHECK: xaddl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]39 call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:3 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]40 store i32 %3, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]41 ; CHECK: andl
42 ; CHECK: lock
43 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]44 call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 ) ; <i32>:4 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]45 store i32 %4, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]46 ; CHECK: orl
47 ; CHECK: lock
48 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]49 call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 ) ; <i32>:5 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]50 store i32 %5, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]51 ; CHECK: xorl
52 ; CHECK: lock
53 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]54 call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 ) ; <i32>:6 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]55 store i32 %6, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]56 ; CHECK: cmov
57 ; CHECK: lock
58 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]59 call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 ) ; <i32>:7 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]60 store i32 %7, i32* %old
61 %neg = sub i32 0, 1 ; <i32> [#uses=1]
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]62 ; CHECK: cmov
63 ; CHECK: lock
64 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]65 call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg ) ; <i32>:8 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]66 store i32 %8, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]67 ; CHECK: cmov
68 ; CHECK: lock
69 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]70 call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:9 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]71 store i32 %9, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]72 ; CHECK: cmov
73 ; CHECK: lock
74 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]75 call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 ) ; <i32>:10 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]76 store i32 %10, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]77 ; CHECK: cmov
78 ; CHECK: lock
79 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]80 call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 65535 ) ; <i32>:11 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]81 store i32 %11, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]82 ; CHECK: cmov
83 ; CHECK: lock
84 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]85 call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 10 ) ; <i32>:12 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]86 store i32 %12, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]87 ; CHECK: cmov
88 ; CHECK: lock
89 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]90 call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:13 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]91 store i32 %13, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]92 ; CHECK: cmov
93 ; CHECK: lock
94 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]95 call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 10 ) ; <i32>:14 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]96 store i32 %14, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]97 ; CHECK: xchgl %{{.*}}, {{.*}}(%esp)
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]98 call i32 @llvm.atomic.swap.i32.p0i32( i32* %val2, i32 1976 ) ; <i32>:15 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]99 store i32 %15, i32* %old
100 %neg1 = sub i32 0, 10 ; <i32> [#uses=1]
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]101 ; CHECK: lock
102 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]103 call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 %neg1, i32 1 ) ; <i32>:16 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]104 store i32 %16, i32* %old
Chris Lattnerb72d53d2010-09-21 23:57:27 +0000[diff] [blame^]105 ; CHECK: lock
106 ; CHECK: cmpxchgl
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]107 call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 1976, i32 1 ) ; <i32>:17 [#uses=1]
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]108 store i32 %17, i32* %old
109 ret void
110}
111
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]112declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]113
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]114declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]115
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]116declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]117
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]118declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]119
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]120declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]121
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]122declare i32 @llvm.atomic.load.min.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]123
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]124declare i32 @llvm.atomic.load.max.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]125
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]126declare i32 @llvm.atomic.load.umax.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]127
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]128declare i32 @llvm.atomic.load.umin.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]129
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]130declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
Mon P Wang63307c32008-05-05 19:05:59 +0000[diff] [blame]131
Mon P Wange3b3a722008-07-30 04:36:53 +0000[diff] [blame]132declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind