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Chris Lattner1c08c712005-01-07 07:47:53 +00001//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
Misha Brukmanedf128a2005-04-21 22:36:52 +00002//
Chris Lattner1c08c712005-01-07 07:47:53 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanedf128a2005-04-21 22:36:52 +00007//
Chris Lattner1c08c712005-01-07 07:47:53 +00008//===----------------------------------------------------------------------===//
9//
10// This implements the SelectionDAGISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
Anton Korobeynikov5502bf62007-04-04 21:14:49 +000015#include "llvm/ADT/BitVector.h"
Jim Laskeyc7c3f112006-10-16 20:52:31 +000016#include "llvm/Analysis/AliasAnalysis.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000017#include "llvm/CodeGen/SelectionDAGISel.h"
Evan Chenga9c20912006-01-21 02:32:06 +000018#include "llvm/CodeGen/ScheduleDAG.h"
Anton Korobeynikov5502bf62007-04-04 21:14:49 +000019#include "llvm/Constants.h"
Chris Lattneradf6a962005-05-13 18:50:42 +000020#include "llvm/CallingConv.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000021#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
Chris Lattner36ce6912005-11-29 06:21:05 +000023#include "llvm/GlobalVariable.h"
Chris Lattnerce7518c2006-01-26 22:24:51 +000024#include "llvm/InlineAsm.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000025#include "llvm/Instructions.h"
26#include "llvm/Intrinsics.h"
Jim Laskey43970fe2006-03-23 18:06:46 +000027#include "llvm/IntrinsicInst.h"
Reid Spencer5694b6e2007-04-09 06:17:21 +000028#include "llvm/ParameterAttributes.h"
Gordon Henriksence224772008-01-07 01:30:38 +000029#include "llvm/CodeGen/Collector.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000030#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineFrameInfo.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000033#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
Jim Laskeyeb577ba2006-08-02 12:30:23 +000036#include "llvm/CodeGen/SchedulerRegistry.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000037#include "llvm/CodeGen/SelectionDAG.h"
Chris Lattnerfa577022005-09-13 19:30:54 +000038#include "llvm/Target/MRegisterInfo.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000039#include "llvm/Target/TargetData.h"
40#include "llvm/Target/TargetFrameInfo.h"
41#include "llvm/Target/TargetInstrInfo.h"
42#include "llvm/Target/TargetLowering.h"
43#include "llvm/Target/TargetMachine.h"
Vladimir Prus12472912006-05-23 13:43:15 +000044#include "llvm/Target/TargetOptions.h"
Chris Lattner7c0104b2005-11-09 04:45:33 +000045#include "llvm/Support/MathExtras.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000046#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000047#include "llvm/Support/Compiler.h"
Jeff Cohen7e881032006-02-24 02:52:40 +000048#include <algorithm>
Chris Lattner1c08c712005-01-07 07:47:53 +000049using namespace llvm;
50
Chris Lattnerda8abb02005-09-01 18:44:10 +000051#ifndef NDEBUG
Chris Lattner7944d9d2005-01-12 03:41:21 +000052static cl::opt<bool>
Evan Chenga9c20912006-01-21 02:32:06 +000053ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
55static cl::opt<bool>
56ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
Dan Gohman3e1a7ae2007-08-28 20:32:58 +000058static cl::opt<bool>
59ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
Chris Lattner5bab7852008-01-25 17:24:52 +000060 cl::desc("Pop up a window to show SUnit dags after they are processed"));
Chris Lattner7944d9d2005-01-12 03:41:21 +000061#else
Dan Gohman3e1a7ae2007-08-28 20:32:58 +000062static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
Chris Lattner7944d9d2005-01-12 03:41:21 +000063#endif
64
Jim Laskeyeb577ba2006-08-02 12:30:23 +000065//===---------------------------------------------------------------------===//
66///
67/// RegisterScheduler class - Track the registration of instruction schedulers.
68///
69//===---------------------------------------------------------------------===//
70MachinePassRegistry RegisterScheduler::Registry;
71
72//===---------------------------------------------------------------------===//
73///
74/// ISHeuristic command line option for instruction schedulers.
75///
76//===---------------------------------------------------------------------===//
Evan Cheng4ef10862006-01-23 07:01:07 +000077namespace {
Jim Laskeyeb577ba2006-08-02 12:30:23 +000078 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
Dale Johannesene7e7d0d2007-07-13 17:13:54 +000080 ISHeuristic("pre-RA-sched",
Chris Lattner3700f902006-08-03 00:18:59 +000081 cl::init(&createDefaultScheduler),
Chris Lattner5bab7852008-01-25 17:24:52 +000082 cl::desc("Instruction schedulers available (before register"
83 " allocation):"));
Jim Laskey13ec7022006-08-01 14:21:23 +000084
Jim Laskey9ff542f2006-08-01 18:29:48 +000085 static RegisterScheduler
Jim Laskey9373beb2006-08-01 19:14:14 +000086 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
Evan Cheng4ef10862006-01-23 07:01:07 +000088} // namespace
89
Chris Lattnerbf996f12007-04-30 17:29:31 +000090namespace { struct AsmOperandInfo; }
91
Chris Lattner864635a2006-02-22 22:37:12 +000092namespace {
93 /// RegsForValue - This struct represents the physical registers that a
94 /// particular value is assigned and the type information about the value.
95 /// This is needed because values can be promoted into larger registers and
96 /// expanded into multiple smaller registers than the value.
Chris Lattner95255282006-06-28 23:17:24 +000097 struct VISIBILITY_HIDDEN RegsForValue {
Dan Gohmanb6f5b002007-06-28 23:29:44 +000098 /// Regs - This list holds the register (for legal and promoted values)
Chris Lattner864635a2006-02-22 22:37:12 +000099 /// or register set (for expanded values) that the value should be assigned
100 /// to.
101 std::vector<unsigned> Regs;
102
103 /// RegVT - The value type of each register.
104 ///
105 MVT::ValueType RegVT;
106
107 /// ValueVT - The value type of the LLVM value, which may be promoted from
108 /// RegVT or made from merging the two expanded parts.
109 MVT::ValueType ValueVT;
110
111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
112
113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
114 : RegVT(regvt), ValueVT(valuevt) {
115 Regs.push_back(Reg);
116 }
117 RegsForValue(const std::vector<unsigned> &regs,
118 MVT::ValueType regvt, MVT::ValueType valuevt)
119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
120 }
121
122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
123 /// this value and returns the result as a ValueVT value. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000125 /// If the Flag pointer is NULL, no flag is used.
Chris Lattner864635a2006-02-22 22:37:12 +0000126 SDOperand getCopyFromRegs(SelectionDAG &DAG,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000127 SDOperand &Chain, SDOperand *Flag) const;
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +0000128
129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
130 /// specified value into the registers specified by this object. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000132 /// If the Flag pointer is NULL, no flag is used.
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +0000133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000134 SDOperand &Chain, SDOperand *Flag) const;
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +0000135
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
Chris Lattner9f6637d2006-02-23 20:06:57 +0000140 std::vector<SDOperand> &Ops) const;
Chris Lattner864635a2006-02-22 22:37:12 +0000141 };
142}
Evan Cheng4ef10862006-01-23 07:01:07 +0000143
Chris Lattner1c08c712005-01-07 07:47:53 +0000144namespace llvm {
145 //===--------------------------------------------------------------------===//
Jim Laskey9373beb2006-08-01 19:14:14 +0000146 /// createDefaultScheduler - This creates an instruction scheduler appropriate
147 /// for the target.
148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
149 SelectionDAG *DAG,
150 MachineBasicBlock *BB) {
151 TargetLowering &TLI = IS->getTargetLowering();
152
153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
154 return createTDListDAGScheduler(IS, DAG, BB);
155 } else {
156 assert(TLI.getSchedulingPreference() ==
157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
158 return createBURRListDAGScheduler(IS, DAG, BB);
159 }
160 }
161
162
163 //===--------------------------------------------------------------------===//
Chris Lattner1c08c712005-01-07 07:47:53 +0000164 /// FunctionLoweringInfo - This contains information that is global to a
165 /// function that is used when lowering a region of the function.
Chris Lattnerf26bc8e2005-01-08 19:52:31 +0000166 class FunctionLoweringInfo {
167 public:
Chris Lattner1c08c712005-01-07 07:47:53 +0000168 TargetLowering &TLI;
169 Function &Fn;
170 MachineFunction &MF;
Chris Lattner84bc5422007-12-31 04:13:23 +0000171 MachineRegisterInfo &RegInfo;
Chris Lattner1c08c712005-01-07 07:47:53 +0000172
173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
174
175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
177
178 /// ValueMap - Since we emit code for the function a basic block at a time,
179 /// we must remember which virtual registers hold the values for
180 /// cross-basic-block values.
Chris Lattner9f24ad72007-02-04 01:35:11 +0000181 DenseMap<const Value*, unsigned> ValueMap;
Chris Lattner1c08c712005-01-07 07:47:53 +0000182
183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
184 /// the entry block. This allows the allocas to be efficiently referenced
185 /// anywhere in the function.
186 std::map<const AllocaInst*, int> StaticAllocaMap;
187
Duncan Sandsf4070822007-06-15 19:04:19 +0000188#ifndef NDEBUG
189 SmallSet<Instruction*, 8> CatchInfoLost;
190 SmallSet<Instruction*, 8> CatchInfoFound;
191#endif
192
Chris Lattner1c08c712005-01-07 07:47:53 +0000193 unsigned MakeReg(MVT::ValueType VT) {
Chris Lattner84bc5422007-12-31 04:13:23 +0000194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
Chris Lattner1c08c712005-01-07 07:47:53 +0000195 }
Chris Lattner571e4342006-10-27 21:36:01 +0000196
197 /// isExportedInst - Return true if the specified value is an instruction
198 /// exported from its block.
199 bool isExportedInst(const Value *V) {
200 return ValueMap.count(V);
201 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000202
Chris Lattner3c384492006-03-16 19:51:18 +0000203 unsigned CreateRegForValue(const Value *V);
204
Chris Lattner1c08c712005-01-07 07:47:53 +0000205 unsigned InitializeRegForValue(const Value *V) {
206 unsigned &R = ValueMap[V];
207 assert(R == 0 && "Already initialized this value register!");
208 return R = CreateRegForValue(V);
209 }
210 };
211}
212
Duncan Sandscf26d7c2007-07-04 20:52:51 +0000213/// isSelector - Return true if this instruction is a call to the
214/// eh.selector intrinsic.
215static bool isSelector(Instruction *I) {
Duncan Sandsf4070822007-06-15 19:04:19 +0000216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +0000217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
218 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
Duncan Sandsf4070822007-06-15 19:04:19 +0000219 return false;
220}
221
Chris Lattner1c08c712005-01-07 07:47:53 +0000222/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
Nate Begemanf15485a2006-03-27 01:32:24 +0000223/// PHI nodes or outside of the basic block that defines it, or used by a
224/// switch instruction, which may expand to multiple basic blocks.
Chris Lattner1c08c712005-01-07 07:47:53 +0000225static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
226 if (isa<PHINode>(I)) return true;
227 BasicBlock *BB = I->getParent();
228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
Nate Begemanf15485a2006-03-27 01:32:24 +0000229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
Chris Lattner571e4342006-10-27 21:36:01 +0000230 // FIXME: Remove switchinst special case.
Nate Begemanf15485a2006-03-27 01:32:24 +0000231 isa<SwitchInst>(*UI))
Chris Lattner1c08c712005-01-07 07:47:53 +0000232 return true;
233 return false;
234}
235
Chris Lattnerbf209482005-10-30 19:42:35 +0000236/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
Nate Begemanf15485a2006-03-27 01:32:24 +0000237/// entry block, return true. This includes arguments used by switches, since
238/// the switch may expand into multiple basic blocks.
Chris Lattnerbf209482005-10-30 19:42:35 +0000239static bool isOnlyUsedInEntryBlock(Argument *A) {
240 BasicBlock *Entry = A->getParent()->begin();
241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
Nate Begemanf15485a2006-03-27 01:32:24 +0000242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
Chris Lattnerbf209482005-10-30 19:42:35 +0000243 return false; // Use not in entry block.
244 return true;
245}
246
Chris Lattner1c08c712005-01-07 07:47:53 +0000247FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
Misha Brukmanedf128a2005-04-21 22:36:52 +0000248 Function &fn, MachineFunction &mf)
Chris Lattner84bc5422007-12-31 04:13:23 +0000249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000250
Chris Lattnerbf209482005-10-30 19:42:35 +0000251 // Create a vreg for each argument register that is not dead and is used
252 // outside of the entry block for the function.
253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
254 AI != E; ++AI)
255 if (!isOnlyUsedInEntryBlock(AI))
256 InitializeRegForValue(AI);
257
Chris Lattner1c08c712005-01-07 07:47:53 +0000258 // Initialize the mapping of values to registers. This is only set up for
259 // instruction values that are used outside of the block that defines
260 // them.
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000261 Function::iterator BB = Fn.begin(), EB = Fn.end();
Chris Lattner1c08c712005-01-07 07:47:53 +0000262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
Reid Spencerb83eb642006-10-20 07:07:24 +0000264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000265 const Type *Ty = AI->getAllocatedType();
Duncan Sands514ab342007-11-01 20:53:16 +0000266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Nate Begemanae232e72005-11-06 09:00:38 +0000267 unsigned Align =
Chris Lattnerd2b7cec2007-02-14 05:52:17 +0000268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
Nate Begemanae232e72005-11-06 09:00:38 +0000269 AI->getAlignment());
Chris Lattnera8217e32005-05-13 23:14:17 +0000270
Reid Spencerb83eb642006-10-20 07:07:24 +0000271 TySize *= CUI->getZExtValue(); // Get total allocated size.
Chris Lattnerd222f6a2005-10-18 22:14:06 +0000272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
Chris Lattner1c08c712005-01-07 07:47:53 +0000273 StaticAllocaMap[AI] =
Chris Lattner6266c182007-04-25 04:08:28 +0000274 MF.getFrameInfo()->CreateStackObject(TySize, Align);
Chris Lattner1c08c712005-01-07 07:47:53 +0000275 }
276
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000277 for (; BB != EB; ++BB)
278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
Chris Lattner1c08c712005-01-07 07:47:53 +0000279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
280 if (!isa<AllocaInst>(I) ||
281 !StaticAllocaMap.count(cast<AllocaInst>(I)))
282 InitializeRegForValue(I);
283
284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
285 // also creates the initial PHI MachineInstrs, though none of the input
286 // operands are populated.
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000288 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
289 MBBMap[BB] = MBB;
290 MF.getBasicBlockList().push_back(MBB);
291
292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
293 // appropriate.
294 PHINode *PN;
Chris Lattner8c494ab2006-10-27 23:50:33 +0000295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
296 if (PN->use_empty()) continue;
297
298 MVT::ValueType VT = TLI.getValueType(PN->getType());
Dan Gohman7f321562007-06-25 16:23:39 +0000299 unsigned NumRegisters = TLI.getNumRegisters(VT);
Chris Lattner8c494ab2006-10-27 23:50:33 +0000300 unsigned PHIReg = ValueMap[PN];
301 assert(PHIReg && "PHI node does not have an assigned virtual register!");
Evan Chengc0f64ff2006-11-27 23:37:22 +0000302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
Dan Gohmanb9f10192007-06-21 14:42:22 +0000303 for (unsigned i = 0; i != NumRegisters; ++i)
Evan Chengc0f64ff2006-11-27 23:37:22 +0000304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
Chris Lattner8c494ab2006-10-27 23:50:33 +0000305 }
Chris Lattner1c08c712005-01-07 07:47:53 +0000306 }
307}
308
Chris Lattner3c384492006-03-16 19:51:18 +0000309/// CreateRegForValue - Allocate the appropriate number of virtual registers of
310/// the correctly promoted or expanded types. Assign these registers
311/// consecutive vreg numbers and return the first assigned number.
312unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
313 MVT::ValueType VT = TLI.getValueType(V->getType());
314
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000315 unsigned NumRegisters = TLI.getNumRegisters(VT);
316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
Bill Wendling95b39552007-04-24 21:13:23 +0000317
Dan Gohman8c8c5fc2007-06-27 14:34:07 +0000318 unsigned R = MakeReg(RegisterVT);
319 for (unsigned i = 1; i != NumRegisters; ++i)
320 MakeReg(RegisterVT);
321
Chris Lattner3c384492006-03-16 19:51:18 +0000322 return R;
323}
Chris Lattner1c08c712005-01-07 07:47:53 +0000324
325//===----------------------------------------------------------------------===//
326/// SelectionDAGLowering - This is the common target-independent lowering
327/// implementation that is parameterized by a TargetLowering object.
328/// Also, targets can overload any lowering method.
329///
330namespace llvm {
331class SelectionDAGLowering {
332 MachineBasicBlock *CurMBB;
333
Chris Lattner0da331f2007-02-04 01:31:47 +0000334 DenseMap<const Value*, SDOperand> NodeMap;
Chris Lattner1c08c712005-01-07 07:47:53 +0000335
Chris Lattnerd3948112005-01-17 22:19:26 +0000336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
337 /// them up and then emit token factor nodes when possible. This allows us to
338 /// get simple disambiguation between loads without worrying about alias
339 /// analysis.
340 std::vector<SDOperand> PendingLoads;
341
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000342 /// Case - A struct to record the Value for a switch case, and the
343 /// case's target basic block.
344 struct Case {
345 Constant* Low;
346 Constant* High;
347 MachineBasicBlock* BB;
348
349 Case() : Low(0), High(0), BB(0) { }
350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
351 Low(low), High(high), BB(bb) { }
352 uint64_t size() const {
353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
355 return (rHigh - rLow + 1ULL);
356 }
357 };
358
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000359 struct CaseBits {
360 uint64_t Mask;
361 MachineBasicBlock* BB;
362 unsigned Bits;
363
364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
365 Mask(mask), BB(bb), Bits(bits) { }
366 };
367
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000368 typedef std::vector<Case> CaseVector;
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000369 typedef std::vector<CaseBits> CaseBitsVector;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000370 typedef CaseVector::iterator CaseItr;
371 typedef std::pair<CaseItr, CaseItr> CaseRange;
Nate Begemanf15485a2006-03-27 01:32:24 +0000372
373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
374 /// of conditional branches.
375 struct CaseRec {
376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
377 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
378
379 /// CaseBB - The MBB in which to emit the compare and branch
380 MachineBasicBlock *CaseBB;
381 /// LT, GE - If nonzero, we know the current case value must be less-than or
382 /// greater-than-or-equal-to these Constants.
383 Constant *LT;
384 Constant *GE;
385 /// Range - A pair of iterators representing the range of case values to be
386 /// processed at this point in the binary search tree.
387 CaseRange Range;
388 };
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000389
390 typedef std::vector<CaseRec> CaseRecVector;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000391
392 /// The comparison function for sorting the switch case values in the vector.
393 /// WARNING: Case ranges should be disjoint!
Nate Begemanf15485a2006-03-27 01:32:24 +0000394 struct CaseCmp {
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000395 bool operator () (const Case& C1, const Case& C2) {
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
399 return CI1->getValue().slt(CI2->getValue());
Nate Begemanf15485a2006-03-27 01:32:24 +0000400 }
401 };
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000402
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000403 struct CaseBitsCmp {
404 bool operator () (const CaseBits& C1, const CaseBits& C2) {
405 return C1.Bits > C2.Bits;
406 }
407 };
408
Anton Korobeynikov5502bf62007-04-04 21:14:49 +0000409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
Nate Begemanf15485a2006-03-27 01:32:24 +0000410
Chris Lattner1c08c712005-01-07 07:47:53 +0000411public:
412 // TLI - This is information that describes the available target features we
413 // need for lowering. This indicates when operations are unavailable,
414 // implemented with a libcall, etc.
415 TargetLowering &TLI;
416 SelectionDAG &DAG;
Owen Andersona69571c2006-05-03 01:29:57 +0000417 const TargetData *TD;
Dan Gohman5f43f922007-08-27 16:26:13 +0000418 AliasAnalysis &AA;
Chris Lattner1c08c712005-01-07 07:47:53 +0000419
Nate Begemanf15485a2006-03-27 01:32:24 +0000420 /// SwitchCases - Vector of CaseBlock structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000423 /// JTCases - Vector of JumpTable structures used to communicate
424 /// SwitchInst code generation information.
425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
Nate Begemanf15485a2006-03-27 01:32:24 +0000427
Chris Lattner1c08c712005-01-07 07:47:53 +0000428 /// FuncInfo - Information about the function as a whole.
429 ///
430 FunctionLoweringInfo &FuncInfo;
Gordon Henriksence224772008-01-07 01:30:38 +0000431
432 /// GCI - Garbage collection metadata for the function.
433 CollectorMetadata *GCI;
Chris Lattner1c08c712005-01-07 07:47:53 +0000434
435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
Dan Gohman5f43f922007-08-27 16:26:13 +0000436 AliasAnalysis &aa,
Gordon Henriksence224772008-01-07 01:30:38 +0000437 FunctionLoweringInfo &funcinfo,
438 CollectorMetadata *gci)
Dan Gohman5f43f922007-08-27 16:26:13 +0000439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
Gordon Henriksence224772008-01-07 01:30:38 +0000440 FuncInfo(funcinfo), GCI(gci) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000441 }
442
Chris Lattnera651cf62005-01-17 19:43:36 +0000443 /// getRoot - Return the current virtual root of the Selection DAG.
444 ///
445 SDOperand getRoot() {
Chris Lattnerd3948112005-01-17 22:19:26 +0000446 if (PendingLoads.empty())
447 return DAG.getRoot();
Misha Brukmanedf128a2005-04-21 22:36:52 +0000448
Chris Lattnerd3948112005-01-17 22:19:26 +0000449 if (PendingLoads.size() == 1) {
450 SDOperand Root = PendingLoads[0];
451 DAG.setRoot(Root);
452 PendingLoads.clear();
453 return Root;
454 }
455
456 // Otherwise, we have to make a token factor node.
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
458 &PendingLoads[0], PendingLoads.size());
Chris Lattnerd3948112005-01-17 22:19:26 +0000459 PendingLoads.clear();
460 DAG.setRoot(Root);
461 return Root;
Chris Lattnera651cf62005-01-17 19:43:36 +0000462 }
463
Chris Lattner571e4342006-10-27 21:36:01 +0000464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
465
Chris Lattner1c08c712005-01-07 07:47:53 +0000466 void visit(Instruction &I) { visit(I.getOpcode(), I); }
467
468 void visit(unsigned Opcode, User &I) {
Chris Lattner1e7aa5c2006-11-10 04:41:34 +0000469 // Note: this doesn't use InstVisitor, because it has to work with
470 // ConstantExpr's in addition to instructions.
Chris Lattner1c08c712005-01-07 07:47:53 +0000471 switch (Opcode) {
472 default: assert(0 && "Unknown instruction type encountered!");
473 abort();
474 // Build the switch statement using the Instruction.def file.
475#define HANDLE_INST(NUM, OPCODE, CLASS) \
476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
477#include "llvm/Instruction.def"
478 }
479 }
480
481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
482
Chris Lattner28b5b1c2006-03-15 22:19:46 +0000483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
Evan Cheng466685d2006-10-09 20:57:25 +0000484 const Value *SV, SDOperand Root,
Christopher Lamb95c218a2007-04-22 23:15:30 +0000485 bool isVolatile, unsigned Alignment);
Chris Lattner1c08c712005-01-07 07:47:53 +0000486
Chris Lattner199862b2006-03-16 19:57:50 +0000487 SDOperand getValue(const Value *V);
Chris Lattner1c08c712005-01-07 07:47:53 +0000488
Chris Lattner0da331f2007-02-04 01:31:47 +0000489 void setValue(const Value *V, SDOperand NewN) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000490 SDOperand &N = NodeMap[V];
491 assert(N.Val == 0 && "Already set a value for this node!");
Chris Lattner0da331f2007-02-04 01:31:47 +0000492 N = NewN;
Chris Lattner1c08c712005-01-07 07:47:53 +0000493 }
Chris Lattner4e4b5762006-02-01 18:59:47 +0000494
Chris Lattnere7cf56a2007-04-30 21:11:17 +0000495 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
496 std::set<unsigned> &OutputRegs,
497 std::set<unsigned> &InputRegs);
Nate Begemanf15485a2006-03-27 01:32:24 +0000498
Chris Lattner571e4342006-10-27 21:36:01 +0000499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
501 unsigned Opc);
Chris Lattner8c494ab2006-10-27 23:50:33 +0000502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
Chris Lattner571e4342006-10-27 21:36:01 +0000503 void ExportFromCurrentBlock(Value *V);
Duncan Sands6f74b482007-12-19 09:48:52 +0000504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
Anton Korobeynikov070280e2007-05-23 11:08:31 +0000505 MachineBasicBlock *LandingPad = NULL);
Duncan Sandsdc024672007-11-27 13:23:08 +0000506
Chris Lattner1c08c712005-01-07 07:47:53 +0000507 // Terminator instructions.
508 void visitRet(ReturnInst &I);
509 void visitBr(BranchInst &I);
Nate Begemanf15485a2006-03-27 01:32:24 +0000510 void visitSwitch(SwitchInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000511 void visitUnreachable(UnreachableInst &I) { /* noop */ }
512
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000513 // Helpers for visitSwitch
Anton Korobeynikovdd433212007-03-27 12:05:48 +0000514 bool handleSmallSwitchRange(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000515 CaseRecVector& WorkList,
516 Value* SV,
517 MachineBasicBlock* Default);
Anton Korobeynikovdd433212007-03-27 12:05:48 +0000518 bool handleJTSwitchCase(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000519 CaseRecVector& WorkList,
520 Value* SV,
521 MachineBasicBlock* Default);
Anton Korobeynikovdd433212007-03-27 12:05:48 +0000522 bool handleBTSplitSwitchCase(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +0000523 CaseRecVector& WorkList,
524 Value* SV,
525 MachineBasicBlock* Default);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000526 bool handleBitTestsSwitchCase(CaseRec& CR,
527 CaseRecVector& WorkList,
528 Value* SV,
529 MachineBasicBlock* Default);
Nate Begemanf15485a2006-03-27 01:32:24 +0000530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
532 void visitBitTestCase(MachineBasicBlock* NextMBB,
533 unsigned Reg,
534 SelectionDAGISel::BitTestCase &B);
Nate Begeman37efe672006-04-22 18:53:45 +0000535 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +0000536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
537 SelectionDAGISel::JumpTableHeader &JTH);
Nate Begemanf15485a2006-03-27 01:32:24 +0000538
Chris Lattner1c08c712005-01-07 07:47:53 +0000539 // These all get lowered before this pass.
Jim Laskeyb180aa12007-02-21 22:53:45 +0000540 void visitInvoke(InvokeInst &I);
541 void visitUnwind(UnwindInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000542
Dan Gohman7f321562007-06-25 16:23:39 +0000543 void visitBinary(User &I, unsigned OpCode);
Nate Begemane21ea612005-11-18 07:42:56 +0000544 void visitShift(User &I, unsigned Opcode);
Nate Begeman5fbb5d22005-11-19 00:36:38 +0000545 void visitAdd(User &I) {
Dan Gohman7f321562007-06-25 16:23:39 +0000546 if (I.getType()->isFPOrFPVector())
547 visitBinary(I, ISD::FADD);
Reid Spencer1628cec2006-10-26 06:15:43 +0000548 else
Dan Gohman7f321562007-06-25 16:23:39 +0000549 visitBinary(I, ISD::ADD);
Chris Lattner01b3d732005-09-28 22:28:18 +0000550 }
Chris Lattnerb9fccc42005-04-02 05:04:50 +0000551 void visitSub(User &I);
Reid Spencer1628cec2006-10-26 06:15:43 +0000552 void visitMul(User &I) {
Dan Gohman7f321562007-06-25 16:23:39 +0000553 if (I.getType()->isFPOrFPVector())
554 visitBinary(I, ISD::FMUL);
Reid Spencer1628cec2006-10-26 06:15:43 +0000555 else
Dan Gohman7f321562007-06-25 16:23:39 +0000556 visitBinary(I, ISD::MUL);
Chris Lattner01b3d732005-09-28 22:28:18 +0000557 }
Dan Gohman7f321562007-06-25 16:23:39 +0000558 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
564 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
565 void visitOr (User &I) { visitBinary(I, ISD::OR); }
566 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
Reid Spencer24d6da52007-01-21 00:29:26 +0000567 void visitShl (User &I) { visitShift(I, ISD::SHL); }
Reid Spencer3822ff52006-11-08 06:47:33 +0000568 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
569 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
Reid Spencer45fb3f32006-11-20 01:22:35 +0000570 void visitICmp(User &I);
571 void visitFCmp(User &I);
Reid Spencer3da59db2006-11-27 01:05:10 +0000572 // Visit the conversion instructions
573 void visitTrunc(User &I);
574 void visitZExt(User &I);
575 void visitSExt(User &I);
576 void visitFPTrunc(User &I);
577 void visitFPExt(User &I);
578 void visitFPToUI(User &I);
579 void visitFPToSI(User &I);
580 void visitUIToFP(User &I);
581 void visitSIToFP(User &I);
582 void visitPtrToInt(User &I);
583 void visitIntToPtr(User &I);
584 void visitBitCast(User &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000585
Chris Lattner2bbd8102006-03-29 00:11:43 +0000586 void visitExtractElement(User &I);
587 void visitInsertElement(User &I);
Chris Lattner3e104b12006-04-08 04:15:24 +0000588 void visitShuffleVector(User &I);
Chris Lattnerc7029802006-03-18 01:44:44 +0000589
Chris Lattner1c08c712005-01-07 07:47:53 +0000590 void visitGetElementPtr(User &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000591 void visitSelect(User &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000592
593 void visitMalloc(MallocInst &I);
594 void visitFree(FreeInst &I);
595 void visitAlloca(AllocaInst &I);
596 void visitLoad(LoadInst &I);
597 void visitStore(StoreInst &I);
598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
599 void visitCall(CallInst &I);
Duncan Sandsfd7b3262007-12-17 18:08:19 +0000600 void visitInlineAsm(CallSite CS);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +0000601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
Chris Lattner0eade312006-03-24 02:22:33 +0000602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
Chris Lattner1c08c712005-01-07 07:47:53 +0000603
Chris Lattner1c08c712005-01-07 07:47:53 +0000604 void visitVAStart(CallInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000605 void visitVAArg(VAArgInst &I);
606 void visitVAEnd(CallInst &I);
607 void visitVACopy(CallInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000608
Chris Lattner7041ee32005-01-11 05:56:49 +0000609 void visitMemIntrinsic(CallInst &I, unsigned Op);
Chris Lattner1c08c712005-01-07 07:47:53 +0000610
611 void visitUserOp1(Instruction &I) {
612 assert(0 && "UserOp1 should not exist at instruction selection time!");
613 abort();
614 }
615 void visitUserOp2(Instruction &I) {
616 assert(0 && "UserOp2 should not exist at instruction selection time!");
617 abort();
618 }
619};
620} // end namespace llvm
621
Dan Gohman6183f782007-07-05 20:12:34 +0000622
623/// getCopyFromParts - Create a value that contains the
624/// specified legal parts combined into the value they represent.
625static SDOperand getCopyFromParts(SelectionDAG &DAG,
626 const SDOperand *Parts,
627 unsigned NumParts,
628 MVT::ValueType PartVT,
629 MVT::ValueType ValueVT,
Dan Gohman6183f782007-07-05 20:12:34 +0000630 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
631 if (!MVT::isVector(ValueVT) || NumParts == 1) {
632 SDOperand Val = Parts[0];
633
634 // If the value was expanded, copy from the top part.
635 if (NumParts > 1) {
636 assert(NumParts == 2 &&
637 "Cannot expand to more than 2 elts yet!");
638 SDOperand Hi = Parts[1];
Dan Gohman532dc2e2007-07-09 20:59:04 +0000639 if (!DAG.getTargetLoweringInfo().isLittleEndian())
Dan Gohman6183f782007-07-05 20:12:34 +0000640 std::swap(Val, Hi);
641 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
642 }
643
644 // Otherwise, if the value was promoted or extended, truncate it to the
645 // appropriate type.
646 if (PartVT == ValueVT)
647 return Val;
648
649 if (MVT::isVector(PartVT)) {
650 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
Dan Gohmana9b51112007-10-12 14:33:11 +0000651 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
652 }
653
654 if (MVT::isVector(ValueVT)) {
655 assert(NumParts == 1 &&
656 MVT::getVectorElementType(ValueVT) == PartVT &&
657 MVT::getVectorNumElements(ValueVT) == 1 &&
658 "Only trivial scalar-to-vector conversions should get here!");
659 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
Dan Gohman6183f782007-07-05 20:12:34 +0000660 }
661
662 if (MVT::isInteger(PartVT) &&
663 MVT::isInteger(ValueVT)) {
664 if (ValueVT < PartVT) {
665 // For a truncate, see if we have any information to
666 // indicate whether the truncated bits will always be
667 // zero or sign-extension.
668 if (AssertOp != ISD::DELETED_NODE)
669 Val = DAG.getNode(AssertOp, PartVT, Val,
670 DAG.getValueType(ValueVT));
671 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
672 } else {
673 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
674 }
675 }
676
Chris Lattner0bd48932008-01-17 07:00:52 +0000677 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
678 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, DAG.getIntPtrConstant(0));
Dan Gohman6183f782007-07-05 20:12:34 +0000679
Chris Lattner0bd48932008-01-17 07:00:52 +0000680 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
Dan Gohman6183f782007-07-05 20:12:34 +0000681 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
682
683 assert(0 && "Unknown mismatch!");
684 }
685
686 // Handle a multi-element vector.
687 MVT::ValueType IntermediateVT, RegisterVT;
688 unsigned NumIntermediates;
689 unsigned NumRegs =
690 DAG.getTargetLoweringInfo()
691 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
692 RegisterVT);
693
694 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
695 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
696 assert(RegisterVT == Parts[0].getValueType() &&
697 "Part type doesn't match part!");
698
699 // Assemble the parts into intermediate operands.
700 SmallVector<SDOperand, 8> Ops(NumIntermediates);
701 if (NumIntermediates == NumParts) {
702 // If the register was not expanded, truncate or copy the value,
703 // as appropriate.
704 for (unsigned i = 0; i != NumParts; ++i)
705 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
Dan Gohman532dc2e2007-07-09 20:59:04 +0000706 PartVT, IntermediateVT);
Dan Gohman6183f782007-07-05 20:12:34 +0000707 } else if (NumParts > 0) {
708 // If the intermediate type was expanded, build the intermediate operands
709 // from the parts.
Dan Gohmanbe444ed2007-07-30 19:09:17 +0000710 assert(NumParts % NumIntermediates == 0 &&
Dan Gohman6183f782007-07-05 20:12:34 +0000711 "Must expand into a divisible number of parts!");
Dan Gohmanbe444ed2007-07-30 19:09:17 +0000712 unsigned Factor = NumParts / NumIntermediates;
Dan Gohman6183f782007-07-05 20:12:34 +0000713 for (unsigned i = 0; i != NumIntermediates; ++i)
714 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
Dan Gohman532dc2e2007-07-09 20:59:04 +0000715 PartVT, IntermediateVT);
Dan Gohman6183f782007-07-05 20:12:34 +0000716 }
717
718 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
719 // operands.
720 return DAG.getNode(MVT::isVector(IntermediateVT) ?
721 ISD::CONCAT_VECTORS :
722 ISD::BUILD_VECTOR,
Dan Gohmanbe444ed2007-07-30 19:09:17 +0000723 ValueVT, &Ops[0], NumIntermediates);
Dan Gohman6183f782007-07-05 20:12:34 +0000724}
725
726/// getCopyToParts - Create a series of nodes that contain the
727/// specified value split into legal parts.
728static void getCopyToParts(SelectionDAG &DAG,
729 SDOperand Val,
730 SDOperand *Parts,
731 unsigned NumParts,
Dan Gohman532dc2e2007-07-09 20:59:04 +0000732 MVT::ValueType PartVT) {
Dan Gohman25ac7e82007-08-10 14:59:38 +0000733 TargetLowering &TLI = DAG.getTargetLoweringInfo();
734 MVT::ValueType PtrVT = TLI.getPointerTy();
Dan Gohman6183f782007-07-05 20:12:34 +0000735 MVT::ValueType ValueVT = Val.getValueType();
736
737 if (!MVT::isVector(ValueVT) || NumParts == 1) {
738 // If the value was expanded, copy from the parts.
739 if (NumParts > 1) {
740 for (unsigned i = 0; i != NumParts; ++i)
741 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
Dan Gohman25ac7e82007-08-10 14:59:38 +0000742 DAG.getConstant(i, PtrVT));
Dan Gohman532dc2e2007-07-09 20:59:04 +0000743 if (!DAG.getTargetLoweringInfo().isLittleEndian())
Dan Gohman6183f782007-07-05 20:12:34 +0000744 std::reverse(Parts, Parts + NumParts);
745 return;
746 }
747
748 // If there is a single part and the types differ, this must be
749 // a promotion.
750 if (PartVT != ValueVT) {
751 if (MVT::isVector(PartVT)) {
752 assert(MVT::isVector(ValueVT) &&
753 "Not a vector-vector cast?");
754 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
Dan Gohmana9b51112007-10-12 14:33:11 +0000755 } else if (MVT::isVector(ValueVT)) {
756 assert(NumParts == 1 &&
757 MVT::getVectorElementType(ValueVT) == PartVT &&
758 MVT::getVectorNumElements(ValueVT) == 1 &&
759 "Only trivial vector-to-scalar conversions should get here!");
760 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
761 DAG.getConstant(0, PtrVT));
Dan Gohman6183f782007-07-05 20:12:34 +0000762 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
763 if (PartVT < ValueVT)
764 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
765 else
766 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
767 } else if (MVT::isFloatingPoint(PartVT) &&
768 MVT::isFloatingPoint(ValueVT)) {
769 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
770 } else if (MVT::getSizeInBits(PartVT) ==
771 MVT::getSizeInBits(ValueVT)) {
772 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
773 } else {
774 assert(0 && "Unknown mismatch!");
775 }
776 }
777 Parts[0] = Val;
778 return;
779 }
780
781 // Handle a multi-element vector.
782 MVT::ValueType IntermediateVT, RegisterVT;
783 unsigned NumIntermediates;
784 unsigned NumRegs =
785 DAG.getTargetLoweringInfo()
786 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
787 RegisterVT);
788 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
789
790 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
791 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
792
793 // Split the vector into intermediate operands.
794 SmallVector<SDOperand, 8> Ops(NumIntermediates);
795 for (unsigned i = 0; i != NumIntermediates; ++i)
796 if (MVT::isVector(IntermediateVT))
797 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
798 IntermediateVT, Val,
799 DAG.getConstant(i * (NumElements / NumIntermediates),
Dan Gohman25ac7e82007-08-10 14:59:38 +0000800 PtrVT));
Dan Gohman6183f782007-07-05 20:12:34 +0000801 else
802 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
803 IntermediateVT, Val,
Dan Gohman25ac7e82007-08-10 14:59:38 +0000804 DAG.getConstant(i, PtrVT));
Dan Gohman6183f782007-07-05 20:12:34 +0000805
806 // Split the intermediate operands into legal parts.
807 if (NumParts == NumIntermediates) {
808 // If the register was not expanded, promote or copy the value,
809 // as appropriate.
810 for (unsigned i = 0; i != NumParts; ++i)
Dan Gohman532dc2e2007-07-09 20:59:04 +0000811 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
Dan Gohman6183f782007-07-05 20:12:34 +0000812 } else if (NumParts > 0) {
813 // If the intermediate type was expanded, split each the value into
814 // legal parts.
815 assert(NumParts % NumIntermediates == 0 &&
816 "Must expand into a divisible number of parts!");
817 unsigned Factor = NumParts / NumIntermediates;
818 for (unsigned i = 0; i != NumIntermediates; ++i)
Dan Gohman532dc2e2007-07-09 20:59:04 +0000819 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
Dan Gohman6183f782007-07-05 20:12:34 +0000820 }
821}
822
823
Chris Lattner199862b2006-03-16 19:57:50 +0000824SDOperand SelectionDAGLowering::getValue(const Value *V) {
825 SDOperand &N = NodeMap[V];
826 if (N.Val) return N;
827
828 const Type *VTy = V->getType();
829 MVT::ValueType VT = TLI.getValueType(VTy);
830 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
831 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
832 visit(CE->getOpcode(), *CE);
Chris Lattner0da331f2007-02-04 01:31:47 +0000833 SDOperand N1 = NodeMap[V];
834 assert(N1.Val && "visit didn't populate the ValueMap!");
835 return N1;
Chris Lattner199862b2006-03-16 19:57:50 +0000836 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
837 return N = DAG.getGlobalAddress(GV, VT);
838 } else if (isa<ConstantPointerNull>(C)) {
839 return N = DAG.getConstant(0, TLI.getPointerTy());
840 } else if (isa<UndefValue>(C)) {
Reid Spencer9d6565a2007-02-15 02:26:10 +0000841 if (!isa<VectorType>(VTy))
Chris Lattner23d564c2006-03-19 00:20:20 +0000842 return N = DAG.getNode(ISD::UNDEF, VT);
843
Dan Gohman7f321562007-06-25 16:23:39 +0000844 // Create a BUILD_VECTOR of undef nodes.
Reid Spencer9d6565a2007-02-15 02:26:10 +0000845 const VectorType *PTy = cast<VectorType>(VTy);
Chris Lattner23d564c2006-03-19 00:20:20 +0000846 unsigned NumElements = PTy->getNumElements();
847 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
848
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000849 SmallVector<SDOperand, 8> Ops;
Chris Lattner23d564c2006-03-19 00:20:20 +0000850 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
851
852 // Create a VConstant node with generic Vector type.
Dan Gohman7f321562007-06-25 16:23:39 +0000853 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
854 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000855 &Ops[0], Ops.size());
Chris Lattner199862b2006-03-16 19:57:50 +0000856 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
Dale Johannesen43421b32007-09-06 18:13:44 +0000857 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
Reid Spencer9d6565a2007-02-15 02:26:10 +0000858 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
Chris Lattner199862b2006-03-16 19:57:50 +0000859 unsigned NumElements = PTy->getNumElements();
860 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
Chris Lattner199862b2006-03-16 19:57:50 +0000861
862 // Now that we know the number and type of the elements, push a
863 // Constant or ConstantFP node onto the ops list for each element of
Dan Gohman07a96762007-07-16 14:29:03 +0000864 // the vector constant.
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000865 SmallVector<SDOperand, 8> Ops;
Reid Spencer9d6565a2007-02-15 02:26:10 +0000866 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
Chris Lattner2bbd8102006-03-29 00:11:43 +0000867 for (unsigned i = 0; i != NumElements; ++i)
868 Ops.push_back(getValue(CP->getOperand(i)));
Chris Lattner199862b2006-03-16 19:57:50 +0000869 } else {
Dan Gohman07a96762007-07-16 14:29:03 +0000870 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
Chris Lattner199862b2006-03-16 19:57:50 +0000871 SDOperand Op;
872 if (MVT::isFloatingPoint(PVT))
873 Op = DAG.getConstantFP(0, PVT);
874 else
875 Op = DAG.getConstant(0, PVT);
876 Ops.assign(NumElements, Op);
877 }
878
Dan Gohman7f321562007-06-25 16:23:39 +0000879 // Create a BUILD_VECTOR node.
880 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
881 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
Chris Lattner0da331f2007-02-04 01:31:47 +0000882 Ops.size());
Chris Lattner199862b2006-03-16 19:57:50 +0000883 } else {
884 // Canonicalize all constant ints to be unsigned.
Zhou Sheng6b6b6ef2007-01-11 12:24:14 +0000885 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
Chris Lattner199862b2006-03-16 19:57:50 +0000886 }
887 }
888
889 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
890 std::map<const AllocaInst*, int>::iterator SI =
891 FuncInfo.StaticAllocaMap.find(AI);
892 if (SI != FuncInfo.StaticAllocaMap.end())
893 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
894 }
895
Chris Lattner251db182007-02-25 18:40:32 +0000896 unsigned InReg = FuncInfo.ValueMap[V];
897 assert(InReg && "Value not in map!");
Chris Lattner199862b2006-03-16 19:57:50 +0000898
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000899 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
900 unsigned NumRegs = TLI.getNumRegisters(VT);
Chris Lattner70c2a612006-03-31 02:06:56 +0000901
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000902 std::vector<unsigned> Regs(NumRegs);
903 for (unsigned i = 0; i != NumRegs; ++i)
904 Regs[i] = InReg + i;
905
906 RegsForValue RFV(Regs, RegisterVT, VT);
907 SDOperand Chain = DAG.getEntryNode();
908
909 return RFV.getCopyFromRegs(DAG, Chain, NULL);
Chris Lattner199862b2006-03-16 19:57:50 +0000910}
911
912
Chris Lattner1c08c712005-01-07 07:47:53 +0000913void SelectionDAGLowering::visitRet(ReturnInst &I) {
914 if (I.getNumOperands() == 0) {
Chris Lattnera651cf62005-01-17 19:43:36 +0000915 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
Chris Lattner1c08c712005-01-07 07:47:53 +0000916 return;
917 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000918 SmallVector<SDOperand, 8> NewValues;
Nate Begemanee625572006-01-27 21:09:22 +0000919 NewValues.push_back(getRoot());
920 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
921 SDOperand RetOp = getValue(I.getOperand(i));
922
923 // If this is an integer return value, we need to promote it ourselves to
Dan Gohman6183f782007-07-05 20:12:34 +0000924 // the full width of a register, since getCopyToParts and Legalize will use
925 // ANY_EXTEND rather than sign/zero.
Evan Cheng8e7d0562006-05-26 23:09:09 +0000926 // FIXME: C calling convention requires the return type to be promoted to
927 // at least 32-bit. But this is not necessary for non-C calling conventions.
Nate Begemanee625572006-01-27 21:09:22 +0000928 if (MVT::isInteger(RetOp.getValueType()) &&
929 RetOp.getValueType() < MVT::i64) {
930 MVT::ValueType TmpVT;
931 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
932 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
933 else
934 TmpVT = MVT::i32;
Duncan Sandsafa3b6d2007-11-28 17:07:01 +0000935 const Function *F = I.getParent()->getParent();
Reid Spencerbcca3402007-01-03 16:49:33 +0000936 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
Duncan Sandsafa3b6d2007-11-28 17:07:01 +0000937 if (F->paramHasAttr(0, ParamAttr::SExt))
Reid Spencer8c57dfb2007-01-03 04:25:33 +0000938 ExtendKind = ISD::SIGN_EXTEND;
Duncan Sandsafa3b6d2007-11-28 17:07:01 +0000939 if (F->paramHasAttr(0, ParamAttr::ZExt))
Reid Spencer47857812006-12-31 05:55:36 +0000940 ExtendKind = ISD::ZERO_EXTEND;
Reid Spencer376dd212007-01-03 05:03:05 +0000941 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
Dan Gohman6183f782007-07-05 20:12:34 +0000942 NewValues.push_back(RetOp);
943 NewValues.push_back(DAG.getConstant(false, MVT::i32));
944 } else {
945 MVT::ValueType VT = RetOp.getValueType();
946 unsigned NumParts = TLI.getNumRegisters(VT);
947 MVT::ValueType PartVT = TLI.getRegisterType(VT);
948 SmallVector<SDOperand, 4> Parts(NumParts);
Dan Gohman532dc2e2007-07-09 20:59:04 +0000949 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
Dan Gohman6183f782007-07-05 20:12:34 +0000950 for (unsigned i = 0; i < NumParts; ++i) {
951 NewValues.push_back(Parts[i]);
952 NewValues.push_back(DAG.getConstant(false, MVT::i32));
953 }
Nate Begemanee625572006-01-27 21:09:22 +0000954 }
Chris Lattner1c08c712005-01-07 07:47:53 +0000955 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000956 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
957 &NewValues[0], NewValues.size()));
Chris Lattner1c08c712005-01-07 07:47:53 +0000958}
959
Chris Lattner571e4342006-10-27 21:36:01 +0000960/// ExportFromCurrentBlock - If this condition isn't known to be exported from
961/// the current basic block, add it to ValueMap now so that we'll get a
962/// CopyTo/FromReg.
963void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
964 // No need to export constants.
965 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
966
967 // Already exported?
968 if (FuncInfo.isExportedInst(V)) return;
969
970 unsigned Reg = FuncInfo.InitializeRegForValue(V);
971 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
972}
973
Chris Lattner8c494ab2006-10-27 23:50:33 +0000974bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
975 const BasicBlock *FromBB) {
976 // The operands of the setcc have to be in this block. We don't know
977 // how to export them from some other block.
978 if (Instruction *VI = dyn_cast<Instruction>(V)) {
979 // Can export from current BB.
980 if (VI->getParent() == FromBB)
981 return true;
982
983 // Is already exported, noop.
984 return FuncInfo.isExportedInst(V);
985 }
986
987 // If this is an argument, we can export it if the BB is the entry block or
988 // if it is already exported.
989 if (isa<Argument>(V)) {
990 if (FromBB == &FromBB->getParent()->getEntryBlock())
991 return true;
992
993 // Otherwise, can only export this if it is already exported.
994 return FuncInfo.isExportedInst(V);
995 }
996
997 // Otherwise, constants can always be exported.
998 return true;
999}
1000
Chris Lattner6a586c82006-10-29 21:01:20 +00001001static bool InBlock(const Value *V, const BasicBlock *BB) {
1002 if (const Instruction *I = dyn_cast<Instruction>(V))
1003 return I->getParent() == BB;
1004 return true;
1005}
1006
Chris Lattner571e4342006-10-27 21:36:01 +00001007/// FindMergedConditions - If Cond is an expression like
1008void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1009 MachineBasicBlock *TBB,
1010 MachineBasicBlock *FBB,
1011 MachineBasicBlock *CurBB,
1012 unsigned Opc) {
Chris Lattner571e4342006-10-27 21:36:01 +00001013 // If this node is not part of the or/and tree, emit it as a branch.
Reid Spencere4d87aa2006-12-23 06:05:41 +00001014 Instruction *BOp = dyn_cast<Instruction>(Cond);
Chris Lattner571e4342006-10-27 21:36:01 +00001015
Reid Spencere4d87aa2006-12-23 06:05:41 +00001016 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1017 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
Chris Lattner6a586c82006-10-29 21:01:20 +00001018 BOp->getParent() != CurBB->getBasicBlock() ||
1019 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1020 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
Chris Lattner571e4342006-10-27 21:36:01 +00001021 const BasicBlock *BB = CurBB->getBasicBlock();
1022
Reid Spencere4d87aa2006-12-23 06:05:41 +00001023 // If the leaf of the tree is a comparison, merge the condition into
1024 // the caseblock.
1025 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1026 // The operands of the cmp have to be in this block. We don't know
Chris Lattner5a145f02006-10-29 18:23:37 +00001027 // how to export them from some other block. If this is the first block
1028 // of the sequence, no exporting is needed.
1029 (CurBB == CurMBB ||
1030 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1031 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
Reid Spencere4d87aa2006-12-23 06:05:41 +00001032 BOp = cast<Instruction>(Cond);
1033 ISD::CondCode Condition;
1034 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1035 switch (IC->getPredicate()) {
1036 default: assert(0 && "Unknown icmp predicate opcode!");
1037 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1038 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1039 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1040 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1041 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1042 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1043 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1044 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1045 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1046 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1047 }
1048 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1049 ISD::CondCode FPC, FOC;
1050 switch (FC->getPredicate()) {
1051 default: assert(0 && "Unknown fcmp predicate opcode!");
1052 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1053 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1054 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1055 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1056 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1057 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1058 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1059 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1060 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1061 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1062 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1063 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1064 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1065 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1066 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1067 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1068 }
1069 if (FiniteOnlyFPMath())
1070 Condition = FOC;
1071 else
1072 Condition = FPC;
1073 } else {
Chris Lattner0da331f2007-02-04 01:31:47 +00001074 Condition = ISD::SETEQ; // silence warning.
Reid Spencere4d87aa2006-12-23 06:05:41 +00001075 assert(0 && "Unknown compare instruction");
Chris Lattner571e4342006-10-27 21:36:01 +00001076 }
1077
Chris Lattner571e4342006-10-27 21:36:01 +00001078 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001079 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
Chris Lattner571e4342006-10-27 21:36:01 +00001080 SwitchCases.push_back(CB);
1081 return;
1082 }
1083
1084 // Create a CaseBlock record representing this branch.
Zhou Sheng6b6b6ef2007-01-11 12:24:14 +00001085 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001086 NULL, TBB, FBB, CurBB);
Chris Lattner571e4342006-10-27 21:36:01 +00001087 SwitchCases.push_back(CB);
Chris Lattner571e4342006-10-27 21:36:01 +00001088 return;
1089 }
1090
Chris Lattnerd2f9ee92006-10-27 21:54:23 +00001091
1092 // Create TmpBB after CurBB.
Chris Lattner571e4342006-10-27 21:36:01 +00001093 MachineFunction::iterator BBI = CurBB;
1094 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1095 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1096
Chris Lattnerd2f9ee92006-10-27 21:54:23 +00001097 if (Opc == Instruction::Or) {
1098 // Codegen X | Y as:
1099 // jmp_if_X TBB
1100 // jmp TmpBB
1101 // TmpBB:
1102 // jmp_if_Y TBB
1103 // jmp FBB
1104 //
Chris Lattner571e4342006-10-27 21:36:01 +00001105
Chris Lattnerd2f9ee92006-10-27 21:54:23 +00001106 // Emit the LHS condition.
1107 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1108
1109 // Emit the RHS condition into TmpBB.
1110 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1111 } else {
1112 assert(Opc == Instruction::And && "Unknown merge op!");
1113 // Codegen X & Y as:
1114 // jmp_if_X TmpBB
1115 // jmp FBB
1116 // TmpBB:
1117 // jmp_if_Y TBB
1118 // jmp FBB
1119 //
1120 // This requires creation of TmpBB after CurBB.
1121
1122 // Emit the LHS condition.
1123 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1124
1125 // Emit the RHS condition into TmpBB.
1126 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1127 }
Chris Lattner571e4342006-10-27 21:36:01 +00001128}
1129
Chris Lattnerdf19f272006-10-31 22:37:42 +00001130/// If the set of cases should be emitted as a series of branches, return true.
1131/// If we should emit this as a bunch of and/or'd together conditions, return
1132/// false.
1133static bool
1134ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1135 if (Cases.size() != 2) return true;
1136
Chris Lattner0ccb5002006-10-31 23:06:00 +00001137 // If this is two comparisons of the same values or'd or and'd together, they
1138 // will get folded into a single comparison, so don't emit two blocks.
1139 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1140 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1141 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1142 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1143 return false;
1144 }
1145
Chris Lattnerdf19f272006-10-31 22:37:42 +00001146 return true;
1147}
1148
Chris Lattner1c08c712005-01-07 07:47:53 +00001149void SelectionDAGLowering::visitBr(BranchInst &I) {
1150 // Update machine-CFG edges.
1151 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
Chris Lattner1c08c712005-01-07 07:47:53 +00001152
1153 // Figure out which block is immediately after the current one.
1154 MachineBasicBlock *NextBlock = 0;
1155 MachineFunction::iterator BBI = CurMBB;
1156 if (++BBI != CurMBB->getParent()->end())
1157 NextBlock = BBI;
1158
1159 if (I.isUnconditional()) {
1160 // If this is not a fall-through branch, emit the branch.
1161 if (Succ0MBB != NextBlock)
Chris Lattnera651cf62005-01-17 19:43:36 +00001162 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
Misha Brukmandedf2bd2005-04-22 04:01:18 +00001163 DAG.getBasicBlock(Succ0MBB)));
Chris Lattner1c08c712005-01-07 07:47:53 +00001164
Chris Lattner57ab6592006-10-24 17:57:59 +00001165 // Update machine-CFG edges.
1166 CurMBB->addSuccessor(Succ0MBB);
Chris Lattner57ab6592006-10-24 17:57:59 +00001167 return;
1168 }
1169
1170 // If this condition is one of the special cases we handle, do special stuff
1171 // now.
1172 Value *CondVal = I.getCondition();
Chris Lattner57ab6592006-10-24 17:57:59 +00001173 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
Chris Lattner571e4342006-10-27 21:36:01 +00001174
1175 // If this is a series of conditions that are or'd or and'd together, emit
1176 // this as a sequence of branches instead of setcc's with and/or operations.
1177 // For example, instead of something like:
1178 // cmp A, B
1179 // C = seteq
1180 // cmp D, E
1181 // F = setle
1182 // or C, F
1183 // jnz foo
1184 // Emit:
1185 // cmp A, B
1186 // je foo
1187 // cmp D, E
1188 // jle foo
1189 //
1190 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1191 if (BOp->hasOneUse() &&
Chris Lattnerd2f9ee92006-10-27 21:54:23 +00001192 (BOp->getOpcode() == Instruction::And ||
Chris Lattner571e4342006-10-27 21:36:01 +00001193 BOp->getOpcode() == Instruction::Or)) {
1194 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
Chris Lattner0ccb5002006-10-31 23:06:00 +00001195 // If the compares in later blocks need to use values not currently
1196 // exported from this block, export them now. This block should always
1197 // be the first entry.
1198 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1199
Chris Lattnerdf19f272006-10-31 22:37:42 +00001200 // Allow some cases to be rejected.
1201 if (ShouldEmitAsBranches(SwitchCases)) {
Chris Lattnerdf19f272006-10-31 22:37:42 +00001202 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1203 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1204 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1205 }
1206
1207 // Emit the branch for this block.
1208 visitSwitchCase(SwitchCases[0]);
1209 SwitchCases.erase(SwitchCases.begin());
1210 return;
Chris Lattner5a145f02006-10-29 18:23:37 +00001211 }
1212
Chris Lattner0ccb5002006-10-31 23:06:00 +00001213 // Okay, we decided not to do this, remove any inserted MBB's and clear
1214 // SwitchCases.
1215 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1216 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1217
Chris Lattnerdf19f272006-10-31 22:37:42 +00001218 SwitchCases.clear();
Chris Lattner571e4342006-10-27 21:36:01 +00001219 }
1220 }
Chris Lattner24525952006-10-24 18:07:37 +00001221
1222 // Create a CaseBlock record representing this branch.
Zhou Sheng6b6b6ef2007-01-11 12:24:14 +00001223 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001224 NULL, Succ0MBB, Succ1MBB, CurMBB);
Chris Lattner24525952006-10-24 18:07:37 +00001225 // Use visitSwitchCase to actually insert the fast branch sequence for this
1226 // cond branch.
1227 visitSwitchCase(CB);
Chris Lattner1c08c712005-01-07 07:47:53 +00001228}
1229
Nate Begemanf15485a2006-03-27 01:32:24 +00001230/// visitSwitchCase - Emits the necessary code to represent a single node in
1231/// the binary search tree resulting from lowering a switch instruction.
1232void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
Chris Lattner57ab6592006-10-24 17:57:59 +00001233 SDOperand Cond;
1234 SDOperand CondLHS = getValue(CB.CmpLHS);
1235
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001236 // Build the setcc now.
1237 if (CB.CmpMHS == NULL) {
1238 // Fold "(X == true)" to X and "(X == false)" to !X to
1239 // handle common cases produced by branch lowering.
1240 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1241 Cond = CondLHS;
1242 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1243 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1244 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1245 } else
1246 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1247 } else {
1248 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001249
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001250 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1251 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1252
1253 SDOperand CmpOp = getValue(CB.CmpMHS);
1254 MVT::ValueType VT = CmpOp.getValueType();
1255
1256 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1257 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1258 } else {
1259 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1260 Cond = DAG.getSetCC(MVT::i1, SUB,
1261 DAG.getConstant(High-Low, VT), ISD::SETULE);
1262 }
1263
1264 }
1265
Nate Begemanf15485a2006-03-27 01:32:24 +00001266 // Set NextBlock to be the MBB immediately after the current one, if any.
1267 // This is used to avoid emitting unnecessary branches to the next block.
1268 MachineBasicBlock *NextBlock = 0;
1269 MachineFunction::iterator BBI = CurMBB;
1270 if (++BBI != CurMBB->getParent()->end())
1271 NextBlock = BBI;
1272
1273 // If the lhs block is the next block, invert the condition so that we can
1274 // fall through to the lhs instead of the rhs block.
Chris Lattner57ab6592006-10-24 17:57:59 +00001275 if (CB.TrueBB == NextBlock) {
1276 std::swap(CB.TrueBB, CB.FalseBB);
Nate Begemanf15485a2006-03-27 01:32:24 +00001277 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1278 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1279 }
1280 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
Chris Lattner57ab6592006-10-24 17:57:59 +00001281 DAG.getBasicBlock(CB.TrueBB));
1282 if (CB.FalseBB == NextBlock)
Nate Begemanf15485a2006-03-27 01:32:24 +00001283 DAG.setRoot(BrCond);
1284 else
1285 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
Chris Lattner57ab6592006-10-24 17:57:59 +00001286 DAG.getBasicBlock(CB.FalseBB)));
Nate Begemanf15485a2006-03-27 01:32:24 +00001287 // Update successor info
Chris Lattner57ab6592006-10-24 17:57:59 +00001288 CurMBB->addSuccessor(CB.TrueBB);
1289 CurMBB->addSuccessor(CB.FalseBB);
Nate Begemanf15485a2006-03-27 01:32:24 +00001290}
1291
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001292/// visitJumpTable - Emit JumpTable node in the current MBB
Nate Begeman37efe672006-04-22 18:53:45 +00001293void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
Nate Begeman37efe672006-04-22 18:53:45 +00001294 // Emit the code for the jump table
Scott Michelf147a8d2007-04-24 01:24:20 +00001295 assert(JT.Reg != -1U && "Should lower JT Header first!");
Nate Begeman37efe672006-04-22 18:53:45 +00001296 MVT::ValueType PTy = TLI.getPointerTy();
Evan Cheng3d4ce112006-10-30 08:00:44 +00001297 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1298 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1299 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1300 Table, Index));
1301 return;
Nate Begeman37efe672006-04-22 18:53:45 +00001302}
1303
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001304/// visitJumpTableHeader - This function emits necessary code to produce index
1305/// in the JumpTable from switch case.
1306void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1307 SelectionDAGISel::JumpTableHeader &JTH) {
1308 // Subtract the lowest switch case value from the value being switched on
1309 // and conditional branch to default mbb if the result is greater than the
1310 // difference between smallest and largest cases.
1311 SDOperand SwitchOp = getValue(JTH.SValue);
1312 MVT::ValueType VT = SwitchOp.getValueType();
1313 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1314 DAG.getConstant(JTH.First, VT));
1315
1316 // The SDNode we just created, which holds the value being switched on
1317 // minus the the smallest case value, needs to be copied to a virtual
1318 // register so it can be used as an index into the jump table in a
1319 // subsequent basic block. This value may be smaller or larger than the
1320 // target's pointer type, and therefore require extension or truncating.
Dan Gohman7f321562007-06-25 16:23:39 +00001321 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001322 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1323 else
1324 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1325
1326 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1327 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1328 JT.Reg = JumpTableReg;
1329
1330 // Emit the range check for the jump table, and branch to the default
1331 // block for the switch statement if the value being switched on exceeds
1332 // the largest case in the switch.
1333 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1334 DAG.getConstant(JTH.Last-JTH.First,VT),
1335 ISD::SETUGT);
1336
1337 // Set NextBlock to be the MBB immediately after the current one, if any.
1338 // This is used to avoid emitting unnecessary branches to the next block.
1339 MachineBasicBlock *NextBlock = 0;
1340 MachineFunction::iterator BBI = CurMBB;
1341 if (++BBI != CurMBB->getParent()->end())
1342 NextBlock = BBI;
1343
1344 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1345 DAG.getBasicBlock(JT.Default));
1346
1347 if (JT.MBB == NextBlock)
1348 DAG.setRoot(BrCond);
1349 else
1350 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001351 DAG.getBasicBlock(JT.MBB)));
1352
1353 return;
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001354}
1355
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001356/// visitBitTestHeader - This function emits necessary code to produce value
1357/// suitable for "bit tests"
1358void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1359 // Subtract the minimum value
1360 SDOperand SwitchOp = getValue(B.SValue);
1361 MVT::ValueType VT = SwitchOp.getValueType();
1362 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1363 DAG.getConstant(B.First, VT));
1364
1365 // Check range
1366 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1367 DAG.getConstant(B.Range, VT),
1368 ISD::SETUGT);
1369
1370 SDOperand ShiftOp;
Dan Gohman7f321562007-06-25 16:23:39 +00001371 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001372 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1373 else
1374 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1375
1376 // Make desired shift
1377 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1378 DAG.getConstant(1, TLI.getPointerTy()),
1379 ShiftOp);
1380
1381 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1382 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1383 B.Reg = SwitchReg;
1384
1385 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1386 DAG.getBasicBlock(B.Default));
1387
1388 // Set NextBlock to be the MBB immediately after the current one, if any.
1389 // This is used to avoid emitting unnecessary branches to the next block.
1390 MachineBasicBlock *NextBlock = 0;
1391 MachineFunction::iterator BBI = CurMBB;
1392 if (++BBI != CurMBB->getParent()->end())
1393 NextBlock = BBI;
1394
1395 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1396 if (MBB == NextBlock)
1397 DAG.setRoot(BrRange);
1398 else
1399 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1400 DAG.getBasicBlock(MBB)));
1401
1402 CurMBB->addSuccessor(B.Default);
1403 CurMBB->addSuccessor(MBB);
1404
1405 return;
1406}
1407
1408/// visitBitTestCase - this function produces one "bit test"
1409void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1410 unsigned Reg,
1411 SelectionDAGISel::BitTestCase &B) {
1412 // Emit bit tests and jumps
1413 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1414
1415 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1416 SwitchVal,
1417 DAG.getConstant(B.Mask,
1418 TLI.getPointerTy()));
1419 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1420 DAG.getConstant(0, TLI.getPointerTy()),
1421 ISD::SETNE);
1422 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1423 AndCmp, DAG.getBasicBlock(B.TargetBB));
1424
1425 // Set NextBlock to be the MBB immediately after the current one, if any.
1426 // This is used to avoid emitting unnecessary branches to the next block.
1427 MachineBasicBlock *NextBlock = 0;
1428 MachineFunction::iterator BBI = CurMBB;
1429 if (++BBI != CurMBB->getParent()->end())
1430 NextBlock = BBI;
1431
1432 if (NextMBB == NextBlock)
1433 DAG.setRoot(BrAnd);
1434 else
1435 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1436 DAG.getBasicBlock(NextMBB)));
1437
1438 CurMBB->addSuccessor(B.TargetBB);
1439 CurMBB->addSuccessor(NextMBB);
1440
1441 return;
1442}
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001443
Jim Laskeyb180aa12007-02-21 22:53:45 +00001444void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1445 // Retrieve successors.
1446 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00001447 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
Duncan Sands9fac0b52007-06-06 10:05:18 +00001448
Duncan Sandsfd7b3262007-12-17 18:08:19 +00001449 if (isa<InlineAsm>(I.getCalledValue()))
1450 visitInlineAsm(&I);
1451 else
Duncan Sands6f74b482007-12-19 09:48:52 +00001452 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
Duncan Sands9fac0b52007-06-06 10:05:18 +00001453
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00001454 // If the value of the invoke is used outside of its defining block, make it
1455 // available as a virtual register.
1456 if (!I.use_empty()) {
1457 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1458 if (VMI != FuncInfo.ValueMap.end())
1459 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
Jim Laskey183f47f2007-02-25 21:43:59 +00001460 }
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00001461
1462 // Drop into normal successor.
1463 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1464 DAG.getBasicBlock(Return)));
1465
1466 // Update successor info
1467 CurMBB->addSuccessor(Return);
1468 CurMBB->addSuccessor(LandingPad);
Jim Laskeyb180aa12007-02-21 22:53:45 +00001469}
1470
1471void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1472}
1473
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001474/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001475/// small case ranges).
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001476bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001477 CaseRecVector& WorkList,
1478 Value* SV,
1479 MachineBasicBlock* Default) {
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001480 Case& BackCase = *(CR.Range.second-1);
1481
1482 // Size is the number of Cases represented by this range.
1483 unsigned Size = CR.Range.second - CR.Range.first;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001484 if (Size > 3)
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001485 return false;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001486
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001487 // Get the MachineFunction which holds the current MBB. This is used when
1488 // inserting any additional MBBs necessary to represent the switch.
1489 MachineFunction *CurMF = CurMBB->getParent();
1490
1491 // Figure out which block is immediately after the current one.
1492 MachineBasicBlock *NextBlock = 0;
1493 MachineFunction::iterator BBI = CR.CaseBB;
1494
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001495 if (++BBI != CurMBB->getParent()->end())
1496 NextBlock = BBI;
1497
1498 // TODO: If any two of the cases has the same destination, and if one value
1499 // is the same as the other, but has one bit unset that the other has set,
1500 // use bit manipulation to do two compares at once. For example:
1501 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1502
1503 // Rearrange the case blocks so that the last one falls through if possible.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001504 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001505 // The last case block won't fall through into 'NextBlock' if we emit the
1506 // branches in this order. See if rearranging a case value would help.
1507 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001508 if (I->BB == NextBlock) {
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001509 std::swap(*I, BackCase);
1510 break;
1511 }
1512 }
1513 }
1514
1515 // Create a CaseBlock record representing a conditional branch to
1516 // the Case's target mbb if the value being switched on SV is equal
1517 // to C.
1518 MachineBasicBlock *CurBlock = CR.CaseBB;
1519 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1520 MachineBasicBlock *FallThrough;
1521 if (I != E-1) {
1522 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1523 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1524 } else {
1525 // If the last case doesn't match, go to the default block.
1526 FallThrough = Default;
1527 }
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001528
1529 Value *RHS, *LHS, *MHS;
1530 ISD::CondCode CC;
1531 if (I->High == I->Low) {
1532 // This is just small small case range :) containing exactly 1 case
1533 CC = ISD::SETEQ;
1534 LHS = SV; RHS = I->High; MHS = NULL;
1535 } else {
1536 CC = ISD::SETLE;
1537 LHS = I->Low; MHS = SV; RHS = I->High;
1538 }
1539 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1540 I->BB, FallThrough, CurBlock);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001541
1542 // If emitting the first comparison, just call visitSwitchCase to emit the
1543 // code into the current block. Otherwise, push the CaseBlock onto the
1544 // vector to be later processed by SDISel, and insert the node's MBB
1545 // before the next MBB.
1546 if (CurBlock == CurMBB)
1547 visitSwitchCase(CB);
1548 else
1549 SwitchCases.push_back(CB);
1550
1551 CurBlock = FallThrough;
1552 }
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001553
1554 return true;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001555}
1556
Anton Korobeynikov7294b582007-05-09 20:07:08 +00001557static inline bool areJTsAllowed(const TargetLowering &TLI) {
1558 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1559 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1560}
1561
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001562/// handleJTSwitchCase - Emit jumptable for current switch case range
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001563bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001564 CaseRecVector& WorkList,
1565 Value* SV,
1566 MachineBasicBlock* Default) {
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001567 Case& FrontCase = *CR.Range.first;
1568 Case& BackCase = *(CR.Range.second-1);
1569
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001570 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1571 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1572
1573 uint64_t TSize = 0;
1574 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1575 I!=E; ++I)
1576 TSize += I->size();
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001577
Anton Korobeynikov7294b582007-05-09 20:07:08 +00001578 if (!areJTsAllowed(TLI) || TSize <= 3)
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001579 return false;
1580
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001581 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1582 if (Density < 0.4)
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001583 return false;
1584
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001585 DOUT << "Lowering jump table\n"
1586 << "First entry: " << First << ". Last entry: " << Last << "\n"
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001587 << "Size: " << TSize << ". Density: " << Density << "\n\n";
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001588
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001589 // Get the MachineFunction which holds the current MBB. This is used when
1590 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001591 MachineFunction *CurMF = CurMBB->getParent();
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001592
1593 // Figure out which block is immediately after the current one.
1594 MachineBasicBlock *NextBlock = 0;
1595 MachineFunction::iterator BBI = CR.CaseBB;
1596
1597 if (++BBI != CurMBB->getParent()->end())
1598 NextBlock = BBI;
1599
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001600 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1601
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001602 // Create a new basic block to hold the code for loading the address
1603 // of the jump table, and jumping to it. Update successor information;
1604 // we will either branch to the default case for the switch, or the jump
1605 // table.
1606 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1607 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1608 CR.CaseBB->addSuccessor(Default);
1609 CR.CaseBB->addSuccessor(JumpTableBB);
1610
1611 // Build a vector of destination BBs, corresponding to each target
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001612 // of the jump table. If the value of the jump table slot corresponds to
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001613 // a case statement, push the case's BB onto the vector, otherwise, push
1614 // the default BB.
1615 std::vector<MachineBasicBlock*> DestBBs;
1616 int64_t TEI = First;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001617 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1618 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1619 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1620
1621 if ((Low <= TEI) && (TEI <= High)) {
1622 DestBBs.push_back(I->BB);
1623 if (TEI==High)
1624 ++I;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001625 } else {
1626 DestBBs.push_back(Default);
1627 }
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001628 }
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001629
1630 // Update successor info. Add one edge to each unique successor.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001631 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001632 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1633 E = DestBBs.end(); I != E; ++I) {
1634 if (!SuccsHandled[(*I)->getNumber()]) {
1635 SuccsHandled[(*I)->getNumber()] = true;
1636 JumpTableBB->addSuccessor(*I);
1637 }
1638 }
1639
1640 // Create a jump table index for this jump table, or return an existing
1641 // one.
1642 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1643
1644 // Set the jump table information so that we can codegen it as a second
1645 // MachineBasicBlock
Scott Michelf147a8d2007-04-24 01:24:20 +00001646 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001647 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1648 (CR.CaseBB == CurMBB));
1649 if (CR.CaseBB == CurMBB)
1650 visitJumpTableHeader(JT, JTH);
1651
1652 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001653
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001654 return true;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001655}
1656
1657/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1658/// 2 subtrees.
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001659bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001660 CaseRecVector& WorkList,
1661 Value* SV,
1662 MachineBasicBlock* Default) {
1663 // Get the MachineFunction which holds the current MBB. This is used when
1664 // inserting any additional MBBs necessary to represent the switch.
1665 MachineFunction *CurMF = CurMBB->getParent();
1666
1667 // Figure out which block is immediately after the current one.
1668 MachineBasicBlock *NextBlock = 0;
1669 MachineFunction::iterator BBI = CR.CaseBB;
1670
1671 if (++BBI != CurMBB->getParent()->end())
1672 NextBlock = BBI;
1673
1674 Case& FrontCase = *CR.Range.first;
1675 Case& BackCase = *(CR.Range.second-1);
1676 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1677
1678 // Size is the number of Cases represented by this range.
1679 unsigned Size = CR.Range.second - CR.Range.first;
1680
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001681 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1682 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001683 double FMetric = 0;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001684 CaseItr Pivot = CR.Range.first + Size/2;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001685
1686 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1687 // (heuristically) allow us to emit JumpTable's later.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001688 uint64_t TSize = 0;
1689 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1690 I!=E; ++I)
1691 TSize += I->size();
1692
1693 uint64_t LSize = FrontCase.size();
1694 uint64_t RSize = TSize-LSize;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001695 DOUT << "Selecting best pivot: \n"
1696 << "First: " << First << ", Last: " << Last <<"\n"
1697 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001698 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001699 J!=E; ++I, ++J) {
1700 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1701 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001702 assert((RBegin-LEnd>=1) && "Invalid case distance");
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001703 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1704 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
Anton Korobeynikov54e2b142007-04-09 21:57:03 +00001705 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001706 // Should always split in some non-trivial place
1707 DOUT <<"=>Step\n"
1708 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1709 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1710 << "Metric: " << Metric << "\n";
1711 if (FMetric < Metric) {
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001712 Pivot = J;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001713 FMetric = Metric;
1714 DOUT << "Current metric set to: " << FMetric << "\n";
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001715 }
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001716
1717 LSize += J->size();
1718 RSize -= J->size();
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001719 }
Anton Korobeynikov7294b582007-05-09 20:07:08 +00001720 if (areJTsAllowed(TLI)) {
1721 // If our case is dense we *really* should handle it earlier!
1722 assert((FMetric > 0) && "Should handle dense range earlier!");
1723 } else {
1724 Pivot = CR.Range.first + Size/2;
1725 }
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001726
1727 CaseRange LHSR(CR.Range.first, Pivot);
1728 CaseRange RHSR(Pivot, CR.Range.second);
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001729 Constant *C = Pivot->Low;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001730 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1731
1732 // We know that we branch to the LHS if the Value being switched on is
1733 // less than the Pivot value, C. We use this to optimize our binary
1734 // tree a bit, by recognizing that if SV is greater than or equal to the
1735 // LHS's Case Value, and that Case Value is exactly one less than the
1736 // Pivot's Value, then we can branch directly to the LHS's Target,
1737 // rather than creating a leaf node for it.
1738 if ((LHSR.second - LHSR.first) == 1 &&
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001739 LHSR.first->High == CR.GE &&
1740 cast<ConstantInt>(C)->getSExtValue() ==
1741 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1742 TrueBB = LHSR.first->BB;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001743 } else {
1744 TrueBB = new MachineBasicBlock(LLVMBB);
1745 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1746 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1747 }
1748
1749 // Similar to the optimization above, if the Value being switched on is
1750 // known to be less than the Constant CR.LT, and the current Case Value
1751 // is CR.LT - 1, then we can branch directly to the target block for
1752 // the current Case Value, rather than emitting a RHS leaf node for it.
1753 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001754 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1755 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1756 FalseBB = RHSR.first->BB;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001757 } else {
1758 FalseBB = new MachineBasicBlock(LLVMBB);
1759 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1760 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1761 }
1762
1763 // Create a CaseBlock record representing a conditional branch to
1764 // the LHS node if the value being switched on SV is less than C.
1765 // Otherwise, branch to LHS.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001766 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1767 TrueBB, FalseBB, CR.CaseBB);
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001768
1769 if (CR.CaseBB == CurMBB)
1770 visitSwitchCase(CB);
1771 else
1772 SwitchCases.push_back(CB);
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001773
1774 return true;
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001775}
1776
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001777/// handleBitTestsSwitchCase - if current case range has few destination and
1778/// range span less, than machine word bitwidth, encode case range into series
1779/// of masks and emit bit tests with these masks.
1780bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1781 CaseRecVector& WorkList,
1782 Value* SV,
Chris Lattner3ff98172007-04-14 02:26:56 +00001783 MachineBasicBlock* Default){
Dan Gohmanb55757e2007-05-18 17:52:13 +00001784 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001785
1786 Case& FrontCase = *CR.Range.first;
1787 Case& BackCase = *(CR.Range.second-1);
1788
1789 // Get the MachineFunction which holds the current MBB. This is used when
1790 // inserting any additional MBBs necessary to represent the switch.
1791 MachineFunction *CurMF = CurMBB->getParent();
1792
1793 unsigned numCmps = 0;
1794 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1795 I!=E; ++I) {
1796 // Single case counts one, case range - two.
1797 if (I->Low == I->High)
1798 numCmps +=1;
1799 else
1800 numCmps +=2;
1801 }
1802
1803 // Count unique destinations
1804 SmallSet<MachineBasicBlock*, 4> Dests;
1805 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1806 Dests.insert(I->BB);
1807 if (Dests.size() > 3)
1808 // Don't bother the code below, if there are too much unique destinations
1809 return false;
1810 }
1811 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1812 << "Total number of comparisons: " << numCmps << "\n";
1813
1814 // Compute span of values.
1815 Constant* minValue = FrontCase.Low;
1816 Constant* maxValue = BackCase.High;
1817 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1818 cast<ConstantInt>(minValue)->getSExtValue();
1819 DOUT << "Compare range: " << range << "\n"
1820 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1821 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1822
Anton Korobeynikovab8fd402007-04-26 20:44:04 +00001823 if (range>=IntPtrBits ||
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001824 (!(Dests.size() == 1 && numCmps >= 3) &&
1825 !(Dests.size() == 2 && numCmps >= 5) &&
1826 !(Dests.size() >= 3 && numCmps >= 6)))
1827 return false;
1828
1829 DOUT << "Emitting bit tests\n";
1830 int64_t lowBound = 0;
1831
1832 // Optimize the case where all the case values fit in a
1833 // word without having to subtract minValue. In this case,
1834 // we can optimize away the subtraction.
1835 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
Anton Korobeynikove01017b2007-04-14 13:25:55 +00001836 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001837 range = cast<ConstantInt>(maxValue)->getSExtValue();
1838 } else {
1839 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1840 }
1841
1842 CaseBitsVector CasesBits;
1843 unsigned i, count = 0;
1844
1845 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1846 MachineBasicBlock* Dest = I->BB;
1847 for (i = 0; i < count; ++i)
1848 if (Dest == CasesBits[i].BB)
1849 break;
1850
1851 if (i == count) {
1852 assert((count < 3) && "Too much destinations to test!");
1853 CasesBits.push_back(CaseBits(0, Dest, 0));
1854 count++;
1855 }
1856
1857 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1858 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1859
1860 for (uint64_t j = lo; j <= hi; j++) {
Anton Korobeynikove01017b2007-04-14 13:25:55 +00001861 CasesBits[i].Mask |= 1ULL << j;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001862 CasesBits[i].Bits++;
1863 }
1864
1865 }
1866 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1867
1868 SelectionDAGISel::BitTestInfo BTC;
1869
1870 // Figure out which block is immediately after the current one.
1871 MachineFunction::iterator BBI = CR.CaseBB;
1872 ++BBI;
1873
1874 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1875
1876 DOUT << "Cases:\n";
1877 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1878 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1879 << ", BB: " << CasesBits[i].BB << "\n";
1880
1881 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1882 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1883 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1884 CaseBB,
1885 CasesBits[i].BB));
1886 }
1887
1888 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
Jeff Cohenefc36622007-04-09 14:32:59 +00001889 -1U, (CR.CaseBB == CurMBB),
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001890 CR.CaseBB, Default, BTC);
1891
1892 if (CR.CaseBB == CurMBB)
1893 visitBitTestHeader(BTB);
1894
1895 BitTestCases.push_back(BTB);
1896
1897 return true;
1898}
1899
1900
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001901// Clusterify - Transform simple list of Cases into list of CaseRange's
1902unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1903 const SwitchInst& SI) {
1904 unsigned numCmps = 0;
1905
1906 // Start with "simple" cases
1907 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1908 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1909 Cases.push_back(Case(SI.getSuccessorValue(i),
1910 SI.getSuccessorValue(i),
1911 SMBB));
1912 }
Chris Lattnerb3d9cdb2007-11-27 06:14:32 +00001913 std::sort(Cases.begin(), Cases.end(), CaseCmp());
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001914
1915 // Merge case into clusters
1916 if (Cases.size()>=2)
David Greenea2a48852007-06-29 03:42:23 +00001917 // Must recompute end() each iteration because it may be
1918 // invalidated by erase if we hold on to it
Chris Lattner27a6c732007-11-24 07:07:01 +00001919 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001920 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1921 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1922 MachineBasicBlock* nextBB = J->BB;
1923 MachineBasicBlock* currentBB = I->BB;
1924
1925 // If the two neighboring cases go to the same destination, merge them
1926 // into a single case.
1927 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1928 I->High = J->High;
1929 J = Cases.erase(J);
1930 } else {
1931 I = J++;
1932 }
1933 }
1934
1935 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1936 if (I->Low != I->High)
1937 // A range counts double, since it requires two compares.
1938 ++numCmps;
1939 }
1940
1941 return numCmps;
1942}
1943
1944void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
Nate Begemanf15485a2006-03-27 01:32:24 +00001945 // Figure out which block is immediately after the current one.
1946 MachineBasicBlock *NextBlock = 0;
1947 MachineFunction::iterator BBI = CurMBB;
Bill Wendlingc70ddad2006-10-19 21:46:38 +00001948
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001949 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
Chris Lattnerd2c1d222006-10-22 21:36:53 +00001950
Nate Begemanf15485a2006-03-27 01:32:24 +00001951 // If there is only the default destination, branch to it if it is not the
1952 // next basic block. Otherwise, just fall through.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001953 if (SI.getNumOperands() == 2) {
Nate Begemanf15485a2006-03-27 01:32:24 +00001954 // Update machine-CFG edges.
Bill Wendlingc70ddad2006-10-19 21:46:38 +00001955
Nate Begemanf15485a2006-03-27 01:32:24 +00001956 // If this is not a fall-through branch, emit the branch.
Chris Lattnerd2c1d222006-10-22 21:36:53 +00001957 if (Default != NextBlock)
Nate Begemanf15485a2006-03-27 01:32:24 +00001958 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
Chris Lattnerd2c1d222006-10-22 21:36:53 +00001959 DAG.getBasicBlock(Default)));
Bill Wendlingc70ddad2006-10-19 21:46:38 +00001960
Chris Lattnerd2c1d222006-10-22 21:36:53 +00001961 CurMBB->addSuccessor(Default);
Nate Begemanf15485a2006-03-27 01:32:24 +00001962 return;
1963 }
1964
1965 // If there are any non-default case statements, create a vector of Cases
1966 // representing each one, and sort the vector so that we can efficiently
1967 // create a binary search tree from them.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001968 CaseVector Cases;
1969 unsigned numCmps = Clusterify(Cases, SI);
1970 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1971 << ". Total compares: " << numCmps << "\n";
Bill Wendlingc70ddad2006-10-19 21:46:38 +00001972
Nate Begemanf15485a2006-03-27 01:32:24 +00001973 // Get the Value to be switched on and default basic blocks, which will be
1974 // inserted into CaseBlock records, representing basic blocks in the binary
1975 // search tree.
Anton Korobeynikov5502bf62007-04-04 21:14:49 +00001976 Value *SV = SI.getOperand(0);
Nate Begeman37efe672006-04-22 18:53:45 +00001977
Nate Begemanf15485a2006-03-27 01:32:24 +00001978 // Push the initial CaseRec onto the worklist
Anton Korobeynikovb17b08d2007-03-27 11:29:11 +00001979 CaseRecVector WorkList;
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001980 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1981
1982 while (!WorkList.empty()) {
Nate Begemanf15485a2006-03-27 01:32:24 +00001983 // Grab a record representing a case range to process off the worklist
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001984 CaseRec CR = WorkList.back();
1985 WorkList.pop_back();
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001986
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001987 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1988 continue;
1989
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001990 // If the range has few cases (two or less) emit a series of specific
1991 // tests.
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001992 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1993 continue;
1994
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001995 // If the switch has more than 5 blocks, and at least 40% dense, and the
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001996 // target supports indirect branches, then emit a jump table rather than
1997 // lowering the switch to a binary tree of conditional branches.
Anton Korobeynikovdd433212007-03-27 12:05:48 +00001998 if (handleJTSwitchCase(CR, WorkList, SV, Default))
1999 continue;
2000
2001 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2002 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2003 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
Nate Begemanf15485a2006-03-27 01:32:24 +00002004 }
2005}
2006
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00002007
Chris Lattnerb9fccc42005-04-02 05:04:50 +00002008void SelectionDAGLowering::visitSub(User &I) {
2009 // -0.0 - X --> fneg
Reid Spencer24d6da52007-01-21 00:29:26 +00002010 const Type *Ty = I.getType();
Reid Spencer9d6565a2007-02-15 02:26:10 +00002011 if (isa<VectorType>(Ty)) {
Dan Gohman7f321562007-06-25 16:23:39 +00002012 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2013 const VectorType *DestTy = cast<VectorType>(I.getType());
2014 const Type *ElTy = DestTy->getElementType();
Evan Chengc45453f2007-06-29 21:44:35 +00002015 if (ElTy->isFloatingPoint()) {
2016 unsigned VL = DestTy->getNumElements();
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00002017 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
Evan Chengc45453f2007-06-29 21:44:35 +00002018 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2019 if (CV == CNZ) {
2020 SDOperand Op2 = getValue(I.getOperand(1));
2021 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2022 return;
2023 }
Dan Gohman7f321562007-06-25 16:23:39 +00002024 }
2025 }
2026 }
2027 if (Ty->isFloatingPoint()) {
Chris Lattner01b3d732005-09-28 22:28:18 +00002028 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
Dale Johannesen9e3d3ab2007-09-14 22:26:36 +00002029 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
Chris Lattner01b3d732005-09-28 22:28:18 +00002030 SDOperand Op2 = getValue(I.getOperand(1));
2031 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2032 return;
2033 }
Dan Gohman7f321562007-06-25 16:23:39 +00002034 }
2035
2036 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
Chris Lattnerb9fccc42005-04-02 05:04:50 +00002037}
2038
Dan Gohman7f321562007-06-25 16:23:39 +00002039void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
Chris Lattner1c08c712005-01-07 07:47:53 +00002040 SDOperand Op1 = getValue(I.getOperand(0));
2041 SDOperand Op2 = getValue(I.getOperand(1));
Reid Spencer24d6da52007-01-21 00:29:26 +00002042
2043 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
Reid Spencer1628cec2006-10-26 06:15:43 +00002044}
2045
Nate Begemane21ea612005-11-18 07:42:56 +00002046void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2047 SDOperand Op1 = getValue(I.getOperand(0));
2048 SDOperand Op2 = getValue(I.getOperand(1));
2049
Dan Gohman7f321562007-06-25 16:23:39 +00002050 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2051 MVT::getSizeInBits(Op2.getValueType()))
Reid Spencer832254e2007-02-02 02:16:23 +00002052 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2053 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2054 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
Nate Begemane21ea612005-11-18 07:42:56 +00002055
Chris Lattner1c08c712005-01-07 07:47:53 +00002056 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2057}
2058
Reid Spencer45fb3f32006-11-20 01:22:35 +00002059void SelectionDAGLowering::visitICmp(User &I) {
Reid Spencere4d87aa2006-12-23 06:05:41 +00002060 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2061 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2062 predicate = IC->getPredicate();
2063 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2064 predicate = ICmpInst::Predicate(IC->getPredicate());
2065 SDOperand Op1 = getValue(I.getOperand(0));
2066 SDOperand Op2 = getValue(I.getOperand(1));
Reid Spencer45fb3f32006-11-20 01:22:35 +00002067 ISD::CondCode Opcode;
Reid Spencere4d87aa2006-12-23 06:05:41 +00002068 switch (predicate) {
Reid Spencer45fb3f32006-11-20 01:22:35 +00002069 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2070 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2071 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2072 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2073 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2074 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2075 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2076 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2077 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2078 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2079 default:
2080 assert(!"Invalid ICmp predicate value");
2081 Opcode = ISD::SETEQ;
2082 break;
2083 }
2084 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2085}
2086
2087void SelectionDAGLowering::visitFCmp(User &I) {
Reid Spencere4d87aa2006-12-23 06:05:41 +00002088 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2089 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2090 predicate = FC->getPredicate();
2091 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2092 predicate = FCmpInst::Predicate(FC->getPredicate());
Chris Lattner1c08c712005-01-07 07:47:53 +00002093 SDOperand Op1 = getValue(I.getOperand(0));
2094 SDOperand Op2 = getValue(I.getOperand(1));
Reid Spencere4d87aa2006-12-23 06:05:41 +00002095 ISD::CondCode Condition, FOC, FPC;
2096 switch (predicate) {
2097 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2098 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2099 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2100 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2101 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2102 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2103 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2104 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2105 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2106 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2107 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2108 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2109 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2110 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2111 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2112 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2113 default:
2114 assert(!"Invalid FCmp predicate value");
2115 FOC = FPC = ISD::SETFALSE;
2116 break;
2117 }
2118 if (FiniteOnlyFPMath())
2119 Condition = FOC;
2120 else
2121 Condition = FPC;
2122 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
Chris Lattner1c08c712005-01-07 07:47:53 +00002123}
2124
2125void SelectionDAGLowering::visitSelect(User &I) {
2126 SDOperand Cond = getValue(I.getOperand(0));
2127 SDOperand TrueVal = getValue(I.getOperand(1));
2128 SDOperand FalseVal = getValue(I.getOperand(2));
Dan Gohman7f321562007-06-25 16:23:39 +00002129 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2130 TrueVal, FalseVal));
Chris Lattner1c08c712005-01-07 07:47:53 +00002131}
2132
Reid Spencer3da59db2006-11-27 01:05:10 +00002133
2134void SelectionDAGLowering::visitTrunc(User &I) {
2135 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2136 SDOperand N = getValue(I.getOperand(0));
2137 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2138 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2139}
2140
2141void SelectionDAGLowering::visitZExt(User &I) {
2142 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2143 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2144 SDOperand N = getValue(I.getOperand(0));
2145 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2146 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2147}
2148
2149void SelectionDAGLowering::visitSExt(User &I) {
2150 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2151 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2152 SDOperand N = getValue(I.getOperand(0));
2153 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2154 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2155}
2156
2157void SelectionDAGLowering::visitFPTrunc(User &I) {
2158 // FPTrunc is never a no-op cast, no need to check
2159 SDOperand N = getValue(I.getOperand(0));
2160 MVT::ValueType DestVT = TLI.getValueType(I.getType());
Chris Lattner0bd48932008-01-17 07:00:52 +00002161 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
Reid Spencer3da59db2006-11-27 01:05:10 +00002162}
2163
2164void SelectionDAGLowering::visitFPExt(User &I){
2165 // FPTrunc is never a no-op cast, no need to check
2166 SDOperand N = getValue(I.getOperand(0));
2167 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2168 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2169}
2170
2171void SelectionDAGLowering::visitFPToUI(User &I) {
2172 // FPToUI is never a no-op cast, no need to check
2173 SDOperand N = getValue(I.getOperand(0));
2174 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2175 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2176}
2177
2178void SelectionDAGLowering::visitFPToSI(User &I) {
2179 // FPToSI is never a no-op cast, no need to check
2180 SDOperand N = getValue(I.getOperand(0));
2181 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2182 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2183}
2184
2185void SelectionDAGLowering::visitUIToFP(User &I) {
2186 // UIToFP is never a no-op cast, no need to check
2187 SDOperand N = getValue(I.getOperand(0));
2188 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2189 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2190}
2191
2192void SelectionDAGLowering::visitSIToFP(User &I){
2193 // UIToFP is never a no-op cast, no need to check
2194 SDOperand N = getValue(I.getOperand(0));
2195 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2196 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2197}
2198
2199void SelectionDAGLowering::visitPtrToInt(User &I) {
2200 // What to do depends on the size of the integer and the size of the pointer.
2201 // We can either truncate, zero extend, or no-op, accordingly.
Chris Lattner1c08c712005-01-07 07:47:53 +00002202 SDOperand N = getValue(I.getOperand(0));
Chris Lattnere25ca692006-03-22 20:09:35 +00002203 MVT::ValueType SrcVT = N.getValueType();
Chris Lattner28b5b1c2006-03-15 22:19:46 +00002204 MVT::ValueType DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002205 SDOperand Result;
2206 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2207 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2208 else
2209 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2210 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2211 setValue(&I, Result);
2212}
Chris Lattner1c08c712005-01-07 07:47:53 +00002213
Reid Spencer3da59db2006-11-27 01:05:10 +00002214void SelectionDAGLowering::visitIntToPtr(User &I) {
2215 // What to do depends on the size of the integer and the size of the pointer.
2216 // We can either truncate, zero extend, or no-op, accordingly.
2217 SDOperand N = getValue(I.getOperand(0));
2218 MVT::ValueType SrcVT = N.getValueType();
2219 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2220 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2221 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2222 else
2223 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2224 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2225}
2226
2227void SelectionDAGLowering::visitBitCast(User &I) {
2228 SDOperand N = getValue(I.getOperand(0));
2229 MVT::ValueType DestVT = TLI.getValueType(I.getType());
Reid Spencer3da59db2006-11-27 01:05:10 +00002230
2231 // BitCast assures us that source and destination are the same size so this
2232 // is either a BIT_CONVERT or a no-op.
2233 if (DestVT != N.getValueType())
2234 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2235 else
2236 setValue(&I, N); // noop cast.
Chris Lattner1c08c712005-01-07 07:47:53 +00002237}
2238
Chris Lattner2bbd8102006-03-29 00:11:43 +00002239void SelectionDAGLowering::visitInsertElement(User &I) {
Chris Lattnerc7029802006-03-18 01:44:44 +00002240 SDOperand InVec = getValue(I.getOperand(0));
2241 SDOperand InVal = getValue(I.getOperand(1));
2242 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2243 getValue(I.getOperand(2)));
2244
Dan Gohman7f321562007-06-25 16:23:39 +00002245 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2246 TLI.getValueType(I.getType()),
2247 InVec, InVal, InIdx));
Chris Lattnerc7029802006-03-18 01:44:44 +00002248}
2249
Chris Lattner2bbd8102006-03-29 00:11:43 +00002250void SelectionDAGLowering::visitExtractElement(User &I) {
Chris Lattner384504c2006-03-21 20:44:12 +00002251 SDOperand InVec = getValue(I.getOperand(0));
2252 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2253 getValue(I.getOperand(1)));
Dan Gohman7f321562007-06-25 16:23:39 +00002254 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
Chris Lattner384504c2006-03-21 20:44:12 +00002255 TLI.getValueType(I.getType()), InVec, InIdx));
2256}
Chris Lattnerc7029802006-03-18 01:44:44 +00002257
Chris Lattner3e104b12006-04-08 04:15:24 +00002258void SelectionDAGLowering::visitShuffleVector(User &I) {
2259 SDOperand V1 = getValue(I.getOperand(0));
2260 SDOperand V2 = getValue(I.getOperand(1));
2261 SDOperand Mask = getValue(I.getOperand(2));
2262
Dan Gohman7f321562007-06-25 16:23:39 +00002263 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2264 TLI.getValueType(I.getType()),
2265 V1, V2, Mask));
Chris Lattner3e104b12006-04-08 04:15:24 +00002266}
2267
2268
Chris Lattner1c08c712005-01-07 07:47:53 +00002269void SelectionDAGLowering::visitGetElementPtr(User &I) {
2270 SDOperand N = getValue(I.getOperand(0));
2271 const Type *Ty = I.getOperand(0)->getType();
Chris Lattner1c08c712005-01-07 07:47:53 +00002272
2273 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2274 OI != E; ++OI) {
2275 Value *Idx = *OI;
Chris Lattnerc88d8e92005-12-05 07:10:48 +00002276 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
Reid Spencerb83eb642006-10-20 07:07:24 +00002277 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
Chris Lattner1c08c712005-01-07 07:47:53 +00002278 if (Field) {
2279 // N = N + Offset
Chris Lattnerb1919e22007-02-10 19:55:17 +00002280 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
Chris Lattner1c08c712005-01-07 07:47:53 +00002281 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
Chris Lattner0bd48932008-01-17 07:00:52 +00002282 DAG.getIntPtrConstant(Offset));
Chris Lattner1c08c712005-01-07 07:47:53 +00002283 }
2284 Ty = StTy->getElementType(Field);
2285 } else {
2286 Ty = cast<SequentialType>(Ty)->getElementType();
Chris Lattner7cc47772005-01-07 21:56:57 +00002287
Chris Lattner7c0104b2005-11-09 04:45:33 +00002288 // If this is a constant subscript, handle it quickly.
2289 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
Reid Spencerb83eb642006-10-20 07:07:24 +00002290 if (CI->getZExtValue() == 0) continue;
Reid Spencer47857812006-12-31 05:55:36 +00002291 uint64_t Offs =
Dale Johannesena7ac2bd2007-10-01 23:08:35 +00002292 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
Chris Lattner0bd48932008-01-17 07:00:52 +00002293 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2294 DAG.getIntPtrConstant(Offs));
Chris Lattner7c0104b2005-11-09 04:45:33 +00002295 continue;
Chris Lattner1c08c712005-01-07 07:47:53 +00002296 }
Chris Lattner7c0104b2005-11-09 04:45:33 +00002297
2298 // N = N + Idx * ElementSize;
Dale Johannesena7ac2bd2007-10-01 23:08:35 +00002299 uint64_t ElementSize = TD->getABITypeSize(Ty);
Chris Lattner7c0104b2005-11-09 04:45:33 +00002300 SDOperand IdxN = getValue(Idx);
2301
2302 // If the index is smaller or larger than intptr_t, truncate or extend
2303 // it.
2304 if (IdxN.getValueType() < N.getValueType()) {
Reid Spencer47857812006-12-31 05:55:36 +00002305 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
Chris Lattner7c0104b2005-11-09 04:45:33 +00002306 } else if (IdxN.getValueType() > N.getValueType())
2307 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2308
2309 // If this is a multiply by a power of two, turn it into a shl
2310 // immediately. This is a very common case.
2311 if (isPowerOf2_64(ElementSize)) {
2312 unsigned Amt = Log2_64(ElementSize);
2313 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
Chris Lattner6b2d6962005-11-09 16:50:40 +00002314 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
Chris Lattner7c0104b2005-11-09 04:45:33 +00002315 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2316 continue;
2317 }
2318
Chris Lattner0bd48932008-01-17 07:00:52 +00002319 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
Chris Lattner7c0104b2005-11-09 04:45:33 +00002320 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2321 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
Chris Lattner1c08c712005-01-07 07:47:53 +00002322 }
2323 }
2324 setValue(&I, N);
2325}
2326
2327void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2328 // If this is a fixed sized alloca in the entry block of the function,
2329 // allocate it statically on the stack.
2330 if (FuncInfo.StaticAllocaMap.count(&I))
2331 return; // getValue will auto-populate this.
2332
2333 const Type *Ty = I.getAllocatedType();
Duncan Sands514ab342007-11-01 20:53:16 +00002334 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Chris Lattner58092e32007-01-20 22:35:55 +00002335 unsigned Align =
Chris Lattnerd2b7cec2007-02-14 05:52:17 +00002336 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
Chris Lattner58092e32007-01-20 22:35:55 +00002337 I.getAlignment());
Chris Lattner1c08c712005-01-07 07:47:53 +00002338
2339 SDOperand AllocSize = getValue(I.getArraySize());
Chris Lattner68cd65e2005-01-22 23:04:37 +00002340 MVT::ValueType IntPtr = TLI.getPointerTy();
2341 if (IntPtr < AllocSize.getValueType())
2342 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2343 else if (IntPtr > AllocSize.getValueType())
2344 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
Chris Lattner1c08c712005-01-07 07:47:53 +00002345
Chris Lattner68cd65e2005-01-22 23:04:37 +00002346 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
Chris Lattner0bd48932008-01-17 07:00:52 +00002347 DAG.getIntPtrConstant(TySize));
Chris Lattner1c08c712005-01-07 07:47:53 +00002348
Evan Cheng45157792007-08-16 23:46:29 +00002349 // Handle alignment. If the requested alignment is less than or equal to
2350 // the stack alignment, ignore it. If the size is greater than or equal to
2351 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
Chris Lattner1c08c712005-01-07 07:47:53 +00002352 unsigned StackAlign =
2353 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
Evan Cheng45157792007-08-16 23:46:29 +00002354 if (Align <= StackAlign)
Chris Lattner1c08c712005-01-07 07:47:53 +00002355 Align = 0;
Evan Cheng45157792007-08-16 23:46:29 +00002356
2357 // Round the size of the allocation up to the stack alignment size
2358 // by add SA-1 to the size.
2359 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
Chris Lattner0bd48932008-01-17 07:00:52 +00002360 DAG.getIntPtrConstant(StackAlign-1));
Evan Cheng45157792007-08-16 23:46:29 +00002361 // Mask out the low bits for alignment purposes.
2362 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
Chris Lattner0bd48932008-01-17 07:00:52 +00002363 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
Chris Lattner1c08c712005-01-07 07:47:53 +00002364
Chris Lattner0bd48932008-01-17 07:00:52 +00002365 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002366 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2367 MVT::Other);
2368 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
Chris Lattner0da331f2007-02-04 01:31:47 +00002369 setValue(&I, DSA);
2370 DAG.setRoot(DSA.getValue(1));
Chris Lattner1c08c712005-01-07 07:47:53 +00002371
2372 // Inform the Frame Information that we have just allocated a variable-sized
2373 // object.
2374 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2375}
2376
Chris Lattner1c08c712005-01-07 07:47:53 +00002377void SelectionDAGLowering::visitLoad(LoadInst &I) {
2378 SDOperand Ptr = getValue(I.getOperand(0));
Misha Brukmanedf128a2005-04-21 22:36:52 +00002379
Chris Lattnerd3948112005-01-17 22:19:26 +00002380 SDOperand Root;
2381 if (I.isVolatile())
2382 Root = getRoot();
2383 else {
2384 // Do not serialize non-volatile loads against each other.
2385 Root = DAG.getRoot();
2386 }
Chris Lattner28b5b1c2006-03-15 22:19:46 +00002387
Evan Cheng466685d2006-10-09 20:57:25 +00002388 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
Christopher Lamb95c218a2007-04-22 23:15:30 +00002389 Root, I.isVolatile(), I.getAlignment()));
Chris Lattner28b5b1c2006-03-15 22:19:46 +00002390}
2391
2392SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
Evan Cheng466685d2006-10-09 20:57:25 +00002393 const Value *SV, SDOperand Root,
Christopher Lamb95c218a2007-04-22 23:15:30 +00002394 bool isVolatile,
2395 unsigned Alignment) {
Dan Gohman7f321562007-06-25 16:23:39 +00002396 SDOperand L =
2397 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2398 isVolatile, Alignment);
Chris Lattnerd3948112005-01-17 22:19:26 +00002399
Chris Lattner28b5b1c2006-03-15 22:19:46 +00002400 if (isVolatile)
Chris Lattnerd3948112005-01-17 22:19:26 +00002401 DAG.setRoot(L.getValue(1));
2402 else
2403 PendingLoads.push_back(L.getValue(1));
Chris Lattner28b5b1c2006-03-15 22:19:46 +00002404
2405 return L;
Chris Lattner1c08c712005-01-07 07:47:53 +00002406}
2407
2408
2409void SelectionDAGLowering::visitStore(StoreInst &I) {
2410 Value *SrcV = I.getOperand(0);
2411 SDOperand Src = getValue(SrcV);
2412 SDOperand Ptr = getValue(I.getOperand(1));
Evan Cheng0b4f80e2006-12-20 01:27:29 +00002413 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
Christopher Lamb95c218a2007-04-22 23:15:30 +00002414 I.isVolatile(), I.getAlignment()));
Chris Lattner1c08c712005-01-07 07:47:53 +00002415}
2416
Chris Lattner0eade312006-03-24 02:22:33 +00002417/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2418/// node.
2419void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2420 unsigned Intrinsic) {
Duncan Sandsa3355ff2007-12-03 20:06:50 +00002421 bool HasChain = !I.doesNotAccessMemory();
2422 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2423
Chris Lattner0eade312006-03-24 02:22:33 +00002424 // Build the operand list.
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002425 SmallVector<SDOperand, 8> Ops;
Chris Lattnere58a7802006-04-02 03:41:14 +00002426 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2427 if (OnlyLoad) {
2428 // We don't need to serialize loads against other loads.
2429 Ops.push_back(DAG.getRoot());
2430 } else {
2431 Ops.push_back(getRoot());
2432 }
2433 }
Chris Lattner0eade312006-03-24 02:22:33 +00002434
2435 // Add the intrinsic ID as an integer operand.
2436 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2437
2438 // Add all operands of the call to the operand list.
2439 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2440 SDOperand Op = getValue(I.getOperand(i));
Chris Lattner0eade312006-03-24 02:22:33 +00002441 assert(TLI.isTypeLegal(Op.getValueType()) &&
2442 "Intrinsic uses a non-legal type?");
2443 Ops.push_back(Op);
2444 }
2445
2446 std::vector<MVT::ValueType> VTs;
2447 if (I.getType() != Type::VoidTy) {
2448 MVT::ValueType VT = TLI.getValueType(I.getType());
Dan Gohman7f321562007-06-25 16:23:39 +00002449 if (MVT::isVector(VT)) {
Reid Spencer9d6565a2007-02-15 02:26:10 +00002450 const VectorType *DestTy = cast<VectorType>(I.getType());
Chris Lattner0eade312006-03-24 02:22:33 +00002451 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2452
2453 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2454 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2455 }
2456
2457 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2458 VTs.push_back(VT);
2459 }
2460 if (HasChain)
2461 VTs.push_back(MVT::Other);
2462
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002463 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2464
Chris Lattner0eade312006-03-24 02:22:33 +00002465 // Create the node.
Chris Lattner48b61a72006-03-28 00:40:33 +00002466 SDOperand Result;
2467 if (!HasChain)
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002468 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2469 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00002470 else if (I.getType() != Type::VoidTy)
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002471 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2472 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00002473 else
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002474 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2475 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00002476
Chris Lattnere58a7802006-04-02 03:41:14 +00002477 if (HasChain) {
2478 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2479 if (OnlyLoad)
2480 PendingLoads.push_back(Chain);
2481 else
2482 DAG.setRoot(Chain);
2483 }
Chris Lattner0eade312006-03-24 02:22:33 +00002484 if (I.getType() != Type::VoidTy) {
Reid Spencer9d6565a2007-02-15 02:26:10 +00002485 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
Dan Gohman7f321562007-06-25 16:23:39 +00002486 MVT::ValueType VT = TLI.getValueType(PTy);
2487 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
Chris Lattner0eade312006-03-24 02:22:33 +00002488 }
2489 setValue(&I, Result);
2490 }
2491}
2492
Duncan Sandsb4fd45e2007-07-06 09:10:03 +00002493/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002494static GlobalVariable *ExtractTypeInfo (Value *V) {
Duncan Sandsb4fd45e2007-07-06 09:10:03 +00002495 V = IntrinsicInst::StripPointerCasts(V);
2496 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002497 assert (GV || isa<ConstantPointerNull>(V) &&
2498 "TypeInfo must be a global variable or NULL");
2499 return GV;
2500}
2501
Duncan Sandsf4070822007-06-15 19:04:19 +00002502/// addCatchInfo - Extract the personality and type infos from an eh.selector
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002503/// call, and add them to the specified machine basic block.
Duncan Sandsf4070822007-06-15 19:04:19 +00002504static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2505 MachineBasicBlock *MBB) {
2506 // Inform the MachineModuleInfo of the personality for this landing pad.
2507 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2508 assert(CE->getOpcode() == Instruction::BitCast &&
2509 isa<Function>(CE->getOperand(0)) &&
2510 "Personality should be a function");
2511 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2512
2513 // Gather all the type infos for this landing pad and pass them along to
2514 // MachineModuleInfo.
2515 std::vector<GlobalVariable *> TyInfo;
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002516 unsigned N = I.getNumOperands();
2517
2518 for (unsigned i = N - 1; i > 2; --i) {
2519 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2520 unsigned FilterLength = CI->getZExtValue();
Duncan Sands6590b042007-08-27 15:47:50 +00002521 unsigned FirstCatch = i + FilterLength + !FilterLength;
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002522 assert (FirstCatch <= N && "Invalid filter length");
2523
2524 if (FirstCatch < N) {
2525 TyInfo.reserve(N - FirstCatch);
2526 for (unsigned j = FirstCatch; j < N; ++j)
2527 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2528 MMI->addCatchTypeInfo(MBB, TyInfo);
2529 TyInfo.clear();
2530 }
2531
Duncan Sands6590b042007-08-27 15:47:50 +00002532 if (!FilterLength) {
2533 // Cleanup.
2534 MMI->addCleanup(MBB);
2535 } else {
2536 // Filter.
2537 TyInfo.reserve(FilterLength - 1);
2538 for (unsigned j = i + 1; j < FirstCatch; ++j)
2539 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2540 MMI->addFilterTypeInfo(MBB, TyInfo);
2541 TyInfo.clear();
2542 }
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002543
2544 N = i;
2545 }
Duncan Sandsf4070822007-06-15 19:04:19 +00002546 }
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002547
2548 if (N > 3) {
2549 TyInfo.reserve(N - 3);
2550 for (unsigned j = 3; j < N; ++j)
2551 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
Duncan Sandsf4070822007-06-15 19:04:19 +00002552 MMI->addCatchTypeInfo(MBB, TyInfo);
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002553 }
Duncan Sandsf4070822007-06-15 19:04:19 +00002554}
2555
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002556/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2557/// we want to emit this as a call to a named external function, return the name
2558/// otherwise lower it and return null.
2559const char *
2560SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2561 switch (Intrinsic) {
Chris Lattner0eade312006-03-24 02:22:33 +00002562 default:
2563 // By default, turn this into a target intrinsic node.
2564 visitTargetIntrinsic(I, Intrinsic);
2565 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002566 case Intrinsic::vastart: visitVAStart(I); return 0;
2567 case Intrinsic::vaend: visitVAEnd(I); return 0;
2568 case Intrinsic::vacopy: visitVACopy(I); return 0;
Nate Begemanbcc5f362007-01-29 22:58:52 +00002569 case Intrinsic::returnaddress:
2570 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2571 getValue(I.getOperand(1))));
2572 return 0;
2573 case Intrinsic::frameaddress:
2574 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2575 getValue(I.getOperand(1))));
2576 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002577 case Intrinsic::setjmp:
Anton Korobeynikovd27a2582006-12-10 23:12:42 +00002578 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002579 break;
2580 case Intrinsic::longjmp:
Anton Korobeynikovd27a2582006-12-10 23:12:42 +00002581 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002582 break;
Chris Lattner03dd4652006-03-03 00:00:25 +00002583 case Intrinsic::memcpy_i32:
2584 case Intrinsic::memcpy_i64:
2585 visitMemIntrinsic(I, ISD::MEMCPY);
2586 return 0;
2587 case Intrinsic::memset_i32:
2588 case Intrinsic::memset_i64:
2589 visitMemIntrinsic(I, ISD::MEMSET);
2590 return 0;
2591 case Intrinsic::memmove_i32:
2592 case Intrinsic::memmove_i64:
2593 visitMemIntrinsic(I, ISD::MEMMOVE);
2594 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002595
Chris Lattner86cb6432005-12-13 17:40:33 +00002596 case Intrinsic::dbg_stoppoint: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002597 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00002598 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002599 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002600 SDOperand Ops[5];
Chris Lattner36ce6912005-11-29 06:21:05 +00002601
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002602 Ops[0] = getRoot();
2603 Ops[1] = getValue(SPI.getLineValue());
2604 Ops[2] = getValue(SPI.getColumnValue());
Chris Lattner36ce6912005-11-29 06:21:05 +00002605
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002606 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
Jim Laskeyce72b172006-02-11 01:01:30 +00002607 assert(DD && "Not a debug information descriptor");
Jim Laskey43970fe2006-03-23 18:06:46 +00002608 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2609
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002610 Ops[3] = DAG.getString(CompileUnit->getFileName());
2611 Ops[4] = DAG.getString(CompileUnit->getDirectory());
Jim Laskeyce72b172006-02-11 01:01:30 +00002612
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002613 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
Chris Lattner86cb6432005-12-13 17:40:33 +00002614 }
Jim Laskey43970fe2006-03-23 18:06:46 +00002615
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00002616 return 0;
Chris Lattner36ce6912005-11-29 06:21:05 +00002617 }
Jim Laskey43970fe2006-03-23 18:06:46 +00002618 case Intrinsic::dbg_region_start: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002619 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00002620 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002621 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2622 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
Jim Laskey1ee29252007-01-26 14:34:52 +00002623 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
Evan Chengbb81d972008-01-31 09:59:15 +00002624 DAG.getConstant(LabelID, MVT::i32),
2625 DAG.getConstant(0, MVT::i32)));
Jim Laskey43970fe2006-03-23 18:06:46 +00002626 }
2627
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00002628 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00002629 }
2630 case Intrinsic::dbg_region_end: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002631 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00002632 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002633 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2634 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
Evan Chengbb81d972008-01-31 09:59:15 +00002635 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2636 DAG.getConstant(LabelID, MVT::i32),
2637 DAG.getConstant(0, MVT::i32)));
Jim Laskey43970fe2006-03-23 18:06:46 +00002638 }
2639
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00002640 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00002641 }
2642 case Intrinsic::dbg_func_start: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002643 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00002644 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002645 if (MMI && FSI.getSubprogram() &&
2646 MMI->Verify(FSI.getSubprogram())) {
2647 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
Evan Chengbb81d972008-01-31 09:59:15 +00002648 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2649 DAG.getConstant(LabelID, MVT::i32),
2650 DAG.getConstant(0, MVT::i32)));
Jim Laskey43970fe2006-03-23 18:06:46 +00002651 }
2652
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00002653 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00002654 }
2655 case Intrinsic::dbg_declare: {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002656 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00002657 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002658 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
Jim Laskey0892cee2006-03-24 09:50:27 +00002659 SDOperand AddressOp = getValue(DI.getAddress());
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002660 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
Jim Laskey44c3b9f2007-01-26 21:22:28 +00002661 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
Jim Laskey43970fe2006-03-23 18:06:46 +00002662 }
2663
2664 return 0;
2665 }
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002666
Jim Laskeyb180aa12007-02-21 22:53:45 +00002667 case Intrinsic::eh_exception: {
Evan Chenge47c3332007-06-27 18:45:32 +00002668 if (ExceptionHandling) {
Duncan Sands90291952007-07-06 09:18:59 +00002669 if (!CurMBB->isLandingPad()) {
2670 // FIXME: Mark exception register as live in. Hack for PR1508.
2671 unsigned Reg = TLI.getExceptionAddressRegister();
2672 if (Reg) CurMBB->addLiveIn(Reg);
2673 }
Jim Laskey735b6f82007-02-22 15:38:06 +00002674 // Insert the EXCEPTIONADDR instruction.
2675 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2676 SDOperand Ops[1];
2677 Ops[0] = DAG.getRoot();
2678 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2679 setValue(&I, Op);
2680 DAG.setRoot(Op.getValue(1));
Jim Laskey7a1de982007-02-24 09:45:44 +00002681 } else {
Jim Laskey64ce0ca2007-02-28 18:37:04 +00002682 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
Jim Laskey735b6f82007-02-22 15:38:06 +00002683 }
Jim Laskeyb180aa12007-02-21 22:53:45 +00002684 return 0;
2685 }
2686
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00002687 case Intrinsic::eh_selector_i32:
2688 case Intrinsic::eh_selector_i64: {
Jim Laskeyb180aa12007-02-21 22:53:45 +00002689 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00002690 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2691 MVT::i32 : MVT::i64);
2692
Duncan Sandsf4070822007-06-15 19:04:19 +00002693 if (ExceptionHandling && MMI) {
2694 if (CurMBB->isLandingPad())
2695 addCatchInfo(I, MMI, CurMBB);
Evan Chenge47c3332007-06-27 18:45:32 +00002696 else {
Duncan Sandsf4070822007-06-15 19:04:19 +00002697#ifndef NDEBUG
Duncan Sandsf4070822007-06-15 19:04:19 +00002698 FuncInfo.CatchInfoLost.insert(&I);
2699#endif
Duncan Sands90291952007-07-06 09:18:59 +00002700 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2701 unsigned Reg = TLI.getExceptionSelectorRegister();
2702 if (Reg) CurMBB->addLiveIn(Reg);
Evan Chenge47c3332007-06-27 18:45:32 +00002703 }
Jim Laskey735b6f82007-02-22 15:38:06 +00002704
2705 // Insert the EHSELECTION instruction.
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00002706 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
Jim Laskey735b6f82007-02-22 15:38:06 +00002707 SDOperand Ops[2];
2708 Ops[0] = getValue(I.getOperand(1));
2709 Ops[1] = getRoot();
2710 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2711 setValue(&I, Op);
2712 DAG.setRoot(Op.getValue(1));
Jim Laskey7a1de982007-02-24 09:45:44 +00002713 } else {
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00002714 setValue(&I, DAG.getConstant(0, VT));
Jim Laskey735b6f82007-02-22 15:38:06 +00002715 }
Jim Laskeyb180aa12007-02-21 22:53:45 +00002716
2717 return 0;
2718 }
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00002719
2720 case Intrinsic::eh_typeid_for_i32:
2721 case Intrinsic::eh_typeid_for_i64: {
Jim Laskeyb180aa12007-02-21 22:53:45 +00002722 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00002723 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2724 MVT::i32 : MVT::i64);
Jim Laskeyb180aa12007-02-21 22:53:45 +00002725
Jim Laskey735b6f82007-02-22 15:38:06 +00002726 if (MMI) {
2727 // Find the type id for the given typeinfo.
Duncan Sandscf26d7c2007-07-04 20:52:51 +00002728 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
Duncan Sands3b346362007-05-04 17:12:26 +00002729
Jim Laskey735b6f82007-02-22 15:38:06 +00002730 unsigned TypeID = MMI->getTypeIDFor(GV);
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00002731 setValue(&I, DAG.getConstant(TypeID, VT));
Jim Laskey7a1de982007-02-24 09:45:44 +00002732 } else {
Duncan Sandsf664e412007-07-06 14:46:23 +00002733 // Return something different to eh_selector.
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00002734 setValue(&I, DAG.getConstant(1, VT));
Jim Laskey735b6f82007-02-22 15:38:06 +00002735 }
Jim Laskeyb180aa12007-02-21 22:53:45 +00002736
2737 return 0;
2738 }
2739
Anton Korobeynikov2365f512007-07-14 14:06:15 +00002740 case Intrinsic::eh_return: {
2741 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2742
2743 if (MMI && ExceptionHandling) {
2744 MMI->setCallsEHReturn(true);
2745 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2746 MVT::Other,
2747 getRoot(),
2748 getValue(I.getOperand(1)),
2749 getValue(I.getOperand(2))));
2750 } else {
2751 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2752 }
2753
2754 return 0;
2755 }
2756
2757 case Intrinsic::eh_unwind_init: {
2758 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2759 MMI->setCallsUnwindInit(true);
2760 }
2761
2762 return 0;
2763 }
2764
2765 case Intrinsic::eh_dwarf_cfa: {
2766 if (ExceptionHandling) {
2767 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
Anton Korobeynikov2f597bd2007-08-23 07:21:06 +00002768 SDOperand CfaArg;
2769 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2770 CfaArg = DAG.getNode(ISD::TRUNCATE,
2771 TLI.getPointerTy(), getValue(I.getOperand(1)));
2772 else
2773 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2774 TLI.getPointerTy(), getValue(I.getOperand(1)));
2775
Anton Korobeynikov2365f512007-07-14 14:06:15 +00002776 SDOperand Offset = DAG.getNode(ISD::ADD,
2777 TLI.getPointerTy(),
2778 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
Anton Korobeynikov2f597bd2007-08-23 07:21:06 +00002779 TLI.getPointerTy()),
2780 CfaArg);
Anton Korobeynikov2365f512007-07-14 14:06:15 +00002781 setValue(&I, DAG.getNode(ISD::ADD,
2782 TLI.getPointerTy(),
2783 DAG.getNode(ISD::FRAMEADDR,
2784 TLI.getPointerTy(),
2785 DAG.getConstant(0,
2786 TLI.getPointerTy())),
2787 Offset));
2788 } else {
2789 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2790 }
2791
2792 return 0;
2793 }
2794
Dale Johannesen9ab7fb32007-10-02 17:43:59 +00002795 case Intrinsic::sqrt:
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002796 setValue(&I, DAG.getNode(ISD::FSQRT,
2797 getValue(I.getOperand(1)).getValueType(),
2798 getValue(I.getOperand(1))));
2799 return 0;
Dale Johannesen9ab7fb32007-10-02 17:43:59 +00002800 case Intrinsic::powi:
Chris Lattner6ddf8ed2006-09-09 06:03:30 +00002801 setValue(&I, DAG.getNode(ISD::FPOWI,
2802 getValue(I.getOperand(1)).getValueType(),
2803 getValue(I.getOperand(1)),
2804 getValue(I.getOperand(2))));
2805 return 0;
Dan Gohmanac9385a2007-10-12 00:01:22 +00002806 case Intrinsic::sin:
2807 setValue(&I, DAG.getNode(ISD::FSIN,
2808 getValue(I.getOperand(1)).getValueType(),
2809 getValue(I.getOperand(1))));
2810 return 0;
2811 case Intrinsic::cos:
2812 setValue(&I, DAG.getNode(ISD::FCOS,
2813 getValue(I.getOperand(1)).getValueType(),
2814 getValue(I.getOperand(1))));
2815 return 0;
2816 case Intrinsic::pow:
2817 setValue(&I, DAG.getNode(ISD::FPOW,
2818 getValue(I.getOperand(1)).getValueType(),
2819 getValue(I.getOperand(1)),
2820 getValue(I.getOperand(2))));
2821 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002822 case Intrinsic::pcmarker: {
2823 SDOperand Tmp = getValue(I.getOperand(1));
2824 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2825 return 0;
2826 }
Andrew Lenharth8b91c772005-11-11 22:48:54 +00002827 case Intrinsic::readcyclecounter: {
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002828 SDOperand Op = getRoot();
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002829 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2830 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2831 &Op, 1);
Andrew Lenharth8b91c772005-11-11 22:48:54 +00002832 setValue(&I, Tmp);
2833 DAG.setRoot(Tmp.getValue(1));
Andrew Lenharth51b8d542005-11-11 16:47:30 +00002834 return 0;
Andrew Lenharth8b91c772005-11-11 22:48:54 +00002835 }
Chris Lattnerc6eb6d72007-04-10 03:20:39 +00002836 case Intrinsic::part_select: {
Reid Spencer3f108cb2007-04-05 01:20:18 +00002837 // Currently not implemented: just abort
Reid Spencerf75b8742007-04-12 02:48:46 +00002838 assert(0 && "part_select intrinsic not implemented");
2839 abort();
2840 }
2841 case Intrinsic::part_set: {
2842 // Currently not implemented: just abort
2843 assert(0 && "part_set intrinsic not implemented");
Reid Spencer3f108cb2007-04-05 01:20:18 +00002844 abort();
Reid Spenceraddd11d2007-04-04 23:48:25 +00002845 }
Reid Spencera4f9c4d2007-04-01 07:34:11 +00002846 case Intrinsic::bswap:
Nate Begemand88fc032006-01-14 03:14:10 +00002847 setValue(&I, DAG.getNode(ISD::BSWAP,
2848 getValue(I.getOperand(1)).getValueType(),
2849 getValue(I.getOperand(1))));
2850 return 0;
Reid Spencera4f9c4d2007-04-01 07:34:11 +00002851 case Intrinsic::cttz: {
2852 SDOperand Arg = getValue(I.getOperand(1));
2853 MVT::ValueType Ty = Arg.getValueType();
2854 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
Reid Spencera4f9c4d2007-04-01 07:34:11 +00002855 setValue(&I, result);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002856 return 0;
Reid Spencera4f9c4d2007-04-01 07:34:11 +00002857 }
2858 case Intrinsic::ctlz: {
2859 SDOperand Arg = getValue(I.getOperand(1));
2860 MVT::ValueType Ty = Arg.getValueType();
2861 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
Reid Spencera4f9c4d2007-04-01 07:34:11 +00002862 setValue(&I, result);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002863 return 0;
Reid Spencera4f9c4d2007-04-01 07:34:11 +00002864 }
2865 case Intrinsic::ctpop: {
2866 SDOperand Arg = getValue(I.getOperand(1));
2867 MVT::ValueType Ty = Arg.getValueType();
2868 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
Reid Spencera4f9c4d2007-04-01 07:34:11 +00002869 setValue(&I, result);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002870 return 0;
Reid Spencera4f9c4d2007-04-01 07:34:11 +00002871 }
Chris Lattner140d53c2006-01-13 02:50:02 +00002872 case Intrinsic::stacksave: {
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002873 SDOperand Op = getRoot();
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002874 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2875 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
Chris Lattner140d53c2006-01-13 02:50:02 +00002876 setValue(&I, Tmp);
2877 DAG.setRoot(Tmp.getValue(1));
2878 return 0;
2879 }
Chris Lattner39a17dd2006-01-23 05:22:07 +00002880 case Intrinsic::stackrestore: {
2881 SDOperand Tmp = getValue(I.getOperand(1));
2882 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
Chris Lattner140d53c2006-01-13 02:50:02 +00002883 return 0;
Chris Lattner39a17dd2006-01-23 05:22:07 +00002884 }
Chris Lattnerac22c832005-12-12 22:51:16 +00002885 case Intrinsic::prefetch:
2886 // FIXME: Currently discarding prefetches.
2887 return 0;
Tanya Lattner24e5aad2007-06-15 22:26:58 +00002888
2889 case Intrinsic::var_annotation:
2890 // Discard annotate attributes
2891 return 0;
Duncan Sands36397f52007-07-27 12:58:54 +00002892
Duncan Sands36397f52007-07-27 12:58:54 +00002893 case Intrinsic::init_trampoline: {
2894 const Function *F =
2895 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2896
2897 SDOperand Ops[6];
2898 Ops[0] = getRoot();
2899 Ops[1] = getValue(I.getOperand(1));
2900 Ops[2] = getValue(I.getOperand(2));
2901 Ops[3] = getValue(I.getOperand(3));
2902 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2903 Ops[5] = DAG.getSrcValue(F);
2904
Duncan Sandsf7331b32007-09-11 14:10:23 +00002905 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
2906 DAG.getNodeValueTypes(TLI.getPointerTy(),
2907 MVT::Other), 2,
2908 Ops, 6);
2909
2910 setValue(&I, Tmp);
2911 DAG.setRoot(Tmp.getValue(1));
Duncan Sands36397f52007-07-27 12:58:54 +00002912 return 0;
2913 }
Gordon Henriksence224772008-01-07 01:30:38 +00002914
2915 case Intrinsic::gcroot:
2916 if (GCI) {
2917 Value *Alloca = I.getOperand(1);
2918 Constant *TypeMap = cast<Constant>(I.getOperand(2));
2919
2920 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
2921 GCI->addStackRoot(FI->getIndex(), TypeMap);
2922 }
2923 return 0;
2924
2925 case Intrinsic::gcread:
2926 case Intrinsic::gcwrite:
2927 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
2928 return 0;
2929
Anton Korobeynikov917c2a62007-11-15 23:25:33 +00002930 case Intrinsic::flt_rounds: {
Dan Gohman1a024862008-01-31 00:41:03 +00002931 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
Anton Korobeynikov917c2a62007-11-15 23:25:33 +00002932 return 0;
2933 }
Anton Korobeynikov66fac792008-01-15 07:02:33 +00002934
2935 case Intrinsic::trap: {
2936 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
2937 return 0;
2938 }
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00002939 }
2940}
2941
2942
Duncan Sands6f74b482007-12-19 09:48:52 +00002943void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
Jim Laskey1da20a72007-02-23 21:45:01 +00002944 bool IsTailCall,
Anton Korobeynikov070280e2007-05-23 11:08:31 +00002945 MachineBasicBlock *LandingPad) {
Duncan Sands6f74b482007-12-19 09:48:52 +00002946 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
Jim Laskey735b6f82007-02-22 15:38:06 +00002947 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
Anton Korobeynikov070280e2007-05-23 11:08:31 +00002948 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2949 unsigned BeginLabel = 0, EndLabel = 0;
Duncan Sands6f74b482007-12-19 09:48:52 +00002950
Jim Laskey735b6f82007-02-22 15:38:06 +00002951 TargetLowering::ArgListTy Args;
2952 TargetLowering::ArgListEntry Entry;
Duncan Sands6f74b482007-12-19 09:48:52 +00002953 Args.reserve(CS.arg_size());
2954 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2955 i != e; ++i) {
2956 SDOperand ArgNode = getValue(*i);
2957 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
Duncan Sands4fee7032007-05-07 20:49:28 +00002958
Duncan Sands6f74b482007-12-19 09:48:52 +00002959 unsigned attrInd = i - CS.arg_begin() + 1;
2960 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
2961 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
2962 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
2963 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
2964 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
2965 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
Jim Laskey735b6f82007-02-22 15:38:06 +00002966 Args.push_back(Entry);
2967 }
2968
Duncan Sands481dc722007-12-19 07:36:31 +00002969 bool MarkTryRange = LandingPad ||
2970 // C++ requires special handling of 'nounwind' calls.
Duncan Sands6f74b482007-12-19 09:48:52 +00002971 (CS.doesNotThrow());
Duncan Sands481dc722007-12-19 07:36:31 +00002972
2973 if (MarkTryRange && ExceptionHandling && MMI) {
Anton Korobeynikov070280e2007-05-23 11:08:31 +00002974 // Insert a label before the invoke call to mark the try range. This can be
2975 // used to detect deletion of the invoke via the MachineModuleInfo.
2976 BeginLabel = MMI->NextLabelID();
2977 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
Evan Chengbb81d972008-01-31 09:59:15 +00002978 DAG.getConstant(BeginLabel, MVT::i32),
2979 DAG.getConstant(1, MVT::i32)));
Anton Korobeynikov070280e2007-05-23 11:08:31 +00002980 }
Duncan Sands6f74b482007-12-19 09:48:52 +00002981
Jim Laskey735b6f82007-02-22 15:38:06 +00002982 std::pair<SDOperand,SDOperand> Result =
Duncan Sands6f74b482007-12-19 09:48:52 +00002983 TLI.LowerCallTo(getRoot(), CS.getType(),
2984 CS.paramHasAttr(0, ParamAttr::SExt),
2985 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
Jim Laskey735b6f82007-02-22 15:38:06 +00002986 Callee, Args, DAG);
Duncan Sands6f74b482007-12-19 09:48:52 +00002987 if (CS.getType() != Type::VoidTy)
2988 setValue(CS.getInstruction(), Result.first);
Jim Laskey735b6f82007-02-22 15:38:06 +00002989 DAG.setRoot(Result.second);
Anton Korobeynikov070280e2007-05-23 11:08:31 +00002990
Duncan Sands481dc722007-12-19 07:36:31 +00002991 if (MarkTryRange && ExceptionHandling && MMI) {
Anton Korobeynikov070280e2007-05-23 11:08:31 +00002992 // Insert a label at the end of the invoke call to mark the try range. This
2993 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2994 EndLabel = MMI->NextLabelID();
2995 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
Evan Chengbb81d972008-01-31 09:59:15 +00002996 DAG.getConstant(EndLabel, MVT::i32),
2997 DAG.getConstant(1, MVT::i32)));
Anton Korobeynikov070280e2007-05-23 11:08:31 +00002998
Duncan Sands6f74b482007-12-19 09:48:52 +00002999 // Inform MachineModuleInfo of range.
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003000 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3001 }
Jim Laskey735b6f82007-02-22 15:38:06 +00003002}
3003
3004
Chris Lattner1c08c712005-01-07 07:47:53 +00003005void SelectionDAGLowering::visitCall(CallInst &I) {
Chris Lattner64e14b12005-01-08 22:48:57 +00003006 const char *RenameFn = 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003007 if (Function *F = I.getCalledFunction()) {
Chris Lattner87b51bc2007-09-10 21:15:22 +00003008 if (F->isDeclaration()) {
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003009 if (unsigned IID = F->getIntrinsicID()) {
3010 RenameFn = visitIntrinsicCall(I, IID);
3011 if (!RenameFn)
3012 return;
Chris Lattner87b51bc2007-09-10 21:15:22 +00003013 }
3014 }
3015
3016 // Check for well-known libc/libm calls. If the function is internal, it
3017 // can't be a library call.
3018 unsigned NameLen = F->getNameLen();
3019 if (!F->hasInternalLinkage() && NameLen) {
3020 const char *NameStr = F->getNameStart();
3021 if (NameStr[0] == 'c' &&
3022 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3023 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3024 if (I.getNumOperands() == 3 && // Basic sanity checks.
3025 I.getOperand(1)->getType()->isFloatingPoint() &&
3026 I.getType() == I.getOperand(1)->getType() &&
3027 I.getType() == I.getOperand(2)->getType()) {
3028 SDOperand LHS = getValue(I.getOperand(1));
3029 SDOperand RHS = getValue(I.getOperand(2));
3030 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3031 LHS, RHS));
3032 return;
3033 }
3034 } else if (NameStr[0] == 'f' &&
3035 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
Dale Johannesen2f429012007-09-26 21:10:55 +00003036 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3037 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
Chris Lattner87b51bc2007-09-10 21:15:22 +00003038 if (I.getNumOperands() == 2 && // Basic sanity checks.
3039 I.getOperand(1)->getType()->isFloatingPoint() &&
3040 I.getType() == I.getOperand(1)->getType()) {
3041 SDOperand Tmp = getValue(I.getOperand(1));
3042 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3043 return;
3044 }
3045 } else if (NameStr[0] == 's' &&
3046 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
Dale Johannesen2f429012007-09-26 21:10:55 +00003047 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3048 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
Chris Lattner87b51bc2007-09-10 21:15:22 +00003049 if (I.getNumOperands() == 2 && // Basic sanity checks.
3050 I.getOperand(1)->getType()->isFloatingPoint() &&
3051 I.getType() == I.getOperand(1)->getType()) {
3052 SDOperand Tmp = getValue(I.getOperand(1));
3053 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3054 return;
3055 }
3056 } else if (NameStr[0] == 'c' &&
3057 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
Dale Johannesen2f429012007-09-26 21:10:55 +00003058 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3059 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
Chris Lattner87b51bc2007-09-10 21:15:22 +00003060 if (I.getNumOperands() == 2 && // Basic sanity checks.
3061 I.getOperand(1)->getType()->isFloatingPoint() &&
3062 I.getType() == I.getOperand(1)->getType()) {
3063 SDOperand Tmp = getValue(I.getOperand(1));
3064 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3065 return;
Chris Lattnerf76e7dc2005-04-30 04:43:14 +00003066 }
Chris Lattner1ca85d52005-05-14 13:56:55 +00003067 }
Chris Lattner87b51bc2007-09-10 21:15:22 +00003068 }
Chris Lattnerce7518c2006-01-26 22:24:51 +00003069 } else if (isa<InlineAsm>(I.getOperand(0))) {
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003070 visitInlineAsm(&I);
Chris Lattnerce7518c2006-01-26 22:24:51 +00003071 return;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003072 }
Misha Brukmanedf128a2005-04-21 22:36:52 +00003073
Chris Lattner64e14b12005-01-08 22:48:57 +00003074 SDOperand Callee;
3075 if (!RenameFn)
3076 Callee = getValue(I.getOperand(0));
3077 else
3078 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
Anton Korobeynikov070280e2007-05-23 11:08:31 +00003079
Duncan Sands6f74b482007-12-19 09:48:52 +00003080 LowerCallTo(&I, Callee, I.isTailCall());
Chris Lattner1c08c712005-01-07 07:47:53 +00003081}
3082
Jim Laskey735b6f82007-02-22 15:38:06 +00003083
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003084/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3085/// this value and returns the result as a ValueVT value. This uses
3086/// Chain/Flag as the input and updates them for the output Chain/Flag.
3087/// If the Flag pointer is NULL, no flag is used.
3088SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3089 SDOperand &Chain, SDOperand *Flag)const{
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003090 // Copy the legal parts from the registers.
3091 unsigned NumParts = Regs.size();
3092 SmallVector<SDOperand, 8> Parts(NumParts);
Dan Gohman27a70be2007-07-02 16:18:06 +00003093 for (unsigned i = 0; i != NumParts; ++i) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003094 SDOperand Part = Flag ?
3095 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3096 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3097 Chain = Part.getValue(1);
3098 if (Flag)
3099 *Flag = Part.getValue(2);
3100 Parts[i] = Part;
Chris Lattnercf752aa2006-06-08 18:22:48 +00003101 }
Chris Lattner5df99b32007-03-25 05:00:54 +00003102
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003103 // Assemble the legal parts into the final value.
Dan Gohman532dc2e2007-07-09 20:59:04 +00003104 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
Chris Lattner864635a2006-02-22 22:37:12 +00003105}
3106
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003107/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3108/// specified value into the registers specified by this object. This uses
3109/// Chain/Flag as the input and updates them for the output Chain/Flag.
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003110/// If the Flag pointer is NULL, no flag is used.
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003111void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003112 SDOperand &Chain, SDOperand *Flag) const {
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003113 // Get the list of the values's legal parts.
3114 unsigned NumParts = Regs.size();
3115 SmallVector<SDOperand, 8> Parts(NumParts);
Dan Gohman532dc2e2007-07-09 20:59:04 +00003116 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003117
3118 // Copy the parts into the registers.
Dan Gohman27a70be2007-07-02 16:18:06 +00003119 for (unsigned i = 0; i != NumParts; ++i) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003120 SDOperand Part = Flag ?
Dan Gohman532dc2e2007-07-09 20:59:04 +00003121 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3122 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003123 Chain = Part.getValue(0);
3124 if (Flag)
3125 *Flag = Part.getValue(1);
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003126 }
3127}
Chris Lattner864635a2006-02-22 22:37:12 +00003128
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003129/// AddInlineAsmOperands - Add this value to the specified inlineasm node
3130/// operand list. This adds the code marker and includes the number of
3131/// values added into it.
3132void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
Chris Lattner9f6637d2006-02-23 20:06:57 +00003133 std::vector<SDOperand> &Ops) const {
Chris Lattner4b993b12007-04-09 00:33:58 +00003134 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3135 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003136 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3137 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3138}
Chris Lattner864635a2006-02-22 22:37:12 +00003139
3140/// isAllocatableRegister - If the specified register is safe to allocate,
3141/// i.e. it isn't a stack pointer or some other special register, return the
3142/// register class for the register. Otherwise, return null.
3143static const TargetRegisterClass *
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003144isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3145 const TargetLowering &TLI, const MRegisterInfo *MRI) {
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003146 MVT::ValueType FoundVT = MVT::Other;
3147 const TargetRegisterClass *FoundRC = 0;
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003148 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3149 E = MRI->regclass_end(); RCI != E; ++RCI) {
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003150 MVT::ValueType ThisVT = MVT::Other;
3151
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003152 const TargetRegisterClass *RC = *RCI;
3153 // If none of the the value types for this register class are valid, we
3154 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003155 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3156 I != E; ++I) {
3157 if (TLI.isTypeLegal(*I)) {
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003158 // If we have already found this register in a different register class,
3159 // choose the one with the largest VT specified. For example, on
3160 // PowerPC, we favor f64 register classes over f32.
3161 if (FoundVT == MVT::Other ||
3162 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3163 ThisVT = *I;
3164 break;
3165 }
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003166 }
3167 }
3168
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003169 if (ThisVT == MVT::Other) continue;
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003170
Chris Lattner864635a2006-02-22 22:37:12 +00003171 // NOTE: This isn't ideal. In particular, this might allocate the
3172 // frame pointer in functions that need it (due to them not being taken
3173 // out of allocation, because a variable sized allocation hasn't been seen
3174 // yet). This is a slight code pessimization, but should still work.
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00003175 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3176 E = RC->allocation_order_end(MF); I != E; ++I)
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003177 if (*I == Reg) {
3178 // We found a matching register class. Keep looking at others in case
3179 // we find one with larger registers that this physreg is also in.
3180 FoundRC = RC;
3181 FoundVT = ThisVT;
3182 break;
3183 }
Chris Lattner4e4b5762006-02-01 18:59:47 +00003184 }
Chris Lattnerf8814cf2006-04-02 00:24:45 +00003185 return FoundRC;
Chris Lattner864635a2006-02-22 22:37:12 +00003186}
3187
Chris Lattner4e4b5762006-02-01 18:59:47 +00003188
Chris Lattner0c583402007-04-28 20:49:53 +00003189namespace {
3190/// AsmOperandInfo - This contains information for each constraint that we are
3191/// lowering.
3192struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3193 /// ConstraintCode - This contains the actual string for the code, like "m".
3194 std::string ConstraintCode;
Chris Lattner2a600be2007-04-28 21:01:43 +00003195
3196 /// ConstraintType - Information about the constraint code, e.g. Register,
3197 /// RegisterClass, Memory, Other, Unknown.
3198 TargetLowering::ConstraintType ConstraintType;
Chris Lattner0c583402007-04-28 20:49:53 +00003199
3200 /// CallOperand/CallOperandval - If this is the result output operand or a
3201 /// clobber, this is null, otherwise it is the incoming operand to the
3202 /// CallInst. This gets modified as the asm is processed.
3203 SDOperand CallOperand;
3204 Value *CallOperandVal;
3205
3206 /// ConstraintVT - The ValueType for the operand value.
3207 MVT::ValueType ConstraintVT;
3208
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003209 /// AssignedRegs - If this is a register or register class operand, this
3210 /// contains the set of register corresponding to the operand.
3211 RegsForValue AssignedRegs;
3212
Chris Lattner0c583402007-04-28 20:49:53 +00003213 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
Chris Lattner2a600be2007-04-28 21:01:43 +00003214 : InlineAsm::ConstraintInfo(info),
3215 ConstraintType(TargetLowering::C_Unknown),
Chris Lattner0c583402007-04-28 20:49:53 +00003216 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3217 }
Chris Lattner3ff90dc2007-04-30 17:16:27 +00003218
3219 void ComputeConstraintToUse(const TargetLowering &TLI);
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003220
3221 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3222 /// busy in OutputRegs/InputRegs.
3223 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3224 std::set<unsigned> &OutputRegs,
3225 std::set<unsigned> &InputRegs) const {
3226 if (isOutReg)
3227 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3228 if (isInReg)
3229 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3230 }
Chris Lattner0c583402007-04-28 20:49:53 +00003231};
3232} // end anon namespace.
Chris Lattner864635a2006-02-22 22:37:12 +00003233
Chris Lattner3ff90dc2007-04-30 17:16:27 +00003234/// getConstraintGenerality - Return an integer indicating how general CT is.
3235static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3236 switch (CT) {
3237 default: assert(0 && "Unknown constraint type!");
3238 case TargetLowering::C_Other:
3239 case TargetLowering::C_Unknown:
3240 return 0;
3241 case TargetLowering::C_Register:
3242 return 1;
3243 case TargetLowering::C_RegisterClass:
3244 return 2;
3245 case TargetLowering::C_Memory:
3246 return 3;
3247 }
3248}
3249
3250void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3251 assert(!Codes.empty() && "Must have at least one constraint");
3252
3253 std::string *Current = &Codes[0];
3254 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3255 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3256 ConstraintCode = *Current;
3257 ConstraintType = CurType;
Dale Johannesenba2a0b92008-01-29 02:21:21 +00003258 } else {
3259 unsigned CurGenerality = getConstraintGenerality(CurType);
3260
3261 // If we have multiple constraints, try to pick the most general one ahead
3262 // of time. This isn't a wonderful solution, but handles common cases.
3263 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3264 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3265 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3266 if (ThisGenerality > CurGenerality) {
3267 // This constraint letter is more general than the previous one,
3268 // use it.
3269 CurType = ThisType;
3270 Current = &Codes[j];
3271 CurGenerality = ThisGenerality;
3272 }
3273 }
3274
3275 ConstraintCode = *Current;
3276 ConstraintType = CurType;
Chris Lattner3ff90dc2007-04-30 17:16:27 +00003277 }
Dale Johannesenba2a0b92008-01-29 02:21:21 +00003278
3279 if (ConstraintCode == "X") {
3280 if (isa<BasicBlock>(CallOperandVal) || isa<ConstantInt>(CallOperandVal))
3281 return;
3282 // This matches anything. Labels and constants we handle elsewhere
3283 // ('X' is the only thing that matches labels). Otherwise, try to
3284 // resolve it to something we know about by looking at the actual
3285 // operand type.
3286 std::string s = "";
3287 TLI.lowerXConstraint(ConstraintVT, s);
3288 if (s!="") {
3289 ConstraintCode = s;
3290 ConstraintType = TLI.getConstraintType(ConstraintCode);
Chris Lattner3ff90dc2007-04-30 17:16:27 +00003291 }
3292 }
Chris Lattner3ff90dc2007-04-30 17:16:27 +00003293}
3294
3295
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003296void SelectionDAGLowering::
3297GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
Chris Lattnerbf996f12007-04-30 17:29:31 +00003298 std::set<unsigned> &OutputRegs,
3299 std::set<unsigned> &InputRegs) {
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003300 // Compute whether this value requires an input register, an output register,
3301 // or both.
3302 bool isOutReg = false;
3303 bool isInReg = false;
3304 switch (OpInfo.Type) {
3305 case InlineAsm::isOutput:
3306 isOutReg = true;
3307
3308 // If this is an early-clobber output, or if there is an input
3309 // constraint that matches this, we need to reserve the input register
3310 // so no other inputs allocate to it.
3311 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3312 break;
3313 case InlineAsm::isInput:
3314 isInReg = true;
3315 isOutReg = false;
3316 break;
3317 case InlineAsm::isClobber:
3318 isOutReg = true;
3319 isInReg = true;
3320 break;
3321 }
3322
3323
3324 MachineFunction &MF = DAG.getMachineFunction();
Chris Lattnerbf996f12007-04-30 17:29:31 +00003325 std::vector<unsigned> Regs;
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003326
3327 // If this is a constraint for a single physreg, or a constraint for a
3328 // register class, find it.
3329 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3330 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3331 OpInfo.ConstraintVT);
Chris Lattnerbf996f12007-04-30 17:29:31 +00003332
3333 unsigned NumRegs = 1;
3334 if (OpInfo.ConstraintVT != MVT::Other)
Dan Gohmanb9f10192007-06-21 14:42:22 +00003335 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
Chris Lattnerbf996f12007-04-30 17:29:31 +00003336 MVT::ValueType RegVT;
3337 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3338
Chris Lattnerbf996f12007-04-30 17:29:31 +00003339
3340 // If this is a constraint for a specific physical register, like {r17},
3341 // assign it now.
3342 if (PhysReg.first) {
3343 if (OpInfo.ConstraintVT == MVT::Other)
3344 ValueVT = *PhysReg.second->vt_begin();
3345
3346 // Get the actual register value type. This is important, because the user
3347 // may have asked for (e.g.) the AX register in i32 type. We need to
3348 // remember that AX is actually i16 to get the right extension.
3349 RegVT = *PhysReg.second->vt_begin();
3350
3351 // This is a explicit reference to a physical register.
3352 Regs.push_back(PhysReg.first);
3353
3354 // If this is an expanded reference, add the rest of the regs to Regs.
3355 if (NumRegs != 1) {
3356 TargetRegisterClass::iterator I = PhysReg.second->begin();
3357 TargetRegisterClass::iterator E = PhysReg.second->end();
3358 for (; *I != PhysReg.first; ++I)
3359 assert(I != E && "Didn't find reg!");
3360
3361 // Already added the first reg.
3362 --NumRegs; ++I;
3363 for (; NumRegs; --NumRegs, ++I) {
3364 assert(I != E && "Ran out of registers to allocate!");
3365 Regs.push_back(*I);
3366 }
3367 }
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003368 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3369 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3370 return;
Chris Lattnerbf996f12007-04-30 17:29:31 +00003371 }
3372
3373 // Otherwise, if this was a reference to an LLVM register class, create vregs
3374 // for this reference.
3375 std::vector<unsigned> RegClassRegs;
Chris Lattnerc2c28fc2007-06-15 19:11:01 +00003376 const TargetRegisterClass *RC = PhysReg.second;
3377 if (RC) {
Chris Lattnerbf996f12007-04-30 17:29:31 +00003378 // If this is an early clobber or tied register, our regalloc doesn't know
3379 // how to maintain the constraint. If it isn't, go ahead and create vreg
3380 // and let the regalloc do the right thing.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003381 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3382 // If there is some other early clobber and this is an input register,
3383 // then we are forced to pre-allocate the input reg so it doesn't
3384 // conflict with the earlyclobber.
3385 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
Chris Lattnerbf996f12007-04-30 17:29:31 +00003386 RegVT = *PhysReg.second->vt_begin();
3387
3388 if (OpInfo.ConstraintVT == MVT::Other)
3389 ValueVT = RegVT;
3390
3391 // Create the appropriate number of virtual registers.
Chris Lattner84bc5422007-12-31 04:13:23 +00003392 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Chris Lattnerbf996f12007-04-30 17:29:31 +00003393 for (; NumRegs; --NumRegs)
Chris Lattner84bc5422007-12-31 04:13:23 +00003394 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
Chris Lattnerbf996f12007-04-30 17:29:31 +00003395
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003396 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3397 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3398 return;
Chris Lattnerbf996f12007-04-30 17:29:31 +00003399 }
3400
3401 // Otherwise, we can't allocate it. Let the code below figure out how to
3402 // maintain these constraints.
3403 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3404
3405 } else {
3406 // This is a reference to a register class that doesn't directly correspond
3407 // to an LLVM register class. Allocate NumRegs consecutive, available,
3408 // registers from the class.
3409 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3410 OpInfo.ConstraintVT);
3411 }
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003412
Chris Lattnerbf996f12007-04-30 17:29:31 +00003413 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3414 unsigned NumAllocated = 0;
3415 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3416 unsigned Reg = RegClassRegs[i];
3417 // See if this register is available.
3418 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3419 (isInReg && InputRegs.count(Reg))) { // Already used.
3420 // Make sure we find consecutive registers.
3421 NumAllocated = 0;
3422 continue;
3423 }
3424
3425 // Check to see if this register is allocatable (i.e. don't give out the
3426 // stack pointer).
Chris Lattnerc2c28fc2007-06-15 19:11:01 +00003427 if (RC == 0) {
3428 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3429 if (!RC) { // Couldn't allocate this register.
3430 // Reset NumAllocated to make sure we return consecutive registers.
3431 NumAllocated = 0;
3432 continue;
3433 }
Chris Lattnerbf996f12007-04-30 17:29:31 +00003434 }
3435
3436 // Okay, this register is good, we can use it.
3437 ++NumAllocated;
3438
3439 // If we allocated enough consecutive registers, succeed.
3440 if (NumAllocated == NumRegs) {
3441 unsigned RegStart = (i-NumAllocated)+1;
3442 unsigned RegEnd = i+1;
3443 // Mark all of the allocated registers used.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003444 for (unsigned i = RegStart; i != RegEnd; ++i)
3445 Regs.push_back(RegClassRegs[i]);
Chris Lattnerbf996f12007-04-30 17:29:31 +00003446
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003447 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3448 OpInfo.ConstraintVT);
3449 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3450 return;
Chris Lattnerbf996f12007-04-30 17:29:31 +00003451 }
3452 }
3453
3454 // Otherwise, we couldn't allocate enough registers for this.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003455 return;
Chris Lattnerbf996f12007-04-30 17:29:31 +00003456}
3457
3458
Chris Lattnerce7518c2006-01-26 22:24:51 +00003459/// visitInlineAsm - Handle a call to an InlineAsm object.
3460///
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003461void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3462 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
Chris Lattnerce7518c2006-01-26 22:24:51 +00003463
Chris Lattner0c583402007-04-28 20:49:53 +00003464 /// ConstraintOperands - Information about all of the constraints.
3465 std::vector<AsmOperandInfo> ConstraintOperands;
Chris Lattnerce7518c2006-01-26 22:24:51 +00003466
3467 SDOperand Chain = getRoot();
3468 SDOperand Flag;
3469
Chris Lattner4e4b5762006-02-01 18:59:47 +00003470 std::set<unsigned> OutputRegs, InputRegs;
Chris Lattner1efa40f2006-02-22 00:56:39 +00003471
Chris Lattner0c583402007-04-28 20:49:53 +00003472 // Do a prepass over the constraints, canonicalizing them, and building up the
3473 // ConstraintOperands list.
3474 std::vector<InlineAsm::ConstraintInfo>
3475 ConstraintInfos = IA->ParseConstraints();
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003476
3477 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3478 // constraint. If so, we can't let the register allocator allocate any input
3479 // registers, because it will not know to avoid the earlyclobbered output reg.
3480 bool SawEarlyClobber = false;
3481
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003482 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
Chris Lattner0c583402007-04-28 20:49:53 +00003483 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3484 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3485 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3486
Chris Lattner0c583402007-04-28 20:49:53 +00003487 MVT::ValueType OpVT = MVT::Other;
3488
3489 // Compute the value type for each operand.
3490 switch (OpInfo.Type) {
Chris Lattner1efa40f2006-02-22 00:56:39 +00003491 case InlineAsm::isOutput:
Chris Lattner0c583402007-04-28 20:49:53 +00003492 if (!OpInfo.isIndirect) {
3493 // The return value of the call is this value. As such, there is no
3494 // corresponding argument.
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003495 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3496 OpVT = TLI.getValueType(CS.getType());
Chris Lattner1efa40f2006-02-22 00:56:39 +00003497 } else {
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003498 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
Chris Lattner1efa40f2006-02-22 00:56:39 +00003499 }
3500 break;
3501 case InlineAsm::isInput:
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003502 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
Chris Lattner1efa40f2006-02-22 00:56:39 +00003503 break;
3504 case InlineAsm::isClobber:
Chris Lattner0c583402007-04-28 20:49:53 +00003505 // Nothing to do.
Chris Lattner1efa40f2006-02-22 00:56:39 +00003506 break;
3507 }
Chris Lattner1efa40f2006-02-22 00:56:39 +00003508
Chris Lattner0c583402007-04-28 20:49:53 +00003509 // If this is an input or an indirect output, process the call argument.
Dale Johanneseneb57ea72007-11-05 21:20:28 +00003510 // BasicBlocks are labels, currently appearing only in asm's.
Chris Lattner0c583402007-04-28 20:49:53 +00003511 if (OpInfo.CallOperandVal) {
Dale Johanneseneb57ea72007-11-05 21:20:28 +00003512 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3513 OpInfo.CallOperand =
Dale Johannesenba2a0b92008-01-29 02:21:21 +00003514 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(
3515 OpInfo.CallOperandVal)]);
Dale Johanneseneb57ea72007-11-05 21:20:28 +00003516 else {
3517 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3518 const Type *OpTy = OpInfo.CallOperandVal->getType();
3519 // If this is an indirect operand, the operand is a pointer to the
3520 // accessed type.
3521 if (OpInfo.isIndirect)
3522 OpTy = cast<PointerType>(OpTy)->getElementType();
3523
3524 // If OpTy is not a first-class value, it may be a struct/union that we
3525 // can tile with integers.
3526 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3527 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3528 switch (BitSize) {
3529 default: break;
3530 case 1:
3531 case 8:
3532 case 16:
3533 case 32:
3534 case 64:
3535 OpTy = IntegerType::get(BitSize);
3536 break;
3537 }
Chris Lattner6995cf62007-04-29 18:58:03 +00003538 }
Dale Johanneseneb57ea72007-11-05 21:20:28 +00003539
3540 OpVT = TLI.getValueType(OpTy, true);
Chris Lattner0c583402007-04-28 20:49:53 +00003541 }
3542 }
3543
3544 OpInfo.ConstraintVT = OpVT;
Chris Lattner2a600be2007-04-28 21:01:43 +00003545
Chris Lattner3ff90dc2007-04-30 17:16:27 +00003546 // Compute the constraint code and ConstraintType to use.
3547 OpInfo.ComputeConstraintToUse(TLI);
Chris Lattner0c583402007-04-28 20:49:53 +00003548
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003549 // Keep track of whether we see an earlyclobber.
3550 SawEarlyClobber |= OpInfo.isEarlyClobber;
Chris Lattner09e4b7e2007-04-28 21:12:06 +00003551
3552 // If this is a memory input, and if the operand is not indirect, do what we
3553 // need to to provide an address for the memory input.
3554 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3555 !OpInfo.isIndirect) {
3556 assert(OpInfo.Type == InlineAsm::isInput &&
3557 "Can only indirectify direct input operands!");
3558
3559 // Memory operands really want the address of the value. If we don't have
3560 // an indirect input, put it in the constpool if we can, otherwise spill
3561 // it to a stack slot.
3562
3563 // If the operand is a float, integer, or vector constant, spill to a
3564 // constant pool entry to get its address.
3565 Value *OpVal = OpInfo.CallOperandVal;
3566 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3567 isa<ConstantVector>(OpVal)) {
3568 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3569 TLI.getPointerTy());
3570 } else {
3571 // Otherwise, create a stack slot and emit a store to it before the
3572 // asm.
3573 const Type *Ty = OpVal->getType();
Duncan Sands514ab342007-11-01 20:53:16 +00003574 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
Chris Lattner09e4b7e2007-04-28 21:12:06 +00003575 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3576 MachineFunction &MF = DAG.getMachineFunction();
3577 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3578 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3579 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3580 OpInfo.CallOperand = StackSlot;
3581 }
3582
3583 // There is no longer a Value* corresponding to this operand.
3584 OpInfo.CallOperandVal = 0;
3585 // It is now an indirect operand.
3586 OpInfo.isIndirect = true;
3587 }
3588
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003589 // If this constraint is for a specific register, allocate it before
3590 // anything else.
3591 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3592 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
Chris Lattner0c583402007-04-28 20:49:53 +00003593 }
Chris Lattner0c583402007-04-28 20:49:53 +00003594 ConstraintInfos.clear();
3595
3596
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003597 // Second pass - Loop over all of the operands, assigning virtual or physregs
3598 // to registerclass operands.
3599 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3600 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3601
3602 // C_Register operands have already been allocated, Other/Memory don't need
3603 // to be.
3604 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3605 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3606 }
3607
Chris Lattner0c583402007-04-28 20:49:53 +00003608 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3609 std::vector<SDOperand> AsmNodeOperands;
3610 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3611 AsmNodeOperands.push_back(
3612 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3613
Chris Lattner2cc2f662006-02-01 01:28:23 +00003614
Chris Lattner0f0b7d42006-02-21 23:12:12 +00003615 // Loop over all of the inputs, copying the operand values into the
3616 // appropriate registers and processing the output regs.
Chris Lattner864635a2006-02-22 22:37:12 +00003617 RegsForValue RetValRegs;
Chris Lattner0f0b7d42006-02-21 23:12:12 +00003618
Chris Lattner0c583402007-04-28 20:49:53 +00003619 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3620 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3621
3622 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3623 AsmOperandInfo &OpInfo = ConstraintOperands[i];
Chris Lattner1efa40f2006-02-22 00:56:39 +00003624
Chris Lattner0c583402007-04-28 20:49:53 +00003625 switch (OpInfo.Type) {
Chris Lattner2cc2f662006-02-01 01:28:23 +00003626 case InlineAsm::isOutput: {
Chris Lattnerc83994e2007-04-28 21:03:16 +00003627 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3628 OpInfo.ConstraintType != TargetLowering::C_Register) {
Chris Lattnerf2f3cd52007-04-28 06:08:13 +00003629 // Memory output, or 'other' output (e.g. 'X' constraint).
Chris Lattner09e4b7e2007-04-28 21:12:06 +00003630 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
Chris Lattner22873462006-02-27 23:45:39 +00003631
Chris Lattner22873462006-02-27 23:45:39 +00003632 // Add information to the INLINEASM node to know about this output.
3633 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
Chris Lattnerc90233b2007-05-15 01:33:58 +00003634 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3635 TLI.getPointerTy()));
Chris Lattner09e4b7e2007-04-28 21:12:06 +00003636 AsmNodeOperands.push_back(OpInfo.CallOperand);
Chris Lattner22873462006-02-27 23:45:39 +00003637 break;
3638 }
3639
Chris Lattner2a600be2007-04-28 21:01:43 +00003640 // Otherwise, this is a register or register class output.
Chris Lattner22873462006-02-27 23:45:39 +00003641
Chris Lattner864635a2006-02-22 22:37:12 +00003642 // Copy the output from the appropriate register. Find a register that
Chris Lattner1efa40f2006-02-22 00:56:39 +00003643 // we can use.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003644 if (OpInfo.AssignedRegs.Regs.empty()) {
Bill Wendling832171c2006-12-07 20:04:42 +00003645 cerr << "Couldn't allocate output reg for contraint '"
Chris Lattner0c583402007-04-28 20:49:53 +00003646 << OpInfo.ConstraintCode << "'!\n";
Chris Lattnerd03f1582006-10-31 07:33:13 +00003647 exit(1);
3648 }
Chris Lattner1efa40f2006-02-22 00:56:39 +00003649
Chris Lattner0c583402007-04-28 20:49:53 +00003650 if (!OpInfo.isIndirect) {
3651 // This is the result value of the call.
Chris Lattner864635a2006-02-22 22:37:12 +00003652 assert(RetValRegs.Regs.empty() &&
Chris Lattner2cc2f662006-02-01 01:28:23 +00003653 "Cannot have multiple output constraints yet!");
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003654 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003655 RetValRegs = OpInfo.AssignedRegs;
Chris Lattner2cc2f662006-02-01 01:28:23 +00003656 } else {
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003657 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
Chris Lattner0c583402007-04-28 20:49:53 +00003658 OpInfo.CallOperandVal));
Chris Lattner2cc2f662006-02-01 01:28:23 +00003659 }
Chris Lattner6656dd12006-01-31 02:03:41 +00003660
3661 // Add information to the INLINEASM node to know that this register is
3662 // set.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003663 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3664 AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00003665 break;
3666 }
3667 case InlineAsm::isInput: {
Chris Lattner0c583402007-04-28 20:49:53 +00003668 SDOperand InOperandVal = OpInfo.CallOperand;
Chris Lattner3d81fee2006-02-04 02:16:44 +00003669
Chris Lattner0c583402007-04-28 20:49:53 +00003670 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
Chris Lattner2223aea2006-02-02 00:25:23 +00003671 // If this is required to match an output register we have already set,
3672 // just use its register.
Chris Lattner0c583402007-04-28 20:49:53 +00003673 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
Chris Lattner3d81fee2006-02-04 02:16:44 +00003674
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003675 // Scan until we find the definition we already emitted of this operand.
3676 // When we find it, create a RegsForValue operand.
3677 unsigned CurOp = 2; // The first operand.
3678 for (; OperandNo; --OperandNo) {
3679 // Advance to the next operand.
3680 unsigned NumOps =
3681 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
Chris Lattnera15cf702006-07-20 19:02:21 +00003682 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3683 (NumOps & 7) == 4 /*MEM*/) &&
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003684 "Skipped past definitions?");
3685 CurOp += (NumOps>>3)+1;
3686 }
3687
3688 unsigned NumOps =
3689 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
Chris Lattner527fae12007-02-01 01:21:12 +00003690 if ((NumOps & 7) == 2 /*REGDEF*/) {
3691 // Add NumOps>>3 registers to MatchedRegs.
3692 RegsForValue MatchedRegs;
3693 MatchedRegs.ValueVT = InOperandVal.getValueType();
3694 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3695 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3696 unsigned Reg =
3697 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3698 MatchedRegs.Regs.push_back(Reg);
3699 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003700
Chris Lattner527fae12007-02-01 01:21:12 +00003701 // Use the produced MatchedRegs object to
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003702 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
Chris Lattner527fae12007-02-01 01:21:12 +00003703 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3704 break;
3705 } else {
3706 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3707 assert(0 && "matching constraints for memory operands unimp");
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003708 }
Chris Lattner2223aea2006-02-02 00:25:23 +00003709 }
Chris Lattner87bc3bd2006-02-24 01:11:24 +00003710
Chris Lattner2a600be2007-04-28 21:01:43 +00003711 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
Chris Lattner0c583402007-04-28 20:49:53 +00003712 assert(!OpInfo.isIndirect &&
Chris Lattner44b2c502007-04-28 06:42:38 +00003713 "Don't know how to handle indirect other inputs yet!");
3714
Chris Lattner48884cd2007-08-25 00:47:38 +00003715 std::vector<SDOperand> Ops;
3716 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3717 Ops, DAG);
3718 if (Ops.empty()) {
Bill Wendling832171c2006-12-07 20:04:42 +00003719 cerr << "Invalid operand for inline asm constraint '"
Chris Lattner0c583402007-04-28 20:49:53 +00003720 << OpInfo.ConstraintCode << "'!\n";
Chris Lattner53069fb2006-10-31 19:41:18 +00003721 exit(1);
3722 }
Chris Lattner87bc3bd2006-02-24 01:11:24 +00003723
3724 // Add information to the INLINEASM node to know about this input.
Chris Lattner48884cd2007-08-25 00:47:38 +00003725 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
Chris Lattnerc90233b2007-05-15 01:33:58 +00003726 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3727 TLI.getPointerTy()));
Chris Lattner48884cd2007-08-25 00:47:38 +00003728 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
Chris Lattner87bc3bd2006-02-24 01:11:24 +00003729 break;
Chris Lattner2a600be2007-04-28 21:01:43 +00003730 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
Chris Lattner09e4b7e2007-04-28 21:12:06 +00003731 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
Chris Lattner44b2c502007-04-28 06:42:38 +00003732 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3733 "Memory operands expect pointer values");
3734
Chris Lattner87bc3bd2006-02-24 01:11:24 +00003735 // Add information to the INLINEASM node to know about this input.
3736 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
Chris Lattnerc90233b2007-05-15 01:33:58 +00003737 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3738 TLI.getPointerTy()));
Chris Lattner87bc3bd2006-02-24 01:11:24 +00003739 AsmNodeOperands.push_back(InOperandVal);
3740 break;
3741 }
3742
Chris Lattner2a600be2007-04-28 21:01:43 +00003743 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3744 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3745 "Unknown constraint type!");
Chris Lattner0c583402007-04-28 20:49:53 +00003746 assert(!OpInfo.isIndirect &&
Chris Lattner44b2c502007-04-28 06:42:38 +00003747 "Don't know how to handle indirect register inputs yet!");
Chris Lattner87bc3bd2006-02-24 01:11:24 +00003748
3749 // Copy the input into the appropriate registers.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003750 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3751 "Couldn't allocate input reg!");
Chris Lattner87bc3bd2006-02-24 01:11:24 +00003752
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003753 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
Chris Lattner87bc3bd2006-02-24 01:11:24 +00003754
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003755 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3756 AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00003757 break;
3758 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003759 case InlineAsm::isClobber: {
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003760 // Add the clobbered value to the operand list, so that the register
3761 // allocator is aware that the physreg got clobbered.
Chris Lattnere7cf56a2007-04-30 21:11:17 +00003762 if (!OpInfo.AssignedRegs.Regs.empty())
3763 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3764 AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00003765 break;
3766 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00003767 }
Chris Lattner6656dd12006-01-31 02:03:41 +00003768 }
Chris Lattnerce7518c2006-01-26 22:24:51 +00003769
3770 // Finish up input operands.
3771 AsmNodeOperands[0] = Chain;
3772 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3773
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00003774 Chain = DAG.getNode(ISD::INLINEASM,
3775 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003776 &AsmNodeOperands[0], AsmNodeOperands.size());
Chris Lattnerce7518c2006-01-26 22:24:51 +00003777 Flag = Chain.getValue(1);
3778
Chris Lattner6656dd12006-01-31 02:03:41 +00003779 // If this asm returns a register value, copy the result from that register
3780 // and set it as the value of the call.
Chris Lattner3a508c92007-04-12 06:00:20 +00003781 if (!RetValRegs.Regs.empty()) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003782 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
Chris Lattner3a508c92007-04-12 06:00:20 +00003783
3784 // If the result of the inline asm is a vector, it may have the wrong
3785 // width/num elts. Make sure to convert it to the right type with
Dan Gohman7f321562007-06-25 16:23:39 +00003786 // bit_convert.
3787 if (MVT::isVector(Val.getValueType())) {
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003788 const VectorType *VTy = cast<VectorType>(CS.getType());
Dan Gohman7f321562007-06-25 16:23:39 +00003789 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
Chris Lattner3a508c92007-04-12 06:00:20 +00003790
Dan Gohman7f321562007-06-25 16:23:39 +00003791 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
Chris Lattner3a508c92007-04-12 06:00:20 +00003792 }
3793
Duncan Sandsfd7b3262007-12-17 18:08:19 +00003794 setValue(CS.getInstruction(), Val);
Chris Lattner3a508c92007-04-12 06:00:20 +00003795 }
Chris Lattnerce7518c2006-01-26 22:24:51 +00003796
Chris Lattner6656dd12006-01-31 02:03:41 +00003797 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3798
3799 // Process indirect outputs, first output all of the flagged copies out of
3800 // physregs.
3801 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
Chris Lattner864635a2006-02-22 22:37:12 +00003802 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
Chris Lattner6656dd12006-01-31 02:03:41 +00003803 Value *Ptr = IndirectStoresToEmit[i].second;
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003804 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
Chris Lattner864635a2006-02-22 22:37:12 +00003805 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
Chris Lattner6656dd12006-01-31 02:03:41 +00003806 }
3807
3808 // Emit the non-flagged stores from the physregs.
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003809 SmallVector<SDOperand, 8> OutChains;
Chris Lattner6656dd12006-01-31 02:03:41 +00003810 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
Chris Lattner0c583402007-04-28 20:49:53 +00003811 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
Chris Lattner6656dd12006-01-31 02:03:41 +00003812 getValue(StoresToEmit[i].second),
Evan Cheng8b2794a2006-10-13 21:14:26 +00003813 StoresToEmit[i].second, 0));
Chris Lattner6656dd12006-01-31 02:03:41 +00003814 if (!OutChains.empty())
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003815 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3816 &OutChains[0], OutChains.size());
Chris Lattnerce7518c2006-01-26 22:24:51 +00003817 DAG.setRoot(Chain);
3818}
3819
3820
Chris Lattner1c08c712005-01-07 07:47:53 +00003821void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3822 SDOperand Src = getValue(I.getOperand(0));
3823
3824 MVT::ValueType IntPtr = TLI.getPointerTy();
Chris Lattner68cd65e2005-01-22 23:04:37 +00003825
3826 if (IntPtr < Src.getValueType())
3827 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3828 else if (IntPtr > Src.getValueType())
3829 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
Chris Lattner1c08c712005-01-07 07:47:53 +00003830
3831 // Scale the source by the type size.
Duncan Sands514ab342007-11-01 20:53:16 +00003832 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
Chris Lattner1c08c712005-01-07 07:47:53 +00003833 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
Chris Lattner0bd48932008-01-17 07:00:52 +00003834 Src, DAG.getIntPtrConstant(ElementSize));
Chris Lattner1c08c712005-01-07 07:47:53 +00003835
Reid Spencer47857812006-12-31 05:55:36 +00003836 TargetLowering::ArgListTy Args;
3837 TargetLowering::ArgListEntry Entry;
3838 Entry.Node = Src;
3839 Entry.Ty = TLI.getTargetData()->getIntPtrType();
Reid Spencer47857812006-12-31 05:55:36 +00003840 Args.push_back(Entry);
Chris Lattnercf5734d2005-01-08 19:26:18 +00003841
3842 std::pair<SDOperand,SDOperand> Result =
Reid Spencer47857812006-12-31 05:55:36 +00003843 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
Chris Lattnercf5734d2005-01-08 19:26:18 +00003844 DAG.getExternalSymbol("malloc", IntPtr),
3845 Args, DAG);
3846 setValue(&I, Result.first); // Pointers always fit in registers
3847 DAG.setRoot(Result.second);
Chris Lattner1c08c712005-01-07 07:47:53 +00003848}
3849
3850void SelectionDAGLowering::visitFree(FreeInst &I) {
Reid Spencer47857812006-12-31 05:55:36 +00003851 TargetLowering::ArgListTy Args;
3852 TargetLowering::ArgListEntry Entry;
3853 Entry.Node = getValue(I.getOperand(0));
3854 Entry.Ty = TLI.getTargetData()->getIntPtrType();
Reid Spencer47857812006-12-31 05:55:36 +00003855 Args.push_back(Entry);
Chris Lattner1c08c712005-01-07 07:47:53 +00003856 MVT::ValueType IntPtr = TLI.getPointerTy();
Chris Lattnercf5734d2005-01-08 19:26:18 +00003857 std::pair<SDOperand,SDOperand> Result =
Reid Spencer47857812006-12-31 05:55:36 +00003858 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
Chris Lattnercf5734d2005-01-08 19:26:18 +00003859 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3860 DAG.setRoot(Result.second);
Chris Lattner1c08c712005-01-07 07:47:53 +00003861}
3862
Evan Chengff9b3732008-01-30 18:18:23 +00003863// EmitInstrWithCustomInserter - This method should be implemented by targets
3864// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
Chris Lattner025c39b2005-08-26 20:54:47 +00003865// instructions are special in various ways, which require special support to
3866// insert. The specified MachineInstr is created but not inserted into any
3867// basic blocks, and the scheduler passes ownership of it to this method.
Evan Chengff9b3732008-01-30 18:18:23 +00003868MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Chris Lattner025c39b2005-08-26 20:54:47 +00003869 MachineBasicBlock *MBB) {
Bill Wendling832171c2006-12-07 20:04:42 +00003870 cerr << "If a target marks an instruction with "
3871 << "'usesCustomDAGSchedInserter', it must implement "
Evan Chengff9b3732008-01-30 18:18:23 +00003872 << "TargetLowering::EmitInstrWithCustomInserter!\n";
Chris Lattner025c39b2005-08-26 20:54:47 +00003873 abort();
3874 return 0;
3875}
3876
Chris Lattner39ae3622005-01-09 00:00:49 +00003877void SelectionDAGLowering::visitVAStart(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00003878 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3879 getValue(I.getOperand(1)),
3880 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner39ae3622005-01-09 00:00:49 +00003881}
3882
3883void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00003884 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3885 getValue(I.getOperand(0)),
3886 DAG.getSrcValue(I.getOperand(0)));
3887 setValue(&I, V);
3888 DAG.setRoot(V.getValue(1));
Chris Lattner1c08c712005-01-07 07:47:53 +00003889}
3890
3891void SelectionDAGLowering::visitVAEnd(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00003892 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3893 getValue(I.getOperand(1)),
3894 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner1c08c712005-01-07 07:47:53 +00003895}
3896
3897void SelectionDAGLowering::visitVACopy(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00003898 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3899 getValue(I.getOperand(1)),
3900 getValue(I.getOperand(2)),
3901 DAG.getSrcValue(I.getOperand(1)),
3902 DAG.getSrcValue(I.getOperand(2))));
Chris Lattner1c08c712005-01-07 07:47:53 +00003903}
3904
Chris Lattnerfdfded52006-04-12 16:20:43 +00003905/// TargetLowering::LowerArguments - This is the default LowerArguments
3906/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
Chris Lattnerf4ec8172006-05-16 22:53:20 +00003907/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3908/// integrated into SDISel.
Chris Lattnerfdfded52006-04-12 16:20:43 +00003909std::vector<SDOperand>
3910TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3911 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3912 std::vector<SDOperand> Ops;
Chris Lattner8c0c10c2006-05-16 06:45:34 +00003913 Ops.push_back(DAG.getRoot());
Chris Lattnerfdfded52006-04-12 16:20:43 +00003914 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3915 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3916
3917 // Add one result value for each formal argument.
3918 std::vector<MVT::ValueType> RetVals;
Anton Korobeynikov6aa279d2007-01-28 18:01:49 +00003919 unsigned j = 1;
Anton Korobeynikovac2b2cf2007-01-28 16:04:40 +00003920 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3921 I != E; ++I, ++j) {
Chris Lattnerfdfded52006-04-12 16:20:43 +00003922 MVT::ValueType VT = getValueType(I->getType());
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00003923 unsigned Flags = ISD::ParamFlags::NoFlagSet;
Lauro Ramos Venancio7aa47b62007-02-13 13:50:08 +00003924 unsigned OriginalAlignment =
Chris Lattnerd2b7cec2007-02-14 05:52:17 +00003925 getTargetData()->getABITypeAlignment(I->getType());
Lauro Ramos Venancio7aa47b62007-02-13 13:50:08 +00003926
Chris Lattnerddf53e42007-02-26 02:56:58 +00003927 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3928 // that is zero extended!
Duncan Sandsafa3b6d2007-11-28 17:07:01 +00003929 if (F.paramHasAttr(j, ParamAttr::ZExt))
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00003930 Flags &= ~(ISD::ParamFlags::SExt);
Duncan Sandsafa3b6d2007-11-28 17:07:01 +00003931 if (F.paramHasAttr(j, ParamAttr::SExt))
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00003932 Flags |= ISD::ParamFlags::SExt;
Duncan Sandsafa3b6d2007-11-28 17:07:01 +00003933 if (F.paramHasAttr(j, ParamAttr::InReg))
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00003934 Flags |= ISD::ParamFlags::InReg;
Duncan Sandsafa3b6d2007-11-28 17:07:01 +00003935 if (F.paramHasAttr(j, ParamAttr::StructRet))
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00003936 Flags |= ISD::ParamFlags::StructReturn;
Duncan Sandsafa3b6d2007-11-28 17:07:01 +00003937 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
Rafael Espindola1aa7efb2007-07-06 10:57:03 +00003938 Flags |= ISD::ParamFlags::ByVal;
Rafael Espindola594d37e2007-08-10 14:44:42 +00003939 const PointerType *Ty = cast<PointerType>(I->getType());
Duncan Sandsa41d7192008-01-13 21:19:59 +00003940 const Type *ElementTy = Ty->getElementType();
Evan Cheng3ae05432008-01-24 00:22:01 +00003941 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
Duncan Sandsa41d7192008-01-13 21:19:59 +00003942 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
3943 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
3944 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
Rafael Espindola594d37e2007-08-10 14:44:42 +00003945 }
Duncan Sandsafa3b6d2007-11-28 17:07:01 +00003946 if (F.paramHasAttr(j, ParamAttr::Nest))
Duncan Sands36397f52007-07-27 12:58:54 +00003947 Flags |= ISD::ParamFlags::Nest;
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00003948 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
Chris Lattnerddf53e42007-02-26 02:56:58 +00003949
Chris Lattnerfdfded52006-04-12 16:20:43 +00003950 switch (getTypeAction(VT)) {
3951 default: assert(0 && "Unknown type action!");
3952 case Legal:
3953 RetVals.push_back(VT);
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00003954 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattnerfdfded52006-04-12 16:20:43 +00003955 break;
3956 case Promote:
3957 RetVals.push_back(getTypeToTransformTo(VT));
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00003958 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattnerfdfded52006-04-12 16:20:43 +00003959 break;
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003960 case Expand: {
3961 // If this is an illegal type, it needs to be broken up to fit into
3962 // registers.
3963 MVT::ValueType RegisterVT = getRegisterType(VT);
3964 unsigned NumRegs = getNumRegisters(VT);
3965 for (unsigned i = 0; i != NumRegs; ++i) {
3966 RetVals.push_back(RegisterVT);
3967 // if it isn't first piece, alignment must be 1
3968 if (i > 0)
3969 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3970 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3971 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattnerfdfded52006-04-12 16:20:43 +00003972 }
3973 break;
3974 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +00003975 }
Chris Lattnerfdfded52006-04-12 16:20:43 +00003976 }
Evan Cheng3b0d2862006-04-25 23:03:35 +00003977
Chris Lattner8c0c10c2006-05-16 06:45:34 +00003978 RetVals.push_back(MVT::Other);
Chris Lattnerfdfded52006-04-12 16:20:43 +00003979
3980 // Create the node.
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00003981 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3982 DAG.getNodeValueTypes(RetVals), RetVals.size(),
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003983 &Ops[0], Ops.size()).Val;
Dan Gohman27a70be2007-07-02 16:18:06 +00003984 unsigned NumArgRegs = Result->getNumValues() - 1;
3985 DAG.setRoot(SDOperand(Result, NumArgRegs));
Chris Lattnerfdfded52006-04-12 16:20:43 +00003986
3987 // Set up the return result vector.
3988 Ops.clear();
3989 unsigned i = 0;
Reid Spencer47857812006-12-31 05:55:36 +00003990 unsigned Idx = 1;
3991 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3992 ++I, ++Idx) {
Chris Lattnerfdfded52006-04-12 16:20:43 +00003993 MVT::ValueType VT = getValueType(I->getType());
3994
3995 switch (getTypeAction(VT)) {
3996 default: assert(0 && "Unknown type action!");
3997 case Legal:
3998 Ops.push_back(SDOperand(Result, i++));
3999 break;
4000 case Promote: {
4001 SDOperand Op(Result, i++);
4002 if (MVT::isInteger(VT)) {
Duncan Sandsafa3b6d2007-11-28 17:07:01 +00004003 if (F.paramHasAttr(Idx, ParamAttr::SExt))
Chris Lattnerf8e7a212007-01-04 22:22:37 +00004004 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
4005 DAG.getValueType(VT));
Duncan Sandsafa3b6d2007-11-28 17:07:01 +00004006 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
Chris Lattnerf8e7a212007-01-04 22:22:37 +00004007 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
4008 DAG.getValueType(VT));
Chris Lattnerfdfded52006-04-12 16:20:43 +00004009 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
4010 } else {
4011 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
Chris Lattner0bd48932008-01-17 07:00:52 +00004012 Op = DAG.getNode(ISD::FP_ROUND, VT, Op, DAG.getIntPtrConstant(1));
Chris Lattnerfdfded52006-04-12 16:20:43 +00004013 }
4014 Ops.push_back(Op);
4015 break;
4016 }
Dan Gohman27a70be2007-07-02 16:18:06 +00004017 case Expand: {
4018 MVT::ValueType PartVT = getRegisterType(VT);
4019 unsigned NumParts = getNumRegisters(VT);
4020 SmallVector<SDOperand, 4> Parts(NumParts);
4021 for (unsigned j = 0; j != NumParts; ++j)
4022 Parts[j] = SDOperand(Result, i++);
Dan Gohman532dc2e2007-07-09 20:59:04 +00004023 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
Chris Lattnerfdfded52006-04-12 16:20:43 +00004024 break;
4025 }
Dan Gohman27a70be2007-07-02 16:18:06 +00004026 }
Chris Lattnerfdfded52006-04-12 16:20:43 +00004027 }
Dan Gohman27a70be2007-07-02 16:18:06 +00004028 assert(i == NumArgRegs && "Argument register count mismatch!");
Chris Lattnerfdfded52006-04-12 16:20:43 +00004029 return Ops;
4030}
4031
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004032
4033/// TargetLowering::LowerCallTo - This is the default LowerCallTo
4034/// implementation, which just inserts an ISD::CALL node, which is later custom
4035/// lowered by the target to something concrete. FIXME: When all targets are
4036/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4037std::pair<SDOperand, SDOperand>
Reid Spencer47857812006-12-31 05:55:36 +00004038TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4039 bool RetTyIsSigned, bool isVarArg,
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004040 unsigned CallingConv, bool isTailCall,
4041 SDOperand Callee,
4042 ArgListTy &Args, SelectionDAG &DAG) {
Chris Lattnerbe384162006-08-16 22:57:46 +00004043 SmallVector<SDOperand, 32> Ops;
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004044 Ops.push_back(Chain); // Op#0 - Chain
4045 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4046 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4047 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4048 Ops.push_back(Callee);
4049
4050 // Handle all of the outgoing arguments.
4051 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
Reid Spencer47857812006-12-31 05:55:36 +00004052 MVT::ValueType VT = getValueType(Args[i].Ty);
4053 SDOperand Op = Args[i].Node;
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00004054 unsigned Flags = ISD::ParamFlags::NoFlagSet;
Lauro Ramos Venancio7aa47b62007-02-13 13:50:08 +00004055 unsigned OriginalAlignment =
Chris Lattnerd2b7cec2007-02-14 05:52:17 +00004056 getTargetData()->getABITypeAlignment(Args[i].Ty);
Anton Korobeynikov0db79d82007-03-06 06:10:33 +00004057
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00004058 if (Args[i].isSExt)
4059 Flags |= ISD::ParamFlags::SExt;
4060 if (Args[i].isZExt)
4061 Flags |= ISD::ParamFlags::ZExt;
Anton Korobeynikov0db79d82007-03-06 06:10:33 +00004062 if (Args[i].isInReg)
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00004063 Flags |= ISD::ParamFlags::InReg;
Anton Korobeynikov0db79d82007-03-06 06:10:33 +00004064 if (Args[i].isSRet)
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00004065 Flags |= ISD::ParamFlags::StructReturn;
Rafael Espindola21485be2007-08-20 15:18:24 +00004066 if (Args[i].isByVal) {
4067 Flags |= ISD::ParamFlags::ByVal;
4068 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
Duncan Sandsa41d7192008-01-13 21:19:59 +00004069 const Type *ElementTy = Ty->getElementType();
Evan Cheng3ae05432008-01-24 00:22:01 +00004070 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
Duncan Sandsa41d7192008-01-13 21:19:59 +00004071 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4072 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4073 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
Rafael Espindola21485be2007-08-20 15:18:24 +00004074 }
Duncan Sands36397f52007-07-27 12:58:54 +00004075 if (Args[i].isNest)
4076 Flags |= ISD::ParamFlags::Nest;
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00004077 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
Anton Korobeynikov0db79d82007-03-06 06:10:33 +00004078
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004079 switch (getTypeAction(VT)) {
4080 default: assert(0 && "Unknown type action!");
Lauro Ramos Venancio7aa47b62007-02-13 13:50:08 +00004081 case Legal:
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004082 Ops.push_back(Op);
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00004083 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004084 break;
4085 case Promote:
4086 if (MVT::isInteger(VT)) {
Anton Korobeynikovd0b82b32007-03-07 16:25:09 +00004087 unsigned ExtOp;
4088 if (Args[i].isSExt)
4089 ExtOp = ISD::SIGN_EXTEND;
4090 else if (Args[i].isZExt)
4091 ExtOp = ISD::ZERO_EXTEND;
4092 else
4093 ExtOp = ISD::ANY_EXTEND;
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004094 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
4095 } else {
4096 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
Dale Johannesen849f2142007-07-03 00:53:03 +00004097 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004098 }
4099 Ops.push_back(Op);
Anton Korobeynikovb10308e2007-01-28 13:31:35 +00004100 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004101 break;
Dan Gohman27a70be2007-07-02 16:18:06 +00004102 case Expand: {
4103 MVT::ValueType PartVT = getRegisterType(VT);
4104 unsigned NumParts = getNumRegisters(VT);
4105 SmallVector<SDOperand, 4> Parts(NumParts);
Dan Gohman532dc2e2007-07-09 20:59:04 +00004106 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
Dan Gohman27a70be2007-07-02 16:18:06 +00004107 for (unsigned i = 0; i != NumParts; ++i) {
4108 // if it isn't first piece, alignment must be 1
4109 unsigned MyFlags = Flags;
4110 if (i != 0)
4111 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4112 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4113
4114 Ops.push_back(Parts[i]);
4115 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004116 }
4117 break;
4118 }
Dan Gohman27a70be2007-07-02 16:18:06 +00004119 }
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004120 }
4121
4122 // Figure out the result value types.
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004123 MVT::ValueType VT = getValueType(RetTy);
4124 MVT::ValueType RegisterVT = getRegisterType(VT);
4125 unsigned NumRegs = getNumRegisters(VT);
4126 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4127 for (unsigned i = 0; i != NumRegs; ++i)
4128 RetTys[i] = RegisterVT;
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004129
4130 RetTys.push_back(MVT::Other); // Always has a chain.
4131
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004132 // Create the CALL node.
Chris Lattnerbe384162006-08-16 22:57:46 +00004133 SDOperand Res = DAG.getNode(ISD::CALL,
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004134 DAG.getVTList(&RetTys[0], NumRegs + 1),
Chris Lattnerbe384162006-08-16 22:57:46 +00004135 &Ops[0], Ops.size());
Chris Lattnerb15e4952007-08-02 18:08:16 +00004136 Chain = Res.getValue(NumRegs);
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004137
4138 // Gather up the call result into a single value.
4139 if (RetTy != Type::VoidTy) {
4140 ISD::NodeType AssertOp = ISD::AssertSext;
4141 if (!RetTyIsSigned)
4142 AssertOp = ISD::AssertZext;
4143 SmallVector<SDOperand, 4> Results(NumRegs);
4144 for (unsigned i = 0; i != NumRegs; ++i)
4145 Results[i] = Res.getValue(i);
Dan Gohman532dc2e2007-07-09 20:59:04 +00004146 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004147 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004148
4149 return std::make_pair(Res, Chain);
Chris Lattnerf4ec8172006-05-16 22:53:20 +00004150}
4151
Chris Lattner50381b62005-05-14 05:50:48 +00004152SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner171453a2005-01-16 07:28:41 +00004153 assert(0 && "LowerOperation not implemented for this target!");
4154 abort();
Misha Brukmand3f03e42005-02-17 21:39:27 +00004155 return SDOperand();
Chris Lattner171453a2005-01-16 07:28:41 +00004156}
4157
Nate Begeman0aed7842006-01-28 03:14:31 +00004158SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4159 SelectionDAG &DAG) {
4160 assert(0 && "CustomPromoteOperation not implemented for this target!");
4161 abort();
4162 return SDOperand();
4163}
4164
Evan Cheng74d0aa92006-02-15 21:59:04 +00004165/// getMemsetValue - Vectorized representation of the memset value
Evan Cheng1db92f92006-02-14 08:22:34 +00004166/// operand.
4167static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
Evan Chenga47876d2006-02-15 22:12:35 +00004168 SelectionDAG &DAG) {
Evan Cheng1db92f92006-02-14 08:22:34 +00004169 MVT::ValueType CurVT = VT;
4170 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4171 uint64_t Val = C->getValue() & 255;
4172 unsigned Shift = 8;
4173 while (CurVT != MVT::i8) {
4174 Val = (Val << Shift) | Val;
4175 Shift <<= 1;
4176 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
Evan Cheng1db92f92006-02-14 08:22:34 +00004177 }
4178 return DAG.getConstant(Val, VT);
4179 } else {
4180 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4181 unsigned Shift = 8;
4182 while (CurVT != MVT::i8) {
4183 Value =
4184 DAG.getNode(ISD::OR, VT,
4185 DAG.getNode(ISD::SHL, VT, Value,
4186 DAG.getConstant(Shift, MVT::i8)), Value);
4187 Shift <<= 1;
4188 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
Evan Cheng1db92f92006-02-14 08:22:34 +00004189 }
4190
4191 return Value;
4192 }
4193}
4194
Evan Cheng74d0aa92006-02-15 21:59:04 +00004195/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4196/// used when a memcpy is turned into a memset when the source is a constant
4197/// string ptr.
4198static SDOperand getMemsetStringVal(MVT::ValueType VT,
4199 SelectionDAG &DAG, TargetLowering &TLI,
4200 std::string &Str, unsigned Offset) {
Evan Cheng74d0aa92006-02-15 21:59:04 +00004201 uint64_t Val = 0;
Dan Gohmanb55757e2007-05-18 17:52:13 +00004202 unsigned MSB = MVT::getSizeInBits(VT) / 8;
Evan Cheng74d0aa92006-02-15 21:59:04 +00004203 if (TLI.isLittleEndian())
4204 Offset = Offset + MSB - 1;
4205 for (unsigned i = 0; i != MSB; ++i) {
Evan Chenga5a57d62006-11-29 01:38:07 +00004206 Val = (Val << 8) | (unsigned char)Str[Offset];
Evan Cheng74d0aa92006-02-15 21:59:04 +00004207 Offset += TLI.isLittleEndian() ? -1 : 1;
4208 }
4209 return DAG.getConstant(Val, VT);
4210}
4211
Evan Cheng1db92f92006-02-14 08:22:34 +00004212/// getMemBasePlusOffset - Returns base and offset node for the
4213static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4214 SelectionDAG &DAG, TargetLowering &TLI) {
4215 MVT::ValueType VT = Base.getValueType();
4216 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4217}
4218
Evan Chengc4f8eee2006-02-14 20:12:38 +00004219/// MeetsMaxMemopRequirement - Determines if the number of memory ops required
Evan Cheng80e89d72006-02-14 09:11:59 +00004220/// to replace the memset / memcpy is below the threshold. It also returns the
4221/// types of the sequence of memory ops to perform memset / memcpy.
Evan Chengc4f8eee2006-02-14 20:12:38 +00004222static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4223 unsigned Limit, uint64_t Size,
4224 unsigned Align, TargetLowering &TLI) {
Evan Cheng1db92f92006-02-14 08:22:34 +00004225 MVT::ValueType VT;
4226
4227 if (TLI.allowsUnalignedMemoryAccesses()) {
4228 VT = MVT::i64;
4229 } else {
4230 switch (Align & 7) {
4231 case 0:
4232 VT = MVT::i64;
4233 break;
4234 case 4:
4235 VT = MVT::i32;
4236 break;
4237 case 2:
4238 VT = MVT::i16;
4239 break;
4240 default:
4241 VT = MVT::i8;
4242 break;
4243 }
4244 }
4245
Evan Cheng80e89d72006-02-14 09:11:59 +00004246 MVT::ValueType LVT = MVT::i64;
4247 while (!TLI.isTypeLegal(LVT))
4248 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4249 assert(MVT::isInteger(LVT));
Evan Cheng1db92f92006-02-14 08:22:34 +00004250
Evan Cheng80e89d72006-02-14 09:11:59 +00004251 if (VT > LVT)
4252 VT = LVT;
4253
Evan Chengdea72452006-02-14 23:05:54 +00004254 unsigned NumMemOps = 0;
Evan Cheng1db92f92006-02-14 08:22:34 +00004255 while (Size != 0) {
Dan Gohmanb55757e2007-05-18 17:52:13 +00004256 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
Evan Cheng1db92f92006-02-14 08:22:34 +00004257 while (VTSize > Size) {
4258 VT = (MVT::ValueType)((unsigned)VT - 1);
Evan Cheng1db92f92006-02-14 08:22:34 +00004259 VTSize >>= 1;
4260 }
Evan Cheng80e89d72006-02-14 09:11:59 +00004261 assert(MVT::isInteger(VT));
4262
4263 if (++NumMemOps > Limit)
4264 return false;
Evan Cheng1db92f92006-02-14 08:22:34 +00004265 MemOps.push_back(VT);
4266 Size -= VTSize;
4267 }
Evan Cheng80e89d72006-02-14 09:11:59 +00004268
4269 return true;
Evan Cheng1db92f92006-02-14 08:22:34 +00004270}
4271
Chris Lattner7041ee32005-01-11 05:56:49 +00004272void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
Evan Cheng1db92f92006-02-14 08:22:34 +00004273 SDOperand Op1 = getValue(I.getOperand(1));
4274 SDOperand Op2 = getValue(I.getOperand(2));
4275 SDOperand Op3 = getValue(I.getOperand(3));
4276 SDOperand Op4 = getValue(I.getOperand(4));
4277 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4278 if (Align == 0) Align = 1;
4279
Dan Gohman5f43f922007-08-27 16:26:13 +00004280 // If the source and destination are known to not be aliases, we can
4281 // lower memmove as memcpy.
4282 if (Op == ISD::MEMMOVE) {
Anton Korobeynikov8806c7b2007-09-07 11:39:35 +00004283 uint64_t Size = -1ULL;
Dan Gohman5f43f922007-08-27 16:26:13 +00004284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4285 Size = C->getValue();
4286 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4287 AliasAnalysis::NoAlias)
4288 Op = ISD::MEMCPY;
4289 }
4290
Evan Cheng1db92f92006-02-14 08:22:34 +00004291 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4292 std::vector<MVT::ValueType> MemOps;
Evan Cheng1db92f92006-02-14 08:22:34 +00004293
4294 // Expand memset / memcpy to a series of load / store ops
4295 // if the size operand falls below a certain threshold.
Chris Lattnerbd564bf2006-08-08 02:23:42 +00004296 SmallVector<SDOperand, 8> OutChains;
Evan Cheng1db92f92006-02-14 08:22:34 +00004297 switch (Op) {
Evan Chengac940ab2006-02-14 19:45:56 +00004298 default: break; // Do nothing for now.
Evan Cheng1db92f92006-02-14 08:22:34 +00004299 case ISD::MEMSET: {
Evan Chengc4f8eee2006-02-14 20:12:38 +00004300 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4301 Size->getValue(), Align, TLI)) {
Evan Cheng80e89d72006-02-14 09:11:59 +00004302 unsigned NumMemOps = MemOps.size();
Evan Cheng1db92f92006-02-14 08:22:34 +00004303 unsigned Offset = 0;
4304 for (unsigned i = 0; i < NumMemOps; i++) {
4305 MVT::ValueType VT = MemOps[i];
Dan Gohmanb55757e2007-05-18 17:52:13 +00004306 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
Evan Chenga47876d2006-02-15 22:12:35 +00004307 SDOperand Value = getMemsetValue(Op2, VT, DAG);
Evan Cheng786225a2006-10-05 23:01:46 +00004308 SDOperand Store = DAG.getStore(getRoot(), Value,
Chris Lattner864635a2006-02-22 22:37:12 +00004309 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004310 I.getOperand(1), Offset);
Evan Chengc080d6f2006-02-15 01:54:51 +00004311 OutChains.push_back(Store);
Evan Cheng1db92f92006-02-14 08:22:34 +00004312 Offset += VTSize;
4313 }
Evan Cheng1db92f92006-02-14 08:22:34 +00004314 }
Evan Chengc080d6f2006-02-15 01:54:51 +00004315 break;
Evan Cheng1db92f92006-02-14 08:22:34 +00004316 }
Evan Chengc080d6f2006-02-15 01:54:51 +00004317 case ISD::MEMCPY: {
4318 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4319 Size->getValue(), Align, TLI)) {
4320 unsigned NumMemOps = MemOps.size();
Evan Chengcffbb512006-02-16 23:11:42 +00004321 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
Evan Cheng74d0aa92006-02-15 21:59:04 +00004322 GlobalAddressSDNode *G = NULL;
4323 std::string Str;
Evan Chengcffbb512006-02-16 23:11:42 +00004324 bool CopyFromStr = false;
Evan Cheng74d0aa92006-02-15 21:59:04 +00004325
4326 if (Op2.getOpcode() == ISD::GlobalAddress)
4327 G = cast<GlobalAddressSDNode>(Op2);
4328 else if (Op2.getOpcode() == ISD::ADD &&
4329 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4330 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4331 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
Evan Chengcffbb512006-02-16 23:11:42 +00004332 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
Evan Cheng74d0aa92006-02-15 21:59:04 +00004333 }
4334 if (G) {
4335 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
Evan Chengf3e486e2006-11-29 01:58:12 +00004336 if (GV && GV->isConstant()) {
Evan Cheng09371032006-03-10 23:52:03 +00004337 Str = GV->getStringValue(false);
Evan Chengcffbb512006-02-16 23:11:42 +00004338 if (!Str.empty()) {
4339 CopyFromStr = true;
4340 SrcOff += SrcDelta;
4341 }
4342 }
Evan Cheng74d0aa92006-02-15 21:59:04 +00004343 }
4344
Evan Chengc080d6f2006-02-15 01:54:51 +00004345 for (unsigned i = 0; i < NumMemOps; i++) {
4346 MVT::ValueType VT = MemOps[i];
Dan Gohmanb55757e2007-05-18 17:52:13 +00004347 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
Evan Cheng74d0aa92006-02-15 21:59:04 +00004348 SDOperand Value, Chain, Store;
4349
Evan Chengcffbb512006-02-16 23:11:42 +00004350 if (CopyFromStr) {
Evan Cheng74d0aa92006-02-15 21:59:04 +00004351 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4352 Chain = getRoot();
4353 Store =
Evan Cheng786225a2006-10-05 23:01:46 +00004354 DAG.getStore(Chain, Value,
4355 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
Evan Cheng8b2794a2006-10-13 21:14:26 +00004356 I.getOperand(1), DstOff);
Evan Cheng74d0aa92006-02-15 21:59:04 +00004357 } else {
4358 Value = DAG.getLoad(VT, getRoot(),
Bill Wendling984e9862007-10-26 20:24:42 +00004359 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4360 I.getOperand(2), SrcOff, false, Align);
Evan Cheng74d0aa92006-02-15 21:59:04 +00004361 Chain = Value.getValue(1);
4362 Store =
Evan Cheng786225a2006-10-05 23:01:46 +00004363 DAG.getStore(Chain, Value,
4364 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
Bill Wendling984e9862007-10-26 20:24:42 +00004365 I.getOperand(1), DstOff, false, Align);
Evan Cheng74d0aa92006-02-15 21:59:04 +00004366 }
Evan Chengc080d6f2006-02-15 01:54:51 +00004367 OutChains.push_back(Store);
Evan Cheng74d0aa92006-02-15 21:59:04 +00004368 SrcOff += VTSize;
4369 DstOff += VTSize;
Evan Chengc080d6f2006-02-15 01:54:51 +00004370 }
4371 }
4372 break;
4373 }
4374 }
4375
4376 if (!OutChains.empty()) {
Chris Lattnerbd564bf2006-08-08 02:23:42 +00004377 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4378 &OutChains[0], OutChains.size()));
Evan Chengc080d6f2006-02-15 01:54:51 +00004379 return;
Evan Cheng1db92f92006-02-14 08:22:34 +00004380 }
4381 }
4382
Rafael Espindola5c0d6ed2007-10-19 10:41:11 +00004383 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4384 SDOperand Node;
4385 switch(Op) {
4386 default:
4387 assert(0 && "Unknown Op");
4388 case ISD::MEMCPY:
4389 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4390 break;
4391 case ISD::MEMMOVE:
4392 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4393 break;
4394 case ISD::MEMSET:
4395 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4396 break;
4397 }
4398 DAG.setRoot(Node);
Chris Lattner1c08c712005-01-07 07:47:53 +00004399}
4400
Chris Lattner7041ee32005-01-11 05:56:49 +00004401//===----------------------------------------------------------------------===//
4402// SelectionDAGISel code
4403//===----------------------------------------------------------------------===//
Chris Lattner1c08c712005-01-07 07:47:53 +00004404
4405unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
Chris Lattner84bc5422007-12-31 04:13:23 +00004406 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
Chris Lattner1c08c712005-01-07 07:47:53 +00004407}
4408
Chris Lattner495a0b52005-08-17 06:37:43 +00004409void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
Jim Laskeyc7c3f112006-10-16 20:52:31 +00004410 AU.addRequired<AliasAnalysis>();
Gordon Henriksence224772008-01-07 01:30:38 +00004411 AU.addRequired<CollectorModuleMetadata>();
Chris Lattnerc8d288f2007-03-31 04:18:03 +00004412 AU.setPreservesAll();
Chris Lattner495a0b52005-08-17 06:37:43 +00004413}
Chris Lattner1c08c712005-01-07 07:47:53 +00004414
Chris Lattnerc88d8e92005-12-05 07:10:48 +00004415
Chris Lattnerbad7f482006-10-28 19:22:10 +00004416
Chris Lattner1c08c712005-01-07 07:47:53 +00004417bool SelectionDAGISel::runOnFunction(Function &Fn) {
Dan Gohman5f43f922007-08-27 16:26:13 +00004418 // Get alias analysis for load/store combining.
4419 AA = &getAnalysis<AliasAnalysis>();
4420
Chris Lattner1c08c712005-01-07 07:47:53 +00004421 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
Gordon Henriksence224772008-01-07 01:30:38 +00004422 if (MF.getFunction()->hasCollector())
4423 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4424 else
4425 GCI = 0;
Chris Lattner84bc5422007-12-31 04:13:23 +00004426 RegInfo = &MF.getRegInfo();
Bill Wendling832171c2006-12-07 20:04:42 +00004427 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
Chris Lattner1c08c712005-01-07 07:47:53 +00004428
4429 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4430
Duncan Sandsea632432007-06-13 16:53:21 +00004431 if (ExceptionHandling)
4432 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4433 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4434 // Mark landing pad.
4435 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
Duncan Sands9fac0b52007-06-06 10:05:18 +00004436
4437 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
Chris Lattner1c08c712005-01-07 07:47:53 +00004438 SelectBasicBlock(I, MF, FuncInfo);
Misha Brukmanedf128a2005-04-21 22:36:52 +00004439
Evan Chengad2070c2007-02-10 02:43:39 +00004440 // Add function live-ins to entry block live-in set.
4441 BasicBlock *EntryBB = &Fn.getEntryBlock();
4442 BB = FuncInfo.MBBMap[EntryBB];
Chris Lattner84bc5422007-12-31 04:13:23 +00004443 if (!RegInfo->livein_empty())
4444 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4445 E = RegInfo->livein_end(); I != E; ++I)
Evan Chengad2070c2007-02-10 02:43:39 +00004446 BB->addLiveIn(I->first);
4447
Duncan Sandsf4070822007-06-15 19:04:19 +00004448#ifndef NDEBUG
4449 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4450 "Not all catch info was assigned to a landing pad!");
4451#endif
4452
Chris Lattner1c08c712005-01-07 07:47:53 +00004453 return true;
4454}
4455
Chris Lattner571e4342006-10-27 21:36:01 +00004456SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4457 unsigned Reg) {
4458 SDOperand Op = getValue(V);
Chris Lattner18c2f132005-01-13 20:50:02 +00004459 assert((Op.getOpcode() != ISD::CopyFromReg ||
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00004460 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
Chris Lattner18c2f132005-01-13 20:50:02 +00004461 "Copy from a reg to the same reg!");
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00004462
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00004463 MVT::ValueType SrcVT = Op.getValueType();
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004464 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4465 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4466 SmallVector<SDOperand, 8> Regs(NumRegs);
4467 SmallVector<SDOperand, 8> Chains(NumRegs);
4468
4469 // Copy the value by legal parts into sequential virtual registers.
Dan Gohman532dc2e2007-07-09 20:59:04 +00004470 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
Dan Gohman27a70be2007-07-02 16:18:06 +00004471 for (unsigned i = 0; i != NumRegs; ++i)
Dan Gohmanb6f5b002007-06-28 23:29:44 +00004472 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4473 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
Chris Lattner1c08c712005-01-07 07:47:53 +00004474}
4475
Chris Lattner068a81e2005-01-17 17:15:02 +00004476void SelectionDAGISel::
Evan Cheng15699fc2007-02-10 01:08:18 +00004477LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
Chris Lattner068a81e2005-01-17 17:15:02 +00004478 std::vector<SDOperand> &UnorderedChains) {
4479 // If this is the entry block, emit arguments.
Evan Cheng15699fc2007-02-10 01:08:18 +00004480 Function &F = *LLVMBB->getParent();
Chris Lattner0afa8e32005-01-17 17:55:19 +00004481 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
Chris Lattnerbf209482005-10-30 19:42:35 +00004482 SDOperand OldRoot = SDL.DAG.getRoot();
4483 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
Chris Lattner068a81e2005-01-17 17:15:02 +00004484
Chris Lattnerbf209482005-10-30 19:42:35 +00004485 unsigned a = 0;
4486 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4487 AI != E; ++AI, ++a)
4488 if (!AI->use_empty()) {
4489 SDL.setValue(AI, Args[a]);
Evan Chengf7179bb2006-04-27 08:29:42 +00004490
Chris Lattnerbf209482005-10-30 19:42:35 +00004491 // If this argument is live outside of the entry block, insert a copy from
4492 // whereever we got it to the vreg that other BB's will reference it as.
Chris Lattner251db182007-02-25 18:40:32 +00004493 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4494 if (VMI != FuncInfo.ValueMap.end()) {
4495 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
Chris Lattnerbf209482005-10-30 19:42:35 +00004496 UnorderedChains.push_back(Copy);
4497 }
Chris Lattner0afa8e32005-01-17 17:55:19 +00004498 }
Chris Lattnerbf209482005-10-30 19:42:35 +00004499
Chris Lattnerbf209482005-10-30 19:42:35 +00004500 // Finally, if the target has anything special to do, allow it to do so.
Chris Lattner96645412006-05-16 06:10:58 +00004501 // FIXME: this should insert code into the DAG!
Chris Lattnerbf209482005-10-30 19:42:35 +00004502 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
Chris Lattner068a81e2005-01-17 17:15:02 +00004503}
4504
Duncan Sandsf4070822007-06-15 19:04:19 +00004505static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4506 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
Duncan Sandsf4070822007-06-15 19:04:19 +00004507 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
Duncan Sandscf26d7c2007-07-04 20:52:51 +00004508 if (isSelector(I)) {
Duncan Sandsf4070822007-06-15 19:04:19 +00004509 // Apply the catch info to DestBB.
4510 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4511#ifndef NDEBUG
Duncan Sands560a7372007-11-15 09:54:37 +00004512 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4513 FLI.CatchInfoFound.insert(I);
Duncan Sandsf4070822007-06-15 19:04:19 +00004514#endif
4515 }
4516}
4517
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004518/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00004519/// DAG and fixes their tailcall attribute operand.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004520static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4521 TargetLowering& TLI) {
4522 SDNode * Ret = NULL;
4523 SDOperand Terminator = DAG.getRoot();
4524
4525 // Find RET node.
4526 if (Terminator.getOpcode() == ISD::RET) {
4527 Ret = Terminator.Val;
4528 }
4529
4530 // Fix tail call attribute of CALL nodes.
4531 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4532 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4533 if (BI->getOpcode() == ISD::CALL) {
4534 SDOperand OpRet(Ret, 0);
4535 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4536 bool isMarkedTailCall =
4537 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4538 // If CALL node has tail call attribute set to true and the call is not
4539 // eligible (no RET or the target rejects) the attribute is fixed to
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00004540 // false. The TargetLowering::IsEligibleForTailCallOptimization function
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004541 // must correctly identify tail call optimizable calls.
4542 if (isMarkedTailCall &&
4543 (Ret==NULL ||
4544 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4545 SmallVector<SDOperand, 32> Ops;
4546 unsigned idx=0;
4547 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4548 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4549 if (idx!=3)
4550 Ops.push_back(*I);
4551 else
4552 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4553 }
4554 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4555 }
4556 }
4557 }
4558}
4559
Chris Lattner1c08c712005-01-07 07:47:53 +00004560void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4561 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
Nate Begemanf15485a2006-03-27 01:32:24 +00004562 FunctionLoweringInfo &FuncInfo) {
Gordon Henriksence224772008-01-07 01:30:38 +00004563 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
Chris Lattnerddb870b2005-01-13 17:59:43 +00004564
4565 std::vector<SDOperand> UnorderedChains;
Misha Brukmanedf128a2005-04-21 22:36:52 +00004566
Chris Lattnerbf209482005-10-30 19:42:35 +00004567 // Lower any arguments needed in this block if this is the entry block.
Dan Gohmanecb7a772007-03-22 16:38:57 +00004568 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
Chris Lattnerbf209482005-10-30 19:42:35 +00004569 LowerArguments(LLVMBB, SDL, UnorderedChains);
Chris Lattner1c08c712005-01-07 07:47:53 +00004570
4571 BB = FuncInfo.MBBMap[LLVMBB];
4572 SDL.setCurrentBasicBlock(BB);
4573
Duncan Sandsf4070822007-06-15 19:04:19 +00004574 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Duncan Sands9fac0b52007-06-06 10:05:18 +00004575
Duncan Sandsf4070822007-06-15 19:04:19 +00004576 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4577 // Add a label to mark the beginning of the landing pad. Deletion of the
4578 // landing pad can thus be detected via the MachineModuleInfo.
4579 unsigned LabelID = MMI->addLandingPad(BB);
4580 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
Evan Chengbb81d972008-01-31 09:59:15 +00004581 DAG.getConstant(LabelID, MVT::i32),
4582 DAG.getConstant(1, MVT::i32)));
Duncan Sandsf4070822007-06-15 19:04:19 +00004583
Evan Chenge47c3332007-06-27 18:45:32 +00004584 // Mark exception register as live in.
4585 unsigned Reg = TLI.getExceptionAddressRegister();
4586 if (Reg) BB->addLiveIn(Reg);
4587
4588 // Mark exception selector register as live in.
4589 Reg = TLI.getExceptionSelectorRegister();
4590 if (Reg) BB->addLiveIn(Reg);
4591
Duncan Sandsf4070822007-06-15 19:04:19 +00004592 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4593 // function and list of typeids logically belong to the invoke (or, if you
4594 // like, the basic block containing the invoke), and need to be associated
4595 // with it in the dwarf exception handling tables. Currently however the
Duncan Sandscf26d7c2007-07-04 20:52:51 +00004596 // information is provided by an intrinsic (eh.selector) that can be moved
4597 // to unexpected places by the optimizers: if the unwind edge is critical,
4598 // then breaking it can result in the intrinsics being in the successor of
4599 // the landing pad, not the landing pad itself. This results in exceptions
4600 // not being caught because no typeids are associated with the invoke.
4601 // This may not be the only way things can go wrong, but it is the only way
4602 // we try to work around for the moment.
Duncan Sandsf4070822007-06-15 19:04:19 +00004603 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4604
4605 if (Br && Br->isUnconditional()) { // Critical edge?
4606 BasicBlock::iterator I, E;
4607 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
Duncan Sandscf26d7c2007-07-04 20:52:51 +00004608 if (isSelector(I))
Duncan Sandsf4070822007-06-15 19:04:19 +00004609 break;
4610
4611 if (I == E)
4612 // No catch info found - try to extract some from the successor.
4613 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
Duncan Sands9fac0b52007-06-06 10:05:18 +00004614 }
4615 }
4616
Chris Lattner1c08c712005-01-07 07:47:53 +00004617 // Lower all of the non-terminator instructions.
4618 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4619 I != E; ++I)
4620 SDL.visit(*I);
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00004621
Chris Lattner1c08c712005-01-07 07:47:53 +00004622 // Ensure that all instructions which are used outside of their defining
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00004623 // blocks are available as virtual registers. Invoke is handled elsewhere.
Chris Lattner1c08c712005-01-07 07:47:53 +00004624 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00004625 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
Chris Lattner9f24ad72007-02-04 01:35:11 +00004626 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
Chris Lattner1c08c712005-01-07 07:47:53 +00004627 if (VMI != FuncInfo.ValueMap.end())
Chris Lattnerddb870b2005-01-13 17:59:43 +00004628 UnorderedChains.push_back(
Chris Lattner571e4342006-10-27 21:36:01 +00004629 SDL.CopyValueToVirtualRegister(I, VMI->second));
Chris Lattner1c08c712005-01-07 07:47:53 +00004630 }
4631
4632 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4633 // ensure constants are generated when needed. Remember the virtual registers
4634 // that need to be added to the Machine PHI nodes as input. We cannot just
4635 // directly add them, because expansion might result in multiple MBB's for one
4636 // BB. As such, the start of the BB might correspond to a different MBB than
4637 // the end.
Misha Brukmanedf128a2005-04-21 22:36:52 +00004638 //
Chris Lattner8c494ab2006-10-27 23:50:33 +00004639 TerminatorInst *TI = LLVMBB->getTerminator();
Chris Lattner1c08c712005-01-07 07:47:53 +00004640
4641 // Emit constants only once even if used by multiple PHI nodes.
4642 std::map<Constant*, unsigned> ConstantsOut;
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004643
Chris Lattner8c494ab2006-10-27 23:50:33 +00004644 // Vector bool would be better, but vector<bool> is really slow.
4645 std::vector<unsigned char> SuccsHandled;
4646 if (TI->getNumSuccessors())
4647 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4648
Dan Gohman532dc2e2007-07-09 20:59:04 +00004649 // Check successor nodes' PHI nodes that expect a constant to be available
4650 // from this block.
Chris Lattner1c08c712005-01-07 07:47:53 +00004651 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4652 BasicBlock *SuccBB = TI->getSuccessor(succ);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004653 if (!isa<PHINode>(SuccBB->begin())) continue;
Chris Lattner8c494ab2006-10-27 23:50:33 +00004654 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004655
Chris Lattner8c494ab2006-10-27 23:50:33 +00004656 // If this terminator has multiple identical successors (common for
4657 // switches), only handle each succ once.
4658 unsigned SuccMBBNo = SuccMBB->getNumber();
4659 if (SuccsHandled[SuccMBBNo]) continue;
4660 SuccsHandled[SuccMBBNo] = true;
4661
4662 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
Chris Lattner1c08c712005-01-07 07:47:53 +00004663 PHINode *PN;
4664
4665 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4666 // nodes and Machine PHI nodes, but the incoming operands have not been
4667 // emitted yet.
4668 for (BasicBlock::iterator I = SuccBB->begin();
Chris Lattner8c494ab2006-10-27 23:50:33 +00004669 (PN = dyn_cast<PHINode>(I)); ++I) {
4670 // Ignore dead phi's.
4671 if (PN->use_empty()) continue;
4672
4673 unsigned Reg;
4674 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
Chris Lattner3f7927c2006-11-29 01:12:32 +00004675
Chris Lattner8c494ab2006-10-27 23:50:33 +00004676 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4677 unsigned &RegOut = ConstantsOut[C];
4678 if (RegOut == 0) {
4679 RegOut = FuncInfo.CreateRegForValue(C);
4680 UnorderedChains.push_back(
4681 SDL.CopyValueToVirtualRegister(C, RegOut));
Chris Lattner1c08c712005-01-07 07:47:53 +00004682 }
Chris Lattner8c494ab2006-10-27 23:50:33 +00004683 Reg = RegOut;
4684 } else {
4685 Reg = FuncInfo.ValueMap[PHIOp];
4686 if (Reg == 0) {
4687 assert(isa<AllocaInst>(PHIOp) &&
4688 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4689 "Didn't codegen value into a register!??");
4690 Reg = FuncInfo.CreateRegForValue(PHIOp);
4691 UnorderedChains.push_back(
4692 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
Chris Lattner7e021512006-03-31 02:12:18 +00004693 }
Chris Lattner1c08c712005-01-07 07:47:53 +00004694 }
Chris Lattner8c494ab2006-10-27 23:50:33 +00004695
4696 // Remember that this register needs to added to the machine PHI node as
4697 // the input for this MBB.
4698 MVT::ValueType VT = TLI.getValueType(PN->getType());
Dan Gohman7f321562007-06-25 16:23:39 +00004699 unsigned NumRegisters = TLI.getNumRegisters(VT);
Dan Gohmanb9f10192007-06-21 14:42:22 +00004700 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
Chris Lattner8c494ab2006-10-27 23:50:33 +00004701 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4702 }
Chris Lattner1c08c712005-01-07 07:47:53 +00004703 }
4704 ConstantsOut.clear();
4705
Chris Lattnerddb870b2005-01-13 17:59:43 +00004706 // Turn all of the unordered chains into one factored node.
Chris Lattner5a6c6d92005-01-13 19:53:14 +00004707 if (!UnorderedChains.empty()) {
Chris Lattner7436b572005-11-09 05:03:03 +00004708 SDOperand Root = SDL.getRoot();
4709 if (Root.getOpcode() != ISD::EntryToken) {
4710 unsigned i = 0, e = UnorderedChains.size();
4711 for (; i != e; ++i) {
4712 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4713 if (UnorderedChains[i].Val->getOperand(0) == Root)
4714 break; // Don't add the root if we already indirectly depend on it.
4715 }
4716
4717 if (i == e)
4718 UnorderedChains.push_back(Root);
4719 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00004720 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4721 &UnorderedChains[0], UnorderedChains.size()));
Chris Lattnerddb870b2005-01-13 17:59:43 +00004722 }
4723
Chris Lattner1c08c712005-01-07 07:47:53 +00004724 // Lower the terminator after the copies are emitted.
Duncan Sandsf19f6bb2007-06-13 05:51:31 +00004725 SDL.visit(*LLVMBB->getTerminator());
Chris Lattnera651cf62005-01-17 19:43:36 +00004726
Nate Begemanf15485a2006-03-27 01:32:24 +00004727 // Copy over any CaseBlock records that may now exist due to SwitchInst
Nate Begeman37efe672006-04-22 18:53:45 +00004728 // lowering, as well as any jump table information.
Nate Begemanf15485a2006-03-27 01:32:24 +00004729 SwitchCases.clear();
4730 SwitchCases = SDL.SwitchCases;
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00004731 JTCases.clear();
4732 JTCases = SDL.JTCases;
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004733 BitTestCases.clear();
4734 BitTestCases = SDL.BitTestCases;
4735
Chris Lattnera651cf62005-01-17 19:43:36 +00004736 // Make sure the root of the DAG is up-to-date.
4737 DAG.setRoot(SDL.getRoot());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00004738
4739 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4740 // with correct tailcall attribute so that the target can rely on the tailcall
4741 // attribute indicating whether the call is really eligible for tail call
4742 // optimization.
4743 CheckDAGForTailCallsAndFixThem(DAG, TLI);
Chris Lattner1c08c712005-01-07 07:47:53 +00004744}
4745
Nate Begemanf15485a2006-03-27 01:32:24 +00004746void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
Dan Gohman417e11b2007-10-08 15:12:17 +00004747 DOUT << "Lowered selection DAG:\n";
4748 DEBUG(DAG.dump());
4749
Chris Lattneraf21d552005-10-10 16:47:10 +00004750 // Run the DAG combiner in pre-legalize mode.
Dan Gohman5f43f922007-08-27 16:26:13 +00004751 DAG.Combine(false, *AA);
Nate Begeman2300f552005-09-07 00:15:36 +00004752
Dan Gohman417e11b2007-10-08 15:12:17 +00004753 DOUT << "Optimized lowered selection DAG:\n";
Chris Lattner1c08c712005-01-07 07:47:53 +00004754 DEBUG(DAG.dump());
Nate Begemanf15485a2006-03-27 01:32:24 +00004755
Chris Lattner1c08c712005-01-07 07:47:53 +00004756 // Second step, hack on the DAG until it only uses operations and types that
4757 // the target supports.
Chris Lattner01d029b2007-10-15 06:10:22 +00004758#if 0 // Enable this some day.
4759 DAG.LegalizeTypes();
4760 // Someday even later, enable a dag combine pass here.
4761#endif
Chris Lattnerac9dc082005-01-23 04:36:26 +00004762 DAG.Legalize();
Nate Begemanf15485a2006-03-27 01:32:24 +00004763
Bill Wendling832171c2006-12-07 20:04:42 +00004764 DOUT << "Legalized selection DAG:\n";
Chris Lattner1c08c712005-01-07 07:47:53 +00004765 DEBUG(DAG.dump());
Nate Begemanf15485a2006-03-27 01:32:24 +00004766
Chris Lattneraf21d552005-10-10 16:47:10 +00004767 // Run the DAG combiner in post-legalize mode.
Dan Gohman5f43f922007-08-27 16:26:13 +00004768 DAG.Combine(true, *AA);
Nate Begeman2300f552005-09-07 00:15:36 +00004769
Dan Gohman417e11b2007-10-08 15:12:17 +00004770 DOUT << "Optimized legalized selection DAG:\n";
4771 DEBUG(DAG.dump());
4772
Evan Chenga9c20912006-01-21 02:32:06 +00004773 if (ViewISelDAGs) DAG.viewGraph();
Evan Cheng552c4a82006-04-28 02:09:19 +00004774
Chris Lattnera33ef482005-03-30 01:10:47 +00004775 // Third, instruction select all of the operations to machine code, adding the
4776 // code to the MachineBasicBlock.
Chris Lattner1c08c712005-01-07 07:47:53 +00004777 InstructionSelectBasicBlock(DAG);
Nate Begemanf15485a2006-03-27 01:32:24 +00004778
Bill Wendling832171c2006-12-07 20:04:42 +00004779 DOUT << "Selected machine code:\n";
Chris Lattner1c08c712005-01-07 07:47:53 +00004780 DEBUG(BB->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +00004781}
Chris Lattner1c08c712005-01-07 07:47:53 +00004782
Nate Begemanf15485a2006-03-27 01:32:24 +00004783void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4784 FunctionLoweringInfo &FuncInfo) {
4785 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4786 {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00004787 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
Nate Begemanf15485a2006-03-27 01:32:24 +00004788 CurDAG = &DAG;
4789
4790 // First step, lower LLVM code to some DAG. This DAG may use operations and
4791 // types that are not supported by the target.
4792 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4793
4794 // Second step, emit the lowered DAG as machine code.
4795 CodeGenAndEmitDAG(DAG);
4796 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004797
4798 DOUT << "Total amount of phi nodes to update: "
4799 << PHINodesToUpdate.size() << "\n";
4800 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4801 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4802 << ", " << PHINodesToUpdate[i].second << ")\n";);
Nate Begemanf15485a2006-03-27 01:32:24 +00004803
Chris Lattnera33ef482005-03-30 01:10:47 +00004804 // Next, now that we know what the last MBB the LLVM BB expanded is, update
Chris Lattner1c08c712005-01-07 07:47:53 +00004805 // PHI nodes in successors.
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004806 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
Nate Begemanf15485a2006-03-27 01:32:24 +00004807 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4808 MachineInstr *PHI = PHINodesToUpdate[i].first;
4809 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4810 "This is not a machine PHI node that we are updating!");
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00004811 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4812 false));
4813 PHI->addOperand(MachineOperand::CreateMBB(BB));
Nate Begemanf15485a2006-03-27 01:32:24 +00004814 }
4815 return;
Chris Lattner1c08c712005-01-07 07:47:53 +00004816 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004817
4818 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4819 // Lower header first, if it wasn't already lowered
4820 if (!BitTestCases[i].Emitted) {
4821 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4822 CurDAG = &HSDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00004823 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004824 // Set the current basic block to the mbb we wish to insert the code into
4825 BB = BitTestCases[i].Parent;
4826 HSDL.setCurrentBasicBlock(BB);
4827 // Emit the code
4828 HSDL.visitBitTestHeader(BitTestCases[i]);
4829 HSDAG.setRoot(HSDL.getRoot());
4830 CodeGenAndEmitDAG(HSDAG);
4831 }
4832
4833 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4834 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4835 CurDAG = &BSDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00004836 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004837 // Set the current basic block to the mbb we wish to insert the code into
4838 BB = BitTestCases[i].Cases[j].ThisBB;
4839 BSDL.setCurrentBasicBlock(BB);
4840 // Emit the code
4841 if (j+1 != ej)
4842 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4843 BitTestCases[i].Reg,
4844 BitTestCases[i].Cases[j]);
4845 else
4846 BSDL.visitBitTestCase(BitTestCases[i].Default,
4847 BitTestCases[i].Reg,
4848 BitTestCases[i].Cases[j]);
4849
4850
4851 BSDAG.setRoot(BSDL.getRoot());
4852 CodeGenAndEmitDAG(BSDAG);
4853 }
4854
4855 // Update PHI Nodes
4856 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4857 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4858 MachineBasicBlock *PHIBB = PHI->getParent();
4859 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4860 "This is not a machine PHI node that we are updating!");
4861 // This is "default" BB. We have two jumps to it. From "header" BB and
4862 // from last "case" BB.
4863 if (PHIBB == BitTestCases[i].Default) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00004864 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4865 false));
4866 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
4867 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4868 false));
4869 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
4870 back().ThisBB));
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004871 }
4872 // One of "cases" BB.
4873 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4874 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4875 if (cBB->succ_end() !=
4876 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00004877 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4878 false));
4879 PHI->addOperand(MachineOperand::CreateMBB(cBB));
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004880 }
4881 }
4882 }
4883 }
4884
Nate Begeman9453eea2006-04-23 06:26:20 +00004885 // If the JumpTable record is filled in, then we need to emit a jump table.
4886 // Updating the PHI nodes is tricky in this case, since we need to determine
4887 // whether the PHI is a successor of the range check MBB or the jump table MBB
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00004888 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4889 // Lower header first, if it wasn't already lowered
4890 if (!JTCases[i].first.Emitted) {
4891 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4892 CurDAG = &HSDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00004893 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00004894 // Set the current basic block to the mbb we wish to insert the code into
4895 BB = JTCases[i].first.HeaderBB;
4896 HSDL.setCurrentBasicBlock(BB);
4897 // Emit the code
4898 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4899 HSDAG.setRoot(HSDL.getRoot());
4900 CodeGenAndEmitDAG(HSDAG);
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004901 }
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00004902
4903 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4904 CurDAG = &JSDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00004905 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
Nate Begeman37efe672006-04-22 18:53:45 +00004906 // Set the current basic block to the mbb we wish to insert the code into
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00004907 BB = JTCases[i].second.MBB;
4908 JSDL.setCurrentBasicBlock(BB);
Nate Begeman37efe672006-04-22 18:53:45 +00004909 // Emit the code
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00004910 JSDL.visitJumpTable(JTCases[i].second);
4911 JSDAG.setRoot(JSDL.getRoot());
4912 CodeGenAndEmitDAG(JSDAG);
4913
Nate Begeman37efe672006-04-22 18:53:45 +00004914 // Update PHI Nodes
4915 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4916 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4917 MachineBasicBlock *PHIBB = PHI->getParent();
4918 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4919 "This is not a machine PHI node that we are updating!");
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004920 // "default" BB. We can go there only from header BB.
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00004921 if (PHIBB == JTCases[i].second.Default) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00004922 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4923 false));
4924 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
Nate Begemanf4360a42006-05-03 03:48:02 +00004925 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +00004926 // JT BB. Just iterate over successors here
Nate Begemanf4360a42006-05-03 03:48:02 +00004927 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00004928 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4929 false));
4930 PHI->addOperand(MachineOperand::CreateMBB(BB));
Nate Begeman37efe672006-04-22 18:53:45 +00004931 }
4932 }
Nate Begeman37efe672006-04-22 18:53:45 +00004933 }
4934
Chris Lattnerb2e806e2006-10-22 23:00:53 +00004935 // If the switch block involved a branch to one of the actual successors, we
4936 // need to update PHI nodes in that block.
4937 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4938 MachineInstr *PHI = PHINodesToUpdate[i].first;
4939 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4940 "This is not a machine PHI node that we are updating!");
4941 if (BB->isSuccessor(PHI->getParent())) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00004942 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4943 false));
4944 PHI->addOperand(MachineOperand::CreateMBB(BB));
Chris Lattnerb2e806e2006-10-22 23:00:53 +00004945 }
4946 }
4947
Nate Begemanf15485a2006-03-27 01:32:24 +00004948 // If we generated any switch lowering information, build and codegen any
4949 // additional DAGs necessary.
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004950 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
Jim Laskey44c3b9f2007-01-26 21:22:28 +00004951 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
Nate Begemanf15485a2006-03-27 01:32:24 +00004952 CurDAG = &SDAG;
Gordon Henriksence224772008-01-07 01:30:38 +00004953 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004954
Nate Begemanf15485a2006-03-27 01:32:24 +00004955 // Set the current basic block to the mbb we wish to insert the code into
4956 BB = SwitchCases[i].ThisBB;
4957 SDL.setCurrentBasicBlock(BB);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004958
Nate Begemanf15485a2006-03-27 01:32:24 +00004959 // Emit the code
4960 SDL.visitSwitchCase(SwitchCases[i]);
4961 SDAG.setRoot(SDL.getRoot());
4962 CodeGenAndEmitDAG(SDAG);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004963
4964 // Handle any PHI nodes in successors of this chunk, as if we were coming
4965 // from the original BB before switch expansion. Note that PHI nodes can
4966 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4967 // handle them the right number of times.
Chris Lattner57ab6592006-10-24 17:57:59 +00004968 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004969 for (MachineBasicBlock::iterator Phi = BB->begin();
4970 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4971 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4972 for (unsigned pn = 0; ; ++pn) {
4973 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4974 if (PHINodesToUpdate[pn].first == Phi) {
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00004975 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
4976 second, false));
4977 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004978 break;
4979 }
4980 }
Nate Begemanf15485a2006-03-27 01:32:24 +00004981 }
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004982
4983 // Don't process RHS if same block as LHS.
Chris Lattner57ab6592006-10-24 17:57:59 +00004984 if (BB == SwitchCases[i].FalseBB)
4985 SwitchCases[i].FalseBB = 0;
Chris Lattnerd5e93c02006-09-07 01:59:34 +00004986
4987 // If we haven't handled the RHS, do so now. Otherwise, we're done.
Chris Lattner24525952006-10-24 18:07:37 +00004988 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
Chris Lattner57ab6592006-10-24 17:57:59 +00004989 SwitchCases[i].FalseBB = 0;
Nate Begemanf15485a2006-03-27 01:32:24 +00004990 }
Chris Lattner57ab6592006-10-24 17:57:59 +00004991 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
Chris Lattnera33ef482005-03-30 01:10:47 +00004992 }
Chris Lattner1c08c712005-01-07 07:47:53 +00004993}
Evan Chenga9c20912006-01-21 02:32:06 +00004994
Jim Laskey13ec7022006-08-01 14:21:23 +00004995
Evan Chenga9c20912006-01-21 02:32:06 +00004996//===----------------------------------------------------------------------===//
4997/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4998/// target node in the graph.
4999void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5000 if (ViewSchedDAGs) DAG.viewGraph();
Evan Cheng4ef10862006-01-23 07:01:07 +00005001
Jim Laskeyeb577ba2006-08-02 12:30:23 +00005002 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
Jim Laskey13ec7022006-08-01 14:21:23 +00005003
5004 if (!Ctor) {
Jim Laskeyeb577ba2006-08-02 12:30:23 +00005005 Ctor = ISHeuristic;
Jim Laskey9373beb2006-08-01 19:14:14 +00005006 RegisterScheduler::setDefault(Ctor);
Evan Cheng4ef10862006-01-23 07:01:07 +00005007 }
Jim Laskey13ec7022006-08-01 14:21:23 +00005008
Jim Laskey9ff542f2006-08-01 18:29:48 +00005009 ScheduleDAG *SL = Ctor(this, &DAG, BB);
Chris Lattnera3818e62006-01-21 19:12:11 +00005010 BB = SL->Run();
Dan Gohman3e1a7ae2007-08-28 20:32:58 +00005011
5012 if (ViewSUnitDAGs) SL->viewGraph();
5013
Evan Chengcccf1232006-02-04 06:49:00 +00005014 delete SL;
Evan Chenga9c20912006-01-21 02:32:06 +00005015}
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005016
Chris Lattner03fc53c2006-03-06 00:22:00 +00005017
Jim Laskey9ff542f2006-08-01 18:29:48 +00005018HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5019 return new HazardRecognizer();
5020}
5021
Chris Lattner75548062006-10-11 03:58:02 +00005022//===----------------------------------------------------------------------===//
5023// Helper functions used by the generated instruction selector.
5024//===----------------------------------------------------------------------===//
5025// Calls to these methods are generated by tblgen.
5026
5027/// CheckAndMask - The isel is trying to match something like (and X, 255). If
5028/// the dag combiner simplified the 255, we still want to match. RHS is the
5029/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5030/// specified in the .td file (e.g. 255).
5031bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
Dan Gohmandc9b3d02007-07-24 23:00:27 +00005032 int64_t DesiredMaskS) const {
Chris Lattner75548062006-10-11 03:58:02 +00005033 uint64_t ActualMask = RHS->getValue();
5034 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5035
5036 // If the actual mask exactly matches, success!
5037 if (ActualMask == DesiredMask)
5038 return true;
5039
5040 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5041 if (ActualMask & ~DesiredMask)
5042 return false;
5043
5044 // Otherwise, the DAG Combiner may have proven that the value coming in is
5045 // either already zero or is not demanded. Check for known zero input bits.
5046 uint64_t NeededMask = DesiredMask & ~ActualMask;
Dan Gohmanea859be2007-06-22 14:59:07 +00005047 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
Chris Lattner75548062006-10-11 03:58:02 +00005048 return true;
5049
5050 // TODO: check to see if missing bits are just not demanded.
5051
5052 // Otherwise, this pattern doesn't match.
5053 return false;
5054}
5055
5056/// CheckOrMask - The isel is trying to match something like (or X, 255). If
5057/// the dag combiner simplified the 255, we still want to match. RHS is the
5058/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5059/// specified in the .td file (e.g. 255).
5060bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
Dan Gohmandc9b3d02007-07-24 23:00:27 +00005061 int64_t DesiredMaskS) const {
Chris Lattner75548062006-10-11 03:58:02 +00005062 uint64_t ActualMask = RHS->getValue();
5063 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5064
5065 // If the actual mask exactly matches, success!
5066 if (ActualMask == DesiredMask)
5067 return true;
5068
5069 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5070 if (ActualMask & ~DesiredMask)
5071 return false;
5072
5073 // Otherwise, the DAG Combiner may have proven that the value coming in is
5074 // either already zero or is not demanded. Check for known zero input bits.
5075 uint64_t NeededMask = DesiredMask & ~ActualMask;
5076
5077 uint64_t KnownZero, KnownOne;
Dan Gohmanea859be2007-06-22 14:59:07 +00005078 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
Chris Lattner75548062006-10-11 03:58:02 +00005079
5080 // If all the missing bits in the or are already known to be set, match!
5081 if ((NeededMask & KnownOne) == NeededMask)
5082 return true;
5083
5084 // TODO: check to see if missing bits are just not demanded.
5085
5086 // Otherwise, this pattern doesn't match.
5087 return false;
5088}
5089
Jim Laskey9ff542f2006-08-01 18:29:48 +00005090
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005091/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5092/// by tblgen. Others should not call it.
5093void SelectionDAGISel::
5094SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5095 std::vector<SDOperand> InOps;
5096 std::swap(InOps, Ops);
5097
5098 Ops.push_back(InOps[0]); // input chain.
5099 Ops.push_back(InOps[1]); // input asm string.
5100
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005101 unsigned i = 2, e = InOps.size();
5102 if (InOps[e-1].getValueType() == MVT::Flag)
5103 --e; // Don't process a flag operand if it is here.
5104
5105 while (i != e) {
5106 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5107 if ((Flags & 7) != 4 /*MEM*/) {
5108 // Just skip over this operand, copying the operands verbatim.
5109 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5110 i += (Flags >> 3) + 1;
5111 } else {
5112 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5113 // Otherwise, this is a memory operand. Ask the target to select it.
5114 std::vector<SDOperand> SelOps;
5115 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
Bill Wendling832171c2006-12-07 20:04:42 +00005116 cerr << "Could not match memory address. Inline asm failure!\n";
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005117 exit(1);
5118 }
5119
5120 // Add this to the output node.
Chris Lattner4b993b12007-04-09 00:33:58 +00005121 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Chris Lattner36d43962006-12-16 21:14:48 +00005122 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
Chris Lattner4b993b12007-04-09 00:33:58 +00005123 IntPtrTy));
Chris Lattner0e43f2b2006-02-24 02:13:54 +00005124 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5125 i += 2;
5126 }
5127 }
5128
5129 // Add the flag input back if present.
5130 if (e != InOps.size())
5131 Ops.push_back(InOps.back());
5132}
Devang Patel794fd752007-05-01 21:15:47 +00005133
Devang Patel19974732007-05-03 01:11:54 +00005134char SelectionDAGISel::ID = 0;