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gerrit-public.fairphone.software / platform / external / llvm / 0f862800821352ea9a12ebb6bc30b145d9ae6596 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 389f2ea5ff163cdbd5734bca3448ad153b7fa6b6 [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattner621c44d2009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattner978b9772010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerc4c40a92009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman1e57df32008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohmane8b391e2008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohmanb4482cf2010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengef7be082008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner1d196bc2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner541d8902010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson1636de92007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Edwin Török675d5622009-07-11 20:10:48 +0000[diff] [blame]29#include "llvm/Support/ErrorHandling.h"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]30#include "llvm/Support/MathExtras.h"
31using namespace llvm;
32
Rafael Espindola7b620af2009-02-27 13:37:18 +0000[diff] [blame]33namespace llvm {
34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
35 bool isLocal = GV->hasLocalLinkage();
36 bool isDeclaration = GV->isDeclaration();
37 // FIXME: what should we do for protected and internal visibility?
38 // For variables, is internal different from hidden?
39 bool isHidden = GV->hasHiddenVisibility();
40
41 if (reloc == Reloc::PIC_) {
42 if (isLocal || isHidden)
43 return TLSModel::LocalDynamic;
44 else
45 return TLSModel::GeneralDynamic;
46 } else {
47 if (!isDeclaration || isHidden)
48 return TLSModel::LocalExec;
49 else
50 return TLSModel::InitialExec;
51 }
52}
53}
54
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]55/// InitLibcallNames - Set default libcall names.
56///
57static void InitLibcallNames(const char **Names) {
Anton Korobeynikoveaef8152009-05-03 13:14:08 +0000[diff] [blame]58 Names[RTLIB::SHL_I16] = "__ashlhi3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]59 Names[RTLIB::SHL_I32] = "__ashlsi3";
60 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sands87833982008-07-11 16:52:29 +0000[diff] [blame]61 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikoveaef8152009-05-03 13:14:08 +0000[diff] [blame]62 Names[RTLIB::SRL_I16] = "__lshrhi3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]63 Names[RTLIB::SRL_I32] = "__lshrsi3";
64 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sands87833982008-07-11 16:52:29 +0000[diff] [blame]65 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikoveaef8152009-05-03 13:14:08 +0000[diff] [blame]66 Names[RTLIB::SRA_I16] = "__ashrhi3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]67 Names[RTLIB::SRA_I32] = "__ashrsi3";
68 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sands87833982008-07-11 16:52:29 +0000[diff] [blame]69 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov0e459b42009-11-07 17:14:39 +0000[diff] [blame]70 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikoveaef8152009-05-03 13:14:08 +0000[diff] [blame]71 Names[RTLIB::MUL_I16] = "__mulhi3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]72 Names[RTLIB::MUL_I32] = "__mulsi3";
73 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands05de150b2008-07-10 15:35:05 +0000[diff] [blame]74 Names[RTLIB::MUL_I128] = "__multi3";
Anton Korobeynikov0e459b42009-11-07 17:14:39 +0000[diff] [blame]75 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov38da80d2009-05-03 13:18:16 +0000[diff] [blame]76 Names[RTLIB::SDIV_I16] = "__divhi3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]77 Names[RTLIB::SDIV_I32] = "__divsi3";
78 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands05de150b2008-07-10 15:35:05 +0000[diff] [blame]79 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov0e459b42009-11-07 17:14:39 +0000[diff] [blame]80 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovba8652d2009-05-08 18:50:54 +0000[diff] [blame]81 Names[RTLIB::UDIV_I16] = "__udivhi3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]82 Names[RTLIB::UDIV_I32] = "__udivsi3";
83 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands05de150b2008-07-10 15:35:05 +0000[diff] [blame]84 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov0e459b42009-11-07 17:14:39 +0000[diff] [blame]85 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov38da80d2009-05-03 13:18:16 +0000[diff] [blame]86 Names[RTLIB::SREM_I16] = "__modhi3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]87 Names[RTLIB::SREM_I32] = "__modsi3";
88 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands05de150b2008-07-10 15:35:05 +0000[diff] [blame]89 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov0e459b42009-11-07 17:14:39 +0000[diff] [blame]90 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov6e8496f2009-05-03 13:19:57 +0000[diff] [blame]91 Names[RTLIB::UREM_I16] = "__umodhi3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]92 Names[RTLIB::UREM_I32] = "__umodsi3";
93 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands05de150b2008-07-10 15:35:05 +0000[diff] [blame]94 Names[RTLIB::UREM_I128] = "__umodti3";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]95 Names[RTLIB::NEG_I32] = "__negsi2";
96 Names[RTLIB::NEG_I64] = "__negdi2";
97 Names[RTLIB::ADD_F32] = "__addsf3";
98 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands37a3f472008-01-10 10:28:30 +0000[diff] [blame]99 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands37a3f472008-01-10 10:28:30 +0000[diff] [blame]103 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]105 Names[RTLIB::MUL_F32] = "__mulsf3";
106 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands37a3f472008-01-10 10:28:30 +0000[diff] [blame]107 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands37a3f472008-01-10 10:28:30 +0000[diff] [blame]111 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands37a3f472008-01-10 10:28:30 +0000[diff] [blame]115 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]116 Names[RTLIB::REM_PPCF128] = "fmodl";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]117 Names[RTLIB::POWI_F32] = "__powisf2";
118 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]119 Names[RTLIB::POWI_F80] = "__powixf2";
120 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]121 Names[RTLIB::SQRT_F32] = "sqrtf";
122 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]123 Names[RTLIB::SQRT_F80] = "sqrtl";
124 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen92b33082008-09-04 00:47:13 +0000[diff] [blame]125 Names[RTLIB::LOG_F32] = "logf";
126 Names[RTLIB::LOG_F64] = "log";
127 Names[RTLIB::LOG_F80] = "logl";
128 Names[RTLIB::LOG_PPCF128] = "logl";
129 Names[RTLIB::LOG2_F32] = "log2f";
130 Names[RTLIB::LOG2_F64] = "log2";
131 Names[RTLIB::LOG2_F80] = "log2l";
132 Names[RTLIB::LOG2_PPCF128] = "log2l";
133 Names[RTLIB::LOG10_F32] = "log10f";
134 Names[RTLIB::LOG10_F64] = "log10";
135 Names[RTLIB::LOG10_F80] = "log10l";
136 Names[RTLIB::LOG10_PPCF128] = "log10l";
137 Names[RTLIB::EXP_F32] = "expf";
138 Names[RTLIB::EXP_F64] = "exp";
139 Names[RTLIB::EXP_F80] = "expl";
140 Names[RTLIB::EXP_PPCF128] = "expl";
141 Names[RTLIB::EXP2_F32] = "exp2f";
142 Names[RTLIB::EXP2_F64] = "exp2";
143 Names[RTLIB::EXP2_F80] = "exp2l";
144 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]145 Names[RTLIB::SIN_F32] = "sinf";
146 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands37a3f472008-01-10 10:28:30 +0000[diff] [blame]147 Names[RTLIB::SIN_F80] = "sinl";
148 Names[RTLIB::SIN_PPCF128] = "sinl";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]149 Names[RTLIB::COS_F32] = "cosf";
150 Names[RTLIB::COS_F64] = "cos";
Duncan Sands37a3f472008-01-10 10:28:30 +0000[diff] [blame]151 Names[RTLIB::COS_F80] = "cosl";
152 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmanfe678632007-10-11 23:09:10 +0000[diff] [blame]153 Names[RTLIB::POW_F32] = "powf";
154 Names[RTLIB::POW_F64] = "pow";
155 Names[RTLIB::POW_F80] = "powl";
156 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohmanb2158232008-08-21 18:38:14 +0000[diff] [blame]157 Names[RTLIB::CEIL_F32] = "ceilf";
158 Names[RTLIB::CEIL_F64] = "ceil";
159 Names[RTLIB::CEIL_F80] = "ceill";
160 Names[RTLIB::CEIL_PPCF128] = "ceill";
161 Names[RTLIB::TRUNC_F32] = "truncf";
162 Names[RTLIB::TRUNC_F64] = "trunc";
163 Names[RTLIB::TRUNC_F80] = "truncl";
164 Names[RTLIB::TRUNC_PPCF128] = "truncl";
165 Names[RTLIB::RINT_F32] = "rintf";
166 Names[RTLIB::RINT_F64] = "rint";
167 Names[RTLIB::RINT_F80] = "rintl";
168 Names[RTLIB::RINT_PPCF128] = "rintl";
169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
170 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
173 Names[RTLIB::FLOOR_F32] = "floorf";
174 Names[RTLIB::FLOOR_F64] = "floor";
175 Names[RTLIB::FLOOR_F80] = "floorl";
176 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sands7e59edf2010-03-14 21:08:40 +0000[diff] [blame]177 Names[RTLIB::COPYSIGN_F32] = "copysignf";
178 Names[RTLIB::COPYSIGN_F64] = "copysign";
179 Names[RTLIB::COPYSIGN_F80] = "copysignl";
180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov899c5cf2010-03-14 18:42:24 +0000[diff] [blame]182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopesb1f11b52008-08-07 19:01:24 +0000[diff] [blame]185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovcad22102010-03-26 21:32:14 +0000[diff] [blame]189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmanec51f642008-03-10 23:03:31 +0000[diff] [blame]193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovcad22102010-03-26 21:32:14 +0000[diff] [blame]194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmanec51f642008-03-10 23:03:31 +0000[diff] [blame]198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsd27dafe2008-07-10 15:33:02 +0000[diff] [blame]199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmanec51f642008-03-10 23:03:31 +0000[diff] [blame]201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands1568af82008-06-25 20:24:48 +0000[diff] [blame]202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmanec51f642008-03-10 23:03:31 +0000[diff] [blame]204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovcad22102010-03-26 21:32:14 +0000[diff] [blame]205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmanec51f642008-03-10 23:03:31 +0000[diff] [blame]209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovcad22102010-03-26 21:32:14 +0000[diff] [blame]210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmanec51f642008-03-10 23:03:31 +0000[diff] [blame]214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmanec51f642008-03-10 23:03:31 +0000[diff] [blame]217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands1568af82008-06-25 20:24:48 +0000[diff] [blame]218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmanec51f642008-03-10 23:03:31 +0000[diff] [blame]220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands3f714972008-07-11 16:57:02 +0000[diff] [blame]223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmanc98645c2008-03-05 01:08:17 +0000[diff] [blame]229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sands25df46a2008-07-11 17:00:14 +0000[diff] [blame]235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sands25df46a2008-07-11 17:00:14 +0000[diff] [blame]239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]245 Names[RTLIB::OEQ_F32] = "__eqsf2";
246 Names[RTLIB::OEQ_F64] = "__eqdf2";
247 Names[RTLIB::UNE_F32] = "__nesf2";
248 Names[RTLIB::UNE_F64] = "__nedf2";
249 Names[RTLIB::OGE_F32] = "__gesf2";
250 Names[RTLIB::OGE_F64] = "__gedf2";
251 Names[RTLIB::OLT_F32] = "__ltsf2";
252 Names[RTLIB::OLT_F64] = "__ltdf2";
253 Names[RTLIB::OLE_F32] = "__lesf2";
254 Names[RTLIB::OLE_F64] = "__ledf2";
255 Names[RTLIB::OGT_F32] = "__gtsf2";
256 Names[RTLIB::OGT_F64] = "__gtdf2";
257 Names[RTLIB::UO_F32] = "__unordsf2";
258 Names[RTLIB::UO_F64] = "__unorddf2";
259 Names[RTLIB::O_F32] = "__unordsf2";
260 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaf4e64d62009-07-30 09:12:56 +0000[diff] [blame]261 Names[RTLIB::MEMCPY] = "memcpy";
262 Names[RTLIB::MEMMOVE] = "memmove";
263 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsf325c482009-05-22 20:36:31 +0000[diff] [blame]264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbach91571972010-06-18 21:43:38 +0000[diff] [blame]265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachdd671592010-06-18 23:03:10 +0000[diff] [blame]269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbach91571972010-06-18 21:43:38 +0000[diff] [blame]273 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
276 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
277 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
280 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
281 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
282 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
283 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
284 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
285 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
286 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
287 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
288 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
289 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
292 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
293 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
296 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]297}
298
Anton Korobeynikovcdab71f2009-08-14 20:10:52 +0000[diff] [blame]299/// InitLibcallCallingConvs - Set default libcall CallingConvs.
300///
301static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
302 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
303 CCs[i] = CallingConv::C;
304 }
305}
306
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]307/// getFPEXT - Return the FPEXT_*_* value for the given types, or
308/// UNKNOWN_LIBCALL if there is none.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]309RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]310 if (OpVT == MVT::f32) {
311 if (RetVT == MVT::f64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]312 return FPEXT_F32_F64;
313 }
Anton Korobeynikov899c5cf2010-03-14 18:42:24 +0000[diff] [blame]314
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]315 return UNKNOWN_LIBCALL;
316}
317
318/// getFPROUND - Return the FPROUND_*_* value for the given types, or
319/// UNKNOWN_LIBCALL if there is none.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]320RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]321 if (RetVT == MVT::f32) {
322 if (OpVT == MVT::f64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]323 return FPROUND_F64_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]324 if (OpVT == MVT::f80)
Bruno Cardoso Lopesb1f11b52008-08-07 19:01:24 +0000[diff] [blame]325 return FPROUND_F80_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]326 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopesb1f11b52008-08-07 19:01:24 +0000[diff] [blame]327 return FPROUND_PPCF128_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]328 } else if (RetVT == MVT::f64) {
329 if (OpVT == MVT::f80)
Bruno Cardoso Lopesb1f11b52008-08-07 19:01:24 +0000[diff] [blame]330 return FPROUND_F80_F64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]331 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopesb1f11b52008-08-07 19:01:24 +0000[diff] [blame]332 return FPROUND_PPCF128_F64;
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]333 }
Anton Korobeynikov899c5cf2010-03-14 18:42:24 +0000[diff] [blame]334
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]335 return UNKNOWN_LIBCALL;
336}
337
338/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
339/// UNKNOWN_LIBCALL if there is none.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]340RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]341 if (OpVT == MVT::f32) {
342 if (RetVT == MVT::i8)
Sanjiv Guptaa5790f92009-06-16 09:03:58 +0000[diff] [blame]343 return FPTOSINT_F32_I8;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]344 if (RetVT == MVT::i16)
Sanjiv Guptaa5790f92009-06-16 09:03:58 +0000[diff] [blame]345 return FPTOSINT_F32_I16;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]346 if (RetVT == MVT::i32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]347 return FPTOSINT_F32_I32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]348 if (RetVT == MVT::i64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]349 return FPTOSINT_F32_I64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]350 if (RetVT == MVT::i128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]351 return FPTOSINT_F32_I128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]352 } else if (OpVT == MVT::f64) {
Anton Korobeynikovcad22102010-03-26 21:32:14 +0000[diff] [blame]353 if (RetVT == MVT::i8)
354 return FPTOSINT_F64_I8;
355 if (RetVT == MVT::i16)
356 return FPTOSINT_F64_I16;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]357 if (RetVT == MVT::i32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]358 return FPTOSINT_F64_I32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]359 if (RetVT == MVT::i64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]360 return FPTOSINT_F64_I64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]361 if (RetVT == MVT::i128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]362 return FPTOSINT_F64_I128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]363 } else if (OpVT == MVT::f80) {
364 if (RetVT == MVT::i32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]365 return FPTOSINT_F80_I32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]366 if (RetVT == MVT::i64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]367 return FPTOSINT_F80_I64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]368 if (RetVT == MVT::i128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]369 return FPTOSINT_F80_I128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]370 } else if (OpVT == MVT::ppcf128) {
371 if (RetVT == MVT::i32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]372 return FPTOSINT_PPCF128_I32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::i64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]374 return FPTOSINT_PPCF128_I64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]375 if (RetVT == MVT::i128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOSINT_PPCF128_I128;
377 }
378 return UNKNOWN_LIBCALL;
379}
380
381/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
382/// UNKNOWN_LIBCALL if there is none.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]383RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]384 if (OpVT == MVT::f32) {
385 if (RetVT == MVT::i8)
Sanjiv Guptaa5790f92009-06-16 09:03:58 +0000[diff] [blame]386 return FPTOUINT_F32_I8;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]387 if (RetVT == MVT::i16)
Sanjiv Guptaa5790f92009-06-16 09:03:58 +0000[diff] [blame]388 return FPTOUINT_F32_I16;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]389 if (RetVT == MVT::i32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]390 return FPTOUINT_F32_I32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]391 if (RetVT == MVT::i64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]392 return FPTOUINT_F32_I64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]393 if (RetVT == MVT::i128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]394 return FPTOUINT_F32_I128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]395 } else if (OpVT == MVT::f64) {
Anton Korobeynikovcad22102010-03-26 21:32:14 +0000[diff] [blame]396 if (RetVT == MVT::i8)
397 return FPTOUINT_F64_I8;
398 if (RetVT == MVT::i16)
399 return FPTOUINT_F64_I16;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]400 if (RetVT == MVT::i32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]401 return FPTOUINT_F64_I32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]402 if (RetVT == MVT::i64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]403 return FPTOUINT_F64_I64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]404 if (RetVT == MVT::i128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]405 return FPTOUINT_F64_I128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]406 } else if (OpVT == MVT::f80) {
407 if (RetVT == MVT::i32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]408 return FPTOUINT_F80_I32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]409 if (RetVT == MVT::i64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]410 return FPTOUINT_F80_I64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]411 if (RetVT == MVT::i128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]412 return FPTOUINT_F80_I128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]413 } else if (OpVT == MVT::ppcf128) {
414 if (RetVT == MVT::i32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]415 return FPTOUINT_PPCF128_I32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]416 if (RetVT == MVT::i64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]417 return FPTOUINT_PPCF128_I64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]418 if (RetVT == MVT::i128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]419 return FPTOUINT_PPCF128_I128;
420 }
421 return UNKNOWN_LIBCALL;
422}
423
424/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
425/// UNKNOWN_LIBCALL if there is none.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]426RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]427 if (OpVT == MVT::i32) {
428 if (RetVT == MVT::f32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]429 return SINTTOFP_I32_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]430 else if (RetVT == MVT::f64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]431 return SINTTOFP_I32_F64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]432 else if (RetVT == MVT::f80)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]433 return SINTTOFP_I32_F80;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]434 else if (RetVT == MVT::ppcf128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]435 return SINTTOFP_I32_PPCF128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]436 } else if (OpVT == MVT::i64) {
437 if (RetVT == MVT::f32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]438 return SINTTOFP_I64_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]439 else if (RetVT == MVT::f64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]440 return SINTTOFP_I64_F64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]441 else if (RetVT == MVT::f80)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]442 return SINTTOFP_I64_F80;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]443 else if (RetVT == MVT::ppcf128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]444 return SINTTOFP_I64_PPCF128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]445 } else if (OpVT == MVT::i128) {
446 if (RetVT == MVT::f32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]447 return SINTTOFP_I128_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]448 else if (RetVT == MVT::f64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]449 return SINTTOFP_I128_F64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]450 else if (RetVT == MVT::f80)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]451 return SINTTOFP_I128_F80;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]452 else if (RetVT == MVT::ppcf128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]453 return SINTTOFP_I128_PPCF128;
454 }
455 return UNKNOWN_LIBCALL;
456}
457
458/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
459/// UNKNOWN_LIBCALL if there is none.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]460RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]461 if (OpVT == MVT::i32) {
462 if (RetVT == MVT::f32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]463 return UINTTOFP_I32_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]464 else if (RetVT == MVT::f64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]465 return UINTTOFP_I32_F64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]466 else if (RetVT == MVT::f80)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]467 return UINTTOFP_I32_F80;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]468 else if (RetVT == MVT::ppcf128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]469 return UINTTOFP_I32_PPCF128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]470 } else if (OpVT == MVT::i64) {
471 if (RetVT == MVT::f32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]472 return UINTTOFP_I64_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]473 else if (RetVT == MVT::f64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]474 return UINTTOFP_I64_F64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]475 else if (RetVT == MVT::f80)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]476 return UINTTOFP_I64_F80;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]477 else if (RetVT == MVT::ppcf128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]478 return UINTTOFP_I64_PPCF128;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]479 } else if (OpVT == MVT::i128) {
480 if (RetVT == MVT::f32)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]481 return UINTTOFP_I128_F32;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]482 else if (RetVT == MVT::f64)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]483 return UINTTOFP_I128_F64;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]484 else if (RetVT == MVT::f80)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]485 return UINTTOFP_I128_F80;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]486 else if (RetVT == MVT::ppcf128)
Duncan Sandsf68dffb2008-07-17 02:36:29 +0000[diff] [blame]487 return UINTTOFP_I128_PPCF128;
488 }
489 return UNKNOWN_LIBCALL;
490}
491
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]492/// InitCmpLibcallCCs - Set default comparison libcall CC.
493///
494static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
495 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
496 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
497 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
498 CCs[RTLIB::UNE_F32] = ISD::SETNE;
499 CCs[RTLIB::UNE_F64] = ISD::SETNE;
500 CCs[RTLIB::OGE_F32] = ISD::SETGE;
501 CCs[RTLIB::OGE_F64] = ISD::SETGE;
502 CCs[RTLIB::OLT_F32] = ISD::SETLT;
503 CCs[RTLIB::OLT_F64] = ISD::SETLT;
504 CCs[RTLIB::OLE_F32] = ISD::SETLE;
505 CCs[RTLIB::OLE_F64] = ISD::SETLE;
506 CCs[RTLIB::OGT_F32] = ISD::SETGT;
507 CCs[RTLIB::OGT_F64] = ISD::SETGT;
508 CCs[RTLIB::UO_F32] = ISD::SETNE;
509 CCs[RTLIB::UO_F64] = ISD::SETNE;
510 CCs[RTLIB::O_F32] = ISD::SETEQ;
511 CCs[RTLIB::O_F64] = ISD::SETEQ;
512}
513
Chris Lattnerc4c40a92009-07-28 03:13:23 +0000[diff] [blame]514/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanb9305c02010-04-21 01:34:56 +0000[diff] [blame]515TargetLowering::TargetLowering(const TargetMachine &tm,
516 const TargetLoweringObjectFile *tlof)
Chris Lattnerc4c40a92009-07-28 03:13:23 +0000[diff] [blame]517 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]518 // All operations default to being supported.
519 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng08c171a2008-10-14 21:26:46 +0000[diff] [blame]520 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattner3bc08502008-01-17 19:59:44 +0000[diff] [blame]521 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattner0d551f32008-01-18 19:36:20 +0000[diff] [blame]522 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng71343822008-10-15 02:05:31 +0000[diff] [blame]523 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]524
Chris Lattnerdb5f7ff2007-12-22 20:47:56 +0000[diff] [blame]525 // Set default actions for various operations.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]526 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattnerdb5f7ff2007-12-22 20:47:56 +0000[diff] [blame]527 // Default all indexed load / store to expand.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]528 for (unsigned IM = (unsigned)ISD::PRE_INC;
529 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]530 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
531 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]532 }
Chris Lattnerdb5f7ff2007-12-22 20:47:56 +0000[diff] [blame]533
534 // These operations default to expand.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]535 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]537 }
Evan Cheng8d51ab32008-03-10 19:38:10 +0000[diff] [blame]538
539 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]540 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Nate Begemane2ba64f2008-02-14 08:57:00 +0000[diff] [blame]541
542 // ConstantFP nodes default to expand. Targets can either change this to
Evan Cheng6337b552009-10-27 19:56:55 +0000[diff] [blame]543 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane2ba64f2008-02-14 08:57:00 +0000[diff] [blame]544 // to optimize expansions for certain constants.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]545 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
546 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
547 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]548
Dale Johannesenb02a1c02008-09-22 21:57:32 +0000[diff] [blame]549 // These library functions default to expand.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]550 setOperationAction(ISD::FLOG , MVT::f64, Expand);
551 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
552 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
553 setOperationAction(ISD::FEXP , MVT::f64, Expand);
554 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
555 setOperationAction(ISD::FLOG , MVT::f32, Expand);
556 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
557 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
558 setOperationAction(ISD::FEXP , MVT::f32, Expand);
559 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
Dale Johannesenb02a1c02008-09-22 21:57:32 +0000[diff] [blame]560
Chris Lattnere99bbb72008-01-15 21:58:08 +0000[diff] [blame]561 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]562 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Chris Lattnere99bbb72008-01-15 21:58:08 +0000[diff] [blame]563
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]564 IsLittleEndian = TD->isLittleEndian();
Owen Anderson35b47072009-08-13 21:58:54 +0000[diff] [blame]565 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]566 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson1636de92007-09-07 04:06:50 +0000[diff] [blame]567 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]568 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng79566822009-05-13 21:42:09 +0000[diff] [blame]569 benefitFromCodePlacementOpt = false;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]570 UseUnderscoreSetJmp = false;
571 UseUnderscoreLongJmp = false;
572 SelectIsExpensive = false;
573 IntDivIsCheap = false;
574 Pow2DivIsCheap = false;
575 StackPointerRegisterToSaveRestore = 0;
576 ExceptionPointerRegister = 0;
577 ExceptionSelectorRegister = 0;
Duncan Sands8cf4a822008-11-23 15:47:28 +0000[diff] [blame]578 BooleanContents = UndefinedBooleanContent;
Evan Chenga9d350e2010-05-19 20:19:50 +0000[diff] [blame]579 SchedPreferenceInfo = Sched::Latency;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]580 JumpBufSize = 0;
581 JumpBufAlignment = 0;
Evan Cheng45c1edb2008-02-28 00:43:03 +0000[diff] [blame]582 PrefLoopAlignment = 0;
Rafael Espindoladeaae442010-07-11 04:01:49 +0000[diff] [blame]583 MinStackArgumentAlignment = 1;
Jim Grosbachc0e1bf42010-06-23 16:07:42 +0000[diff] [blame]584 ShouldFoldAtomicFences = false;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]585
586 InitLibcallNames(LibcallRoutineNames);
587 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikovcdab71f2009-08-14 20:10:52 +0000[diff] [blame]588 InitLibcallCallingConvs(LibcallCallingConvs);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]589}
590
Chris Lattnerc4c40a92009-07-28 03:13:23 +0000[diff] [blame]591TargetLowering::~TargetLowering() {
592 delete &TLOF;
593}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]594
Mon P Wang15e34202010-02-10 23:37:45 +0000[diff] [blame]595/// canOpTrap - Returns true if the operation can trap for the value type.
596/// VT must be a legal type.
597bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
598 assert(isTypeLegal(VT));
599 switch (Op) {
600 default:
601 return false;
602 case ISD::FDIV:
603 case ISD::FREM:
604 case ISD::SDIV:
605 case ISD::UDIV:
606 case ISD::SREM:
607 case ISD::UREM:
608 return true;
609 }
610}
611
612
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]613static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner81fa5fa2010-07-05 05:36:21 +0000[diff] [blame]614 unsigned &NumIntermediates,
615 EVT &RegisterVT,
616 TargetLowering *TLI) {
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]617 // Figure out the right, legal destination reg to copy into.
618 unsigned NumElts = VT.getVectorNumElements();
619 MVT EltTy = VT.getVectorElementType();
620
621 unsigned NumVectorRegs = 1;
622
623 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
624 // could break down into LHS/RHS like LegalizeDAG does.
625 if (!isPowerOf2_32(NumElts)) {
626 NumVectorRegs = NumElts;
627 NumElts = 1;
628 }
629
630 // Divide the input until we get to a supported size. This will always
631 // end with a scalar if the target doesn't support vectors.
632 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
633 NumElts >>= 1;
634 NumVectorRegs <<= 1;
635 }
636
637 NumIntermediates = NumVectorRegs;
638
639 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
640 if (!TLI->isTypeLegal(NewVT))
641 NewVT = EltTy;
642 IntermediateVT = NewVT;
643
644 EVT DestVT = TLI->getRegisterType(NewVT);
645 RegisterVT = DestVT;
Chris Lattner062eb0c2010-07-05 05:53:14 +0000[diff] [blame]646 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]647 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]648
Chris Lattner062eb0c2010-07-05 05:53:14 +0000[diff] [blame]649 // Otherwise, promotion or legal types use the same number of registers as
650 // the vector decimated to the appropriate level.
651 return NumVectorRegs;
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]652}
653
Evan Cheng2e3c1532010-07-19 18:47:01 +0000[diff] [blame]654/// isLegalRC - Return true if the value types that can be represented by the
655/// specified register class are all legal.
656bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
657 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
658 I != E; ++I) {
659 if (isTypeLegal(*I))
660 return true;
661 }
662 return false;
663}
664
665/// hasLegalSuperRegRegClasses - Return true if the specified register class
666/// has one or more super-reg register classes that are legal.
Evan Chengfe8ff142010-07-19 22:15:08 +0000[diff] [blame]667bool
668TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
Evan Cheng2e3c1532010-07-19 18:47:01 +0000[diff] [blame]669 if (*RC->superregclasses_begin() == 0)
670 return false;
671 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
672 E = RC->superregclasses_end(); I != E; ++I) {
673 const TargetRegisterClass *RRC = *I;
674 if (isLegalRC(RRC))
675 return true;
676 }
677 return false;
678}
679
680/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng83bd3e62010-07-21 06:09:07 +0000[diff] [blame]681/// of the register class for the specified type and its associated "cost".
682std::pair<const TargetRegisterClass*, uint8_t>
683TargetLowering::findRepresentativeClass(EVT VT) const {
684 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
685 if (!RC)
686 return std::make_pair(RC, 0);
Evan Cheng2e3c1532010-07-19 18:47:01 +0000[diff] [blame]687 const TargetRegisterClass *BestRC = RC;
688 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
689 E = RC->superregclasses_end(); I != E; ++I) {
690 const TargetRegisterClass *RRC = *I;
691 if (RRC->isASubClass() || !isLegalRC(RRC))
692 continue;
693 if (!hasLegalSuperRegRegClasses(RRC))
Evan Cheng83bd3e62010-07-21 06:09:07 +0000[diff] [blame]694 return std::make_pair(RRC, 1);
Evan Cheng2e3c1532010-07-19 18:47:01 +0000[diff] [blame]695 BestRC = RRC;
696 }
Evan Cheng83bd3e62010-07-21 06:09:07 +0000[diff] [blame]697 return std::make_pair(BestRC, 1);
Evan Cheng2e3c1532010-07-19 18:47:01 +0000[diff] [blame]698}
699
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]700/// computeRegisterProperties - Once all of the register classes are added,
701/// this allows us to compute derived properties we expose.
702void TargetLowering::computeRegisterProperties() {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]703 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]704 "Too many value types for ValueTypeActions to hold!");
705
706 // Everything defaults to needing one register.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]707 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]708 NumRegistersForVT[i] = 1;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]709 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]710 }
711 // ...except isVoid, which doesn't need any registers.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]712 NumRegistersForVT[MVT::isVoid] = 0;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]713
714 // Find the largest integer register class.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]715 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]716 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]717 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]718
719 // Every integer value type larger than this largest register takes twice as
720 // many registers to represent as the previous ValueType.
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]721 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman3bab1f72009-09-23 21:02:20 +0000[diff] [blame]722 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
723 if (!ExpandedVT.isInteger())
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]724 break;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]725 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]726 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
727 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Dan Gohman3bab1f72009-09-23 21:02:20 +0000[diff] [blame]728 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]729 }
730
731 // Inspect all of the ValueType's smaller than the largest integer
732 // register to see which ones need promotion.
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]733 unsigned LegalIntReg = LargestIntReg;
734 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]735 IntReg >= (unsigned)MVT::i1; --IntReg) {
736 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]737 if (isTypeLegal(IVT)) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]738 LegalIntReg = IntReg;
739 } else {
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]740 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]741 (MVT::SimpleValueType)LegalIntReg;
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]742 ValueTypeActions.setTypeAction(IVT, Promote);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]743 }
744 }
745
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]746 // ppcf128 type is really two f64's.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]747 if (!isTypeLegal(MVT::ppcf128)) {
748 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
749 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
750 TransformToType[MVT::ppcf128] = MVT::f64;
751 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
Dale Johannesenac77b272007-10-05 20:04:43 +0000[diff] [blame]752 }
753
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]754 // Decide how to handle f64. If the target does not have native f64 support,
755 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]756 if (!isTypeLegal(MVT::f64)) {
757 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
758 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
759 TransformToType[MVT::f64] = MVT::i64;
760 ValueTypeActions.setTypeAction(MVT::f64, Expand);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]761 }
762
763 // Decide how to handle f32. If the target does not have native support for
764 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]765 if (!isTypeLegal(MVT::f32)) {
766 if (isTypeLegal(MVT::f64)) {
767 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
768 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
769 TransformToType[MVT::f32] = MVT::f64;
770 ValueTypeActions.setTypeAction(MVT::f32, Promote);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]771 } else {
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]772 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
773 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
774 TransformToType[MVT::f32] = MVT::i32;
775 ValueTypeActions.setTypeAction(MVT::f32, Expand);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]776 }
777 }
778
779 // Loop over all of the vector value types to see which need transformations.
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]780 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
781 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]782 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner81fa5fa2010-07-05 05:36:21 +0000[diff] [blame]783 if (isTypeLegal(VT)) continue;
784
785 MVT IntermediateVT;
786 EVT RegisterVT;
787 unsigned NumIntermediates;
788 NumRegistersForVT[i] =
789 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
790 RegisterVT, this);
791 RegisterTypeForVT[i] = RegisterVT;
792
793 // Determine if there is a legal wider type.
794 bool IsLegalWiderType = false;
795 EVT EltVT = VT.getVectorElementType();
796 unsigned NElts = VT.getVectorNumElements();
797 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
798 EVT SVT = (MVT::SimpleValueType)nVT;
799 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
800 SVT.getVectorNumElements() > NElts && NElts != 1) {
801 TransformToType[i] = SVT;
802 ValueTypeActions.setTypeAction(VT, Promote);
803 IsLegalWiderType = true;
804 break;
Mon P Wang26342922008-12-18 20:03:17 +0000[diff] [blame]805 }
Chris Lattner81fa5fa2010-07-05 05:36:21 +0000[diff] [blame]806 }
807 if (!IsLegalWiderType) {
808 EVT NVT = VT.getPow2VectorType();
809 if (NVT == VT) {
810 // Type is already a power of 2. The default action is to split.
811 TransformToType[i] = MVT::Other;
812 ValueTypeActions.setTypeAction(VT, Expand);
813 } else {
814 TransformToType[i] = NVT;
815 ValueTypeActions.setTypeAction(VT, Promote);
Mon P Wang26342922008-12-18 20:03:17 +0000[diff] [blame]816 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]817 }
818 }
Evan Cheng2e3c1532010-07-19 18:47:01 +0000[diff] [blame]819
820 // Determine the 'representative' register class for each value type.
821 // An representative register class is the largest (meaning one which is
822 // not a sub-register class / subreg register class) legal register class for
823 // a group of value types. For example, on i386, i8, i16, and i32
824 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengfe8ff142010-07-19 22:15:08 +0000[diff] [blame]825 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng83bd3e62010-07-21 06:09:07 +0000[diff] [blame]826 const TargetRegisterClass* RRC;
827 uint8_t Cost;
828 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
829 RepRegClassForVT[i] = RRC;
830 RepRegClassCostForVT[i] = Cost;
Evan Chengfe8ff142010-07-19 22:15:08 +0000[diff] [blame]831 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]832}
833
834const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
835 return NULL;
836}
837
Scott Michel502151f2008-03-10 15:42:14 +0000[diff] [blame]838
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]839MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson35b47072009-08-13 21:58:54 +0000[diff] [blame]840 return PointerTy.SimpleTy;
Scott Michel502151f2008-03-10 15:42:14 +0000[diff] [blame]841}
842
Sanjiv Gupta10619612009-12-28 02:40:33 +0000[diff] [blame]843MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
844 return MVT::i32; // return the default value
845}
846
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]847/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]848/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
849/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
850/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]851///
852/// This method returns the number of registers needed, and the VT for each
853/// register. It also returns the VT and quantity of the intermediate values
854/// before they are promoted/expanded.
855///
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]856unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]857 EVT &IntermediateVT,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]858 unsigned &NumIntermediates,
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]859 EVT &RegisterVT) const {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]860 // Figure out the right, legal destination reg to copy into.
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]861 unsigned NumElts = VT.getVectorNumElements();
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]862 EVT EltTy = VT.getVectorElementType();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]863
864 unsigned NumVectorRegs = 1;
865
Nate Begeman3d83c3f2007-11-27 19:28:48 +0000[diff] [blame]866 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
867 // could break down into LHS/RHS like LegalizeDAG does.
868 if (!isPowerOf2_32(NumElts)) {
869 NumVectorRegs = NumElts;
870 NumElts = 1;
871 }
872
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]873 // Divide the input until we get to a supported size. This will always
874 // end with a scalar if the target doesn't support vectors.
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]875 while (NumElts > 1 && !isTypeLegal(
876 EVT::getVectorVT(Context, EltTy, NumElts))) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]877 NumElts >>= 1;
878 NumVectorRegs <<= 1;
879 }
880
881 NumIntermediates = NumVectorRegs;
882
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]883 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]884 if (!isTypeLegal(NewVT))
885 NewVT = EltTy;
886 IntermediateVT = NewVT;
887
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]888 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]889 RegisterVT = DestVT;
Duncan Sandsec142ee2008-06-08 20:54:56 +0000[diff] [blame]890 if (DestVT.bitsLT(NewVT)) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]891 // Value is expanded, e.g. i64 -> i16.
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]892 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]893 } else {
894 // Otherwise, promotion or legal types use the same number of registers as
895 // the vector decimated to the appropriate level.
896 return NumVectorRegs;
897 }
898
899 return 1;
900}
901
Dan Gohmanb4482cf2010-07-10 09:00:22 +0000[diff] [blame]902/// Get the EVTs and ArgFlags collections that represent the legalized return
903/// type of the given function. This does not require a DAG or a return value,
904/// and is suitable for use before any DAGs for the function are constructed.
905/// TODO: Move this out of TargetLowering.cpp.
906void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
907 SmallVectorImpl<ISD::OutputArg> &Outs,
908 const TargetLowering &TLI,
909 SmallVectorImpl<uint64_t> *Offsets) {
910 SmallVector<EVT, 4> ValueVTs;
911 ComputeValueVTs(TLI, ReturnType, ValueVTs);
912 unsigned NumValues = ValueVTs.size();
913 if (NumValues == 0) return;
914 unsigned Offset = 0;
915
916 for (unsigned j = 0, f = NumValues; j != f; ++j) {
917 EVT VT = ValueVTs[j];
918 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
919
920 if (attr & Attribute::SExt)
921 ExtendKind = ISD::SIGN_EXTEND;
922 else if (attr & Attribute::ZExt)
923 ExtendKind = ISD::ZERO_EXTEND;
924
925 // FIXME: C calling convention requires the return type to be promoted to
926 // at least 32-bit. But this is not necessary for non-C calling
927 // conventions. The frontend should mark functions whose return values
928 // require promoting with signext or zeroext attributes.
929 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
930 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
931 if (VT.bitsLT(MinVT))
932 VT = MinVT;
933 }
934
935 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
936 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
937 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
938 PartVT.getTypeForEVT(ReturnType->getContext()));
939
940 // 'inreg' on function refers to return value
941 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
942 if (attr & Attribute::InReg)
943 Flags.setInReg();
944
945 // Propagate extension type if any
946 if (attr & Attribute::SExt)
947 Flags.setSExt();
948 else if (attr & Attribute::ZExt)
949 Flags.setZExt();
950
951 for (unsigned i = 0; i < NumParts; ++i) {
952 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
953 if (Offsets) {
954 Offsets->push_back(Offset);
955 Offset += PartSize;
956 }
957 }
958 }
959}
960
Evan Cheng9b5992a2008-01-24 00:22:01 +0000[diff] [blame]961/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen88945f82008-02-28 22:31:51 +0000[diff] [blame]962/// function arguments in the caller parameter area. This is the actual
963/// alignment, not its logarithm.
Evan Cheng9b5992a2008-01-24 00:22:01 +0000[diff] [blame]964unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Dale Johannesen88945f82008-02-28 22:31:51 +0000[diff] [blame]965 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng9b5992a2008-01-24 00:22:01 +0000[diff] [blame]966}
967
Chris Lattner1d196bc2010-01-25 23:26:13 +0000[diff] [blame]968/// getJumpTableEncoding - Return the entry encoding for a jump table in the
969/// current function. The returned value is a member of the
970/// MachineJumpTableInfo::JTEntryKind enum.
971unsigned TargetLowering::getJumpTableEncoding() const {
972 // In non-pic modes, just use the address of a block.
973 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
974 return MachineJumpTableInfo::EK_BlockAddress;
975
976 // In PIC mode, if the target supports a GPRel32 directive, use it.
977 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
978 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
979
980 // Otherwise, use a label difference.
981 return MachineJumpTableInfo::EK_LabelDifference32;
982}
983
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]984SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
985 SelectionDAG &DAG) const {
Chris Lattneraf706422010-01-26 06:53:37 +0000[diff] [blame]986 // If our PIC model is GP relative, use the global offset table as the base.
987 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesen24dd9a52009-02-07 00:55:49 +0000[diff] [blame]988 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Cheng6fb06762007-11-09 01:32:10 +0000[diff] [blame]989 return Table;
990}
991
Chris Lattner9f5b9c12010-01-26 05:30:30 +0000[diff] [blame]992/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
993/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
994/// MCExpr.
995const MCExpr *
Chris Lattner541d8902010-01-26 06:28:43 +0000[diff] [blame]996TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
997 unsigned JTI,MCContext &Ctx) const{
Chris Lattner978b9772010-01-26 05:58:28 +0000[diff] [blame]998 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner541d8902010-01-26 06:28:43 +0000[diff] [blame]999 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner9f5b9c12010-01-26 05:30:30 +0000[diff] [blame]1000}
1001
Dan Gohman36322c72008-10-18 02:06:02 +0000[diff] [blame]1002bool
1003TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1004 // Assume that everything is safe in static mode.
1005 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1006 return true;
1007
1008 // In dynamic-no-pic mode, assume that known defined values are safe.
1009 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1010 GA &&
1011 !GA->getGlobal()->isDeclaration() &&
Duncan Sands19d161f2009-03-07 15:45:40 +0000[diff] [blame]1012 !GA->getGlobal()->isWeakForLinker())
Dan Gohman36322c72008-10-18 02:06:02 +0000[diff] [blame]1013 return true;
1014
1015 // Otherwise assume nothing is safe.
1016 return false;
1017}
1018
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1019//===----------------------------------------------------------------------===//
1020// Optimization Methods
1021//===----------------------------------------------------------------------===//
1022
1023/// ShrinkDemandedConstant - Check to see if the specified operand of the
1024/// specified instruction is a constant integer. If so, check to see if there
1025/// are any bits set in the constant that are not demanded. If so, shrink the
1026/// constant and return true.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1027bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1028 const APInt &Demanded) {
Dale Johannesen175fdef2009-02-06 21:50:26 +0000[diff] [blame]1029 DebugLoc dl = Op.getDebugLoc();
Bill Wendlinge16c4332009-03-04 00:18:06 +0000[diff] [blame]1030
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1031 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]1032 switch (Op.getOpcode()) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1033 default: break;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1034 case ISD::XOR:
Bill Wendlinge16c4332009-03-04 00:18:06 +0000[diff] [blame]1035 case ISD::AND:
1036 case ISD::OR: {
1037 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1038 if (!C) return false;
1039
1040 if (Op.getOpcode() == ISD::XOR &&
1041 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1042 return false;
1043
1044 // if we can expand it to have all bits set, do it
1045 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1046 EVT VT = Op.getValueType();
Bill Wendlinge16c4332009-03-04 00:18:06 +0000[diff] [blame]1047 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1048 DAG.getConstant(Demanded &
1049 C->getAPIntValue(),
1050 VT));
1051 return CombineTo(Op, New);
1052 }
1053
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1054 break;
1055 }
Bill Wendlinge16c4332009-03-04 00:18:06 +0000[diff] [blame]1056 }
1057
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1058 return false;
1059}
1060
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1061/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1062/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1063/// cast, but it could be generalized for targets with other types of
1064/// implicit widening casts.
1065bool
1066TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1067 unsigned BitWidth,
1068 const APInt &Demanded,
1069 DebugLoc dl) {
1070 assert(Op.getNumOperands() == 2 &&
1071 "ShrinkDemandedOp only supports binary operators!");
1072 assert(Op.getNode()->getNumValues() == 1 &&
1073 "ShrinkDemandedOp only supports nodes with one result!");
1074
1075 // Don't do this if the node has another user, which may require the
1076 // full value.
1077 if (!Op.getNode()->hasOneUse())
1078 return false;
1079
1080 // Search for the smallest integer type with free casts to and from
1081 // Op's type. For expedience, just check power-of-2 integer types.
1082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1083 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1084 if (!isPowerOf2_32(SmallVTBits))
1085 SmallVTBits = NextPowerOf2(SmallVTBits);
1086 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]1087 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1088 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1089 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1090 // We found a type with free casts.
1091 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1092 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1093 Op.getNode()->getOperand(0)),
1094 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1095 Op.getNode()->getOperand(1)));
1096 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1097 return CombineTo(Op, Z);
1098 }
1099 }
1100 return false;
1101}
1102
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1103/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1104/// DemandedMask bits of the result of Op are ever used downstream. If we can
1105/// use this information to simplify Op, create a new simplified DAG node and
1106/// return true, returning the original and new nodes in Old and New. Otherwise,
1107/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1108/// the expression (used to simplify the caller). The KnownZero/One bits may
1109/// only be accurate for those bits in the DemandedMask.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1110bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1111 const APInt &DemandedMask,
1112 APInt &KnownZero,
1113 APInt &KnownOne,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1114 TargetLoweringOpt &TLO,
1115 unsigned Depth) const {
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1116 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman9d501bd2009-12-11 21:31:27 +0000[diff] [blame]1117 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1118 "Mask size mismatches value type size!");
1119 APInt NewMask = DemandedMask;
Dale Johannesen2dbdb0e2009-02-07 19:59:05 +0000[diff] [blame]1120 DebugLoc dl = Op.getDebugLoc();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1121
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1122 // Don't know anything.
1123 KnownZero = KnownOne = APInt(BitWidth, 0);
1124
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1125 // Other users may use these bits.
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]1126 if (!Op.getNode()->hasOneUse()) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1127 if (Depth != 0) {
1128 // If not at the root, Just compute the KnownZero/KnownOne bits to
1129 // simplify things downstream.
1130 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
1131 return false;
1132 }
1133 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1134 // just set the NewMask to all bits.
1135 NewMask = APInt::getAllOnesValue(BitWidth);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1136 } else if (DemandedMask == 0) {
1137 // Not demanding any bits from Op.
1138 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesen9bfc0172009-02-06 23:05:02 +0000[diff] [blame]1139 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1140 return false;
1141 } else if (Depth == 6) { // Limit search depth.
1142 return false;
1143 }
1144
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1145 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1146 switch (Op.getOpcode()) {
1147 case ISD::Constant:
1148 // We know all of the bits for a constant!
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1149 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1150 KnownZero = ~KnownOne & NewMask;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1151 return false; // Don't fall through, will infinitely loop.
1152 case ISD::AND:
1153 // If the RHS is a constant, check to see if the LHS would be zero without
1154 // using the bits from the RHS. Below, we use knowledge about the RHS to
1155 // simplify the LHS, here we're using information from the LHS to simplify
1156 // the RHS.
1157 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1158 APInt LHSZero, LHSOne;
1159 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1160 LHSZero, LHSOne, Depth+1);
1161 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1162 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1163 return TLO.CombineTo(Op, Op.getOperand(0));
1164 // If any of the set bits in the RHS are known zero on the LHS, shrink
1165 // the constant.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1166 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1167 return true;
1168 }
1169
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1170 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1171 KnownOne, TLO, Depth+1))
1172 return true;
1173 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1174 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1175 KnownZero2, KnownOne2, TLO, Depth+1))
1176 return true;
1177 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1178
1179 // If all of the demanded bits are known one on one side, return the other.
1180 // These bits cannot contribute to the result of the 'and'.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1181 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1182 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1183 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1184 return TLO.CombineTo(Op, Op.getOperand(1));
1185 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1186 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1187 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1188 // If the RHS is a constant, see if we can simplify it.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1189 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1190 return true;
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1191 // If the operation can be done in a smaller type, do so.
Dan Gohman50fbd4f2010-06-24 14:30:44 +0000[diff] [blame]1192 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1193 return true;
1194
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1195 // Output known-1 bits are only known if set in both the LHS & RHS.
1196 KnownOne &= KnownOne2;
1197 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1198 KnownZero |= KnownZero2;
1199 break;
1200 case ISD::OR:
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1201 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1202 KnownOne, TLO, Depth+1))
1203 return true;
1204 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1205 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1206 KnownZero2, KnownOne2, TLO, Depth+1))
1207 return true;
1208 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1209
1210 // If all of the demanded bits are known zero on one side, return the other.
1211 // These bits cannot contribute to the result of the 'or'.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1212 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1213 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1214 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1215 return TLO.CombineTo(Op, Op.getOperand(1));
1216 // If all of the potentially set bits on one side are known to be set on
1217 // the other side, just use the 'other' side.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1218 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1219 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1220 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1221 return TLO.CombineTo(Op, Op.getOperand(1));
1222 // If the RHS is a constant, see if we can simplify it.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1223 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1224 return true;
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1225 // If the operation can be done in a smaller type, do so.
Dan Gohman50fbd4f2010-06-24 14:30:44 +0000[diff] [blame]1226 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1227 return true;
1228
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1229 // Output known-0 bits are only known if clear in both the LHS & RHS.
1230 KnownZero &= KnownZero2;
1231 // Output known-1 are known to be set if set in either the LHS | RHS.
1232 KnownOne |= KnownOne2;
1233 break;
1234 case ISD::XOR:
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1235 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1236 KnownOne, TLO, Depth+1))
1237 return true;
1238 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1239 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1240 KnownOne2, TLO, Depth+1))
1241 return true;
1242 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1243
1244 // If all of the demanded bits are known zero on one side, return the other.
1245 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1246 if ((KnownZero & NewMask) == NewMask)
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1247 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1248 if ((KnownZero2 & NewMask) == NewMask)
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1249 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1250 // If the operation can be done in a smaller type, do so.
Dan Gohman50fbd4f2010-06-24 14:30:44 +0000[diff] [blame]1251 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1252 return true;
1253
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1254 // If all of the unknown bits are known to be zero on one side or the other
1255 // (but not both) turn this into an *inclusive* or.
1256 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1257 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesen175fdef2009-02-06 21:50:26 +0000[diff] [blame]1258 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1259 Op.getOperand(0),
1260 Op.getOperand(1)));
1261
1262 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1263 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1264 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1265 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1266
1267 // If all of the demanded bits on one side are known, and all of the set
1268 // bits on that side are also known to be set on the other side, turn this
1269 // into an AND, as we know the bits will be cleared.
1270 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1271 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1272 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1273 EVT VT = Op.getValueType();
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1274 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1275 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1276 Op.getOperand(0), ANDC));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1277 }
1278 }
1279
1280 // If the RHS is a constant, see if we can simplify it.
Edwin Török405b2432008-04-06 21:23:02 +0000[diff] [blame]1281 // for XOR, we prefer to force bits to 1 if they will make a -1.
1282 // if we can't force bits, try to shrink constant
1283 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1284 APInt Expanded = C->getAPIntValue() | (~NewMask);
1285 // if we can expand it to have all bits set, do it
1286 if (Expanded.isAllOnesValue()) {
1287 if (Expanded != C->getAPIntValue()) {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1288 EVT VT = Op.getValueType();
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1289 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Edwin Török405b2432008-04-06 21:23:02 +0000[diff] [blame]1290 TLO.DAG.getConstant(Expanded, VT));
1291 return TLO.CombineTo(Op, New);
1292 }
1293 // if it already has all the bits set, nothing to change
1294 // but don't shrink either!
1295 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1296 return true;
1297 }
1298 }
1299
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1300 KnownZero = KnownZeroOut;
1301 KnownOne = KnownOneOut;
1302 break;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1303 case ISD::SELECT:
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1304 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1305 KnownOne, TLO, Depth+1))
1306 return true;
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1307 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1308 KnownOne2, TLO, Depth+1))
1309 return true;
1310 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1311 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1312
1313 // If the operands are constants, see if we can simplify them.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1314 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1315 return true;
1316
1317 // Only known if known in both the LHS and RHS.
1318 KnownOne &= KnownOne2;
1319 KnownZero &= KnownZero2;
1320 break;
1321 case ISD::SELECT_CC:
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1322 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1323 KnownOne, TLO, Depth+1))
1324 return true;
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1325 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1326 KnownOne2, TLO, Depth+1))
1327 return true;
1328 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1329 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1330
1331 // If the operands are constants, see if we can simplify them.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1332 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1333 return true;
1334
1335 // Only known if known in both the LHS and RHS.
1336 KnownOne &= KnownOne2;
1337 KnownZero &= KnownZero2;
1338 break;
1339 case ISD::SHL:
1340 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]1341 unsigned ShAmt = SA->getZExtValue();
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1342 SDValue InOp = Op.getOperand(0);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1343
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1344 // If the shift count is an invalid immediate, don't do anything.
1345 if (ShAmt >= BitWidth)
1346 break;
1347
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1348 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1349 // single shift. We can do this if the bottom bits (which are shifted
1350 // out) are never demanded.
1351 if (InOp.getOpcode() == ISD::SRL &&
1352 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1353 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]1354 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1355 unsigned Opc = ISD::SHL;
1356 int Diff = ShAmt-C1;
1357 if (Diff < 0) {
1358 Diff = -Diff;
1359 Opc = ISD::SRL;
1360 }
1361
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1362 SDValue NewSA =
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1363 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1364 EVT VT = Op.getValueType();
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1365 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1366 InOp.getOperand(0), NewSA));
1367 }
1368 }
1369
Dan Gohmanee105e22010-07-23 18:03:30 +0000[diff] [blame]1370 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1371 KnownZero, KnownOne, TLO, Depth+1))
1372 return true;
Dan Gohmanee105e22010-07-23 18:03:30 +0000[diff] [blame]1373
1374 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1375 // are not demanded. This will likely allow the anyext to be folded away.
1376 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1377 SDValue InnerOp = InOp.getNode()->getOperand(0);
1378 EVT InnerVT = InnerOp.getValueType();
1379 if ((APInt::getHighBitsSet(BitWidth,
1380 BitWidth - InnerVT.getSizeInBits()) &
1381 DemandedMask) == 0 &&
1382 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1383 SDValue NarrowShl =
1384 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1385 TLO.DAG.getConstant(ShAmt, InnerVT));
1386 return
1387 TLO.CombineTo(Op,
1388 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1389 NarrowShl));
1390 }
1391 }
1392
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]1393 KnownZero <<= SA->getZExtValue();
1394 KnownOne <<= SA->getZExtValue();
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1395 // low bits known zero.
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]1396 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1397 }
1398 break;
1399 case ISD::SRL:
1400 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1401 EVT VT = Op.getValueType();
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]1402 unsigned ShAmt = SA->getZExtValue();
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]1403 unsigned VTSize = VT.getSizeInBits();
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1404 SDValue InOp = Op.getOperand(0);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1405
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1406 // If the shift count is an invalid immediate, don't do anything.
1407 if (ShAmt >= BitWidth)
1408 break;
1409
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1410 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1411 // single shift. We can do this if the top bits (which are shifted out)
1412 // are never demanded.
1413 if (InOp.getOpcode() == ISD::SHL &&
1414 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1415 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]1416 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1417 unsigned Opc = ISD::SRL;
1418 int Diff = ShAmt-C1;
1419 if (Diff < 0) {
1420 Diff = -Diff;
1421 Opc = ISD::SHL;
1422 }
1423
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1424 SDValue NewSA =
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1425 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1426 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1427 InOp.getOperand(0), NewSA));
1428 }
1429 }
1430
1431 // Compute the new bits that are at the top now.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1432 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1433 KnownZero, KnownOne, TLO, Depth+1))
1434 return true;
1435 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1436 KnownZero = KnownZero.lshr(ShAmt);
1437 KnownOne = KnownOne.lshr(ShAmt);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1438
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1439 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1440 KnownZero |= HighBits; // High bits known zero.
1441 }
1442 break;
1443 case ISD::SRA:
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]1444 // If this is an arithmetic shift right and only the low-bit is set, we can
1445 // always convert this into a logical shr, even if the shift amount is
1446 // variable. The low bit of the shift cannot be an input sign bit unless
1447 // the shift amount is >= the size of the datatype, which is undefined.
1448 if (DemandedMask == 1)
Evan Cheng3cbcbbb2010-04-17 06:13:15 +0000[diff] [blame]1449 return TLO.CombineTo(Op,
1450 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1451 Op.getOperand(0), Op.getOperand(1)));
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]1452
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1453 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1454 EVT VT = Op.getValueType();
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]1455 unsigned ShAmt = SA->getZExtValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1456
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1457 // If the shift count is an invalid immediate, don't do anything.
1458 if (ShAmt >= BitWidth)
1459 break;
1460
1461 APInt InDemandedMask = (NewMask << ShAmt);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1462
1463 // If any of the demanded bits are produced by the sign extension, we also
1464 // demand the input sign bit.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1465 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1466 if (HighBits.intersects(NewMask))
Dan Gohman9d501bd2009-12-11 21:31:27 +0000[diff] [blame]1467 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1468
1469 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1470 KnownZero, KnownOne, TLO, Depth+1))
1471 return true;
1472 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1473 KnownZero = KnownZero.lshr(ShAmt);
1474 KnownOne = KnownOne.lshr(ShAmt);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1475
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1476 // Handle the sign bit, adjusted to where it is now in the mask.
1477 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1478
1479 // If the input sign bit is known to be zero, or if none of the top bits
1480 // are demanded, turn this into an unsigned shift right.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1481 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1482 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1483 Op.getOperand(0),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1484 Op.getOperand(1)));
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1485 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1486 KnownOne |= HighBits;
1487 }
1488 }
1489 break;
1490 case ISD::SIGN_EXTEND_INREG: {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1491 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1492
1493 // Sign extension. Compute the demanded bits in the result that are not
1494 // present in the input.
Dan Gohman7196cb12010-01-09 02:13:55 +0000[diff] [blame]1495 APInt NewBits =
1496 APInt::getHighBitsSet(BitWidth,
1497 BitWidth - EVT.getScalarType().getSizeInBits()) &
1498 NewMask;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1499
1500 // If none of the extended bits are demanded, eliminate the sextinreg.
1501 if (NewBits == 0)
1502 return TLO.CombineTo(Op, Op.getOperand(0));
1503
Dan Gohman7196cb12010-01-09 02:13:55 +0000[diff] [blame]1504 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1505 InSignBit.zext(BitWidth);
Dan Gohman7196cb12010-01-09 02:13:55 +0000[diff] [blame]1506 APInt InputDemandedBits =
1507 APInt::getLowBitsSet(BitWidth,
1508 EVT.getScalarType().getSizeInBits()) &
1509 NewMask;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1510
1511 // Since the sign extended bits are demanded, we know that the sign
1512 // bit is demanded.
1513 InputDemandedBits |= InSignBit;
1514
1515 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1516 KnownZero, KnownOne, TLO, Depth+1))
1517 return true;
1518 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1519
1520 // If the sign bit of the input is known set or clear, then we know the
1521 // top bits of the result.
1522
1523 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1524 if (KnownZero.intersects(InSignBit))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1525 return TLO.CombineTo(Op,
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1526 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1527
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1528 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1529 KnownOne |= NewBits;
1530 KnownZero &= ~NewBits;
1531 } else { // Input sign bit unknown
1532 KnownZero &= ~NewBits;
1533 KnownOne &= ~NewBits;
1534 }
1535 break;
1536 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1537 case ISD::ZERO_EXTEND: {
Dan Gohman7196cb12010-01-09 02:13:55 +0000[diff] [blame]1538 unsigned OperandBitWidth =
1539 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1540 APInt InMask = NewMask;
1541 InMask.trunc(OperandBitWidth);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1542
1543 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1544 APInt NewBits =
1545 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1546 if (!NewBits.intersects(NewMask))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1547 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1548 Op.getValueType(),
1549 Op.getOperand(0)));
1550
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1551 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1552 KnownZero, KnownOne, TLO, Depth+1))
1553 return true;
1554 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1555 KnownZero.zext(BitWidth);
1556 KnownOne.zext(BitWidth);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1557 KnownZero |= NewBits;
1558 break;
1559 }
1560 case ISD::SIGN_EXTEND: {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1561 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohman7196cb12010-01-09 02:13:55 +0000[diff] [blame]1562 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1563 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman343b4d92008-03-11 21:29:43 +0000[diff] [blame]1564 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1565 APInt NewBits = ~InMask & NewMask;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1566
1567 // If none of the top bits are demanded, convert this into an any_extend.
1568 if (NewBits == 0)
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1569 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1570 Op.getValueType(),
1571 Op.getOperand(0)));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1572
1573 // Since some of the sign extended bits are demanded, we know that the sign
1574 // bit is demanded.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1575 APInt InDemandedBits = InMask & NewMask;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1576 InDemandedBits |= InSignBit;
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1577 InDemandedBits.trunc(InBits);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1578
1579 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1580 KnownOne, TLO, Depth+1))
1581 return true;
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1582 KnownZero.zext(BitWidth);
1583 KnownOne.zext(BitWidth);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1584
1585 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1586 if (KnownZero.intersects(InSignBit))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1587 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1588 Op.getValueType(),
1589 Op.getOperand(0)));
1590
1591 // If the sign bit is known one, the top bits match.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1592 if (KnownOne.intersects(InSignBit)) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1593 KnownOne |= NewBits;
1594 KnownZero &= ~NewBits;
1595 } else { // Otherwise, top bits aren't known.
1596 KnownOne &= ~NewBits;
1597 KnownZero &= ~NewBits;
1598 }
1599 break;
1600 }
1601 case ISD::ANY_EXTEND: {
Dan Gohman7196cb12010-01-09 02:13:55 +0000[diff] [blame]1602 unsigned OperandBitWidth =
1603 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1604 APInt InMask = NewMask;
1605 InMask.trunc(OperandBitWidth);
1606 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1607 KnownZero, KnownOne, TLO, Depth+1))
1608 return true;
1609 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1610 KnownZero.zext(BitWidth);
1611 KnownOne.zext(BitWidth);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1612 break;
1613 }
1614 case ISD::TRUNCATE: {
1615 // Simplify the input, using demanded bit information, and compute the known
1616 // zero/one bits live out.
Dan Gohmanf4aab032010-03-01 17:59:21 +0000[diff] [blame]1617 unsigned OperandBitWidth =
1618 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1619 APInt TruncMask = NewMask;
Dan Gohmanf4aab032010-03-01 17:59:21 +0000[diff] [blame]1620 TruncMask.zext(OperandBitWidth);
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1621 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1622 KnownZero, KnownOne, TLO, Depth+1))
1623 return true;
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1624 KnownZero.trunc(BitWidth);
1625 KnownOne.trunc(BitWidth);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1626
1627 // If the input is only used by this truncate, see if we can shrink it based
1628 // on the known demanded bits.
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]1629 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1630 SDValue In = Op.getOperand(0);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1631 switch (In.getOpcode()) {
1632 default: break;
1633 case ISD::SRL:
1634 // Shrink SRL by a constant if none of the high bits shifted in are
1635 // demanded.
Evan Cheng3cbcbbb2010-04-17 06:13:15 +0000[diff] [blame]1636 if (TLO.LegalTypes() &&
1637 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1638 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1639 // undesirable.
1640 break;
1641 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1642 if (!ShAmt)
1643 break;
1644 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1645 OperandBitWidth - BitWidth);
1646 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1647 HighBits.trunc(BitWidth);
1648
1649 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1650 // None of the shifted in bits are needed. Add a truncate of the
1651 // shift input, then shift it.
1652 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1653 Op.getValueType(),
1654 In.getOperand(0));
1655 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1656 Op.getValueType(),
1657 NewTrunc,
1658 In.getOperand(1)));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1659 }
1660 break;
1661 }
1662 }
1663
1664 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1665 break;
1666 }
1667 case ISD::AssertZext: {
Dan Gohman81016822010-06-03 20:21:33 +0000[diff] [blame]1668 // Demand all the bits of the input that are demanded in the output.
1669 // The low bits are obvious; the high bits are demanded because we're
1670 // asserting that they're zero here.
1671 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1672 KnownZero, KnownOne, TLO, Depth+1))
1673 return true;
1674 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman81016822010-06-03 20:21:33 +0000[diff] [blame]1675
1676 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1677 APInt InMask = APInt::getLowBitsSet(BitWidth,
1678 VT.getSizeInBits());
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1679 KnownZero |= ~InMask & NewMask;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1680 break;
1681 }
Chris Lattner516731f2007-12-22 21:35:38 +0000[diff] [blame]1682 case ISD::BIT_CONVERT:
1683#if 0
1684 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1685 // is demanded, turn this into a FGETSIGN.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1686 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]1687 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1688 !MVT::isVector(Op.getOperand(0).getValueType())) {
Chris Lattner516731f2007-12-22 21:35:38 +0000[diff] [blame]1689 // Only do this xform if FGETSIGN is valid or if before legalize.
1690 if (!TLO.AfterLegalize ||
1691 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1692 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1693 // place. We expect the SHL to be eliminated by other optimizations.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1694 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Chris Lattner516731f2007-12-22 21:35:38 +0000[diff] [blame]1695 Op.getOperand(0));
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]1696 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1697 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
Chris Lattner516731f2007-12-22 21:35:38 +0000[diff] [blame]1698 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1699 Sign, ShAmt));
1700 }
1701 }
1702#endif
1703 break;
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1704 case ISD::ADD:
1705 case ISD::MUL:
1706 case ISD::SUB: {
1707 // Add, Sub, and Mul don't demand any bits in positions beyond that
1708 // of the highest bit demanded of them.
1709 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1710 BitWidth - NewMask.countLeadingZeros());
1711 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1712 KnownOne2, TLO, Depth+1))
1713 return true;
1714 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1715 KnownOne2, TLO, Depth+1))
1716 return true;
1717 // See if the operation should be performed at a smaller bit width.
Dan Gohman50fbd4f2010-06-24 14:30:44 +0000[diff] [blame]1718 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman4cedb1c2009-04-08 00:15:30 +0000[diff] [blame]1719 return true;
1720 }
1721 // FALL THROUGH
Dan Gohman9a77bb62008-05-06 00:53:29 +0000[diff] [blame]1722 default:
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1723 // Just use ComputeMaskedBits to compute output bits.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1724 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1725 break;
1726 }
1727
1728 // If we know the value of all of the demanded bits, return this as a
1729 // constant.
Dan Gohman11607792008-02-27 00:25:32 +0000[diff] [blame]1730 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1731 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1732
1733 return false;
1734}
1735
1736/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1737/// in Mask are known to be either zero or one and return them in the
1738/// KnownZero/KnownOne bitsets.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1739void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohmand0dfc772008-02-13 22:28:48 +0000[diff] [blame]1740 const APInt &Mask,
Dan Gohman229fa052008-02-13 00:35:47 +0000[diff] [blame]1741 APInt &KnownZero,
1742 APInt &KnownOne,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1743 const SelectionDAG &DAG,
1744 unsigned Depth) const {
1745 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1746 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1747 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1748 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1749 "Should use MaskedValueIsZero if you don't know whether Op"
1750 " is a target node!");
Dan Gohmand0dfc772008-02-13 22:28:48 +0000[diff] [blame]1751 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1752}
1753
1754/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1755/// targets that want to expose additional information about sign bits to the
1756/// DAG Combiner.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1757unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1758 unsigned Depth) const {
1759 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1760 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1761 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1762 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1763 "Should use ComputeNumSignBits if you don't know whether Op"
1764 " is a target node!");
1765 return 1;
1766}
1767
Dan Gohmanfaab1fb2009-02-15 23:59:32 +0000[diff] [blame]1768/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1769/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1770/// determine which bit is set.
1771///
Dale Johannesen0ca3f132009-02-11 19:19:41 +0000[diff] [blame]1772static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohmanfaab1fb2009-02-15 23:59:32 +0000[diff] [blame]1773 // A left-shift of a constant one will have exactly one bit set, because
1774 // shifting the bit off the end is undefined.
1775 if (Val.getOpcode() == ISD::SHL)
1776 if (ConstantSDNode *C =
1777 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1778 if (C->getAPIntValue() == 1)
1779 return true;
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]1780
Dan Gohmanfaab1fb2009-02-15 23:59:32 +0000[diff] [blame]1781 // Similarly, a right-shift of a constant sign-bit will have exactly
1782 // one bit set.
1783 if (Val.getOpcode() == ISD::SRL)
1784 if (ConstantSDNode *C =
1785 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1786 if (C->getAPIntValue().isSignBit())
1787 return true;
1788
1789 // More could be done here, though the above checks are enough
1790 // to handle some common cases.
1791
1792 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1793 EVT OpVT = Val.getValueType();
Dan Gohman978e5262010-03-02 02:14:38 +0000[diff] [blame]1794 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]1795 APInt Mask = APInt::getAllOnesValue(BitWidth);
1796 APInt KnownZero, KnownOne;
1797 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen0ca3f132009-02-11 19:19:41 +0000[diff] [blame]1798 return (KnownZero.countPopulation() == BitWidth - 1) &&
1799 (KnownOne.countPopulation() == 1);
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]1800}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1801
1802/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]1803/// and cc. If it is unable to simplify it, return a null SDValue.
1804SDValue
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1805TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1806 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]1807 DAGCombinerInfo &DCI, DebugLoc dl) const {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1808 SelectionDAG &DAG = DCI.DAG;
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]1809 LLVMContext &Context = *DAG.getContext();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1810
1811 // These setcc operations always fold.
1812 switch (Cond) {
1813 default: break;
1814 case ISD::SETFALSE:
1815 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1816 case ISD::SETTRUE:
1817 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1818 }
1819
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1820 if (isa<ConstantSDNode>(N0.getNode())) {
1821 // Ensure that the constant occurs on the RHS, and fold constant
1822 // comparisons.
1823 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1824 }
1825
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]1826 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohmand00055a2008-03-03 22:22:56 +0000[diff] [blame]1827 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesend0a7c0e2008-11-07 01:28:02 +0000[diff] [blame]1828
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1829 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1830 // equality comparison, then we're just comparing whether X itself is
1831 // zero.
1832 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1833 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1834 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1835 const APInt &ShAmt
1836 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1837 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1838 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1839 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1840 // (srl (ctlz x), 5) == 0 -> X != 0
1841 // (srl (ctlz x), 5) != 1 -> X != 0
1842 Cond = ISD::SETNE;
1843 } else {
1844 // (srl (ctlz x), 5) != 0 -> X == 0
1845 // (srl (ctlz x), 5) == 1 -> X == 0
1846 Cond = ISD::SETEQ;
1847 }
1848 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1849 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1850 Zero, Cond);
1851 }
1852 }
1853
1854 // If the LHS is '(and load, const)', the RHS is 0,
1855 // the test is for equality or unsigned, and all 1 bits of the const are
1856 // in the same partial word, see if we can shorten the load.
1857 if (DCI.isBeforeLegalize() &&
1858 N0.getOpcode() == ISD::AND && C1 == 0 &&
1859 N0.getNode()->hasOneUse() &&
1860 isa<LoadSDNode>(N0.getOperand(0)) &&
1861 N0.getOperand(0).getNode()->hasOneUse() &&
1862 isa<ConstantSDNode>(N0.getOperand(1))) {
1863 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1864 APInt bestMask;
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1865 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1866 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1867 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1868 unsigned maskWidth = origWidth;
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1869 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1870 // 8 bits, but have to be careful...
1871 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1872 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1873 const APInt &Mask =
1874 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1875 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1876 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1877 for (unsigned offset=0; offset<origWidth/width; offset++) {
1878 if ((newMask & Mask) == Mask) {
1879 if (!TD->isLittleEndian())
1880 bestOffset = (origWidth/width - offset - 1) * (width/8);
1881 else
1882 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1883 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1884 bestWidth = width;
1885 break;
Dale Johannesend0a7c0e2008-11-07 01:28:02 +0000[diff] [blame]1886 }
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1887 newMask = newMask << width;
Dale Johannesend0a7c0e2008-11-07 01:28:02 +0000[diff] [blame]1888 }
1889 }
1890 }
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1891 if (bestWidth) {
Owen Anderson77f4eb52009-08-12 00:36:31 +0000[diff] [blame]1892 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1893 if (newVT.isRound()) {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1894 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1895 SDValue Ptr = Lod->getBasePtr();
1896 if (bestOffset != 0)
1897 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1898 DAG.getConstant(bestOffset, PtrType));
1899 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1900 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1901 Lod->getSrcValue(),
1902 Lod->getSrcValueOffset() + bestOffset,
David Greene7c5a5062010-02-15 17:00:31 +0000[diff] [blame]1903 false, false, NewAlign);
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1904 return DAG.getSetCC(dl, VT,
1905 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1906 DAG.getConstant(bestMask.trunc(bestWidth),
1907 newVT)),
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1908 DAG.getConstant(0LL, newVT), Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1909 }
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1910 }
1911 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1912
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1913 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1914 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1915 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1916
1917 // If the comparison constant has bits in the upper part, the
1918 // zero-extended value could never match.
1919 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1920 C1.getBitWidth() - InSize))) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1921 switch (Cond) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1922 case ISD::SETUGT:
1923 case ISD::SETUGE:
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1924 case ISD::SETEQ: return DAG.getConstant(0, VT);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1925 case ISD::SETULT:
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1926 case ISD::SETULE:
1927 case ISD::SETNE: return DAG.getConstant(1, VT);
1928 case ISD::SETGT:
1929 case ISD::SETGE:
1930 // True if the sign bit of C1 is set.
1931 return DAG.getConstant(C1.isNegative(), VT);
1932 case ISD::SETLT:
1933 case ISD::SETLE:
1934 // True if the sign bit of C1 isn't set.
1935 return DAG.getConstant(C1.isNonNegative(), VT);
1936 default:
Jakob Stoklund Olesenca037df2009-07-24 18:22:59 +0000[diff] [blame]1937 break;
1938 }
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1939 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1940
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1941 // Otherwise, we can perform the comparison with the low bits.
1942 switch (Cond) {
1943 case ISD::SETEQ:
1944 case ISD::SETNE:
1945 case ISD::SETUGT:
1946 case ISD::SETUGE:
1947 case ISD::SETULT:
1948 case ISD::SETULE: {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1949 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1950 if (DCI.isBeforeLegalizeOps() ||
1951 (isOperationLegal(ISD::SETCC, newVT) &&
1952 getCondCodeAction(Cond, newVT)==Legal))
1953 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1954 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1955 Cond);
1956 break;
1957 }
1958 default:
1959 break; // todo, be more careful with signed comparisons
1960 }
1961 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]1962 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1963 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1964 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1965 EVT ExtDstTy = N0.getValueType();
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1966 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1967
1968 // If the extended part has any inconsistent bits, it cannot ever
1969 // compare equal. In other words, they have to be all ones or all
1970 // zeros.
1971 APInt ExtBits =
1972 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1973 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1974 return DAG.getConstant(Cond == ISD::SETNE, VT);
1975
1976 SDValue ZextOp;
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]1977 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1978 if (Op0Ty == ExtSrcTy) {
1979 ZextOp = N0.getOperand(0);
1980 } else {
1981 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1982 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1983 DAG.getConstant(Imm, Op0Ty));
1984 }
1985 if (!DCI.isCalledByLegalizer())
1986 DCI.AddToWorklist(ZextOp.getNode());
1987 // Otherwise, make this a use of a zext.
1988 return DAG.getSetCC(dl, VT, ZextOp,
1989 DAG.getConstant(C1 & APInt::getLowBitsSet(
1990 ExtDstTyBits,
1991 ExtSrcTyBits),
1992 ExtDstTy),
1993 Cond);
1994 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1995 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]1996 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]1997 if (N0.getOpcode() == ISD::SETCC &&
1998 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]1999 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2000 if (TrueWhenTrue)
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]2001 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2002 // Invert the condition.
2003 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2004 CC = ISD::getSetCCInverse(CC,
2005 N0.getOperand(0).getValueType().isInteger());
2006 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2007 }
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]2008
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2009 if ((N0.getOpcode() == ISD::XOR ||
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]2010 (N0.getOpcode() == ISD::AND &&
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2011 N0.getOperand(0).getOpcode() == ISD::XOR &&
2012 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2013 isa<ConstantSDNode>(N0.getOperand(1)) &&
2014 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2015 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2016 // can only do this if the top bits are known zero.
2017 unsigned BitWidth = N0.getValueSizeInBits();
2018 if (DAG.MaskedValueIsZero(N0,
2019 APInt::getHighBitsSet(BitWidth,
2020 BitWidth-1))) {
2021 // Okay, get the un-inverted input value.
2022 SDValue Val;
2023 if (N0.getOpcode() == ISD::XOR)
2024 Val = N0.getOperand(0);
2025 else {
2026 assert(N0.getOpcode() == ISD::AND &&
2027 N0.getOperand(0).getOpcode() == ISD::XOR);
2028 // ((X^1)&1)^1 -> X & 1
2029 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2030 N0.getOperand(0).getOperand(0),
2031 N0.getOperand(1));
2032 }
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]2033
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2034 return DAG.getSetCC(dl, VT, Val, N1,
2035 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2036 }
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]2037 } else if (N1C->getAPIntValue() == 1 &&
2038 (VT == MVT::i1 ||
2039 getBooleanContents() == ZeroOrOneBooleanContent)) {
2040 SDValue Op0 = N0;
2041 if (Op0.getOpcode() == ISD::TRUNCATE)
2042 Op0 = Op0.getOperand(0);
2043
2044 if ((Op0.getOpcode() == ISD::XOR) &&
2045 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2046 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2047 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2048 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2049 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2050 Cond);
2051 } else if (Op0.getOpcode() == ISD::AND &&
2052 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2053 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2054 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikovc9c3d992010-05-01 12:52:34 +0000[diff] [blame]2055 if (Op0.getValueType().bitsGT(VT))
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]2056 Op0 = DAG.getNode(ISD::AND, dl, VT,
2057 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2058 DAG.getConstant(1, VT));
Anton Korobeynikovc9c3d992010-05-01 12:52:34 +0000[diff] [blame]2059 else if (Op0.getValueType().bitsLT(VT))
2060 Op0 = DAG.getNode(ISD::AND, dl, VT,
2061 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2062 DAG.getConstant(1, VT));
2063
Evan Chengcb611272010-02-27 07:36:59 +0000[diff] [blame]2064 return DAG.getSetCC(dl, VT, Op0,
2065 DAG.getConstant(0, Op0.getValueType()),
2066 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2067 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2068 }
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2069 }
2070
2071 APInt MinVal, MaxVal;
2072 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2073 if (ISD::isSignedIntSetCC(Cond)) {
2074 MinVal = APInt::getSignedMinValue(OperandBitSize);
2075 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2076 } else {
2077 MinVal = APInt::getMinValue(OperandBitSize);
2078 MaxVal = APInt::getMaxValue(OperandBitSize);
2079 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2080
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2081 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2082 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2083 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2084 // X >= C0 --> X > (C0-1)
2085 return DAG.getSetCC(dl, VT, N0,
2086 DAG.getConstant(C1-1, N1.getValueType()),
2087 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2088 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2089
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2090 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2091 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2092 // X <= C0 --> X < (C0+1)
2093 return DAG.getSetCC(dl, VT, N0,
2094 DAG.getConstant(C1+1, N1.getValueType()),
2095 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2096 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2097
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2098 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2099 return DAG.getConstant(0, VT); // X < MIN --> false
2100 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2101 return DAG.getConstant(1, VT); // X >= MIN --> true
2102 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2103 return DAG.getConstant(0, VT); // X > MAX --> false
2104 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2105 return DAG.getConstant(1, VT); // X <= MAX --> true
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2106
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2107 // Canonicalize setgt X, Min --> setne X, Min
2108 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2109 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2110 // Canonicalize setlt X, Max --> setne X, Max
2111 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2112 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2113
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2114 // If we have setult X, 1, turn it into seteq X, 0
2115 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2116 return DAG.getSetCC(dl, VT, N0,
2117 DAG.getConstant(MinVal, N0.getValueType()),
2118 ISD::SETEQ);
2119 // If we have setugt X, Max-1, turn it into seteq X, Max
2120 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2121 return DAG.getSetCC(dl, VT, N0,
2122 DAG.getConstant(MaxVal, N0.getValueType()),
2123 ISD::SETEQ);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2124
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2125 // If we have "setcc X, C0", check to see if we can shrink the immediate
2126 // by changing cc.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2127
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2128 // SETUGT X, SINTMAX -> SETLT X, 0
2129 if (Cond == ISD::SETUGT &&
2130 C1 == APInt::getSignedMaxValue(OperandBitSize))
2131 return DAG.getSetCC(dl, VT, N0,
2132 DAG.getConstant(0, N1.getValueType()),
2133 ISD::SETLT);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2134
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2135 // SETULT X, SINTMIN -> SETGT X, -1
2136 if (Cond == ISD::SETULT &&
2137 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2138 SDValue ConstMinusOne =
2139 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2140 N1.getValueType());
2141 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2142 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2143
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2144 // Fold bit comparisons when we can.
2145 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Cheng095dac22010-01-06 19:38:29 +0000[diff] [blame]2146 (VT == N0.getValueType() ||
2147 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2148 N0.getOpcode() == ISD::AND)
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2149 if (ConstantSDNode *AndRHS =
2150 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]2151 EVT ShiftTy = DCI.isBeforeLegalize() ?
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2152 getPointerTy() : getShiftAmountTy();
2153 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2154 // Perform the xform if the AND RHS is a single bit.
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]2155 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Cheng095dac22010-01-06 19:38:29 +0000[diff] [blame]2156 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2157 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]2158 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2159 }
Evan Cheng746ff382010-01-07 20:58:44 +0000[diff] [blame]2160 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2161 // (X & 8) == 8 --> (X & 8) >> 3
2162 // Perform the xform if C1 is a single bit.
2163 if (C1.isPowerOf2()) {
Evan Cheng095dac22010-01-06 19:38:29 +0000[diff] [blame]2164 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2165 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2166 DAG.getConstant(C1.logBase2(), ShiftTy)));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2167 }
2168 }
Eli Friedman060189a2009-07-26 23:47:17 +0000[diff] [blame]2169 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2170 }
2171
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2172 if (isa<ConstantFPSDNode>(N0.getNode())) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2173 // Constant fold or commute setcc.
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2174 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2175 if (O.getNode()) return O;
2176 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner42184432007-12-29 08:37:08 +0000[diff] [blame]2177 // If the RHS of an FP comparison is a constant, simplify it away in
2178 // some cases.
2179 if (CFP->getValueAPF().isNaN()) {
2180 // If an operand is known to be a nan, we can fold it.
2181 switch (ISD::getUnorderedFlavor(Cond)) {
Edwin Törökbd448e32009-07-14 16:55:14 +0000[diff] [blame]2182 default: llvm_unreachable("Unknown flavor!");
Chris Lattner42184432007-12-29 08:37:08 +0000[diff] [blame]2183 case 0: // Known false.
2184 return DAG.getConstant(0, VT);
2185 case 1: // Known true.
2186 return DAG.getConstant(1, VT);
Chris Lattner0bcfea02007-12-30 21:21:10 +0000[diff] [blame]2187 case 2: // Undefined.
Dale Johannesen9bfc0172009-02-06 23:05:02 +0000[diff] [blame]2188 return DAG.getUNDEF(VT);
Chris Lattner42184432007-12-29 08:37:08 +0000[diff] [blame]2189 }
2190 }
2191
2192 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2193 // constant if knowing that the operand is non-nan is enough. We prefer to
2194 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2195 // materialize 0.0.
2196 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2197 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman2221f562009-09-26 15:24:17 +0000[diff] [blame]2198
2199 // If the condition is not legal, see if we can find an equivalent one
2200 // which is legal.
2201 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2202 // If the comparison was an awkward floating-point == or != and one of
2203 // the comparison operands is infinity or negative infinity, convert the
2204 // condition to a less-awkward <= or >=.
2205 if (CFP->getValueAPF().isInfinity()) {
2206 if (CFP->getValueAPF().isNegative()) {
2207 if (Cond == ISD::SETOEQ &&
2208 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2209 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2210 if (Cond == ISD::SETUEQ &&
2211 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2212 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2213 if (Cond == ISD::SETUNE &&
2214 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2215 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2216 if (Cond == ISD::SETONE &&
2217 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2218 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2219 } else {
2220 if (Cond == ISD::SETOEQ &&
2221 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2222 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2223 if (Cond == ISD::SETUEQ &&
2224 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2225 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2226 if (Cond == ISD::SETUNE &&
2227 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2228 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2229 if (Cond == ISD::SETONE &&
2230 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2231 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2232 }
2233 }
2234 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2235 }
2236
2237 if (N0 == N1) {
2238 // We can always fold X == X for integer setcc's.
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]2239 if (N0.getValueType().isInteger())
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2240 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2241 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2242 if (UOF == 2) // FP operators that are undefined on NaNs.
2243 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2244 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2245 return DAG.getConstant(UOF, VT);
2246 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2247 // if it is not already.
2248 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2249 if (NewCond != Cond)
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2250 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2251 }
2252
2253 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]2254 N0.getValueType().isInteger()) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2255 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2256 N0.getOpcode() == ISD::XOR) {
2257 // Simplify (X+Y) == (X+Z) --> Y == Z
2258 if (N0.getOpcode() == N1.getOpcode()) {
2259 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2260 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2261 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2262 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2263 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2264 // If X op Y == Y op X, try other combinations.
2265 if (N0.getOperand(0) == N1.getOperand(1))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2266 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2267 Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2268 if (N0.getOperand(1) == N1.getOperand(0))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2269 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2270 Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2271 }
2272 }
2273
2274 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2275 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2276 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2277 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2278 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]2279 DAG.getConstant(RHSC->getAPIntValue()-
2280 LHSR->getAPIntValue(),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2281 N0.getValueType()), Cond);
2282 }
2283
2284 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2285 if (N0.getOpcode() == ISD::XOR)
2286 // If we know that all of the inverted bits are zero, don't bother
2287 // performing the inversion.
Dan Gohman07961cd2008-02-25 21:11:39 +0000[diff] [blame]2288 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2289 return
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2290 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman07961cd2008-02-25 21:11:39 +0000[diff] [blame]2291 DAG.getConstant(LHSR->getAPIntValue() ^
2292 RHSC->getAPIntValue(),
2293 N0.getValueType()),
2294 Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2295 }
2296
2297 // Turn (C1-X) == C2 --> X == C1-C2
2298 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2299 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman07961cd2008-02-25 21:11:39 +0000[diff] [blame]2300 return
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2301 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman07961cd2008-02-25 21:11:39 +0000[diff] [blame]2302 DAG.getConstant(SUBC->getAPIntValue() -
2303 RHSC->getAPIntValue(),
2304 N0.getValueType()),
2305 Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2306 }
2307 }
2308 }
2309
2310 // Simplify (X+Z) == X --> Z == 0
2311 if (N0.getOperand(0) == N1)
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2312 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2313 DAG.getConstant(0, N0.getValueType()), Cond);
2314 if (N0.getOperand(1) == N1) {
2315 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2316 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2317 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2318 else if (N0.getNode()->hasOneUse()) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2319 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2320 // (Z-X) == X --> Z == X<<1
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2321 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2322 N1,
2323 DAG.getConstant(1, getShiftAmountTy()));
2324 if (!DCI.isCalledByLegalizer())
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2325 DCI.AddToWorklist(SH.getNode());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2326 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2327 }
2328 }
2329 }
2330
2331 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2332 N1.getOpcode() == ISD::XOR) {
2333 // Simplify X == (X+Z) --> Z == 0
2334 if (N1.getOperand(0) == N0) {
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2335 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2336 DAG.getConstant(0, N1.getValueType()), Cond);
2337 } else if (N1.getOperand(1) == N0) {
2338 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2339 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2340 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2341 } else if (N1.getNode()->hasOneUse()) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2342 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2343 // X == (Z-X) --> X<<1 == Z
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2344 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2345 DAG.getConstant(1, getShiftAmountTy()));
2346 if (!DCI.isCalledByLegalizer())
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2347 DCI.AddToWorklist(SH.getNode());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2348 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2349 }
2350 }
2351 }
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]2352
Dan Gohman8710f1c2009-01-29 16:18:12 +0000[diff] [blame]2353 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen0ca3f132009-02-11 19:19:41 +0000[diff] [blame]2354 // Note that where y is variable and is known to have at most
2355 // one bit set (for example, if it is z&1) we cannot do this;
2356 // the expressions are not equivalent when y==0.
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]2357 if (N0.getOpcode() == ISD::AND)
2358 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen0ca3f132009-02-11 19:19:41 +0000[diff] [blame]2359 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]2360 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2361 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2362 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]2363 }
2364 }
2365 if (N1.getOpcode() == ISD::AND)
2366 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen0ca3f132009-02-11 19:19:41 +0000[diff] [blame]2367 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]2368 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2369 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2370 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohman22cefb02009-01-29 01:59:02 +0000[diff] [blame]2371 }
2372 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2373 }
2374
2375 // Fold away ALL boolean setcc's.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2376 SDValue Temp;
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2377 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2378 switch (Cond) {
Edwin Törökbd448e32009-07-14 16:55:14 +0000[diff] [blame]2379 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson81a42cf2009-01-22 17:39:32 +0000[diff] [blame]2380 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2381 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2382 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2383 if (!DCI.isCalledByLegalizer())
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2384 DCI.AddToWorklist(Temp.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2385 break;
2386 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2387 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2388 break;
Bob Wilson81a42cf2009-01-22 17:39:32 +0000[diff] [blame]2389 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2390 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2391 Temp = DAG.getNOT(dl, N0, MVT::i1);
2392 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2393 if (!DCI.isCalledByLegalizer())
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2394 DCI.AddToWorklist(Temp.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2395 break;
Bob Wilson81a42cf2009-01-22 17:39:32 +0000[diff] [blame]2396 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2397 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2398 Temp = DAG.getNOT(dl, N1, MVT::i1);
2399 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2400 if (!DCI.isCalledByLegalizer())
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2401 DCI.AddToWorklist(Temp.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2402 break;
Bob Wilson81a42cf2009-01-22 17:39:32 +0000[diff] [blame]2403 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2404 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2405 Temp = DAG.getNOT(dl, N0, MVT::i1);
2406 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2407 if (!DCI.isCalledByLegalizer())
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2408 DCI.AddToWorklist(Temp.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2409 break;
Bob Wilson81a42cf2009-01-22 17:39:32 +0000[diff] [blame]2410 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2411 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2412 Temp = DAG.getNOT(dl, N1, MVT::i1);
2413 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2414 break;
2415 }
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2416 if (VT != MVT::i1) {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2417 if (!DCI.isCalledByLegalizer())
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2418 DCI.AddToWorklist(N0.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2419 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2420 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2421 }
2422 return N0;
2423 }
2424
2425 // Could not fold it.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2426 return SDValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2427}
2428
Evan Chengef7be082008-05-12 19:56:52 +0000[diff] [blame]2429/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2430/// node is a GlobalAddress + offset.
Dan Gohman36c56d02010-04-15 01:51:59 +0000[diff] [blame]2431bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
Evan Chengef7be082008-05-12 19:56:52 +0000[diff] [blame]2432 int64_t &Offset) const {
2433 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman00403842008-06-09 22:05:52 +0000[diff] [blame]2434 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2435 GA = GASD->getGlobal();
2436 Offset += GASD->getOffset();
Evan Chengef7be082008-05-12 19:56:52 +0000[diff] [blame]2437 return true;
2438 }
2439
2440 if (N->getOpcode() == ISD::ADD) {
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2441 SDValue N1 = N->getOperand(0);
2442 SDValue N2 = N->getOperand(1);
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2443 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengef7be082008-05-12 19:56:52 +0000[diff] [blame]2444 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2445 if (V) {
Dan Gohman40686732008-09-26 21:54:37 +0000[diff] [blame]2446 Offset += V->getSExtValue();
Evan Chengef7be082008-05-12 19:56:52 +0000[diff] [blame]2447 return true;
2448 }
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2449 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengef7be082008-05-12 19:56:52 +0000[diff] [blame]2450 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2451 if (V) {
Dan Gohman40686732008-09-26 21:54:37 +0000[diff] [blame]2452 Offset += V->getSExtValue();
Evan Chengef7be082008-05-12 19:56:52 +0000[diff] [blame]2453 return true;
2454 }
2455 }
2456 }
2457 return false;
2458}
2459
2460
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2461SDValue TargetLowering::
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2462PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2463 // Default implementation: no optimization.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2464 return SDValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2465}
2466
2467//===----------------------------------------------------------------------===//
2468// Inline Assembler Implementation Methods
2469//===----------------------------------------------------------------------===//
2470
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2471
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2472TargetLowering::ConstraintType
2473TargetLowering::getConstraintType(const std::string &Constraint) const {
2474 // FIXME: lots more standard ones to handle.
2475 if (Constraint.size() == 1) {
2476 switch (Constraint[0]) {
2477 default: break;
2478 case 'r': return C_RegisterClass;
2479 case 'm': // memory
2480 case 'o': // offsetable
2481 case 'V': // not offsetable
2482 return C_Memory;
2483 case 'i': // Simple Integer or Relocatable Constant
2484 case 'n': // Simple Integer
2485 case 's': // Relocatable Constant
2486 case 'X': // Allow ANY value.
2487 case 'I': // Target registers.
2488 case 'J':
2489 case 'K':
2490 case 'L':
2491 case 'M':
2492 case 'N':
2493 case 'O':
2494 case 'P':
2495 return C_Other;
2496 }
2497 }
2498
2499 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2500 Constraint[Constraint.size()-1] == '}')
2501 return C_Register;
2502 return C_Unknown;
2503}
2504
Dale Johannesene99fc902008-01-29 02:21:21 +0000[diff] [blame]2505/// LowerXConstraint - try to replace an X constraint, which matches anything,
2506/// with another that has more specific requirements based on the type of the
2507/// corresponding operand.
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]2508const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]2509 if (ConstraintVT.isInteger())
Chris Lattnereca405c2008-04-26 23:02:14 +0000[diff] [blame]2510 return "r";
Duncan Sands92c43912008-06-06 12:08:01 +0000[diff] [blame]2511 if (ConstraintVT.isFloatingPoint())
Chris Lattnereca405c2008-04-26 23:02:14 +0000[diff] [blame]2512 return "f"; // works for many targets
2513 return 0;
Dale Johannesene99fc902008-01-29 02:21:21 +0000[diff] [blame]2514}
2515
Chris Lattnera531abc2007-08-25 00:47:38 +0000[diff] [blame]2516/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2517/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2518void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattnera531abc2007-08-25 00:47:38 +0000[diff] [blame]2519 char ConstraintLetter,
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2520 std::vector<SDValue> &Ops,
Chris Lattnereca405c2008-04-26 23:02:14 +0000[diff] [blame]2521 SelectionDAG &DAG) const {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2522 switch (ConstraintLetter) {
2523 default: break;
Dale Johannesencfb19e62007-11-05 21:20:28 +0000[diff] [blame]2524 case 'X': // Allows any operand; labels (basic block) use this.
2525 if (Op.getOpcode() == ISD::BasicBlock) {
2526 Ops.push_back(Op);
2527 return;
2528 }
2529 // fall through
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2530 case 'i': // Simple Integer or Relocatable Constant
2531 case 'n': // Simple Integer
Dale Johannesencfb19e62007-11-05 21:20:28 +0000[diff] [blame]2532 case 's': { // Relocatable Constant
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2533 // These operands are interested in values of the form (GV+C), where C may
2534 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2535 // is possible and fine if either GV or C are missing.
2536 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2537 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2538
2539 // If we have "(add GV, C)", pull out GV/C
2540 if (Op.getOpcode() == ISD::ADD) {
2541 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2542 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2543 if (C == 0 || GA == 0) {
2544 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2545 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2546 }
2547 if (C == 0 || GA == 0)
2548 C = 0, GA = 0;
2549 }
2550
2551 // If we find a valid operand, map to the TargetXXX version so that the
2552 // value itself doesn't get selected.
2553 if (GA) { // Either &GV or &GV+C
2554 if (ConstraintLetter != 'n') {
2555 int64_t Offs = GA->getOffset();
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000[diff] [blame]2556 if (C) Offs += C->getZExtValue();
Devang Patelde09e922010-07-06 22:08:15 +0000[diff] [blame]2557 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel4ef03212010-07-15 18:45:27 +0000[diff] [blame]2558 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattnera531abc2007-08-25 00:47:38 +0000[diff] [blame]2559 Op.getValueType(), Offs));
2560 return;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2561 }
2562 }
2563 if (C) { // just C, no GV.
2564 // Simple constants are not allowed for 's'.
Chris Lattnera531abc2007-08-25 00:47:38 +0000[diff] [blame]2565 if (ConstraintLetter != 's') {
Dale Johannesenf190a032009-02-12 20:58:09 +0000[diff] [blame]2566 // gcc prints these as sign extended. Sign extend value to 64 bits
2567 // now; without this it would get ZExt'd later in
2568 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2569 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson36e3a6e2009-08-11 20:47:22 +0000[diff] [blame]2570 MVT::i64));
Chris Lattnera531abc2007-08-25 00:47:38 +0000[diff] [blame]2571 return;
2572 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2573 }
2574 break;
2575 }
2576 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2577}
2578
2579std::vector<unsigned> TargetLowering::
2580getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]2581 EVT VT) const {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2582 return std::vector<unsigned>();
2583}
2584
2585
2586std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2587getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]2588 EVT VT) const {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2589 if (Constraint[0] != '{')
Douglas Gregor491363c2010-05-11 06:17:44 +0000[diff] [blame]2590 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2591 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2592
2593 // Remove the braces from around the name.
Benjamin Kramerea862b02009-11-12 20:36:59 +0000[diff] [blame]2594 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2595
2596 // Figure out which register class contains this reg.
Dan Gohman1e57df32008-02-10 18:45:23 +0000[diff] [blame]2597 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2598 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2599 E = RI->regclass_end(); RCI != E; ++RCI) {
2600 const TargetRegisterClass *RC = *RCI;
2601
Dan Gohmandf1a7ff2010-02-10 16:03:48 +0000[diff] [blame]2602 // If none of the value types for this register class are valid, we
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2603 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2604 bool isLegal = false;
2605 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2606 I != E; ++I) {
2607 if (isTypeLegal(*I)) {
2608 isLegal = true;
2609 break;
2610 }
2611 }
2612
2613 if (!isLegal) continue;
2614
2615 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2616 I != E; ++I) {
Benjamin Kramerea862b02009-11-12 20:36:59 +0000[diff] [blame]2617 if (RegName.equals_lower(RI->getName(*I)))
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2618 return std::make_pair(*I, RC);
2619 }
2620 }
2621
Douglas Gregor491363c2010-05-11 06:17:44 +0000[diff] [blame]2622 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2623}
2624
2625//===----------------------------------------------------------------------===//
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2626// Constraint Selection.
2627
Chris Lattnerefec3242008-10-17 16:47:46 +0000[diff] [blame]2628/// isMatchingInputConstraint - Return true of this is an input operand that is
2629/// a matching constraint like "4".
2630bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner01f53542008-10-17 16:21:11 +0000[diff] [blame]2631 assert(!ConstraintCode.empty() && "No known constraint!");
2632 return isdigit(ConstraintCode[0]);
2633}
2634
2635/// getMatchedOperand - If this is an input matching constraint, this method
2636/// returns the output operand it matches.
2637unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2638 assert(!ConstraintCode.empty() && "No known constraint!");
2639 return atoi(ConstraintCode.c_str());
2640}
2641
2642
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2643/// getConstraintGenerality - Return an integer indicating how general CT
2644/// is.
2645static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2646 switch (CT) {
Edwin Törökbd448e32009-07-14 16:55:14 +0000[diff] [blame]2647 default: llvm_unreachable("Unknown constraint type!");
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2648 case TargetLowering::C_Other:
2649 case TargetLowering::C_Unknown:
2650 return 0;
2651 case TargetLowering::C_Register:
2652 return 1;
2653 case TargetLowering::C_RegisterClass:
2654 return 2;
2655 case TargetLowering::C_Memory:
2656 return 3;
2657 }
2658}
2659
2660/// ChooseConstraint - If there are multiple different constraints that we
2661/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattnerf9fde542008-04-27 01:49:46 +0000[diff] [blame]2662/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2663/// Other -> immediates and magic values
2664/// Register -> one specific register
2665/// RegisterClass -> a group of regs
2666/// Memory -> memory
2667/// Ideally, we would pick the most specific constraint possible: if we have
2668/// something that fits into a register, we would pick it. The problem here
2669/// is that if we have something that could either be in a register or in
2670/// memory that use of the register could cause selection of *other*
2671/// operands to fail: they might only succeed if we pick memory. Because of
2672/// this the heuristic we use is:
2673///
2674/// 1) If there is an 'other' constraint, and if the operand is valid for
2675/// that constraint, use it. This makes us take advantage of 'i'
2676/// constraints when available.
2677/// 2) Otherwise, pick the most general constraint present. This prefers
2678/// 'm' over 'r', for example.
2679///
2680static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesena7ba9cd2010-06-25 21:55:36 +0000[diff] [blame]2681 const TargetLowering &TLI,
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2682 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2683 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2684 unsigned BestIdx = 0;
2685 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2686 int BestGenerality = -1;
Dale Johannesen0d7310c2010-06-28 22:09:45 +0000[diff] [blame]2687
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2688 // Loop over the options, keeping track of the most general one.
2689 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2690 TargetLowering::ConstraintType CType =
2691 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesen0d7310c2010-06-28 22:09:45 +0000[diff] [blame]2692
Chris Lattner4486c2e2008-04-27 00:37:18 +0000[diff] [blame]2693 // If this is an 'other' constraint, see if the operand is valid for it.
2694 // For example, on X86 we might have an 'rI' constraint. If the operand
2695 // is an integer in the range [0..31] we want to use I (saving a load
2696 // of a register), otherwise we must use 'r'.
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2697 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner4486c2e2008-04-27 00:37:18 +0000[diff] [blame]2698 assert(OpInfo.Codes[i].size() == 1 &&
2699 "Unhandled multi-letter 'other' constraint");
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2700 std::vector<SDValue> ResultOps;
Dale Johannesena7ba9cd2010-06-25 21:55:36 +0000[diff] [blame]2701 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
Chris Lattner4486c2e2008-04-27 00:37:18 +0000[diff] [blame]2702 ResultOps, *DAG);
2703 if (!ResultOps.empty()) {
2704 BestType = CType;
2705 BestIdx = i;
2706 break;
2707 }
2708 }
2709
Dale Johannesen0d7310c2010-06-28 22:09:45 +0000[diff] [blame]2710 // Things with matching constraints can only be registers, per gcc
2711 // documentation. This mainly affects "g" constraints.
2712 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2713 continue;
2714
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2715 // This constraint letter is more general than the previous one, use it.
2716 int Generality = getConstraintGenerality(CType);
2717 if (Generality > BestGenerality) {
2718 BestType = CType;
2719 BestIdx = i;
2720 BestGenerality = Generality;
2721 }
2722 }
2723
2724 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2725 OpInfo.ConstraintType = BestType;
2726}
2727
2728/// ComputeConstraintToUse - Determines the constraint code and constraint
2729/// type to use for the specific AsmOperandInfo, setting
2730/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner4486c2e2008-04-27 00:37:18 +0000[diff] [blame]2731void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2732 SDValue Op,
Chris Lattner4486c2e2008-04-27 00:37:18 +0000[diff] [blame]2733 SelectionDAG *DAG) const {
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2734 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2735
2736 // Single-letter constraints ('r') are very common.
2737 if (OpInfo.Codes.size() == 1) {
2738 OpInfo.ConstraintCode = OpInfo.Codes[0];
2739 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2740 } else {
Dale Johannesena7ba9cd2010-06-25 21:55:36 +0000[diff] [blame]2741 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2742 }
2743
2744 // 'X' matches anything.
2745 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2746 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesend4389112009-07-07 23:26:33 +0000[diff] [blame]2747 // that matches labels). For Functions, the type here is the type of
Dale Johannesend3d20992009-07-20 23:27:39 +0000[diff] [blame]2748 // the result, which is not what we want to look at; leave them alone.
2749 Value *v = OpInfo.CallOperandVal;
Dale Johannesend4389112009-07-07 23:26:33 +0000[diff] [blame]2750 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2751 OpInfo.CallOperandVal = v;
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2752 return;
Dale Johannesend4389112009-07-07 23:26:33 +0000[diff] [blame]2753 }
Chris Lattner4cf8c702008-04-27 00:09:47 +0000[diff] [blame]2754
2755 // Otherwise, try to resolve it to something we know about by looking at
2756 // the actual operand type.
2757 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2758 OpInfo.ConstraintCode = Repl;
2759 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2760 }
2761 }
2762}
2763
2764//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2765// Loop Strength Reduction hooks
2766//===----------------------------------------------------------------------===//
2767
2768/// isLegalAddressingMode - Return true if the addressing mode represented
2769/// by AM is legal for this target, for a load/store of the specified type.
2770bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2771 const Type *Ty) const {
2772 // The default implementation of this implements a conservative RISCy, r+r and
2773 // r+i addr mode.
2774
2775 // Allows a sign-extended 16-bit immediate field.
2776 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2777 return false;
2778
2779 // No global is ever allowed as a base.
2780 if (AM.BaseGV)
2781 return false;
2782
2783 // Only support r+r,
2784 switch (AM.Scale) {
2785 case 0: // "r+i" or just "i", depending on HasBaseReg.
2786 break;
2787 case 1:
2788 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2789 return false;
2790 // Otherwise we have r+r or r+i.
2791 break;
2792 case 2:
2793 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2794 return false;
2795 // Allow 2*r as r+r.
2796 break;
2797 }
2798
2799 return true;
2800}
2801
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2802/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2803/// return a DAG expression to select that will generate the same value by
2804/// multiplying by a magic number. See:
2805/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2806SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2807 std::vector<SDNode*>* Created) const {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]2808 EVT VT = N->getValueType(0);
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2809 DebugLoc dl= N->getDebugLoc();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2810
2811 // Check to see if we can do this.
Eli Friedman2589b502008-11-30 06:35:39 +0000[diff] [blame]2812 // FIXME: We should be more aggressive here.
2813 if (!isTypeLegal(VT))
2814 return SDValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2815
Eli Friedman2589b502008-11-30 06:35:39 +0000[diff] [blame]2816 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad56b11f92009-04-30 10:15:35 +0000[diff] [blame]2817 APInt::ms magics = d.magic();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2818
2819 // Multiply the numerator (operand 0) by the magic value
Eli Friedman2589b502008-11-30 06:35:39 +0000[diff] [blame]2820 // FIXME: We should support doing a MUL in a wider type
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2821 SDValue Q;
Dan Gohman52c51aa2009-01-28 17:46:25 +0000[diff] [blame]2822 if (isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2823 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman5a199552007-10-08 18:33:35 +0000[diff] [blame]2824 DAG.getConstant(magics.m, VT));
Dan Gohman52c51aa2009-01-28 17:46:25 +0000[diff] [blame]2825 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2826 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman5a199552007-10-08 18:33:35 +0000[diff] [blame]2827 N->getOperand(0),
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2828 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman5a199552007-10-08 18:33:35 +0000[diff] [blame]2829 else
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2830 return SDValue(); // No mulhs or equvialent
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2831 // If d > 0 and m < 0, add the numerator
Eli Friedman2589b502008-11-30 06:35:39 +0000[diff] [blame]2832 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2833 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2834 if (Created)
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2835 Created->push_back(Q.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2836 }
2837 // If d < 0 and m > 0, subtract the numerator.
Eli Friedman2589b502008-11-30 06:35:39 +0000[diff] [blame]2838 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2839 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2840 if (Created)
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2841 Created->push_back(Q.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2842 }
2843 // Shift right algebraic if shift value is nonzero
2844 if (magics.s > 0) {
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2845 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2846 DAG.getConstant(magics.s, getShiftAmountTy()));
2847 if (Created)
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2848 Created->push_back(Q.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2849 }
2850 // Extract the sign bit and add it to the quotient
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2851 SDValue T =
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2852 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2853 getShiftAmountTy()));
2854 if (Created)
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2855 Created->push_back(T.getNode());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2856 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2857}
2858
2859/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2860/// return a DAG expression to select that will generate the same value by
2861/// multiplying by a magic number. See:
2862/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2863SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2864 std::vector<SDNode*>* Created) const {
Owen Andersonac9de032009-08-10 22:56:29 +0000[diff] [blame]2865 EVT VT = N->getValueType(0);
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2866 DebugLoc dl = N->getDebugLoc();
Eli Friedmanca009722008-11-30 06:02:26 +0000[diff] [blame]2867
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2868 // Check to see if we can do this.
Eli Friedmanca009722008-11-30 06:02:26 +0000[diff] [blame]2869 // FIXME: We should be more aggressive here.
2870 if (!isTypeLegal(VT))
2871 return SDValue();
2872
2873 // FIXME: We should use a narrower constant when the upper
2874 // bits are known to be zero.
2875 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
Jay Foad56b11f92009-04-30 10:15:35 +0000[diff] [blame]2876 APInt::mu magics = N1C->getAPIntValue().magicu();
Eli Friedmanca009722008-11-30 06:02:26 +0000[diff] [blame]2877
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2878 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanca009722008-11-30 06:02:26 +0000[diff] [blame]2879 // FIXME: We should support doing a MUL in a wider type
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2880 SDValue Q;
Dan Gohman52c51aa2009-01-28 17:46:25 +0000[diff] [blame]2881 if (isOperationLegalOrCustom(ISD::MULHU, VT))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2882 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
Dan Gohman5a199552007-10-08 18:33:35 +0000[diff] [blame]2883 DAG.getConstant(magics.m, VT));
Dan Gohman52c51aa2009-01-28 17:46:25 +0000[diff] [blame]2884 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2885 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman5a199552007-10-08 18:33:35 +0000[diff] [blame]2886 N->getOperand(0),
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2887 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman5a199552007-10-08 18:33:35 +0000[diff] [blame]2888 else
Dan Gohman8181bd12008-07-27 21:46:04 +0000[diff] [blame]2889 return SDValue(); // No mulhu or equvialent
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2890 if (Created)
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2891 Created->push_back(Q.getNode());
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2892
2893 if (magics.a == 0) {
Eli Friedmanca009722008-11-30 06:02:26 +0000[diff] [blame]2894 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2895 "We shouldn't generate an undefined shift!");
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2896 return DAG.getNode(ISD::SRL, dl, VT, Q,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2897 DAG.getConstant(magics.s, getShiftAmountTy()));
2898 } else {
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2899 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2900 if (Created)
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2901 Created->push_back(NPQ.getNode());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2902 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2903 DAG.getConstant(1, getShiftAmountTy()));
2904 if (Created)
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2905 Created->push_back(NPQ.getNode());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2906 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2907 if (Created)
Gabor Greif1c80d112008-08-28 21:40:38 +0000[diff] [blame]2908 Created->push_back(NPQ.getNode());
Dale Johannesen38496eb2009-02-03 00:47:48 +0000[diff] [blame]2909 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2910 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2911 }
2912}