Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / llvm / c18e940c5a1c050701594ee2b356cd40249505a3 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 702a794fad87d2a562b2dcd9701934281ae1bd5c [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]16#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]17#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]18#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]22#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]39 ARMDisassembler(const MCSubtargetInfo &STI) :
40 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]41 }
42
43 ~ARMDisassembler() {
44 }
45
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
48 uint64_t &size,
49 const MemoryObject &region,
50 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]51 raw_ostream &vStream,
52 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]53
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62 /// Constructor - Initializes the disassembler.
63 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]64 ThumbDisassembler(const MCSubtargetInfo &STI) :
65 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]66 }
67
68 ~ThumbDisassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
74 const MemoryObject &region,
75 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]78
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
81private:
82 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]83 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]84 void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]88static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]89 switch (In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
92 return true;
93 case MCDisassembler::SoftFail:
94 Out = In;
95 return true;
96 case MCDisassembler::Fail:
97 Out = In;
98 return false;
99 }
100 return false;
101}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]102
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]103
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]120 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]122 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]129
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]139 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]141 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]148 unsigned Insn,
149 uint64_t Address,
150 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]154 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]158 uint64_t Address, const void *Decoder);
159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 unsigned Insn,
162 uint64_t Adddress,
163 const void *Decoder);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]182static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]184static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]186static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]188static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]190static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]192static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]194static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]196static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]198static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]200static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]202static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]204static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]206static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]208static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]210static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]212static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]214static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]216static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]218static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]224static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]226static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]228static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]230static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]232static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]234static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]236static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]238static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]240static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]242static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]244static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]246static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]247 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]248static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]249 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]250static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]251 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]252
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]253static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]255static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]257static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]259static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]261static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]277static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
278 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]279static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]287static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]293static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
294 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]295static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]296 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]297static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]299static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]301static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]303static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]304 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]305static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
306 uint64_t Address, const void *Decoder);
307static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]309static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
310 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]311static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]313static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
315
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]316
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]317
318#include "ARMGenDisassemblerTables.inc"
319#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]320#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]321
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]322static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
323 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]324}
325
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]326static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
327 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]328}
329
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]330EDInstInfo *ARMDisassembler::getEDInfo() const {
331 return instInfoARM;
332}
333
334EDInstInfo *ThumbDisassembler::getEDInfo() const {
335 return instInfoARM;
336}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]338DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]339 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]340 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]341 raw_ostream &os,
342 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]343 CommentStream = &cs;
344
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 uint8_t bytes[4];
346
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
348 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
349
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]350 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]351 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
352 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]353 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]354 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355
356 // Encoded as a small-endian 32-bit word in the stream.
357 uint32_t insn = (bytes[3] << 24) |
358 (bytes[2] << 16) |
359 (bytes[1] << 8) |
360 (bytes[0] << 0);
361
362 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]364 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]366 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]367 }
368
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 // VFP and NEON instructions, similarly, are shared between ARM
370 // and Thumb modes.
371 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]372 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]375 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]376 }
377
378 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]379 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]380 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]381 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]382 // Add a fake predicate operand, because we share these instruction
383 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]384 if (!DecodePredicateOperand(MI, 0xE, Address, this))
385 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]386 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]387 }
388
389 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]390 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]391 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]392 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]393 // Add a fake predicate operand, because we share these instruction
394 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]395 if (!DecodePredicateOperand(MI, 0xE, Address, this))
396 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]397 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]398 }
399
400 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]401 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]402 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]403 Size = 4;
404 // Add a fake predicate operand, because we share these instruction
405 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]406 if (!DecodePredicateOperand(MI, 0xE, Address, this))
407 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]408 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]409 }
410
411 MI.clear();
412
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]413 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]414 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415}
416
417namespace llvm {
418extern MCInstrDesc ARMInsts[];
419}
420
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]421/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
422/// immediate Value in the MCInst. The immediate Value has had any PC
423/// adjustment made by the caller. If the instruction is a branch instruction
424/// then isBranch is true, else false. If the getOpInfo() function was set as
425/// part of the setupForSymbolicDisassembly() call then that function is called
426/// to get any symbolic information at the Address for this instruction. If
427/// that returns non-zero then the symbolic information it returns is used to
428/// create an MCExpr and that is added as an operand to the MCInst. If
429/// getOpInfo() returns zero and isBranch is true then a symbol look up for
430/// Value is done and if a symbol is found an MCExpr is created with that, else
431/// an MCExpr with Value is created. This function returns true if it adds an
432/// operand to the MCInst and false otherwise.
433static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
434 bool isBranch, uint64_t InstSize,
435 MCInst &MI, const void *Decoder) {
436 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
437 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
438 if (!getOpInfo)
439 return false;
440
441 struct LLVMOpInfo1 SymbolicOp;
442 SymbolicOp.Value = Value;
443 void *DisInfo = Dis->getDisInfoBlock();
444 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
445 if (isBranch) {
446 LLVMSymbolLookupCallback SymbolLookUp =
447 Dis->getLLVMSymbolLookupCallback();
448 if (SymbolLookUp) {
449 uint64_t ReferenceType;
450 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
451 const char *ReferenceName;
452 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
453 &ReferenceName);
454 if (Name) {
455 SymbolicOp.AddSymbol.Name = Name;
456 SymbolicOp.AddSymbol.Present = true;
457 SymbolicOp.Value = 0;
458 }
459 else {
460 SymbolicOp.Value = Value;
461 }
462 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
463 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
464 }
465 else {
466 return false;
467 }
468 }
469 else {
470 return false;
471 }
472 }
473
474 MCContext *Ctx = Dis->getMCContext();
475 const MCExpr *Add = NULL;
476 if (SymbolicOp.AddSymbol.Present) {
477 if (SymbolicOp.AddSymbol.Name) {
478 StringRef Name(SymbolicOp.AddSymbol.Name);
479 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
480 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
481 } else {
482 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
483 }
484 }
485
486 const MCExpr *Sub = NULL;
487 if (SymbolicOp.SubtractSymbol.Present) {
488 if (SymbolicOp.SubtractSymbol.Name) {
489 StringRef Name(SymbolicOp.SubtractSymbol.Name);
490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
491 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
492 } else {
493 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
494 }
495 }
496
497 const MCExpr *Off = NULL;
498 if (SymbolicOp.Value != 0)
499 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
500
501 const MCExpr *Expr;
502 if (Sub) {
503 const MCExpr *LHS;
504 if (Add)
505 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
506 else
507 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
508 if (Off != 0)
509 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
510 else
511 Expr = LHS;
512 } else if (Add) {
513 if (Off != 0)
514 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
515 else
516 Expr = Add;
517 } else {
518 if (Off != 0)
519 Expr = Off;
520 else
521 Expr = MCConstantExpr::Create(0, *Ctx);
522 }
523
524 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
526 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
529 MI.addOperand(MCOperand::CreateExpr(Expr));
530 else
531 assert("bad SymbolicOp.VariantKind");
532
533 return true;
534}
535
536/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
537/// referenced by a load instruction with the base register that is the Pc.
538/// These can often be values in a literal pool near the Address of the
539/// instruction. The Address of the instruction and its immediate Value are
540/// used as a possible literal pool entry. The SymbolLookUp call back will
541/// return the name of a symbol referenced by the the literal pool's entry if
542/// the referenced address is that of a symbol. Or it will return a pointer to
543/// a literal 'C' string if the referenced address of the literal pool's entry
544/// is an address into a section with 'C' string literals.
545static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
546 const void *Decoder) {
547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
548 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
549 if (SymbolLookUp) {
550 void *DisInfo = Dis->getDisInfoBlock();
551 uint64_t ReferenceType;
552 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
553 const char *ReferenceName;
554 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
555 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
556 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
557 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
558 }
559}
560
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]561// Thumb1 instructions don't have explicit S bits. Rather, they
562// implicitly set CPSR. Since it's not represented in the encoding, the
563// auto-generated decoder won't inject the CPSR operand. We need to fix
564// that as a post-pass.
565static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]568 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]569 for (unsigned i = 0; i < NumOps; ++i, ++I) {
570 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]572 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
574 return;
575 }
576 }
577
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579}
580
581// Most Thumb instructions don't have explicit predicates in the
582// encoding, but rather get their predicates from IT context. We need
583// to fix up the predicate operands using this context information as a
584// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]585MCDisassembler::DecodeStatus
586ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]587 MCDisassembler::DecodeStatus S = Success;
588
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]589 // A few instructions actually have predicates encoded in them. Don't
590 // try to overwrite it if we're seeing one of those.
591 switch (MI.getOpcode()) {
592 case ARM::tBcc:
593 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]594 case ARM::tCBZ:
595 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]596 case ARM::tCPS:
597 case ARM::t2CPS3p:
598 case ARM::t2CPS2p:
599 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]600 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame^]601 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]602 // Some instructions (mostly conditional branches) are not
603 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]604 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]605 S = SoftFail;
606 else
607 return Success;
608 break;
609 case ARM::tB:
610 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]611 case ARM::t2TBB:
612 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]613 // Some instructions (mostly unconditional branches) can
614 // only appears at the end of, or outside of, an IT.
615 if (ITBlock.size() > 1)
616 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]617 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]618 default:
619 break;
620 }
621
622 // If we're in an IT block, base the predicate on that. Otherwise,
623 // assume a predicate of AL.
624 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]625 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]626 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]627 if (CC == 0xF)
628 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]629 ITBlock.pop_back();
630 } else
631 CC = ARMCC::AL;
632
633 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]634 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]635 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]636 for (unsigned i = 0; i < NumOps; ++i, ++I) {
637 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]638 if (OpInfo[i].isPredicate()) {
639 I = MI.insert(I, MCOperand::CreateImm(CC));
640 ++I;
641 if (CC == ARMCC::AL)
642 MI.insert(I, MCOperand::CreateReg(0));
643 else
644 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]645 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]646 }
647 }
648
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]649 I = MI.insert(I, MCOperand::CreateImm(CC));
650 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]651 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]652 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]653 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]655
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]656 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]657}
658
659// Thumb VFP instructions are a special case. Because we share their
660// encodings between ARM and Thumb modes, and they are predicable in ARM
661// mode, the auto-generated decoder will give them an (incorrect)
662// predicate operand. We need to rewrite these operands based on the IT
663// context as a post-pass.
664void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
665 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]666 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]667 CC = ITBlock.back();
668 ITBlock.pop_back();
669 } else
670 CC = ARMCC::AL;
671
672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
673 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
675 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]676 if (OpInfo[i].isPredicate() ) {
677 I->setImm(CC);
678 ++I;
679 if (CC == ARMCC::AL)
680 I->setReg(0);
681 else
682 I->setReg(ARM::CPSR);
683 return;
684 }
685 }
686}
687
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]688DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]689 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]690 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]691 raw_ostream &os,
692 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]693 CommentStream = &cs;
694
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]695 uint8_t bytes[4];
696
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]697 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
698 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
699
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]700 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]701 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
702 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]703 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]704 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]705
706 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]707 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]708 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]709 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]710 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]711 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]712 }
713
714 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]715 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]716 if (result) {
717 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]718 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]719 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]720 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]721 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]722 }
723
724 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]725 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]726 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]727 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]728
729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
730 // the Thumb predicate.
731 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
732 result = MCDisassembler::SoftFail;
733
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]734 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]735
736 // If we find an IT instruction, we need to parse its condition
737 // code and mask operands so that we can apply them correctly
738 // to the subsequent instructions.
739 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]740
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]741 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]742 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]743 unsigned Mask = MI.getOperand(1).getImm();
744 unsigned CondBit0 = Mask >> 4 & 1;
745 unsigned NumTZ = CountTrailingZeros_32(Mask);
746 assert(NumTZ <= 3 && "Invalid IT mask!");
747 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
748 bool T = ((Mask >> Pos) & 1) == CondBit0;
749 if (T)
750 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]751 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]752 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]754
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]755 ITBlock.push_back(firstcond);
756 }
757
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]758 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]759 }
760
761 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]762 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
763 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]764 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]765 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]766
767 uint32_t insn32 = (bytes[3] << 8) |
768 (bytes[2] << 0) |
769 (bytes[1] << 24) |
770 (bytes[0] << 16);
771 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]772 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]773 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]774 Size = 4;
775 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]776 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]777 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]778 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]779 }
780
781 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]782 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]783 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]784 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]785 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]786 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]787 }
788
789 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]790 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]791 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]792 Size = 4;
793 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]794 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]795 }
796
797 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]798 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]799 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]800 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]801 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]802 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]803 }
804
805 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
806 MI.clear();
807 uint32_t NEONLdStInsn = insn32;
808 NEONLdStInsn &= 0xF0FFFFFF;
809 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]810 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]811 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]812 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]813 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]814 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]815 }
816 }
817
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]818 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]819 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]820 uint32_t NEONDataInsn = insn32;
821 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
822 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
823 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]824 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]825 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]826 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]827 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]828 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]829 }
830 }
831
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]832 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]833 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]834}
835
836
837extern "C" void LLVMInitializeARMDisassembler() {
838 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
839 createARMDisassembler);
840 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
841 createThumbDisassembler);
842}
843
844static const unsigned GPRDecoderTable[] = {
845 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
846 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
847 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
848 ARM::R12, ARM::SP, ARM::LR, ARM::PC
849};
850
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]851static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]852 uint64_t Address, const void *Decoder) {
853 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]854 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]855
856 unsigned Register = GPRDecoderTable[RegNo];
857 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]858 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]859}
860
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]861static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]862DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
863 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]864 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]865 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
866}
867
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]868static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]869 uint64_t Address, const void *Decoder) {
870 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]871 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]872 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
873}
874
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]875static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]876 uint64_t Address, const void *Decoder) {
877 unsigned Register = 0;
878 switch (RegNo) {
879 case 0:
880 Register = ARM::R0;
881 break;
882 case 1:
883 Register = ARM::R1;
884 break;
885 case 2:
886 Register = ARM::R2;
887 break;
888 case 3:
889 Register = ARM::R3;
890 break;
891 case 9:
892 Register = ARM::R9;
893 break;
894 case 12:
895 Register = ARM::R12;
896 break;
897 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]898 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]899 }
900
901 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]902 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]903}
904
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]905static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]906 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]907 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
909}
910
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]911static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]912 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
913 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
914 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
915 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
916 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
917 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
918 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
919 ARM::S28, ARM::S29, ARM::S30, ARM::S31
920};
921
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]922static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]923 uint64_t Address, const void *Decoder) {
924 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]925 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]926
927 unsigned Register = SPRDecoderTable[RegNo];
928 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]929 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]930}
931
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]932static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]933 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
934 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
935 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
936 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
937 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
938 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
939 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
940 ARM::D28, ARM::D29, ARM::D30, ARM::D31
941};
942
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]943static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]944 uint64_t Address, const void *Decoder) {
945 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]946 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]947
948 unsigned Register = DPRDecoderTable[RegNo];
949 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]950 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]951}
952
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]953static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]954 uint64_t Address, const void *Decoder) {
955 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]956 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]957 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
958}
959
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]960static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]961DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
962 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]964 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]965 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
966}
967
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]968static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]969 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
970 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
971 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
972 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
973};
974
975
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]976static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]977 uint64_t Address, const void *Decoder) {
978 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]979 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]980 RegNo >>= 1;
981
982 unsigned Register = QPRDecoderTable[RegNo];
983 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]984 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]985}
986
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]987static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]988 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]989 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]990 // AL predicate is not allowed on Thumb1 branches.
991 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]992 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]993 Inst.addOperand(MCOperand::CreateImm(Val));
994 if (Val == ARMCC::AL) {
995 Inst.addOperand(MCOperand::CreateReg(0));
996 } else
997 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]998 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999}
1000
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1001static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1002 uint64_t Address, const void *Decoder) {
1003 if (Val)
1004 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1005 else
1006 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1007 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1008}
1009
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1010static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1011 uint64_t Address, const void *Decoder) {
1012 uint32_t imm = Val & 0xFF;
1013 uint32_t rot = (Val & 0xF00) >> 7;
1014 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
1015 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1016 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1017}
1018
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1019static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1020 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1021 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1022
1023 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1024 unsigned type = fieldFromInstruction32(Val, 5, 2);
1025 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1026
1027 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1029 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1030
1031 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1032 switch (type) {
1033 case 0:
1034 Shift = ARM_AM::lsl;
1035 break;
1036 case 1:
1037 Shift = ARM_AM::lsr;
1038 break;
1039 case 2:
1040 Shift = ARM_AM::asr;
1041 break;
1042 case 3:
1043 Shift = ARM_AM::ror;
1044 break;
1045 }
1046
1047 if (Shift == ARM_AM::ror && imm == 0)
1048 Shift = ARM_AM::rrx;
1049
1050 unsigned Op = Shift | (imm << 3);
1051 Inst.addOperand(MCOperand::CreateImm(Op));
1052
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1053 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1054}
1055
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1056static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1057 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1058 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1059
1060 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1061 unsigned type = fieldFromInstruction32(Val, 5, 2);
1062 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1063
1064 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1065 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1066 return MCDisassembler::Fail;
1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1068 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1069
1070 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1071 switch (type) {
1072 case 0:
1073 Shift = ARM_AM::lsl;
1074 break;
1075 case 1:
1076 Shift = ARM_AM::lsr;
1077 break;
1078 case 2:
1079 Shift = ARM_AM::asr;
1080 break;
1081 case 3:
1082 Shift = ARM_AM::ror;
1083 break;
1084 }
1085
1086 Inst.addOperand(MCOperand::CreateImm(Shift));
1087
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1088 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1089}
1090
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1091static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1092 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1093 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1094
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1095 bool writebackLoad = false;
1096 unsigned writebackReg = 0;
1097 switch (Inst.getOpcode()) {
1098 default:
1099 break;
1100 case ARM::LDMIA_UPD:
1101 case ARM::LDMDB_UPD:
1102 case ARM::LDMIB_UPD:
1103 case ARM::LDMDA_UPD:
1104 case ARM::t2LDMIA_UPD:
1105 case ARM::t2LDMDB_UPD:
1106 writebackLoad = true;
1107 writebackReg = Inst.getOperand(0).getReg();
1108 break;
1109 }
1110
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1111 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1112 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1113 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1114 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1115 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1116 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1117 // Writeback not allowed if Rn is in the target list.
1118 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1119 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1120 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1121 }
1122
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1123 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1124}
1125
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1126static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1127 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1128 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1129
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1130 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1131 unsigned regs = Val & 0xFF;
1132
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1133 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1134 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1135 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1136 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1137 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1138 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1139
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1140 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1141}
1142
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1143static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1144 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1145 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1146
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1147 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1148 unsigned regs = (Val & 0xFF) / 2;
1149
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1151 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1152 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1153 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1154 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1155 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1156
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1157 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1158}
1159
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1160static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1161 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1162 // This operand encodes a mask of contiguous zeros between a specified MSB
1163 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1164 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1165 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1166 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1167 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1168 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1169
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1170 DecodeStatus S = MCDisassembler::Success;
1171 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1172
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1173 uint32_t msb_mask = 0xFFFFFFFF;
1174 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1175 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1176
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1177 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1178 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1179}
1180
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1181static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1182 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1183 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1184
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1185 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1186 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1187 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1188 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1189 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1190 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1191
1192 switch (Inst.getOpcode()) {
1193 case ARM::LDC_OFFSET:
1194 case ARM::LDC_PRE:
1195 case ARM::LDC_POST:
1196 case ARM::LDC_OPTION:
1197 case ARM::LDCL_OFFSET:
1198 case ARM::LDCL_PRE:
1199 case ARM::LDCL_POST:
1200 case ARM::LDCL_OPTION:
1201 case ARM::STC_OFFSET:
1202 case ARM::STC_PRE:
1203 case ARM::STC_POST:
1204 case ARM::STC_OPTION:
1205 case ARM::STCL_OFFSET:
1206 case ARM::STCL_PRE:
1207 case ARM::STCL_POST:
1208 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1209 case ARM::t2LDC_OFFSET:
1210 case ARM::t2LDC_PRE:
1211 case ARM::t2LDC_POST:
1212 case ARM::t2LDC_OPTION:
1213 case ARM::t2LDCL_OFFSET:
1214 case ARM::t2LDCL_PRE:
1215 case ARM::t2LDCL_POST:
1216 case ARM::t2LDCL_OPTION:
1217 case ARM::t2STC_OFFSET:
1218 case ARM::t2STC_PRE:
1219 case ARM::t2STC_POST:
1220 case ARM::t2STC_OPTION:
1221 case ARM::t2STCL_OFFSET:
1222 case ARM::t2STCL_PRE:
1223 case ARM::t2STCL_POST:
1224 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1225 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1226 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1227 break;
1228 default:
1229 break;
1230 }
1231
1232 Inst.addOperand(MCOperand::CreateImm(coproc));
1233 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1235 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1236
1237 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1238 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1239
1240 bool writeback = (P == 0) || (W == 1);
1241 unsigned idx_mode = 0;
1242 if (P && writeback)
1243 idx_mode = ARMII::IndexModePre;
1244 else if (!P && writeback)
1245 idx_mode = ARMII::IndexModePost;
1246
1247 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1248 case ARM::t2LDC2_OFFSET:
1249 case ARM::t2LDC2L_OFFSET:
1250 case ARM::t2LDC2_PRE:
1251 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1252 case ARM::t2STC2_OFFSET:
1253 case ARM::t2STC2L_OFFSET:
1254 case ARM::t2STC2_PRE:
1255 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1256 case ARM::LDC2_OFFSET:
1257 case ARM::LDC2L_OFFSET:
1258 case ARM::LDC2_PRE:
1259 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1260 case ARM::STC2_OFFSET:
1261 case ARM::STC2L_OFFSET:
1262 case ARM::STC2_PRE:
1263 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1264 case ARM::t2LDC_OFFSET:
1265 case ARM::t2LDCL_OFFSET:
1266 case ARM::t2LDC_PRE:
1267 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1268 case ARM::t2STC_OFFSET:
1269 case ARM::t2STCL_OFFSET:
1270 case ARM::t2STC_PRE:
1271 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1272 case ARM::LDC_OFFSET:
1273 case ARM::LDCL_OFFSET:
1274 case ARM::LDC_PRE:
1275 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1276 case ARM::STC_OFFSET:
1277 case ARM::STCL_OFFSET:
1278 case ARM::STC_PRE:
1279 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1280 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1281 Inst.addOperand(MCOperand::CreateImm(imm));
1282 break;
1283 case ARM::t2LDC2_POST:
1284 case ARM::t2LDC2L_POST:
1285 case ARM::t2STC2_POST:
1286 case ARM::t2STC2L_POST:
1287 case ARM::LDC2_POST:
1288 case ARM::LDC2L_POST:
1289 case ARM::STC2_POST:
1290 case ARM::STC2L_POST:
1291 case ARM::t2LDC_POST:
1292 case ARM::t2LDCL_POST:
1293 case ARM::t2STC_POST:
1294 case ARM::t2STCL_POST:
1295 case ARM::LDC_POST:
1296 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1297 case ARM::STC_POST:
1298 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1299 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1300 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1301 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1302 // The 'option' variant doesn't encode 'U' in the immediate since
1303 // the immediate is unsigned [0,255].
1304 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1305 break;
1306 }
1307
1308 switch (Inst.getOpcode()) {
1309 case ARM::LDC_OFFSET:
1310 case ARM::LDC_PRE:
1311 case ARM::LDC_POST:
1312 case ARM::LDC_OPTION:
1313 case ARM::LDCL_OFFSET:
1314 case ARM::LDCL_PRE:
1315 case ARM::LDCL_POST:
1316 case ARM::LDCL_OPTION:
1317 case ARM::STC_OFFSET:
1318 case ARM::STC_PRE:
1319 case ARM::STC_POST:
1320 case ARM::STC_OPTION:
1321 case ARM::STCL_OFFSET:
1322 case ARM::STCL_PRE:
1323 case ARM::STCL_POST:
1324 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1325 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1326 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1327 break;
1328 default:
1329 break;
1330 }
1331
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1332 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1333}
1334
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1335static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1336DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1337 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1338 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1339
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1340 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1341 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1342 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1343 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1344 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1345 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1346 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1347 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1348
1349 // On stores, the writeback operand precedes Rt.
1350 switch (Inst.getOpcode()) {
1351 case ARM::STR_POST_IMM:
1352 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1353 case ARM::STRB_POST_IMM:
1354 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1355 case ARM::STRT_POST_REG:
1356 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1357 case ARM::STRBT_POST_REG:
1358 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1360 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1361 break;
1362 default:
1363 break;
1364 }
1365
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1367 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1368
1369 // On loads, the writeback operand comes after Rt.
1370 switch (Inst.getOpcode()) {
1371 case ARM::LDR_POST_IMM:
1372 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1373 case ARM::LDRB_POST_IMM:
1374 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1375 case ARM::LDRBT_POST_REG:
1376 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1377 case ARM::LDRT_POST_REG:
1378 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1380 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1381 break;
1382 default:
1383 break;
1384 }
1385
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1387 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1388
1389 ARM_AM::AddrOpc Op = ARM_AM::add;
1390 if (!fieldFromInstruction32(Insn, 23, 1))
1391 Op = ARM_AM::sub;
1392
1393 bool writeback = (P == 0) || (W == 1);
1394 unsigned idx_mode = 0;
1395 if (P && writeback)
1396 idx_mode = ARMII::IndexModePre;
1397 else if (!P && writeback)
1398 idx_mode = ARMII::IndexModePost;
1399
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1400 if (writeback && (Rn == 15 || Rn == Rt))
1401 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1402
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1403 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1404 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1405 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1406 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1407 switch( fieldFromInstruction32(Insn, 5, 2)) {
1408 case 0:
1409 Opc = ARM_AM::lsl;
1410 break;
1411 case 1:
1412 Opc = ARM_AM::lsr;
1413 break;
1414 case 2:
1415 Opc = ARM_AM::asr;
1416 break;
1417 case 3:
1418 Opc = ARM_AM::ror;
1419 break;
1420 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1421 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1422 }
1423 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1424 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1425
1426 Inst.addOperand(MCOperand::CreateImm(imm));
1427 } else {
1428 Inst.addOperand(MCOperand::CreateReg(0));
1429 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1430 Inst.addOperand(MCOperand::CreateImm(tmp));
1431 }
1432
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1433 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1434 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1435
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1436 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1437}
1438
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1439static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1440 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1441 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1442
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1443 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1444 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1445 unsigned type = fieldFromInstruction32(Val, 5, 2);
1446 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1447 unsigned U = fieldFromInstruction32(Val, 12, 1);
1448
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1449 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1450 switch (type) {
1451 case 0:
1452 ShOp = ARM_AM::lsl;
1453 break;
1454 case 1:
1455 ShOp = ARM_AM::lsr;
1456 break;
1457 case 2:
1458 ShOp = ARM_AM::asr;
1459 break;
1460 case 3:
1461 ShOp = ARM_AM::ror;
1462 break;
1463 }
1464
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1466 return MCDisassembler::Fail;
1467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1468 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1469 unsigned shift;
1470 if (U)
1471 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1472 else
1473 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1474 Inst.addOperand(MCOperand::CreateImm(shift));
1475
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1476 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1477}
1478
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1479static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1480DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1481 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1482 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1483
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1484 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1485 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1486 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1487 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1488 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1489 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1490 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1491 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1492 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1493
1494 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1495
1496 // For {LD,ST}RD, Rt must be even, else undefined.
1497 switch (Inst.getOpcode()) {
1498 case ARM::STRD:
1499 case ARM::STRD_PRE:
1500 case ARM::STRD_POST:
1501 case ARM::LDRD:
1502 case ARM::LDRD_PRE:
1503 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1504 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1505 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1506 default:
1507 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1508 }
1509
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1510 if (writeback) { // Writeback
1511 if (P)
1512 U |= ARMII::IndexModePre << 9;
1513 else
1514 U |= ARMII::IndexModePost << 9;
1515
1516 // On stores, the writeback operand precedes Rt.
1517 switch (Inst.getOpcode()) {
1518 case ARM::STRD:
1519 case ARM::STRD_PRE:
1520 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1521 case ARM::STRH:
1522 case ARM::STRH_PRE:
1523 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1525 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1526 break;
1527 default:
1528 break;
1529 }
1530 }
1531
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1533 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1534 switch (Inst.getOpcode()) {
1535 case ARM::STRD:
1536 case ARM::STRD_PRE:
1537 case ARM::STRD_POST:
1538 case ARM::LDRD:
1539 case ARM::LDRD_PRE:
1540 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1541 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1542 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1543 break;
1544 default:
1545 break;
1546 }
1547
1548 if (writeback) {
1549 // On loads, the writeback operand comes after Rt.
1550 switch (Inst.getOpcode()) {
1551 case ARM::LDRD:
1552 case ARM::LDRD_PRE:
1553 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1554 case ARM::LDRH:
1555 case ARM::LDRH_PRE:
1556 case ARM::LDRH_POST:
1557 case ARM::LDRSH:
1558 case ARM::LDRSH_PRE:
1559 case ARM::LDRSH_POST:
1560 case ARM::LDRSB:
1561 case ARM::LDRSB_PRE:
1562 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1563 case ARM::LDRHTr:
1564 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1566 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1567 break;
1568 default:
1569 break;
1570 }
1571 }
1572
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1574 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1575
1576 if (type) {
1577 Inst.addOperand(MCOperand::CreateReg(0));
1578 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1579 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1581 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1582 Inst.addOperand(MCOperand::CreateImm(U));
1583 }
1584
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1585 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1586 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1587
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1588 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1589}
1590
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1591static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1592 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1593 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1594
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1595 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1596 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1597
1598 switch (mode) {
1599 case 0:
1600 mode = ARM_AM::da;
1601 break;
1602 case 1:
1603 mode = ARM_AM::ia;
1604 break;
1605 case 2:
1606 mode = ARM_AM::db;
1607 break;
1608 case 3:
1609 mode = ARM_AM::ib;
1610 break;
1611 }
1612
1613 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1615 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1616
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1617 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1618}
1619
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1620static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1621 unsigned Insn,
1622 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1623 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1624
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1625 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1626 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1627 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1628
1629 if (pred == 0xF) {
1630 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1631 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1632 Inst.setOpcode(ARM::RFEDA);
1633 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1634 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1635 Inst.setOpcode(ARM::RFEDA_UPD);
1636 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1637 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1638 Inst.setOpcode(ARM::RFEDB);
1639 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1640 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1641 Inst.setOpcode(ARM::RFEDB_UPD);
1642 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1643 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1644 Inst.setOpcode(ARM::RFEIA);
1645 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1646 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1647 Inst.setOpcode(ARM::RFEIA_UPD);
1648 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1649 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1650 Inst.setOpcode(ARM::RFEIB);
1651 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1652 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1653 Inst.setOpcode(ARM::RFEIB_UPD);
1654 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1655 case ARM::STMDA:
1656 Inst.setOpcode(ARM::SRSDA);
1657 break;
1658 case ARM::STMDA_UPD:
1659 Inst.setOpcode(ARM::SRSDA_UPD);
1660 break;
1661 case ARM::STMDB:
1662 Inst.setOpcode(ARM::SRSDB);
1663 break;
1664 case ARM::STMDB_UPD:
1665 Inst.setOpcode(ARM::SRSDB_UPD);
1666 break;
1667 case ARM::STMIA:
1668 Inst.setOpcode(ARM::SRSIA);
1669 break;
1670 case ARM::STMIA_UPD:
1671 Inst.setOpcode(ARM::SRSIA_UPD);
1672 break;
1673 case ARM::STMIB:
1674 Inst.setOpcode(ARM::SRSIB);
1675 break;
1676 case ARM::STMIB_UPD:
1677 Inst.setOpcode(ARM::SRSIB_UPD);
1678 break;
1679 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1680 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1681 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1682
1683 // For stores (which become SRS's, the only operand is the mode.
1684 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1685 Inst.addOperand(
1686 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1687 return S;
1688 }
1689
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1690 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1691 }
1692
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1694 return MCDisassembler::Fail;
1695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1696 return MCDisassembler::Fail; // Tied
1697 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1698 return MCDisassembler::Fail;
1699 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1700 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1701
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1702 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1703}
1704
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1705static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1706 uint64_t Address, const void *Decoder) {
1707 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1708 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1709 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1710 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1711
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1712 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1713
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1714 // imod == '01' --> UNPREDICTABLE
1715 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1716 // return failure here. The '01' imod value is unprintable, so there's
1717 // nothing useful we could do even if we returned UNPREDICTABLE.
1718
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1719 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1720
1721 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1722 Inst.setOpcode(ARM::CPS3p);
1723 Inst.addOperand(MCOperand::CreateImm(imod));
1724 Inst.addOperand(MCOperand::CreateImm(iflags));
1725 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1726 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1727 Inst.setOpcode(ARM::CPS2p);
1728 Inst.addOperand(MCOperand::CreateImm(imod));
1729 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1730 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1731 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1732 Inst.setOpcode(ARM::CPS1p);
1733 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1734 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1735 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1736 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1737 Inst.setOpcode(ARM::CPS1p);
1738 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1739 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1740 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1741
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1742 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1743}
1744
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1745static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1746 uint64_t Address, const void *Decoder) {
1747 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1748 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1749 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1750 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1751
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1752 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1753
1754 // imod == '01' --> UNPREDICTABLE
1755 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1756 // return failure here. The '01' imod value is unprintable, so there's
1757 // nothing useful we could do even if we returned UNPREDICTABLE.
1758
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1759 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1760
1761 if (imod && M) {
1762 Inst.setOpcode(ARM::t2CPS3p);
1763 Inst.addOperand(MCOperand::CreateImm(imod));
1764 Inst.addOperand(MCOperand::CreateImm(iflags));
1765 Inst.addOperand(MCOperand::CreateImm(mode));
1766 } else if (imod && !M) {
1767 Inst.setOpcode(ARM::t2CPS2p);
1768 Inst.addOperand(MCOperand::CreateImm(imod));
1769 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1770 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1771 } else if (!imod && M) {
1772 Inst.setOpcode(ARM::t2CPS1p);
1773 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1774 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1775 } else {
1776 // imod == '00' && M == '0' --> UNPREDICTABLE
1777 Inst.setOpcode(ARM::t2CPS1p);
1778 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1779 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1780 }
1781
1782 return S;
1783}
1784
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1785static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1786 uint64_t Address, const void *Decoder) {
1787 DecodeStatus S = MCDisassembler::Success;
1788
1789 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1790 unsigned imm = 0;
1791
1792 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1793 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1794 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1795 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1796
1797 if (Inst.getOpcode() == ARM::t2MOVTi16)
1798 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1799 return MCDisassembler::Fail;
1800 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1801 return MCDisassembler::Fail;
1802
1803 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1804 Inst.addOperand(MCOperand::CreateImm(imm));
1805
1806 return S;
1807}
1808
1809static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1810 uint64_t Address, const void *Decoder) {
1811 DecodeStatus S = MCDisassembler::Success;
1812
1813 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1814 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1815 unsigned imm = 0;
1816
1817 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1818 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1819
1820 if (Inst.getOpcode() == ARM::MOVTi16)
1821 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1822 return MCDisassembler::Fail;
1823 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1824 return MCDisassembler::Fail;
1825
1826 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1827 Inst.addOperand(MCOperand::CreateImm(imm));
1828
1829 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1830 return MCDisassembler::Fail;
1831
1832 return S;
1833}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1834
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1835static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1836 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1837 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1838
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1839 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1840 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1841 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1842 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1843 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1844
1845 if (pred == 0xF)
1846 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1847
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1849 return MCDisassembler::Fail;
1850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1851 return MCDisassembler::Fail;
1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1853 return MCDisassembler::Fail;
1854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1855 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1856
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1857 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1858 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1859
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1860 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1861}
1862
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1863static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1864 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1865 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1866
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1867 unsigned add = fieldFromInstruction32(Val, 12, 1);
1868 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1869 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1870
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1871 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1872 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1873
1874 if (!add) imm *= -1;
1875 if (imm == 0 && !add) imm = INT32_MIN;
1876 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1877 if (Rn == 15)
1878 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1879
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1880 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1881}
1882
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1883static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1884 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1885 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1886
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1887 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1888 unsigned U = fieldFromInstruction32(Val, 8, 1);
1889 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1890
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1892 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1893
1894 if (U)
1895 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1896 else
1897 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1898
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1899 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1900}
1901
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1902static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1903 uint64_t Address, const void *Decoder) {
1904 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1905}
1906
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1907static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1908DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1909 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1910 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1911
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1912 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1913 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1914
1915 if (pred == 0xF) {
1916 Inst.setOpcode(ARM::BLXi);
1917 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1918 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1919 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1920 }
1921
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1922 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1923 4, Inst, Decoder))
1924 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1925 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1926 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1927
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1928 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1929}
1930
1931
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1932static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1933 uint64_t Address, const void *Decoder) {
1934 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1935 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1936}
1937
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1938static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1939 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1940 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1941
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1942 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1943 unsigned align = fieldFromInstruction32(Val, 4, 2);
1944
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1946 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1947 if (!align)
1948 Inst.addOperand(MCOperand::CreateImm(0));
1949 else
1950 Inst.addOperand(MCOperand::CreateImm(4 << align));
1951
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1952 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1953}
1954
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1955static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1956 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1957 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1958
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1960 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1961 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1962 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1963 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1964 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1965
1966 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1967 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1968 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1969
1970 // Second output register
1971 switch (Inst.getOpcode()) {
1972 case ARM::VLD1q8:
1973 case ARM::VLD1q16:
1974 case ARM::VLD1q32:
1975 case ARM::VLD1q64:
1976 case ARM::VLD1q8_UPD:
1977 case ARM::VLD1q16_UPD:
1978 case ARM::VLD1q32_UPD:
1979 case ARM::VLD1q64_UPD:
1980 case ARM::VLD1d8T:
1981 case ARM::VLD1d16T:
1982 case ARM::VLD1d32T:
1983 case ARM::VLD1d64T:
1984 case ARM::VLD1d8T_UPD:
1985 case ARM::VLD1d16T_UPD:
1986 case ARM::VLD1d32T_UPD:
1987 case ARM::VLD1d64T_UPD:
1988 case ARM::VLD1d8Q:
1989 case ARM::VLD1d16Q:
1990 case ARM::VLD1d32Q:
1991 case ARM::VLD1d64Q:
1992 case ARM::VLD1d8Q_UPD:
1993 case ARM::VLD1d16Q_UPD:
1994 case ARM::VLD1d32Q_UPD:
1995 case ARM::VLD1d64Q_UPD:
1996 case ARM::VLD2d8:
1997 case ARM::VLD2d16:
1998 case ARM::VLD2d32:
1999 case ARM::VLD2d8_UPD:
2000 case ARM::VLD2d16_UPD:
2001 case ARM::VLD2d32_UPD:
2002 case ARM::VLD2q8:
2003 case ARM::VLD2q16:
2004 case ARM::VLD2q32:
2005 case ARM::VLD2q8_UPD:
2006 case ARM::VLD2q16_UPD:
2007 case ARM::VLD2q32_UPD:
2008 case ARM::VLD3d8:
2009 case ARM::VLD3d16:
2010 case ARM::VLD3d32:
2011 case ARM::VLD3d8_UPD:
2012 case ARM::VLD3d16_UPD:
2013 case ARM::VLD3d32_UPD:
2014 case ARM::VLD4d8:
2015 case ARM::VLD4d16:
2016 case ARM::VLD4d32:
2017 case ARM::VLD4d8_UPD:
2018 case ARM::VLD4d16_UPD:
2019 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2020 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2021 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2022 break;
2023 case ARM::VLD2b8:
2024 case ARM::VLD2b16:
2025 case ARM::VLD2b32:
2026 case ARM::VLD2b8_UPD:
2027 case ARM::VLD2b16_UPD:
2028 case ARM::VLD2b32_UPD:
2029 case ARM::VLD3q8:
2030 case ARM::VLD3q16:
2031 case ARM::VLD3q32:
2032 case ARM::VLD3q8_UPD:
2033 case ARM::VLD3q16_UPD:
2034 case ARM::VLD3q32_UPD:
2035 case ARM::VLD4q8:
2036 case ARM::VLD4q16:
2037 case ARM::VLD4q32:
2038 case ARM::VLD4q8_UPD:
2039 case ARM::VLD4q16_UPD:
2040 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2041 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2042 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2043 default:
2044 break;
2045 }
2046
2047 // Third output register
2048 switch(Inst.getOpcode()) {
2049 case ARM::VLD1d8T:
2050 case ARM::VLD1d16T:
2051 case ARM::VLD1d32T:
2052 case ARM::VLD1d64T:
2053 case ARM::VLD1d8T_UPD:
2054 case ARM::VLD1d16T_UPD:
2055 case ARM::VLD1d32T_UPD:
2056 case ARM::VLD1d64T_UPD:
2057 case ARM::VLD1d8Q:
2058 case ARM::VLD1d16Q:
2059 case ARM::VLD1d32Q:
2060 case ARM::VLD1d64Q:
2061 case ARM::VLD1d8Q_UPD:
2062 case ARM::VLD1d16Q_UPD:
2063 case ARM::VLD1d32Q_UPD:
2064 case ARM::VLD1d64Q_UPD:
2065 case ARM::VLD2q8:
2066 case ARM::VLD2q16:
2067 case ARM::VLD2q32:
2068 case ARM::VLD2q8_UPD:
2069 case ARM::VLD2q16_UPD:
2070 case ARM::VLD2q32_UPD:
2071 case ARM::VLD3d8:
2072 case ARM::VLD3d16:
2073 case ARM::VLD3d32:
2074 case ARM::VLD3d8_UPD:
2075 case ARM::VLD3d16_UPD:
2076 case ARM::VLD3d32_UPD:
2077 case ARM::VLD4d8:
2078 case ARM::VLD4d16:
2079 case ARM::VLD4d32:
2080 case ARM::VLD4d8_UPD:
2081 case ARM::VLD4d16_UPD:
2082 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2083 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2084 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2085 break;
2086 case ARM::VLD3q8:
2087 case ARM::VLD3q16:
2088 case ARM::VLD3q32:
2089 case ARM::VLD3q8_UPD:
2090 case ARM::VLD3q16_UPD:
2091 case ARM::VLD3q32_UPD:
2092 case ARM::VLD4q8:
2093 case ARM::VLD4q16:
2094 case ARM::VLD4q32:
2095 case ARM::VLD4q8_UPD:
2096 case ARM::VLD4q16_UPD:
2097 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2098 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2099 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2100 break;
2101 default:
2102 break;
2103 }
2104
2105 // Fourth output register
2106 switch (Inst.getOpcode()) {
2107 case ARM::VLD1d8Q:
2108 case ARM::VLD1d16Q:
2109 case ARM::VLD1d32Q:
2110 case ARM::VLD1d64Q:
2111 case ARM::VLD1d8Q_UPD:
2112 case ARM::VLD1d16Q_UPD:
2113 case ARM::VLD1d32Q_UPD:
2114 case ARM::VLD1d64Q_UPD:
2115 case ARM::VLD2q8:
2116 case ARM::VLD2q16:
2117 case ARM::VLD2q32:
2118 case ARM::VLD2q8_UPD:
2119 case ARM::VLD2q16_UPD:
2120 case ARM::VLD2q32_UPD:
2121 case ARM::VLD4d8:
2122 case ARM::VLD4d16:
2123 case ARM::VLD4d32:
2124 case ARM::VLD4d8_UPD:
2125 case ARM::VLD4d16_UPD:
2126 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2127 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2128 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2129 break;
2130 case ARM::VLD4q8:
2131 case ARM::VLD4q16:
2132 case ARM::VLD4q32:
2133 case ARM::VLD4q8_UPD:
2134 case ARM::VLD4q16_UPD:
2135 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2136 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2137 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2138 break;
2139 default:
2140 break;
2141 }
2142
2143 // Writeback operand
2144 switch (Inst.getOpcode()) {
2145 case ARM::VLD1d8_UPD:
2146 case ARM::VLD1d16_UPD:
2147 case ARM::VLD1d32_UPD:
2148 case ARM::VLD1d64_UPD:
2149 case ARM::VLD1q8_UPD:
2150 case ARM::VLD1q16_UPD:
2151 case ARM::VLD1q32_UPD:
2152 case ARM::VLD1q64_UPD:
2153 case ARM::VLD1d8T_UPD:
2154 case ARM::VLD1d16T_UPD:
2155 case ARM::VLD1d32T_UPD:
2156 case ARM::VLD1d64T_UPD:
2157 case ARM::VLD1d8Q_UPD:
2158 case ARM::VLD1d16Q_UPD:
2159 case ARM::VLD1d32Q_UPD:
2160 case ARM::VLD1d64Q_UPD:
2161 case ARM::VLD2d8_UPD:
2162 case ARM::VLD2d16_UPD:
2163 case ARM::VLD2d32_UPD:
2164 case ARM::VLD2q8_UPD:
2165 case ARM::VLD2q16_UPD:
2166 case ARM::VLD2q32_UPD:
2167 case ARM::VLD2b8_UPD:
2168 case ARM::VLD2b16_UPD:
2169 case ARM::VLD2b32_UPD:
2170 case ARM::VLD3d8_UPD:
2171 case ARM::VLD3d16_UPD:
2172 case ARM::VLD3d32_UPD:
2173 case ARM::VLD3q8_UPD:
2174 case ARM::VLD3q16_UPD:
2175 case ARM::VLD3q32_UPD:
2176 case ARM::VLD4d8_UPD:
2177 case ARM::VLD4d16_UPD:
2178 case ARM::VLD4d32_UPD:
2179 case ARM::VLD4q8_UPD:
2180 case ARM::VLD4q16_UPD:
2181 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2182 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2183 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2184 break;
2185 default:
2186 break;
2187 }
2188
2189 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2190 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2191 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2192
2193 // AddrMode6 Offset (register)
2194 if (Rm == 0xD)
2195 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2196 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2198 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2199 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2200
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2201 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2202}
2203
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2204static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2205 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2206 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2207
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2208 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2209 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2210 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2211 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2212 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2213 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2214
2215 // Writeback Operand
2216 switch (Inst.getOpcode()) {
2217 case ARM::VST1d8_UPD:
2218 case ARM::VST1d16_UPD:
2219 case ARM::VST1d32_UPD:
2220 case ARM::VST1d64_UPD:
2221 case ARM::VST1q8_UPD:
2222 case ARM::VST1q16_UPD:
2223 case ARM::VST1q32_UPD:
2224 case ARM::VST1q64_UPD:
2225 case ARM::VST1d8T_UPD:
2226 case ARM::VST1d16T_UPD:
2227 case ARM::VST1d32T_UPD:
2228 case ARM::VST1d64T_UPD:
2229 case ARM::VST1d8Q_UPD:
2230 case ARM::VST1d16Q_UPD:
2231 case ARM::VST1d32Q_UPD:
2232 case ARM::VST1d64Q_UPD:
2233 case ARM::VST2d8_UPD:
2234 case ARM::VST2d16_UPD:
2235 case ARM::VST2d32_UPD:
2236 case ARM::VST2q8_UPD:
2237 case ARM::VST2q16_UPD:
2238 case ARM::VST2q32_UPD:
2239 case ARM::VST2b8_UPD:
2240 case ARM::VST2b16_UPD:
2241 case ARM::VST2b32_UPD:
2242 case ARM::VST3d8_UPD:
2243 case ARM::VST3d16_UPD:
2244 case ARM::VST3d32_UPD:
2245 case ARM::VST3q8_UPD:
2246 case ARM::VST3q16_UPD:
2247 case ARM::VST3q32_UPD:
2248 case ARM::VST4d8_UPD:
2249 case ARM::VST4d16_UPD:
2250 case ARM::VST4d32_UPD:
2251 case ARM::VST4q8_UPD:
2252 case ARM::VST4q16_UPD:
2253 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2254 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2255 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2256 break;
2257 default:
2258 break;
2259 }
2260
2261 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2262 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2263 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2264
2265 // AddrMode6 Offset (register)
2266 if (Rm == 0xD)
2267 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2268 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2270 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2271 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2272
2273 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2274 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2275 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2276
2277 // Second input register
2278 switch (Inst.getOpcode()) {
2279 case ARM::VST1q8:
2280 case ARM::VST1q16:
2281 case ARM::VST1q32:
2282 case ARM::VST1q64:
2283 case ARM::VST1q8_UPD:
2284 case ARM::VST1q16_UPD:
2285 case ARM::VST1q32_UPD:
2286 case ARM::VST1q64_UPD:
2287 case ARM::VST1d8T:
2288 case ARM::VST1d16T:
2289 case ARM::VST1d32T:
2290 case ARM::VST1d64T:
2291 case ARM::VST1d8T_UPD:
2292 case ARM::VST1d16T_UPD:
2293 case ARM::VST1d32T_UPD:
2294 case ARM::VST1d64T_UPD:
2295 case ARM::VST1d8Q:
2296 case ARM::VST1d16Q:
2297 case ARM::VST1d32Q:
2298 case ARM::VST1d64Q:
2299 case ARM::VST1d8Q_UPD:
2300 case ARM::VST1d16Q_UPD:
2301 case ARM::VST1d32Q_UPD:
2302 case ARM::VST1d64Q_UPD:
2303 case ARM::VST2d8:
2304 case ARM::VST2d16:
2305 case ARM::VST2d32:
2306 case ARM::VST2d8_UPD:
2307 case ARM::VST2d16_UPD:
2308 case ARM::VST2d32_UPD:
2309 case ARM::VST2q8:
2310 case ARM::VST2q16:
2311 case ARM::VST2q32:
2312 case ARM::VST2q8_UPD:
2313 case ARM::VST2q16_UPD:
2314 case ARM::VST2q32_UPD:
2315 case ARM::VST3d8:
2316 case ARM::VST3d16:
2317 case ARM::VST3d32:
2318 case ARM::VST3d8_UPD:
2319 case ARM::VST3d16_UPD:
2320 case ARM::VST3d32_UPD:
2321 case ARM::VST4d8:
2322 case ARM::VST4d16:
2323 case ARM::VST4d32:
2324 case ARM::VST4d8_UPD:
2325 case ARM::VST4d16_UPD:
2326 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2327 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2328 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2329 break;
2330 case ARM::VST2b8:
2331 case ARM::VST2b16:
2332 case ARM::VST2b32:
2333 case ARM::VST2b8_UPD:
2334 case ARM::VST2b16_UPD:
2335 case ARM::VST2b32_UPD:
2336 case ARM::VST3q8:
2337 case ARM::VST3q16:
2338 case ARM::VST3q32:
2339 case ARM::VST3q8_UPD:
2340 case ARM::VST3q16_UPD:
2341 case ARM::VST3q32_UPD:
2342 case ARM::VST4q8:
2343 case ARM::VST4q16:
2344 case ARM::VST4q32:
2345 case ARM::VST4q8_UPD:
2346 case ARM::VST4q16_UPD:
2347 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2348 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2349 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2350 break;
2351 default:
2352 break;
2353 }
2354
2355 // Third input register
2356 switch (Inst.getOpcode()) {
2357 case ARM::VST1d8T:
2358 case ARM::VST1d16T:
2359 case ARM::VST1d32T:
2360 case ARM::VST1d64T:
2361 case ARM::VST1d8T_UPD:
2362 case ARM::VST1d16T_UPD:
2363 case ARM::VST1d32T_UPD:
2364 case ARM::VST1d64T_UPD:
2365 case ARM::VST1d8Q:
2366 case ARM::VST1d16Q:
2367 case ARM::VST1d32Q:
2368 case ARM::VST1d64Q:
2369 case ARM::VST1d8Q_UPD:
2370 case ARM::VST1d16Q_UPD:
2371 case ARM::VST1d32Q_UPD:
2372 case ARM::VST1d64Q_UPD:
2373 case ARM::VST2q8:
2374 case ARM::VST2q16:
2375 case ARM::VST2q32:
2376 case ARM::VST2q8_UPD:
2377 case ARM::VST2q16_UPD:
2378 case ARM::VST2q32_UPD:
2379 case ARM::VST3d8:
2380 case ARM::VST3d16:
2381 case ARM::VST3d32:
2382 case ARM::VST3d8_UPD:
2383 case ARM::VST3d16_UPD:
2384 case ARM::VST3d32_UPD:
2385 case ARM::VST4d8:
2386 case ARM::VST4d16:
2387 case ARM::VST4d32:
2388 case ARM::VST4d8_UPD:
2389 case ARM::VST4d16_UPD:
2390 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2391 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2392 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2393 break;
2394 case ARM::VST3q8:
2395 case ARM::VST3q16:
2396 case ARM::VST3q32:
2397 case ARM::VST3q8_UPD:
2398 case ARM::VST3q16_UPD:
2399 case ARM::VST3q32_UPD:
2400 case ARM::VST4q8:
2401 case ARM::VST4q16:
2402 case ARM::VST4q32:
2403 case ARM::VST4q8_UPD:
2404 case ARM::VST4q16_UPD:
2405 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2406 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2407 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2408 break;
2409 default:
2410 break;
2411 }
2412
2413 // Fourth input register
2414 switch (Inst.getOpcode()) {
2415 case ARM::VST1d8Q:
2416 case ARM::VST1d16Q:
2417 case ARM::VST1d32Q:
2418 case ARM::VST1d64Q:
2419 case ARM::VST1d8Q_UPD:
2420 case ARM::VST1d16Q_UPD:
2421 case ARM::VST1d32Q_UPD:
2422 case ARM::VST1d64Q_UPD:
2423 case ARM::VST2q8:
2424 case ARM::VST2q16:
2425 case ARM::VST2q32:
2426 case ARM::VST2q8_UPD:
2427 case ARM::VST2q16_UPD:
2428 case ARM::VST2q32_UPD:
2429 case ARM::VST4d8:
2430 case ARM::VST4d16:
2431 case ARM::VST4d32:
2432 case ARM::VST4d8_UPD:
2433 case ARM::VST4d16_UPD:
2434 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2435 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2436 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2437 break;
2438 case ARM::VST4q8:
2439 case ARM::VST4q16:
2440 case ARM::VST4q32:
2441 case ARM::VST4q8_UPD:
2442 case ARM::VST4q16_UPD:
2443 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2444 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2445 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2446 break;
2447 default:
2448 break;
2449 }
2450
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2451 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2452}
2453
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2454static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2455 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2456 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2457
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2458 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2459 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2460 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2461 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2462 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2463 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2464 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2465
2466 align *= (1 << size);
2467
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2468 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2469 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2470 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2471 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2472 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2473 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2474 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2476 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2477 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2478
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2480 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2481 Inst.addOperand(MCOperand::CreateImm(align));
2482
2483 if (Rm == 0xD)
2484 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2485 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2487 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2488 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2489
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2490 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2491}
2492
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2493static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2494 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2495 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2496
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2497 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2498 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2499 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2500 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2501 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2502 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2503 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2504 align *= 2*size;
2505
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2506 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2507 return MCDisassembler::Fail;
2508 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2509 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2510 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2512 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2513 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2514
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2516 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2517 Inst.addOperand(MCOperand::CreateImm(align));
2518
2519 if (Rm == 0xD)
2520 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2521 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2523 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2524 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2525
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2526 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2527}
2528
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2529static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2530 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2531 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2532
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2533 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2534 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2535 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2536 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2537 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2538
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2539 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2540 return MCDisassembler::Fail;
2541 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2542 return MCDisassembler::Fail;
2543 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2544 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2545 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2546 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2547 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2548 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2549
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2551 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2552 Inst.addOperand(MCOperand::CreateImm(0));
2553
2554 if (Rm == 0xD)
2555 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2556 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2558 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2559 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2560
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2561 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2562}
2563
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2564static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2565 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2566 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2567
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2568 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2569 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2570 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2571 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2572 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2573 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2574 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2575
2576 if (size == 0x3) {
2577 size = 4;
2578 align = 16;
2579 } else {
2580 if (size == 2) {
2581 size = 1 << size;
2582 align *= 8;
2583 } else {
2584 size = 1 << size;
2585 align *= 4*size;
2586 }
2587 }
2588
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2590 return MCDisassembler::Fail;
2591 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2592 return MCDisassembler::Fail;
2593 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2594 return MCDisassembler::Fail;
2595 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2596 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2597 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2599 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2600 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2601
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2603 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2604 Inst.addOperand(MCOperand::CreateImm(align));
2605
2606 if (Rm == 0xD)
2607 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2608 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2610 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2611 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2612
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2613 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2614}
2615
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2616static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2617DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2618 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2619 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2620
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2621 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2622 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2623 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2624 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2625 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2626 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2627 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2628 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2629
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2630 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2631 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2632 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2633 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2634 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2635 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2636 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2637
2638 Inst.addOperand(MCOperand::CreateImm(imm));
2639
2640 switch (Inst.getOpcode()) {
2641 case ARM::VORRiv4i16:
2642 case ARM::VORRiv2i32:
2643 case ARM::VBICiv4i16:
2644 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2646 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2647 break;
2648 case ARM::VORRiv8i16:
2649 case ARM::VORRiv4i32:
2650 case ARM::VBICiv8i16:
2651 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2652 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2653 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2654 break;
2655 default:
2656 break;
2657 }
2658
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2659 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2660}
2661
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2662static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2663 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2664 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2665
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2666 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2667 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2668 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2669 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2670 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2671
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2672 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2673 return MCDisassembler::Fail;
2674 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2675 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2676 Inst.addOperand(MCOperand::CreateImm(8 << size));
2677
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2678 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2679}
2680
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2681static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682 uint64_t Address, const void *Decoder) {
2683 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2684 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2685}
2686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2687static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2688 uint64_t Address, const void *Decoder) {
2689 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2690 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2691}
2692
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2693static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2694 uint64_t Address, const void *Decoder) {
2695 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2696 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2697}
2698
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2699static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2700 uint64_t Address, const void *Decoder) {
2701 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2702 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2703}
2704
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2705static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2706 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2707 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2708
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2709 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2710 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2711 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2712 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2713 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2714 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2715 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2716 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2717
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2718 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2719 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2720 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2721 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2722 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2723 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2724
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2725 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2726 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2727 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2728 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2729
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2731 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2732
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2733 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2734}
2735
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2736static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2737 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2738 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2739
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2740 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2741 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2742
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2743 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2744 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2745
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2746 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2747 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2748 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2749 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2750 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2751 case ARM::tADDrSPi:
2752 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2753 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2754 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2755
2756 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2757 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2758}
2759
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2760static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2761 uint64_t Address, const void *Decoder) {
2762 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2763 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2764}
2765
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2766static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2767 uint64_t Address, const void *Decoder) {
2768 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2769 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2770}
2771
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2772static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2773 uint64_t Address, const void *Decoder) {
2774 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2775 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2776}
2777
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2778static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2779 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2780 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2781
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2782 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2783 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2784
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2785 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2786 return MCDisassembler::Fail;
2787 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2788 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2789
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2790 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2791}
2792
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2793static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2794 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2795 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2796
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2797 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2798 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2799
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2800 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2801 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2802 Inst.addOperand(MCOperand::CreateImm(imm));
2803
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2804 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2805}
2806
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2807static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2809 unsigned imm = Val << 2;
2810
2811 Inst.addOperand(MCOperand::CreateImm(imm));
2812 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2813
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2814 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2815}
2816
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2817static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2818 uint64_t Address, const void *Decoder) {
2819 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2820 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2821
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2822 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2823}
2824
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2825static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2826 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2827 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2828
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2829 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2830 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2831 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2832
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2834 return MCDisassembler::Fail;
2835 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2836 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2837 Inst.addOperand(MCOperand::CreateImm(imm));
2838
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2839 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2840}
2841
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2842static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2843 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2844 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2845
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2846 switch (Inst.getOpcode()) {
2847 case ARM::t2PLDs:
2848 case ARM::t2PLDWs:
2849 case ARM::t2PLIs:
2850 break;
2851 default: {
2852 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2853 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2854 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2855 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2856 }
2857
2858 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2859 if (Rn == 0xF) {
2860 switch (Inst.getOpcode()) {
2861 case ARM::t2LDRBs:
2862 Inst.setOpcode(ARM::t2LDRBpci);
2863 break;
2864 case ARM::t2LDRHs:
2865 Inst.setOpcode(ARM::t2LDRHpci);
2866 break;
2867 case ARM::t2LDRSHs:
2868 Inst.setOpcode(ARM::t2LDRSHpci);
2869 break;
2870 case ARM::t2LDRSBs:
2871 Inst.setOpcode(ARM::t2LDRSBpci);
2872 break;
2873 case ARM::t2PLDs:
2874 Inst.setOpcode(ARM::t2PLDi12);
2875 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2876 break;
2877 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2878 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2879 }
2880
2881 int imm = fieldFromInstruction32(Insn, 0, 12);
2882 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2883 Inst.addOperand(MCOperand::CreateImm(imm));
2884
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2885 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2886 }
2887
2888 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2889 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2890 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2891 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2892 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2893
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2894 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2895}
2896
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2897static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2898 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2899 int imm = Val & 0xFF;
2900 if (!(Val & 0x100)) imm *= -1;
2901 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2902
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2903 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2904}
2905
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2906static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2907 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2908 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2909
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2910 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2911 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2912
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2914 return MCDisassembler::Fail;
2915 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2916 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2917
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2918 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2919}
2920
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]2921static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2922 uint64_t Address, const void *Decoder) {
2923 DecodeStatus S = MCDisassembler::Success;
2924
2925 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2926 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2927
2928 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2929 return MCDisassembler::Fail;
2930
2931 Inst.addOperand(MCOperand::CreateImm(imm));
2932
2933 return S;
2934}
2935
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2936static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2937 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2938 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]2939 if (Val == 0)
2940 imm = INT32_MIN;
2941 else if (!(Val & 0x100))
2942 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2943 Inst.addOperand(MCOperand::CreateImm(imm));
2944
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2945 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2946}
2947
2948
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2949static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2950 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2951 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2952
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2953 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2954 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2955
2956 // Some instructions always use an additive offset.
2957 switch (Inst.getOpcode()) {
2958 case ARM::t2LDRT:
2959 case ARM::t2LDRBT:
2960 case ARM::t2LDRHT:
2961 case ARM::t2LDRSBT:
2962 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]2963 case ARM::t2STRT:
2964 case ARM::t2STRBT:
2965 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2966 imm |= 0x100;
2967 break;
2968 default:
2969 break;
2970 }
2971
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2973 return MCDisassembler::Fail;
2974 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2975 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2976
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2977 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2978}
2979
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2980static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2981 uint64_t Address, const void *Decoder) {
2982 DecodeStatus S = MCDisassembler::Success;
2983
2984 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2985 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2986 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2987 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2988 addr |= Rn << 9;
2989 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2990
2991 if (!load) {
2992 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2993 return MCDisassembler::Fail;
2994 }
2995
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]2996 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]2997 return MCDisassembler::Fail;
2998
2999 if (load) {
3000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3001 return MCDisassembler::Fail;
3002 }
3003
3004 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3005 return MCDisassembler::Fail;
3006
3007 return S;
3008}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3009
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3010static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3011 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3012 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3013
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3014 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3015 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3016
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3017 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3018 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3019 Inst.addOperand(MCOperand::CreateImm(imm));
3020
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3021 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3022}
3023
3024
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3025static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3026 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3027 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3028
3029 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3030 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3031 Inst.addOperand(MCOperand::CreateImm(imm));
3032
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3033 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3034}
3035
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3036static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3037 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3038 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3039
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3040 if (Inst.getOpcode() == ARM::tADDrSP) {
3041 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3042 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3043
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3045 return MCDisassembler::Fail;
3046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3047 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3048 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3049 } else if (Inst.getOpcode() == ARM::tADDspr) {
3050 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3051
3052 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3053 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3055 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3056 }
3057
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3058 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3059}
3060
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3061static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3062 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3063 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3064 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3065
3066 Inst.addOperand(MCOperand::CreateImm(imod));
3067 Inst.addOperand(MCOperand::CreateImm(flags));
3068
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3069 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3070}
3071
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3072static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3073 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3074 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3075 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3076 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3077
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3079 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3080 Inst.addOperand(MCOperand::CreateImm(add));
3081
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3082 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3083}
3084
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3085static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3086 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3087 if (!tryAddingSymbolicOperand(Address,
3088 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3089 true, 4, Inst, Decoder))
3090 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3091 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3092}
3093
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3094static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3095 uint64_t Address, const void *Decoder) {
3096 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3097 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3098
3099 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3100 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3101}
3102
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3103static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3104DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3105 uint64_t Address, const void *Decoder) {
3106 DecodeStatus S = MCDisassembler::Success;
3107
3108 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3109 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3110
3111 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3113 return MCDisassembler::Fail;
3114 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3115 return MCDisassembler::Fail;
3116 return S;
3117}
3118
3119static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3120DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3121 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3122 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3123
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3124 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3125 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3126 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3127 switch (opc) {
3128 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3129 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3130 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3131 Inst.setOpcode(ARM::t2DSB);
3132 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3133 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3134 Inst.setOpcode(ARM::t2DMB);
3135 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3136 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3137 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3138 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3139 }
3140
3141 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3142 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3143 }
3144
3145 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3146 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3147 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3148 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3149 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3150
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3151 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3152 return MCDisassembler::Fail;
3153 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3154 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3155
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3156 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3157}
3158
3159// Decode a shifted immediate operand. These basically consist
3160// of an 8-bit value, and a 4-bit directive that specifies either
3161// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3162static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3163 uint64_t Address, const void *Decoder) {
3164 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3165 if (ctrl == 0) {
3166 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3167 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3168 switch (byte) {
3169 case 0:
3170 Inst.addOperand(MCOperand::CreateImm(imm));
3171 break;
3172 case 1:
3173 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3174 break;
3175 case 2:
3176 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3177 break;
3178 case 3:
3179 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3180 (imm << 8) | imm));
3181 break;
3182 }
3183 } else {
3184 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3185 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3186 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3187 Inst.addOperand(MCOperand::CreateImm(imm));
3188 }
3189
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3190 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3191}
3192
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3193static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3194DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3195 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3196 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3197 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3198}
3199
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3200static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3201 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3202 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3203 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3204}
3205
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3206static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3207 uint64_t Address, const void *Decoder) {
3208 switch (Val) {
3209 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3210 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3211 case 0xF: // SY
3212 case 0xE: // ST
3213 case 0xB: // ISH
3214 case 0xA: // ISHST
3215 case 0x7: // NSH
3216 case 0x6: // NSHST
3217 case 0x3: // OSH
3218 case 0x2: // OSHST
3219 break;
3220 }
3221
3222 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3223 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3224}
3225
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3226static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3227 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3228 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3229 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3230 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3231}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3232
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3233static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3234 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3235 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3236
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3237 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3238 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3239 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3240
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3241 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3242
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3244 return MCDisassembler::Fail;
3245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3246 return MCDisassembler::Fail;
3247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3248 return MCDisassembler::Fail;
3249 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3250 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3251
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3252 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3253}
3254
3255
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3256static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3257 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3258 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3259
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3260 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3261 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3262 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3263 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3264
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3265 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3266 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3267
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3268 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3269 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3270
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3272 return MCDisassembler::Fail;
3273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3274 return MCDisassembler::Fail;
3275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3276 return MCDisassembler::Fail;
3277 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3278 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3279
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3280 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3281}
3282
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3283static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3284 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3285 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3286
3287 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3288 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3289 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3290 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3291 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3292 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3293
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3294 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3295
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3297 return MCDisassembler::Fail;
3298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3299 return MCDisassembler::Fail;
3300 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3301 return MCDisassembler::Fail;
3302 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3303 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3304
3305 return S;
3306}
3307
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3308static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3309 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3310 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3311
3312 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3313 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3314 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3315 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3316 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3317 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3318 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3319
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3320 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3321 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3322
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3324 return MCDisassembler::Fail;
3325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3326 return MCDisassembler::Fail;
3327 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3328 return MCDisassembler::Fail;
3329 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3330 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3331
3332 return S;
3333}
3334
3335
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3336static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3337 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3338 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3339
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3340 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3341 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3342 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3343 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3344 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3345 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3346
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3347 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3348
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3350 return MCDisassembler::Fail;
3351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3352 return MCDisassembler::Fail;
3353 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3354 return MCDisassembler::Fail;
3355 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3356 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3357
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3358 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3359}
3360
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3361static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3362 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3363 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3364
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3365 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3366 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3367 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3368 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3369 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3370 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3371
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3372 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3373
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3375 return MCDisassembler::Fail;
3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3377 return MCDisassembler::Fail;
3378 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3379 return MCDisassembler::Fail;
3380 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3381 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3382
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3383 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3384}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3385
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3386static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3387 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3388 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3389
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3390 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3391 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3392 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3393 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3394 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3395
3396 unsigned align = 0;
3397 unsigned index = 0;
3398 switch (size) {
3399 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3400 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3401 case 0:
3402 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3403 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3404 index = fieldFromInstruction32(Insn, 5, 3);
3405 break;
3406 case 1:
3407 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3408 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3409 index = fieldFromInstruction32(Insn, 6, 2);
3410 if (fieldFromInstruction32(Insn, 4, 1))
3411 align = 2;
3412 break;
3413 case 2:
3414 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3415 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3416 index = fieldFromInstruction32(Insn, 7, 1);
3417 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3418 align = 4;
3419 }
3420
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3421 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3422 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3423 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3425 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3426 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3428 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3429 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3430 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3431 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3433 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3434 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3435 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3436 }
3437
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3438 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3439 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3440 Inst.addOperand(MCOperand::CreateImm(index));
3441
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3442 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3443}
3444
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3445static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3446 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3447 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3448
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3449 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3450 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3451 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3452 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3453 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3454
3455 unsigned align = 0;
3456 unsigned index = 0;
3457 switch (size) {
3458 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3459 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3460 case 0:
3461 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3462 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3463 index = fieldFromInstruction32(Insn, 5, 3);
3464 break;
3465 case 1:
3466 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3467 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3468 index = fieldFromInstruction32(Insn, 6, 2);
3469 if (fieldFromInstruction32(Insn, 4, 1))
3470 align = 2;
3471 break;
3472 case 2:
3473 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3474 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3475 index = fieldFromInstruction32(Insn, 7, 1);
3476 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3477 align = 4;
3478 }
3479
3480 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3482 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3483 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3485 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3486 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3487 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3488 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3490 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3491 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3492 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3493 }
3494
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3496 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3497 Inst.addOperand(MCOperand::CreateImm(index));
3498
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3499 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3500}
3501
3502
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3503static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3504 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3505 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3506
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3507 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3508 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3509 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3510 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3511 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3512
3513 unsigned align = 0;
3514 unsigned index = 0;
3515 unsigned inc = 1;
3516 switch (size) {
3517 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3518 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3519 case 0:
3520 index = fieldFromInstruction32(Insn, 5, 3);
3521 if (fieldFromInstruction32(Insn, 4, 1))
3522 align = 2;
3523 break;
3524 case 1:
3525 index = fieldFromInstruction32(Insn, 6, 2);
3526 if (fieldFromInstruction32(Insn, 4, 1))
3527 align = 4;
3528 if (fieldFromInstruction32(Insn, 5, 1))
3529 inc = 2;
3530 break;
3531 case 2:
3532 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3533 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3534 index = fieldFromInstruction32(Insn, 7, 1);
3535 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3536 align = 8;
3537 if (fieldFromInstruction32(Insn, 6, 1))
3538 inc = 2;
3539 break;
3540 }
3541
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3542 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3543 return MCDisassembler::Fail;
3544 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3545 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3546 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3548 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3549 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3551 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3552 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3553 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3554 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3556 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3557 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3558 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3559 }
3560
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3561 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3562 return MCDisassembler::Fail;
3563 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3564 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3565 Inst.addOperand(MCOperand::CreateImm(index));
3566
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3567 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3568}
3569
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3570static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3571 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3572 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3573
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3574 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3576 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3577 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3578 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3579
3580 unsigned align = 0;
3581 unsigned index = 0;
3582 unsigned inc = 1;
3583 switch (size) {
3584 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3585 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3586 case 0:
3587 index = fieldFromInstruction32(Insn, 5, 3);
3588 if (fieldFromInstruction32(Insn, 4, 1))
3589 align = 2;
3590 break;
3591 case 1:
3592 index = fieldFromInstruction32(Insn, 6, 2);
3593 if (fieldFromInstruction32(Insn, 4, 1))
3594 align = 4;
3595 if (fieldFromInstruction32(Insn, 5, 1))
3596 inc = 2;
3597 break;
3598 case 2:
3599 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3600 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3601 index = fieldFromInstruction32(Insn, 7, 1);
3602 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3603 align = 8;
3604 if (fieldFromInstruction32(Insn, 6, 1))
3605 inc = 2;
3606 break;
3607 }
3608
3609 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3611 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3612 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3614 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3615 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3616 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3617 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3619 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3620 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3621 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3622 }
3623
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3625 return MCDisassembler::Fail;
3626 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3627 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3628 Inst.addOperand(MCOperand::CreateImm(index));
3629
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3630 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3631}
3632
3633
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3634static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3635 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3636 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3637
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3638 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3639 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3640 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3641 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3642 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3643
3644 unsigned align = 0;
3645 unsigned index = 0;
3646 unsigned inc = 1;
3647 switch (size) {
3648 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3649 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3650 case 0:
3651 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3652 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3653 index = fieldFromInstruction32(Insn, 5, 3);
3654 break;
3655 case 1:
3656 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3657 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3658 index = fieldFromInstruction32(Insn, 6, 2);
3659 if (fieldFromInstruction32(Insn, 5, 1))
3660 inc = 2;
3661 break;
3662 case 2:
3663 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3664 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3665 index = fieldFromInstruction32(Insn, 7, 1);
3666 if (fieldFromInstruction32(Insn, 6, 1))
3667 inc = 2;
3668 break;
3669 }
3670
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3672 return MCDisassembler::Fail;
3673 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3674 return MCDisassembler::Fail;
3675 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3676 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3677
3678 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3680 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3681 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3683 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3684 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3685 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3686 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3688 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3689 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3690 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3691 }
3692
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3693 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3694 return MCDisassembler::Fail;
3695 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3696 return MCDisassembler::Fail;
3697 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3698 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3699 Inst.addOperand(MCOperand::CreateImm(index));
3700
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3701 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3702}
3703
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3704static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3705 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3706 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3707
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3708 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3709 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3710 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3711 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3712 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3713
3714 unsigned align = 0;
3715 unsigned index = 0;
3716 unsigned inc = 1;
3717 switch (size) {
3718 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3719 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3720 case 0:
3721 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3722 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3723 index = fieldFromInstruction32(Insn, 5, 3);
3724 break;
3725 case 1:
3726 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3727 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3728 index = fieldFromInstruction32(Insn, 6, 2);
3729 if (fieldFromInstruction32(Insn, 5, 1))
3730 inc = 2;
3731 break;
3732 case 2:
3733 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3734 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3735 index = fieldFromInstruction32(Insn, 7, 1);
3736 if (fieldFromInstruction32(Insn, 6, 1))
3737 inc = 2;
3738 break;
3739 }
3740
3741 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3743 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3744 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3746 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3747 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3748 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3749 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3751 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3752 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3753 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3754 }
3755
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3756 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3757 return MCDisassembler::Fail;
3758 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3759 return MCDisassembler::Fail;
3760 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3761 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3762 Inst.addOperand(MCOperand::CreateImm(index));
3763
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3764 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3765}
3766
3767
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3768static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3769 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3770 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3771
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3772 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3773 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3774 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3775 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3776 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3777
3778 unsigned align = 0;
3779 unsigned index = 0;
3780 unsigned inc = 1;
3781 switch (size) {
3782 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3783 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3784 case 0:
3785 if (fieldFromInstruction32(Insn, 4, 1))
3786 align = 4;
3787 index = fieldFromInstruction32(Insn, 5, 3);
3788 break;
3789 case 1:
3790 if (fieldFromInstruction32(Insn, 4, 1))
3791 align = 8;
3792 index = fieldFromInstruction32(Insn, 6, 2);
3793 if (fieldFromInstruction32(Insn, 5, 1))
3794 inc = 2;
3795 break;
3796 case 2:
3797 if (fieldFromInstruction32(Insn, 4, 2))
3798 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3799 index = fieldFromInstruction32(Insn, 7, 1);
3800 if (fieldFromInstruction32(Insn, 6, 1))
3801 inc = 2;
3802 break;
3803 }
3804
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3806 return MCDisassembler::Fail;
3807 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3808 return MCDisassembler::Fail;
3809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3810 return MCDisassembler::Fail;
3811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3812 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3813
3814 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3816 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3817 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3819 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3820 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3821 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3822 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3824 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3825 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3826 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3827 }
3828
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3830 return MCDisassembler::Fail;
3831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3832 return MCDisassembler::Fail;
3833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3834 return MCDisassembler::Fail;
3835 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3836 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3837 Inst.addOperand(MCOperand::CreateImm(index));
3838
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3839 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3840}
3841
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3842static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3843 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3844 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3845
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3846 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3847 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3848 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3849 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3850 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3851
3852 unsigned align = 0;
3853 unsigned index = 0;
3854 unsigned inc = 1;
3855 switch (size) {
3856 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3857 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3858 case 0:
3859 if (fieldFromInstruction32(Insn, 4, 1))
3860 align = 4;
3861 index = fieldFromInstruction32(Insn, 5, 3);
3862 break;
3863 case 1:
3864 if (fieldFromInstruction32(Insn, 4, 1))
3865 align = 8;
3866 index = fieldFromInstruction32(Insn, 6, 2);
3867 if (fieldFromInstruction32(Insn, 5, 1))
3868 inc = 2;
3869 break;
3870 case 2:
3871 if (fieldFromInstruction32(Insn, 4, 2))
3872 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3873 index = fieldFromInstruction32(Insn, 7, 1);
3874 if (fieldFromInstruction32(Insn, 6, 1))
3875 inc = 2;
3876 break;
3877 }
3878
3879 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3881 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3882 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3884 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3885 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3886 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3887 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3889 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3890 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3891 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3892 }
3893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3895 return MCDisassembler::Fail;
3896 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3897 return MCDisassembler::Fail;
3898 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3899 return MCDisassembler::Fail;
3900 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3901 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3902 Inst.addOperand(MCOperand::CreateImm(index));
3903
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3904 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3905}
3906
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3907static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3908 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3909 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3910 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3911 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3912 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3913 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3914 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3915
3916 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3917 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3918
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3919 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3920 return MCDisassembler::Fail;
3921 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3922 return MCDisassembler::Fail;
3923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3924 return MCDisassembler::Fail;
3925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3926 return MCDisassembler::Fail;
3927 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3928 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3929
3930 return S;
3931}
3932
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3933static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3934 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3935 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3936 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3937 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3938 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3939 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3940 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3941
3942 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3943 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3944
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3946 return MCDisassembler::Fail;
3947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3948 return MCDisassembler::Fail;
3949 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3950 return MCDisassembler::Fail;
3951 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3952 return MCDisassembler::Fail;
3953 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3954 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3955
3956 return S;
3957}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3959static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3960 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3961 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3962 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3963 // The InstPrinter needs to have the low bit of the predicate in
3964 // the mask operand to be able to print it properly.
3965 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3966
3967 if (pred == 0xF) {
3968 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3969 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3970 }
3971
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3972 if ((mask & 0xF) == 0) {
3973 // Preserve the high bit of the mask, which is the low bit of
3974 // the predicate.
3975 mask &= 0x10;
3976 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3977 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3978 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3979
3980 Inst.addOperand(MCOperand::CreateImm(pred));
3981 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3982 return S;
3983}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]3984
3985static DecodeStatus
3986DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3987 uint64_t Address, const void *Decoder) {
3988 DecodeStatus S = MCDisassembler::Success;
3989
3990 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3991 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3992 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3993 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3994 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3995 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3996 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3997 bool writeback = (W == 1) | (P == 0);
3998
3999 addr |= (U << 8) | (Rn << 9);
4000
4001 if (writeback && (Rn == Rt || Rn == Rt2))
4002 Check(S, MCDisassembler::SoftFail);
4003 if (Rt == Rt2)
4004 Check(S, MCDisassembler::SoftFail);
4005
4006 // Rt
4007 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4008 return MCDisassembler::Fail;
4009 // Rt2
4010 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4011 return MCDisassembler::Fail;
4012 // Writeback operand
4013 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4014 return MCDisassembler::Fail;
4015 // addr
4016 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4017 return MCDisassembler::Fail;
4018
4019 return S;
4020}
4021
4022static DecodeStatus
4023DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4024 uint64_t Address, const void *Decoder) {
4025 DecodeStatus S = MCDisassembler::Success;
4026
4027 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4028 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4029 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4030 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4031 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4032 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4033 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4034 bool writeback = (W == 1) | (P == 0);
4035
4036 addr |= (U << 8) | (Rn << 9);
4037
4038 if (writeback && (Rn == Rt || Rn == Rt2))
4039 Check(S, MCDisassembler::SoftFail);
4040
4041 // Writeback operand
4042 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4043 return MCDisassembler::Fail;
4044 // Rt
4045 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4046 return MCDisassembler::Fail;
4047 // Rt2
4048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4049 return MCDisassembler::Fail;
4050 // addr
4051 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4052 return MCDisassembler::Fail;
4053
4054 return S;
4055}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4056
4057static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4058 uint64_t Address, const void *Decoder) {
4059 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4060 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4061 if (sign1 != sign2) return MCDisassembler::Fail;
4062
4063 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4064 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4065 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4066 Val |= sign1 << 12;
4067 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4068
4069 return MCDisassembler::Success;
4070}
4071
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4072static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4073 uint64_t Address,
4074 const void *Decoder) {
4075 DecodeStatus S = MCDisassembler::Success;
4076
4077 // Shift of "asr #32" is not allowed in Thumb2 mode.
4078 if (Val == 0x20) S = MCDisassembler::SoftFail;
4079 Inst.addOperand(MCOperand::CreateImm(Val));
4080 return S;
4081}
4082